1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 MA 02111-1307, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
432 /* Parsing and Idiom Translation. */
434 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
436 /* Various Other Internal Functions. */
438 static void xtensa_mark_literal_pool_location (void);
439 static addressT
get_expanded_loop_offset (xtensa_opcode
);
440 static fragS
*get_literal_pool_location (segT
);
441 static void set_literal_pool_location (segT
, fragS
*);
442 static void xtensa_set_frag_assembly_state (fragS
*);
443 static void finish_vinsn (vliw_insn
*);
444 static bfd_boolean
emit_single_op (TInsn
*);
445 static int total_frag_text_expansion (fragS
*);
447 /* Alignment Functions. */
449 static int get_text_align_power (unsigned);
450 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
452 /* Helpers for xtensa_relax_frag(). */
454 static long relax_frag_add_nop (fragS
*);
456 /* Accessors for additional per-subsegment information. */
458 static unsigned get_last_insn_flags (segT
, subsegT
);
459 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
460 static float get_subseg_total_freq (segT
, subsegT
);
461 static float get_subseg_target_freq (segT
, subsegT
);
462 static void set_subseg_freq (segT
, subsegT
, float, float);
464 /* Segment list functions. */
466 static void xtensa_move_literals (void);
467 static void xtensa_reorder_segments (void);
468 static void xtensa_switch_to_literal_fragment (emit_state
*);
469 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
470 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
471 static void xtensa_restore_emit_state (emit_state
*);
472 static void cache_literal_section
473 (seg_list
*, const char *, segT
*, bfd_boolean
);
475 /* Import from elf32-xtensa.c in BFD library. */
477 extern char *xtensa_get_property_section_name (asection
*, const char *);
479 /* op_placement_info functions. */
481 static void init_op_placement_info_table (void);
482 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
483 static int xg_get_single_size (xtensa_opcode
);
484 static xtensa_format
xg_get_single_format (xtensa_opcode
);
486 /* TInsn and IStack functions. */
488 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
489 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
490 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
491 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
492 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
493 static void tinsn_from_chars (TInsn
*, char *, int);
494 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
495 static int get_num_stack_text_bytes (IStack
*);
496 static int get_num_stack_literal_bytes (IStack
*);
498 /* vliw_insn functions. */
500 static void xg_init_vinsn (vliw_insn
*);
501 static void xg_clear_vinsn (vliw_insn
*);
502 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
503 static void xg_free_vinsn (vliw_insn
*);
504 static bfd_boolean vinsn_to_insnbuf
505 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
506 static void vinsn_from_chars (vliw_insn
*, char *);
508 /* Expression Utilities. */
510 bfd_boolean
expr_is_const (const expressionS
*);
511 offsetT
get_expr_const (const expressionS
*);
512 void set_expr_const (expressionS
*, offsetT
);
513 bfd_boolean
expr_is_register (const expressionS
*);
514 offsetT
get_expr_register (const expressionS
*);
515 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
516 static void set_expr_symbol_offset_diff
517 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
518 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
519 static void copy_expr (expressionS
*, const expressionS
*);
521 /* Section renaming. */
523 static void build_section_rename (const char *);
526 /* ISA imported from bfd. */
527 extern xtensa_isa xtensa_default_isa
;
529 extern int target_big_endian
;
531 static xtensa_opcode xtensa_addi_opcode
;
532 static xtensa_opcode xtensa_addmi_opcode
;
533 static xtensa_opcode xtensa_call0_opcode
;
534 static xtensa_opcode xtensa_call4_opcode
;
535 static xtensa_opcode xtensa_call8_opcode
;
536 static xtensa_opcode xtensa_call12_opcode
;
537 static xtensa_opcode xtensa_callx0_opcode
;
538 static xtensa_opcode xtensa_callx4_opcode
;
539 static xtensa_opcode xtensa_callx8_opcode
;
540 static xtensa_opcode xtensa_callx12_opcode
;
541 static xtensa_opcode xtensa_const16_opcode
;
542 static xtensa_opcode xtensa_entry_opcode
;
543 static xtensa_opcode xtensa_movi_opcode
;
544 static xtensa_opcode xtensa_movi_n_opcode
;
545 static xtensa_opcode xtensa_isync_opcode
;
546 static xtensa_opcode xtensa_jx_opcode
;
547 static xtensa_opcode xtensa_l32r_opcode
;
548 static xtensa_opcode xtensa_loop_opcode
;
549 static xtensa_opcode xtensa_loopnez_opcode
;
550 static xtensa_opcode xtensa_loopgtz_opcode
;
551 static xtensa_opcode xtensa_nop_opcode
;
552 static xtensa_opcode xtensa_nop_n_opcode
;
553 static xtensa_opcode xtensa_or_opcode
;
554 static xtensa_opcode xtensa_ret_opcode
;
555 static xtensa_opcode xtensa_ret_n_opcode
;
556 static xtensa_opcode xtensa_retw_opcode
;
557 static xtensa_opcode xtensa_retw_n_opcode
;
558 static xtensa_opcode xtensa_rsr_lcount_opcode
;
559 static xtensa_opcode xtensa_waiti_opcode
;
562 /* Command-line Options. */
564 bfd_boolean use_literal_section
= TRUE
;
565 static bfd_boolean align_targets
= TRUE
;
566 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
567 static bfd_boolean has_a0_b_retw
= FALSE
;
568 static bfd_boolean workaround_a0_b_retw
= FALSE
;
569 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
570 static bfd_boolean workaround_short_loop
= FALSE
;
571 static bfd_boolean maybe_has_short_loop
= FALSE
;
572 static bfd_boolean workaround_close_loop_end
= FALSE
;
573 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
575 /* When workaround_short_loops is TRUE, all loops with early exits must
576 have at least 3 instructions. workaround_all_short_loops is a modifier
577 to the workaround_short_loop flag. In addition to the
578 workaround_short_loop actions, all straightline loopgtz and loopnez
579 must have at least 3 instructions. */
581 static bfd_boolean workaround_all_short_loops
= FALSE
;
585 xtensa_setup_hw_workarounds (int earliest
, int latest
)
587 if (earliest
> latest
)
588 as_fatal (_("illegal range of target hardware versions"));
590 /* Enable all workarounds for pre-T1050.0 hardware. */
591 if (earliest
< 105000 || latest
< 105000)
593 workaround_a0_b_retw
|= TRUE
;
594 workaround_b_j_loop_end
|= TRUE
;
595 workaround_short_loop
|= TRUE
;
596 workaround_close_loop_end
|= TRUE
;
597 workaround_all_short_loops
|= TRUE
;
604 option_density
= OPTION_MD_BASE
,
611 option_no_link_relax
,
619 option_text_section_literals
,
620 option_no_text_section_literals
,
622 option_absolute_literals
,
623 option_no_absolute_literals
,
625 option_align_targets
,
626 option_no_align_targets
,
628 option_warn_unaligned_targets
,
633 option_workaround_a0_b_retw
,
634 option_no_workaround_a0_b_retw
,
636 option_workaround_b_j_loop_end
,
637 option_no_workaround_b_j_loop_end
,
639 option_workaround_short_loop
,
640 option_no_workaround_short_loop
,
642 option_workaround_all_short_loops
,
643 option_no_workaround_all_short_loops
,
645 option_workaround_close_loop_end
,
646 option_no_workaround_close_loop_end
,
648 option_no_workarounds
,
650 option_rename_section_name
,
653 option_prefer_const16
,
655 option_target_hardware
658 const char *md_shortopts
= "";
660 struct option md_longopts
[] =
662 { "density", no_argument
, NULL
, option_density
},
663 { "no-density", no_argument
, NULL
, option_no_density
},
665 /* Both "relax" and "generics" are deprecated and treated as equivalent
666 to the "transform" option. */
667 { "relax", no_argument
, NULL
, option_relax
},
668 { "no-relax", no_argument
, NULL
, option_no_relax
},
669 { "generics", no_argument
, NULL
, option_generics
},
670 { "no-generics", no_argument
, NULL
, option_no_generics
},
672 { "transform", no_argument
, NULL
, option_transform
},
673 { "no-transform", no_argument
, NULL
, option_no_transform
},
674 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
675 { "no-text-section-literals", no_argument
, NULL
,
676 option_no_text_section_literals
},
677 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
678 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
679 /* This option was changed from -align-target to -target-align
680 because it conflicted with the "-al" option. */
681 { "target-align", no_argument
, NULL
, option_align_targets
},
682 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
683 { "warn-unaligned-targets", no_argument
, NULL
,
684 option_warn_unaligned_targets
},
685 { "longcalls", no_argument
, NULL
, option_longcalls
},
686 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
688 { "no-workaround-a0-b-retw", no_argument
, NULL
,
689 option_no_workaround_a0_b_retw
},
690 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
692 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
693 option_no_workaround_b_j_loop_end
},
694 { "workaround-b-j-loop-end", no_argument
, NULL
,
695 option_workaround_b_j_loop_end
},
697 { "no-workaround-short-loops", no_argument
, NULL
,
698 option_no_workaround_short_loop
},
699 { "workaround-short-loops", no_argument
, NULL
,
700 option_workaround_short_loop
},
702 { "no-workaround-all-short-loops", no_argument
, NULL
,
703 option_no_workaround_all_short_loops
},
704 { "workaround-all-short-loop", no_argument
, NULL
,
705 option_workaround_all_short_loops
},
707 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
708 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
710 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
712 { "no-workaround-close-loop-end", no_argument
, NULL
,
713 option_no_workaround_close_loop_end
},
714 { "workaround-close-loop-end", no_argument
, NULL
,
715 option_workaround_close_loop_end
},
717 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
719 { "link-relax", no_argument
, NULL
, option_link_relax
},
720 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
722 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
724 { NULL
, no_argument
, NULL
, 0 }
727 size_t md_longopts_size
= sizeof md_longopts
;
731 md_parse_option (int c
, char *arg
)
736 as_warn (_("--density option is ignored"));
738 case option_no_density
:
739 as_warn (_("--no-density option is ignored"));
741 case option_link_relax
:
744 case option_no_link_relax
:
747 case option_generics
:
748 as_warn (_("--generics is deprecated; use --transform instead"));
749 return md_parse_option (option_transform
, arg
);
750 case option_no_generics
:
751 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
752 return md_parse_option (option_no_transform
, arg
);
754 as_warn (_("--relax is deprecated; use --transform instead"));
755 return md_parse_option (option_transform
, arg
);
756 case option_no_relax
:
757 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
758 return md_parse_option (option_no_transform
, arg
);
759 case option_longcalls
:
760 directive_state
[directive_longcalls
] = TRUE
;
762 case option_no_longcalls
:
763 directive_state
[directive_longcalls
] = FALSE
;
765 case option_text_section_literals
:
766 use_literal_section
= FALSE
;
768 case option_no_text_section_literals
:
769 use_literal_section
= TRUE
;
771 case option_absolute_literals
:
772 if (!absolute_literals_supported
)
774 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
777 directive_state
[directive_absolute_literals
] = TRUE
;
779 case option_no_absolute_literals
:
780 directive_state
[directive_absolute_literals
] = FALSE
;
783 case option_workaround_a0_b_retw
:
784 workaround_a0_b_retw
= TRUE
;
786 case option_no_workaround_a0_b_retw
:
787 workaround_a0_b_retw
= FALSE
;
789 case option_workaround_b_j_loop_end
:
790 workaround_b_j_loop_end
= TRUE
;
792 case option_no_workaround_b_j_loop_end
:
793 workaround_b_j_loop_end
= FALSE
;
796 case option_workaround_short_loop
:
797 workaround_short_loop
= TRUE
;
799 case option_no_workaround_short_loop
:
800 workaround_short_loop
= FALSE
;
803 case option_workaround_all_short_loops
:
804 workaround_all_short_loops
= TRUE
;
806 case option_no_workaround_all_short_loops
:
807 workaround_all_short_loops
= FALSE
;
810 case option_workaround_close_loop_end
:
811 workaround_close_loop_end
= TRUE
;
813 case option_no_workaround_close_loop_end
:
814 workaround_close_loop_end
= FALSE
;
817 case option_no_workarounds
:
818 workaround_a0_b_retw
= FALSE
;
819 workaround_b_j_loop_end
= FALSE
;
820 workaround_short_loop
= FALSE
;
821 workaround_all_short_loops
= FALSE
;
822 workaround_close_loop_end
= FALSE
;
825 case option_align_targets
:
826 align_targets
= TRUE
;
828 case option_no_align_targets
:
829 align_targets
= FALSE
;
832 case option_warn_unaligned_targets
:
833 warn_unaligned_branch_targets
= TRUE
;
836 case option_rename_section_name
:
837 build_section_rename (arg
);
841 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
842 should be emitted or not. FIXME: Not implemented. */
845 case option_prefer_l32r
:
847 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
851 case option_prefer_const16
:
853 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
857 case option_target_hardware
:
859 int earliest
, latest
= 0;
860 if (*arg
== 0 || *arg
== '-')
861 as_fatal (_("invalid target hardware version"));
863 earliest
= strtol (arg
, &arg
, 0);
867 else if (*arg
== '-')
870 as_fatal (_("invalid target hardware version"));
871 latest
= strtol (arg
, &arg
, 0);
874 as_fatal (_("invalid target hardware version"));
876 xtensa_setup_hw_workarounds (earliest
, latest
);
880 case option_transform
:
881 /* This option has no affect other than to use the defaults,
882 which are already set. */
885 case option_no_transform
:
886 /* This option turns off all transformations of any kind.
887 However, because we want to preserve the state of other
888 directives, we only change its own field. Thus, before
889 you perform any transformation, always check if transform
890 is available. If you use the functions we provide for this
891 purpose, you will be ok. */
892 directive_state
[directive_transform
] = FALSE
;
902 md_show_usage (FILE *stream
)
906 --[no-]text-section-literals\n\
907 [Do not] put literals in the text section\n\
908 --[no-]absolute-literals\n\
909 [Do not] default to use non-PC-relative literals\n\
910 --[no-]target-align [Do not] try to align branch targets\n\
911 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
912 --[no-]transform [Do not] transform instructions\n\
913 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
917 /* Functions related to the list of current label symbols. */
920 xtensa_add_insn_label (symbolS
*sym
)
924 if (!free_insn_labels
)
925 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
928 l
= free_insn_labels
;
929 free_insn_labels
= l
->next
;
933 l
->next
= insn_labels
;
939 xtensa_clear_insn_labels (void)
943 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
950 /* The "loops_ok" argument is provided to allow ignoring labels that
951 define loop ends. This fixes a bug where the NOPs to align a
952 loop opcode were included in a previous zero-cost loop:
971 This argument is used to prevent moving the NOP to before the
972 loop-end label, which is what you want in this special case. */
975 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
979 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
981 symbolS
*lit_sym
= lit
->sym
;
982 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
984 S_SET_VALUE (lit_sym
, new_offset
);
985 symbol_set_frag (lit_sym
, new_frag
);
991 /* Directive data and functions. */
993 typedef struct state_stackS_struct
995 directiveE directive
;
997 bfd_boolean old_state
;
1001 struct state_stackS_struct
*prev
;
1004 state_stackS
*directive_state_stack
;
1006 const pseudo_typeS md_pseudo_table
[] =
1008 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1009 { "literal_position", xtensa_literal_position
, 0 },
1010 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1011 { "long", xtensa_elf_cons
, 4 },
1012 { "word", xtensa_elf_cons
, 4 },
1013 { "short", xtensa_elf_cons
, 2 },
1014 { "begin", xtensa_begin_directive
, 0 },
1015 { "end", xtensa_end_directive
, 0 },
1016 { "loc", xtensa_dwarf2_directive_loc
, 0 },
1017 { "literal", xtensa_literal_pseudo
, 0 },
1018 { "frequency", xtensa_frequency_pseudo
, 0 },
1024 use_transform (void)
1026 /* After md_end, you should be checking frag by frag, rather
1027 than state directives. */
1028 assert (!past_xtensa_end
);
1029 return directive_state
[directive_transform
];
1034 do_align_targets (void)
1036 /* Do not use this function after md_end; just look at align_targets
1037 instead. There is no target-align directive, so alignment is either
1038 enabled for all frags or not done at all. */
1039 assert (!past_xtensa_end
);
1040 return align_targets
&& use_transform ();
1045 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1049 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1051 as_where (&file
, &line
);
1053 stack
->directive
= directive
;
1054 stack
->negated
= negated
;
1055 stack
->old_state
= directive_state
[directive
];
1058 stack
->datum
= datum
;
1059 stack
->prev
= directive_state_stack
;
1060 directive_state_stack
= stack
;
1062 directive_state
[directive
] = !negated
;
1067 directive_pop (directiveE
*directive
,
1068 bfd_boolean
*negated
,
1073 state_stackS
*top
= directive_state_stack
;
1075 if (!directive_state_stack
)
1077 as_bad (_("unmatched end directive"));
1078 *directive
= directive_none
;
1082 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1083 *directive
= top
->directive
;
1084 *negated
= top
->negated
;
1087 *datum
= top
->datum
;
1088 directive_state_stack
= top
->prev
;
1094 directive_balance (void)
1096 while (directive_state_stack
)
1098 directiveE directive
;
1099 bfd_boolean negated
;
1104 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1105 as_warn_where ((char *) file
, line
,
1106 _(".begin directive with no matching .end directive"));
1112 inside_directive (directiveE dir
)
1114 state_stackS
*top
= directive_state_stack
;
1116 while (top
&& top
->directive
!= dir
)
1119 return (top
!= NULL
);
1124 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1128 char *directive_string
;
1130 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1135 input_line_pointer
+= 3;
1138 len
= strspn (input_line_pointer
,
1139 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1141 /* This code is a hack to make .begin [no-][generics|relax] exactly
1142 equivalent to .begin [no-]transform. We should remove it when
1143 we stop accepting those options. */
1145 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1147 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1148 directive_string
= "transform";
1150 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1152 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1153 directive_string
= "transform";
1156 directive_string
= input_line_pointer
;
1158 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1160 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1162 input_line_pointer
+= len
;
1163 *directive
= (directiveE
) i
;
1164 if (*negated
&& !directive_info
[i
].can_be_negated
)
1165 as_bad (_("directive %s cannot be negated"),
1166 directive_info
[i
].name
);
1171 as_bad (_("unknown directive"));
1172 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1177 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1179 directiveE directive
;
1180 bfd_boolean negated
;
1185 get_directive (&directive
, &negated
);
1186 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1188 discard_rest_of_line ();
1192 if (cur_vinsn
.inside_bundle
)
1193 as_bad (_("directives are not valid inside bundles"));
1197 case directive_literal
:
1198 if (!inside_directive (directive_literal
))
1200 /* Previous labels go with whatever follows this directive, not with
1201 the literal, so save them now. */
1202 saved_insn_labels
= insn_labels
;
1205 as_warn (_(".begin literal is deprecated; use .literal instead"));
1206 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1207 xtensa_switch_to_literal_fragment (state
);
1208 directive_push (directive_literal
, negated
, state
);
1211 case directive_literal_prefix
:
1212 /* Have to flush pending output because a movi relaxed to an l32r
1213 might produce a literal. */
1214 md_flush_pending_output ();
1215 /* Check to see if the current fragment is a literal
1216 fragment. If it is, then this operation is not allowed. */
1217 if (generating_literals
)
1219 as_bad (_("cannot set literal_prefix inside literal fragment"));
1223 /* Allocate the literal state for this section and push
1224 onto the directive stack. */
1225 ls
= xmalloc (sizeof (lit_state
));
1228 *ls
= default_lit_sections
;
1230 directive_push (directive_literal_prefix
, negated
, ls
);
1232 /* Parse the new prefix from the input_line_pointer. */
1234 len
= strspn (input_line_pointer
,
1235 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1236 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1238 /* Process the new prefix. */
1239 xtensa_literal_prefix (input_line_pointer
, len
);
1241 /* Skip the name in the input line. */
1242 input_line_pointer
+= len
;
1245 case directive_freeregs
:
1246 /* This information is currently unused, but we'll accept the statement
1247 and just discard the rest of the line. This won't check the syntax,
1248 but it will accept every correct freeregs directive. */
1249 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1250 directive_push (directive_freeregs
, negated
, 0);
1253 case directive_schedule
:
1254 md_flush_pending_output ();
1255 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1256 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1257 directive_push (directive_schedule
, negated
, 0);
1258 xtensa_set_frag_assembly_state (frag_now
);
1261 case directive_density
:
1262 as_warn (_(".begin [no-]density is ignored"));
1265 case directive_absolute_literals
:
1266 md_flush_pending_output ();
1267 if (!absolute_literals_supported
&& !negated
)
1269 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1272 xtensa_set_frag_assembly_state (frag_now
);
1273 directive_push (directive
, negated
, 0);
1277 md_flush_pending_output ();
1278 xtensa_set_frag_assembly_state (frag_now
);
1279 directive_push (directive
, negated
, 0);
1283 demand_empty_rest_of_line ();
1288 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1290 directiveE begin_directive
, end_directive
;
1291 bfd_boolean begin_negated
, end_negated
;
1295 emit_state
**state_ptr
;
1298 if (cur_vinsn
.inside_bundle
)
1299 as_bad (_("directives are not valid inside bundles"));
1301 get_directive (&end_directive
, &end_negated
);
1303 md_flush_pending_output ();
1305 switch (end_directive
)
1307 case (directiveE
) XTENSA_UNDEFINED
:
1308 discard_rest_of_line ();
1311 case directive_density
:
1312 as_warn (_(".end [no-]density is ignored"));
1313 demand_empty_rest_of_line ();
1316 case directive_absolute_literals
:
1317 if (!absolute_literals_supported
&& !end_negated
)
1319 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1320 demand_empty_rest_of_line ();
1329 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1330 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1331 (const void **) state_ptr
);
1333 if (begin_directive
!= directive_none
)
1335 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1337 as_bad (_("does not match begin %s%s at %s:%d"),
1338 begin_negated
? "no-" : "",
1339 directive_info
[begin_directive
].name
, file
, line
);
1343 switch (end_directive
)
1345 case directive_literal
:
1346 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1347 xtensa_restore_emit_state (state
);
1348 xtensa_set_frag_assembly_state (frag_now
);
1350 if (!inside_directive (directive_literal
))
1352 /* Restore the list of current labels. */
1353 xtensa_clear_insn_labels ();
1354 insn_labels
= saved_insn_labels
;
1358 case directive_literal_prefix
:
1359 /* Restore the default collection sections from saved state. */
1360 s
= (lit_state
*) state
;
1363 if (use_literal_section
)
1364 default_lit_sections
= *s
;
1366 /* free the state storage */
1370 case directive_schedule
:
1371 case directive_freeregs
:
1375 xtensa_set_frag_assembly_state (frag_now
);
1381 demand_empty_rest_of_line ();
1385 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1387 static bfd_boolean xtensa_loc_directive_seen
= FALSE
;
1390 xtensa_dwarf2_directive_loc (int x
)
1392 xtensa_loc_directive_seen
= TRUE
;
1393 dwarf2_directive_loc (x
);
1398 xtensa_dwarf2_emit_insn (int size
, struct dwarf2_line_info
*loc
)
1400 if (debug_type
!= DEBUG_DWARF2
&& ! xtensa_loc_directive_seen
)
1402 xtensa_loc_directive_seen
= FALSE
;
1403 dwarf2_gen_line_info (frag_now_fix () - size
, loc
);
1407 /* Place an aligned literal fragment at the current location. */
1410 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1412 md_flush_pending_output ();
1414 if (inside_directive (directive_literal
))
1415 as_warn (_(".literal_position inside literal directive; ignoring"));
1416 xtensa_mark_literal_pool_location ();
1418 demand_empty_rest_of_line ();
1419 xtensa_clear_insn_labels ();
1423 /* Support .literal label, expr, ... */
1426 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1429 char *p
, *base_name
;
1433 if (inside_directive (directive_literal
))
1435 as_bad (_(".literal not allowed inside .begin literal region"));
1436 ignore_rest_of_line ();
1440 md_flush_pending_output ();
1442 /* Previous labels go with whatever follows this directive, not with
1443 the literal, so save them now. */
1444 saved_insn_labels
= insn_labels
;
1447 /* If we are using text-section literals, then this is the right value... */
1450 base_name
= input_line_pointer
;
1452 xtensa_switch_to_literal_fragment (&state
);
1454 /* ...but if we aren't using text-section-literals, then we
1455 need to put them in the section we just switched to. */
1456 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1459 /* All literals are aligned to four-byte boundaries. */
1460 frag_align (2, 0, 0);
1461 record_alignment (now_seg
, 2);
1463 c
= get_symbol_end ();
1464 /* Just after name is now '\0'. */
1465 p
= input_line_pointer
;
1469 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1471 as_bad (_("expected comma or colon after symbol name; "
1472 "rest of line ignored"));
1473 ignore_rest_of_line ();
1474 xtensa_restore_emit_state (&state
);
1482 input_line_pointer
++; /* skip ',' or ':' */
1484 xtensa_elf_cons (4);
1486 xtensa_restore_emit_state (&state
);
1488 /* Restore the list of current labels. */
1489 xtensa_clear_insn_labels ();
1490 insn_labels
= saved_insn_labels
;
1495 xtensa_literal_prefix (char const *start
, int len
)
1497 char *name
, *linkonce_suffix
;
1498 char *newname
, *newname4
;
1499 size_t linkonce_len
;
1501 /* Get a null-terminated copy of the name. */
1502 name
= xmalloc (len
+ 1);
1505 strncpy (name
, start
, len
);
1508 /* Allocate the sections (interesting note: the memory pointing to
1509 the name is actually used for the name by the new section). */
1511 newname
= xmalloc (len
+ strlen (".literal") + 1);
1512 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1514 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1515 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1516 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1518 strcpy (newname
, ".gnu.linkonce.literal");
1519 strcpy (newname4
, ".gnu.linkonce.lit4");
1521 strcat (newname
, linkonce_suffix
);
1522 strcat (newname4
, linkonce_suffix
);
1526 int suffix_pos
= len
;
1528 /* If the section name ends with ".text", then replace that suffix
1529 instead of appending an additional suffix. */
1530 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1533 strcpy (newname
, name
);
1534 strcpy (newname4
, name
);
1536 strcpy (newname
+ suffix_pos
, ".literal");
1537 strcpy (newname4
+ suffix_pos
, ".lit4");
1540 /* Note that cache_literal_section does not create a segment if
1541 it already exists. */
1542 default_lit_sections
.lit_seg
= NULL
;
1543 default_lit_sections
.lit4_seg
= NULL
;
1545 /* Canonicalizing section names allows renaming literal
1546 sections to occur correctly. */
1547 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1548 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1554 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1557 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1559 float fall_through_f
, target_f
;
1561 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1562 if (fall_through_f
< 0)
1564 as_bad (_("fall through frequency must be greater than 0"));
1565 ignore_rest_of_line ();
1569 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1572 as_bad (_("branch target frequency must be greater than 0"));
1573 ignore_rest_of_line ();
1577 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1579 demand_empty_rest_of_line ();
1583 /* Like normal .long/.short/.word, except support @plt, etc.
1584 Clobbers input_line_pointer, checks end-of-line. */
1587 xtensa_elf_cons (int nbytes
)
1590 bfd_reloc_code_real_type reloc
;
1592 md_flush_pending_output ();
1594 if (cur_vinsn
.inside_bundle
)
1595 as_bad (_("directives are not valid inside bundles"));
1597 if (is_it_end_of_statement ())
1599 demand_empty_rest_of_line ();
1606 if (exp
.X_op
== O_symbol
1607 && *input_line_pointer
== '@'
1608 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1611 reloc_howto_type
*reloc_howto
=
1612 bfd_reloc_type_lookup (stdoutput
, reloc
);
1614 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1615 as_bad (_("unsupported relocation"));
1616 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1617 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1618 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1619 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1620 as_bad (_("opcode-specific %s relocation used outside "
1621 "an instruction"), reloc_howto
->name
);
1622 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1623 as_bad (_("%s relocations do not fit in %d bytes"),
1624 reloc_howto
->name
, nbytes
);
1627 char *p
= frag_more ((int) nbytes
);
1628 xtensa_set_frag_assembly_state (frag_now
);
1629 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1630 nbytes
, &exp
, 0, reloc
);
1634 emit_expr (&exp
, (unsigned int) nbytes
);
1636 while (*input_line_pointer
++ == ',');
1638 input_line_pointer
--; /* Put terminator back into stream. */
1639 demand_empty_rest_of_line ();
1643 /* Parsing and Idiom Translation. */
1645 /* Parse @plt, etc. and return the desired relocation. */
1646 static bfd_reloc_code_real_type
1647 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1653 bfd_reloc_code_real_type reloc
;
1661 struct map_bfd
*ptr
;
1663 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1665 static struct map_bfd mapping
[] =
1667 MAP ("l", BFD_RELOC_LO16
),
1668 MAP ("h", BFD_RELOC_HI16
),
1669 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1670 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1674 return BFD_RELOC_NONE
;
1676 for (ch
= *str
, str2
= ident
;
1677 (str2
< ident
+ sizeof (ident
) - 1
1678 && (ISALNUM (ch
) || ch
== '@'));
1681 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1688 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1689 if (ch
== ptr
->string
[0]
1690 && len
== ptr
->length
1691 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1693 /* Now check for "identifier@suffix+constant". */
1694 if (*str
== '-' || *str
== '+')
1696 char *orig_line
= input_line_pointer
;
1697 expressionS new_exp
;
1699 input_line_pointer
= str
;
1700 expression (&new_exp
);
1701 if (new_exp
.X_op
== O_constant
)
1703 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1704 str
= input_line_pointer
;
1707 if (&input_line_pointer
!= str_p
)
1708 input_line_pointer
= orig_line
;
1715 return BFD_RELOC_UNUSED
;
1720 expression_end (const char *name
)
1743 #define ERROR_REG_NUM ((unsigned) -1)
1746 tc_get_register (const char *prefix
)
1749 const char *next_expr
;
1750 const char *old_line_pointer
;
1753 old_line_pointer
= input_line_pointer
;
1755 if (*input_line_pointer
== '$')
1756 ++input_line_pointer
;
1758 /* Accept "sp" as a synonym for "a1". */
1759 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1760 && expression_end (input_line_pointer
+ 2))
1762 input_line_pointer
+= 2;
1763 return 1; /* AR[1] */
1766 while (*input_line_pointer
++ == *prefix
++)
1768 --input_line_pointer
;
1773 as_bad (_("bad register name: %s"), old_line_pointer
);
1774 return ERROR_REG_NUM
;
1777 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1779 as_bad (_("bad register number: %s"), input_line_pointer
);
1780 return ERROR_REG_NUM
;
1785 while (ISDIGIT ((int) *input_line_pointer
))
1786 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1788 if (!(next_expr
= expression_end (input_line_pointer
)))
1790 as_bad (_("bad register name: %s"), old_line_pointer
);
1791 return ERROR_REG_NUM
;
1794 input_line_pointer
= (char *) next_expr
;
1801 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1803 xtensa_isa isa
= xtensa_default_isa
;
1805 /* Check if this is an immediate operand. */
1806 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1808 bfd_reloc_code_real_type reloc
;
1809 segT t
= expression (tok
);
1810 if (t
== absolute_section
1811 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1813 assert (tok
->X_op
== O_constant
);
1814 tok
->X_op
= O_symbol
;
1815 tok
->X_add_symbol
= &abs_symbol
;
1818 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1819 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1820 && (reloc
!= BFD_RELOC_NONE
))
1825 case BFD_RELOC_UNUSED
:
1826 as_bad (_("unsupported relocation"));
1829 case BFD_RELOC_XTENSA_PLT
:
1830 tok
->X_op
= O_pltrel
;
1833 case BFD_RELOC_LO16
:
1834 if (tok
->X_op
== O_constant
)
1835 tok
->X_add_number
&= 0xffff;
1840 case BFD_RELOC_HI16
:
1841 if (tok
->X_op
== O_constant
)
1842 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1851 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1852 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1854 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1857 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1858 as_bad (_("register number out of range"));
1861 tok
->X_op
= O_register
;
1862 tok
->X_add_symbol
= 0;
1863 tok
->X_add_number
= reg
;
1868 /* Split up the arguments for an opcode or pseudo-op. */
1871 tokenize_arguments (char **args
, char *str
)
1873 char *old_input_line_pointer
;
1874 bfd_boolean saw_comma
= FALSE
;
1875 bfd_boolean saw_arg
= FALSE
;
1876 bfd_boolean saw_colon
= FALSE
;
1878 char *arg_end
, *arg
;
1881 /* Save and restore input_line_pointer around this function. */
1882 old_input_line_pointer
= input_line_pointer
;
1883 input_line_pointer
= str
;
1885 while (*input_line_pointer
)
1888 switch (*input_line_pointer
)
1895 input_line_pointer
++;
1896 if (saw_comma
|| saw_colon
|| !saw_arg
)
1902 input_line_pointer
++;
1903 if (saw_comma
|| saw_colon
|| !saw_arg
)
1909 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1912 arg_end
= input_line_pointer
+ 1;
1913 while (!expression_end (arg_end
))
1916 arg_len
= arg_end
- input_line_pointer
;
1917 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1918 args
[num_args
] = arg
;
1922 strncpy (arg
, input_line_pointer
, arg_len
);
1923 arg
[arg_len
] = '\0';
1925 input_line_pointer
= arg_end
;
1935 if (saw_comma
|| saw_colon
)
1937 input_line_pointer
= old_input_line_pointer
;
1942 as_bad (_("extra comma"));
1944 as_bad (_("extra colon"));
1946 as_bad (_("missing argument"));
1948 as_bad (_("missing comma or colon"));
1949 input_line_pointer
= old_input_line_pointer
;
1954 /* Parse the arguments to an opcode. Return TRUE on error. */
1957 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1959 expressionS
*tok
, *last_tok
;
1960 xtensa_opcode opcode
= insn
->opcode
;
1961 bfd_boolean had_error
= TRUE
;
1962 xtensa_isa isa
= xtensa_default_isa
;
1963 int n
, num_regs
= 0;
1964 int opcode_operand_count
;
1965 int opnd_cnt
, last_opnd_cnt
;
1966 unsigned int next_reg
= 0;
1967 char *old_input_line_pointer
;
1969 if (insn
->insn_type
== ITYPE_LITERAL
)
1970 opcode_operand_count
= 1;
1972 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1975 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1977 /* Save and restore input_line_pointer around this function. */
1978 old_input_line_pointer
= input_line_pointer
;
1984 /* Skip invisible operands. */
1985 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1991 for (n
= 0; n
< num_args
; n
++)
1993 input_line_pointer
= arg_strings
[n
];
1994 if (*input_line_pointer
== ':')
1996 xtensa_regfile opnd_rf
;
1997 input_line_pointer
++;
2000 assert (opnd_cnt
> 0);
2002 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2004 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2005 as_warn (_("incorrect register number, ignoring"));
2010 if (opnd_cnt
>= opcode_operand_count
)
2012 as_warn (_("too many arguments"));
2015 assert (opnd_cnt
< MAX_INSN_ARGS
);
2017 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2018 next_reg
= tok
->X_add_number
+ 1;
2020 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2022 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2024 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2025 /* minus 1 because we are seeing one right now */
2031 last_opnd_cnt
= opnd_cnt
;
2038 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2042 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2045 insn
->ntok
= tok
- insn
->tok
;
2049 input_line_pointer
= old_input_line_pointer
;
2055 get_invisible_operands (TInsn
*insn
)
2057 xtensa_isa isa
= xtensa_default_isa
;
2058 static xtensa_insnbuf slotbuf
= NULL
;
2060 xtensa_opcode opc
= insn
->opcode
;
2061 int slot
, opnd
, fmt_found
;
2065 slotbuf
= xtensa_insnbuf_alloc (isa
);
2067 /* Find format/slot where this can be encoded. */
2070 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2072 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2074 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2080 if (fmt_found
) break;
2085 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2089 /* First encode all the visible operands
2090 (to deal with shared field operands). */
2091 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2093 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2094 && (insn
->tok
[opnd
].X_op
== O_register
2095 || insn
->tok
[opnd
].X_op
== O_constant
))
2097 val
= insn
->tok
[opnd
].X_add_number
;
2098 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2099 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2103 /* Then pull out the values for the invisible ones. */
2104 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2106 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2108 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2109 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2110 insn
->tok
[opnd
].X_add_number
= val
;
2111 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2112 insn
->tok
[opnd
].X_op
= O_register
;
2114 insn
->tok
[opnd
].X_op
= O_constant
;
2123 xg_reverse_shift_count (char **cnt_argp
)
2125 char *cnt_arg
, *new_arg
;
2126 cnt_arg
= *cnt_argp
;
2128 /* replace the argument with "31-(argument)" */
2129 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2130 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2133 *cnt_argp
= new_arg
;
2137 /* If "arg" is a constant expression, return non-zero with the value
2141 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2144 char *save_ptr
= input_line_pointer
;
2146 input_line_pointer
= arg
;
2148 input_line_pointer
= save_ptr
;
2150 if (exp
.X_op
== O_constant
)
2152 *valp
= exp
.X_add_number
;
2161 xg_replace_opname (char **popname
, char *newop
)
2164 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2165 strcpy (*popname
, newop
);
2170 xg_check_num_args (int *pnum_args
,
2175 int num_args
= *pnum_args
;
2177 if (num_args
< expected_num
)
2179 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2180 num_args
, opname
, expected_num
);
2184 if (num_args
> expected_num
)
2186 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2187 num_args
, opname
, expected_num
);
2188 while (num_args
-- > expected_num
)
2190 free (arg_strings
[num_args
]);
2191 arg_strings
[num_args
] = 0;
2193 *pnum_args
= expected_num
;
2201 /* If the register is not specified as part of the opcode,
2202 then get it from the operand and move it to the opcode. */
2205 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2207 xtensa_isa isa
= xtensa_default_isa
;
2209 char *opname
, *new_opname
;
2210 const char *sr_name
;
2211 int is_user
, is_write
;
2212 bfd_boolean has_underbar
= FALSE
;
2217 has_underbar
= TRUE
;
2220 is_user
= (opname
[1] == 'u');
2221 is_write
= (opname
[0] == 'w');
2223 /* Opname == [rw]ur or [rwx]sr... */
2225 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2228 /* Check if the argument is a symbolic register name. */
2229 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2230 /* Handle WSR to "INTSET" as a special case. */
2231 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2232 && !strcasecmp (arg_strings
[1], "intset"))
2233 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2234 if (sr
== XTENSA_UNDEFINED
2235 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2237 /* Maybe it's a register number.... */
2239 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2241 as_bad (_("invalid register '%s' for '%s' instruction"),
2242 arg_strings
[1], opname
);
2245 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2246 if (sr
== XTENSA_UNDEFINED
)
2248 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2254 /* Remove the last argument, which is now part of the opcode. */
2255 free (arg_strings
[1]);
2259 /* Translate the opcode. */
2260 sr_name
= xtensa_sysreg_name (isa
, sr
);
2261 /* Another special case for "WSR.INTSET".... */
2262 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2264 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2265 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2268 *popname
= new_opname
;
2275 xtensa_translate_old_userreg_ops (char **popname
)
2277 xtensa_isa isa
= xtensa_default_isa
;
2279 char *opname
, *new_opname
;
2280 const char *sr_name
;
2281 bfd_boolean has_underbar
= FALSE
;
2284 if (opname
[0] == '_')
2286 has_underbar
= TRUE
;
2290 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2291 if (sr
!= XTENSA_UNDEFINED
)
2293 /* The new default name ("nnn") is different from the old default
2294 name ("URnnn"). The old default is handled below, and we don't
2295 want to recognize [RW]nnn, so do nothing if the name is the (new)
2297 static char namebuf
[10];
2298 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2299 if (strcmp (namebuf
, opname
+ 1) == 0)
2307 /* Only continue if the reg name is "URnnn". */
2308 if (opname
[1] != 'u' || opname
[2] != 'r')
2310 val
= strtoul (opname
+ 3, &end
, 10);
2314 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2315 if (sr
== XTENSA_UNDEFINED
)
2317 as_bad (_("invalid register number (%ld) for '%s'"),
2323 /* Translate the opcode. */
2324 sr_name
= xtensa_sysreg_name (isa
, sr
);
2325 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2326 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2327 opname
[0], sr_name
);
2329 *popname
= new_opname
;
2336 xtensa_translate_zero_immed (char *old_op
,
2346 assert (opname
[0] != '_');
2348 if (strcmp (opname
, old_op
) != 0)
2351 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2353 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2355 xg_replace_opname (popname
, new_op
);
2356 free (arg_strings
[1]);
2357 arg_strings
[1] = arg_strings
[2];
2366 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2367 Returns non-zero if an error was found. */
2370 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2372 char *opname
= *popname
;
2373 bfd_boolean has_underbar
= FALSE
;
2375 if (cur_vinsn
.inside_bundle
)
2380 has_underbar
= TRUE
;
2384 if (strcmp (opname
, "mov") == 0)
2386 if (use_transform () && !has_underbar
&& density_supported
)
2387 xg_replace_opname (popname
, "mov.n");
2390 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2392 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2393 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2394 strcpy (arg_strings
[2], arg_strings
[1]);
2400 if (strcmp (opname
, "bbsi.l") == 0)
2402 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2404 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2405 if (target_big_endian
)
2406 xg_reverse_shift_count (&arg_strings
[1]);
2410 if (strcmp (opname
, "bbci.l") == 0)
2412 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2414 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2415 if (target_big_endian
)
2416 xg_reverse_shift_count (&arg_strings
[1]);
2420 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2421 && strcmp (opname
, "nop") == 0)
2423 if (use_transform () && !has_underbar
&& density_supported
)
2424 xg_replace_opname (popname
, "nop.n");
2427 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2429 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2430 arg_strings
[0] = (char *) xmalloc (3);
2431 arg_strings
[1] = (char *) xmalloc (3);
2432 arg_strings
[2] = (char *) xmalloc (3);
2433 strcpy (arg_strings
[0], "a1");
2434 strcpy (arg_strings
[1], "a1");
2435 strcpy (arg_strings
[2], "a1");
2441 /* Recognize [RW]UR and [RWX]SR. */
2442 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2443 && (opname
[1] == 'u' || opname
[1] == 's'))
2444 || (opname
[0] == 'x' && opname
[1] == 's'))
2446 && opname
[3] == '\0')
2447 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2449 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2450 [RW]<name> if <name> is the non-default name of a user register. */
2451 if ((opname
[0] == 'r' || opname
[0] == 'w')
2452 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2453 return xtensa_translate_old_userreg_ops (popname
);
2455 /* Relax branches that don't allow comparisons against an immediate value
2456 of zero to the corresponding branches with implicit zero immediates. */
2457 if (!has_underbar
&& use_transform ())
2459 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2460 pnum_args
, arg_strings
))
2463 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2464 pnum_args
, arg_strings
))
2467 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2468 pnum_args
, arg_strings
))
2471 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2472 pnum_args
, arg_strings
))
2480 /* Functions for dealing with the Xtensa ISA. */
2482 /* Currently the assembler only allows us to use a single target per
2483 fragment. Because of this, only one operand for a given
2484 instruction may be symbolic. If there is a PC-relative operand,
2485 the last one is chosen. Otherwise, the result is the number of the
2486 last immediate operand, and if there are none of those, we fail and
2490 get_relaxable_immed (xtensa_opcode opcode
)
2492 int last_immed
= -1;
2495 if (opcode
== XTENSA_UNDEFINED
)
2498 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2499 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2501 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2503 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2505 if (last_immed
== -1
2506 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2513 static xtensa_opcode
2514 get_opcode_from_buf (const char *buf
, int slot
)
2516 static xtensa_insnbuf insnbuf
= NULL
;
2517 static xtensa_insnbuf slotbuf
= NULL
;
2518 xtensa_isa isa
= xtensa_default_isa
;
2523 insnbuf
= xtensa_insnbuf_alloc (isa
);
2524 slotbuf
= xtensa_insnbuf_alloc (isa
);
2527 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2528 fmt
= xtensa_format_decode (isa
, insnbuf
);
2529 if (fmt
== XTENSA_UNDEFINED
)
2530 return XTENSA_UNDEFINED
;
2532 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2533 return XTENSA_UNDEFINED
;
2535 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2536 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2540 #ifdef TENSILICA_DEBUG
2542 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2545 xtensa_print_insn_table (void)
2547 int num_opcodes
, num_operands
;
2548 xtensa_opcode opcode
;
2549 xtensa_isa isa
= xtensa_default_isa
;
2551 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2552 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2555 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2556 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2557 for (opn
= 0; opn
< num_operands
; opn
++)
2559 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2561 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2563 xtensa_regfile opnd_rf
=
2564 xtensa_operand_regfile (isa
, opcode
, opn
);
2565 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2567 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2568 fputs ("[lLr] ", stderr
);
2570 fputs ("i ", stderr
);
2572 fprintf (stderr
, "\n");
2578 print_vliw_insn (xtensa_insnbuf vbuf
)
2580 xtensa_isa isa
= xtensa_default_isa
;
2581 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2582 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2585 fprintf (stderr
, "format = %d\n", f
);
2587 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2589 xtensa_opcode opcode
;
2593 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2594 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2595 opname
= xtensa_opcode_name (isa
, opcode
);
2597 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2598 fprintf (stderr
, " operands = ");
2600 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2604 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2606 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2607 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2608 fprintf (stderr
, "%d ", val
);
2610 fprintf (stderr
, "\n");
2612 xtensa_insnbuf_free (isa
, sbuf
);
2615 #endif /* TENSILICA_DEBUG */
2619 is_direct_call_opcode (xtensa_opcode opcode
)
2621 xtensa_isa isa
= xtensa_default_isa
;
2622 int n
, num_operands
;
2624 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2627 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2628 for (n
= 0; n
< num_operands
; n
++)
2630 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2631 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2638 /* Convert from BFD relocation type code to slot and operand number.
2639 Returns non-zero on failure. */
2642 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2644 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2645 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2647 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2650 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2651 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2653 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2663 /* Convert from slot number to BFD relocation type code for the
2664 standard PC-relative relocations. Return BFD_RELOC_NONE on
2667 static bfd_reloc_code_real_type
2668 encode_reloc (int slot
)
2670 if (slot
< 0 || slot
> 14)
2671 return BFD_RELOC_NONE
;
2673 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2677 /* Convert from slot numbers to BFD relocation type code for the
2678 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2680 static bfd_reloc_code_real_type
2681 encode_alt_reloc (int slot
)
2683 if (slot
< 0 || slot
> 14)
2684 return BFD_RELOC_NONE
;
2686 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2691 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2694 xtensa_opcode opcode
,
2700 uint32 valbuf
= value
;
2702 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2704 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2706 as_bad_where ((char *) file
, line
,
2707 _("operand %u is out of range for '%s'"), value
,
2708 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2710 as_bad_where ((char *) file
, line
,
2711 _("operand %u is invalid for '%s'"), value
,
2712 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2716 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2722 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2725 xtensa_opcode opcode
,
2729 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2730 fmt
, slot
, slotbuf
, &val
);
2731 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2736 /* Checks for rules from xtensa-relax tables. */
2738 /* The routine xg_instruction_matches_option_term must return TRUE
2739 when a given option term is true. The meaning of all of the option
2740 terms is given interpretation by this function. This is needed when
2741 an option depends on the state of a directive, but there are no such
2742 options in use right now. */
2745 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2746 const ReqOrOption
*option
)
2748 if (strcmp (option
->option_name
, "realnop") == 0
2749 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2751 /* These conditions were evaluated statically when building the
2752 relaxation table. There's no need to reevaluate them now. */
2757 as_fatal (_("internal error: unknown option name '%s'"),
2758 option
->option_name
);
2764 xg_instruction_matches_or_options (TInsn
*insn
,
2765 const ReqOrOptionList
*or_option
)
2767 const ReqOrOption
*option
;
2768 /* Must match each of the AND terms. */
2769 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2771 if (xg_instruction_matches_option_term (insn
, option
))
2779 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2781 const ReqOption
*req_options
;
2782 /* Must match each of the AND terms. */
2783 for (req_options
= options
;
2784 req_options
!= NULL
;
2785 req_options
= req_options
->next
)
2787 /* Must match one of the OR clauses. */
2788 if (!xg_instruction_matches_or_options (insn
,
2789 req_options
->or_option_terms
))
2796 /* Return the transition rule that matches or NULL if none matches. */
2799 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2801 PreconditionList
*condition_l
;
2803 if (rule
->opcode
!= insn
->opcode
)
2806 for (condition_l
= rule
->conditions
;
2807 condition_l
!= NULL
;
2808 condition_l
= condition_l
->next
)
2812 Precondition
*cond
= condition_l
->precond
;
2817 /* The expression must be the constant. */
2818 assert (cond
->op_num
< insn
->ntok
);
2819 exp1
= &insn
->tok
[cond
->op_num
];
2820 if (expr_is_const (exp1
))
2825 if (get_expr_const (exp1
) != cond
->op_data
)
2829 if (get_expr_const (exp1
) == cond
->op_data
)
2836 else if (expr_is_register (exp1
))
2841 if (get_expr_register (exp1
) != cond
->op_data
)
2845 if (get_expr_register (exp1
) == cond
->op_data
)
2857 assert (cond
->op_num
< insn
->ntok
);
2858 assert (cond
->op_data
< insn
->ntok
);
2859 exp1
= &insn
->tok
[cond
->op_num
];
2860 exp2
= &insn
->tok
[cond
->op_data
];
2865 if (!expr_is_equal (exp1
, exp2
))
2869 if (expr_is_equal (exp1
, exp2
))
2881 if (!xg_instruction_matches_options (insn
, rule
->options
))
2889 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2891 bfd_boolean a_greater
= FALSE
;
2892 bfd_boolean b_greater
= FALSE
;
2894 ReqOptionList
*l_a
= a
->options
;
2895 ReqOptionList
*l_b
= b
->options
;
2897 /* We only care if they both are the same except for
2898 a const16 vs. an l32r. */
2900 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2902 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2903 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2904 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2906 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2908 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2910 /* This is the case we care about. */
2911 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2912 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2919 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2920 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2930 l_or_a
= l_or_a
->next
;
2931 l_or_b
= l_or_b
->next
;
2933 if (l_or_a
|| l_or_b
)
2942 /* Incomparable if the substitution was used differently in two cases. */
2943 if (a_greater
&& b_greater
)
2955 static TransitionRule
*
2956 xg_instruction_match (TInsn
*insn
)
2958 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2960 assert (insn
->opcode
< table
->num_opcodes
);
2962 /* Walk through all of the possible transitions. */
2963 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2965 TransitionRule
*rule
= l
->rule
;
2966 if (xg_instruction_matches_rule (insn
, rule
))
2973 /* Various Other Internal Functions. */
2976 is_unique_insn_expansion (TransitionRule
*r
)
2978 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2980 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2987 xg_get_build_instr_size (BuildInstr
*insn
)
2989 assert (insn
->typ
== INSTR_INSTR
);
2990 return xg_get_single_size (insn
->opcode
);
2995 xg_is_narrow_insn (TInsn
*insn
)
2997 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3000 assert (insn
->insn_type
== ITYPE_INSN
);
3001 assert (insn
->opcode
< table
->num_opcodes
);
3003 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3005 TransitionRule
*rule
= l
->rule
;
3007 if (xg_instruction_matches_rule (insn
, rule
)
3008 && is_unique_insn_expansion (rule
))
3010 /* It only generates one instruction... */
3011 assert (insn
->insn_type
== ITYPE_INSN
);
3012 /* ...and it is a larger instruction. */
3013 if (xg_get_single_size (insn
->opcode
)
3014 < xg_get_build_instr_size (rule
->to_instr
))
3022 return (num_match
== 1);
3027 xg_is_single_relaxable_insn (TInsn
*insn
)
3029 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3032 assert (insn
->insn_type
== ITYPE_INSN
);
3033 assert (insn
->opcode
< table
->num_opcodes
);
3035 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3037 TransitionRule
*rule
= l
->rule
;
3039 if (xg_instruction_matches_rule (insn
, rule
)
3040 && is_unique_insn_expansion (rule
))
3042 /* It only generates one instruction... */
3043 assert (insn
->insn_type
== ITYPE_INSN
);
3044 /* ... and it is a larger instruction. */
3045 if (xg_get_single_size (insn
->opcode
)
3046 <= xg_get_build_instr_size (rule
->to_instr
))
3054 return (num_match
== 1);
3058 /* Return the maximum number of bytes this opcode can expand to. */
3061 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3063 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3065 int max_size
= xg_get_single_size (opcode
);
3067 assert (opcode
< table
->num_opcodes
);
3069 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3071 TransitionRule
*rule
= l
->rule
;
3072 BuildInstr
*build_list
;
3077 build_list
= rule
->to_instr
;
3078 if (is_unique_insn_expansion (rule
))
3080 assert (build_list
->typ
== INSTR_INSTR
);
3081 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3084 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3086 switch (build_list
->typ
)
3089 this_size
+= xg_get_single_size (build_list
->opcode
);
3091 case INSTR_LITERAL_DEF
:
3092 case INSTR_LABEL_DEF
:
3097 if (this_size
> max_size
)
3098 max_size
= this_size
;
3104 /* Return the maximum number of literal bytes this opcode can generate. */
3107 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3109 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3113 assert (opcode
< table
->num_opcodes
);
3115 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3117 TransitionRule
*rule
= l
->rule
;
3118 BuildInstr
*build_list
;
3123 build_list
= rule
->to_instr
;
3124 if (is_unique_insn_expansion (rule
))
3126 assert (build_list
->typ
== INSTR_INSTR
);
3127 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3130 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3132 switch (build_list
->typ
)
3134 case INSTR_LITERAL_DEF
:
3135 /* Hard-coded 4-byte literal. */
3139 case INSTR_LABEL_DEF
:
3144 if (this_size
> max_size
)
3145 max_size
= this_size
;
3152 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3154 int steps_taken
= 0;
3155 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3158 assert (insn
->insn_type
== ITYPE_INSN
);
3159 assert (insn
->opcode
< table
->num_opcodes
);
3161 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3163 TransitionRule
*rule
= l
->rule
;
3165 if (xg_instruction_matches_rule (insn
, rule
))
3167 if (steps_taken
== lateral_steps
)
3177 get_special_literal_symbol (void)
3179 static symbolS
*sym
= NULL
;
3182 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3188 get_special_label_symbol (void)
3190 static symbolS
*sym
= NULL
;
3193 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3199 xg_valid_literal_expression (const expressionS
*exp
)
3216 /* This will check to see if the value can be converted into the
3217 operand type. It will return TRUE if it does not fit. */
3220 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3222 uint32 valbuf
= value
;
3223 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3229 /* Assumes: All immeds are constants. Check that all constants fit
3230 into their immeds; return FALSE if not. */
3233 xg_immeds_fit (const TInsn
*insn
)
3235 xtensa_isa isa
= xtensa_default_isa
;
3239 assert (insn
->insn_type
== ITYPE_INSN
);
3240 for (i
= 0; i
< n
; ++i
)
3242 const expressionS
*expr
= &insn
->tok
[i
];
3243 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3250 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3255 /* The symbol should have a fixup associated with it. */
3264 /* This should only be called after we have an initial
3265 estimate of the addresses. */
3268 xg_symbolic_immeds_fit (const TInsn
*insn
,
3274 xtensa_isa isa
= xtensa_default_isa
;
3282 assert (insn
->insn_type
== ITYPE_INSN
);
3284 for (i
= 0; i
< n
; ++i
)
3286 const expressionS
*expr
= &insn
->tok
[i
];
3287 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3294 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3300 /* Check for the worst case. */
3301 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3306 /* We only allow symbols for PC-relative references.
3307 If pc_frag == 0, then we don't have frag locations yet. */
3309 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3312 /* If it is a weak symbol, then assume it won't reach. */
3313 if (S_IS_WEAK (expr
->X_add_symbol
))
3316 if (is_direct_call_opcode (insn
->opcode
)
3317 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3319 /* If callee is undefined or in a different segment, be
3320 optimistic and assume it will be in range. */
3321 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3325 /* Only references within a segment can be known to fit in the
3326 operands at assembly time. */
3327 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3330 symbolP
= expr
->X_add_symbol
;
3331 sym_frag
= symbol_get_frag (symbolP
);
3332 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3333 pc
= pc_frag
->fr_address
+ pc_offset
;
3335 /* If frag has yet to be reached on this pass, assume it
3336 will move by STRETCH just as we did. If this is not so,
3337 it will be because some frag between grows, and that will
3338 force another pass. Beware zero-length frags. There
3339 should be a faster way to do this. */
3342 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3343 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3348 new_offset
= target
;
3349 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3350 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3355 /* The symbol should have a fixup associated with it. */
3364 /* Return TRUE on success. */
3367 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3372 memset (targ
, 0, sizeof (TInsn
));
3373 targ
->loc
= insn
->loc
;
3378 targ
->opcode
= bi
->opcode
;
3379 targ
->insn_type
= ITYPE_INSN
;
3380 targ
->is_specific_opcode
= FALSE
;
3382 for (; op
!= NULL
; op
= op
->next
)
3384 int op_num
= op
->op_num
;
3385 int op_data
= op
->op_data
;
3387 assert (op
->op_num
< MAX_INSN_ARGS
);
3389 if (targ
->ntok
<= op_num
)
3390 targ
->ntok
= op_num
+ 1;
3395 set_expr_const (&targ
->tok
[op_num
], op_data
);
3398 assert (op_data
< insn
->ntok
);
3399 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3402 sym
= get_special_literal_symbol ();
3403 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3406 sym
= get_special_label_symbol ();
3407 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3409 case OP_OPERAND_HI16U
:
3410 case OP_OPERAND_LOW16U
:
3411 assert (op_data
< insn
->ntok
);
3412 if (expr_is_const (&insn
->tok
[op_data
]))
3415 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3416 val
= xg_apply_userdef_op_fn (op
->typ
,
3419 targ
->tok
[op_num
].X_add_number
= val
;
3423 /* For const16 we can create relocations for these. */
3424 if (targ
->opcode
== XTENSA_UNDEFINED
3425 || (targ
->opcode
!= xtensa_const16_opcode
))
3427 assert (op_data
< insn
->ntok
);
3428 /* Need to build a O_lo16 or O_hi16. */
3429 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3430 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3432 if (op
->typ
== OP_OPERAND_HI16U
)
3433 targ
->tok
[op_num
].X_op
= O_hi16
;
3434 else if (op
->typ
== OP_OPERAND_LOW16U
)
3435 targ
->tok
[op_num
].X_op
= O_lo16
;
3442 /* currently handles:
3445 OP_OPERAND_F32MINUS */
3446 if (xg_has_userdef_op_fn (op
->typ
))
3448 assert (op_data
< insn
->ntok
);
3449 if (expr_is_const (&insn
->tok
[op_data
]))
3452 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3453 val
= xg_apply_userdef_op_fn (op
->typ
,
3456 targ
->tok
[op_num
].X_add_number
= val
;
3459 return FALSE
; /* We cannot use a relocation for this. */
3468 case INSTR_LITERAL_DEF
:
3470 targ
->opcode
= XTENSA_UNDEFINED
;
3471 targ
->insn_type
= ITYPE_LITERAL
;
3472 targ
->is_specific_opcode
= FALSE
;
3473 for (; op
!= NULL
; op
= op
->next
)
3475 int op_num
= op
->op_num
;
3476 int op_data
= op
->op_data
;
3477 assert (op
->op_num
< MAX_INSN_ARGS
);
3479 if (targ
->ntok
<= op_num
)
3480 targ
->ntok
= op_num
+ 1;
3485 assert (op_data
< insn
->ntok
);
3486 /* We can only pass resolvable literals through. */
3487 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3489 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3501 case INSTR_LABEL_DEF
:
3503 targ
->opcode
= XTENSA_UNDEFINED
;
3504 targ
->insn_type
= ITYPE_LABEL
;
3505 targ
->is_specific_opcode
= FALSE
;
3506 /* Literal with no ops is a label? */
3507 assert (op
== NULL
);
3518 /* Return TRUE on success. */
3521 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3523 for (; bi
!= NULL
; bi
= bi
->next
)
3525 TInsn
*next_insn
= istack_push_space (istack
);
3527 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3534 /* Return TRUE on valid expansion. */
3537 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3539 int stack_size
= istack
->ninsn
;
3540 int steps_taken
= 0;
3541 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3544 assert (insn
->insn_type
== ITYPE_INSN
);
3545 assert (insn
->opcode
< table
->num_opcodes
);
3547 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3549 TransitionRule
*rule
= l
->rule
;
3551 if (xg_instruction_matches_rule (insn
, rule
))
3553 if (lateral_steps
== steps_taken
)
3557 /* This is it. Expand the rule to the stack. */
3558 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3561 /* Check to see if it fits. */
3562 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3564 TInsn
*insn
= &istack
->insn
[i
];
3566 if (insn
->insn_type
== ITYPE_INSN
3567 && !tinsn_has_symbolic_operands (insn
)
3568 && !xg_immeds_fit (insn
))
3570 istack
->ninsn
= stack_size
;
3584 xg_expand_narrow (TInsn
*targ
, TInsn
*insn
)
3586 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3589 assert (insn
->insn_type
== ITYPE_INSN
);
3590 assert (insn
->opcode
< table
->num_opcodes
);
3592 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3594 TransitionRule
*rule
= l
->rule
;
3595 if (xg_instruction_matches_rule (insn
, rule
)
3596 && is_unique_insn_expansion (rule
))
3598 /* Is it a larger instruction? */
3599 if (xg_get_single_size (insn
->opcode
)
3600 <= xg_get_build_instr_size (rule
->to_instr
))
3602 xg_build_to_insn (targ
, insn
, rule
->to_instr
);
3611 /* Relax the assembly instruction at least "min_steps".
3612 Return the number of steps taken. */
3615 xg_assembly_relax (IStack
*istack
,
3618 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3619 offsetT pc_offset
, /* offset in fragment */
3620 int min_steps
, /* minimum conversion steps */
3621 long stretch
) /* number of bytes stretched so far */
3623 int steps_taken
= 0;
3625 /* assert (has no symbolic operands)
3626 Some of its immeds don't fit.
3627 Try to build a relaxed version.
3628 This may go through a couple of stages
3629 of single instruction transformations before
3632 TInsn single_target
;
3634 int lateral_steps
= 0;
3635 int istack_size
= istack
->ninsn
;
3637 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3638 && steps_taken
>= min_steps
)
3640 istack_push (istack
, insn
);
3643 current_insn
= *insn
;
3645 /* Walk through all of the single instruction expansions. */
3646 while (xg_is_single_relaxable_insn (¤t_insn
))
3648 int error_val
= xg_expand_narrow (&single_target
, ¤t_insn
);
3650 assert (!error_val
);
3652 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3656 if (steps_taken
>= min_steps
)
3658 istack_push (istack
, &single_target
);
3662 current_insn
= single_target
;
3665 /* Now check for a multi-instruction expansion. */
3666 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3668 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3671 if (steps_taken
>= min_steps
)
3673 istack_push (istack
, ¤t_insn
);
3678 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3680 if (steps_taken
>= min_steps
)
3684 istack
->ninsn
= istack_size
;
3687 /* It's not going to work -- use the original. */
3688 istack_push (istack
, insn
);
3694 xg_force_frag_space (int size
)
3696 /* This may have the side effect of creating a new fragment for the
3697 space to go into. I just do not like the name of the "frag"
3704 xg_finish_frag (char *last_insn
,
3705 enum xtensa_relax_statesE frag_state
,
3706 enum xtensa_relax_statesE slot0_state
,
3708 bfd_boolean is_insn
)
3710 /* Finish off this fragment so that it has at LEAST the desired
3711 max_growth. If it doesn't fit in this fragment, close this one
3712 and start a new one. In either case, return a pointer to the
3713 beginning of the growth area. */
3717 xg_force_frag_space (max_growth
);
3719 old_frag
= frag_now
;
3721 frag_now
->fr_opcode
= last_insn
;
3723 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3725 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3726 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3728 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3729 xtensa_set_frag_assembly_state (frag_now
);
3731 /* Just to make sure that we did not split it up. */
3732 assert (old_frag
->fr_next
== frag_now
);
3736 /* Return TRUE if the target frag is one of the next non-empty frags. */
3739 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3744 for (; fragP
; fragP
= fragP
->fr_next
)
3746 if (fragP
== target
)
3748 if (fragP
->fr_fix
!= 0)
3750 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3752 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3753 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3755 if (fragP
->fr_type
== rs_space
)
3763 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3765 xtensa_isa isa
= xtensa_default_isa
;
3767 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3772 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3773 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3776 for (i
= 0; i
< num_ops
; i
++)
3778 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3784 if (target_op
== -1)
3787 if (insn
->ntok
<= target_op
)
3790 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3793 sym
= insn
->tok
[target_op
].X_add_symbol
;
3797 if (insn
->tok
[target_op
].X_add_number
!= 0)
3800 target_frag
= symbol_get_frag (sym
);
3801 if (target_frag
== NULL
)
3804 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3805 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3813 xg_add_branch_and_loop_targets (TInsn
*insn
)
3815 xtensa_isa isa
= xtensa_default_isa
;
3816 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3818 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3821 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3822 && insn
->tok
[i
].X_op
== O_symbol
)
3823 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3827 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3828 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3832 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3834 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3835 && insn
->tok
[i
].X_op
== O_symbol
)
3837 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3838 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3839 if (S_IS_DEFINED (sym
))
3840 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3847 /* Return FALSE if no error. */
3850 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3855 switch (instr_spec
->typ
)
3858 new_insn
->insn_type
= ITYPE_INSN
;
3859 new_insn
->opcode
= instr_spec
->opcode
;
3860 new_insn
->is_specific_opcode
= FALSE
;
3861 new_insn
->loc
= old_insn
->loc
;
3863 case INSTR_LITERAL_DEF
:
3864 new_insn
->insn_type
= ITYPE_LITERAL
;
3865 new_insn
->opcode
= XTENSA_UNDEFINED
;
3866 new_insn
->is_specific_opcode
= FALSE
;
3867 new_insn
->loc
= old_insn
->loc
;
3869 case INSTR_LABEL_DEF
:
3870 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3874 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3877 const expressionS
*src_exp
;
3883 /* The expression must be the constant. */
3884 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3885 exp
= &new_insn
->tok
[b_op
->op_num
];
3886 set_expr_const (exp
, b_op
->op_data
);
3890 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3891 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3892 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3893 exp
= &new_insn
->tok
[b_op
->op_num
];
3894 copy_expr (exp
, src_exp
);
3899 as_bad (_("can't handle generation of literal/labels yet"));
3903 as_bad (_("can't handle undefined OP TYPE"));
3908 new_insn
->ntok
= num_ops
;
3913 /* Return TRUE if it was simplified. */
3916 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3918 TransitionRule
*rule
;
3919 BuildInstr
*insn_spec
;
3921 if (old_insn
->is_specific_opcode
|| !density_supported
)
3924 rule
= xg_instruction_match (old_insn
);
3928 insn_spec
= rule
->to_instr
;
3929 /* There should only be one. */
3930 assert (insn_spec
!= NULL
);
3931 assert (insn_spec
->next
== NULL
);
3932 if (insn_spec
->next
!= NULL
)
3935 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3941 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3942 l32i.n. (2) Check the number of operands. (3) Place the instruction
3943 tokens into the stack or relax it and place multiple
3944 instructions/literals onto the stack. Return FALSE if no error. */
3947 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3951 bfd_boolean do_expand
;
3953 memset (&new_insn
, 0, sizeof (TInsn
));
3955 /* Narrow it if we can. xg_simplify_insn now does all the
3956 appropriate checking (e.g., for the density option). */
3957 if (xg_simplify_insn (orig_insn
, &new_insn
))
3958 orig_insn
= &new_insn
;
3960 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3962 if (orig_insn
->ntok
< noperands
)
3964 as_bad (_("found %d operands for '%s': Expected %d"),
3966 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3970 if (orig_insn
->ntok
> noperands
)
3971 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3973 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3976 /* If there are not enough operands, we will assert above. If there
3977 are too many, just cut out the extras here. */
3978 orig_insn
->ntok
= noperands
;
3980 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3983 /* If the instruction will definitely need to be relaxed, it is better
3984 to expand it now for better scheduling. Decide whether to expand
3986 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3988 /* Calls should be expanded to longcalls only in the backend relaxation
3989 so that the assembly scheduler will keep the L32R/CALLX instructions
3991 if (is_direct_call_opcode (orig_insn
->opcode
))
3994 if (tinsn_has_symbolic_operands (orig_insn
))
3996 /* The values of symbolic operands are not known yet, so only expand
3997 now if an operand is "complex" (e.g., difference of symbols) and
3998 will have to be stored as a literal regardless of the value. */
3999 if (!tinsn_has_complex_operands (orig_insn
))
4002 else if (xg_immeds_fit (orig_insn
))
4006 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4008 istack_push (istack
, orig_insn
);
4014 /* Return TRUE if the section flags are marked linkonce
4015 or the name is .gnu.linkonce*. */
4018 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4020 flagword flags
, link_once_flags
;
4022 flags
= bfd_get_section_flags (abfd
, sec
);
4023 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4025 /* Flags might not be set yet. */
4026 if (!link_once_flags
)
4028 static size_t len
= sizeof ".gnu.linkonce.t.";
4030 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
4031 link_once_flags
= SEC_LINK_ONCE
;
4033 return (link_once_flags
!= 0);
4038 xtensa_add_literal_sym (symbolS
*sym
)
4042 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4044 l
->next
= literal_syms
;
4050 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4052 static int lit_num
= 0;
4053 static char name
[256];
4056 sprintf (name
, ".L_lit_sym%d", lit_num
);
4058 /* Create a local symbol. If it is in a linkonce section, we have to
4059 be careful to make sure that if it is used in a relocation that the
4060 symbol will be in the output file. */
4061 if (get_is_linkonce_section (stdoutput
, sec
))
4063 symbolP
= symbol_new (name
, sec
, 0, frag
);
4064 S_CLEAR_EXTERNAL (symbolP
);
4065 /* symbolP->local = 1; */
4068 symbolP
= symbol_new (name
, sec
, 0, frag
);
4070 xtensa_add_literal_sym (symbolP
);
4072 frag
->tc_frag_data
.is_literal
= TRUE
;
4078 /* Currently all literals that are generated here are 32-bit L32R targets. */
4081 xg_assemble_literal (/* const */ TInsn
*insn
)
4084 symbolS
*lit_sym
= NULL
;
4086 /* size = 4 for L32R. It could easily be larger when we move to
4087 larger constants. Add a parameter later. */
4088 offsetT litsize
= 4;
4089 offsetT litalign
= 2; /* 2^2 = 4 */
4090 expressionS saved_loc
;
4091 expressionS
* emit_val
;
4093 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4095 assert (insn
->insn_type
== ITYPE_LITERAL
);
4096 assert (insn
->ntok
== 1); /* must be only one token here */
4098 xtensa_switch_to_literal_fragment (&state
);
4100 emit_val
= &insn
->tok
[0];
4101 if (emit_val
->X_op
== O_big
)
4103 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4106 /* This happens when someone writes a "movi a2, big_number". */
4107 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4108 _("invalid immediate"));
4109 xtensa_restore_emit_state (&state
);
4114 /* Force a 4-byte align here. Note that this opens a new frag, so all
4115 literals done with this function have a frag to themselves. That's
4116 important for the way text section literals work. */
4117 frag_align (litalign
, 0, 0);
4118 record_alignment (now_seg
, litalign
);
4120 if (emit_val
->X_op
== O_pltrel
)
4122 char *p
= frag_more (litsize
);
4123 xtensa_set_frag_assembly_state (frag_now
);
4124 if (emit_val
->X_add_symbol
)
4125 emit_val
->X_op
= O_symbol
;
4127 emit_val
->X_op
= O_constant
;
4128 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4129 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4132 emit_expr (emit_val
, litsize
);
4134 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4135 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4136 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4137 lit_sym
= frag_now
->fr_symbol
;
4138 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4141 xtensa_restore_emit_state (&state
);
4147 xg_assemble_literal_space (/* const */ int size
, int slot
)
4150 /* We might have to do something about this alignment. It only
4151 takes effect if something is placed here. */
4152 offsetT litalign
= 2; /* 2^2 = 4 */
4153 fragS
*lit_saved_frag
;
4155 assert (size
% 4 == 0);
4157 xtensa_switch_to_literal_fragment (&state
);
4159 /* Force a 4-byte align here. */
4160 frag_align (litalign
, 0, 0);
4161 record_alignment (now_seg
, litalign
);
4163 xg_force_frag_space (size
);
4165 lit_saved_frag
= frag_now
;
4166 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4167 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4168 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4169 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4172 xtensa_restore_emit_state (&state
);
4173 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4177 /* Put in a fixup record based on the opcode.
4178 Return TRUE on success. */
4181 xg_add_opcode_fix (TInsn
*tinsn
,
4189 xtensa_opcode opcode
= tinsn
->opcode
;
4190 bfd_reloc_code_real_type reloc
;
4191 reloc_howto_type
*howto
;
4195 reloc
= BFD_RELOC_NONE
;
4197 /* First try the special cases for "alternate" relocs. */
4198 if (opcode
== xtensa_l32r_opcode
)
4200 if (fragP
->tc_frag_data
.use_absolute_literals
)
4201 reloc
= encode_alt_reloc (slot
);
4203 else if (opcode
== xtensa_const16_opcode
)
4205 if (expr
->X_op
== O_lo16
)
4207 reloc
= encode_reloc (slot
);
4208 expr
->X_op
= O_symbol
;
4210 else if (expr
->X_op
== O_hi16
)
4212 reloc
= encode_alt_reloc (slot
);
4213 expr
->X_op
= O_symbol
;
4217 if (opnum
!= get_relaxable_immed (opcode
))
4219 as_bad (_("invalid relocation for operand %i of '%s'"),
4220 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4224 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4225 into the symbol table where the generic portions of the assembler
4226 won't know what to do with them. */
4227 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4229 as_bad (_("invalid expression for operand %i of '%s'"),
4230 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4234 /* Next try the generic relocs. */
4235 if (reloc
== BFD_RELOC_NONE
)
4236 reloc
= encode_reloc (slot
);
4237 if (reloc
== BFD_RELOC_NONE
)
4239 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4243 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4246 as_bad (_("undefined symbol for opcode \"%s\""),
4247 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4251 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4252 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4253 howto
->pc_relative
, reloc
);
4254 the_fix
->fx_no_overflow
= 1;
4256 if (expr
->X_add_symbol
4257 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4258 || S_IS_WEAK (expr
->X_add_symbol
)))
4259 the_fix
->fx_plt
= TRUE
;
4261 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4262 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4263 the_fix
->tc_fix_data
.slot
= slot
;
4270 xg_emit_insn_to_buf (TInsn
*tinsn
,
4275 bfd_boolean build_fix
)
4277 static xtensa_insnbuf insnbuf
= NULL
;
4278 bfd_boolean has_symbolic_immed
= FALSE
;
4279 bfd_boolean ok
= TRUE
;
4281 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4283 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4284 if (has_symbolic_immed
&& build_fix
)
4287 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4288 expressionS
*exp
= &tinsn
->tok
[opnum
];
4290 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4293 fragP
->tc_frag_data
.is_insn
= TRUE
;
4294 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4295 (unsigned char *) buf
, 0);
4301 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4303 symbolS
*sym
= get_special_literal_symbol ();
4307 assert (insn
->insn_type
== ITYPE_INSN
);
4308 for (i
= 0; i
< insn
->ntok
; i
++)
4309 if (insn
->tok
[i
].X_add_symbol
== sym
)
4310 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4316 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4318 symbolS
*sym
= get_special_label_symbol ();
4320 /* assert (!insn->is_literal); */
4321 for (i
= 0; i
< insn
->ntok
; i
++)
4322 if (insn
->tok
[i
].X_add_symbol
== sym
)
4323 insn
->tok
[i
].X_add_symbol
= label_sym
;
4328 /* Return TRUE if the instruction can write to the specified
4329 integer register. */
4332 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4336 xtensa_isa isa
= xtensa_default_isa
;
4338 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4340 for (i
= 0; i
< num_ops
; i
++)
4343 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4344 if ((inout
== 'o' || inout
== 'm')
4345 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4347 xtensa_regfile opnd_rf
=
4348 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4349 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4351 if ((insn
->tok
[i
].X_op
== O_register
)
4352 && (insn
->tok
[i
].X_add_number
== regnum
))
4362 is_bad_loopend_opcode (const TInsn
*tinsn
)
4364 xtensa_opcode opcode
= tinsn
->opcode
;
4366 if (opcode
== XTENSA_UNDEFINED
)
4369 if (opcode
== xtensa_call0_opcode
4370 || opcode
== xtensa_callx0_opcode
4371 || opcode
== xtensa_call4_opcode
4372 || opcode
== xtensa_callx4_opcode
4373 || opcode
== xtensa_call8_opcode
4374 || opcode
== xtensa_callx8_opcode
4375 || opcode
== xtensa_call12_opcode
4376 || opcode
== xtensa_callx12_opcode
4377 || opcode
== xtensa_isync_opcode
4378 || opcode
== xtensa_ret_opcode
4379 || opcode
== xtensa_ret_n_opcode
4380 || opcode
== xtensa_retw_opcode
4381 || opcode
== xtensa_retw_n_opcode
4382 || opcode
== xtensa_waiti_opcode
4383 || opcode
== xtensa_rsr_lcount_opcode
)
4390 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4391 This allows the debugger to add unaligned labels.
4392 Also, the assembler generates stabs labels that need
4393 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4396 is_unaligned_label (symbolS
*sym
)
4398 const char *name
= S_GET_NAME (sym
);
4399 static size_t fake_size
= 0;
4403 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4406 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4408 fake_size
= strlen (FAKE_LABEL_NAME
);
4411 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4412 && (name
[fake_size
] == 'F'
4413 || name
[fake_size
] == 'L'
4414 || (name
[fake_size
] == 'e'
4415 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4423 next_non_empty_frag (const fragS
*fragP
)
4425 fragS
*next_fragP
= fragP
->fr_next
;
4427 /* Sometimes an empty will end up here due storage allocation issues.
4428 So we have to skip until we find something legit. */
4429 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4430 next_fragP
= next_fragP
->fr_next
;
4432 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4440 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4442 xtensa_opcode out_opcode
;
4443 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4445 if (next_fragP
== NULL
)
4448 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4449 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4451 *opcode
= out_opcode
;
4459 frag_format_size (const fragS
*fragP
)
4461 static xtensa_insnbuf insnbuf
= NULL
;
4462 xtensa_isa isa
= xtensa_default_isa
;
4467 insnbuf
= xtensa_insnbuf_alloc (isa
);
4470 return XTENSA_UNDEFINED
;
4472 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4473 (unsigned char *) fragP
->fr_literal
, 0);
4475 fmt
= xtensa_format_decode (isa
, insnbuf
);
4476 if (fmt
== XTENSA_UNDEFINED
)
4477 return XTENSA_UNDEFINED
;
4478 fmt_size
= xtensa_format_length (isa
, fmt
);
4480 /* If the next format won't be changing due to relaxation, just
4481 return the length of the first format. */
4482 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4485 /* If during relaxation we have to pull an instruction out of a
4486 multi-slot instruction, we will return the more conservative
4487 number. This works because alignment on bigger instructions
4488 is more restrictive than alignment on smaller instructions.
4489 This is more conservative than we would like, but it happens
4492 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4495 /* If we aren't doing one of our own relaxations or it isn't
4496 slot-based, then the insn size won't change. */
4497 if (fragP
->fr_type
!= rs_machine_dependent
)
4499 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4502 /* If an instruction is about to grow, return the longer size. */
4503 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4504 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4507 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4508 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4515 next_frag_format_size (const fragS
*fragP
)
4517 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4518 return frag_format_size (next_fragP
);
4522 /* If the next legit fragment is an end-of-loop marker,
4523 switch its state so it will instantiate a NOP. */
4526 update_next_frag_state (fragS
*fragP
)
4528 fragS
*next_fragP
= fragP
->fr_next
;
4529 fragS
*new_target
= NULL
;
4533 /* We are guaranteed there will be one of these... */
4534 while (!(next_fragP
->fr_type
== rs_machine_dependent
4535 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4536 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4537 next_fragP
= next_fragP
->fr_next
;
4539 assert (next_fragP
->fr_type
== rs_machine_dependent
4540 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4541 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4543 /* ...and one of these. */
4544 new_target
= next_fragP
->fr_next
;
4545 while (!(new_target
->fr_type
== rs_machine_dependent
4546 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4547 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4548 new_target
= new_target
->fr_next
;
4550 assert (new_target
->fr_type
== rs_machine_dependent
4551 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4552 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4555 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4557 if (next_fragP
->fr_type
== rs_machine_dependent
4558 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4560 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4564 next_fragP
= next_fragP
->fr_next
;
4570 next_frag_is_branch_target (const fragS
*fragP
)
4572 /* Sometimes an empty will end up here due to storage allocation issues,
4573 so we have to skip until we find something legit. */
4574 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4576 if (fragP
->tc_frag_data
.is_branch_target
)
4578 if (fragP
->fr_fix
!= 0)
4586 next_frag_is_loop_target (const fragS
*fragP
)
4588 /* Sometimes an empty will end up here due storage allocation issues.
4589 So we have to skip until we find something legit. */
4590 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4592 if (fragP
->tc_frag_data
.is_loop_target
)
4594 if (fragP
->fr_fix
!= 0)
4602 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4604 const fragS
*next_fragp
= fragp
->fr_next
;
4605 xtensa_opcode next_opcode
;
4607 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4610 /* Sometimes an empty will end up here due to storage allocation issues,
4611 so we have to skip until we find something legit. */
4612 while (next_fragp
->fr_fix
== 0)
4613 next_fragp
= next_fragp
->fr_next
;
4615 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4618 /* There is some implicit knowledge encoded in here.
4619 The LOOP instructions that are NOT RELAX_IMMED have
4620 been relaxed. Note that we can assume that the LOOP
4621 instruction is in slot 0 because loops aren't bundleable. */
4622 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4623 return get_expanded_loop_offset (next_opcode
);
4629 /* Mark a location where we can later insert literal frags. Update
4630 the section's literal_pool_loc, so subsequent literals can be
4631 placed nearest to their use. */
4634 xtensa_mark_literal_pool_location (void)
4636 /* Any labels pointing to the current location need
4637 to be adjusted to after the literal pool. */
4639 fragS
*pool_location
;
4641 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4644 frag_align (2, 0, 0);
4645 record_alignment (now_seg
, 2);
4647 /* We stash info in the fr_var of these frags
4648 so we can later move the literal's fixes into this
4649 frchain's fix list. We can use fr_var because fr_var's
4650 interpretation depends solely on the fr_type and subtype. */
4651 pool_location
= frag_now
;
4652 frag_variant (rs_machine_dependent
, 0, (int) frchain_now
,
4653 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4654 xtensa_set_frag_assembly_state (frag_now
);
4655 frag_variant (rs_machine_dependent
, 0, (int) now_seg
,
4656 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4657 xtensa_set_frag_assembly_state (frag_now
);
4659 /* Now put a frag into the literal pool that points to this location. */
4660 set_literal_pool_location (now_seg
, pool_location
);
4661 xtensa_switch_to_non_abs_literal_fragment (&s
);
4662 frag_align (2, 0, 0);
4663 record_alignment (now_seg
, 2);
4665 /* Close whatever frag is there. */
4666 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4667 xtensa_set_frag_assembly_state (frag_now
);
4668 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4669 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4670 xtensa_restore_emit_state (&s
);
4671 xtensa_set_frag_assembly_state (frag_now
);
4675 /* Build a nop of the correct size into tinsn. */
4678 build_nop (TInsn
*tinsn
, int size
)
4684 tinsn
->opcode
= xtensa_nop_n_opcode
;
4686 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4687 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4691 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4693 tinsn
->opcode
= xtensa_or_opcode
;
4694 set_expr_const (&tinsn
->tok
[0], 1);
4695 set_expr_const (&tinsn
->tok
[1], 1);
4696 set_expr_const (&tinsn
->tok
[2], 1);
4700 tinsn
->opcode
= xtensa_nop_opcode
;
4702 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4707 /* Assemble a NOP of the requested size in the buffer. User must have
4708 allocated "buf" with at least "size" bytes. */
4711 assemble_nop (int size
, char *buf
)
4713 static xtensa_insnbuf insnbuf
= NULL
;
4716 build_nop (&tinsn
, size
);
4719 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4721 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4722 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4723 (unsigned char *) buf
, 0);
4727 /* Return the number of bytes for the offset of the expanded loop
4728 instruction. This should be incorporated into the relaxation
4729 specification but is hard-coded here. This is used to auto-align
4730 the loop instruction. It is invalid to call this function if the
4731 configuration does not have loops or if the opcode is not a loop
4735 get_expanded_loop_offset (xtensa_opcode opcode
)
4737 /* This is the OFFSET of the loop instruction in the expanded loop.
4738 This MUST correspond directly to the specification of the loop
4739 expansion. It will be validated on fragment conversion. */
4740 assert (opcode
!= XTENSA_UNDEFINED
);
4741 if (opcode
== xtensa_loop_opcode
)
4743 if (opcode
== xtensa_loopnez_opcode
)
4745 if (opcode
== xtensa_loopgtz_opcode
)
4747 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4753 get_literal_pool_location (segT seg
)
4755 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4760 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4762 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4766 /* Set frag assembly state should be called when a new frag is
4767 opened and after a frag has been closed. */
4770 xtensa_set_frag_assembly_state (fragS
*fragP
)
4772 if (!density_supported
)
4773 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4775 /* This function is called from subsegs_finish, which is called
4776 after xtensa_end, so we can't use "use_transform" or
4777 "use_schedule" here. */
4778 if (!directive_state
[directive_transform
])
4779 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4780 if (directive_state
[directive_longcalls
])
4781 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4782 fragP
->tc_frag_data
.use_absolute_literals
=
4783 directive_state
[directive_absolute_literals
];
4784 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4789 relaxable_section (asection
*sec
)
4791 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4796 xtensa_find_unmarked_state_frags (void)
4800 /* Walk over each fragment of all of the current segments. For each
4801 unmarked fragment, mark it with the same info as the previous
4803 for (seclist
= &stdoutput
->sections
;
4804 seclist
&& *seclist
;
4805 seclist
= &(*seclist
)->next
)
4807 segT sec
= *seclist
;
4808 segment_info_type
*seginfo
;
4811 flags
= bfd_get_section_flags (stdoutput
, sec
);
4812 if (flags
& SEC_DEBUGGING
)
4814 if (!(flags
& SEC_ALLOC
))
4817 seginfo
= seg_info (sec
);
4818 if (seginfo
&& seginfo
->frchainP
)
4820 fragS
*last_fragP
= 0;
4821 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4822 fragP
= fragP
->fr_next
)
4824 if (fragP
->fr_fix
!= 0
4825 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4827 if (last_fragP
== 0)
4829 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4830 _("assembly state not set for first frag in section %s"),
4835 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4836 fragP
->tc_frag_data
.is_no_density
=
4837 last_fragP
->tc_frag_data
.is_no_density
;
4838 fragP
->tc_frag_data
.is_no_transform
=
4839 last_fragP
->tc_frag_data
.is_no_transform
;
4840 fragP
->tc_frag_data
.use_longcalls
=
4841 last_fragP
->tc_frag_data
.use_longcalls
;
4842 fragP
->tc_frag_data
.use_absolute_literals
=
4843 last_fragP
->tc_frag_data
.use_absolute_literals
;
4846 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4855 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4857 void *unused ATTRIBUTE_UNUSED
)
4859 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4860 segment_info_type
*seginfo
= seg_info (sec
);
4861 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4863 if (flags
& SEC_CODE
)
4865 xtensa_isa isa
= xtensa_default_isa
;
4866 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4867 while (frag
!= NULL
)
4869 if (frag
->tc_frag_data
.is_branch_target
)
4875 xtensa_insnbuf_from_chars
4876 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4877 fmt
= xtensa_format_decode (isa
, insnbuf
);
4878 op_size
= xtensa_format_length (isa
, fmt
);
4879 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4880 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4881 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4882 _("unaligned branch target: %d bytes at 0x%lx"),
4883 op_size
, frag
->fr_address
);
4885 frag
= frag
->fr_next
;
4887 xtensa_insnbuf_free (isa
, insnbuf
);
4893 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4895 void *unused ATTRIBUTE_UNUSED
)
4897 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4898 segment_info_type
*seginfo
= seg_info (sec
);
4899 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4900 xtensa_isa isa
= xtensa_default_isa
;
4902 if (flags
& SEC_CODE
)
4904 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4905 while (frag
!= NULL
)
4907 if (frag
->tc_frag_data
.is_first_loop_insn
)
4913 xtensa_insnbuf_from_chars
4914 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4915 fmt
= xtensa_format_decode (isa
, insnbuf
);
4916 op_size
= xtensa_format_length (isa
, fmt
);
4917 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4919 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4920 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4921 _("unaligned loop: %d bytes at 0x%lx"),
4922 op_size
, frag
->fr_address
);
4924 frag
= frag
->fr_next
;
4926 xtensa_insnbuf_free (isa
, insnbuf
);
4932 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4934 xtensa_isa isa
= xtensa_default_isa
;
4935 static xtensa_insnbuf insnbuf
= NULL
;
4936 static xtensa_insnbuf slotbuf
= NULL
;
4939 bfd_boolean alt_reloc
;
4940 xtensa_opcode opcode
;
4941 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4943 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4945 as_fatal (_("unexpected fix"));
4949 insnbuf
= xtensa_insnbuf_alloc (isa
);
4950 slotbuf
= xtensa_insnbuf_alloc (isa
);
4953 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4954 fmt
= xtensa_format_decode (isa
, insnbuf
);
4955 if (fmt
== XTENSA_UNDEFINED
)
4956 as_fatal (_("undecodable fix"));
4957 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4958 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4959 if (opcode
== XTENSA_UNDEFINED
)
4960 as_fatal (_("undecodable fix"));
4962 /* CONST16 immediates are not PC-relative, despite the fact that we
4963 reuse the normal PC-relative operand relocations for the low part
4964 of a CONST16 operand. */
4965 if (opcode
== xtensa_const16_opcode
)
4968 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4969 get_relaxable_immed (opcode
), val
,
4970 fixP
->fx_file
, fixP
->fx_line
);
4972 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4973 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4979 /* External Functions and Other GAS Hooks. */
4982 xtensa_target_format (void)
4984 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4989 xtensa_file_arch_init (bfd
*abfd
)
4991 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4996 md_number_to_chars (char *buf
, valueT val
, int n
)
4998 if (target_big_endian
)
4999 number_to_chars_bigendian (buf
, val
, n
);
5001 number_to_chars_littleendian (buf
, val
, n
);
5005 /* This function is called once, at assembler startup time. It should
5006 set up all the tables, etc. that the MD part of the assembler will
5012 segT current_section
= now_seg
;
5013 int current_subsec
= now_subseg
;
5016 xtensa_default_isa
= xtensa_isa_init (0, 0);
5017 isa
= xtensa_default_isa
;
5021 /* Set up the .literal, .fini.literal and .init.literal sections. */
5022 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5023 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
5024 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
5025 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
5026 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
5028 subseg_set (current_section
, current_subsec
);
5030 xg_init_vinsn (&cur_vinsn
);
5032 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5033 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5034 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5035 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5036 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5037 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5038 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5039 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5040 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5041 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5042 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5043 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5044 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5045 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5046 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5047 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5048 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5049 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5050 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5051 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5052 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5053 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5054 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5055 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5056 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5057 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5058 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5059 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5060 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5062 init_op_placement_info_table ();
5064 /* Set up the assembly state. */
5065 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5066 xtensa_set_frag_assembly_state (frag_now
);
5070 /* TC_INIT_FIX_DATA hook */
5073 xtensa_init_fix_data (fixS
*x
)
5075 x
->tc_fix_data
.slot
= 0;
5076 x
->tc_fix_data
.X_add_symbol
= NULL
;
5077 x
->tc_fix_data
.X_add_number
= 0;
5081 /* tc_frob_label hook */
5084 xtensa_frob_label (symbolS
*sym
)
5086 float freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5088 /* Since the label was already attached to a frag associated with the
5089 previous basic block, it now needs to be reset to the current frag. */
5090 symbol_set_frag (sym
, frag_now
);
5091 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5093 if (generating_literals
)
5094 xtensa_add_literal_sym (sym
);
5096 xtensa_add_insn_label (sym
);
5098 if (symbol_get_tc (sym
)->is_loop_target
)
5100 if ((get_last_insn_flags (now_seg
, now_subseg
)
5101 & FLAG_IS_BAD_LOOPEND
) != 0)
5102 as_bad (_("invalid last instruction for a zero-overhead loop"));
5104 xtensa_set_frag_assembly_state (frag_now
);
5105 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5106 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5108 xtensa_set_frag_assembly_state (frag_now
);
5109 xtensa_move_labels (frag_now
, 0, TRUE
);
5112 /* No target aligning in the absolute section. */
5113 if (now_seg
!= absolute_section
5114 && do_align_targets ()
5115 && !is_unaligned_label (sym
)
5116 && !generating_literals
)
5118 xtensa_set_frag_assembly_state (frag_now
);
5120 frag_var (rs_machine_dependent
,
5122 RELAX_DESIRE_ALIGN_IF_TARGET
,
5123 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5124 xtensa_set_frag_assembly_state (frag_now
);
5125 xtensa_move_labels (frag_now
, 0, TRUE
);
5128 /* We need to mark the following properties even if we aren't aligning. */
5130 /* If the label is already known to be a branch target, i.e., a
5131 forward branch, mark the frag accordingly. Backward branches
5132 are handled by xg_add_branch_and_loop_targets. */
5133 if (symbol_get_tc (sym
)->is_branch_target
)
5134 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5136 /* Loops only go forward, so they can be identified here. */
5137 if (symbol_get_tc (sym
)->is_loop_target
)
5138 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5142 /* tc_unrecognized_line hook */
5145 xtensa_unrecognized_line (int ch
)
5150 if (cur_vinsn
.inside_bundle
== 0)
5152 /* PR8110: Cannot emit line number info inside a FLIX bundle
5153 when using --gstabs. Temporarily disable debug info. */
5154 generate_lineno_debug ();
5155 if (debug_type
== DEBUG_STABS
)
5157 xt_saved_debug_type
= debug_type
;
5158 debug_type
= DEBUG_NONE
;
5161 cur_vinsn
.inside_bundle
= 1;
5165 as_bad (_("extra opening brace"));
5171 if (cur_vinsn
.inside_bundle
)
5172 finish_vinsn (&cur_vinsn
);
5175 as_bad (_("extra closing brace"));
5180 as_bad (_("syntax error"));
5187 /* md_flush_pending_output hook */
5190 xtensa_flush_pending_output (void)
5192 if (cur_vinsn
.inside_bundle
)
5193 as_bad (_("missing closing brace"));
5195 /* If there is a non-zero instruction fragment, close it. */
5196 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5198 frag_wane (frag_now
);
5200 xtensa_set_frag_assembly_state (frag_now
);
5202 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5204 xtensa_clear_insn_labels ();
5208 /* We had an error while parsing an instruction. The string might look
5209 like this: "insn arg1, arg2 }". If so, we need to see the closing
5210 brace and reset some fields. Otherwise, the vinsn never gets closed
5211 and the num_slots field will grow past the end of the array of slots,
5212 and bad things happen. */
5215 error_reset_cur_vinsn (void)
5217 if (cur_vinsn
.inside_bundle
)
5219 if (*input_line_pointer
== '}'
5220 || *(input_line_pointer
- 1) == '}'
5221 || *(input_line_pointer
- 2) == '}')
5222 xg_clear_vinsn (&cur_vinsn
);
5228 md_assemble (char *str
)
5230 xtensa_isa isa
= xtensa_default_isa
;
5233 bfd_boolean has_underbar
= FALSE
;
5234 char *arg_strings
[MAX_INSN_ARGS
];
5236 TInsn orig_insn
; /* Original instruction from the input. */
5238 tinsn_init (&orig_insn
);
5240 /* Split off the opcode. */
5241 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5242 opname
= xmalloc (opnamelen
+ 1);
5243 memcpy (opname
, str
, opnamelen
);
5244 opname
[opnamelen
] = '\0';
5246 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5249 as_bad (_("syntax error"));
5253 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5256 /* Check for an underbar prefix. */
5259 has_underbar
= TRUE
;
5263 orig_insn
.insn_type
= ITYPE_INSN
;
5265 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5267 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5268 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5270 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5271 if (fmt
== XTENSA_UNDEFINED
)
5273 as_bad (_("unknown opcode or format name '%s'"), opname
);
5274 error_reset_cur_vinsn ();
5277 if (!cur_vinsn
.inside_bundle
)
5279 as_bad (_("format names only valid inside bundles"));
5280 error_reset_cur_vinsn ();
5283 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5284 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5286 cur_vinsn
.format
= fmt
;
5287 free (has_underbar
? opname
- 1 : opname
);
5288 error_reset_cur_vinsn ();
5292 /* Parse the arguments. */
5293 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5295 as_bad (_("syntax error"));
5296 error_reset_cur_vinsn ();
5300 /* Free the opcode and argument strings, now that they've been parsed. */
5301 free (has_underbar
? opname
- 1 : opname
);
5303 while (num_args
-- > 0)
5304 free (arg_strings
[num_args
]);
5306 /* Get expressions for invisible operands. */
5307 if (get_invisible_operands (&orig_insn
))
5309 error_reset_cur_vinsn ();
5313 /* Check for the right number and type of arguments. */
5314 if (tinsn_check_arguments (&orig_insn
))
5316 error_reset_cur_vinsn ();
5320 dwarf2_where (&orig_insn
.loc
);
5322 xg_add_branch_and_loop_targets (&orig_insn
);
5324 /* Special-case for "entry" instruction. */
5325 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5327 /* Check that the third opcode (#2) is >= 16. */
5328 if (orig_insn
.ntok
>= 3)
5330 expressionS
*exp
= &orig_insn
.tok
[2];
5334 if (exp
->X_add_number
< 16)
5335 as_warn (_("entry instruction with stack decrement < 16"));
5339 as_warn (_("entry instruction with non-constant decrement"));
5345 assemble_tokens (opcode, tok, ntok);
5346 expand the tokens from the orig_insn into the
5347 stack of instructions that will not expand
5348 unless required at relaxation time. */
5350 if (!cur_vinsn
.inside_bundle
)
5351 emit_single_op (&orig_insn
);
5352 else /* We are inside a bundle. */
5354 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5355 cur_vinsn
.num_slots
++;
5356 if (*input_line_pointer
== '}'
5357 || *(input_line_pointer
- 1) == '}'
5358 || *(input_line_pointer
- 2) == '}')
5359 finish_vinsn (&cur_vinsn
);
5362 /* We've just emitted a new instruction so clear the list of labels. */
5363 xtensa_clear_insn_labels ();
5367 /* HANDLE_ALIGN hook */
5369 /* For a .align directive, we mark the previous block with the alignment
5370 information. This will be placed in the object file in the
5371 property section corresponding to this section. */
5374 xtensa_handle_align (fragS
*fragP
)
5377 && ! fragP
->tc_frag_data
.is_literal
5378 && (fragP
->fr_type
== rs_align
5379 || fragP
->fr_type
== rs_align_code
)
5380 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5381 && fragP
->fr_offset
> 0
5382 && now_seg
!= bss_section
)
5384 fragP
->tc_frag_data
.is_align
= TRUE
;
5385 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5388 if (fragP
->fr_type
== rs_align_test
)
5391 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5393 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5394 _("unaligned entry instruction"));
5399 /* TC_FRAG_INIT hook */
5402 xtensa_frag_init (fragS
*frag
)
5404 xtensa_set_frag_assembly_state (frag
);
5409 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5415 /* Round up a section size to the appropriate boundary. */
5418 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5420 return size
; /* Byte alignment is fine. */
5425 md_pcrel_from (fixS
*fixP
)
5428 static xtensa_insnbuf insnbuf
= NULL
;
5429 static xtensa_insnbuf slotbuf
= NULL
;
5432 xtensa_opcode opcode
;
5435 xtensa_isa isa
= xtensa_default_isa
;
5436 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5437 bfd_boolean alt_reloc
;
5439 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5444 insnbuf
= xtensa_insnbuf_alloc (isa
);
5445 slotbuf
= xtensa_insnbuf_alloc (isa
);
5448 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5449 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5450 fmt
= xtensa_format_decode (isa
, insnbuf
);
5452 if (fmt
== XTENSA_UNDEFINED
)
5453 as_fatal (_("bad instruction format"));
5455 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5456 as_fatal (_("invalid relocation"));
5458 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5459 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5461 /* Check for "alternate" relocations (operand not specified). None
5462 of the current uses for these are really PC-relative. */
5463 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5465 if (opcode
!= xtensa_l32r_opcode
5466 && opcode
!= xtensa_const16_opcode
)
5467 as_fatal (_("invalid relocation for '%s' instruction"),
5468 xtensa_opcode_name (isa
, opcode
));
5472 opnum
= get_relaxable_immed (opcode
);
5474 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5475 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5477 as_bad_where (fixP
->fx_file
,
5479 _("invalid relocation for operand %d of '%s'"),
5480 opnum
, xtensa_opcode_name (isa
, opcode
));
5483 return 0 - opnd_value
;
5487 /* TC_FORCE_RELOCATION hook */
5490 xtensa_force_relocation (fixS
*fix
)
5492 switch (fix
->fx_r_type
)
5494 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5495 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5496 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5497 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5498 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5499 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5500 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5501 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5502 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5503 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5504 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5505 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5506 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5507 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5508 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5509 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5515 if (linkrelax
&& fix
->fx_addsy
5516 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5519 return generic_force_reloc (fix
);
5523 /* TC_VALIDATE_FIX_SUB hook */
5526 xtensa_validate_fix_sub (fixS
*fix
)
5528 segT add_symbol_segment
, sub_symbol_segment
;
5530 /* The difference of two symbols should be resolved by the assembler when
5531 linkrelax is not set. If the linker may relax the section containing
5532 the symbols, then an Xtensa DIFF relocation must be generated so that
5533 the linker knows to adjust the difference value. */
5534 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5537 /* Make sure both symbols are in the same segment, and that segment is
5538 "normal" and relaxable. If the segment is not "normal", then the
5539 fix is not valid. If the segment is not "relaxable", then the fix
5540 should have been handled earlier. */
5541 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5542 if (! SEG_NORMAL (add_symbol_segment
) ||
5543 ! relaxable_section (add_symbol_segment
))
5545 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5546 return (sub_symbol_segment
== add_symbol_segment
);
5550 /* NO_PSEUDO_DOT hook */
5552 /* This function has nothing to do with pseudo dots, but this is the
5553 nearest macro to where the check needs to take place. FIXME: This
5557 xtensa_check_inside_bundle (void)
5559 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5560 as_bad (_("directives are not valid inside bundles"));
5562 /* This function must always return FALSE because it is called via a
5563 macro that has nothing to do with bundling. */
5568 /* md_elf_section_change_hook */
5571 xtensa_elf_section_change_hook (void)
5573 /* Set up the assembly state. */
5574 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5575 xtensa_set_frag_assembly_state (frag_now
);
5579 /* tc_fix_adjustable hook */
5582 xtensa_fix_adjustable (fixS
*fixP
)
5584 /* An offset is not allowed in combination with the difference of two
5585 symbols, but that cannot be easily detected after a local symbol
5586 has been adjusted to a (section+offset) form. Return 0 so that such
5587 an fix will not be adjusted. */
5588 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5589 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5592 /* We need the symbol name for the VTABLE entries. */
5593 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5594 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5602 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg
)
5604 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5607 switch (fixP
->fx_r_type
)
5612 if (linkrelax
&& fixP
->fx_subsy
)
5614 switch (fixP
->fx_r_type
)
5617 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5620 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5623 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5629 /* An offset is only allowed when it results from adjusting a
5630 local symbol into a section-relative offset. If the offset
5631 came from the original expression, tc_fix_adjustable will have
5632 prevented the fix from being converted to a section-relative
5633 form so that we can flag the error here. */
5634 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5636 _("cannot represent subtraction with an offset"));
5638 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5639 - S_GET_VALUE (fixP
->fx_subsy
));
5641 /* The difference value gets written out, and the DIFF reloc
5642 identifies the address of the subtracted symbol (i.e., the one
5643 with the lowest address). */
5645 fixP
->fx_offset
-= val
;
5646 fixP
->fx_subsy
= NULL
;
5648 else if (! fixP
->fx_addsy
)
5655 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5656 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5659 case BFD_RELOC_XTENSA_SLOT0_OP
:
5660 case BFD_RELOC_XTENSA_SLOT1_OP
:
5661 case BFD_RELOC_XTENSA_SLOT2_OP
:
5662 case BFD_RELOC_XTENSA_SLOT3_OP
:
5663 case BFD_RELOC_XTENSA_SLOT4_OP
:
5664 case BFD_RELOC_XTENSA_SLOT5_OP
:
5665 case BFD_RELOC_XTENSA_SLOT6_OP
:
5666 case BFD_RELOC_XTENSA_SLOT7_OP
:
5667 case BFD_RELOC_XTENSA_SLOT8_OP
:
5668 case BFD_RELOC_XTENSA_SLOT9_OP
:
5669 case BFD_RELOC_XTENSA_SLOT10_OP
:
5670 case BFD_RELOC_XTENSA_SLOT11_OP
:
5671 case BFD_RELOC_XTENSA_SLOT12_OP
:
5672 case BFD_RELOC_XTENSA_SLOT13_OP
:
5673 case BFD_RELOC_XTENSA_SLOT14_OP
:
5676 /* Write the tentative value of a PC-relative relocation to a
5677 local symbol into the instruction. The value will be ignored
5678 by the linker, and it makes the object file disassembly
5679 readable when all branch targets are encoded in relocations. */
5681 assert (fixP
->fx_addsy
);
5682 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5683 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5685 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5686 - md_pcrel_from (fixP
));
5687 (void) xg_apply_fix_value (fixP
, val
);
5690 else if (! fixP
->fx_addsy
)
5693 if (xg_apply_fix_value (fixP
, val
))
5698 case BFD_RELOC_XTENSA_PLT
:
5699 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5700 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5701 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5702 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5703 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5704 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5705 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5706 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5707 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5708 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5709 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5710 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5711 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5712 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5713 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5714 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5715 /* These all need to be resolved at link-time. Do nothing now. */
5718 case BFD_RELOC_VTABLE_INHERIT
:
5719 case BFD_RELOC_VTABLE_ENTRY
:
5724 as_bad (_("unhandled local relocation fix %s"),
5725 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5731 md_atof (int type
, char *litP
, int *sizeP
)
5734 LITTLENUM_TYPE words
[4];
5750 return "bad call to md_atof";
5753 t
= atof_ieee (input_line_pointer
, type
, words
);
5755 input_line_pointer
= t
;
5759 for (i
= prec
- 1; i
>= 0; i
--)
5762 if (target_big_endian
)
5763 idx
= (prec
- 1 - i
);
5765 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5774 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5776 return total_frag_text_expansion (fragP
);
5780 /* Translate internal representation of relocation info to BFD target
5784 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5788 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5789 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5790 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5791 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5793 /* Make sure none of our internal relocations make it this far.
5794 They'd better have been fully resolved by this point. */
5795 assert ((int) fixp
->fx_r_type
> 0);
5797 reloc
->addend
= fixp
->fx_offset
;
5799 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5800 if (reloc
->howto
== NULL
)
5802 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5803 _("cannot represent `%s' relocation in object file"),
5804 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5805 free (reloc
->sym_ptr_ptr
);
5810 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5811 as_fatal (_("internal error? cannot generate `%s' relocation"),
5812 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5818 /* Checks for resource conflicts between instructions. */
5820 /* The func unit stuff could be implemented as bit-vectors rather
5821 than the iterative approach here. If it ends up being too
5822 slow, we will switch it. */
5825 new_resource_table (void *data
,
5828 unit_num_copies_func uncf
,
5829 opcode_num_units_func onuf
,
5830 opcode_funcUnit_use_unit_func ouuf
,
5831 opcode_funcUnit_use_stage_func ousf
)
5834 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5836 rt
->cycles
= cycles
;
5837 rt
->allocated_cycles
= cycles
;
5839 rt
->unit_num_copies
= uncf
;
5840 rt
->opcode_num_units
= onuf
;
5841 rt
->opcode_unit_use
= ouuf
;
5842 rt
->opcode_unit_stage
= ousf
;
5844 rt
->units
= (char **) xcalloc (cycles
, sizeof (char *));
5845 for (i
= 0; i
< cycles
; i
++)
5846 rt
->units
[i
] = (char *) xcalloc (nu
, sizeof (char));
5853 clear_resource_table (resource_table
*rt
)
5856 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5857 for (j
= 0; j
< rt
->num_units
; j
++)
5858 rt
->units
[i
][j
] = 0;
5862 /* We never shrink it, just fake it into thinking so. */
5865 resize_resource_table (resource_table
*rt
, int cycles
)
5869 rt
->cycles
= cycles
;
5870 if (cycles
<= rt
->allocated_cycles
)
5873 old_cycles
= rt
->allocated_cycles
;
5874 rt
->allocated_cycles
= cycles
;
5876 rt
->units
= xrealloc (rt
->units
, sizeof (char *) * rt
->allocated_cycles
);
5877 for (i
= 0; i
< old_cycles
; i
++)
5878 rt
->units
[i
] = xrealloc (rt
->units
[i
], sizeof (char) * rt
->num_units
);
5879 for (i
= old_cycles
; i
< cycles
; i
++)
5880 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (char));
5885 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5888 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5890 for (i
= 0; i
< uses
; i
++)
5892 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5893 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5894 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5895 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5896 if (copies_in_use
>= copies
)
5904 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5907 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5909 for (i
= 0; i
< uses
; i
++)
5911 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5912 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5913 /* Note that this allows resources to be oversubscribed. That's
5914 essential to the way the optional scheduler works.
5915 resources_available reports when a resource is over-subscribed,
5916 so it's easy to tell. */
5917 rt
->units
[stage
+ cycle
][unit
]++;
5923 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5926 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5928 for (i
= 0; i
< uses
; i
++)
5930 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5931 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5932 rt
->units
[stage
+ cycle
][unit
]--;
5933 assert (rt
->units
[stage
+ cycle
][unit
] >= 0);
5938 /* Wrapper functions make parameterized resource reservation
5942 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5944 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5950 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5952 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5957 /* Note that this function does not check issue constraints, but
5958 solely whether the hardware is available to execute the given
5959 instructions together. It also doesn't check if the tinsns
5960 write the same state, or access the same tieports. That is
5961 checked by check_t1_t2_reads_and_writes. */
5964 resources_conflict (vliw_insn
*vinsn
)
5967 static resource_table
*rt
= NULL
;
5969 /* This is the most common case by far. Optimize it. */
5970 if (vinsn
->num_slots
== 1)
5975 xtensa_isa isa
= xtensa_default_isa
;
5976 rt
= new_resource_table
5977 (isa
, xtensa_isa_num_pipe_stages (isa
),
5978 xtensa_isa_num_funcUnits (isa
),
5979 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5980 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5981 opcode_funcUnit_use_unit
,
5982 opcode_funcUnit_use_stage
);
5985 clear_resource_table (rt
);
5987 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5989 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5991 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5998 /* finish_vinsn, emit_single_op and helper functions. */
6000 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6001 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6002 static void bundle_single_op (TInsn
*);
6003 static void xg_assemble_vliw_tokens (vliw_insn
*);
6006 /* We have reached the end of a bundle; emit into the frag. */
6009 finish_vinsn (vliw_insn
*vinsn
)
6016 if (find_vinsn_conflicts (vinsn
))
6018 xg_clear_vinsn (vinsn
);
6022 /* First, find a format that works. */
6023 if (vinsn
->format
== XTENSA_UNDEFINED
)
6024 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6026 if (vinsn
->format
== XTENSA_UNDEFINED
)
6028 as_where (&file_name
, &line
);
6029 as_bad_where (file_name
, line
,
6030 _("couldn't find a valid instruction format"));
6031 fprintf (stderr
, _(" ops were: "));
6032 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6033 fprintf (stderr
, _(" %s;"),
6034 xtensa_opcode_name (xtensa_default_isa
,
6035 vinsn
->slots
[i
].opcode
));
6036 fprintf (stderr
, _("\n"));
6037 xg_clear_vinsn (vinsn
);
6041 if (vinsn
->num_slots
6042 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6044 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6045 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6046 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6048 xg_clear_vinsn (vinsn
);
6052 if (resources_conflict (vinsn
))
6054 as_where (&file_name
, &line
);
6055 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6056 fprintf (stderr
, " ops were: ");
6057 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6058 fprintf (stderr
, " %s;",
6059 xtensa_opcode_name (xtensa_default_isa
,
6060 vinsn
->slots
[i
].opcode
));
6061 fprintf (stderr
, "\n");
6062 xg_clear_vinsn (vinsn
);
6066 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6068 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6070 symbolS
*lit_sym
= NULL
;
6072 bfd_boolean e
= FALSE
;
6073 bfd_boolean saved_density
= density_supported
;
6075 /* We don't want to narrow ops inside multi-slot bundles. */
6076 if (vinsn
->num_slots
> 1)
6077 density_supported
= FALSE
;
6079 istack_init (&slotstack
);
6080 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6082 vinsn
->slots
[i
].opcode
=
6083 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6085 vinsn
->slots
[i
].ntok
= 0;
6088 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6094 density_supported
= saved_density
;
6098 xg_clear_vinsn (vinsn
);
6102 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6104 TInsn
*insn
= &slotstack
.insn
[j
];
6105 if (insn
->insn_type
== ITYPE_LITERAL
)
6107 assert (lit_sym
== NULL
);
6108 lit_sym
= xg_assemble_literal (insn
);
6112 assert (insn
->insn_type
== ITYPE_INSN
);
6114 xg_resolve_literals (insn
, lit_sym
);
6115 if (j
!= slotstack
.ninsn
- 1)
6116 emit_single_op (insn
);
6120 if (vinsn
->num_slots
> 1)
6122 if (opcode_fits_format_slot
6123 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6126 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6130 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6131 if (vinsn
->format
== XTENSA_UNDEFINED
)
6132 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6134 vinsn
->slots
[i
].opcode
6135 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6138 vinsn
->slots
[i
].ntok
= 0;
6143 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6144 vinsn
->format
= XTENSA_UNDEFINED
;
6149 /* Now check resource conflicts on the modified bundle. */
6150 if (resources_conflict (vinsn
))
6152 as_where (&file_name
, &line
);
6153 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6154 fprintf (stderr
, " ops were: ");
6155 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6156 fprintf (stderr
, " %s;",
6157 xtensa_opcode_name (xtensa_default_isa
,
6158 vinsn
->slots
[i
].opcode
));
6159 fprintf (stderr
, "\n");
6160 xg_clear_vinsn (vinsn
);
6164 /* First, find a format that works. */
6165 if (vinsn
->format
== XTENSA_UNDEFINED
)
6166 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6168 xg_assemble_vliw_tokens (vinsn
);
6170 xg_clear_vinsn (vinsn
);
6174 /* Given an vliw instruction, what conflicts are there in register
6175 usage and in writes to states and queues?
6177 This function does two things:
6178 1. Reports an error when a vinsn contains illegal combinations
6179 of writes to registers states or queues.
6180 2. Marks individual tinsns as not relaxable if the combination
6181 contains antidependencies.
6183 Job 2 handles things like swap semantics in instructions that need
6184 to be relaxed. For example,
6188 normally would be relaxed to
6193 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6195 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6197 then we can't relax it into
6200 { add a0, a1, a0 ; add a2, a0, a4 ; }
6202 because the value of a0 is trashed before the second add can read it. */
6204 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6207 find_vinsn_conflicts (vliw_insn
*vinsn
)
6211 xtensa_isa isa
= xtensa_default_isa
;
6213 assert (!past_xtensa_end
);
6215 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6217 TInsn
*op1
= &vinsn
->slots
[i
];
6218 if (op1
->is_specific_opcode
)
6219 op1
->keep_wide
= TRUE
;
6221 op1
->keep_wide
= FALSE
;
6224 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6226 TInsn
*op1
= &vinsn
->slots
[i
];
6228 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6231 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6235 TInsn
*op2
= &vinsn
->slots
[j
];
6236 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6237 switch (conflict_type
)
6240 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6241 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6242 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6245 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6246 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6247 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6250 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6251 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6252 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6255 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6256 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6257 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6260 /* Everything is OK. */
6263 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6264 || conflict_type
== 'a');
6271 as_bad (_("multiple branches or jumps in the same bundle"));
6279 /* Check how the state used by t1 and t2 relate.
6282 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6283 case B: no relationship between what is read and written (both could
6284 read the same reg though)
6285 case C: t1 writes a register t2 writes (a register conflict within a
6287 case D: t1 writes a state that t2 also writes
6288 case E: t1 writes a tie queue that t2 also writes
6289 case F: two volatile queue accesses
6293 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6295 xtensa_isa isa
= xtensa_default_isa
;
6296 xtensa_regfile t1_regfile
, t2_regfile
;
6298 int t1_base_reg
, t1_last_reg
;
6299 int t2_base_reg
, t2_last_reg
;
6300 char t1_inout
, t2_inout
;
6302 char conflict
= 'b';
6307 bfd_boolean t1_volatile
= FALSE
;
6308 bfd_boolean t2_volatile
= FALSE
;
6310 /* Check registers. */
6311 for (j
= 0; j
< t2
->ntok
; j
++)
6313 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6316 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6317 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6318 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6320 for (i
= 0; i
< t1
->ntok
; i
++)
6322 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6325 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6327 if (t1_regfile
!= t2_regfile
)
6330 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6331 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6333 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6334 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6336 if (t1_inout
== 'm' || t1_inout
== 'o'
6337 || t2_inout
== 'm' || t2_inout
== 'o')
6344 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6345 t1_last_reg
= (t1_base_reg
6346 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6348 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6350 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6352 if (t1_reg
!= t2_reg
)
6355 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6361 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6367 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6375 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6376 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6377 for (j
= 0; j
< t2_states
; j
++)
6379 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6380 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6381 for (i
= 0; i
< t1_states
; i
++)
6383 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6384 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6388 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6394 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6400 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6405 /* Check tieports. */
6406 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6407 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6408 for (j
= 0; j
< t2_interfaces
; j
++)
6410 xtensa_interface t2_int
6411 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6412 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6414 t2_inout
= xtensa_interface_inout (isa
, j
);
6415 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6418 for (i
= 0; i
< t1_interfaces
; i
++)
6420 xtensa_interface t1_int
6421 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6422 int t1_class
= xtensa_interface_class_id (isa
, t2_int
);
6424 t1_inout
= xtensa_interface_inout (isa
, i
);
6425 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6428 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6431 if (t1_int
!= t2_int
)
6434 if (t2_inout
== 'i' && t1_inout
== 'o')
6440 if (t1_inout
== 'i' && t2_inout
== 'o')
6446 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6455 static xtensa_format
6456 xg_find_narrowest_format (vliw_insn
*vinsn
)
6458 /* Right now we assume that the ops within the vinsn are properly
6459 ordered for the slots that the programmer wanted them in. In
6460 other words, we don't rearrange the ops in hopes of finding a
6461 better format. The scheduler handles that. */
6463 xtensa_isa isa
= xtensa_default_isa
;
6464 xtensa_format format
;
6465 vliw_insn v_copy
= *vinsn
;
6466 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6468 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6471 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6475 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6477 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6479 v_copy
.slots
[slot
].opcode
=
6480 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6481 v_copy
.slots
[slot
].ntok
= 0;
6484 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6487 else if (v_copy
.num_slots
> 1)
6490 /* Try the widened version. */
6491 if (!v_copy
.slots
[slot
].keep_wide
6492 && !v_copy
.slots
[slot
].is_specific_opcode
6493 && xg_is_narrow_insn (&v_copy
.slots
[slot
])
6494 && !xg_expand_narrow (&widened
, &v_copy
.slots
[slot
])
6495 && opcode_fits_format_slot (widened
.opcode
,
6498 /* The xg_is_narrow clause requires some explanation:
6500 addi can be "widened" to an addmi, which is then
6501 expanded to an addmi/addi pair if the immediate
6502 requires it, but here we must have a single widen
6505 xg_is_narrow tells us that addi isn't really
6506 narrow. The widen_spec_list says that there are
6509 v_copy
.slots
[slot
] = widened
;
6514 if (fit
== v_copy
.num_slots
)
6517 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6518 vinsn
->format
= format
;
6524 if (format
== xtensa_isa_num_formats (isa
))
6525 return XTENSA_UNDEFINED
;
6531 /* Return the additional space needed in a frag
6532 for possible relaxations of any ops in a VLIW insn.
6533 Also fill out the relaxations that might be required of
6534 each tinsn in the vinsn. */
6537 relaxation_requirements (vliw_insn
*vinsn
)
6539 int extra_space
= 0;
6542 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6544 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6545 if (!tinsn_has_symbolic_operands (tinsn
))
6547 /* A narrow instruction could be widened later to help
6548 alignment issues. */
6549 if (xg_is_narrow_insn (tinsn
)
6550 && !tinsn
->is_specific_opcode
6551 && vinsn
->num_slots
== 1)
6553 /* Difference in bytes between narrow and wide insns... */
6555 tinsn
->subtype
= RELAX_NARROW
;
6556 tinsn
->record_fix
= TRUE
;
6561 tinsn
->record_fix
= FALSE
;
6562 /* No extra_space needed. */
6567 if (workaround_b_j_loop_end
6568 && tinsn
->opcode
== xtensa_jx_opcode
6569 && use_transform ())
6571 /* Add 2 of these. */
6572 extra_space
+= 3; /* for the nop size */
6573 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6576 /* Need to assemble it with space for the relocation. */
6577 if (xg_is_relaxable_insn (tinsn
, 0)
6578 && !tinsn
->is_specific_opcode
)
6580 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6581 int max_literal_size
=
6582 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6584 tinsn
->literal_space
= max_literal_size
;
6586 tinsn
->subtype
= RELAX_IMMED
;
6587 tinsn
->record_fix
= FALSE
;
6588 extra_space
+= max_size
;
6592 tinsn
->record_fix
= TRUE
;
6593 /* No extra space needed. */
6602 bundle_single_op (TInsn
*orig_insn
)
6604 xtensa_isa isa
= xtensa_default_isa
;
6609 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6610 assert (v
.format
!= XTENSA_UNDEFINED
);
6611 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6614 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6617 v
.slots
[slot
].opcode
=
6618 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6619 v
.slots
[slot
].ntok
= 0;
6620 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6623 v
.slots
[slot
] = *orig_insn
;
6626 for ( ; slot
< v
.num_slots
; slot
++)
6628 v
.slots
[slot
].opcode
=
6629 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6630 v
.slots
[slot
].ntok
= 0;
6631 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6640 emit_single_op (TInsn
*orig_insn
)
6643 IStack istack
; /* put instructions into here */
6644 symbolS
*lit_sym
= NULL
;
6645 symbolS
*label_sym
= NULL
;
6647 istack_init (&istack
);
6649 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6650 Because the scheduling and bundling characteristics of movi and
6651 l32r or const16 are so different, we can do much better if we relax
6652 it prior to scheduling and bundling, rather than after. */
6653 if ((orig_insn
->opcode
== xtensa_movi_opcode
6654 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6655 && !cur_vinsn
.inside_bundle
6656 && (orig_insn
->tok
[1].X_op
== O_symbol
6657 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6658 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6660 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6663 for (i
= 0; i
< istack
.ninsn
; i
++)
6665 TInsn
*insn
= &istack
.insn
[i
];
6666 switch (insn
->insn_type
)
6669 assert (lit_sym
== NULL
);
6670 lit_sym
= xg_assemble_literal (insn
);
6674 static int relaxed_sym_idx
= 0;
6675 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6676 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6678 assert (label_sym
== NULL
);
6679 label_sym
= symbol_find_or_make (label
);
6686 xg_resolve_literals (insn
, lit_sym
);
6688 xg_resolve_labels (insn
, label_sym
);
6689 bundle_single_op (insn
);
6701 total_frag_text_expansion (fragS
*fragP
)
6704 int total_expansion
= 0;
6706 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6707 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6709 return total_expansion
;
6713 /* Emit a vliw instruction to the current fragment. */
6716 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6718 bfd_boolean finish_frag
= FALSE
;
6719 bfd_boolean is_jump
= FALSE
;
6720 bfd_boolean is_branch
= FALSE
;
6721 xtensa_isa isa
= xtensa_default_isa
;
6727 struct dwarf2_line_info best_loc
;
6729 best_loc
.line
= INT_MAX
;
6731 if (generating_literals
)
6733 static int reported
= 0;
6735 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6736 _("cannot assemble into a literal fragment"));
6743 if (frag_now_fix () != 0
6744 && (! frag_now
->tc_frag_data
.is_insn
6745 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6746 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6747 || (directive_state
[directive_longcalls
]
6748 != frag_now
->tc_frag_data
.use_longcalls
)
6749 || (directive_state
[directive_absolute_literals
]
6750 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6752 frag_wane (frag_now
);
6754 xtensa_set_frag_assembly_state (frag_now
);
6757 if (workaround_a0_b_retw
6758 && vinsn
->num_slots
== 1
6759 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6760 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6761 && use_transform ())
6763 has_a0_b_retw
= TRUE
;
6765 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6766 After the first assembly pass we will check all of them and
6767 add a nop if needed. */
6768 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6769 frag_var (rs_machine_dependent
, 4, 4,
6770 RELAX_ADD_NOP_IF_A0_B_RETW
,
6771 frag_now
->fr_symbol
,
6772 frag_now
->fr_offset
,
6774 xtensa_set_frag_assembly_state (frag_now
);
6775 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6776 frag_var (rs_machine_dependent
, 4, 4,
6777 RELAX_ADD_NOP_IF_A0_B_RETW
,
6778 frag_now
->fr_symbol
,
6779 frag_now
->fr_offset
,
6781 xtensa_set_frag_assembly_state (frag_now
);
6784 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6786 /* See if the instruction implies an aligned section. */
6787 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6788 record_alignment (now_seg
, 2);
6790 /* Also determine the best line number for debug info. */
6791 best_loc
= vinsn
->slots
[i
].loc
.line
< best_loc
.line
6792 ? vinsn
->slots
[i
].loc
: best_loc
;
6795 /* Special cases for instructions that force an alignment... */
6796 /* None of these opcodes are bundle-able. */
6797 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6801 xtensa_set_frag_assembly_state (frag_now
);
6802 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6804 max_fill
= get_text_align_max_fill_size
6805 (get_text_align_power (xtensa_fetch_width
),
6806 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6808 if (use_transform ())
6809 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6810 RELAX_ALIGN_NEXT_OPCODE
,
6811 frag_now
->fr_symbol
,
6812 frag_now
->fr_offset
,
6815 frag_var (rs_machine_dependent
, 0, 0,
6816 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6817 xtensa_set_frag_assembly_state (frag_now
);
6819 xtensa_move_labels (frag_now
, 0, FALSE
);
6822 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6823 && !vinsn
->slots
[0].is_specific_opcode
)
6825 xtensa_mark_literal_pool_location ();
6826 xtensa_move_labels (frag_now
, 0, TRUE
);
6827 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6830 if (vinsn
->num_slots
== 1)
6832 if (workaround_a0_b_retw
&& use_transform ())
6833 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6834 is_register_writer (&vinsn
->slots
[0], "a", 0));
6836 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6837 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6840 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6842 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6844 extra_space
= relaxation_requirements (vinsn
);
6846 /* vinsn_to_insnbuf will produce the error. */
6847 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6849 f
= frag_more (insn_size
+ extra_space
);
6850 xtensa_set_frag_assembly_state (frag_now
);
6851 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6854 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6855 if (vinsn
->format
== XTENSA_UNDEFINED
)
6858 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6860 xtensa_dwarf2_emit_insn (insn_size
- extra_space
, &best_loc
);
6862 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6864 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6865 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6866 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6867 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6868 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6869 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6870 if (tinsn
->literal_space
!= 0)
6871 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6873 if (tinsn
->subtype
== RELAX_NARROW
)
6874 assert (vinsn
->num_slots
== 1);
6875 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6877 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6880 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6881 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6885 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6886 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6890 frag_variant (rs_machine_dependent
,
6891 extra_space
, extra_space
, RELAX_SLOTS
,
6892 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6893 xtensa_set_frag_assembly_state (frag_now
);
6896 /* Special cases for loops:
6897 close_loop_end should be inserted AFTER short_loop.
6898 Make sure that CLOSE loops are processed BEFORE short_loops
6899 when converting them. */
6901 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6902 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6903 && !vinsn
->slots
[0].is_specific_opcode
)
6905 if (workaround_short_loop
&& use_transform ())
6907 maybe_has_short_loop
= TRUE
;
6908 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6909 frag_var (rs_machine_dependent
, 4, 4,
6910 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6911 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6912 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6913 frag_var (rs_machine_dependent
, 4, 4,
6914 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6915 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6918 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6919 loop at least 12 bytes away from another loop's end. */
6920 if (workaround_close_loop_end
&& use_transform ())
6922 maybe_has_close_loop_end
= TRUE
;
6923 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6924 frag_var (rs_machine_dependent
, 12, 12,
6925 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6926 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6930 if (use_transform ())
6934 assert (finish_frag
);
6935 frag_var (rs_machine_dependent
,
6936 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6938 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6939 xtensa_set_frag_assembly_state (frag_now
);
6941 else if (is_branch
&& do_align_targets ())
6943 assert (finish_frag
);
6944 frag_var (rs_machine_dependent
,
6945 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6946 RELAX_MAYBE_UNREACHABLE
,
6947 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6948 xtensa_set_frag_assembly_state (frag_now
);
6949 frag_var (rs_machine_dependent
,
6951 RELAX_MAYBE_DESIRE_ALIGN
,
6952 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6953 xtensa_set_frag_assembly_state (frag_now
);
6957 /* Now, if the original opcode was a call... */
6958 if (do_align_targets ()
6959 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6961 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6962 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6963 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6964 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6965 xtensa_set_frag_assembly_state (frag_now
);
6968 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6970 frag_wane (frag_now
);
6972 xtensa_set_frag_assembly_state (frag_now
);
6977 /* xtensa_end and helper functions. */
6979 static void xtensa_cleanup_align_frags (void);
6980 static void xtensa_fix_target_frags (void);
6981 static void xtensa_mark_narrow_branches (void);
6982 static void xtensa_mark_zcl_first_insns (void);
6983 static void xtensa_fix_a0_b_retw_frags (void);
6984 static void xtensa_fix_b_j_loop_end_frags (void);
6985 static void xtensa_fix_close_loop_end_frags (void);
6986 static void xtensa_fix_short_loop_frags (void);
6987 static void xtensa_sanity_check (void);
6992 directive_balance ();
6993 xtensa_flush_pending_output ();
6995 past_xtensa_end
= TRUE
;
6997 xtensa_move_literals ();
6999 xtensa_reorder_segments ();
7000 xtensa_cleanup_align_frags ();
7001 xtensa_fix_target_frags ();
7002 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7003 xtensa_fix_a0_b_retw_frags ();
7004 if (workaround_b_j_loop_end
)
7005 xtensa_fix_b_j_loop_end_frags ();
7007 /* "close_loop_end" should be processed BEFORE "short_loop". */
7008 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7009 xtensa_fix_close_loop_end_frags ();
7011 if (workaround_short_loop
&& maybe_has_short_loop
)
7012 xtensa_fix_short_loop_frags ();
7013 xtensa_mark_narrow_branches ();
7014 xtensa_mark_zcl_first_insns ();
7016 xtensa_sanity_check ();
7021 xtensa_cleanup_align_frags (void)
7025 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7028 /* Walk over all of the fragments in a subsection. */
7029 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7031 if ((fragP
->fr_type
== rs_align
7032 || fragP
->fr_type
== rs_align_code
7033 || (fragP
->fr_type
== rs_machine_dependent
7034 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7035 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7036 && fragP
->fr_fix
== 0)
7038 fragS
*next
= fragP
->fr_next
;
7041 && next
->fr_fix
== 0
7042 && next
->fr_type
== rs_machine_dependent
7043 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7046 next
= next
->fr_next
;
7049 /* If we don't widen branch targets, then they
7050 will be easier to align. */
7051 if (fragP
->tc_frag_data
.is_branch_target
7052 && fragP
->fr_opcode
== fragP
->fr_literal
7053 && fragP
->fr_type
== rs_machine_dependent
7054 && fragP
->fr_subtype
== RELAX_SLOTS
7055 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7057 if (fragP
->fr_type
== rs_machine_dependent
7058 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7059 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7065 /* Re-process all of the fragments looking to convert all of the
7066 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7067 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7068 Otherwise, convert to a .fill 0. */
7071 xtensa_fix_target_frags (void)
7075 /* When this routine is called, all of the subsections are still intact
7076 so we walk over subsections instead of sections. */
7077 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7081 /* Walk over all of the fragments in a subsection. */
7082 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7084 if (fragP
->fr_type
== rs_machine_dependent
7085 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7087 if (next_frag_is_branch_target (fragP
))
7088 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7097 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7100 xtensa_mark_narrow_branches (void)
7104 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7107 /* Walk over all of the fragments in a subsection. */
7108 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7110 if (fragP
->fr_type
== rs_machine_dependent
7111 && fragP
->fr_subtype
== RELAX_SLOTS
7112 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7115 const expressionS
*expr
;
7118 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7119 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7121 expr
= &vinsn
.slots
[0].tok
[1];
7122 symbolP
= expr
->X_add_symbol
;
7124 if (vinsn
.num_slots
== 1
7125 && xtensa_opcode_is_branch (xtensa_default_isa
,
7126 vinsn
.slots
[0].opcode
)
7127 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7128 && is_narrow_branch_guaranteed_in_range (fragP
,
7131 fragP
->fr_subtype
= RELAX_SLOTS
;
7132 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7140 /* A branch is typically widened only when its target is out of
7141 range. However, we would like to widen them to align a subsequent
7142 branch target when possible.
7144 Because the branch relaxation code is so convoluted, the optimal solution
7145 (combining the two cases) is difficult to get right in all circumstances.
7146 We therefore go with an "almost as good" solution, where we only
7147 use for alignment narrow branches that definitely will not expand to a
7148 jump and a branch. These functions find and mark these cases. */
7150 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7151 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7152 We start counting beginning with the frag after the 2-byte branch, so the
7153 maximum offset is (4 - 2) + 63 = 65. */
7154 #define MAX_IMMED6 65
7156 static offsetT
unrelaxed_frag_max_size (fragS
*);
7159 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7161 const expressionS
*expr
= &tinsn
->tok
[1];
7162 symbolS
*symbolP
= expr
->X_add_symbol
;
7163 fragS
*target_frag
= symbol_get_frag (symbolP
);
7164 offsetT max_distance
= expr
->X_add_number
;
7165 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7166 if (is_branch_jmp_to_next (tinsn
, fragP
))
7169 /* The branch doesn't branch over it's own frag,
7170 but over the subsequent ones. */
7171 fragP
= fragP
->fr_next
;
7172 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7174 max_distance
+= unrelaxed_frag_max_size (fragP
);
7175 fragP
= fragP
->fr_next
;
7177 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7184 xtensa_mark_zcl_first_insns (void)
7188 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7191 /* Walk over all of the fragments in a subsection. */
7192 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7194 if (fragP
->fr_type
== rs_machine_dependent
7195 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7196 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7198 /* Find the loop frag. */
7199 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7200 /* Find the first insn frag. */
7201 targ_frag
= next_non_empty_frag (targ_frag
);
7203 /* Of course, sometimes (mostly for toy test cases) a
7204 zero-cost loop instruction is the last in a section. */
7207 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7208 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7217 /* Re-process all of the fragments looking to convert all of the
7218 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7219 conditional branch or a retw/retw.n, convert this frag to one that
7220 will generate a NOP. In any case close it off with a .fill 0. */
7222 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7225 xtensa_fix_a0_b_retw_frags (void)
7229 /* When this routine is called, all of the subsections are still intact
7230 so we walk over subsections instead of sections. */
7231 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7235 /* Walk over all of the fragments in a subsection. */
7236 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7238 if (fragP
->fr_type
== rs_machine_dependent
7239 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7241 if (next_instrs_are_b_retw (fragP
))
7243 if (fragP
->tc_frag_data
.is_no_transform
)
7244 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7246 relax_frag_add_nop (fragP
);
7256 next_instrs_are_b_retw (fragS
*fragP
)
7258 xtensa_opcode opcode
;
7260 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7261 static xtensa_insnbuf insnbuf
= NULL
;
7262 static xtensa_insnbuf slotbuf
= NULL
;
7263 xtensa_isa isa
= xtensa_default_isa
;
7266 bfd_boolean branch_seen
= FALSE
;
7270 insnbuf
= xtensa_insnbuf_alloc (isa
);
7271 slotbuf
= xtensa_insnbuf_alloc (isa
);
7274 if (next_fragP
== NULL
)
7277 /* Check for the conditional branch. */
7278 xtensa_insnbuf_from_chars
7279 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7280 fmt
= xtensa_format_decode (isa
, insnbuf
);
7281 if (fmt
== XTENSA_UNDEFINED
)
7284 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7286 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7287 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7289 branch_seen
= (branch_seen
7290 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7296 offset
+= xtensa_format_length (isa
, fmt
);
7297 if (offset
== next_fragP
->fr_fix
)
7299 next_fragP
= next_non_empty_frag (next_fragP
);
7303 if (next_fragP
== NULL
)
7306 /* Check for the retw/retw.n. */
7307 xtensa_insnbuf_from_chars
7308 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7309 fmt
= xtensa_format_decode (isa
, insnbuf
);
7311 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7312 have no problems. */
7313 if (fmt
== XTENSA_UNDEFINED
7314 || xtensa_format_num_slots (isa
, fmt
) != 1)
7317 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7318 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7320 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7327 /* Re-process all of the fragments looking to convert all of the
7328 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7329 loop end label, convert this frag to one that will generate a NOP.
7330 In any case close it off with a .fill 0. */
7332 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7335 xtensa_fix_b_j_loop_end_frags (void)
7339 /* When this routine is called, all of the subsections are still intact
7340 so we walk over subsections instead of sections. */
7341 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7345 /* Walk over all of the fragments in a subsection. */
7346 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7348 if (fragP
->fr_type
== rs_machine_dependent
7349 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7351 if (next_instr_is_loop_end (fragP
))
7353 if (fragP
->tc_frag_data
.is_no_transform
)
7354 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7356 relax_frag_add_nop (fragP
);
7366 next_instr_is_loop_end (fragS
*fragP
)
7368 const fragS
*next_fragP
;
7370 if (next_frag_is_loop_target (fragP
))
7373 next_fragP
= next_non_empty_frag (fragP
);
7374 if (next_fragP
== NULL
)
7377 if (!next_frag_is_loop_target (next_fragP
))
7380 /* If the size is >= 3 then there is more than one instruction here.
7381 The hardware bug will not fire. */
7382 if (next_fragP
->fr_fix
> 3)
7389 /* Re-process all of the fragments looking to convert all of the
7390 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7391 not MY loop's loop end within 12 bytes, add enough nops here to
7392 make it at least 12 bytes away. In any case close it off with a
7395 static offsetT min_bytes_to_other_loop_end
7396 (fragS
*, fragS
*, offsetT
, offsetT
);
7399 xtensa_fix_close_loop_end_frags (void)
7403 /* When this routine is called, all of the subsections are still intact
7404 so we walk over subsections instead of sections. */
7405 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7409 fragS
*current_target
= NULL
;
7410 offsetT current_offset
= 0;
7412 /* Walk over all of the fragments in a subsection. */
7413 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7415 if (fragP
->fr_type
== rs_machine_dependent
7416 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7417 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7418 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7421 /* Read it. If the instruction is a loop, get the target. */
7423 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7424 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7425 t_insn
.opcode
) == 1)
7427 /* Get the current fragment target. */
7428 if (fragP
->tc_frag_data
.slot_symbols
[0])
7430 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7431 current_target
= symbol_get_frag (sym
);
7432 current_offset
= fragP
->fr_offset
;
7438 && fragP
->fr_type
== rs_machine_dependent
7439 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7442 int bytes_added
= 0;
7444 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7445 /* Max out at 12. */
7446 min_bytes
= min_bytes_to_other_loop_end
7447 (fragP
->fr_next
, current_target
, current_offset
,
7448 REQUIRED_LOOP_DIVIDING_BYTES
);
7450 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7452 if (fragP
->tc_frag_data
.is_no_transform
)
7453 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7456 while (min_bytes
+ bytes_added
7457 < REQUIRED_LOOP_DIVIDING_BYTES
)
7461 if (fragP
->fr_var
< length
)
7462 as_fatal (_("fr_var %lu < length %d"),
7463 fragP
->fr_var
, length
);
7466 assemble_nop (length
,
7467 fragP
->fr_literal
+ fragP
->fr_fix
);
7468 fragP
->fr_fix
+= length
;
7469 fragP
->fr_var
-= length
;
7471 bytes_added
+= length
;
7477 assert (fragP
->fr_type
!= rs_machine_dependent
7478 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7484 static offsetT
unrelaxed_frag_min_size (fragS
*);
7487 min_bytes_to_other_loop_end (fragS
*fragP
,
7488 fragS
*current_target
,
7489 offsetT current_offset
,
7493 fragS
*current_fragP
;
7495 for (current_fragP
= fragP
;
7497 current_fragP
= current_fragP
->fr_next
)
7499 if (current_fragP
->tc_frag_data
.is_loop_target
7500 && current_fragP
!= current_target
)
7501 return offset
+ current_offset
;
7503 offset
+= unrelaxed_frag_min_size (current_fragP
);
7505 if (offset
+ current_offset
>= max_size
)
7513 unrelaxed_frag_min_size (fragS
*fragP
)
7515 offsetT size
= fragP
->fr_fix
;
7517 /* Add fill size. */
7518 if (fragP
->fr_type
== rs_fill
)
7519 size
+= fragP
->fr_offset
;
7526 unrelaxed_frag_max_size (fragS
*fragP
)
7528 offsetT size
= fragP
->fr_fix
;
7529 switch (fragP
->fr_type
)
7532 /* Empty frags created by the obstack allocation scheme
7533 end up with type 0. */
7538 size
+= fragP
->fr_offset
;
7546 /* No further adjustments needed. */
7548 case rs_machine_dependent
:
7549 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7550 size
+= fragP
->fr_var
;
7553 /* We had darn well better know how big it is. */
7562 /* Re-process all of the fragments looking to convert all
7563 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7566 1) the instruction size count to the loop end label
7567 is too short (<= 2 instructions),
7568 2) loop has a jump or branch in it
7571 1) workaround_all_short_loops is TRUE
7572 2) The generating loop was a 'loopgtz' or 'loopnez'
7573 3) the instruction size count to the loop end label is too short
7575 then convert this frag (and maybe the next one) to generate a NOP.
7576 In any case close it off with a .fill 0. */
7578 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7579 static bfd_boolean
branch_before_loop_end (fragS
*);
7582 xtensa_fix_short_loop_frags (void)
7586 /* When this routine is called, all of the subsections are still intact
7587 so we walk over subsections instead of sections. */
7588 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7591 fragS
*current_target
= NULL
;
7592 offsetT current_offset
= 0;
7593 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7595 /* Walk over all of the fragments in a subsection. */
7596 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7598 /* Check on the current loop. */
7599 if (fragP
->fr_type
== rs_machine_dependent
7600 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7601 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7602 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7607 /* Read it. If the instruction is a loop, get the target. */
7608 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7609 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7610 t_insn
.opcode
) == 1)
7612 /* Get the current fragment target. */
7613 if (fragP
->tc_frag_data
.slot_symbols
[0])
7615 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7616 current_target
= symbol_get_frag (sym
);
7617 current_offset
= fragP
->fr_offset
;
7618 current_opcode
= t_insn
.opcode
;
7623 if (fragP
->fr_type
== rs_machine_dependent
7624 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7626 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7627 && (branch_before_loop_end (fragP
->fr_next
)
7628 || (workaround_all_short_loops
7629 && current_opcode
!= XTENSA_UNDEFINED
7630 && current_opcode
!= xtensa_loop_opcode
)))
7632 if (fragP
->tc_frag_data
.is_no_transform
)
7633 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7635 relax_frag_add_nop (fragP
);
7644 static int unrelaxed_frag_min_insn_count (fragS
*);
7647 count_insns_to_loop_end (fragS
*base_fragP
,
7648 bfd_boolean count_relax_add
,
7651 fragS
*fragP
= NULL
;
7656 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7658 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7659 if (insn_count
>= max_count
)
7662 if (count_relax_add
)
7664 if (fragP
->fr_type
== rs_machine_dependent
7665 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7667 /* In order to add the appropriate number of
7668 NOPs, we count an instruction for downstream
7671 if (insn_count
>= max_count
)
7681 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7683 xtensa_isa isa
= xtensa_default_isa
;
7684 static xtensa_insnbuf insnbuf
= NULL
;
7688 if (!fragP
->tc_frag_data
.is_insn
)
7692 insnbuf
= xtensa_insnbuf_alloc (isa
);
7694 /* Decode the fixed instructions. */
7695 while (offset
< fragP
->fr_fix
)
7699 xtensa_insnbuf_from_chars
7700 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7701 fmt
= xtensa_format_decode (isa
, insnbuf
);
7703 if (fmt
== XTENSA_UNDEFINED
)
7705 as_fatal (_("undecodable instruction in instruction frag"));
7708 offset
+= xtensa_format_length (isa
, fmt
);
7716 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7719 branch_before_loop_end (fragS
*base_fragP
)
7723 for (fragP
= base_fragP
;
7724 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7725 fragP
= fragP
->fr_next
)
7727 if (unrelaxed_frag_has_b_j (fragP
))
7735 unrelaxed_frag_has_b_j (fragS
*fragP
)
7737 static xtensa_insnbuf insnbuf
= NULL
;
7738 xtensa_isa isa
= xtensa_default_isa
;
7741 if (!fragP
->tc_frag_data
.is_insn
)
7745 insnbuf
= xtensa_insnbuf_alloc (isa
);
7747 /* Decode the fixed instructions. */
7748 while (offset
< fragP
->fr_fix
)
7753 xtensa_insnbuf_from_chars
7754 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7755 fmt
= xtensa_format_decode (isa
, insnbuf
);
7756 if (fmt
== XTENSA_UNDEFINED
)
7759 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7761 xtensa_opcode opcode
=
7762 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7763 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7764 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7767 offset
+= xtensa_format_length (isa
, fmt
);
7773 /* Checks to be made after initial assembly but before relaxation. */
7775 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7776 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7779 xtensa_sanity_check (void)
7786 as_where (&file_name
, &line
);
7787 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7791 /* Walk over all of the fragments in a subsection. */
7792 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7794 /* Currently we only check for empty loops here. */
7795 if (fragP
->fr_type
== rs_machine_dependent
7796 && fragP
->fr_subtype
== RELAX_IMMED
)
7798 static xtensa_insnbuf insnbuf
= NULL
;
7801 if (fragP
->fr_opcode
!= NULL
)
7804 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7805 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7806 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7808 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7809 t_insn
.opcode
) == 1)
7811 if (is_empty_loop (&t_insn
, fragP
))
7813 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7814 as_bad (_("invalid empty loop"));
7816 if (!is_local_forward_loop (&t_insn
, fragP
))
7818 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7819 as_bad (_("loop target does not follow "
7820 "loop instruction in section"));
7827 new_logical_line (file_name
, line
);
7831 #define LOOP_IMMED_OPN 1
7833 /* Return TRUE if the loop target is the next non-zero fragment. */
7836 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7838 const expressionS
*expr
;
7842 if (insn
->insn_type
!= ITYPE_INSN
)
7845 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7848 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7851 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7853 if (expr
->X_op
!= O_symbol
)
7856 symbolP
= expr
->X_add_symbol
;
7860 if (symbol_get_frag (symbolP
) == NULL
)
7863 if (S_GET_VALUE (symbolP
) != 0)
7866 /* Walk through the zero-size fragments from this one. If we find
7867 the target fragment, then this is a zero-size loop. */
7869 for (next_fragP
= fragP
->fr_next
;
7871 next_fragP
= next_fragP
->fr_next
)
7873 if (next_fragP
== symbol_get_frag (symbolP
))
7875 if (next_fragP
->fr_fix
!= 0)
7883 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7885 const expressionS
*expr
;
7889 if (insn
->insn_type
!= ITYPE_INSN
)
7892 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7895 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7898 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7900 if (expr
->X_op
!= O_symbol
)
7903 symbolP
= expr
->X_add_symbol
;
7907 if (symbol_get_frag (symbolP
) == NULL
)
7910 /* Walk through fragments until we find the target.
7911 If we do not find the target, then this is an invalid loop. */
7913 for (next_fragP
= fragP
->fr_next
;
7915 next_fragP
= next_fragP
->fr_next
)
7917 if (next_fragP
== symbol_get_frag (symbolP
))
7925 /* Alignment Functions. */
7928 get_text_align_power (unsigned target_size
)
7933 assert (target_size
<= INT_MAX
);
7934 while (target_size
> power
)
7944 get_text_align_max_fill_size (int align_pow
,
7945 bfd_boolean use_nops
,
7946 bfd_boolean use_no_density
)
7949 return (1 << align_pow
);
7951 return 3 * (1 << align_pow
);
7953 return 1 + (1 << align_pow
);
7957 /* Calculate the minimum bytes of fill needed at "address" to align a
7958 target instruction of size "target_size" so that it does not cross a
7959 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7960 the fill can be an arbitrary number of bytes. Otherwise, the space must
7961 be filled by NOP instructions. */
7964 get_text_align_fill_size (addressT address
,
7967 bfd_boolean use_nops
,
7968 bfd_boolean use_no_density
)
7970 addressT alignment
, fill
, fill_limit
, fill_step
;
7971 bfd_boolean skip_one
= FALSE
;
7973 alignment
= (1 << align_pow
);
7974 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7978 fill_limit
= alignment
;
7981 else if (!use_no_density
)
7983 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7984 fill_limit
= alignment
* 2;
7990 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7991 fill_limit
= alignment
* 3;
7995 /* Try all fill sizes until finding one that works. */
7996 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7998 if (skip_one
&& fill
== 1)
8000 if ((address
+ fill
) >> align_pow
8001 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8009 /* This will assert if it is not possible. */
8012 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8018 assert (fill_size
% 3 == 0);
8019 return (fill_size
/ 3);
8022 assert (fill_size
!= 1); /* Bad argument. */
8024 while (fill_size
> 1)
8027 if (fill_size
== 2 || fill_size
== 4)
8029 fill_size
-= insn_size
;
8032 assert (fill_size
!= 1); /* Bad algorithm. */
8038 get_text_align_nth_nop_size (offsetT fill_size
,
8040 bfd_boolean use_no_density
)
8047 assert (fill_size
!= 1); /* Bad argument. */
8049 while (fill_size
> 1)
8052 if (fill_size
== 2 || fill_size
== 4)
8054 fill_size
-= insn_size
;
8064 /* For the given fragment, find the appropriate address
8065 for it to begin at if we are using NOPs to align it. */
8068 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8070 /* The rule is: get next fragment's FIRST instruction. Find
8071 the smallest number of bytes that need to be added to
8072 ensure that the next fragment's FIRST instruction will fit
8075 E.G., 2 bytes : 0, 1, 2 mod 4
8078 If the FIRST instruction MIGHT be relaxed,
8079 assume that it will become a 3-byte instruction.
8081 Note again here that LOOP instructions are not bundleable,
8082 and this relaxation only applies to LOOP opcodes. */
8085 int first_insn_size
;
8087 addressT pre_opcode_bytes
;
8090 xtensa_opcode opcode
;
8091 bfd_boolean is_loop
;
8093 assert (fragP
->fr_type
== rs_machine_dependent
);
8094 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8096 /* Find the loop frag. */
8097 first_insn
= next_non_empty_frag (fragP
);
8098 /* Now find the first insn frag. */
8099 first_insn
= next_non_empty_frag (first_insn
);
8101 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8103 loop_insn_size
= xg_get_single_size (opcode
);
8105 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8106 pre_opcode_bytes
+= loop_insn_size
;
8108 /* For loops, the alignment depends on the size of the
8109 instruction following the loop, not the LOOP instruction. */
8111 if (first_insn
== NULL
)
8114 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8116 first_insn_size
= frag_format_size (first_insn
);
8118 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8119 first_insn_size
= 3; /* ISA specifies this */
8121 /* If it was 8, then we'll need a larger alignment for the section. */
8122 align_power
= get_text_align_power (first_insn_size
);
8123 record_alignment (now_seg
, align_power
);
8125 fill_size
= get_text_align_fill_size
8126 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8127 fragP
->tc_frag_data
.is_no_density
);
8129 return address
+ fill_size
;
8133 /* 3 mechanisms for relaxing an alignment:
8135 Align to a power of 2.
8136 Align so the next fragment's instruction does not cross a word boundary.
8137 Align the current instruction so that if the next instruction
8138 were 3 bytes, it would not cross a word boundary.
8142 zeros - This is easy; always insert zeros.
8143 nops - 3-byte and 2-byte instructions
8147 >=5 : 3-byte instruction + fn (n-3)
8148 widening - widen previous instructions. */
8151 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8153 addressT target_address
, loop_insn_offset
;
8155 xtensa_opcode loop_opcode
;
8156 bfd_boolean is_loop
;
8160 assert (fragP
->fr_type
== rs_machine_dependent
);
8161 switch (fragP
->fr_subtype
)
8163 case RELAX_DESIRE_ALIGN
:
8164 target_size
= next_frag_format_size (fragP
);
8165 if (target_size
== XTENSA_UNDEFINED
)
8167 align_power
= get_text_align_power (xtensa_fetch_width
);
8168 opt_diff
= get_text_align_fill_size (address
, align_power
,
8169 target_size
, FALSE
, FALSE
);
8171 *max_diff
= (opt_diff
+ xtensa_fetch_width
8172 - (target_size
+ ((address
+ opt_diff
)
8173 % xtensa_fetch_width
)));
8174 assert (*max_diff
>= opt_diff
);
8177 case RELAX_ALIGN_NEXT_OPCODE
:
8178 target_size
= next_frag_format_size (fragP
);
8179 loop_insn_offset
= 0;
8180 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8183 /* If the loop has been expanded then the LOOP instruction
8184 could be at an offset from this fragment. */
8185 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8187 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8189 if (target_size
== 2)
8190 target_size
= 3; /* ISA specifies this */
8192 /* In an ideal world, which is what we are shooting for here,
8193 we wouldn't need to use any NOPs immediately prior to the
8194 LOOP instruction. If this approach fails, relax_frag_loop_align
8195 will call get_noop_aligned_address. */
8197 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8198 align_power
= get_text_align_power (target_size
),
8199 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8200 target_size
, FALSE
, FALSE
);
8202 *max_diff
= xtensa_fetch_width
8203 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8204 - target_size
+ opt_diff
;
8205 assert (*max_diff
>= opt_diff
);
8216 /* md_relax_frag Hook and Helper Functions. */
8218 static long relax_frag_loop_align (fragS
*, long);
8219 static long relax_frag_for_align (fragS
*, long);
8220 static long relax_frag_immed
8221 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8224 /* Return the number of bytes added to this fragment, given that the
8225 input has been stretched already by "stretch". */
8228 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8230 xtensa_isa isa
= xtensa_default_isa
;
8231 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8232 long new_stretch
= 0;
8236 static xtensa_insnbuf vbuf
= NULL
;
8237 int slot
, num_slots
;
8240 as_where (&file_name
, &line
);
8241 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8243 fragP
->tc_frag_data
.unreported_expansion
= 0;
8245 switch (fragP
->fr_subtype
)
8247 case RELAX_ALIGN_NEXT_OPCODE
:
8248 /* Always convert. */
8249 if (fragP
->tc_frag_data
.relax_seen
)
8250 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8253 case RELAX_LOOP_END
:
8257 case RELAX_LOOP_END_ADD_NOP
:
8258 /* Add a NOP and switch to .fill 0. */
8259 new_stretch
= relax_frag_add_nop (fragP
);
8263 case RELAX_DESIRE_ALIGN
:
8264 /* Do nothing. The narrowing before this frag will either align
8269 case RELAX_LITERAL_FINAL
:
8272 case RELAX_LITERAL_NR
:
8274 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8275 assert (unreported
== lit_size
);
8276 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8277 fragP
->fr_var
-= lit_size
;
8278 fragP
->fr_fix
+= lit_size
;
8284 vbuf
= xtensa_insnbuf_alloc (isa
);
8286 xtensa_insnbuf_from_chars
8287 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8288 fmt
= xtensa_format_decode (isa
, vbuf
);
8289 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8291 for (slot
= 0; slot
< num_slots
; slot
++)
8293 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8296 if (fragP
->tc_frag_data
.relax_seen
)
8297 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8301 case RELAX_IMMED_STEP1
:
8302 case RELAX_IMMED_STEP2
:
8303 /* Place the immediate. */
8304 new_stretch
+= relax_frag_immed
8305 (now_seg
, fragP
, stretch
,
8306 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8307 fmt
, slot
, stretched_p
, FALSE
);
8311 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8317 case RELAX_LITERAL_POOL_BEGIN
:
8318 case RELAX_LITERAL_POOL_END
:
8319 case RELAX_MAYBE_UNREACHABLE
:
8320 case RELAX_MAYBE_DESIRE_ALIGN
:
8321 /* No relaxation required. */
8324 case RELAX_FILL_NOP
:
8325 case RELAX_UNREACHABLE
:
8326 if (fragP
->tc_frag_data
.relax_seen
)
8327 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8331 as_bad (_("bad relaxation state"));
8334 /* Tell gas we need another relaxation pass. */
8335 if (! fragP
->tc_frag_data
.relax_seen
)
8337 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8341 new_logical_line (file_name
, line
);
8347 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8349 addressT old_address
, old_next_address
, old_size
;
8350 addressT new_address
, new_next_address
, new_size
;
8353 /* All the frags with relax_frag_for_alignment prior to this one in the
8354 section have been done, hopefully eliminating the need for a NOP here.
8355 But, this will put it in if necessary. */
8357 /* Calculate the old address of this fragment and the next fragment. */
8358 old_address
= fragP
->fr_address
- stretch
;
8359 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8360 fragP
->tc_frag_data
.text_expansion
[0]);
8361 old_size
= old_next_address
- old_address
;
8363 /* Calculate the new address of this fragment and the next fragment. */
8364 new_address
= fragP
->fr_address
;
8366 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8367 new_size
= new_next_address
- new_address
;
8369 growth
= new_size
- old_size
;
8371 /* Fix up the text_expansion field and return the new growth. */
8372 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8377 /* Add a NOP instruction. */
8380 relax_frag_add_nop (fragS
*fragP
)
8382 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8383 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8384 assemble_nop (length
, nop_buf
);
8385 fragP
->tc_frag_data
.is_insn
= TRUE
;
8387 if (fragP
->fr_var
< length
)
8389 as_fatal (_("fr_var (%ld) < length (%d)"), fragP
->fr_var
, length
);
8393 fragP
->fr_fix
+= length
;
8394 fragP
->fr_var
-= length
;
8399 static long future_alignment_required (fragS
*, long);
8402 relax_frag_for_align (fragS
*fragP
, long stretch
)
8404 /* Overview of the relaxation procedure for alignment:
8405 We can widen with NOPs or by widening instructions or by filling
8406 bytes after jump instructions. Find the opportune places and widen
8407 them if necessary. */
8412 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8413 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8414 || (fragP
->fr_subtype
== RELAX_SLOTS
8415 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8417 stretch_me
= future_alignment_required (fragP
, stretch
);
8418 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8424 /* We expanded on a previous pass. Can we shrink now? */
8425 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8426 if (shrink
<= stretch
&& stretch
> 0)
8428 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8434 /* Below here, diff > 0. */
8435 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8441 /* Return the address of the next frag that should be aligned.
8443 By "address" we mean the address it _would_ be at if there
8444 is no action taken to align it between here and the target frag.
8445 In other words, if no narrows and no fill nops are used between
8446 here and the frag to align, _even_if_ some of the frags we use
8447 to align targets have already expanded on a previous relaxation
8450 Also, count each frag that may be used to help align the target.
8452 Return 0 if there are no frags left in the chain that need to be
8456 find_address_of_next_align_frag (fragS
**fragPP
,
8460 bfd_boolean
*paddable
)
8462 fragS
*fragP
= *fragPP
;
8463 addressT address
= fragP
->fr_address
;
8465 /* Do not reset the counts to 0. */
8469 /* Limit this to a small search. */
8475 address
+= fragP
->fr_fix
;
8477 if (fragP
->fr_type
== rs_fill
)
8478 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8479 else if (fragP
->fr_type
== rs_machine_dependent
)
8481 switch (fragP
->fr_subtype
)
8483 case RELAX_UNREACHABLE
:
8487 case RELAX_FILL_NOP
:
8489 if (!fragP
->tc_frag_data
.is_no_density
)
8494 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8499 address
+= total_frag_text_expansion (fragP
);;
8503 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8506 case RELAX_ALIGN_NEXT_OPCODE
:
8507 case RELAX_DESIRE_ALIGN
:
8511 case RELAX_MAYBE_UNREACHABLE
:
8512 case RELAX_MAYBE_DESIRE_ALIGN
:
8517 /* Just punt if we don't know the type. */
8524 /* Just punt if we don't know the type. */
8528 fragP
= fragP
->fr_next
;
8536 static long bytes_to_stretch (fragS
*, int, int, int, int);
8538 /* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8539 I'll leave this in until I am more confident this works. */
8541 #define LOOKAHEAD_ALIGNER 1
8544 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8546 fragS
*this_frag
= fragP
;
8550 int narrow_nops
= 0;
8551 bfd_boolean paddable
= FALSE
;
8552 offsetT local_opt_diff
;
8555 int stretch_amount
= 0;
8556 int local_stretch_amount
;
8557 int global_stretch_amount
;
8559 address
= find_address_of_next_align_frag
8560 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8564 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8565 opt_diff
= local_opt_diff
;
8566 assert (opt_diff
>= 0);
8567 assert (max_diff
>= opt_diff
);
8570 #ifdef LOOKAHEAD_ALIGNER
8572 fragP
= fragP
->fr_next
;
8574 while (fragP
&& opt_diff
< max_diff
&& address
)
8576 /* We only use these to determine if we can exit early
8577 because there will be plenty of ways to align future
8579 int glob_widens
= 0;
8582 bfd_boolean glob_pad
= 0;
8583 address
= find_address_of_next_align_frag
8584 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8585 /* If there is a padable portion, then skip. */
8586 if (glob_pad
|| glob_widens
>= (int) xtensa_fetch_width
)
8591 offsetT next_m_diff
;
8592 offsetT next_o_diff
;
8594 /* Downrange frags haven't had stretch added to them yet. */
8597 /* The address also includes any text expansion from this
8598 frag in a previous pass, but we don't want that. */
8599 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8601 /* Assume we are going to move at least opt_diff. In
8602 reality, we might not be able to, but assuming that
8603 we will helps catch cases where moving opt_diff pushes
8604 the next target from aligned to unaligned. */
8605 address
+= opt_diff
;
8607 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8609 /* Now cleanup for the adjustments to address. */
8610 next_o_diff
+= opt_diff
;
8611 next_m_diff
+= opt_diff
;
8612 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8613 opt_diff
= next_o_diff
;
8614 if (next_m_diff
< max_diff
)
8615 max_diff
= next_m_diff
;
8616 fragP
= fragP
->fr_next
;
8619 #endif /* LOOKAHEAD_ALIGNER */
8620 /* If there are enough wideners in between, do it. */
8623 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8625 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8630 local_stretch_amount
8631 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8632 num_widens
, local_opt_diff
);
8633 #ifdef LOOKAHEAD_ALIGNER
8634 global_stretch_amount
8635 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8636 num_widens
, opt_diff
);
8637 /* If the condition below is true, then the frag couldn't
8638 stretch the correct amount for the global case, so we just
8639 optimize locally. We'll rely on the subsequent frags to get
8640 the correct alignment in the global case. */
8641 if (global_stretch_amount
< local_stretch_amount
)
8642 stretch_amount
= local_stretch_amount
;
8644 stretch_amount
= global_stretch_amount
;
8645 #else /* ! LOOKAHEAD_ALIGNER */
8646 stretch_amount
= local_stretch_amount
;
8647 #endif /* ! LOOKAHEAD_ALIGNER */
8648 if (this_frag
->fr_subtype
== RELAX_SLOTS
8649 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8650 assert (stretch_amount
<= 1);
8651 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8653 if (this_frag
->tc_frag_data
.is_no_density
)
8654 assert (stretch_amount
== 3 || stretch_amount
== 0);
8656 assert (stretch_amount
<= 3);
8659 return stretch_amount
;
8663 /* The idea: widen everything you can to get a target or loop aligned,
8664 then start using NOPs.
8666 When we must have a NOP, here is a table of how we decide
8667 (so you don't have to fight through the control flow below):
8669 wide_nops = the number of wide NOPs available for aligning
8670 narrow_nops = the number of narrow NOPs available for aligning
8671 (a subset of wide_nops)
8672 widens = the number of narrow instructions that should be widened
8679 b 0 1 1 (case 3a makes this case unnecessary)
8682 c 0 1 2 (case 4a makes this case unnecessary)
8685 c 0 2 1 (case 5b makes this case unnecessary)
8688 c 0 1 4 (case 6b makes this case unneccesary)
8689 d 1 1 1 (case 6a makes this case unnecessary)
8690 e 0 2 2 (case 6a makes this case unnecessary)
8691 f 0 3 0 (case 6a makes this case unnecessary)
8694 c 1 1 2 (case 7b makes this case unnecessary)
8695 d 0 1 5 (case 7a makes this case unnecessary)
8696 e 0 2 3 (case 7b makes this case unnecessary)
8697 f 0 3 1 (case 7b makes this case unnecessary)
8698 g 1 2 1 (case 7b makes this case unnecessary)
8702 bytes_to_stretch (fragS
*this_frag
,
8708 int bytes_short
= desired_diff
- num_widens
;
8710 assert (desired_diff
>= 0 && desired_diff
< 8);
8711 if (desired_diff
== 0)
8714 assert (wide_nops
> 0 || num_widens
> 0);
8716 /* Always prefer widening to NOP-filling. */
8717 if (bytes_short
< 0)
8719 /* There are enough RELAX_NARROW frags after this one
8720 to align the target without widening this frag in any way. */
8724 if (bytes_short
== 0)
8726 /* Widen every narrow between here and the align target
8727 and the align target will be properly aligned. */
8728 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8734 /* From here we will need at least one NOP to get an alignment.
8735 However, we may not be able to align at all, in which case,
8737 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8739 switch (desired_diff
)
8744 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8745 return 2; /* case 2 */
8751 return 3; /* case 3a */
8753 if (num_widens
>= 1 && wide_nops
== 1)
8754 return 3; /* case 4a */
8755 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8756 return 2; /* case 4b */
8759 if (num_widens
>= 2 && wide_nops
== 1)
8760 return 3; /* case 5a */
8761 /* We will need two nops. Are there enough nops
8762 between here and the align target? */
8763 if (wide_nops
< 2 || narrow_nops
== 0)
8765 /* Are there other nops closer that can serve instead? */
8766 if (wide_nops
> 2 && narrow_nops
> 1)
8768 /* Take the density one first, because there might not be
8769 another density one available. */
8770 if (!this_frag
->tc_frag_data
.is_no_density
)
8771 return 2; /* case 5b narrow */
8773 return 3; /* case 5b wide */
8777 return 3; /* case 6a */
8778 else if (num_widens
>= 3 && wide_nops
== 1)
8779 return 3; /* case 6b */
8782 if (wide_nops
== 1 && num_widens
>= 4)
8783 return 3; /* case 7a */
8784 else if (wide_nops
== 2 && num_widens
>= 1)
8785 return 3; /* case 7b */
8793 /* We will need a NOP no matter what, but should we widen
8794 this instruction to help?
8796 This is a RELAX_FRAG_NARROW frag. */
8797 switch (desired_diff
)
8806 if (wide_nops
>= 1 && num_widens
== 1)
8807 return 1; /* case 4a */
8810 if (wide_nops
>= 1 && num_widens
== 2)
8811 return 1; /* case 5a */
8815 return 0; /* case 6a */
8816 else if (wide_nops
>= 1 && num_widens
== 3)
8817 return 1; /* case 6b */
8820 if (wide_nops
>= 1 && num_widens
== 4)
8821 return 1; /* case 7a */
8822 else if (wide_nops
>= 2 && num_widens
== 1)
8823 return 1; /* case 7b */
8836 relax_frag_immed (segT segP
,
8843 bfd_boolean estimate_only
)
8846 vliw_insn orig_vinsn
;
8848 bfd_boolean negatable_branch
= FALSE
;
8849 bfd_boolean branch_jmp_to_next
= FALSE
;
8850 bfd_boolean wide_insn
= FALSE
;
8851 xtensa_isa isa
= xtensa_default_isa
;
8853 offsetT frag_offset
;
8856 int num_text_bytes
, num_literal_bytes
;
8857 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8859 assert (fragP
->fr_opcode
!= NULL
);
8861 xg_init_vinsn (&orig_vinsn
);
8862 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
8863 if (xtensa_format_num_slots (isa
, fmt
) > 1)
8866 tinsn
= orig_vinsn
.slots
[slot
];
8867 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8869 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8872 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8873 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8875 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8877 old_size
= xtensa_format_length (isa
, fmt
);
8879 /* Special case: replace a branch to the next instruction with a NOP.
8880 This is required to work around a hardware bug in T1040.0 and also
8881 serves as an optimization. */
8883 if (branch_jmp_to_next
8884 && ((old_size
== 2) || (old_size
== 3))
8885 && !next_frag_is_loop_target (fragP
))
8888 /* Here is the fun stuff: Get the immediate field from this
8889 instruction. If it fits, we are done. If not, find the next
8890 instruction sequence that fits. */
8892 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8893 istack_init (&istack
);
8894 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8895 min_steps
, stretch
);
8896 if (num_steps
< min_steps
)
8898 as_fatal (_("internal error: relaxation failed"));
8902 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8904 as_fatal (_("internal error: relaxation requires too many steps"));
8908 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8910 /* Figure out the number of bytes needed. */
8912 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8914 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8916 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8918 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8921 num_text_bytes
+= old_size
;
8922 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8923 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8925 total_text_diff
= num_text_bytes
- old_size
;
8926 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8928 /* It MUST get larger. If not, we could get an infinite loop. */
8929 assert (num_text_bytes
>= 0);
8930 assert (literal_diff
>= 0);
8931 assert (total_text_diff
>= 0);
8933 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8934 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8935 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8936 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8938 /* Find the associated expandable literal for this. */
8939 if (literal_diff
!= 0)
8941 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8944 assert (literal_diff
== 4);
8945 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8947 /* We expect that the literal section state has NOT been
8949 assert (lit_fragP
->fr_type
== rs_machine_dependent
8950 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8951 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8953 /* We need to mark this section for another iteration
8959 if (negatable_branch
&& istack
.ninsn
> 1)
8960 update_next_frag_state (fragP
);
8962 return this_text_diff
;
8966 /* md_convert_frag Hook and Helper Functions. */
8968 static void convert_frag_align_next_opcode (fragS
*);
8969 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8970 static void convert_frag_fill_nop (fragS
*);
8971 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8974 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8976 static xtensa_insnbuf vbuf
= NULL
;
8977 xtensa_isa isa
= xtensa_default_isa
;
8984 as_where (&file_name
, &line
);
8985 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8987 switch (fragp
->fr_subtype
)
8989 case RELAX_ALIGN_NEXT_OPCODE
:
8990 /* Always convert. */
8991 convert_frag_align_next_opcode (fragp
);
8994 case RELAX_DESIRE_ALIGN
:
8995 /* Do nothing. If not aligned already, too bad. */
8999 case RELAX_LITERAL_FINAL
:
9004 vbuf
= xtensa_insnbuf_alloc (isa
);
9006 xtensa_insnbuf_from_chars
9007 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9008 fmt
= xtensa_format_decode (isa
, vbuf
);
9009 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9011 for (slot
= 0; slot
< num_slots
; slot
++)
9013 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9016 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9020 case RELAX_IMMED_STEP1
:
9021 case RELAX_IMMED_STEP2
:
9022 /* Place the immediate. */
9025 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9030 /* This is OK because some slots could have
9031 relaxations and others have none. */
9037 case RELAX_UNREACHABLE
:
9038 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9039 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9040 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9044 case RELAX_MAYBE_UNREACHABLE
:
9045 case RELAX_MAYBE_DESIRE_ALIGN
:
9049 case RELAX_FILL_NOP
:
9050 convert_frag_fill_nop (fragp
);
9053 case RELAX_LITERAL_NR
:
9054 if (use_literal_section
)
9056 /* This should have been handled during relaxation. When
9057 relaxing a code segment, literals sometimes need to be
9058 added to the corresponding literal segment. If that
9059 literal segment has already been relaxed, then we end up
9060 in this situation. Marking the literal segments as data
9061 would make this happen less often (since GAS always relaxes
9062 code before data), but we could still get into trouble if
9063 there are instructions in a segment that is not marked as
9064 containing code. Until we can implement a better solution,
9065 cheat and adjust the addresses of all the following frags.
9066 This could break subsequent alignments, but the linker's
9067 literal coalescing will do that anyway. */
9070 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9071 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9072 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9075 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9079 as_bad (_("invalid relaxation fragment result"));
9084 new_logical_line (file_name
, line
);
9089 convert_frag_align_next_opcode (fragS
*fragp
)
9091 char *nop_buf
; /* Location for Writing. */
9092 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9093 addressT aligned_address
;
9097 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9099 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9100 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9101 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9103 for (nop
= 0; nop
< nop_count
; nop
++)
9106 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9108 assemble_nop (nop_size
, nop_buf
);
9109 nop_buf
+= nop_size
;
9112 fragp
->fr_fix
+= fill_size
;
9113 fragp
->fr_var
-= fill_size
;
9118 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9120 TInsn tinsn
, single_target
;
9121 xtensa_format single_fmt
;
9122 int size
, old_size
, diff
, error_val
;
9123 offsetT frag_offset
;
9126 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9128 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
9130 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9131 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9132 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9137 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9139 /* No conversion. */
9144 assert (fragP
->fr_opcode
!= NULL
);
9146 /* Frags in this relaxation state should only contain
9147 single instruction bundles. */
9148 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9150 /* Just convert it to a wide form.... */
9152 old_size
= xg_get_single_size (tinsn
.opcode
);
9154 tinsn_init (&single_target
);
9155 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9157 error_val
= xg_expand_narrow (&single_target
, &tinsn
);
9160 as_bad (_("unable to widen instruction"));
9164 size
= xg_get_single_size (single_target
.opcode
);
9165 single_fmt
= xg_get_single_format (single_target
.opcode
);
9167 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9168 fragP
, frag_offset
, TRUE
);
9170 diff
= size
- old_size
;
9172 assert (diff
<= fragP
->fr_var
);
9173 fragP
->fr_var
-= diff
;
9174 fragP
->fr_fix
+= diff
;
9182 convert_frag_fill_nop (fragS
*fragP
)
9184 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9185 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9186 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9187 - fragP
->fr_address
- fragP
->fr_fix
));
9190 /* No conversion. */
9194 assemble_nop (size
, loc
);
9195 fragP
->tc_frag_data
.is_insn
= TRUE
;
9196 fragP
->fr_var
-= size
;
9197 fragP
->fr_fix
+= size
;
9202 static fixS
*fix_new_exp_in_seg
9203 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9204 bfd_reloc_code_real_type
);
9205 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9208 convert_frag_immed (segT segP
,
9214 char *immed_instr
= fragP
->fr_opcode
;
9216 bfd_boolean expanded
= FALSE
;
9217 bfd_boolean branch_jmp_to_next
= FALSE
;
9218 char *fr_opcode
= fragP
->fr_opcode
;
9219 vliw_insn orig_vinsn
;
9220 xtensa_isa isa
= xtensa_default_isa
;
9221 bfd_boolean wide_insn
= FALSE
;
9223 bfd_boolean is_loop
;
9225 assert (fr_opcode
!= NULL
);
9227 xg_init_vinsn (&orig_vinsn
);
9229 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
9230 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9233 orig_tinsn
= orig_vinsn
.slots
[slot
];
9234 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9236 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9238 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9239 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9241 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9243 /* Conversion just inserts a NOP and marks the fix as completed. */
9244 bytes
= xtensa_format_length (isa
, fmt
);
9247 orig_vinsn
.slots
[slot
].opcode
=
9248 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
9249 orig_vinsn
.slots
[slot
].ntok
= 0;
9253 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9254 assert (bytes
== 2 || bytes
== 3);
9255 build_nop (&orig_vinsn
.slots
[0], bytes
);
9256 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9258 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
9259 xtensa_insnbuf_to_chars
9260 (isa
, orig_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9265 /* Here is the fun stuff: Get the immediate field from this
9266 instruction. If it fits, we're done. If not, find the next
9267 instruction sequence that fits. */
9271 symbolS
*lit_sym
= NULL
;
9273 int target_offset
= 0;
9276 symbolS
*gen_label
= NULL
;
9277 offsetT frag_offset
;
9278 bfd_boolean first
= TRUE
;
9279 bfd_boolean last_is_jump
;
9281 /* It does not fit. Find something that does and
9282 convert immediately. */
9283 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9284 istack_init (&istack
);
9285 xg_assembly_relax (&istack
, &orig_tinsn
,
9286 segP
, fragP
, frag_offset
, min_steps
, 0);
9288 old_size
= xtensa_format_length (isa
, fmt
);
9290 /* Assemble this right inline. */
9292 /* First, create the mapping from a label name to the REAL label. */
9294 for (i
= 0; i
< istack
.ninsn
; i
++)
9296 TInsn
*tinsn
= &istack
.insn
[i
];
9299 switch (tinsn
->insn_type
)
9302 if (lit_sym
!= NULL
)
9303 as_bad (_("multiple literals in expansion"));
9304 /* First find the appropriate space in the literal pool. */
9305 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9306 if (lit_frag
== NULL
)
9307 as_bad (_("no registered fragment for literal"));
9308 if (tinsn
->ntok
!= 1)
9309 as_bad (_("number of literal tokens != 1"));
9311 /* Set the literal symbol and add a fixup. */
9312 lit_sym
= lit_frag
->fr_symbol
;
9316 if (align_targets
&& !is_loop
)
9318 fragS
*unreach
= fragP
->fr_next
;
9319 while (!(unreach
->fr_type
== rs_machine_dependent
9320 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9321 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9323 unreach
= unreach
->fr_next
;
9326 assert (unreach
->fr_type
== rs_machine_dependent
9327 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9328 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9330 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9332 assert (gen_label
== NULL
);
9333 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9334 fr_opcode
- fragP
->fr_literal
9335 + target_offset
, fragP
);
9339 if (first
&& wide_insn
)
9341 target_offset
+= xtensa_format_length (isa
, fmt
);
9343 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9344 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9347 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9354 last_is_jump
= FALSE
;
9355 for (i
= 0; i
< istack
.ninsn
; i
++)
9357 TInsn
*tinsn
= &istack
.insn
[i
];
9361 bfd_reloc_code_real_type reloc_type
;
9363 switch (tinsn
->insn_type
)
9366 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9367 /* Already checked. */
9368 assert (lit_frag
!= NULL
);
9369 assert (lit_sym
!= NULL
);
9370 assert (tinsn
->ntok
== 1);
9372 target_seg
= S_GET_SEGMENT (lit_sym
);
9373 assert (target_seg
);
9374 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9375 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9377 reloc_type
= BFD_RELOC_32
;
9378 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9379 &tinsn
->tok
[0], FALSE
, reloc_type
);
9386 xg_resolve_labels (tinsn
, gen_label
);
9387 xg_resolve_literals (tinsn
, lit_sym
);
9388 if (wide_insn
&& first
)
9391 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9393 tinsn
->record_fix
= TRUE
;
9394 orig_vinsn
.slots
[slot
] = *tinsn
;
9398 orig_vinsn
.slots
[slot
].opcode
=
9399 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9400 orig_vinsn
.slots
[slot
].ntok
= 0;
9401 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
9403 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
9404 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
9405 (unsigned char *) immed_instr
, 0);
9406 fragP
->tc_frag_data
.is_insn
= TRUE
;
9407 size
= xtensa_format_length (isa
, fmt
);
9408 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9410 xtensa_format single_fmt
=
9411 xg_get_single_format (tinsn
->opcode
);
9414 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9415 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9416 size
+= xg_get_single_size (tinsn
->opcode
);
9421 xtensa_format single_format
;
9422 size
= xg_get_single_size (tinsn
->opcode
);
9423 single_format
= xg_get_single_format (tinsn
->opcode
);
9424 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9426 immed_instr
- fragP
->fr_literal
, TRUE
);
9428 immed_instr
+= size
;
9434 diff
= total_size
- old_size
;
9438 assert (diff
<= fragP
->fr_var
);
9439 fragP
->fr_var
-= diff
;
9440 fragP
->fr_fix
+= diff
;
9444 xg_free_vinsn (&orig_vinsn
);
9446 /* Check for undefined immediates in LOOP instructions. */
9450 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9451 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9453 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9456 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9457 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9459 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9464 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9465 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9467 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9469 /* Add an expansion note on the expanded instruction. */
9470 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9471 &orig_tinsn
.tok
[0], TRUE
,
9472 BFD_RELOC_XTENSA_ASM_EXPAND
);
9477 /* Add a new fix expression into the desired segment. We have to
9478 switch to that segment to do this. */
9481 fix_new_exp_in_seg (segT new_seg
,
9488 bfd_reloc_code_real_type r_type
)
9492 subsegT subseg
= now_subseg
;
9494 assert (new_seg
!= 0);
9495 subseg_set (new_seg
, new_subseg
);
9497 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9498 subseg_set (seg
, subseg
);
9503 /* Relax a loop instruction so that it can span loop >256 bytes.
9509 addi as, as, lo8 (label-.L1)
9510 addmi as, as, mid8 (label-.L1)
9521 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9526 unsigned long target
;
9527 static xtensa_insnbuf insnbuf
= NULL
;
9528 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9529 xtensa_isa isa
= xtensa_default_isa
;
9530 addressT loop_offset
;
9531 addressT addi_offset
= 9;
9532 addressT addmi_offset
= 12;
9537 insnbuf
= xtensa_insnbuf_alloc (isa
);
9539 /* Get the loop offset. */
9540 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9542 /* Validate that there really is a LOOP at the loop_offset. Because
9543 loops are not bundleable, we can assume that the instruction will be
9545 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9546 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9548 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9549 addi_offset
+= loop_offset
;
9550 addmi_offset
+= loop_offset
;
9552 assert (tinsn
->ntok
== 2);
9553 if (tinsn
->tok
[1].X_op
== O_constant
)
9554 target
= tinsn
->tok
[1].X_add_number
;
9555 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9557 /* Find the fragment. */
9558 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9559 assert (S_GET_SEGMENT (sym
) == segP
9560 || S_GET_SEGMENT (sym
) == absolute_section
);
9561 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9565 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9570 know (symbolP
->sy_frag
);
9571 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9572 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9574 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9575 loop_length_hi
= loop_length
& ~0x0ff;
9576 loop_length_lo
= loop_length
& 0x0ff;
9577 if (loop_length_lo
>= 128)
9579 loop_length_lo
-= 256;
9580 loop_length_hi
+= 256;
9583 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9584 32512. If the loop is larger than that, then we just fail. */
9585 if (loop_length_hi
> 32512)
9586 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9587 _("loop too long for LOOP instruction"));
9589 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9590 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9592 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9593 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9595 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9596 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9598 fragP
->tc_frag_data
.is_insn
= TRUE
;
9599 xtensa_insnbuf_to_chars
9600 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9602 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9603 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9604 xtensa_insnbuf_to_chars
9605 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9607 /* Walk through all of the frags from here to the loop end
9608 and mark them as no_transform to keep them from being modified
9609 by the linker. If we ever have a relocation for the
9610 addi/addmi of the difference of two symbols we can remove this. */
9613 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9614 next_fragP
= next_fragP
->fr_next
)
9616 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9617 if (next_fragP
->tc_frag_data
.is_loop_target
)
9619 if (target_count
== 2)
9625 /* A map that keeps information on a per-subsegment basis. This is
9626 maintained during initial assembly, but is invalid once the
9627 subsegments are smashed together. I.E., it cannot be used during
9630 typedef struct subseg_map_struct
9638 float total_freq
; /* fall-through + branch target frequency */
9639 float target_freq
; /* branch target frequency alone */
9641 struct subseg_map_struct
*next
;
9645 static subseg_map
*sseg_map
= NULL
;
9648 get_subseg_info (segT seg
, subsegT subseg
)
9650 subseg_map
*subseg_e
;
9652 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9654 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9662 add_subseg_info (segT seg
, subsegT subseg
)
9664 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9665 memset (subseg_e
, 0, sizeof (subseg_map
));
9666 subseg_e
->seg
= seg
;
9667 subseg_e
->subseg
= subseg
;
9668 subseg_e
->flags
= 0;
9669 /* Start off considering every branch target very important. */
9670 subseg_e
->target_freq
= 1.0;
9671 subseg_e
->total_freq
= 1.0;
9672 subseg_e
->next
= sseg_map
;
9673 sseg_map
= subseg_e
;
9679 get_last_insn_flags (segT seg
, subsegT subseg
)
9681 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9683 return subseg_e
->flags
;
9689 set_last_insn_flags (segT seg
,
9694 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9696 subseg_e
= add_subseg_info (seg
, subseg
);
9698 subseg_e
->flags
|= fl
;
9700 subseg_e
->flags
&= ~fl
;
9705 get_subseg_total_freq (segT seg
, subsegT subseg
)
9707 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9709 return subseg_e
->total_freq
;
9715 get_subseg_target_freq (segT seg
, subsegT subseg
)
9717 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9719 return subseg_e
->target_freq
;
9725 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9727 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9729 subseg_e
= add_subseg_info (seg
, subseg
);
9730 subseg_e
->total_freq
= total_f
;
9731 subseg_e
->target_freq
= target_f
;
9735 /* Segment Lists and emit_state Stuff. */
9737 /* Remove the segment from the global sections list. */
9740 xtensa_remove_section (segT sec
)
9742 /* Handle brain-dead bfd_section_list_remove macro, which
9743 expect the address of the prior section's "next" field, not
9744 just the address of the section to remove. */
9746 segT
*ps_next_ptr
= &stdoutput
->sections
;
9747 while (*ps_next_ptr
!= sec
&& *ps_next_ptr
!= NULL
)
9748 ps_next_ptr
= &(*ps_next_ptr
)->next
;
9750 assert (*ps_next_ptr
!= NULL
);
9752 bfd_section_list_remove (stdoutput
, ps_next_ptr
);
9757 xtensa_insert_section (segT after_sec
, segT sec
)
9759 segT
*after_sec_next
;
9760 if (after_sec
== NULL
)
9761 after_sec_next
= &stdoutput
->sections
;
9763 after_sec_next
= &after_sec
->next
;
9765 bfd_section_list_insert (stdoutput
, after_sec_next
, sec
);
9770 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9775 segT literal_section
= head
->seg
;
9777 /* Move the literal section to the front of the section list. */
9778 assert (literal_section
);
9779 xtensa_remove_section (literal_section
);
9780 xtensa_insert_section (NULL
, literal_section
);
9787 static void mark_literal_frags (seg_list
*);
9790 xtensa_move_literals (void)
9793 frchainS
*frchain_from
, *frchain_to
;
9794 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9795 fragS
**frag_splice
;
9798 fixS
*fix
, *next_fix
, **fix_splice
;
9801 mark_literal_frags (literal_head
->next
);
9802 mark_literal_frags (init_literal_head
->next
);
9803 mark_literal_frags (fini_literal_head
->next
);
9805 if (use_literal_section
)
9808 segment
= literal_head
->next
;
9811 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9812 search_frag
= frchain_from
->frch_root
;
9813 literal_pool
= NULL
;
9815 frag_splice
= &(frchain_from
->frch_root
);
9817 while (!search_frag
->tc_frag_data
.literal_frag
)
9819 assert (search_frag
->fr_fix
== 0
9820 || search_frag
->fr_type
== rs_align
);
9821 search_frag
= search_frag
->fr_next
;
9824 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9825 == RELAX_LITERAL_POOL_BEGIN
);
9826 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9828 /* Make sure that all the frags in this series are closed, and
9829 that there is at least one left over of zero-size. This
9830 prevents us from making a segment with an frchain without any
9832 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9833 xtensa_set_frag_assembly_state (frag_now
);
9834 last_frag
= frag_now
;
9835 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9836 xtensa_set_frag_assembly_state (frag_now
);
9838 while (search_frag
!= frag_now
)
9840 next_frag
= search_frag
->fr_next
;
9842 /* First, move the frag out of the literal section and
9843 to the appropriate place. */
9844 if (search_frag
->tc_frag_data
.literal_frag
)
9846 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9847 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9848 /* Note that we set this fr_var to be a fix
9849 chain when we created the literal pool location
9850 as RELAX_LITERAL_POOL_BEGIN. */
9851 frchain_to
= (frchainS
*) literal_pool
->fr_var
;
9853 insert_after
= literal_pool
;
9855 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9856 insert_after
= insert_after
->fr_next
;
9858 dest_seg
= (segT
) insert_after
->fr_next
->fr_var
;
9860 *frag_splice
= next_frag
;
9861 search_frag
->fr_next
= insert_after
->fr_next
;
9862 insert_after
->fr_next
= search_frag
;
9863 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9865 /* Now move any fixups associated with this frag to the
9867 fix
= frchain_from
->fix_root
;
9868 fix_splice
= &(frchain_from
->fix_root
);
9871 next_fix
= fix
->fx_next
;
9872 if (fix
->fx_frag
== search_frag
)
9874 *fix_splice
= next_fix
;
9875 fix
->fx_next
= frchain_to
->fix_root
;
9876 frchain_to
->fix_root
= fix
;
9877 if (frchain_to
->fix_tail
== NULL
)
9878 frchain_to
->fix_tail
= fix
;
9881 fix_splice
= &(fix
->fx_next
);
9884 search_frag
= next_frag
;
9887 if (frchain_from
->fix_root
!= NULL
)
9889 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9890 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9892 assert (frchain_from
->fix_root
== NULL
);
9894 frchain_from
->fix_tail
= NULL
;
9895 xtensa_restore_emit_state (&state
);
9896 segment
= segment
->next
;
9899 /* Now fix up the SEGMENT value for all the literal symbols. */
9900 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9902 symbolS
*lit_sym
= lit
->sym
;
9903 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9905 S_SET_SEGMENT (lit_sym
, dest_seg
);
9910 /* Walk over all the frags for segments in a list and mark them as
9911 containing literals. As clunky as this is, we can't rely on frag_var
9912 and frag_variant to get called in all situations. */
9915 mark_literal_frags (seg_list
*segment
)
9917 frchainS
*frchain_from
;
9922 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9923 search_frag
= frchain_from
->frch_root
;
9926 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9927 search_frag
= search_frag
->fr_next
;
9929 segment
= segment
->next
;
9935 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9937 /* Move all of the sections in the section list to come
9938 after "after" in the gnu segment list. */
9943 segT literal_section
= head
->seg
;
9945 /* Move the literal section after "after". */
9946 assert (literal_section
);
9947 if (literal_section
!= after
)
9949 xtensa_remove_section (literal_section
);
9950 xtensa_insert_section (after
, literal_section
);
9958 /* Push all the literal segments to the end of the gnu list. */
9961 xtensa_reorder_segments (void)
9968 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9974 /* Now that we have the last section, push all the literal
9975 sections to the end. */
9976 xtensa_reorder_seg_list (literal_head
, last_sec
);
9977 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
9978 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
9980 /* Now perform the final error check. */
9981 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9983 assert (new_count
== old_count
);
9987 /* Change the emit state (seg, subseg, and frag related stuff) to the
9988 correct location. Return a emit_state which can be passed to
9989 xtensa_restore_emit_state to return to current fragment. */
9992 xtensa_switch_to_literal_fragment (emit_state
*result
)
9994 if (directive_state
[directive_absolute_literals
])
9996 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
9997 &default_lit_sections
.lit4_seg
, FALSE
);
9998 xtensa_switch_section_emit_state (result
,
9999 default_lit_sections
.lit4_seg
, 0);
10002 xtensa_switch_to_non_abs_literal_fragment (result
);
10004 /* Do a 4-byte align here. */
10005 frag_align (2, 0, 0);
10006 record_alignment (now_seg
, 2);
10011 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10013 /* When we mark a literal pool location, we want to put a frag in
10014 the literal pool that points to it. But to do that, we want to
10015 switch_to_literal_fragment. But literal sections don't have
10016 literal pools, so their location is always null, so we would
10017 recurse forever. This is kind of hacky, but it works. */
10019 static bfd_boolean recursive
= FALSE
;
10020 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10021 bfd_boolean is_init
=
10022 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10024 bfd_boolean is_fini
=
10025 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10027 if (pool_location
== NULL
10028 && !use_literal_section
10030 && !is_init
&& ! is_fini
)
10032 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10034 xtensa_mark_literal_pool_location ();
10038 /* Special case: If we are in the ".fini" or ".init" section, then
10039 we will ALWAYS be generating to the ".fini.literal" and
10040 ".init.literal" sections. */
10044 cache_literal_section (init_literal_head
,
10045 default_lit_sections
.init_lit_seg_name
,
10046 &default_lit_sections
.init_lit_seg
, TRUE
);
10047 xtensa_switch_section_emit_state (result
,
10048 default_lit_sections
.init_lit_seg
, 0);
10052 cache_literal_section (fini_literal_head
,
10053 default_lit_sections
.fini_lit_seg_name
,
10054 &default_lit_sections
.fini_lit_seg
, TRUE
);
10055 xtensa_switch_section_emit_state (result
,
10056 default_lit_sections
.fini_lit_seg
, 0);
10060 cache_literal_section (literal_head
,
10061 default_lit_sections
.lit_seg_name
,
10062 &default_lit_sections
.lit_seg
, TRUE
);
10063 xtensa_switch_section_emit_state (result
,
10064 default_lit_sections
.lit_seg
, 0);
10067 if (!use_literal_section
10068 && !is_init
&& !is_fini
10069 && get_literal_pool_location (now_seg
) != pool_location
)
10071 /* Close whatever frag is there. */
10072 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10073 xtensa_set_frag_assembly_state (frag_now
);
10074 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10075 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10076 xtensa_set_frag_assembly_state (frag_now
);
10081 /* Call this function before emitting data into the literal section.
10082 This is a helper function for xtensa_switch_to_literal_fragment.
10083 This is similar to a .section new_now_seg subseg. */
10086 xtensa_switch_section_emit_state (emit_state
*state
,
10088 subsegT new_now_subseg
)
10090 state
->name
= now_seg
->name
;
10091 state
->now_seg
= now_seg
;
10092 state
->now_subseg
= now_subseg
;
10093 state
->generating_literals
= generating_literals
;
10094 generating_literals
++;
10095 subseg_set (new_now_seg
, new_now_subseg
);
10099 /* Use to restore the emitting into the normal place. */
10102 xtensa_restore_emit_state (emit_state
*state
)
10104 generating_literals
= state
->generating_literals
;
10105 subseg_set (state
->now_seg
, state
->now_subseg
);
10109 /* Get a segment of a given name. If the segment is already
10110 present, return it; otherwise, create a new one. */
10113 cache_literal_section (seg_list
*head
,
10116 bfd_boolean is_code
)
10118 segT current_section
= now_seg
;
10119 int current_subsec
= now_subseg
;
10125 /* Check if the named section exists. */
10126 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10128 if (!strcmp (segment_name (seg
), name
))
10134 /* Create a new literal section. */
10135 seg
= subseg_new (name
, (subsegT
) 0);
10138 /* Add the newly created literal segment to the specified list. */
10139 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10141 n
->next
= head
->next
;
10144 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10145 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10146 | (is_code
? SEC_CODE
: SEC_DATA
));
10147 bfd_set_section_alignment (stdoutput
, seg
, 2);
10151 subseg_set (current_section
, current_subsec
);
10155 /* Property Tables Stuff. */
10157 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10158 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10159 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10161 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10162 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10164 static bfd_boolean
get_frag_is_literal (const fragS
*);
10165 static void xtensa_create_property_segments
10166 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10167 static void xtensa_create_xproperty_segments
10168 (frag_flags_fn
, const char *, xt_section_type
);
10169 static segment_info_type
*retrieve_segment_info (segT
);
10170 static segT
retrieve_xtensa_section (char *);
10171 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10172 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10173 static void add_xt_block_frags
10174 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10175 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10176 static void xtensa_frag_flags_init (frag_flags
*);
10177 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10178 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10179 static void add_xt_prop_frags
10180 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10182 /* Set up property tables after relaxation. */
10185 xtensa_post_relax_hook (void)
10187 xtensa_move_seg_list_to_beginning (literal_head
);
10188 xtensa_move_seg_list_to_beginning (init_literal_head
);
10189 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10191 xtensa_find_unmarked_state_frags ();
10193 if (use_literal_section
)
10194 xtensa_create_property_segments (get_frag_is_literal
,
10196 XTENSA_LIT_SEC_NAME
,
10198 xtensa_create_xproperty_segments (get_frag_property_flags
,
10199 XTENSA_PROP_SEC_NAME
,
10202 if (warn_unaligned_branch_targets
)
10203 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10204 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10208 /* This function is only meaningful after xtensa_move_literals. */
10211 get_frag_is_literal (const fragS
*fragP
)
10213 assert (fragP
!= NULL
);
10214 return fragP
->tc_frag_data
.is_literal
;
10219 xtensa_create_property_segments (frag_predicate property_function
,
10220 frag_predicate end_property_function
,
10221 const char *section_name_base
,
10222 xt_section_type sec_type
)
10226 /* Walk over all of the current segments.
10227 Walk over each fragment
10228 For each non-empty fragment,
10229 Build a property record (append where possible). */
10231 for (seclist
= &stdoutput
->sections
;
10232 seclist
&& *seclist
;
10233 seclist
= &(*seclist
)->next
)
10235 segT sec
= *seclist
;
10238 flags
= bfd_get_section_flags (stdoutput
, sec
);
10239 if (flags
& SEC_DEBUGGING
)
10241 if (!(flags
& SEC_ALLOC
))
10244 if (section_has_property (sec
, property_function
))
10246 char *property_section_name
=
10247 xtensa_get_property_section_name (sec
, section_name_base
);
10248 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10249 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10250 xtensa_block_info
**xt_blocks
=
10251 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10252 /* Walk over all of the frchains here and add new sections. */
10253 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10254 end_property_function
);
10258 /* Now we fill them out.... */
10260 for (seclist
= &stdoutput
->sections
;
10261 seclist
&& *seclist
;
10262 seclist
= &(*seclist
)->next
)
10264 segment_info_type
*seginfo
;
10265 xtensa_block_info
*block
;
10266 segT sec
= *seclist
;
10268 seginfo
= seg_info (sec
);
10269 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10273 xtensa_block_info
*cur_block
;
10274 /* This is a section with some data. */
10276 bfd_size_type rec_size
;
10278 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10281 rec_size
= num_recs
* 8;
10282 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10284 /* In order to make this work with the assembler, we have to
10285 build some frags and then build the "fixups" for it. It
10286 would be easier to just set the contents then set the
10291 /* Allocate a fragment and leak it. */
10293 bfd_size_type frag_size
;
10295 frchainS
*frchainP
;
10299 frag_size
= sizeof (fragS
) + rec_size
;
10300 fragP
= (fragS
*) xmalloc (frag_size
);
10302 memset (fragP
, 0, frag_size
);
10303 fragP
->fr_address
= 0;
10304 fragP
->fr_next
= NULL
;
10305 fragP
->fr_fix
= rec_size
;
10307 fragP
->fr_type
= rs_fill
;
10308 /* The rest are zeros. */
10310 frchainP
= seginfo
->frchainP
;
10311 frchainP
->frch_root
= fragP
;
10312 frchainP
->frch_last
= fragP
;
10314 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10315 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10317 seginfo
->fix_root
= fixes
;
10318 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10320 frag_data
= &fragP
->fr_literal
[0];
10321 for (i
= 0; i
< num_recs
; i
++)
10323 fixS
*fix
= &fixes
[i
];
10324 assert (cur_block
);
10326 /* Write the fixup. */
10327 if (i
!= num_recs
- 1)
10328 fix
->fx_next
= &fixes
[i
+ 1];
10330 fix
->fx_next
= NULL
;
10333 fix
->fx_frag
= fragP
;
10334 fix
->fx_where
= i
* 8;
10335 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10336 fix
->fx_offset
= cur_block
->offset
;
10337 fix
->fx_r_type
= BFD_RELOC_32
;
10338 fix
->fx_file
= "Internal Assembly";
10341 /* Write the length. */
10342 md_number_to_chars (&frag_data
[4 + 8 * i
],
10343 cur_block
->size
, 4);
10344 cur_block
= cur_block
->next
;
10353 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10354 const char *section_name_base
,
10355 xt_section_type sec_type
)
10359 /* Walk over all of the current segments.
10360 Walk over each fragment.
10361 For each fragment that has instructions,
10362 build an instruction record (append where possible). */
10364 for (seclist
= &stdoutput
->sections
;
10365 seclist
&& *seclist
;
10366 seclist
= &(*seclist
)->next
)
10368 segT sec
= *seclist
;
10371 flags
= bfd_get_section_flags (stdoutput
, sec
);
10372 if (flags
& SEC_DEBUGGING
)
10374 if (!(flags
& SEC_ALLOC
))
10377 if (section_has_xproperty (sec
, flag_fn
))
10379 char *property_section_name
=
10380 xtensa_get_property_section_name (sec
, section_name_base
);
10381 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10382 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10383 xtensa_block_info
**xt_blocks
=
10384 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10385 /* Walk over all of the frchains here and add new sections. */
10386 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10390 /* Now we fill them out.... */
10392 for (seclist
= &stdoutput
->sections
;
10393 seclist
&& *seclist
;
10394 seclist
= &(*seclist
)->next
)
10396 segment_info_type
*seginfo
;
10397 xtensa_block_info
*block
;
10398 segT sec
= *seclist
;
10400 seginfo
= seg_info (sec
);
10401 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10405 xtensa_block_info
*cur_block
;
10406 /* This is a section with some data. */
10408 bfd_size_type rec_size
;
10410 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10413 rec_size
= num_recs
* (8 + 4);
10414 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10416 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10418 /* In order to make this work with the assembler, we have to build
10419 some frags then build the "fixups" for it. It would be easier to
10420 just set the contents then set the arlents. */
10424 /* Allocate a fragment and (unfortunately) leak it. */
10426 bfd_size_type frag_size
;
10428 frchainS
*frchainP
;
10432 frag_size
= sizeof (fragS
) + rec_size
;
10433 fragP
= (fragS
*) xmalloc (frag_size
);
10435 memset (fragP
, 0, frag_size
);
10436 fragP
->fr_address
= 0;
10437 fragP
->fr_next
= NULL
;
10438 fragP
->fr_fix
= rec_size
;
10440 fragP
->fr_type
= rs_fill
;
10441 /* The rest are zeros. */
10443 frchainP
= seginfo
->frchainP
;
10444 frchainP
->frch_root
= fragP
;
10445 frchainP
->frch_last
= fragP
;
10447 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10448 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10450 seginfo
->fix_root
= fixes
;
10451 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10453 frag_data
= &fragP
->fr_literal
[0];
10454 for (i
= 0; i
< num_recs
; i
++)
10456 fixS
*fix
= &fixes
[i
];
10457 assert (cur_block
);
10459 /* Write the fixup. */
10460 if (i
!= num_recs
- 1)
10461 fix
->fx_next
= &fixes
[i
+ 1];
10463 fix
->fx_next
= NULL
;
10466 fix
->fx_frag
= fragP
;
10467 fix
->fx_where
= i
* (8 + 4);
10468 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10469 fix
->fx_offset
= cur_block
->offset
;
10470 fix
->fx_r_type
= BFD_RELOC_32
;
10471 fix
->fx_file
= "Internal Assembly";
10474 /* Write the length. */
10475 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10476 cur_block
->size
, 4);
10477 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10478 frag_flags_to_number (&cur_block
->flags
),
10480 cur_block
= cur_block
->next
;
10488 static segment_info_type
*
10489 retrieve_segment_info (segT seg
)
10491 segment_info_type
*seginfo
;
10492 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10495 frchainS
*frchainP
;
10497 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10498 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10499 seginfo
->fix_root
= NULL
;
10500 seginfo
->fix_tail
= NULL
;
10501 seginfo
->bfd_section
= seg
;
10503 /* We will not be dealing with these, only our special ones. */
10504 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10506 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10507 frchainP
->frch_root
= NULL
;
10508 frchainP
->frch_last
= NULL
;
10509 frchainP
->frch_next
= NULL
;
10510 frchainP
->frch_seg
= seg
;
10511 frchainP
->frch_subseg
= 0;
10512 frchainP
->fix_root
= NULL
;
10513 frchainP
->fix_tail
= NULL
;
10514 /* Do not init the objstack. */
10515 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10516 /* frchainP->frch_frag_now = fragP; */
10517 frchainP
->frch_frag_now
= NULL
;
10519 seginfo
->frchainP
= frchainP
;
10527 retrieve_xtensa_section (char *sec_name
)
10529 bfd
*abfd
= stdoutput
;
10530 flagword flags
, out_flags
, link_once_flags
;
10533 flags
= bfd_get_section_flags (abfd
, now_seg
);
10534 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10535 if (link_once_flags
)
10536 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10537 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10539 s
= bfd_make_section_old_way (abfd
, sec_name
);
10541 as_bad (_("could not create section %s"), sec_name
);
10542 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10543 as_bad (_("invalid flag combination on section %s"), sec_name
);
10550 section_has_property (segT sec
, frag_predicate property_function
)
10552 segment_info_type
*seginfo
= seg_info (sec
);
10555 if (seginfo
&& seginfo
->frchainP
)
10557 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10559 if (property_function (fragP
)
10560 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10569 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10571 segment_info_type
*seginfo
= seg_info (sec
);
10574 if (seginfo
&& seginfo
->frchainP
)
10576 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10578 frag_flags prop_flags
;
10579 property_function (fragP
, &prop_flags
);
10580 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10588 /* Two types of block sections exist right now: literal and insns. */
10591 add_xt_block_frags (segT sec
,
10593 xtensa_block_info
**xt_block
,
10594 frag_predicate property_function
,
10595 frag_predicate end_property_function
)
10597 segment_info_type
*seg_info
;
10598 segment_info_type
*xt_seg_info
;
10599 bfd_vma seg_offset
;
10602 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10603 seg_info
= retrieve_segment_info (sec
);
10605 /* Build it if needed. */
10606 while (*xt_block
!= NULL
)
10607 xt_block
= &(*xt_block
)->next
;
10608 /* We are either at NULL at the beginning or at the end. */
10610 /* Walk through the frags. */
10613 if (seg_info
->frchainP
)
10615 for (fragP
= seg_info
->frchainP
->frch_root
;
10617 fragP
= fragP
->fr_next
)
10619 if (property_function (fragP
)
10620 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10622 if (*xt_block
!= NULL
)
10624 if ((*xt_block
)->offset
+ (*xt_block
)->size
10625 == fragP
->fr_address
)
10626 (*xt_block
)->size
+= fragP
->fr_fix
;
10628 xt_block
= &((*xt_block
)->next
);
10630 if (*xt_block
== NULL
)
10632 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10633 xmalloc (sizeof (xtensa_block_info
));
10634 new_block
->sec
= sec
;
10635 new_block
->offset
= fragP
->fr_address
;
10636 new_block
->size
= fragP
->fr_fix
;
10637 new_block
->next
= NULL
;
10638 xtensa_frag_flags_init (&new_block
->flags
);
10639 *xt_block
= new_block
;
10641 if (end_property_function
10642 && end_property_function (fragP
))
10644 xt_block
= &((*xt_block
)->next
);
10652 /* Break the encapsulation of add_xt_prop_frags here. */
10655 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10657 if (prop_flags
->is_literal
10658 || prop_flags
->is_insn
10659 || prop_flags
->is_data
10660 || prop_flags
->is_unreachable
)
10667 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10669 memset (prop_flags
, 0, sizeof (frag_flags
));
10674 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10676 xtensa_frag_flags_init (prop_flags
);
10677 if (fragP
->tc_frag_data
.is_literal
)
10678 prop_flags
->is_literal
= TRUE
;
10679 if (fragP
->tc_frag_data
.is_unreachable
)
10680 prop_flags
->is_unreachable
= TRUE
;
10681 else if (fragP
->tc_frag_data
.is_insn
)
10683 prop_flags
->is_insn
= TRUE
;
10684 if (fragP
->tc_frag_data
.is_loop_target
)
10685 prop_flags
->insn
.is_loop_target
= TRUE
;
10686 if (fragP
->tc_frag_data
.is_branch_target
)
10687 prop_flags
->insn
.is_branch_target
= TRUE
;
10688 if (fragP
->tc_frag_data
.is_specific_opcode
10689 || fragP
->tc_frag_data
.is_no_transform
)
10690 prop_flags
->insn
.is_no_transform
= TRUE
;
10691 if (fragP
->tc_frag_data
.is_no_density
)
10692 prop_flags
->insn
.is_no_density
= TRUE
;
10693 if (fragP
->tc_frag_data
.use_absolute_literals
)
10694 prop_flags
->insn
.is_abslit
= TRUE
;
10696 if (fragP
->tc_frag_data
.is_align
)
10698 prop_flags
->is_align
= TRUE
;
10699 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10700 if (xtensa_frag_flags_is_empty (prop_flags
))
10701 prop_flags
->is_data
= TRUE
;
10707 frag_flags_to_number (const frag_flags
*prop_flags
)
10710 if (prop_flags
->is_literal
)
10711 num
|= XTENSA_PROP_LITERAL
;
10712 if (prop_flags
->is_insn
)
10713 num
|= XTENSA_PROP_INSN
;
10714 if (prop_flags
->is_data
)
10715 num
|= XTENSA_PROP_DATA
;
10716 if (prop_flags
->is_unreachable
)
10717 num
|= XTENSA_PROP_UNREACHABLE
;
10718 if (prop_flags
->insn
.is_loop_target
)
10719 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10720 if (prop_flags
->insn
.is_branch_target
)
10722 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10723 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10726 if (prop_flags
->insn
.is_no_density
)
10727 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10728 if (prop_flags
->insn
.is_no_transform
)
10729 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10730 if (prop_flags
->insn
.is_no_reorder
)
10731 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10732 if (prop_flags
->insn
.is_abslit
)
10733 num
|= XTENSA_PROP_INSN_ABSLIT
;
10735 if (prop_flags
->is_align
)
10737 num
|= XTENSA_PROP_ALIGN
;
10738 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10746 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10747 const frag_flags
*prop_flags_2
)
10749 /* Cannot combine with an end marker. */
10751 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10753 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10755 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10758 if (prop_flags_1
->is_insn
)
10760 /* Properties of the beginning of the frag. */
10761 if (prop_flags_2
->insn
.is_loop_target
)
10763 if (prop_flags_2
->insn
.is_branch_target
)
10765 if (prop_flags_1
->insn
.is_no_density
!=
10766 prop_flags_2
->insn
.is_no_density
)
10768 if (prop_flags_1
->insn
.is_no_transform
!=
10769 prop_flags_2
->insn
.is_no_transform
)
10771 if (prop_flags_1
->insn
.is_no_reorder
!=
10772 prop_flags_2
->insn
.is_no_reorder
)
10774 if (prop_flags_1
->insn
.is_abslit
!=
10775 prop_flags_2
->insn
.is_abslit
)
10779 if (prop_flags_1
->is_align
)
10787 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10790 unsigned align_bits
;
10792 if (!xt_block
->flags
.is_align
)
10793 return xt_block
->size
;
10795 end_addr
= xt_block
->offset
+ xt_block
->size
;
10796 align_bits
= xt_block
->flags
.alignment
;
10797 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10798 return end_addr
- xt_block
->offset
;
10803 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10804 const xtensa_block_info
*xt_block_2
)
10806 if (xt_block
->sec
!= xt_block_2
->sec
)
10808 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10809 != xt_block_2
->offset
)
10812 if (xt_block_2
->size
== 0
10813 && (!xt_block_2
->flags
.is_unreachable
10814 || xt_block
->flags
.is_unreachable
))
10816 if (xt_block_2
->flags
.is_align
10817 && xt_block
->flags
.is_align
)
10819 /* Nothing needed. */
10820 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10825 if (xt_block_2
->flags
.is_align
)
10827 /* Push alignment to previous entry. */
10828 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10829 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10834 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10835 &xt_block_2
->flags
))
10838 xt_block
->size
+= xt_block_2
->size
;
10840 if (xt_block_2
->flags
.is_align
)
10842 xt_block
->flags
.is_align
= TRUE
;
10843 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10851 add_xt_prop_frags (segT sec
,
10853 xtensa_block_info
**xt_block
,
10854 frag_flags_fn property_function
)
10856 segment_info_type
*seg_info
;
10857 segment_info_type
*xt_seg_info
;
10858 bfd_vma seg_offset
;
10861 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10862 seg_info
= retrieve_segment_info (sec
);
10863 /* Build it if needed. */
10864 while (*xt_block
!= NULL
)
10866 xt_block
= &(*xt_block
)->next
;
10868 /* We are either at NULL at the beginning or at the end. */
10870 /* Walk through the frags. */
10873 if (seg_info
->frchainP
)
10875 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10876 fragP
= fragP
->fr_next
)
10878 xtensa_block_info tmp_block
;
10879 tmp_block
.sec
= sec
;
10880 tmp_block
.offset
= fragP
->fr_address
;
10881 tmp_block
.size
= fragP
->fr_fix
;
10882 tmp_block
.next
= NULL
;
10883 property_function (fragP
, &tmp_block
.flags
);
10885 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10886 /* && fragP->fr_fix != 0) */
10888 if ((*xt_block
) == NULL
10889 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10891 xtensa_block_info
*new_block
;
10892 if ((*xt_block
) != NULL
)
10893 xt_block
= &(*xt_block
)->next
;
10894 new_block
= (xtensa_block_info
*)
10895 xmalloc (sizeof (xtensa_block_info
));
10896 *new_block
= tmp_block
;
10897 *xt_block
= new_block
;
10905 /* op_placement_info_table */
10907 /* op_placement_info makes it easier to determine which
10908 ops can go in which slots. */
10911 init_op_placement_info_table (void)
10913 xtensa_isa isa
= xtensa_default_isa
;
10914 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10915 xtensa_opcode opcode
;
10918 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10920 op_placement_table
= (op_placement_info_table
)
10921 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10922 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10924 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10926 op_placement_info
*opi
= &op_placement_table
[opcode
];
10927 /* FIXME: Make tinsn allocation dynamic. */
10928 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10929 as_fatal (_("too many operands in instruction"));
10930 opi
->single
= XTENSA_UNDEFINED
;
10931 opi
->single_size
= 0;
10932 opi
->widest
= XTENSA_UNDEFINED
;
10933 opi
->widest_size
= 0;
10934 opi
->narrowest
= XTENSA_UNDEFINED
;
10935 opi
->narrowest_size
= 0x7F;
10937 opi
->num_formats
= 0;
10939 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10941 opi
->slots
[fmt
] = 0;
10942 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10944 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10946 int fmt_length
= xtensa_format_length (isa
, fmt
);
10948 set_bit (fmt
, opi
->formats
);
10949 set_bit (slot
, opi
->slots
[fmt
]);
10950 /* opi->slot_count[fmt]++; */
10951 if (fmt_length
< opi
->narrowest_size
)
10953 opi
->narrowest
= fmt
;
10954 opi
->narrowest_size
= fmt_length
;
10956 if (fmt_length
> opi
->widest_size
)
10959 opi
->widest_size
= fmt_length
;
10961 if (xtensa_format_num_slots (isa
, fmt
) == 1)
10963 if (opi
->single_size
== 0
10964 || fmt_length
< opi
->single_size
)
10967 opi
->single_size
= fmt_length
;
10973 opi
->num_formats
++;
10976 xtensa_insnbuf_free (isa
, ibuf
);
10981 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10983 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10987 /* If the opcode is available in a single slot format, return its size. */
10990 xg_get_single_size (xtensa_opcode opcode
)
10992 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
10993 return op_placement_table
[opcode
].single_size
;
10997 static xtensa_format
10998 xg_get_single_format (xtensa_opcode opcode
)
11000 return op_placement_table
[opcode
].single
;
11004 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11007 istack_init (IStack
*stack
)
11009 memset (stack
, 0, sizeof (IStack
));
11015 istack_empty (IStack
*stack
)
11017 return (stack
->ninsn
== 0);
11022 istack_full (IStack
*stack
)
11024 return (stack
->ninsn
== MAX_ISTACK
);
11028 /* Return a pointer to the top IStack entry.
11029 It is an error to call this if istack_empty () is TRUE. */
11032 istack_top (IStack
*stack
)
11034 int rec
= stack
->ninsn
- 1;
11035 assert (!istack_empty (stack
));
11036 return &stack
->insn
[rec
];
11040 /* Add a new TInsn to an IStack.
11041 It is an error to call this if istack_full () is TRUE. */
11044 istack_push (IStack
*stack
, TInsn
*insn
)
11046 int rec
= stack
->ninsn
;
11047 assert (!istack_full (stack
));
11048 stack
->insn
[rec
] = *insn
;
11053 /* Clear space for the next TInsn on the IStack and return a pointer
11054 to it. It is an error to call this if istack_full () is TRUE. */
11057 istack_push_space (IStack
*stack
)
11059 int rec
= stack
->ninsn
;
11061 assert (!istack_full (stack
));
11062 insn
= &stack
->insn
[rec
];
11063 memset (insn
, 0, sizeof (TInsn
));
11069 /* Remove the last pushed instruction. It is an error to call this if
11070 istack_empty () returns TRUE. */
11073 istack_pop (IStack
*stack
)
11075 int rec
= stack
->ninsn
- 1;
11076 assert (!istack_empty (stack
));
11078 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11082 /* TInsn functions. */
11085 tinsn_init (TInsn
*dst
)
11087 memset (dst
, 0, sizeof (TInsn
));
11091 /* Get the ``num''th token of the TInsn.
11092 It is illegal to call this if num > insn->ntoks. */
11095 tinsn_get_tok (TInsn
*insn
, int num
)
11097 assert (num
< insn
->ntok
);
11098 return &insn
->tok
[num
];
11102 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11105 tinsn_has_symbolic_operands (const TInsn
*insn
)
11108 int n
= insn
->ntok
;
11110 assert (insn
->insn_type
== ITYPE_INSN
);
11112 for (i
= 0; i
< n
; ++i
)
11114 switch (insn
->tok
[i
].X_op
)
11128 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11130 xtensa_isa isa
= xtensa_default_isa
;
11132 int n
= insn
->ntok
;
11134 assert (insn
->insn_type
== ITYPE_INSN
);
11136 for (i
= 0; i
< n
; ++i
)
11138 switch (insn
->tok
[i
].X_op
)
11146 /* Errors for these types are caught later. */
11151 /* Symbolic immediates are only allowed on the last immediate
11152 operand. At this time, CONST16 is the only opcode where we
11153 support non-PC-relative relocations. (It isn't necessary
11154 to complain about non-PC-relative relocations here, but
11155 otherwise, no error is reported until the relocations are
11156 generated, and the assembler won't get that far if there
11157 are any other errors. It's nice to see all the problems
11159 if (i
!= get_relaxable_immed (insn
->opcode
)
11160 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11161 && insn
->opcode
!= xtensa_const16_opcode
))
11163 as_bad (_("invalid symbolic operand %d on '%s'"),
11164 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11173 /* For assembly code with complex expressions (e.g. subtraction),
11174 we have to build them in the literal pool so that
11175 their results are calculated correctly after relaxation.
11176 The relaxation only handles expressions that
11177 boil down to SYMBOL + OFFSET. */
11180 tinsn_has_complex_operands (const TInsn
*insn
)
11183 int n
= insn
->ntok
;
11184 assert (insn
->insn_type
== ITYPE_INSN
);
11185 for (i
= 0; i
< n
; ++i
)
11187 switch (insn
->tok
[i
].X_op
)
11203 /* Convert the constant operands in the tinsn to insnbuf.
11204 Return TRUE if there is a symbol in the immediate field.
11206 Before this is called,
11207 1) the number of operands are correct
11208 2) the tinsn is a ITYPE_INSN
11209 3) ONLY the relaxable_ is built
11210 4) All operands are O_constant, O_symbol. All constants fit
11211 The return value tells whether there are any remaining O_symbols. */
11214 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11216 static xtensa_insnbuf slotbuf
= 0;
11217 xtensa_isa isa
= xtensa_default_isa
;
11218 xtensa_opcode opcode
= tinsn
->opcode
;
11219 xtensa_format fmt
= xg_get_single_format (opcode
);
11220 bfd_boolean has_fixup
= FALSE
;
11221 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11228 slotbuf
= xtensa_insnbuf_alloc (isa
);
11230 assert (tinsn
->insn_type
== ITYPE_INSN
);
11231 if (noperands
!= tinsn
->ntok
)
11232 as_fatal (_("operand number mismatch"));
11234 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11235 as_fatal (_("cannot encode opcode"));
11237 for (i
= 0; i
< noperands
; ++i
)
11239 expressionS
*expr
= &tinsn
->tok
[i
];
11240 switch (expr
->X_op
)
11243 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11245 /* The register number has already been checked in
11246 expression_maybe_register, so we don't need to check here. */
11247 opnd_value
= expr
->X_add_number
;
11248 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11249 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11250 slotbuf
, opnd_value
);
11254 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11256 as_where (&file_name
, &line
);
11257 /* It is a constant and we called this function,
11258 then we have to try to fit it. */
11259 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11260 expr
->X_add_number
, file_name
, line
);
11269 xtensa_format_encode (isa
, fmt
, insnbuf
);
11270 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11276 /* Convert the constant operands in the tinsn to slotbuf.
11277 Return TRUE if there is a symbol in the immediate field.
11278 (Eventually this should replace tinsn_to_insnbuf.) */
11280 /* Before this is called,
11281 1) the number of operands are correct
11282 2) the tinsn is a ITYPE_INSN
11283 3) ONLY the relaxable_ is built
11284 4) All operands are
11285 O_constant, O_symbol
11288 The return value tells whether there are any remaining O_symbols. */
11291 tinsn_to_slotbuf (xtensa_format fmt
,
11294 xtensa_insnbuf slotbuf
)
11296 xtensa_isa isa
= xtensa_default_isa
;
11297 xtensa_opcode opcode
= tinsn
->opcode
;
11298 bfd_boolean has_fixup
= FALSE
;
11299 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11302 *((int *) &slotbuf
[0]) = 0;
11303 *((int *) &slotbuf
[1]) = 0;
11304 assert (tinsn
->insn_type
== ITYPE_INSN
);
11305 if (noperands
!= tinsn
->ntok
)
11306 as_fatal (_("operand number mismatch"));
11308 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11310 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11311 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11315 for (i
= 0; i
< noperands
; i
++)
11317 expressionS
*expr
= &tinsn
->tok
[i
];
11323 switch (expr
->X_op
)
11326 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11328 /* The register number has already been checked in
11329 expression_maybe_register, so we don't need to check here. */
11330 opnd_value
= expr
->X_add_number
;
11331 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11332 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11335 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11339 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11341 as_where (&file_name
, &line
);
11342 /* It is a constant and we called this function
11343 then we have to try to fit it. */
11344 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11345 expr
->X_add_number
, file_name
, line
);
11358 /* Check the instruction arguments. Return TRUE on failure. */
11361 tinsn_check_arguments (const TInsn
*insn
)
11363 xtensa_isa isa
= xtensa_default_isa
;
11364 xtensa_opcode opcode
= insn
->opcode
;
11366 if (opcode
== XTENSA_UNDEFINED
)
11368 as_bad (_("invalid opcode"));
11372 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11374 as_bad (_("too few operands"));
11378 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11380 as_bad (_("too many operands"));
11387 /* Load an instruction from its encoded form. */
11390 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11394 xg_init_vinsn (&vinsn
);
11395 vinsn_from_chars (&vinsn
, f
);
11397 *tinsn
= vinsn
.slots
[slot
];
11398 xg_free_vinsn (&vinsn
);
11403 tinsn_from_insnbuf (TInsn
*tinsn
,
11404 xtensa_insnbuf slotbuf
,
11409 xtensa_isa isa
= xtensa_default_isa
;
11411 /* Find the immed. */
11412 tinsn_init (tinsn
);
11413 tinsn
->insn_type
= ITYPE_INSN
;
11414 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11415 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11416 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11417 for (i
= 0; i
< tinsn
->ntok
; i
++)
11419 set_expr_const (&tinsn
->tok
[i
],
11420 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11421 tinsn
->opcode
, i
));
11426 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11429 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11431 xtensa_opcode opcode
= tinsn
->opcode
;
11434 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11436 opnum
= get_relaxable_immed (opcode
);
11437 assert (opnum
>= 0);
11438 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11440 set_expr_symbol_offset_diff
11441 (&tinsn
->tok
[opnum
],
11442 fragP
->tc_frag_data
.slot_symbols
[slot
],
11443 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11444 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11448 set_expr_symbol_offset
11449 (&tinsn
->tok
[opnum
],
11450 fragP
->tc_frag_data
.slot_symbols
[slot
],
11451 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11458 get_num_stack_text_bytes (IStack
*istack
)
11461 int text_bytes
= 0;
11463 for (i
= 0; i
< istack
->ninsn
; i
++)
11465 TInsn
*tinsn
= &istack
->insn
[i
];
11466 if (tinsn
->insn_type
== ITYPE_INSN
)
11467 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11474 get_num_stack_literal_bytes (IStack
*istack
)
11479 for (i
= 0; i
< istack
->ninsn
; i
++)
11481 TInsn
*tinsn
= &istack
->insn
[i
];
11482 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11489 /* vliw_insn functions. */
11492 xg_init_vinsn (vliw_insn
*v
)
11495 xtensa_isa isa
= xtensa_default_isa
;
11497 xg_clear_vinsn (v
);
11499 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11500 if (v
->insnbuf
== NULL
)
11501 as_fatal (_("out of memory"));
11503 for (i
= 0; i
< MAX_SLOTS
; i
++)
11505 tinsn_init (&v
->slots
[i
]);
11506 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11507 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11508 if (v
->slotbuf
[i
] == NULL
)
11509 as_fatal (_("out of memory"));
11515 xg_clear_vinsn (vliw_insn
*v
)
11518 v
->format
= XTENSA_UNDEFINED
;
11520 v
->inside_bundle
= FALSE
;
11522 if (xt_saved_debug_type
!= DEBUG_NONE
)
11523 debug_type
= xt_saved_debug_type
;
11525 for (i
= 0; i
< MAX_SLOTS
; i
++)
11527 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
11528 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11534 vinsn_has_specific_opcodes (vliw_insn
*v
)
11538 for (i
= 0; i
< v
->num_slots
; i
++)
11540 if (v
->slots
[i
].is_specific_opcode
)
11548 xg_free_vinsn (vliw_insn
*v
)
11551 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11552 for (i
= 0; i
< MAX_SLOTS
; i
++)
11553 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11557 /* Before this is called, we should have
11558 filled out the following fields:
11560 1) the number of operands for each opcode are correct
11561 2) the tinsn in the slots are ITYPE_INSN
11562 3) ONLY the relaxable_ is built
11563 4) All operands are
11564 O_constant, O_symbol
11567 The return value tells whether there are any remaining O_symbols. */
11570 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11573 bfd_boolean record_fixup
)
11575 xtensa_isa isa
= xtensa_default_isa
;
11576 xtensa_format fmt
= vinsn
->format
;
11577 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11579 bfd_boolean has_fixup
= FALSE
;
11581 xtensa_format_encode (isa
, fmt
, insnbuf
);
11583 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11585 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11586 bfd_boolean tinsn_has_fixup
=
11587 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11588 vinsn
->slotbuf
[slot
]);
11590 xtensa_format_set_slot (isa
, fmt
, slot
,
11591 insnbuf
, vinsn
->slotbuf
[slot
]);
11592 /* tinsn_has_fixup tracks if there is a fixup at all.
11593 record_fixup controls globally. I.E., we use this
11594 function from several places, some of which are after
11595 fixups have already been recorded. Finally,
11596 tinsn->record_fixup controls based on the individual ops,
11597 which may or may not need it based on the relaxation
11599 if (tinsn_has_fixup
&& record_fixup
)
11602 xtensa_opcode opcode
= tinsn
->opcode
;
11603 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11606 for (i
= 0; i
< noperands
; i
++)
11608 expressionS
* expr
= &tinsn
->tok
[i
];
11609 switch (expr
->X_op
)
11614 if (get_relaxable_immed (opcode
) == i
)
11616 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11618 if (!xg_add_opcode_fix
11619 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11620 frag_offset
- fragP
->fr_literal
))
11621 as_bad (_("instruction with constant operands does not fit"));
11625 tinsn
->symbol
= expr
->X_add_symbol
;
11626 tinsn
->offset
= expr
->X_add_number
;
11630 as_bad (_("invalid operand %d on '%s'"),
11631 i
, xtensa_opcode_name (isa
, opcode
));
11639 if (get_relaxable_immed (opcode
) == i
)
11641 if (tinsn
->record_fix
)
11642 as_bad (_("invalid subtract operand"));
11645 tinsn
->symbol
= expr
->X_add_symbol
;
11646 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11647 tinsn
->offset
= expr
->X_add_number
;
11651 as_bad (_("invalid operand %d on '%s'"),
11652 i
, xtensa_opcode_name (isa
, opcode
));
11656 as_bad (_("invalid expression for operand %d on '%s'"),
11657 i
, xtensa_opcode_name (isa
, opcode
));
11669 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11671 static xtensa_insnbuf insnbuf
= NULL
;
11672 static xtensa_insnbuf slotbuf
= NULL
;
11675 xtensa_isa isa
= xtensa_default_isa
;
11679 insnbuf
= xtensa_insnbuf_alloc (isa
);
11680 slotbuf
= xtensa_insnbuf_alloc (isa
);
11683 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11684 fmt
= xtensa_format_decode (isa
, insnbuf
);
11685 if (fmt
== XTENSA_UNDEFINED
)
11686 as_fatal (_("cannot decode instruction format"));
11687 vinsn
->format
= fmt
;
11688 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11690 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11692 TInsn
*tinsn
= &vinsn
->slots
[i
];
11693 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11694 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11699 /* Expression utilities. */
11701 /* Return TRUE if the expression is an integer constant. */
11704 expr_is_const (const expressionS
*s
)
11706 return (s
->X_op
== O_constant
);
11710 /* Get the expression constant.
11711 Calling this is illegal if expr_is_const () returns TRUE. */
11714 get_expr_const (const expressionS
*s
)
11716 assert (expr_is_const (s
));
11717 return s
->X_add_number
;
11721 /* Set the expression to a constant value. */
11724 set_expr_const (expressionS
*s
, offsetT val
)
11726 s
->X_op
= O_constant
;
11727 s
->X_add_number
= val
;
11728 s
->X_add_symbol
= NULL
;
11729 s
->X_op_symbol
= NULL
;
11734 expr_is_register (const expressionS
*s
)
11736 return (s
->X_op
== O_register
);
11740 /* Get the expression constant.
11741 Calling this is illegal if expr_is_const () returns TRUE. */
11744 get_expr_register (const expressionS
*s
)
11746 assert (expr_is_register (s
));
11747 return s
->X_add_number
;
11751 /* Set the expression to a symbol + constant offset. */
11754 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11756 s
->X_op
= O_symbol
;
11757 s
->X_add_symbol
= sym
;
11758 s
->X_op_symbol
= NULL
; /* unused */
11759 s
->X_add_number
= offset
;
11763 /* Set the expression to symbol - minus_sym + offset. */
11766 set_expr_symbol_offset_diff (expressionS
*s
,
11768 symbolS
*minus_sym
,
11771 s
->X_op
= O_subtract
;
11772 s
->X_add_symbol
= sym
;
11773 s
->X_op_symbol
= minus_sym
; /* unused */
11774 s
->X_add_number
= offset
;
11778 /* Return TRUE if the two expressions are equal. */
11781 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11783 if (s1
->X_op
!= s2
->X_op
)
11785 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11787 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11789 if (s1
->X_add_number
!= s2
->X_add_number
)
11796 copy_expr (expressionS
*dst
, const expressionS
*src
)
11798 memcpy (dst
, src
, sizeof (expressionS
));
11802 /* Support for the "--rename-section" option. */
11804 struct rename_section_struct
11808 struct rename_section_struct
*next
;
11811 static struct rename_section_struct
*section_rename
;
11814 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11815 entries to the section_rename list. Note: Specifying multiple
11816 renamings separated by colons is not documented and is retained only
11817 for backward compatibility. */
11820 build_section_rename (const char *arg
)
11822 struct rename_section_struct
*r
;
11823 char *this_arg
= NULL
;
11824 char *next_arg
= NULL
;
11826 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11828 char *old_name
, *new_name
;
11832 next_arg
= strchr (this_arg
, ':');
11840 old_name
= this_arg
;
11841 new_name
= strchr (this_arg
, '=');
11843 if (*old_name
== '\0')
11845 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11848 if (!new_name
|| new_name
[1] == '\0')
11850 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11857 /* Check for invalid section renaming. */
11858 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11860 if (strcmp (r
->old_name
, old_name
) == 0)
11861 as_bad (_("section %s renamed multiple times"), old_name
);
11862 if (strcmp (r
->new_name
, new_name
) == 0)
11863 as_bad (_("multiple sections remapped to output section %s"),
11868 r
= (struct rename_section_struct
*)
11869 xmalloc (sizeof (struct rename_section_struct
));
11870 r
->old_name
= xstrdup (old_name
);
11871 r
->new_name
= xstrdup (new_name
);
11872 r
->next
= section_rename
;
11873 section_rename
= r
;
11879 xtensa_section_rename (char *name
)
11881 struct rename_section_struct
*r
= section_rename
;
11883 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11885 if (strcmp (r
->old_name
, name
) == 0)
11886 return r
->new_name
;