1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "xtensa-istack.h"
29 #include "dwarf2dbg.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 /* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
358 struct suffix_reloc_map
362 bfd_reloc_code_real_type reloc
;
363 unsigned char operator;
366 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
368 static struct suffix_reloc_map suffix_relocs
[] =
370 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
371 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
372 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
373 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
387 directive_literal_prefix
,
389 directive_absolute_literals
,
390 directive_last_directive
396 bfd_boolean can_be_negated
;
399 const directive_infoS directive_info
[] =
402 { "literal", FALSE
},
404 { "transform", TRUE
},
405 { "freeregs", FALSE
},
406 { "longcalls", TRUE
},
407 { "literal_prefix", FALSE
},
408 { "schedule", TRUE
},
409 { "absolute-literals", TRUE
}
412 bfd_boolean directive_state
[] =
416 #if !XCHAL_HAVE_DENSITY
421 TRUE
, /* transform */
422 FALSE
, /* freeregs */
423 FALSE
, /* longcalls */
424 FALSE
, /* literal_prefix */
425 FALSE
, /* schedule */
426 #if XSHAL_USE_ABSOLUTE_LITERALS
427 TRUE
/* absolute_literals */
429 FALSE
/* absolute_literals */
434 /* Directive functions. */
436 static void xtensa_begin_directive (int);
437 static void xtensa_end_directive (int);
438 static void xtensa_literal_prefix (void);
439 static void xtensa_literal_position (int);
440 static void xtensa_literal_pseudo (int);
441 static void xtensa_frequency_pseudo (int);
442 static void xtensa_elf_cons (int);
444 /* Parsing and Idiom Translation. */
446 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
448 /* Various Other Internal Functions. */
450 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
451 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
452 static void xtensa_mark_literal_pool_location (void);
453 static addressT
get_expanded_loop_offset (xtensa_opcode
);
454 static fragS
*get_literal_pool_location (segT
);
455 static void set_literal_pool_location (segT
, fragS
*);
456 static void xtensa_set_frag_assembly_state (fragS
*);
457 static void finish_vinsn (vliw_insn
*);
458 static bfd_boolean
emit_single_op (TInsn
*);
459 static int total_frag_text_expansion (fragS
*);
461 /* Alignment Functions. */
463 static int get_text_align_power (unsigned);
464 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
465 static int branch_align_power (segT
);
467 /* Helpers for xtensa_relax_frag(). */
469 static long relax_frag_add_nop (fragS
*);
471 /* Accessors for additional per-subsegment information. */
473 static unsigned get_last_insn_flags (segT
, subsegT
);
474 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
475 static float get_subseg_total_freq (segT
, subsegT
);
476 static float get_subseg_target_freq (segT
, subsegT
);
477 static void set_subseg_freq (segT
, subsegT
, float, float);
479 /* Segment list functions. */
481 static void xtensa_move_literals (void);
482 static void xtensa_reorder_segments (void);
483 static void xtensa_switch_to_literal_fragment (emit_state
*);
484 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
485 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
486 static void xtensa_restore_emit_state (emit_state
*);
487 static segT
cache_literal_section (bfd_boolean
);
489 /* Import from elf32-xtensa.c in BFD library. */
491 extern asection
*xtensa_get_property_section (asection
*, const char *);
493 /* op_placement_info functions. */
495 static void init_op_placement_info_table (void);
496 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
497 static int xg_get_single_size (xtensa_opcode
);
498 static xtensa_format
xg_get_single_format (xtensa_opcode
);
499 static int xg_get_single_slot (xtensa_opcode
);
501 /* TInsn and IStack functions. */
503 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
504 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
505 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
506 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
507 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
508 static void tinsn_from_chars (TInsn
*, char *, int);
509 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
510 static int get_num_stack_text_bytes (IStack
*);
511 static int get_num_stack_literal_bytes (IStack
*);
513 /* vliw_insn functions. */
515 static void xg_init_vinsn (vliw_insn
*);
516 static void xg_clear_vinsn (vliw_insn
*);
517 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
518 static void xg_free_vinsn (vliw_insn
*);
519 static bfd_boolean vinsn_to_insnbuf
520 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
521 static void vinsn_from_chars (vliw_insn
*, char *);
523 /* Expression Utilities. */
525 bfd_boolean
expr_is_const (const expressionS
*);
526 offsetT
get_expr_const (const expressionS
*);
527 void set_expr_const (expressionS
*, offsetT
);
528 bfd_boolean
expr_is_register (const expressionS
*);
529 offsetT
get_expr_register (const expressionS
*);
530 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
531 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
532 static void copy_expr (expressionS
*, const expressionS
*);
534 /* Section renaming. */
536 static void build_section_rename (const char *);
539 /* ISA imported from bfd. */
540 extern xtensa_isa xtensa_default_isa
;
542 extern int target_big_endian
;
544 static xtensa_opcode xtensa_addi_opcode
;
545 static xtensa_opcode xtensa_addmi_opcode
;
546 static xtensa_opcode xtensa_call0_opcode
;
547 static xtensa_opcode xtensa_call4_opcode
;
548 static xtensa_opcode xtensa_call8_opcode
;
549 static xtensa_opcode xtensa_call12_opcode
;
550 static xtensa_opcode xtensa_callx0_opcode
;
551 static xtensa_opcode xtensa_callx4_opcode
;
552 static xtensa_opcode xtensa_callx8_opcode
;
553 static xtensa_opcode xtensa_callx12_opcode
;
554 static xtensa_opcode xtensa_const16_opcode
;
555 static xtensa_opcode xtensa_entry_opcode
;
556 static xtensa_opcode xtensa_movi_opcode
;
557 static xtensa_opcode xtensa_movi_n_opcode
;
558 static xtensa_opcode xtensa_isync_opcode
;
559 static xtensa_opcode xtensa_jx_opcode
;
560 static xtensa_opcode xtensa_l32r_opcode
;
561 static xtensa_opcode xtensa_loop_opcode
;
562 static xtensa_opcode xtensa_loopnez_opcode
;
563 static xtensa_opcode xtensa_loopgtz_opcode
;
564 static xtensa_opcode xtensa_nop_opcode
;
565 static xtensa_opcode xtensa_nop_n_opcode
;
566 static xtensa_opcode xtensa_or_opcode
;
567 static xtensa_opcode xtensa_ret_opcode
;
568 static xtensa_opcode xtensa_ret_n_opcode
;
569 static xtensa_opcode xtensa_retw_opcode
;
570 static xtensa_opcode xtensa_retw_n_opcode
;
571 static xtensa_opcode xtensa_rsr_lcount_opcode
;
572 static xtensa_opcode xtensa_waiti_opcode
;
575 /* Command-line Options. */
577 bfd_boolean use_literal_section
= TRUE
;
578 static bfd_boolean align_targets
= TRUE
;
579 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
580 static bfd_boolean has_a0_b_retw
= FALSE
;
581 static bfd_boolean workaround_a0_b_retw
= FALSE
;
582 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
583 static bfd_boolean workaround_short_loop
= FALSE
;
584 static bfd_boolean maybe_has_short_loop
= FALSE
;
585 static bfd_boolean workaround_close_loop_end
= FALSE
;
586 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
587 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
589 /* When workaround_short_loops is TRUE, all loops with early exits must
590 have at least 3 instructions. workaround_all_short_loops is a modifier
591 to the workaround_short_loop flag. In addition to the
592 workaround_short_loop actions, all straightline loopgtz and loopnez
593 must have at least 3 instructions. */
595 static bfd_boolean workaround_all_short_loops
= FALSE
;
599 xtensa_setup_hw_workarounds (int earliest
, int latest
)
601 if (earliest
> latest
)
602 as_fatal (_("illegal range of target hardware versions"));
604 /* Enable all workarounds for pre-T1050.0 hardware. */
605 if (earliest
< 105000 || latest
< 105000)
607 workaround_a0_b_retw
|= TRUE
;
608 workaround_b_j_loop_end
|= TRUE
;
609 workaround_short_loop
|= TRUE
;
610 workaround_close_loop_end
|= TRUE
;
611 workaround_all_short_loops
|= TRUE
;
612 enforce_three_byte_loop_align
= TRUE
;
619 option_density
= OPTION_MD_BASE
,
626 option_no_link_relax
,
634 option_text_section_literals
,
635 option_no_text_section_literals
,
637 option_absolute_literals
,
638 option_no_absolute_literals
,
640 option_align_targets
,
641 option_no_align_targets
,
643 option_warn_unaligned_targets
,
648 option_workaround_a0_b_retw
,
649 option_no_workaround_a0_b_retw
,
651 option_workaround_b_j_loop_end
,
652 option_no_workaround_b_j_loop_end
,
654 option_workaround_short_loop
,
655 option_no_workaround_short_loop
,
657 option_workaround_all_short_loops
,
658 option_no_workaround_all_short_loops
,
660 option_workaround_close_loop_end
,
661 option_no_workaround_close_loop_end
,
663 option_no_workarounds
,
665 option_rename_section_name
,
668 option_prefer_const16
,
670 option_target_hardware
673 const char *md_shortopts
= "";
675 struct option md_longopts
[] =
677 { "density", no_argument
, NULL
, option_density
},
678 { "no-density", no_argument
, NULL
, option_no_density
},
680 /* Both "relax" and "generics" are deprecated and treated as equivalent
681 to the "transform" option. */
682 { "relax", no_argument
, NULL
, option_relax
},
683 { "no-relax", no_argument
, NULL
, option_no_relax
},
684 { "generics", no_argument
, NULL
, option_generics
},
685 { "no-generics", no_argument
, NULL
, option_no_generics
},
687 { "transform", no_argument
, NULL
, option_transform
},
688 { "no-transform", no_argument
, NULL
, option_no_transform
},
689 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
690 { "no-text-section-literals", no_argument
, NULL
,
691 option_no_text_section_literals
},
692 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
693 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
694 /* This option was changed from -align-target to -target-align
695 because it conflicted with the "-al" option. */
696 { "target-align", no_argument
, NULL
, option_align_targets
},
697 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
698 { "warn-unaligned-targets", no_argument
, NULL
,
699 option_warn_unaligned_targets
},
700 { "longcalls", no_argument
, NULL
, option_longcalls
},
701 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
703 { "no-workaround-a0-b-retw", no_argument
, NULL
,
704 option_no_workaround_a0_b_retw
},
705 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
707 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
708 option_no_workaround_b_j_loop_end
},
709 { "workaround-b-j-loop-end", no_argument
, NULL
,
710 option_workaround_b_j_loop_end
},
712 { "no-workaround-short-loops", no_argument
, NULL
,
713 option_no_workaround_short_loop
},
714 { "workaround-short-loops", no_argument
, NULL
,
715 option_workaround_short_loop
},
717 { "no-workaround-all-short-loops", no_argument
, NULL
,
718 option_no_workaround_all_short_loops
},
719 { "workaround-all-short-loop", no_argument
, NULL
,
720 option_workaround_all_short_loops
},
722 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
723 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
725 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
727 { "no-workaround-close-loop-end", no_argument
, NULL
,
728 option_no_workaround_close_loop_end
},
729 { "workaround-close-loop-end", no_argument
, NULL
,
730 option_workaround_close_loop_end
},
732 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
734 { "link-relax", no_argument
, NULL
, option_link_relax
},
735 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
737 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
739 { NULL
, no_argument
, NULL
, 0 }
742 size_t md_longopts_size
= sizeof md_longopts
;
746 md_parse_option (int c
, char *arg
)
751 as_warn (_("--density option is ignored"));
753 case option_no_density
:
754 as_warn (_("--no-density option is ignored"));
756 case option_link_relax
:
759 case option_no_link_relax
:
762 case option_generics
:
763 as_warn (_("--generics is deprecated; use --transform instead"));
764 return md_parse_option (option_transform
, arg
);
765 case option_no_generics
:
766 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
767 return md_parse_option (option_no_transform
, arg
);
769 as_warn (_("--relax is deprecated; use --transform instead"));
770 return md_parse_option (option_transform
, arg
);
771 case option_no_relax
:
772 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
773 return md_parse_option (option_no_transform
, arg
);
774 case option_longcalls
:
775 directive_state
[directive_longcalls
] = TRUE
;
777 case option_no_longcalls
:
778 directive_state
[directive_longcalls
] = FALSE
;
780 case option_text_section_literals
:
781 use_literal_section
= FALSE
;
783 case option_no_text_section_literals
:
784 use_literal_section
= TRUE
;
786 case option_absolute_literals
:
787 if (!absolute_literals_supported
)
789 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
792 directive_state
[directive_absolute_literals
] = TRUE
;
794 case option_no_absolute_literals
:
795 directive_state
[directive_absolute_literals
] = FALSE
;
798 case option_workaround_a0_b_retw
:
799 workaround_a0_b_retw
= TRUE
;
801 case option_no_workaround_a0_b_retw
:
802 workaround_a0_b_retw
= FALSE
;
804 case option_workaround_b_j_loop_end
:
805 workaround_b_j_loop_end
= TRUE
;
807 case option_no_workaround_b_j_loop_end
:
808 workaround_b_j_loop_end
= FALSE
;
811 case option_workaround_short_loop
:
812 workaround_short_loop
= TRUE
;
814 case option_no_workaround_short_loop
:
815 workaround_short_loop
= FALSE
;
818 case option_workaround_all_short_loops
:
819 workaround_all_short_loops
= TRUE
;
821 case option_no_workaround_all_short_loops
:
822 workaround_all_short_loops
= FALSE
;
825 case option_workaround_close_loop_end
:
826 workaround_close_loop_end
= TRUE
;
828 case option_no_workaround_close_loop_end
:
829 workaround_close_loop_end
= FALSE
;
832 case option_no_workarounds
:
833 workaround_a0_b_retw
= FALSE
;
834 workaround_b_j_loop_end
= FALSE
;
835 workaround_short_loop
= FALSE
;
836 workaround_all_short_loops
= FALSE
;
837 workaround_close_loop_end
= FALSE
;
840 case option_align_targets
:
841 align_targets
= TRUE
;
843 case option_no_align_targets
:
844 align_targets
= FALSE
;
847 case option_warn_unaligned_targets
:
848 warn_unaligned_branch_targets
= TRUE
;
851 case option_rename_section_name
:
852 build_section_rename (arg
);
856 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
857 should be emitted or not. FIXME: Not implemented. */
860 case option_prefer_l32r
:
862 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
866 case option_prefer_const16
:
868 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
872 case option_target_hardware
:
874 int earliest
, latest
= 0;
875 if (*arg
== 0 || *arg
== '-')
876 as_fatal (_("invalid target hardware version"));
878 earliest
= strtol (arg
, &arg
, 0);
882 else if (*arg
== '-')
885 as_fatal (_("invalid target hardware version"));
886 latest
= strtol (arg
, &arg
, 0);
889 as_fatal (_("invalid target hardware version"));
891 xtensa_setup_hw_workarounds (earliest
, latest
);
895 case option_transform
:
896 /* This option has no affect other than to use the defaults,
897 which are already set. */
900 case option_no_transform
:
901 /* This option turns off all transformations of any kind.
902 However, because we want to preserve the state of other
903 directives, we only change its own field. Thus, before
904 you perform any transformation, always check if transform
905 is available. If you use the functions we provide for this
906 purpose, you will be ok. */
907 directive_state
[directive_transform
] = FALSE
;
917 md_show_usage (FILE *stream
)
921 --[no-]text-section-literals\n\
922 [Do not] put literals in the text section\n\
923 --[no-]absolute-literals\n\
924 [Do not] default to use non-PC-relative literals\n\
925 --[no-]target-align [Do not] try to align branch targets\n\
926 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
927 --[no-]transform [Do not] transform instructions\n\
928 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
932 /* Functions related to the list of current label symbols. */
935 xtensa_add_insn_label (symbolS
*sym
)
939 if (!free_insn_labels
)
940 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
943 l
= free_insn_labels
;
944 free_insn_labels
= l
->next
;
948 l
->next
= insn_labels
;
954 xtensa_clear_insn_labels (void)
958 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
966 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
970 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
972 symbolS
*lit_sym
= lit
->sym
;
973 S_SET_VALUE (lit_sym
, new_offset
);
974 symbol_set_frag (lit_sym
, new_frag
);
979 /* Directive data and functions. */
981 typedef struct state_stackS_struct
983 directiveE directive
;
985 bfd_boolean old_state
;
989 struct state_stackS_struct
*prev
;
992 state_stackS
*directive_state_stack
;
994 const pseudo_typeS md_pseudo_table
[] =
996 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
997 { "literal_position", xtensa_literal_position
, 0 },
998 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
999 { "long", xtensa_elf_cons
, 4 },
1000 { "word", xtensa_elf_cons
, 4 },
1001 { "short", xtensa_elf_cons
, 2 },
1002 { "begin", xtensa_begin_directive
, 0 },
1003 { "end", xtensa_end_directive
, 0 },
1004 { "literal", xtensa_literal_pseudo
, 0 },
1005 { "frequency", xtensa_frequency_pseudo
, 0 },
1011 use_transform (void)
1013 /* After md_end, you should be checking frag by frag, rather
1014 than state directives. */
1015 assert (!past_xtensa_end
);
1016 return directive_state
[directive_transform
];
1021 do_align_targets (void)
1023 /* Do not use this function after md_end; just look at align_targets
1024 instead. There is no target-align directive, so alignment is either
1025 enabled for all frags or not done at all. */
1026 assert (!past_xtensa_end
);
1027 return align_targets
&& use_transform ();
1032 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1036 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1038 as_where (&file
, &line
);
1040 stack
->directive
= directive
;
1041 stack
->negated
= negated
;
1042 stack
->old_state
= directive_state
[directive
];
1045 stack
->datum
= datum
;
1046 stack
->prev
= directive_state_stack
;
1047 directive_state_stack
= stack
;
1049 directive_state
[directive
] = !negated
;
1054 directive_pop (directiveE
*directive
,
1055 bfd_boolean
*negated
,
1060 state_stackS
*top
= directive_state_stack
;
1062 if (!directive_state_stack
)
1064 as_bad (_("unmatched end directive"));
1065 *directive
= directive_none
;
1069 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1070 *directive
= top
->directive
;
1071 *negated
= top
->negated
;
1074 *datum
= top
->datum
;
1075 directive_state_stack
= top
->prev
;
1081 directive_balance (void)
1083 while (directive_state_stack
)
1085 directiveE directive
;
1086 bfd_boolean negated
;
1091 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1092 as_warn_where ((char *) file
, line
,
1093 _(".begin directive with no matching .end directive"));
1099 inside_directive (directiveE dir
)
1101 state_stackS
*top
= directive_state_stack
;
1103 while (top
&& top
->directive
!= dir
)
1106 return (top
!= NULL
);
1111 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1115 char *directive_string
;
1117 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1122 input_line_pointer
+= 3;
1125 len
= strspn (input_line_pointer
,
1126 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1128 /* This code is a hack to make .begin [no-][generics|relax] exactly
1129 equivalent to .begin [no-]transform. We should remove it when
1130 we stop accepting those options. */
1132 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1134 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1135 directive_string
= "transform";
1137 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1139 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1140 directive_string
= "transform";
1143 directive_string
= input_line_pointer
;
1145 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1147 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1149 input_line_pointer
+= len
;
1150 *directive
= (directiveE
) i
;
1151 if (*negated
&& !directive_info
[i
].can_be_negated
)
1152 as_bad (_("directive %s cannot be negated"),
1153 directive_info
[i
].name
);
1158 as_bad (_("unknown directive"));
1159 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1164 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1166 directiveE directive
;
1167 bfd_boolean negated
;
1171 get_directive (&directive
, &negated
);
1172 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1174 discard_rest_of_line ();
1178 if (cur_vinsn
.inside_bundle
)
1179 as_bad (_("directives are not valid inside bundles"));
1183 case directive_literal
:
1184 if (!inside_directive (directive_literal
))
1186 /* Previous labels go with whatever follows this directive, not with
1187 the literal, so save them now. */
1188 saved_insn_labels
= insn_labels
;
1191 as_warn (_(".begin literal is deprecated; use .literal instead"));
1192 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1193 xtensa_switch_to_literal_fragment (state
);
1194 directive_push (directive_literal
, negated
, state
);
1197 case directive_literal_prefix
:
1198 /* Have to flush pending output because a movi relaxed to an l32r
1199 might produce a literal. */
1200 md_flush_pending_output ();
1201 /* Check to see if the current fragment is a literal
1202 fragment. If it is, then this operation is not allowed. */
1203 if (generating_literals
)
1205 as_bad (_("cannot set literal_prefix inside literal fragment"));
1209 /* Allocate the literal state for this section and push
1210 onto the directive stack. */
1211 ls
= xmalloc (sizeof (lit_state
));
1214 *ls
= default_lit_sections
;
1215 directive_push (directive_literal_prefix
, negated
, ls
);
1217 /* Process the new prefix. */
1218 xtensa_literal_prefix ();
1221 case directive_freeregs
:
1222 /* This information is currently unused, but we'll accept the statement
1223 and just discard the rest of the line. This won't check the syntax,
1224 but it will accept every correct freeregs directive. */
1225 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1226 directive_push (directive_freeregs
, negated
, 0);
1229 case directive_schedule
:
1230 md_flush_pending_output ();
1231 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1232 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1233 directive_push (directive_schedule
, negated
, 0);
1234 xtensa_set_frag_assembly_state (frag_now
);
1237 case directive_density
:
1238 as_warn (_(".begin [no-]density is ignored"));
1241 case directive_absolute_literals
:
1242 md_flush_pending_output ();
1243 if (!absolute_literals_supported
&& !negated
)
1245 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1248 xtensa_set_frag_assembly_state (frag_now
);
1249 directive_push (directive
, negated
, 0);
1253 md_flush_pending_output ();
1254 xtensa_set_frag_assembly_state (frag_now
);
1255 directive_push (directive
, negated
, 0);
1259 demand_empty_rest_of_line ();
1264 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1266 directiveE begin_directive
, end_directive
;
1267 bfd_boolean begin_negated
, end_negated
;
1271 emit_state
**state_ptr
;
1274 if (cur_vinsn
.inside_bundle
)
1275 as_bad (_("directives are not valid inside bundles"));
1277 get_directive (&end_directive
, &end_negated
);
1279 md_flush_pending_output ();
1281 switch (end_directive
)
1283 case (directiveE
) XTENSA_UNDEFINED
:
1284 discard_rest_of_line ();
1287 case directive_density
:
1288 as_warn (_(".end [no-]density is ignored"));
1289 demand_empty_rest_of_line ();
1292 case directive_absolute_literals
:
1293 if (!absolute_literals_supported
&& !end_negated
)
1295 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1296 demand_empty_rest_of_line ();
1305 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1306 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1307 (const void **) state_ptr
);
1309 if (begin_directive
!= directive_none
)
1311 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1313 as_bad (_("does not match begin %s%s at %s:%d"),
1314 begin_negated
? "no-" : "",
1315 directive_info
[begin_directive
].name
, file
, line
);
1319 switch (end_directive
)
1321 case directive_literal
:
1322 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1323 xtensa_restore_emit_state (state
);
1324 xtensa_set_frag_assembly_state (frag_now
);
1326 if (!inside_directive (directive_literal
))
1328 /* Restore the list of current labels. */
1329 xtensa_clear_insn_labels ();
1330 insn_labels
= saved_insn_labels
;
1334 case directive_literal_prefix
:
1335 /* Restore the default collection sections from saved state. */
1336 s
= (lit_state
*) state
;
1338 default_lit_sections
= *s
;
1340 /* Free the state storage. */
1341 free (s
->lit_prefix
);
1345 case directive_schedule
:
1346 case directive_freeregs
:
1350 xtensa_set_frag_assembly_state (frag_now
);
1356 demand_empty_rest_of_line ();
1360 /* Place an aligned literal fragment at the current location. */
1363 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1365 md_flush_pending_output ();
1367 if (inside_directive (directive_literal
))
1368 as_warn (_(".literal_position inside literal directive; ignoring"));
1369 xtensa_mark_literal_pool_location ();
1371 demand_empty_rest_of_line ();
1372 xtensa_clear_insn_labels ();
1376 /* Support .literal label, expr, ... */
1379 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1382 char *p
, *base_name
;
1386 if (inside_directive (directive_literal
))
1388 as_bad (_(".literal not allowed inside .begin literal region"));
1389 ignore_rest_of_line ();
1393 md_flush_pending_output ();
1395 /* Previous labels go with whatever follows this directive, not with
1396 the literal, so save them now. */
1397 saved_insn_labels
= insn_labels
;
1400 /* If we are using text-section literals, then this is the right value... */
1403 base_name
= input_line_pointer
;
1405 xtensa_switch_to_literal_fragment (&state
);
1407 /* ...but if we aren't using text-section-literals, then we
1408 need to put them in the section we just switched to. */
1409 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1412 /* All literals are aligned to four-byte boundaries. */
1413 frag_align (2, 0, 0);
1414 record_alignment (now_seg
, 2);
1416 c
= get_symbol_end ();
1417 /* Just after name is now '\0'. */
1418 p
= input_line_pointer
;
1422 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1424 as_bad (_("expected comma or colon after symbol name; "
1425 "rest of line ignored"));
1426 ignore_rest_of_line ();
1427 xtensa_restore_emit_state (&state
);
1435 input_line_pointer
++; /* skip ',' or ':' */
1437 xtensa_elf_cons (4);
1439 xtensa_restore_emit_state (&state
);
1441 /* Restore the list of current labels. */
1442 xtensa_clear_insn_labels ();
1443 insn_labels
= saved_insn_labels
;
1448 xtensa_literal_prefix (void)
1453 /* Parse the new prefix from the input_line_pointer. */
1455 len
= strspn (input_line_pointer
,
1456 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1457 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1459 /* Get a null-terminated copy of the name. */
1460 name
= xmalloc (len
+ 1);
1462 strncpy (name
, input_line_pointer
, len
);
1465 /* Skip the name in the input line. */
1466 input_line_pointer
+= len
;
1468 default_lit_sections
.lit_prefix
= name
;
1470 /* Clear cached literal sections, since the prefix has changed. */
1471 default_lit_sections
.lit_seg
= NULL
;
1472 default_lit_sections
.lit4_seg
= NULL
;
1476 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1479 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1481 float fall_through_f
, target_f
;
1483 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1484 if (fall_through_f
< 0)
1486 as_bad (_("fall through frequency must be greater than 0"));
1487 ignore_rest_of_line ();
1491 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1494 as_bad (_("branch target frequency must be greater than 0"));
1495 ignore_rest_of_line ();
1499 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1501 demand_empty_rest_of_line ();
1505 /* Like normal .long/.short/.word, except support @plt, etc.
1506 Clobbers input_line_pointer, checks end-of-line. */
1509 xtensa_elf_cons (int nbytes
)
1512 bfd_reloc_code_real_type reloc
;
1514 md_flush_pending_output ();
1516 if (cur_vinsn
.inside_bundle
)
1517 as_bad (_("directives are not valid inside bundles"));
1519 if (is_it_end_of_statement ())
1521 demand_empty_rest_of_line ();
1528 if (exp
.X_op
== O_symbol
1529 && *input_line_pointer
== '@'
1530 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1533 reloc_howto_type
*reloc_howto
=
1534 bfd_reloc_type_lookup (stdoutput
, reloc
);
1536 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1537 as_bad (_("unsupported relocation"));
1538 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1539 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1540 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1541 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1542 as_bad (_("opcode-specific %s relocation used outside "
1543 "an instruction"), reloc_howto
->name
);
1544 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1545 as_bad (_("%s relocations do not fit in %d bytes"),
1546 reloc_howto
->name
, nbytes
);
1549 char *p
= frag_more ((int) nbytes
);
1550 xtensa_set_frag_assembly_state (frag_now
);
1551 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1552 nbytes
, &exp
, 0, reloc
);
1556 emit_expr (&exp
, (unsigned int) nbytes
);
1558 while (*input_line_pointer
++ == ',');
1560 input_line_pointer
--; /* Put terminator back into stream. */
1561 demand_empty_rest_of_line ();
1565 /* Parsing and Idiom Translation. */
1567 /* Parse @plt, etc. and return the desired relocation. */
1568 static bfd_reloc_code_real_type
1569 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1576 struct suffix_reloc_map
*ptr
;
1579 return BFD_RELOC_NONE
;
1581 for (ch
= *str
, str2
= ident
;
1582 (str2
< ident
+ sizeof (ident
) - 1
1583 && (ISALNUM (ch
) || ch
== '@'));
1586 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1593 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1594 if (ch
== ptr
->suffix
[0]
1595 && len
== ptr
->length
1596 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1598 /* Now check for "identifier@suffix+constant". */
1599 if (*str
== '-' || *str
== '+')
1601 char *orig_line
= input_line_pointer
;
1602 expressionS new_exp
;
1604 input_line_pointer
= str
;
1605 expression (&new_exp
);
1606 if (new_exp
.X_op
== O_constant
)
1608 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1609 str
= input_line_pointer
;
1612 if (&input_line_pointer
!= str_p
)
1613 input_line_pointer
= orig_line
;
1620 return BFD_RELOC_UNUSED
;
1624 /* Find the matching operator type. */
1625 static unsigned char
1626 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1628 struct suffix_reloc_map
*sfx
;
1629 unsigned char operator = (unsigned char) -1;
1631 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1633 if (sfx
->reloc
== reloc
)
1635 operator = sfx
->operator;
1639 assert (operator != (unsigned char) -1);
1644 /* Find the matching reloc type. */
1645 static bfd_reloc_code_real_type
1646 map_operator_to_reloc (unsigned char operator)
1648 struct suffix_reloc_map
*sfx
;
1649 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1651 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1653 if (sfx
->operator == operator)
1660 if (reloc
== BFD_RELOC_UNUSED
)
1661 return BFD_RELOC_32
;
1668 expression_end (const char *name
)
1691 #define ERROR_REG_NUM ((unsigned) -1)
1694 tc_get_register (const char *prefix
)
1697 const char *next_expr
;
1698 const char *old_line_pointer
;
1701 old_line_pointer
= input_line_pointer
;
1703 if (*input_line_pointer
== '$')
1704 ++input_line_pointer
;
1706 /* Accept "sp" as a synonym for "a1". */
1707 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1708 && expression_end (input_line_pointer
+ 2))
1710 input_line_pointer
+= 2;
1711 return 1; /* AR[1] */
1714 while (*input_line_pointer
++ == *prefix
++)
1716 --input_line_pointer
;
1721 as_bad (_("bad register name: %s"), old_line_pointer
);
1722 return ERROR_REG_NUM
;
1725 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1727 as_bad (_("bad register number: %s"), input_line_pointer
);
1728 return ERROR_REG_NUM
;
1733 while (ISDIGIT ((int) *input_line_pointer
))
1734 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1736 if (!(next_expr
= expression_end (input_line_pointer
)))
1738 as_bad (_("bad register name: %s"), old_line_pointer
);
1739 return ERROR_REG_NUM
;
1742 input_line_pointer
= (char *) next_expr
;
1749 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1751 xtensa_isa isa
= xtensa_default_isa
;
1753 /* Check if this is an immediate operand. */
1754 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1756 bfd_reloc_code_real_type reloc
;
1757 segT t
= expression (tok
);
1758 if (t
== absolute_section
1759 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1761 assert (tok
->X_op
== O_constant
);
1762 tok
->X_op
= O_symbol
;
1763 tok
->X_add_symbol
= &abs_symbol
;
1766 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1767 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1770 if (reloc
== BFD_RELOC_UNUSED
)
1772 as_bad (_("unsupported relocation"));
1776 if (tok
->X_op
== O_constant
)
1780 case BFD_RELOC_LO16
:
1781 tok
->X_add_number
&= 0xffff;
1784 case BFD_RELOC_HI16
:
1785 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1792 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1797 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1798 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1800 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1803 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1804 as_bad (_("register number out of range"));
1807 tok
->X_op
= O_register
;
1808 tok
->X_add_symbol
= 0;
1809 tok
->X_add_number
= reg
;
1814 /* Split up the arguments for an opcode or pseudo-op. */
1817 tokenize_arguments (char **args
, char *str
)
1819 char *old_input_line_pointer
;
1820 bfd_boolean saw_comma
= FALSE
;
1821 bfd_boolean saw_arg
= FALSE
;
1822 bfd_boolean saw_colon
= FALSE
;
1824 char *arg_end
, *arg
;
1827 /* Save and restore input_line_pointer around this function. */
1828 old_input_line_pointer
= input_line_pointer
;
1829 input_line_pointer
= str
;
1831 while (*input_line_pointer
)
1834 switch (*input_line_pointer
)
1841 input_line_pointer
++;
1842 if (saw_comma
|| saw_colon
|| !saw_arg
)
1848 input_line_pointer
++;
1849 if (saw_comma
|| saw_colon
|| !saw_arg
)
1855 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1858 arg_end
= input_line_pointer
+ 1;
1859 while (!expression_end (arg_end
))
1862 arg_len
= arg_end
- input_line_pointer
;
1863 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1864 args
[num_args
] = arg
;
1868 strncpy (arg
, input_line_pointer
, arg_len
);
1869 arg
[arg_len
] = '\0';
1871 input_line_pointer
= arg_end
;
1881 if (saw_comma
|| saw_colon
)
1883 input_line_pointer
= old_input_line_pointer
;
1888 as_bad (_("extra comma"));
1890 as_bad (_("extra colon"));
1892 as_bad (_("missing argument"));
1894 as_bad (_("missing comma or colon"));
1895 input_line_pointer
= old_input_line_pointer
;
1900 /* Parse the arguments to an opcode. Return TRUE on error. */
1903 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1905 expressionS
*tok
, *last_tok
;
1906 xtensa_opcode opcode
= insn
->opcode
;
1907 bfd_boolean had_error
= TRUE
;
1908 xtensa_isa isa
= xtensa_default_isa
;
1909 int n
, num_regs
= 0;
1910 int opcode_operand_count
;
1911 int opnd_cnt
, last_opnd_cnt
;
1912 unsigned int next_reg
= 0;
1913 char *old_input_line_pointer
;
1915 if (insn
->insn_type
== ITYPE_LITERAL
)
1916 opcode_operand_count
= 1;
1918 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1921 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1923 /* Save and restore input_line_pointer around this function. */
1924 old_input_line_pointer
= input_line_pointer
;
1930 /* Skip invisible operands. */
1931 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1937 for (n
= 0; n
< num_args
; n
++)
1939 input_line_pointer
= arg_strings
[n
];
1940 if (*input_line_pointer
== ':')
1942 xtensa_regfile opnd_rf
;
1943 input_line_pointer
++;
1946 assert (opnd_cnt
> 0);
1948 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1950 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1951 as_warn (_("incorrect register number, ignoring"));
1956 if (opnd_cnt
>= opcode_operand_count
)
1958 as_warn (_("too many arguments"));
1961 assert (opnd_cnt
< MAX_INSN_ARGS
);
1963 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1964 next_reg
= tok
->X_add_number
+ 1;
1966 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1968 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1970 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1971 /* minus 1 because we are seeing one right now */
1977 last_opnd_cnt
= opnd_cnt
;
1984 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1988 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1991 insn
->ntok
= tok
- insn
->tok
;
1995 input_line_pointer
= old_input_line_pointer
;
2001 get_invisible_operands (TInsn
*insn
)
2003 xtensa_isa isa
= xtensa_default_isa
;
2004 static xtensa_insnbuf slotbuf
= NULL
;
2006 xtensa_opcode opc
= insn
->opcode
;
2007 int slot
, opnd
, fmt_found
;
2011 slotbuf
= xtensa_insnbuf_alloc (isa
);
2013 /* Find format/slot where this can be encoded. */
2016 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2018 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2020 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2026 if (fmt_found
) break;
2031 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2035 /* First encode all the visible operands
2036 (to deal with shared field operands). */
2037 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2039 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2040 && (insn
->tok
[opnd
].X_op
== O_register
2041 || insn
->tok
[opnd
].X_op
== O_constant
))
2043 val
= insn
->tok
[opnd
].X_add_number
;
2044 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2045 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2049 /* Then pull out the values for the invisible ones. */
2050 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2052 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2054 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2055 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2056 insn
->tok
[opnd
].X_add_number
= val
;
2057 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2058 insn
->tok
[opnd
].X_op
= O_register
;
2060 insn
->tok
[opnd
].X_op
= O_constant
;
2069 xg_reverse_shift_count (char **cnt_argp
)
2071 char *cnt_arg
, *new_arg
;
2072 cnt_arg
= *cnt_argp
;
2074 /* replace the argument with "31-(argument)" */
2075 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2076 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2079 *cnt_argp
= new_arg
;
2083 /* If "arg" is a constant expression, return non-zero with the value
2087 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2090 char *save_ptr
= input_line_pointer
;
2092 input_line_pointer
= arg
;
2094 input_line_pointer
= save_ptr
;
2096 if (exp
.X_op
== O_constant
)
2098 *valp
= exp
.X_add_number
;
2107 xg_replace_opname (char **popname
, char *newop
)
2110 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2111 strcpy (*popname
, newop
);
2116 xg_check_num_args (int *pnum_args
,
2121 int num_args
= *pnum_args
;
2123 if (num_args
< expected_num
)
2125 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2126 num_args
, opname
, expected_num
);
2130 if (num_args
> expected_num
)
2132 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2133 num_args
, opname
, expected_num
);
2134 while (num_args
-- > expected_num
)
2136 free (arg_strings
[num_args
]);
2137 arg_strings
[num_args
] = 0;
2139 *pnum_args
= expected_num
;
2147 /* If the register is not specified as part of the opcode,
2148 then get it from the operand and move it to the opcode. */
2151 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2153 xtensa_isa isa
= xtensa_default_isa
;
2155 char *opname
, *new_opname
;
2156 const char *sr_name
;
2157 int is_user
, is_write
;
2162 is_user
= (opname
[1] == 'u');
2163 is_write
= (opname
[0] == 'w');
2165 /* Opname == [rw]ur or [rwx]sr... */
2167 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2170 /* Check if the argument is a symbolic register name. */
2171 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2172 /* Handle WSR to "INTSET" as a special case. */
2173 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2174 && !strcasecmp (arg_strings
[1], "intset"))
2175 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2176 if (sr
== XTENSA_UNDEFINED
2177 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2179 /* Maybe it's a register number.... */
2181 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2183 as_bad (_("invalid register '%s' for '%s' instruction"),
2184 arg_strings
[1], opname
);
2187 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2188 if (sr
== XTENSA_UNDEFINED
)
2190 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2191 (long) val
, opname
);
2196 /* Remove the last argument, which is now part of the opcode. */
2197 free (arg_strings
[1]);
2201 /* Translate the opcode. */
2202 sr_name
= xtensa_sysreg_name (isa
, sr
);
2203 /* Another special case for "WSR.INTSET".... */
2204 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2206 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2207 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2209 *popname
= new_opname
;
2216 xtensa_translate_old_userreg_ops (char **popname
)
2218 xtensa_isa isa
= xtensa_default_isa
;
2220 char *opname
, *new_opname
;
2221 const char *sr_name
;
2222 bfd_boolean has_underbar
= FALSE
;
2225 if (opname
[0] == '_')
2227 has_underbar
= TRUE
;
2231 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2232 if (sr
!= XTENSA_UNDEFINED
)
2234 /* The new default name ("nnn") is different from the old default
2235 name ("URnnn"). The old default is handled below, and we don't
2236 want to recognize [RW]nnn, so do nothing if the name is the (new)
2238 static char namebuf
[10];
2239 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2240 if (strcmp (namebuf
, opname
+ 1) == 0)
2248 /* Only continue if the reg name is "URnnn". */
2249 if (opname
[1] != 'u' || opname
[2] != 'r')
2251 val
= strtoul (opname
+ 3, &end
, 10);
2255 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2256 if (sr
== XTENSA_UNDEFINED
)
2258 as_bad (_("invalid register number (%ld) for '%s'"),
2259 (long) val
, opname
);
2264 /* Translate the opcode. */
2265 sr_name
= xtensa_sysreg_name (isa
, sr
);
2266 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2267 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2268 opname
[0], sr_name
);
2270 *popname
= new_opname
;
2277 xtensa_translate_zero_immed (char *old_op
,
2287 assert (opname
[0] != '_');
2289 if (strcmp (opname
, old_op
) != 0)
2292 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2294 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2296 xg_replace_opname (popname
, new_op
);
2297 free (arg_strings
[1]);
2298 arg_strings
[1] = arg_strings
[2];
2307 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2308 Returns non-zero if an error was found. */
2311 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2313 char *opname
= *popname
;
2314 bfd_boolean has_underbar
= FALSE
;
2318 has_underbar
= TRUE
;
2322 if (strcmp (opname
, "mov") == 0)
2324 if (use_transform () && !has_underbar
&& density_supported
)
2325 xg_replace_opname (popname
, "mov.n");
2328 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2330 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2331 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2332 strcpy (arg_strings
[2], arg_strings
[1]);
2338 if (strcmp (opname
, "bbsi.l") == 0)
2340 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2342 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2343 if (target_big_endian
)
2344 xg_reverse_shift_count (&arg_strings
[1]);
2348 if (strcmp (opname
, "bbci.l") == 0)
2350 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2352 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2353 if (target_big_endian
)
2354 xg_reverse_shift_count (&arg_strings
[1]);
2358 /* Don't do anything special with NOPs inside FLIX instructions. They
2359 are handled elsewhere. Real NOP instructions are always available
2360 in configurations with FLIX, so this should never be an issue but
2361 check for it anyway. */
2362 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2363 && strcmp (opname
, "nop") == 0)
2365 if (use_transform () && !has_underbar
&& density_supported
)
2366 xg_replace_opname (popname
, "nop.n");
2369 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2371 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2372 arg_strings
[0] = (char *) xmalloc (3);
2373 arg_strings
[1] = (char *) xmalloc (3);
2374 arg_strings
[2] = (char *) xmalloc (3);
2375 strcpy (arg_strings
[0], "a1");
2376 strcpy (arg_strings
[1], "a1");
2377 strcpy (arg_strings
[2], "a1");
2383 /* Recognize [RW]UR and [RWX]SR. */
2384 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2385 && (opname
[1] == 'u' || opname
[1] == 's'))
2386 || (opname
[0] == 'x' && opname
[1] == 's'))
2388 && opname
[3] == '\0')
2389 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2391 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2392 [RW]<name> if <name> is the non-default name of a user register. */
2393 if ((opname
[0] == 'r' || opname
[0] == 'w')
2394 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2395 return xtensa_translate_old_userreg_ops (popname
);
2397 /* Relax branches that don't allow comparisons against an immediate value
2398 of zero to the corresponding branches with implicit zero immediates. */
2399 if (!has_underbar
&& use_transform ())
2401 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2402 pnum_args
, arg_strings
))
2405 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2406 pnum_args
, arg_strings
))
2409 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2410 pnum_args
, arg_strings
))
2413 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2414 pnum_args
, arg_strings
))
2422 /* Functions for dealing with the Xtensa ISA. */
2424 /* Currently the assembler only allows us to use a single target per
2425 fragment. Because of this, only one operand for a given
2426 instruction may be symbolic. If there is a PC-relative operand,
2427 the last one is chosen. Otherwise, the result is the number of the
2428 last immediate operand, and if there are none of those, we fail and
2432 get_relaxable_immed (xtensa_opcode opcode
)
2434 int last_immed
= -1;
2437 if (opcode
== XTENSA_UNDEFINED
)
2440 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2441 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2443 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2445 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2447 if (last_immed
== -1
2448 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2455 static xtensa_opcode
2456 get_opcode_from_buf (const char *buf
, int slot
)
2458 static xtensa_insnbuf insnbuf
= NULL
;
2459 static xtensa_insnbuf slotbuf
= NULL
;
2460 xtensa_isa isa
= xtensa_default_isa
;
2465 insnbuf
= xtensa_insnbuf_alloc (isa
);
2466 slotbuf
= xtensa_insnbuf_alloc (isa
);
2469 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2470 fmt
= xtensa_format_decode (isa
, insnbuf
);
2471 if (fmt
== XTENSA_UNDEFINED
)
2472 return XTENSA_UNDEFINED
;
2474 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2475 return XTENSA_UNDEFINED
;
2477 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2478 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2482 #ifdef TENSILICA_DEBUG
2484 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2487 xtensa_print_insn_table (void)
2489 int num_opcodes
, num_operands
;
2490 xtensa_opcode opcode
;
2491 xtensa_isa isa
= xtensa_default_isa
;
2493 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2494 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2497 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2498 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2499 for (opn
= 0; opn
< num_operands
; opn
++)
2501 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2503 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2505 xtensa_regfile opnd_rf
=
2506 xtensa_operand_regfile (isa
, opcode
, opn
);
2507 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2509 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2510 fputs ("[lLr] ", stderr
);
2512 fputs ("i ", stderr
);
2514 fprintf (stderr
, "\n");
2520 print_vliw_insn (xtensa_insnbuf vbuf
)
2522 xtensa_isa isa
= xtensa_default_isa
;
2523 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2524 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2527 fprintf (stderr
, "format = %d\n", f
);
2529 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2531 xtensa_opcode opcode
;
2535 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2536 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2537 opname
= xtensa_opcode_name (isa
, opcode
);
2539 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2540 fprintf (stderr
, " operands = ");
2542 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2546 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2548 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2549 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2550 fprintf (stderr
, "%d ", val
);
2552 fprintf (stderr
, "\n");
2554 xtensa_insnbuf_free (isa
, sbuf
);
2557 #endif /* TENSILICA_DEBUG */
2561 is_direct_call_opcode (xtensa_opcode opcode
)
2563 xtensa_isa isa
= xtensa_default_isa
;
2564 int n
, num_operands
;
2566 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2569 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2570 for (n
= 0; n
< num_operands
; n
++)
2572 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2573 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2580 /* Convert from BFD relocation type code to slot and operand number.
2581 Returns non-zero on failure. */
2584 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2586 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2587 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2589 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2592 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2593 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2595 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2605 /* Convert from slot number to BFD relocation type code for the
2606 standard PC-relative relocations. Return BFD_RELOC_NONE on
2609 static bfd_reloc_code_real_type
2610 encode_reloc (int slot
)
2612 if (slot
< 0 || slot
> 14)
2613 return BFD_RELOC_NONE
;
2615 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2619 /* Convert from slot numbers to BFD relocation type code for the
2620 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2622 static bfd_reloc_code_real_type
2623 encode_alt_reloc (int slot
)
2625 if (slot
< 0 || slot
> 14)
2626 return BFD_RELOC_NONE
;
2628 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2633 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2636 xtensa_opcode opcode
,
2642 uint32 valbuf
= value
;
2644 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2646 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2648 as_bad_where ((char *) file
, line
,
2649 _("operand %d of '%s' has out of range value '%u'"),
2651 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2654 as_bad_where ((char *) file
, line
,
2655 _("operand %d of '%s' has invalid value '%u'"),
2657 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2662 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2668 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2671 xtensa_opcode opcode
,
2675 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2676 fmt
, slot
, slotbuf
, &val
);
2677 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2682 /* Checks for rules from xtensa-relax tables. */
2684 /* The routine xg_instruction_matches_option_term must return TRUE
2685 when a given option term is true. The meaning of all of the option
2686 terms is given interpretation by this function. This is needed when
2687 an option depends on the state of a directive, but there are no such
2688 options in use right now. */
2691 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2692 const ReqOrOption
*option
)
2694 if (strcmp (option
->option_name
, "realnop") == 0
2695 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2697 /* These conditions were evaluated statically when building the
2698 relaxation table. There's no need to reevaluate them now. */
2703 as_fatal (_("internal error: unknown option name '%s'"),
2704 option
->option_name
);
2710 xg_instruction_matches_or_options (TInsn
*insn
,
2711 const ReqOrOptionList
*or_option
)
2713 const ReqOrOption
*option
;
2714 /* Must match each of the AND terms. */
2715 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2717 if (xg_instruction_matches_option_term (insn
, option
))
2725 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2727 const ReqOption
*req_options
;
2728 /* Must match each of the AND terms. */
2729 for (req_options
= options
;
2730 req_options
!= NULL
;
2731 req_options
= req_options
->next
)
2733 /* Must match one of the OR clauses. */
2734 if (!xg_instruction_matches_or_options (insn
,
2735 req_options
->or_option_terms
))
2742 /* Return the transition rule that matches or NULL if none matches. */
2745 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2747 PreconditionList
*condition_l
;
2749 if (rule
->opcode
!= insn
->opcode
)
2752 for (condition_l
= rule
->conditions
;
2753 condition_l
!= NULL
;
2754 condition_l
= condition_l
->next
)
2758 Precondition
*cond
= condition_l
->precond
;
2763 /* The expression must be the constant. */
2764 assert (cond
->op_num
< insn
->ntok
);
2765 exp1
= &insn
->tok
[cond
->op_num
];
2766 if (expr_is_const (exp1
))
2771 if (get_expr_const (exp1
) != cond
->op_data
)
2775 if (get_expr_const (exp1
) == cond
->op_data
)
2782 else if (expr_is_register (exp1
))
2787 if (get_expr_register (exp1
) != cond
->op_data
)
2791 if (get_expr_register (exp1
) == cond
->op_data
)
2803 assert (cond
->op_num
< insn
->ntok
);
2804 assert (cond
->op_data
< insn
->ntok
);
2805 exp1
= &insn
->tok
[cond
->op_num
];
2806 exp2
= &insn
->tok
[cond
->op_data
];
2811 if (!expr_is_equal (exp1
, exp2
))
2815 if (expr_is_equal (exp1
, exp2
))
2827 if (!xg_instruction_matches_options (insn
, rule
->options
))
2835 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2837 bfd_boolean a_greater
= FALSE
;
2838 bfd_boolean b_greater
= FALSE
;
2840 ReqOptionList
*l_a
= a
->options
;
2841 ReqOptionList
*l_b
= b
->options
;
2843 /* We only care if they both are the same except for
2844 a const16 vs. an l32r. */
2846 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2848 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2849 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2850 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2852 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2854 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2856 /* This is the case we care about. */
2857 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2858 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2865 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2866 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2876 l_or_a
= l_or_a
->next
;
2877 l_or_b
= l_or_b
->next
;
2879 if (l_or_a
|| l_or_b
)
2888 /* Incomparable if the substitution was used differently in two cases. */
2889 if (a_greater
&& b_greater
)
2901 static TransitionRule
*
2902 xg_instruction_match (TInsn
*insn
)
2904 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2906 assert (insn
->opcode
< table
->num_opcodes
);
2908 /* Walk through all of the possible transitions. */
2909 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2911 TransitionRule
*rule
= l
->rule
;
2912 if (xg_instruction_matches_rule (insn
, rule
))
2919 /* Various Other Internal Functions. */
2922 is_unique_insn_expansion (TransitionRule
*r
)
2924 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2926 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2932 /* Check if there is exactly one relaxation for INSN that converts it to
2933 another instruction of equal or larger size. If so, and if TARG is
2934 non-null, go ahead and generate the relaxed instruction into TARG. If
2935 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2936 instruction, i.e., ignore relaxations that convert to an instruction of
2937 equal size. In some contexts where this function is used, only
2938 a single widening is allowed and the NARROW_ONLY argument is used to
2939 exclude cases like ADDI being "widened" to an ADDMI, which may
2940 later be relaxed to an ADDMI/ADDI pair. */
2943 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2945 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2947 TransitionRule
*match
= 0;
2949 assert (insn
->insn_type
== ITYPE_INSN
);
2950 assert (insn
->opcode
< table
->num_opcodes
);
2952 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2954 TransitionRule
*rule
= l
->rule
;
2956 if (xg_instruction_matches_rule (insn
, rule
)
2957 && is_unique_insn_expansion (rule
)
2958 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2959 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2970 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2975 /* Return the maximum number of bytes this opcode can expand to. */
2978 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2980 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2982 int max_size
= xg_get_single_size (opcode
);
2984 assert (opcode
< table
->num_opcodes
);
2986 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2988 TransitionRule
*rule
= l
->rule
;
2989 BuildInstr
*build_list
;
2994 build_list
= rule
->to_instr
;
2995 if (is_unique_insn_expansion (rule
))
2997 assert (build_list
->typ
== INSTR_INSTR
);
2998 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3001 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3003 switch (build_list
->typ
)
3006 this_size
+= xg_get_single_size (build_list
->opcode
);
3008 case INSTR_LITERAL_DEF
:
3009 case INSTR_LABEL_DEF
:
3014 if (this_size
> max_size
)
3015 max_size
= this_size
;
3021 /* Return the maximum number of literal bytes this opcode can generate. */
3024 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3026 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3030 assert (opcode
< table
->num_opcodes
);
3032 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3034 TransitionRule
*rule
= l
->rule
;
3035 BuildInstr
*build_list
;
3040 build_list
= rule
->to_instr
;
3041 if (is_unique_insn_expansion (rule
))
3043 assert (build_list
->typ
== INSTR_INSTR
);
3044 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3047 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3049 switch (build_list
->typ
)
3051 case INSTR_LITERAL_DEF
:
3052 /* Hard-coded 4-byte literal. */
3056 case INSTR_LABEL_DEF
:
3061 if (this_size
> max_size
)
3062 max_size
= this_size
;
3069 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3071 int steps_taken
= 0;
3072 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3075 assert (insn
->insn_type
== ITYPE_INSN
);
3076 assert (insn
->opcode
< table
->num_opcodes
);
3078 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3080 TransitionRule
*rule
= l
->rule
;
3082 if (xg_instruction_matches_rule (insn
, rule
))
3084 if (steps_taken
== lateral_steps
)
3094 get_special_literal_symbol (void)
3096 static symbolS
*sym
= NULL
;
3099 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3105 get_special_label_symbol (void)
3107 static symbolS
*sym
= NULL
;
3110 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3116 xg_valid_literal_expression (const expressionS
*exp
)
3133 /* This will check to see if the value can be converted into the
3134 operand type. It will return TRUE if it does not fit. */
3137 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3139 uint32 valbuf
= value
;
3140 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3146 /* Assumes: All immeds are constants. Check that all constants fit
3147 into their immeds; return FALSE if not. */
3150 xg_immeds_fit (const TInsn
*insn
)
3152 xtensa_isa isa
= xtensa_default_isa
;
3156 assert (insn
->insn_type
== ITYPE_INSN
);
3157 for (i
= 0; i
< n
; ++i
)
3159 const expressionS
*expr
= &insn
->tok
[i
];
3160 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3167 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3172 /* The symbol should have a fixup associated with it. */
3181 /* This should only be called after we have an initial
3182 estimate of the addresses. */
3185 xg_symbolic_immeds_fit (const TInsn
*insn
,
3191 xtensa_isa isa
= xtensa_default_isa
;
3199 assert (insn
->insn_type
== ITYPE_INSN
);
3201 for (i
= 0; i
< n
; ++i
)
3203 const expressionS
*expr
= &insn
->tok
[i
];
3204 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3211 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3217 /* Check for the worst case. */
3218 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3223 /* We only allow symbols for PC-relative references.
3224 If pc_frag == 0, then we don't have frag locations yet. */
3226 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3229 /* If it is a weak symbol, then assume it won't reach. */
3230 if (S_IS_WEAK (expr
->X_add_symbol
))
3233 if (is_direct_call_opcode (insn
->opcode
)
3234 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3236 /* If callee is undefined or in a different segment, be
3237 optimistic and assume it will be in range. */
3238 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3242 /* Only references within a segment can be known to fit in the
3243 operands at assembly time. */
3244 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3247 symbolP
= expr
->X_add_symbol
;
3248 sym_frag
= symbol_get_frag (symbolP
);
3249 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3250 pc
= pc_frag
->fr_address
+ pc_offset
;
3252 /* If frag has yet to be reached on this pass, assume it
3253 will move by STRETCH just as we did. If this is not so,
3254 it will be because some frag between grows, and that will
3255 force another pass. Beware zero-length frags. There
3256 should be a faster way to do this. */
3259 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3260 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3265 new_offset
= target
;
3266 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3267 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3272 /* The symbol should have a fixup associated with it. */
3281 /* Return TRUE on success. */
3284 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3290 targ
->linenum
= insn
->linenum
;
3295 targ
->opcode
= bi
->opcode
;
3296 targ
->insn_type
= ITYPE_INSN
;
3297 targ
->is_specific_opcode
= FALSE
;
3299 for (; op
!= NULL
; op
= op
->next
)
3301 int op_num
= op
->op_num
;
3302 int op_data
= op
->op_data
;
3304 assert (op
->op_num
< MAX_INSN_ARGS
);
3306 if (targ
->ntok
<= op_num
)
3307 targ
->ntok
= op_num
+ 1;
3312 set_expr_const (&targ
->tok
[op_num
], op_data
);
3315 assert (op_data
< insn
->ntok
);
3316 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3319 sym
= get_special_literal_symbol ();
3320 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3323 sym
= get_special_label_symbol ();
3324 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3326 case OP_OPERAND_HI16U
:
3327 case OP_OPERAND_LOW16U
:
3328 assert (op_data
< insn
->ntok
);
3329 if (expr_is_const (&insn
->tok
[op_data
]))
3332 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3333 val
= xg_apply_userdef_op_fn (op
->typ
,
3336 targ
->tok
[op_num
].X_add_number
= val
;
3340 /* For const16 we can create relocations for these. */
3341 if (targ
->opcode
== XTENSA_UNDEFINED
3342 || (targ
->opcode
!= xtensa_const16_opcode
))
3344 assert (op_data
< insn
->ntok
);
3345 /* Need to build a O_lo16 or O_hi16. */
3346 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3347 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3349 if (op
->typ
== OP_OPERAND_HI16U
)
3350 targ
->tok
[op_num
].X_op
= O_hi16
;
3351 else if (op
->typ
== OP_OPERAND_LOW16U
)
3352 targ
->tok
[op_num
].X_op
= O_lo16
;
3359 /* currently handles:
3362 OP_OPERAND_F32MINUS */
3363 if (xg_has_userdef_op_fn (op
->typ
))
3365 assert (op_data
< insn
->ntok
);
3366 if (expr_is_const (&insn
->tok
[op_data
]))
3369 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3370 val
= xg_apply_userdef_op_fn (op
->typ
,
3373 targ
->tok
[op_num
].X_add_number
= val
;
3376 return FALSE
; /* We cannot use a relocation for this. */
3385 case INSTR_LITERAL_DEF
:
3387 targ
->opcode
= XTENSA_UNDEFINED
;
3388 targ
->insn_type
= ITYPE_LITERAL
;
3389 targ
->is_specific_opcode
= FALSE
;
3390 for (; op
!= NULL
; op
= op
->next
)
3392 int op_num
= op
->op_num
;
3393 int op_data
= op
->op_data
;
3394 assert (op
->op_num
< MAX_INSN_ARGS
);
3396 if (targ
->ntok
<= op_num
)
3397 targ
->ntok
= op_num
+ 1;
3402 assert (op_data
< insn
->ntok
);
3403 /* We can only pass resolvable literals through. */
3404 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3406 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3418 case INSTR_LABEL_DEF
:
3420 targ
->opcode
= XTENSA_UNDEFINED
;
3421 targ
->insn_type
= ITYPE_LABEL
;
3422 targ
->is_specific_opcode
= FALSE
;
3423 /* Literal with no ops is a label? */
3424 assert (op
== NULL
);
3435 /* Return TRUE on success. */
3438 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3440 for (; bi
!= NULL
; bi
= bi
->next
)
3442 TInsn
*next_insn
= istack_push_space (istack
);
3444 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3451 /* Return TRUE on valid expansion. */
3454 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3456 int stack_size
= istack
->ninsn
;
3457 int steps_taken
= 0;
3458 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3461 assert (insn
->insn_type
== ITYPE_INSN
);
3462 assert (insn
->opcode
< table
->num_opcodes
);
3464 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3466 TransitionRule
*rule
= l
->rule
;
3468 if (xg_instruction_matches_rule (insn
, rule
))
3470 if (lateral_steps
== steps_taken
)
3474 /* This is it. Expand the rule to the stack. */
3475 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3478 /* Check to see if it fits. */
3479 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3481 TInsn
*insn
= &istack
->insn
[i
];
3483 if (insn
->insn_type
== ITYPE_INSN
3484 && !tinsn_has_symbolic_operands (insn
)
3485 && !xg_immeds_fit (insn
))
3487 istack
->ninsn
= stack_size
;
3500 /* Relax the assembly instruction at least "min_steps".
3501 Return the number of steps taken.
3503 For relaxation to correctly terminate, every relaxation chain must
3504 terminate in one of two ways:
3506 1. If the chain from one instruction to the next consists entirely of
3507 single instructions, then the chain *must* handle all possible
3508 immediates without failing. It must not ever fail because an
3509 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3510 chain is one example. L32R loads 32 bits, and there cannot be an
3511 immediate larger than 32 bits, so it satisfies this condition.
3512 Single instruction relaxation chains are as defined by
3513 xg_is_single_relaxable_instruction.
3515 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3516 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3518 Strictly speaking, in most cases you can violate condition 1 and be OK
3519 -- in particular when the last two instructions have the same single
3520 size. But nevertheless, you should guarantee the above two conditions.
3522 We could fix this so that single-instruction expansions correctly
3523 terminate when they can't handle the range, but the error messages are
3524 worse, and it actually turns out that in every case but one (18-bit wide
3525 branches), you need a multi-instruction expansion to get the full range
3526 anyway. And because 18-bit branches are handled identically to 15-bit
3527 branches, there isn't any point in changing it. */
3530 xg_assembly_relax (IStack
*istack
,
3533 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3534 offsetT pc_offset
, /* offset in fragment */
3535 int min_steps
, /* minimum conversion steps */
3536 long stretch
) /* number of bytes stretched so far */
3538 int steps_taken
= 0;
3540 /* Some of its immeds don't fit. Try to build a relaxed version.
3541 This may go through a couple of stages of single instruction
3542 transformations before we get there. */
3544 TInsn single_target
;
3546 int lateral_steps
= 0;
3547 int istack_size
= istack
->ninsn
;
3549 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3550 && steps_taken
>= min_steps
)
3552 istack_push (istack
, insn
);
3555 current_insn
= *insn
;
3557 /* Walk through all of the single instruction expansions. */
3558 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3561 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3564 if (steps_taken
>= min_steps
)
3566 istack_push (istack
, &single_target
);
3570 current_insn
= single_target
;
3573 /* Now check for a multi-instruction expansion. */
3574 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3576 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3579 if (steps_taken
>= min_steps
)
3581 istack_push (istack
, ¤t_insn
);
3586 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3588 if (steps_taken
>= min_steps
)
3592 istack
->ninsn
= istack_size
;
3595 /* It's not going to work -- use the original. */
3596 istack_push (istack
, insn
);
3602 xg_force_frag_space (int size
)
3604 /* This may have the side effect of creating a new fragment for the
3605 space to go into. I just do not like the name of the "frag"
3612 xg_finish_frag (char *last_insn
,
3613 enum xtensa_relax_statesE frag_state
,
3614 enum xtensa_relax_statesE slot0_state
,
3616 bfd_boolean is_insn
)
3618 /* Finish off this fragment so that it has at LEAST the desired
3619 max_growth. If it doesn't fit in this fragment, close this one
3620 and start a new one. In either case, return a pointer to the
3621 beginning of the growth area. */
3625 xg_force_frag_space (max_growth
);
3627 old_frag
= frag_now
;
3629 frag_now
->fr_opcode
= last_insn
;
3631 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3633 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3634 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3636 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3637 xtensa_set_frag_assembly_state (frag_now
);
3639 /* Just to make sure that we did not split it up. */
3640 assert (old_frag
->fr_next
== frag_now
);
3644 /* Return TRUE if the target frag is one of the next non-empty frags. */
3647 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3652 for (; fragP
; fragP
= fragP
->fr_next
)
3654 if (fragP
== target
)
3656 if (fragP
->fr_fix
!= 0)
3658 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3660 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3661 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3663 if (fragP
->fr_type
== rs_space
)
3671 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3673 xtensa_isa isa
= xtensa_default_isa
;
3675 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3680 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3681 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3684 for (i
= 0; i
< num_ops
; i
++)
3686 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3692 if (target_op
== -1)
3695 if (insn
->ntok
<= target_op
)
3698 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3701 sym
= insn
->tok
[target_op
].X_add_symbol
;
3705 if (insn
->tok
[target_op
].X_add_number
!= 0)
3708 target_frag
= symbol_get_frag (sym
);
3709 if (target_frag
== NULL
)
3712 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3713 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3721 xg_add_branch_and_loop_targets (TInsn
*insn
)
3723 xtensa_isa isa
= xtensa_default_isa
;
3724 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3726 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3729 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3730 && insn
->tok
[i
].X_op
== O_symbol
)
3731 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3735 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3736 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3740 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3742 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3743 && insn
->tok
[i
].X_op
== O_symbol
)
3745 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3746 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3747 if (S_IS_DEFINED (sym
))
3748 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3755 /* Return FALSE if no error. */
3758 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3763 switch (instr_spec
->typ
)
3766 new_insn
->insn_type
= ITYPE_INSN
;
3767 new_insn
->opcode
= instr_spec
->opcode
;
3768 new_insn
->is_specific_opcode
= FALSE
;
3769 new_insn
->linenum
= old_insn
->linenum
;
3771 case INSTR_LITERAL_DEF
:
3772 new_insn
->insn_type
= ITYPE_LITERAL
;
3773 new_insn
->opcode
= XTENSA_UNDEFINED
;
3774 new_insn
->is_specific_opcode
= FALSE
;
3775 new_insn
->linenum
= old_insn
->linenum
;
3777 case INSTR_LABEL_DEF
:
3778 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3782 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3785 const expressionS
*src_exp
;
3791 /* The expression must be the constant. */
3792 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3793 exp
= &new_insn
->tok
[b_op
->op_num
];
3794 set_expr_const (exp
, b_op
->op_data
);
3798 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3799 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3800 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3801 exp
= &new_insn
->tok
[b_op
->op_num
];
3802 copy_expr (exp
, src_exp
);
3807 as_bad (_("can't handle generation of literal/labels yet"));
3811 as_bad (_("can't handle undefined OP TYPE"));
3816 new_insn
->ntok
= num_ops
;
3821 /* Return TRUE if it was simplified. */
3824 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3826 TransitionRule
*rule
;
3827 BuildInstr
*insn_spec
;
3829 if (old_insn
->is_specific_opcode
|| !density_supported
)
3832 rule
= xg_instruction_match (old_insn
);
3836 insn_spec
= rule
->to_instr
;
3837 /* There should only be one. */
3838 assert (insn_spec
!= NULL
);
3839 assert (insn_spec
->next
== NULL
);
3840 if (insn_spec
->next
!= NULL
)
3843 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3849 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3850 l32i.n. (2) Check the number of operands. (3) Place the instruction
3851 tokens into the stack or relax it and place multiple
3852 instructions/literals onto the stack. Return FALSE if no error. */
3855 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3859 bfd_boolean do_expand
;
3861 tinsn_init (&new_insn
);
3863 /* Narrow it if we can. xg_simplify_insn now does all the
3864 appropriate checking (e.g., for the density option). */
3865 if (xg_simplify_insn (orig_insn
, &new_insn
))
3866 orig_insn
= &new_insn
;
3868 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3870 if (orig_insn
->ntok
< noperands
)
3872 as_bad (_("found %d operands for '%s': Expected %d"),
3874 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3878 if (orig_insn
->ntok
> noperands
)
3879 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3881 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3884 /* If there are not enough operands, we will assert above. If there
3885 are too many, just cut out the extras here. */
3886 orig_insn
->ntok
= noperands
;
3888 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3891 /* If the instruction will definitely need to be relaxed, it is better
3892 to expand it now for better scheduling. Decide whether to expand
3894 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3896 /* Calls should be expanded to longcalls only in the backend relaxation
3897 so that the assembly scheduler will keep the L32R/CALLX instructions
3899 if (is_direct_call_opcode (orig_insn
->opcode
))
3902 if (tinsn_has_symbolic_operands (orig_insn
))
3904 /* The values of symbolic operands are not known yet, so only expand
3905 now if an operand is "complex" (e.g., difference of symbols) and
3906 will have to be stored as a literal regardless of the value. */
3907 if (!tinsn_has_complex_operands (orig_insn
))
3910 else if (xg_immeds_fit (orig_insn
))
3914 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3916 istack_push (istack
, orig_insn
);
3922 /* Return TRUE if the section flags are marked linkonce
3923 or the name is .gnu.linkonce.*. */
3925 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3928 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3930 flagword flags
, link_once_flags
;
3932 flags
= bfd_get_section_flags (abfd
, sec
);
3933 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3935 /* Flags might not be set yet. */
3936 if (!link_once_flags
3937 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3938 link_once_flags
= SEC_LINK_ONCE
;
3940 return (link_once_flags
!= 0);
3945 xtensa_add_literal_sym (symbolS
*sym
)
3949 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3951 l
->next
= literal_syms
;
3957 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3959 static int lit_num
= 0;
3960 static char name
[256];
3963 sprintf (name
, ".L_lit_sym%d", lit_num
);
3965 /* Create a local symbol. If it is in a linkonce section, we have to
3966 be careful to make sure that if it is used in a relocation that the
3967 symbol will be in the output file. */
3968 if (get_is_linkonce_section (stdoutput
, sec
))
3970 symbolP
= symbol_new (name
, sec
, 0, frag
);
3971 S_CLEAR_EXTERNAL (symbolP
);
3972 /* symbolP->local = 1; */
3975 symbolP
= symbol_new (name
, sec
, 0, frag
);
3977 xtensa_add_literal_sym (symbolP
);
3984 /* Currently all literals that are generated here are 32-bit L32R targets. */
3987 xg_assemble_literal (/* const */ TInsn
*insn
)
3990 symbolS
*lit_sym
= NULL
;
3991 bfd_reloc_code_real_type reloc
;
3994 /* size = 4 for L32R. It could easily be larger when we move to
3995 larger constants. Add a parameter later. */
3996 offsetT litsize
= 4;
3997 offsetT litalign
= 2; /* 2^2 = 4 */
3998 expressionS saved_loc
;
3999 expressionS
* emit_val
;
4001 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4003 assert (insn
->insn_type
== ITYPE_LITERAL
);
4004 assert (insn
->ntok
== 1); /* must be only one token here */
4006 xtensa_switch_to_literal_fragment (&state
);
4008 emit_val
= &insn
->tok
[0];
4009 if (emit_val
->X_op
== O_big
)
4011 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4014 /* This happens when someone writes a "movi a2, big_number". */
4015 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4016 _("invalid immediate"));
4017 xtensa_restore_emit_state (&state
);
4022 /* Force a 4-byte align here. Note that this opens a new frag, so all
4023 literals done with this function have a frag to themselves. That's
4024 important for the way text section literals work. */
4025 frag_align (litalign
, 0, 0);
4026 record_alignment (now_seg
, litalign
);
4028 switch (emit_val
->X_op
)
4031 p
= frag_more (litsize
);
4032 xtensa_set_frag_assembly_state (frag_now
);
4033 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4034 if (emit_val
->X_add_symbol
)
4035 emit_val
->X_op
= O_symbol
;
4037 emit_val
->X_op
= O_constant
;
4038 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4039 litsize
, emit_val
, 0, reloc
);
4043 emit_expr (emit_val
, litsize
);
4047 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4048 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4049 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4050 lit_sym
= frag_now
->fr_symbol
;
4053 xtensa_restore_emit_state (&state
);
4059 xg_assemble_literal_space (/* const */ int size
, int slot
)
4062 /* We might have to do something about this alignment. It only
4063 takes effect if something is placed here. */
4064 offsetT litalign
= 2; /* 2^2 = 4 */
4065 fragS
*lit_saved_frag
;
4067 assert (size
% 4 == 0);
4069 xtensa_switch_to_literal_fragment (&state
);
4071 /* Force a 4-byte align here. */
4072 frag_align (litalign
, 0, 0);
4073 record_alignment (now_seg
, litalign
);
4075 xg_force_frag_space (size
);
4077 lit_saved_frag
= frag_now
;
4078 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4079 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4080 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4083 xtensa_restore_emit_state (&state
);
4084 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4088 /* Put in a fixup record based on the opcode.
4089 Return TRUE on success. */
4092 xg_add_opcode_fix (TInsn
*tinsn
,
4100 xtensa_opcode opcode
= tinsn
->opcode
;
4101 bfd_reloc_code_real_type reloc
;
4102 reloc_howto_type
*howto
;
4106 reloc
= BFD_RELOC_NONE
;
4108 /* First try the special cases for "alternate" relocs. */
4109 if (opcode
== xtensa_l32r_opcode
)
4111 if (fragP
->tc_frag_data
.use_absolute_literals
)
4112 reloc
= encode_alt_reloc (slot
);
4114 else if (opcode
== xtensa_const16_opcode
)
4116 if (expr
->X_op
== O_lo16
)
4118 reloc
= encode_reloc (slot
);
4119 expr
->X_op
= O_symbol
;
4121 else if (expr
->X_op
== O_hi16
)
4123 reloc
= encode_alt_reloc (slot
);
4124 expr
->X_op
= O_symbol
;
4128 if (opnum
!= get_relaxable_immed (opcode
))
4130 as_bad (_("invalid relocation for operand %i of '%s'"),
4131 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4135 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4136 into the symbol table where the generic portions of the assembler
4137 won't know what to do with them. */
4138 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4140 as_bad (_("invalid expression for operand %i of '%s'"),
4141 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4145 /* Next try the generic relocs. */
4146 if (reloc
== BFD_RELOC_NONE
)
4147 reloc
= encode_reloc (slot
);
4148 if (reloc
== BFD_RELOC_NONE
)
4150 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4154 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4157 as_bad (_("undefined symbol for opcode \"%s\""),
4158 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4162 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4163 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4164 howto
->pc_relative
, reloc
);
4165 the_fix
->fx_no_overflow
= 1;
4166 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4167 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4168 the_fix
->tc_fix_data
.slot
= slot
;
4175 xg_emit_insn_to_buf (TInsn
*tinsn
,
4179 bfd_boolean build_fix
)
4181 static xtensa_insnbuf insnbuf
= NULL
;
4182 bfd_boolean has_symbolic_immed
= FALSE
;
4183 bfd_boolean ok
= TRUE
;
4186 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4188 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4189 if (has_symbolic_immed
&& build_fix
)
4192 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4193 int slot
= xg_get_single_slot (tinsn
->opcode
);
4194 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4195 expressionS
*exp
= &tinsn
->tok
[opnum
];
4197 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4200 fragP
->tc_frag_data
.is_insn
= TRUE
;
4201 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4202 (unsigned char *) buf
, 0);
4208 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4210 symbolS
*sym
= get_special_literal_symbol ();
4214 assert (insn
->insn_type
== ITYPE_INSN
);
4215 for (i
= 0; i
< insn
->ntok
; i
++)
4216 if (insn
->tok
[i
].X_add_symbol
== sym
)
4217 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4223 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4225 symbolS
*sym
= get_special_label_symbol ();
4227 for (i
= 0; i
< insn
->ntok
; i
++)
4228 if (insn
->tok
[i
].X_add_symbol
== sym
)
4229 insn
->tok
[i
].X_add_symbol
= label_sym
;
4234 /* Return TRUE if the instruction can write to the specified
4235 integer register. */
4238 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4242 xtensa_isa isa
= xtensa_default_isa
;
4244 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4246 for (i
= 0; i
< num_ops
; i
++)
4249 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4250 if ((inout
== 'o' || inout
== 'm')
4251 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4253 xtensa_regfile opnd_rf
=
4254 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4255 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4257 if ((insn
->tok
[i
].X_op
== O_register
)
4258 && (insn
->tok
[i
].X_add_number
== regnum
))
4268 is_bad_loopend_opcode (const TInsn
*tinsn
)
4270 xtensa_opcode opcode
= tinsn
->opcode
;
4272 if (opcode
== XTENSA_UNDEFINED
)
4275 if (opcode
== xtensa_call0_opcode
4276 || opcode
== xtensa_callx0_opcode
4277 || opcode
== xtensa_call4_opcode
4278 || opcode
== xtensa_callx4_opcode
4279 || opcode
== xtensa_call8_opcode
4280 || opcode
== xtensa_callx8_opcode
4281 || opcode
== xtensa_call12_opcode
4282 || opcode
== xtensa_callx12_opcode
4283 || opcode
== xtensa_isync_opcode
4284 || opcode
== xtensa_ret_opcode
4285 || opcode
== xtensa_ret_n_opcode
4286 || opcode
== xtensa_retw_opcode
4287 || opcode
== xtensa_retw_n_opcode
4288 || opcode
== xtensa_waiti_opcode
4289 || opcode
== xtensa_rsr_lcount_opcode
)
4296 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4297 This allows the debugger to add unaligned labels.
4298 Also, the assembler generates stabs labels that need
4299 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4302 is_unaligned_label (symbolS
*sym
)
4304 const char *name
= S_GET_NAME (sym
);
4305 static size_t fake_size
= 0;
4309 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4312 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4314 fake_size
= strlen (FAKE_LABEL_NAME
);
4317 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4318 && (name
[fake_size
] == 'F'
4319 || name
[fake_size
] == 'L'
4320 || (name
[fake_size
] == 'e'
4321 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4329 next_non_empty_frag (const fragS
*fragP
)
4331 fragS
*next_fragP
= fragP
->fr_next
;
4333 /* Sometimes an empty will end up here due storage allocation issues.
4334 So we have to skip until we find something legit. */
4335 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4336 next_fragP
= next_fragP
->fr_next
;
4338 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4346 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4348 xtensa_opcode out_opcode
;
4349 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4351 if (next_fragP
== NULL
)
4354 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4355 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4357 *opcode
= out_opcode
;
4365 frag_format_size (const fragS
*fragP
)
4367 static xtensa_insnbuf insnbuf
= NULL
;
4368 xtensa_isa isa
= xtensa_default_isa
;
4373 insnbuf
= xtensa_insnbuf_alloc (isa
);
4376 return XTENSA_UNDEFINED
;
4378 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4379 (unsigned char *) fragP
->fr_literal
, 0);
4381 fmt
= xtensa_format_decode (isa
, insnbuf
);
4382 if (fmt
== XTENSA_UNDEFINED
)
4383 return XTENSA_UNDEFINED
;
4384 fmt_size
= xtensa_format_length (isa
, fmt
);
4386 /* If the next format won't be changing due to relaxation, just
4387 return the length of the first format. */
4388 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4391 /* If during relaxation we have to pull an instruction out of a
4392 multi-slot instruction, we will return the more conservative
4393 number. This works because alignment on bigger instructions
4394 is more restrictive than alignment on smaller instructions.
4395 This is more conservative than we would like, but it happens
4398 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4401 /* If we aren't doing one of our own relaxations or it isn't
4402 slot-based, then the insn size won't change. */
4403 if (fragP
->fr_type
!= rs_machine_dependent
)
4405 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4408 /* If an instruction is about to grow, return the longer size. */
4409 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4410 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4411 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4414 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4415 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4422 next_frag_format_size (const fragS
*fragP
)
4424 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4425 return frag_format_size (next_fragP
);
4429 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4430 required two-byte instructions to be treated as three-byte instructions
4431 for loop instruction alignment. This restriction was removed beginning
4432 with Xtensa LX. Now the only requirement on loop instruction alignment
4433 is that the first instruction of the loop must appear at an address that
4434 does not cross a fetch boundary. */
4437 get_loop_align_size (int insn_size
)
4439 if (insn_size
== XTENSA_UNDEFINED
)
4440 return xtensa_fetch_width
;
4442 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4449 /* If the next legit fragment is an end-of-loop marker,
4450 switch its state so it will instantiate a NOP. */
4453 update_next_frag_state (fragS
*fragP
)
4455 fragS
*next_fragP
= fragP
->fr_next
;
4456 fragS
*new_target
= NULL
;
4460 /* We are guaranteed there will be one of these... */
4461 while (!(next_fragP
->fr_type
== rs_machine_dependent
4462 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4463 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4464 next_fragP
= next_fragP
->fr_next
;
4466 assert (next_fragP
->fr_type
== rs_machine_dependent
4467 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4468 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4470 /* ...and one of these. */
4471 new_target
= next_fragP
->fr_next
;
4472 while (!(new_target
->fr_type
== rs_machine_dependent
4473 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4474 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4475 new_target
= new_target
->fr_next
;
4477 assert (new_target
->fr_type
== rs_machine_dependent
4478 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4479 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4482 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4484 if (next_fragP
->fr_type
== rs_machine_dependent
4485 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4487 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4491 next_fragP
= next_fragP
->fr_next
;
4497 next_frag_is_branch_target (const fragS
*fragP
)
4499 /* Sometimes an empty will end up here due to storage allocation issues,
4500 so we have to skip until we find something legit. */
4501 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4503 if (fragP
->tc_frag_data
.is_branch_target
)
4505 if (fragP
->fr_fix
!= 0)
4513 next_frag_is_loop_target (const fragS
*fragP
)
4515 /* Sometimes an empty will end up here due storage allocation issues.
4516 So we have to skip until we find something legit. */
4517 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4519 if (fragP
->tc_frag_data
.is_loop_target
)
4521 if (fragP
->fr_fix
!= 0)
4529 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4531 const fragS
*next_fragp
= fragp
->fr_next
;
4532 xtensa_opcode next_opcode
;
4534 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4537 /* Sometimes an empty will end up here due to storage allocation issues,
4538 so we have to skip until we find something legit. */
4539 while (next_fragp
->fr_fix
== 0)
4540 next_fragp
= next_fragp
->fr_next
;
4542 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4545 /* There is some implicit knowledge encoded in here.
4546 The LOOP instructions that are NOT RELAX_IMMED have
4547 been relaxed. Note that we can assume that the LOOP
4548 instruction is in slot 0 because loops aren't bundleable. */
4549 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4550 return get_expanded_loop_offset (next_opcode
);
4556 /* Mark a location where we can later insert literal frags. Update
4557 the section's literal_pool_loc, so subsequent literals can be
4558 placed nearest to their use. */
4561 xtensa_mark_literal_pool_location (void)
4563 /* Any labels pointing to the current location need
4564 to be adjusted to after the literal pool. */
4566 fragS
*pool_location
;
4568 if (use_literal_section
)
4571 /* We stash info in these frags so we can later move the literal's
4572 fixes into this frchain's fix list. */
4573 pool_location
= frag_now
;
4574 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4575 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4576 frag_variant (rs_machine_dependent
, 0, 0,
4577 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4578 xtensa_set_frag_assembly_state (frag_now
);
4579 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4580 frag_variant (rs_machine_dependent
, 0, 0,
4581 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4582 xtensa_set_frag_assembly_state (frag_now
);
4584 /* Now put a frag into the literal pool that points to this location. */
4585 set_literal_pool_location (now_seg
, pool_location
);
4586 xtensa_switch_to_non_abs_literal_fragment (&s
);
4587 frag_align (2, 0, 0);
4588 record_alignment (now_seg
, 2);
4590 /* Close whatever frag is there. */
4591 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4592 xtensa_set_frag_assembly_state (frag_now
);
4593 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4594 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4595 xtensa_restore_emit_state (&s
);
4596 xtensa_set_frag_assembly_state (frag_now
);
4600 /* Build a nop of the correct size into tinsn. */
4603 build_nop (TInsn
*tinsn
, int size
)
4609 tinsn
->opcode
= xtensa_nop_n_opcode
;
4611 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4612 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4616 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4618 tinsn
->opcode
= xtensa_or_opcode
;
4619 set_expr_const (&tinsn
->tok
[0], 1);
4620 set_expr_const (&tinsn
->tok
[1], 1);
4621 set_expr_const (&tinsn
->tok
[2], 1);
4625 tinsn
->opcode
= xtensa_nop_opcode
;
4627 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4632 /* Assemble a NOP of the requested size in the buffer. User must have
4633 allocated "buf" with at least "size" bytes. */
4636 assemble_nop (int size
, char *buf
)
4638 static xtensa_insnbuf insnbuf
= NULL
;
4641 build_nop (&tinsn
, size
);
4644 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4646 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4647 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4648 (unsigned char *) buf
, 0);
4652 /* Return the number of bytes for the offset of the expanded loop
4653 instruction. This should be incorporated into the relaxation
4654 specification but is hard-coded here. This is used to auto-align
4655 the loop instruction. It is invalid to call this function if the
4656 configuration does not have loops or if the opcode is not a loop
4660 get_expanded_loop_offset (xtensa_opcode opcode
)
4662 /* This is the OFFSET of the loop instruction in the expanded loop.
4663 This MUST correspond directly to the specification of the loop
4664 expansion. It will be validated on fragment conversion. */
4665 assert (opcode
!= XTENSA_UNDEFINED
);
4666 if (opcode
== xtensa_loop_opcode
)
4668 if (opcode
== xtensa_loopnez_opcode
)
4670 if (opcode
== xtensa_loopgtz_opcode
)
4672 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4678 get_literal_pool_location (segT seg
)
4680 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4685 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4687 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4691 /* Set frag assembly state should be called when a new frag is
4692 opened and after a frag has been closed. */
4695 xtensa_set_frag_assembly_state (fragS
*fragP
)
4697 if (!density_supported
)
4698 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4700 /* This function is called from subsegs_finish, which is called
4701 after xtensa_end, so we can't use "use_transform" or
4702 "use_schedule" here. */
4703 if (!directive_state
[directive_transform
])
4704 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4705 if (directive_state
[directive_longcalls
])
4706 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4707 fragP
->tc_frag_data
.use_absolute_literals
=
4708 directive_state
[directive_absolute_literals
];
4709 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4714 relaxable_section (asection
*sec
)
4716 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4721 xtensa_mark_frags_for_org (void)
4725 /* Walk over each fragment of all of the current segments. If we find
4726 a .org frag in any of the segments, mark all frags prior to it as
4727 "no transform", which will prevent linker optimizations from messing
4728 up the .org distance. This should be done after
4729 xtensa_find_unmarked_state_frags, because we don't want to worry here
4730 about that function trashing the data we save here. */
4732 for (seclist
= &stdoutput
->sections
;
4733 seclist
&& *seclist
;
4734 seclist
= &(*seclist
)->next
)
4736 segT sec
= *seclist
;
4737 segment_info_type
*seginfo
;
4740 flags
= bfd_get_section_flags (stdoutput
, sec
);
4741 if (flags
& SEC_DEBUGGING
)
4743 if (!(flags
& SEC_ALLOC
))
4746 seginfo
= seg_info (sec
);
4747 if (seginfo
&& seginfo
->frchainP
)
4749 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4750 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4751 fragP
= fragP
->fr_next
)
4753 /* cvt_frag_to_fill has changed the fr_type of org frags to
4754 rs_fill, so use the value as cached in rs_subtype here. */
4755 if (fragP
->fr_subtype
== RELAX_ORG
)
4757 while (last_fragP
!= fragP
->fr_next
)
4759 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4760 last_fragP
= last_fragP
->fr_next
;
4770 xtensa_find_unmarked_state_frags (void)
4774 /* Walk over each fragment of all of the current segments. For each
4775 unmarked fragment, mark it with the same info as the previous
4777 for (seclist
= &stdoutput
->sections
;
4778 seclist
&& *seclist
;
4779 seclist
= &(*seclist
)->next
)
4781 segT sec
= *seclist
;
4782 segment_info_type
*seginfo
;
4785 flags
= bfd_get_section_flags (stdoutput
, sec
);
4786 if (flags
& SEC_DEBUGGING
)
4788 if (!(flags
& SEC_ALLOC
))
4791 seginfo
= seg_info (sec
);
4792 if (seginfo
&& seginfo
->frchainP
)
4794 fragS
*last_fragP
= 0;
4795 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4796 fragP
= fragP
->fr_next
)
4798 if (fragP
->fr_fix
!= 0
4799 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4801 if (last_fragP
== 0)
4803 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4804 _("assembly state not set for first frag in section %s"),
4809 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4810 fragP
->tc_frag_data
.is_no_density
=
4811 last_fragP
->tc_frag_data
.is_no_density
;
4812 fragP
->tc_frag_data
.is_no_transform
=
4813 last_fragP
->tc_frag_data
.is_no_transform
;
4814 fragP
->tc_frag_data
.use_longcalls
=
4815 last_fragP
->tc_frag_data
.use_longcalls
;
4816 fragP
->tc_frag_data
.use_absolute_literals
=
4817 last_fragP
->tc_frag_data
.use_absolute_literals
;
4820 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4829 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4831 void *unused ATTRIBUTE_UNUSED
)
4833 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4834 segment_info_type
*seginfo
= seg_info (sec
);
4835 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4837 if (flags
& SEC_CODE
)
4839 xtensa_isa isa
= xtensa_default_isa
;
4840 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4841 while (frag
!= NULL
)
4843 if (frag
->tc_frag_data
.is_branch_target
)
4846 addressT branch_align
, frag_addr
;
4849 xtensa_insnbuf_from_chars
4850 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4851 fmt
= xtensa_format_decode (isa
, insnbuf
);
4852 op_size
= xtensa_format_length (isa
, fmt
);
4853 branch_align
= 1 << branch_align_power (sec
);
4854 frag_addr
= frag
->fr_address
% branch_align
;
4855 if (frag_addr
+ op_size
> branch_align
)
4856 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4857 _("unaligned branch target: %d bytes at 0x%lx"),
4858 op_size
, (long) frag
->fr_address
);
4860 frag
= frag
->fr_next
;
4862 xtensa_insnbuf_free (isa
, insnbuf
);
4868 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4870 void *unused ATTRIBUTE_UNUSED
)
4872 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4873 segment_info_type
*seginfo
= seg_info (sec
);
4874 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4875 xtensa_isa isa
= xtensa_default_isa
;
4877 if (flags
& SEC_CODE
)
4879 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4880 while (frag
!= NULL
)
4882 if (frag
->tc_frag_data
.is_first_loop_insn
)
4888 xtensa_insnbuf_from_chars
4889 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4890 fmt
= xtensa_format_decode (isa
, insnbuf
);
4891 op_size
= xtensa_format_length (isa
, fmt
);
4892 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4894 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4895 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4896 _("unaligned loop: %d bytes at 0x%lx"),
4897 op_size
, (long) frag
->fr_address
);
4899 frag
= frag
->fr_next
;
4901 xtensa_insnbuf_free (isa
, insnbuf
);
4907 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4909 xtensa_isa isa
= xtensa_default_isa
;
4910 static xtensa_insnbuf insnbuf
= NULL
;
4911 static xtensa_insnbuf slotbuf
= NULL
;
4914 bfd_boolean alt_reloc
;
4915 xtensa_opcode opcode
;
4916 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4918 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4920 as_fatal (_("unexpected fix"));
4924 insnbuf
= xtensa_insnbuf_alloc (isa
);
4925 slotbuf
= xtensa_insnbuf_alloc (isa
);
4928 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4929 fmt
= xtensa_format_decode (isa
, insnbuf
);
4930 if (fmt
== XTENSA_UNDEFINED
)
4931 as_fatal (_("undecodable fix"));
4932 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4933 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4934 if (opcode
== XTENSA_UNDEFINED
)
4935 as_fatal (_("undecodable fix"));
4937 /* CONST16 immediates are not PC-relative, despite the fact that we
4938 reuse the normal PC-relative operand relocations for the low part
4939 of a CONST16 operand. */
4940 if (opcode
== xtensa_const16_opcode
)
4943 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4944 get_relaxable_immed (opcode
), val
,
4945 fixP
->fx_file
, fixP
->fx_line
);
4947 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4948 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4954 /* External Functions and Other GAS Hooks. */
4957 xtensa_target_format (void)
4959 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4964 xtensa_file_arch_init (bfd
*abfd
)
4966 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4971 md_number_to_chars (char *buf
, valueT val
, int n
)
4973 if (target_big_endian
)
4974 number_to_chars_bigendian (buf
, val
, n
);
4976 number_to_chars_littleendian (buf
, val
, n
);
4980 /* This function is called once, at assembler startup time. It should
4981 set up all the tables, etc. that the MD part of the assembler will
4987 segT current_section
= now_seg
;
4988 int current_subsec
= now_subseg
;
4991 xtensa_default_isa
= xtensa_isa_init (0, 0);
4992 isa
= xtensa_default_isa
;
4996 /* Set up the literal sections. */
4997 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4999 subseg_set (current_section
, current_subsec
);
5001 xg_init_vinsn (&cur_vinsn
);
5003 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5004 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5005 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5006 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5007 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5008 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5009 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5010 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5011 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5012 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5013 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5014 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5015 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5016 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5017 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5018 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5019 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5020 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5021 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5022 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5023 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5024 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5025 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5026 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5027 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5028 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5029 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5030 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5031 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5033 init_op_placement_info_table ();
5035 /* Set up the assembly state. */
5036 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5037 xtensa_set_frag_assembly_state (frag_now
);
5041 /* TC_INIT_FIX_DATA hook */
5044 xtensa_init_fix_data (fixS
*x
)
5046 x
->tc_fix_data
.slot
= 0;
5047 x
->tc_fix_data
.X_add_symbol
= NULL
;
5048 x
->tc_fix_data
.X_add_number
= 0;
5052 /* tc_frob_label hook */
5055 xtensa_frob_label (symbolS
*sym
)
5059 if (cur_vinsn
.inside_bundle
)
5061 as_bad (_("labels are not valid inside bundles"));
5065 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5067 /* Since the label was already attached to a frag associated with the
5068 previous basic block, it now needs to be reset to the current frag. */
5069 symbol_set_frag (sym
, frag_now
);
5070 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5072 if (generating_literals
)
5073 xtensa_add_literal_sym (sym
);
5075 xtensa_add_insn_label (sym
);
5077 if (symbol_get_tc (sym
)->is_loop_target
)
5079 if ((get_last_insn_flags (now_seg
, now_subseg
)
5080 & FLAG_IS_BAD_LOOPEND
) != 0)
5081 as_bad (_("invalid last instruction for a zero-overhead loop"));
5083 xtensa_set_frag_assembly_state (frag_now
);
5084 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5085 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5087 xtensa_set_frag_assembly_state (frag_now
);
5088 xtensa_move_labels (frag_now
, 0);
5091 /* No target aligning in the absolute section. */
5092 if (now_seg
!= absolute_section
5093 && do_align_targets ()
5094 && !is_unaligned_label (sym
)
5095 && !generating_literals
)
5097 xtensa_set_frag_assembly_state (frag_now
);
5099 frag_var (rs_machine_dependent
,
5101 RELAX_DESIRE_ALIGN_IF_TARGET
,
5102 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5103 xtensa_set_frag_assembly_state (frag_now
);
5104 xtensa_move_labels (frag_now
, 0);
5107 /* We need to mark the following properties even if we aren't aligning. */
5109 /* If the label is already known to be a branch target, i.e., a
5110 forward branch, mark the frag accordingly. Backward branches
5111 are handled by xg_add_branch_and_loop_targets. */
5112 if (symbol_get_tc (sym
)->is_branch_target
)
5113 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5115 /* Loops only go forward, so they can be identified here. */
5116 if (symbol_get_tc (sym
)->is_loop_target
)
5117 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5119 dwarf2_emit_label (sym
);
5123 /* tc_unrecognized_line hook */
5126 xtensa_unrecognized_line (int ch
)
5131 if (cur_vinsn
.inside_bundle
== 0)
5133 /* PR8110: Cannot emit line number info inside a FLIX bundle
5134 when using --gstabs. Temporarily disable debug info. */
5135 generate_lineno_debug ();
5136 if (debug_type
== DEBUG_STABS
)
5138 xt_saved_debug_type
= debug_type
;
5139 debug_type
= DEBUG_NONE
;
5142 cur_vinsn
.inside_bundle
= 1;
5146 as_bad (_("extra opening brace"));
5152 if (cur_vinsn
.inside_bundle
)
5153 finish_vinsn (&cur_vinsn
);
5156 as_bad (_("extra closing brace"));
5161 as_bad (_("syntax error"));
5168 /* md_flush_pending_output hook */
5171 xtensa_flush_pending_output (void)
5173 /* This line fixes a bug where automatically generated gstabs info
5174 separates a function label from its entry instruction, ending up
5175 with the literal position between the function label and the entry
5176 instruction and crashing code. It only happens with --gstabs and
5177 --text-section-literals, and when several other obscure relaxation
5178 conditions are met. */
5179 if (outputting_stabs_line_debug
)
5182 if (cur_vinsn
.inside_bundle
)
5183 as_bad (_("missing closing brace"));
5185 /* If there is a non-zero instruction fragment, close it. */
5186 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5188 frag_wane (frag_now
);
5190 xtensa_set_frag_assembly_state (frag_now
);
5192 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5194 xtensa_clear_insn_labels ();
5198 /* We had an error while parsing an instruction. The string might look
5199 like this: "insn arg1, arg2 }". If so, we need to see the closing
5200 brace and reset some fields. Otherwise, the vinsn never gets closed
5201 and the num_slots field will grow past the end of the array of slots,
5202 and bad things happen. */
5205 error_reset_cur_vinsn (void)
5207 if (cur_vinsn
.inside_bundle
)
5209 if (*input_line_pointer
== '}'
5210 || *(input_line_pointer
- 1) == '}'
5211 || *(input_line_pointer
- 2) == '}')
5212 xg_clear_vinsn (&cur_vinsn
);
5218 md_assemble (char *str
)
5220 xtensa_isa isa
= xtensa_default_isa
;
5221 char *opname
, *file_name
;
5223 bfd_boolean has_underbar
= FALSE
;
5224 char *arg_strings
[MAX_INSN_ARGS
];
5226 TInsn orig_insn
; /* Original instruction from the input. */
5228 tinsn_init (&orig_insn
);
5230 /* Split off the opcode. */
5231 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5232 opname
= xmalloc (opnamelen
+ 1);
5233 memcpy (opname
, str
, opnamelen
);
5234 opname
[opnamelen
] = '\0';
5236 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5239 as_bad (_("syntax error"));
5243 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5246 /* Check for an underbar prefix. */
5249 has_underbar
= TRUE
;
5253 orig_insn
.insn_type
= ITYPE_INSN
;
5255 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5257 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5258 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5260 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5261 if (fmt
== XTENSA_UNDEFINED
)
5263 as_bad (_("unknown opcode or format name '%s'"), opname
);
5264 error_reset_cur_vinsn ();
5267 if (!cur_vinsn
.inside_bundle
)
5269 as_bad (_("format names only valid inside bundles"));
5270 error_reset_cur_vinsn ();
5273 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5274 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5276 cur_vinsn
.format
= fmt
;
5277 free (has_underbar
? opname
- 1 : opname
);
5278 error_reset_cur_vinsn ();
5282 /* Parse the arguments. */
5283 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5285 as_bad (_("syntax error"));
5286 error_reset_cur_vinsn ();
5290 /* Free the opcode and argument strings, now that they've been parsed. */
5291 free (has_underbar
? opname
- 1 : opname
);
5293 while (num_args
-- > 0)
5294 free (arg_strings
[num_args
]);
5296 /* Get expressions for invisible operands. */
5297 if (get_invisible_operands (&orig_insn
))
5299 error_reset_cur_vinsn ();
5303 /* Check for the right number and type of arguments. */
5304 if (tinsn_check_arguments (&orig_insn
))
5306 error_reset_cur_vinsn ();
5310 /* A FLIX bundle may be spread across multiple input lines. We want to
5311 report the first such line in the debug information. Record the line
5312 number for each TInsn (assume the file name doesn't change), so the
5313 first line can be found later. */
5314 as_where (&file_name
, &orig_insn
.linenum
);
5316 xg_add_branch_and_loop_targets (&orig_insn
);
5318 /* Check that immediate value for ENTRY is >= 16. */
5319 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5321 expressionS
*exp
= &orig_insn
.tok
[2];
5322 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5323 as_warn (_("entry instruction with stack decrement < 16"));
5327 assemble_tokens (opcode, tok, ntok);
5328 expand the tokens from the orig_insn into the
5329 stack of instructions that will not expand
5330 unless required at relaxation time. */
5332 if (!cur_vinsn
.inside_bundle
)
5333 emit_single_op (&orig_insn
);
5334 else /* We are inside a bundle. */
5336 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5337 cur_vinsn
.num_slots
++;
5338 if (*input_line_pointer
== '}'
5339 || *(input_line_pointer
- 1) == '}'
5340 || *(input_line_pointer
- 2) == '}')
5341 finish_vinsn (&cur_vinsn
);
5344 /* We've just emitted a new instruction so clear the list of labels. */
5345 xtensa_clear_insn_labels ();
5349 /* HANDLE_ALIGN hook */
5351 /* For a .align directive, we mark the previous block with the alignment
5352 information. This will be placed in the object file in the
5353 property section corresponding to this section. */
5356 xtensa_handle_align (fragS
*fragP
)
5359 && ! fragP
->tc_frag_data
.is_literal
5360 && (fragP
->fr_type
== rs_align
5361 || fragP
->fr_type
== rs_align_code
)
5362 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5363 && fragP
->fr_offset
> 0
5364 && now_seg
!= bss_section
)
5366 fragP
->tc_frag_data
.is_align
= TRUE
;
5367 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5370 if (fragP
->fr_type
== rs_align_test
)
5373 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5375 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5376 _("unaligned entry instruction"));
5379 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5380 fragP
->fr_subtype
= RELAX_ORG
;
5384 /* TC_FRAG_INIT hook */
5387 xtensa_frag_init (fragS
*frag
)
5389 xtensa_set_frag_assembly_state (frag
);
5394 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5400 /* Round up a section size to the appropriate boundary. */
5403 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5405 return size
; /* Byte alignment is fine. */
5410 md_pcrel_from (fixS
*fixP
)
5413 static xtensa_insnbuf insnbuf
= NULL
;
5414 static xtensa_insnbuf slotbuf
= NULL
;
5417 xtensa_opcode opcode
;
5420 xtensa_isa isa
= xtensa_default_isa
;
5421 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5422 bfd_boolean alt_reloc
;
5424 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5429 insnbuf
= xtensa_insnbuf_alloc (isa
);
5430 slotbuf
= xtensa_insnbuf_alloc (isa
);
5433 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5434 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5435 fmt
= xtensa_format_decode (isa
, insnbuf
);
5437 if (fmt
== XTENSA_UNDEFINED
)
5438 as_fatal (_("bad instruction format"));
5440 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5441 as_fatal (_("invalid relocation"));
5443 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5444 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5446 /* Check for "alternate" relocations (operand not specified). None
5447 of the current uses for these are really PC-relative. */
5448 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5450 if (opcode
!= xtensa_l32r_opcode
5451 && opcode
!= xtensa_const16_opcode
)
5452 as_fatal (_("invalid relocation for '%s' instruction"),
5453 xtensa_opcode_name (isa
, opcode
));
5457 opnum
= get_relaxable_immed (opcode
);
5459 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5460 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5462 as_bad_where (fixP
->fx_file
,
5464 _("invalid relocation for operand %d of '%s'"),
5465 opnum
, xtensa_opcode_name (isa
, opcode
));
5468 return 0 - opnd_value
;
5472 /* TC_FORCE_RELOCATION hook */
5475 xtensa_force_relocation (fixS
*fix
)
5477 switch (fix
->fx_r_type
)
5479 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5480 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5481 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5482 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5483 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5484 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5485 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5486 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5487 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5488 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5489 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5490 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5491 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5492 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5493 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5494 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5500 if (linkrelax
&& fix
->fx_addsy
5501 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5504 return generic_force_reloc (fix
);
5508 /* TC_VALIDATE_FIX_SUB hook */
5511 xtensa_validate_fix_sub (fixS
*fix
)
5513 segT add_symbol_segment
, sub_symbol_segment
;
5515 /* The difference of two symbols should be resolved by the assembler when
5516 linkrelax is not set. If the linker may relax the section containing
5517 the symbols, then an Xtensa DIFF relocation must be generated so that
5518 the linker knows to adjust the difference value. */
5519 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5522 /* Make sure both symbols are in the same segment, and that segment is
5523 "normal" and relaxable. If the segment is not "normal", then the
5524 fix is not valid. If the segment is not "relaxable", then the fix
5525 should have been handled earlier. */
5526 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5527 if (! SEG_NORMAL (add_symbol_segment
) ||
5528 ! relaxable_section (add_symbol_segment
))
5530 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5531 return (sub_symbol_segment
== add_symbol_segment
);
5535 /* NO_PSEUDO_DOT hook */
5537 /* This function has nothing to do with pseudo dots, but this is the
5538 nearest macro to where the check needs to take place. FIXME: This
5542 xtensa_check_inside_bundle (void)
5544 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5545 as_bad (_("directives are not valid inside bundles"));
5547 /* This function must always return FALSE because it is called via a
5548 macro that has nothing to do with bundling. */
5553 /* md_elf_section_change_hook */
5556 xtensa_elf_section_change_hook (void)
5558 /* Set up the assembly state. */
5559 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5560 xtensa_set_frag_assembly_state (frag_now
);
5564 /* tc_fix_adjustable hook */
5567 xtensa_fix_adjustable (fixS
*fixP
)
5569 /* An offset is not allowed in combination with the difference of two
5570 symbols, but that cannot be easily detected after a local symbol
5571 has been adjusted to a (section+offset) form. Return 0 so that such
5572 an fix will not be adjusted. */
5573 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5574 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5577 /* We need the symbol name for the VTABLE entries. */
5578 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5579 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5587 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5589 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5592 /* Subtracted symbols are only allowed for a few relocation types, and
5593 unless linkrelax is enabled, they should not make it to this point. */
5594 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5595 || fixP
->fx_r_type
== BFD_RELOC_16
5596 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5599 switch (fixP
->fx_r_type
)
5606 switch (fixP
->fx_r_type
)
5609 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5612 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5615 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5621 /* An offset is only allowed when it results from adjusting a
5622 local symbol into a section-relative offset. If the offset
5623 came from the original expression, tc_fix_adjustable will have
5624 prevented the fix from being converted to a section-relative
5625 form so that we can flag the error here. */
5626 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5628 _("cannot represent subtraction with an offset"));
5630 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5631 - S_GET_VALUE (fixP
->fx_subsy
));
5633 /* The difference value gets written out, and the DIFF reloc
5634 identifies the address of the subtracted symbol (i.e., the one
5635 with the lowest address). */
5637 fixP
->fx_offset
-= val
;
5638 fixP
->fx_subsy
= NULL
;
5640 else if (! fixP
->fx_addsy
)
5647 case BFD_RELOC_XTENSA_PLT
:
5648 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5649 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5652 case BFD_RELOC_XTENSA_SLOT0_OP
:
5653 case BFD_RELOC_XTENSA_SLOT1_OP
:
5654 case BFD_RELOC_XTENSA_SLOT2_OP
:
5655 case BFD_RELOC_XTENSA_SLOT3_OP
:
5656 case BFD_RELOC_XTENSA_SLOT4_OP
:
5657 case BFD_RELOC_XTENSA_SLOT5_OP
:
5658 case BFD_RELOC_XTENSA_SLOT6_OP
:
5659 case BFD_RELOC_XTENSA_SLOT7_OP
:
5660 case BFD_RELOC_XTENSA_SLOT8_OP
:
5661 case BFD_RELOC_XTENSA_SLOT9_OP
:
5662 case BFD_RELOC_XTENSA_SLOT10_OP
:
5663 case BFD_RELOC_XTENSA_SLOT11_OP
:
5664 case BFD_RELOC_XTENSA_SLOT12_OP
:
5665 case BFD_RELOC_XTENSA_SLOT13_OP
:
5666 case BFD_RELOC_XTENSA_SLOT14_OP
:
5669 /* Write the tentative value of a PC-relative relocation to a
5670 local symbol into the instruction. The value will be ignored
5671 by the linker, and it makes the object file disassembly
5672 readable when all branch targets are encoded in relocations. */
5674 assert (fixP
->fx_addsy
);
5675 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5676 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5678 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5679 - md_pcrel_from (fixP
));
5680 (void) xg_apply_fix_value (fixP
, val
);
5683 else if (! fixP
->fx_addsy
)
5686 if (xg_apply_fix_value (fixP
, val
))
5691 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5692 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5693 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5694 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5695 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5696 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5697 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5698 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5699 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5700 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5701 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5702 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5703 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5704 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5705 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5706 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5707 /* These all need to be resolved at link-time. Do nothing now. */
5710 case BFD_RELOC_VTABLE_INHERIT
:
5711 case BFD_RELOC_VTABLE_ENTRY
:
5716 as_bad (_("unhandled local relocation fix %s"),
5717 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5723 md_atof (int type
, char *litP
, int *sizeP
)
5726 LITTLENUM_TYPE words
[4];
5742 return "bad call to md_atof";
5745 t
= atof_ieee (input_line_pointer
, type
, words
);
5747 input_line_pointer
= t
;
5751 for (i
= prec
- 1; i
>= 0; i
--)
5754 if (target_big_endian
)
5755 idx
= (prec
- 1 - i
);
5757 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5766 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5768 return total_frag_text_expansion (fragP
);
5772 /* Translate internal representation of relocation info to BFD target
5776 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5780 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5781 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5782 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5783 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5785 /* Make sure none of our internal relocations make it this far.
5786 They'd better have been fully resolved by this point. */
5787 assert ((int) fixp
->fx_r_type
> 0);
5789 reloc
->addend
= fixp
->fx_offset
;
5791 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5792 if (reloc
->howto
== NULL
)
5794 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5795 _("cannot represent `%s' relocation in object file"),
5796 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5797 free (reloc
->sym_ptr_ptr
);
5802 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5803 as_fatal (_("internal error? cannot generate `%s' relocation"),
5804 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5810 /* Checks for resource conflicts between instructions. */
5812 /* The func unit stuff could be implemented as bit-vectors rather
5813 than the iterative approach here. If it ends up being too
5814 slow, we will switch it. */
5817 new_resource_table (void *data
,
5820 unit_num_copies_func uncf
,
5821 opcode_num_units_func onuf
,
5822 opcode_funcUnit_use_unit_func ouuf
,
5823 opcode_funcUnit_use_stage_func ousf
)
5826 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5828 rt
->cycles
= cycles
;
5829 rt
->allocated_cycles
= cycles
;
5831 rt
->unit_num_copies
= uncf
;
5832 rt
->opcode_num_units
= onuf
;
5833 rt
->opcode_unit_use
= ouuf
;
5834 rt
->opcode_unit_stage
= ousf
;
5836 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5837 for (i
= 0; i
< cycles
; i
++)
5838 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5845 clear_resource_table (resource_table
*rt
)
5848 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5849 for (j
= 0; j
< rt
->num_units
; j
++)
5850 rt
->units
[i
][j
] = 0;
5854 /* We never shrink it, just fake it into thinking so. */
5857 resize_resource_table (resource_table
*rt
, int cycles
)
5861 rt
->cycles
= cycles
;
5862 if (cycles
<= rt
->allocated_cycles
)
5865 old_cycles
= rt
->allocated_cycles
;
5866 rt
->allocated_cycles
= cycles
;
5868 rt
->units
= xrealloc (rt
->units
,
5869 rt
->allocated_cycles
* sizeof (unsigned char *));
5870 for (i
= 0; i
< old_cycles
; i
++)
5871 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5872 rt
->num_units
* sizeof (unsigned char));
5873 for (i
= old_cycles
; i
< cycles
; i
++)
5874 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5879 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5882 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5884 for (i
= 0; i
< uses
; i
++)
5886 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5887 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5888 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5889 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5890 if (copies_in_use
>= copies
)
5898 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5901 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5903 for (i
= 0; i
< uses
; i
++)
5905 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5906 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5907 /* Note that this allows resources to be oversubscribed. That's
5908 essential to the way the optional scheduler works.
5909 resources_available reports when a resource is over-subscribed,
5910 so it's easy to tell. */
5911 rt
->units
[stage
+ cycle
][unit
]++;
5917 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5920 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5922 for (i
= 0; i
< uses
; i
++)
5924 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5925 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5926 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5927 rt
->units
[stage
+ cycle
][unit
]--;
5932 /* Wrapper functions make parameterized resource reservation
5936 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5938 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5944 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5946 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5951 /* Note that this function does not check issue constraints, but
5952 solely whether the hardware is available to execute the given
5953 instructions together. It also doesn't check if the tinsns
5954 write the same state, or access the same tieports. That is
5955 checked by check_t1_t2_reads_and_writes. */
5958 resources_conflict (vliw_insn
*vinsn
)
5961 static resource_table
*rt
= NULL
;
5963 /* This is the most common case by far. Optimize it. */
5964 if (vinsn
->num_slots
== 1)
5969 xtensa_isa isa
= xtensa_default_isa
;
5970 rt
= new_resource_table
5971 (isa
, xtensa_isa_num_pipe_stages (isa
),
5972 xtensa_isa_num_funcUnits (isa
),
5973 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5974 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5975 opcode_funcUnit_use_unit
,
5976 opcode_funcUnit_use_stage
);
5979 clear_resource_table (rt
);
5981 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5983 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5985 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5992 /* finish_vinsn, emit_single_op and helper functions. */
5994 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5995 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5996 static void xg_assemble_vliw_tokens (vliw_insn
*);
5999 /* We have reached the end of a bundle; emit into the frag. */
6002 finish_vinsn (vliw_insn
*vinsn
)
6009 if (find_vinsn_conflicts (vinsn
))
6011 xg_clear_vinsn (vinsn
);
6015 /* First, find a format that works. */
6016 if (vinsn
->format
== XTENSA_UNDEFINED
)
6017 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6019 if (vinsn
->format
== XTENSA_UNDEFINED
)
6021 as_where (&file_name
, &line
);
6022 as_bad_where (file_name
, line
,
6023 _("couldn't find a valid instruction format"));
6024 fprintf (stderr
, _(" ops were: "));
6025 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6026 fprintf (stderr
, _(" %s;"),
6027 xtensa_opcode_name (xtensa_default_isa
,
6028 vinsn
->slots
[i
].opcode
));
6029 fprintf (stderr
, _("\n"));
6030 xg_clear_vinsn (vinsn
);
6034 if (vinsn
->num_slots
6035 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6037 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6038 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6039 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6041 xg_clear_vinsn (vinsn
);
6045 if (resources_conflict (vinsn
))
6047 as_where (&file_name
, &line
);
6048 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6049 fprintf (stderr
, " ops were: ");
6050 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6051 fprintf (stderr
, " %s;",
6052 xtensa_opcode_name (xtensa_default_isa
,
6053 vinsn
->slots
[i
].opcode
));
6054 fprintf (stderr
, "\n");
6055 xg_clear_vinsn (vinsn
);
6059 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6061 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6063 symbolS
*lit_sym
= NULL
;
6065 bfd_boolean e
= FALSE
;
6066 bfd_boolean saved_density
= density_supported
;
6068 /* We don't want to narrow ops inside multi-slot bundles. */
6069 if (vinsn
->num_slots
> 1)
6070 density_supported
= FALSE
;
6072 istack_init (&slotstack
);
6073 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6075 vinsn
->slots
[i
].opcode
=
6076 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6078 vinsn
->slots
[i
].ntok
= 0;
6081 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6087 density_supported
= saved_density
;
6091 xg_clear_vinsn (vinsn
);
6095 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6097 TInsn
*insn
= &slotstack
.insn
[j
];
6098 if (insn
->insn_type
== ITYPE_LITERAL
)
6100 assert (lit_sym
== NULL
);
6101 lit_sym
= xg_assemble_literal (insn
);
6105 assert (insn
->insn_type
== ITYPE_INSN
);
6107 xg_resolve_literals (insn
, lit_sym
);
6108 if (j
!= slotstack
.ninsn
- 1)
6109 emit_single_op (insn
);
6113 if (vinsn
->num_slots
> 1)
6115 if (opcode_fits_format_slot
6116 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6119 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6123 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6124 if (vinsn
->format
== XTENSA_UNDEFINED
)
6125 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6127 vinsn
->slots
[i
].opcode
6128 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6131 vinsn
->slots
[i
].ntok
= 0;
6136 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6137 vinsn
->format
= XTENSA_UNDEFINED
;
6142 /* Now check resource conflicts on the modified bundle. */
6143 if (resources_conflict (vinsn
))
6145 as_where (&file_name
, &line
);
6146 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6147 fprintf (stderr
, " ops were: ");
6148 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6149 fprintf (stderr
, " %s;",
6150 xtensa_opcode_name (xtensa_default_isa
,
6151 vinsn
->slots
[i
].opcode
));
6152 fprintf (stderr
, "\n");
6153 xg_clear_vinsn (vinsn
);
6157 /* First, find a format that works. */
6158 if (vinsn
->format
== XTENSA_UNDEFINED
)
6159 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6161 xg_assemble_vliw_tokens (vinsn
);
6163 xg_clear_vinsn (vinsn
);
6167 /* Given an vliw instruction, what conflicts are there in register
6168 usage and in writes to states and queues?
6170 This function does two things:
6171 1. Reports an error when a vinsn contains illegal combinations
6172 of writes to registers states or queues.
6173 2. Marks individual tinsns as not relaxable if the combination
6174 contains antidependencies.
6176 Job 2 handles things like swap semantics in instructions that need
6177 to be relaxed. For example,
6181 normally would be relaxed to
6186 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6188 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6190 then we can't relax it into
6193 { add a0, a1, a0 ; add a2, a0, a4 ; }
6195 because the value of a0 is trashed before the second add can read it. */
6197 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6200 find_vinsn_conflicts (vliw_insn
*vinsn
)
6204 xtensa_isa isa
= xtensa_default_isa
;
6206 assert (!past_xtensa_end
);
6208 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6210 TInsn
*op1
= &vinsn
->slots
[i
];
6211 if (op1
->is_specific_opcode
)
6212 op1
->keep_wide
= TRUE
;
6214 op1
->keep_wide
= FALSE
;
6217 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6219 TInsn
*op1
= &vinsn
->slots
[i
];
6221 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6224 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6228 TInsn
*op2
= &vinsn
->slots
[j
];
6229 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6230 switch (conflict_type
)
6233 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6234 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6235 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6238 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6239 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6240 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6243 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6244 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6245 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6248 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6249 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6250 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6253 /* Everything is OK. */
6256 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6257 || conflict_type
== 'a');
6264 as_bad (_("multiple branches or jumps in the same bundle"));
6272 /* Check how the state used by t1 and t2 relate.
6275 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6276 case B: no relationship between what is read and written (both could
6277 read the same reg though)
6278 case C: t1 writes a register t2 writes (a register conflict within a
6280 case D: t1 writes a state that t2 also writes
6281 case E: t1 writes a tie queue that t2 also writes
6282 case F: two volatile queue accesses
6286 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6288 xtensa_isa isa
= xtensa_default_isa
;
6289 xtensa_regfile t1_regfile
, t2_regfile
;
6291 int t1_base_reg
, t1_last_reg
;
6292 int t2_base_reg
, t2_last_reg
;
6293 char t1_inout
, t2_inout
;
6295 char conflict
= 'b';
6300 bfd_boolean t1_volatile
= FALSE
;
6301 bfd_boolean t2_volatile
= FALSE
;
6303 /* Check registers. */
6304 for (j
= 0; j
< t2
->ntok
; j
++)
6306 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6309 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6310 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6311 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6313 for (i
= 0; i
< t1
->ntok
; i
++)
6315 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6318 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6320 if (t1_regfile
!= t2_regfile
)
6323 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6324 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6326 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6327 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6329 if (t1_inout
== 'm' || t1_inout
== 'o'
6330 || t2_inout
== 'm' || t2_inout
== 'o')
6337 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6338 t1_last_reg
= (t1_base_reg
6339 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6341 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6343 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6345 if (t1_reg
!= t2_reg
)
6348 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6354 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6360 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6368 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6369 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6370 for (j
= 0; j
< t2_states
; j
++)
6372 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6373 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6374 for (i
= 0; i
< t1_states
; i
++)
6376 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6377 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6381 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6387 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6393 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6398 /* Check tieports. */
6399 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6400 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6401 for (j
= 0; j
< t2_interfaces
; j
++)
6403 xtensa_interface t2_int
6404 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6405 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6407 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6408 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6411 for (i
= 0; i
< t1_interfaces
; i
++)
6413 xtensa_interface t1_int
6414 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6415 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6417 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6418 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6421 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6424 if (t1_int
!= t2_int
)
6427 if (t2_inout
== 'i' && t1_inout
== 'o')
6433 if (t1_inout
== 'i' && t2_inout
== 'o')
6439 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6448 static xtensa_format
6449 xg_find_narrowest_format (vliw_insn
*vinsn
)
6451 /* Right now we assume that the ops within the vinsn are properly
6452 ordered for the slots that the programmer wanted them in. In
6453 other words, we don't rearrange the ops in hopes of finding a
6454 better format. The scheduler handles that. */
6456 xtensa_isa isa
= xtensa_default_isa
;
6457 xtensa_format format
;
6458 vliw_insn v_copy
= *vinsn
;
6459 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6461 if (vinsn
->num_slots
== 1)
6462 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6464 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6467 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6471 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6473 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6475 v_copy
.slots
[slot
].opcode
=
6476 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6477 v_copy
.slots
[slot
].ntok
= 0;
6480 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6483 else if (v_copy
.num_slots
> 1)
6486 /* Try the widened version. */
6487 if (!v_copy
.slots
[slot
].keep_wide
6488 && !v_copy
.slots
[slot
].is_specific_opcode
6489 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6491 && opcode_fits_format_slot (widened
.opcode
,
6494 v_copy
.slots
[slot
] = widened
;
6499 if (fit
== v_copy
.num_slots
)
6502 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6503 vinsn
->format
= format
;
6509 if (format
== xtensa_isa_num_formats (isa
))
6510 return XTENSA_UNDEFINED
;
6516 /* Return the additional space needed in a frag
6517 for possible relaxations of any ops in a VLIW insn.
6518 Also fill out the relaxations that might be required of
6519 each tinsn in the vinsn. */
6522 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6524 bfd_boolean finish_frag
= FALSE
;
6525 int extra_space
= 0;
6528 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6530 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6531 if (!tinsn_has_symbolic_operands (tinsn
))
6533 /* A narrow instruction could be widened later to help
6534 alignment issues. */
6535 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6536 && !tinsn
->is_specific_opcode
6537 && vinsn
->num_slots
== 1)
6539 /* Difference in bytes between narrow and wide insns... */
6541 tinsn
->subtype
= RELAX_NARROW
;
6546 if (workaround_b_j_loop_end
6547 && tinsn
->opcode
== xtensa_jx_opcode
6548 && use_transform ())
6550 /* Add 2 of these. */
6551 extra_space
+= 3; /* for the nop size */
6552 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6555 /* Need to assemble it with space for the relocation. */
6556 if (xg_is_relaxable_insn (tinsn
, 0)
6557 && !tinsn
->is_specific_opcode
)
6559 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6560 int max_literal_size
=
6561 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6563 tinsn
->literal_space
= max_literal_size
;
6565 tinsn
->subtype
= RELAX_IMMED
;
6566 extra_space
+= max_size
;
6570 /* A fix record will be added for this instruction prior
6571 to relaxation, so make it end the frag. */
6576 *pfinish_frag
= finish_frag
;
6582 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6584 xtensa_isa isa
= xtensa_default_isa
;
6585 int slot
, chosen_slot
;
6587 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6588 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6589 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6591 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6592 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6594 if (slot
== chosen_slot
)
6595 vinsn
->slots
[slot
] = *tinsn
;
6598 vinsn
->slots
[slot
].opcode
=
6599 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6600 vinsn
->slots
[slot
].ntok
= 0;
6601 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6608 emit_single_op (TInsn
*orig_insn
)
6611 IStack istack
; /* put instructions into here */
6612 symbolS
*lit_sym
= NULL
;
6613 symbolS
*label_sym
= NULL
;
6615 istack_init (&istack
);
6617 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6618 Because the scheduling and bundling characteristics of movi and
6619 l32r or const16 are so different, we can do much better if we relax
6620 it prior to scheduling and bundling, rather than after. */
6621 if ((orig_insn
->opcode
== xtensa_movi_opcode
6622 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6623 && !cur_vinsn
.inside_bundle
6624 && (orig_insn
->tok
[1].X_op
== O_symbol
6625 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6626 && !orig_insn
->is_specific_opcode
&& use_transform ())
6627 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6629 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6632 for (i
= 0; i
< istack
.ninsn
; i
++)
6634 TInsn
*insn
= &istack
.insn
[i
];
6635 switch (insn
->insn_type
)
6638 assert (lit_sym
== NULL
);
6639 lit_sym
= xg_assemble_literal (insn
);
6643 static int relaxed_sym_idx
= 0;
6644 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6645 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6647 assert (label_sym
== NULL
);
6648 label_sym
= symbol_find_or_make (label
);
6657 xg_resolve_literals (insn
, lit_sym
);
6659 xg_resolve_labels (insn
, label_sym
);
6661 bundle_tinsn (insn
, &v
);
6676 total_frag_text_expansion (fragS
*fragP
)
6679 int total_expansion
= 0;
6681 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6682 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6684 return total_expansion
;
6688 /* Emit a vliw instruction to the current fragment. */
6691 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6693 bfd_boolean finish_frag
;
6694 bfd_boolean is_jump
= FALSE
;
6695 bfd_boolean is_branch
= FALSE
;
6696 xtensa_isa isa
= xtensa_default_isa
;
6702 unsigned current_line
, best_linenum
;
6705 best_linenum
= UINT_MAX
;
6707 if (generating_literals
)
6709 static int reported
= 0;
6711 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6712 _("cannot assemble into a literal fragment"));
6719 if (frag_now_fix () != 0
6720 && (! frag_now
->tc_frag_data
.is_insn
6721 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6722 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6723 || (directive_state
[directive_longcalls
]
6724 != frag_now
->tc_frag_data
.use_longcalls
)
6725 || (directive_state
[directive_absolute_literals
]
6726 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6728 frag_wane (frag_now
);
6730 xtensa_set_frag_assembly_state (frag_now
);
6733 if (workaround_a0_b_retw
6734 && vinsn
->num_slots
== 1
6735 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6736 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6737 && use_transform ())
6739 has_a0_b_retw
= TRUE
;
6741 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6742 After the first assembly pass we will check all of them and
6743 add a nop if needed. */
6744 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6745 frag_var (rs_machine_dependent
, 4, 4,
6746 RELAX_ADD_NOP_IF_A0_B_RETW
,
6747 frag_now
->fr_symbol
,
6748 frag_now
->fr_offset
,
6750 xtensa_set_frag_assembly_state (frag_now
);
6751 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6752 frag_var (rs_machine_dependent
, 4, 4,
6753 RELAX_ADD_NOP_IF_A0_B_RETW
,
6754 frag_now
->fr_symbol
,
6755 frag_now
->fr_offset
,
6757 xtensa_set_frag_assembly_state (frag_now
);
6760 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6762 /* See if the instruction implies an aligned section. */
6763 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6764 record_alignment (now_seg
, 2);
6766 /* Also determine the best line number for debug info. */
6767 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6768 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6771 /* Special cases for instructions that force an alignment... */
6772 /* None of these opcodes are bundle-able. */
6773 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6777 /* Remember the symbol that marks the end of the loop in the frag
6778 that marks the start of the loop. This way we can easily find
6779 the end of the loop at the beginning, without adding special code
6780 to mark the loop instructions themselves. */
6781 symbolS
*target_sym
= NULL
;
6782 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6783 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6785 xtensa_set_frag_assembly_state (frag_now
);
6786 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6788 max_fill
= get_text_align_max_fill_size
6789 (get_text_align_power (xtensa_fetch_width
),
6790 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6792 if (use_transform ())
6793 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6794 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6796 frag_var (rs_machine_dependent
, 0, 0,
6797 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6798 xtensa_set_frag_assembly_state (frag_now
);
6801 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6802 && !vinsn
->slots
[0].is_specific_opcode
)
6804 xtensa_mark_literal_pool_location ();
6805 xtensa_move_labels (frag_now
, 0);
6806 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6809 if (vinsn
->num_slots
== 1)
6811 if (workaround_a0_b_retw
&& use_transform ())
6812 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6813 is_register_writer (&vinsn
->slots
[0], "a", 0));
6815 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6816 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6819 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6821 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6823 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6825 /* vinsn_to_insnbuf will produce the error. */
6826 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6828 f
= frag_more (insn_size
+ extra_space
);
6829 xtensa_set_frag_assembly_state (frag_now
);
6830 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6833 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6834 if (vinsn
->format
== XTENSA_UNDEFINED
)
6837 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6839 /* Temporarily set the logical line number to the one we want to appear
6840 in the debug information. */
6841 as_where (¤t_file
, ¤t_line
);
6842 new_logical_line (current_file
, best_linenum
);
6843 dwarf2_emit_insn (insn_size
+ extra_space
);
6844 new_logical_line (current_file
, current_line
);
6846 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6848 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6849 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6850 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6851 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6852 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6853 if (tinsn
->literal_space
!= 0)
6854 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6856 if (tinsn
->subtype
== RELAX_NARROW
)
6857 assert (vinsn
->num_slots
== 1);
6858 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6860 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6863 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6864 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6868 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6869 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6873 frag_variant (rs_machine_dependent
,
6874 extra_space
, extra_space
, RELAX_SLOTS
,
6875 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6876 xtensa_set_frag_assembly_state (frag_now
);
6879 /* Special cases for loops:
6880 close_loop_end should be inserted AFTER short_loop.
6881 Make sure that CLOSE loops are processed BEFORE short_loops
6882 when converting them. */
6884 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6885 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6886 && !vinsn
->slots
[0].is_specific_opcode
)
6888 if (workaround_short_loop
&& use_transform ())
6890 maybe_has_short_loop
= TRUE
;
6891 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6892 frag_var (rs_machine_dependent
, 4, 4,
6893 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6894 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6895 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6896 frag_var (rs_machine_dependent
, 4, 4,
6897 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6898 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6901 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6902 loop at least 12 bytes away from another loop's end. */
6903 if (workaround_close_loop_end
&& use_transform ())
6905 maybe_has_close_loop_end
= TRUE
;
6906 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6907 frag_var (rs_machine_dependent
, 12, 12,
6908 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6909 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6913 if (use_transform ())
6917 assert (finish_frag
);
6918 frag_var (rs_machine_dependent
,
6919 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6921 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6922 xtensa_set_frag_assembly_state (frag_now
);
6924 else if (is_branch
&& do_align_targets ())
6926 assert (finish_frag
);
6927 frag_var (rs_machine_dependent
,
6928 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6929 RELAX_MAYBE_UNREACHABLE
,
6930 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6931 xtensa_set_frag_assembly_state (frag_now
);
6932 frag_var (rs_machine_dependent
,
6934 RELAX_MAYBE_DESIRE_ALIGN
,
6935 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6936 xtensa_set_frag_assembly_state (frag_now
);
6940 /* Now, if the original opcode was a call... */
6941 if (do_align_targets ()
6942 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6944 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6945 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6946 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6947 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6948 xtensa_set_frag_assembly_state (frag_now
);
6951 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6953 frag_wane (frag_now
);
6955 xtensa_set_frag_assembly_state (frag_now
);
6960 /* xtensa_end and helper functions. */
6962 static void xtensa_cleanup_align_frags (void);
6963 static void xtensa_fix_target_frags (void);
6964 static void xtensa_mark_narrow_branches (void);
6965 static void xtensa_mark_zcl_first_insns (void);
6966 static void xtensa_fix_a0_b_retw_frags (void);
6967 static void xtensa_fix_b_j_loop_end_frags (void);
6968 static void xtensa_fix_close_loop_end_frags (void);
6969 static void xtensa_fix_short_loop_frags (void);
6970 static void xtensa_sanity_check (void);
6971 static void xtensa_add_config_info (void);
6976 directive_balance ();
6977 xtensa_flush_pending_output ();
6979 past_xtensa_end
= TRUE
;
6981 xtensa_move_literals ();
6983 xtensa_reorder_segments ();
6984 xtensa_cleanup_align_frags ();
6985 xtensa_fix_target_frags ();
6986 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6987 xtensa_fix_a0_b_retw_frags ();
6988 if (workaround_b_j_loop_end
)
6989 xtensa_fix_b_j_loop_end_frags ();
6991 /* "close_loop_end" should be processed BEFORE "short_loop". */
6992 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6993 xtensa_fix_close_loop_end_frags ();
6995 if (workaround_short_loop
&& maybe_has_short_loop
)
6996 xtensa_fix_short_loop_frags ();
6998 xtensa_mark_narrow_branches ();
6999 xtensa_mark_zcl_first_insns ();
7001 xtensa_sanity_check ();
7003 xtensa_add_config_info ();
7008 xtensa_cleanup_align_frags (void)
7013 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7014 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7017 /* Walk over all of the fragments in a subsection. */
7018 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7020 if ((fragP
->fr_type
== rs_align
7021 || fragP
->fr_type
== rs_align_code
7022 || (fragP
->fr_type
== rs_machine_dependent
7023 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7024 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7025 && fragP
->fr_fix
== 0)
7027 fragS
*next
= fragP
->fr_next
;
7030 && next
->fr_fix
== 0
7031 && next
->fr_type
== rs_machine_dependent
7032 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7035 next
= next
->fr_next
;
7038 /* If we don't widen branch targets, then they
7039 will be easier to align. */
7040 if (fragP
->tc_frag_data
.is_branch_target
7041 && fragP
->fr_opcode
== fragP
->fr_literal
7042 && fragP
->fr_type
== rs_machine_dependent
7043 && fragP
->fr_subtype
== RELAX_SLOTS
7044 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7046 if (fragP
->fr_type
== rs_machine_dependent
7047 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7048 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7054 /* Re-process all of the fragments looking to convert all of the
7055 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7056 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7057 Otherwise, convert to a .fill 0. */
7060 xtensa_fix_target_frags (void)
7065 /* When this routine is called, all of the subsections are still intact
7066 so we walk over subsections instead of sections. */
7067 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7068 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7072 /* Walk over all of the fragments in a subsection. */
7073 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7075 if (fragP
->fr_type
== rs_machine_dependent
7076 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7078 if (next_frag_is_branch_target (fragP
))
7079 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7088 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7091 xtensa_mark_narrow_branches (void)
7096 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7097 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7100 /* Walk over all of the fragments in a subsection. */
7101 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7103 if (fragP
->fr_type
== rs_machine_dependent
7104 && fragP
->fr_subtype
== RELAX_SLOTS
7105 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7109 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7110 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7112 if (vinsn
.num_slots
== 1
7113 && xtensa_opcode_is_branch (xtensa_default_isa
,
7114 vinsn
.slots
[0].opcode
) == 1
7115 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7116 && is_narrow_branch_guaranteed_in_range (fragP
,
7119 fragP
->fr_subtype
= RELAX_SLOTS
;
7120 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7121 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7129 /* A branch is typically widened only when its target is out of
7130 range. However, we would like to widen them to align a subsequent
7131 branch target when possible.
7133 Because the branch relaxation code is so convoluted, the optimal solution
7134 (combining the two cases) is difficult to get right in all circumstances.
7135 We therefore go with an "almost as good" solution, where we only
7136 use for alignment narrow branches that definitely will not expand to a
7137 jump and a branch. These functions find and mark these cases. */
7139 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7140 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7141 We start counting beginning with the frag after the 2-byte branch, so the
7142 maximum offset is (4 - 2) + 63 = 65. */
7143 #define MAX_IMMED6 65
7145 static offsetT
unrelaxed_frag_max_size (fragS
*);
7148 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7150 const expressionS
*expr
= &tinsn
->tok
[1];
7151 symbolS
*symbolP
= expr
->X_add_symbol
;
7152 offsetT max_distance
= expr
->X_add_number
;
7155 if (expr
->X_op
!= O_symbol
)
7158 target_frag
= symbol_get_frag (symbolP
);
7160 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7161 if (is_branch_jmp_to_next (tinsn
, fragP
))
7164 /* The branch doesn't branch over it's own frag,
7165 but over the subsequent ones. */
7166 fragP
= fragP
->fr_next
;
7167 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7169 max_distance
+= unrelaxed_frag_max_size (fragP
);
7170 fragP
= fragP
->fr_next
;
7172 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7179 xtensa_mark_zcl_first_insns (void)
7184 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7185 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7188 /* Walk over all of the fragments in a subsection. */
7189 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7191 if (fragP
->fr_type
== rs_machine_dependent
7192 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7193 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7195 /* Find the loop frag. */
7196 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7197 /* Find the first insn frag. */
7198 targ_frag
= next_non_empty_frag (targ_frag
);
7200 /* Of course, sometimes (mostly for toy test cases) a
7201 zero-cost loop instruction is the last in a section. */
7204 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7205 /* Do not widen a frag that is the first instruction of a
7206 zero-cost loop. It makes that loop harder to align. */
7207 if (targ_frag
->fr_type
== rs_machine_dependent
7208 && targ_frag
->fr_subtype
== RELAX_SLOTS
7209 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7212 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7213 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7216 frag_wane (targ_frag
);
7217 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7221 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7229 /* Re-process all of the fragments looking to convert all of the
7230 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7231 conditional branch or a retw/retw.n, convert this frag to one that
7232 will generate a NOP. In any case close it off with a .fill 0. */
7234 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7237 xtensa_fix_a0_b_retw_frags (void)
7242 /* When this routine is called, all of the subsections are still intact
7243 so we walk over subsections instead of sections. */
7244 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7245 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7249 /* Walk over all of the fragments in a subsection. */
7250 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7252 if (fragP
->fr_type
== rs_machine_dependent
7253 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7255 if (next_instrs_are_b_retw (fragP
))
7257 if (fragP
->tc_frag_data
.is_no_transform
)
7258 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7260 relax_frag_add_nop (fragP
);
7270 next_instrs_are_b_retw (fragS
*fragP
)
7272 xtensa_opcode opcode
;
7274 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7275 static xtensa_insnbuf insnbuf
= NULL
;
7276 static xtensa_insnbuf slotbuf
= NULL
;
7277 xtensa_isa isa
= xtensa_default_isa
;
7280 bfd_boolean branch_seen
= FALSE
;
7284 insnbuf
= xtensa_insnbuf_alloc (isa
);
7285 slotbuf
= xtensa_insnbuf_alloc (isa
);
7288 if (next_fragP
== NULL
)
7291 /* Check for the conditional branch. */
7292 xtensa_insnbuf_from_chars
7293 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7294 fmt
= xtensa_format_decode (isa
, insnbuf
);
7295 if (fmt
== XTENSA_UNDEFINED
)
7298 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7300 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7301 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7303 branch_seen
= (branch_seen
7304 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7310 offset
+= xtensa_format_length (isa
, fmt
);
7311 if (offset
== next_fragP
->fr_fix
)
7313 next_fragP
= next_non_empty_frag (next_fragP
);
7317 if (next_fragP
== NULL
)
7320 /* Check for the retw/retw.n. */
7321 xtensa_insnbuf_from_chars
7322 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7323 fmt
= xtensa_format_decode (isa
, insnbuf
);
7325 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7326 have no problems. */
7327 if (fmt
== XTENSA_UNDEFINED
7328 || xtensa_format_num_slots (isa
, fmt
) != 1)
7331 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7332 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7334 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7341 /* Re-process all of the fragments looking to convert all of the
7342 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7343 loop end label, convert this frag to one that will generate a NOP.
7344 In any case close it off with a .fill 0. */
7346 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7349 xtensa_fix_b_j_loop_end_frags (void)
7354 /* When this routine is called, all of the subsections are still intact
7355 so we walk over subsections instead of sections. */
7356 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7357 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7361 /* Walk over all of the fragments in a subsection. */
7362 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7364 if (fragP
->fr_type
== rs_machine_dependent
7365 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7367 if (next_instr_is_loop_end (fragP
))
7369 if (fragP
->tc_frag_data
.is_no_transform
)
7370 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7372 relax_frag_add_nop (fragP
);
7382 next_instr_is_loop_end (fragS
*fragP
)
7384 const fragS
*next_fragP
;
7386 if (next_frag_is_loop_target (fragP
))
7389 next_fragP
= next_non_empty_frag (fragP
);
7390 if (next_fragP
== NULL
)
7393 if (!next_frag_is_loop_target (next_fragP
))
7396 /* If the size is >= 3 then there is more than one instruction here.
7397 The hardware bug will not fire. */
7398 if (next_fragP
->fr_fix
> 3)
7405 /* Re-process all of the fragments looking to convert all of the
7406 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7407 not MY loop's loop end within 12 bytes, add enough nops here to
7408 make it at least 12 bytes away. In any case close it off with a
7411 static offsetT min_bytes_to_other_loop_end
7412 (fragS
*, fragS
*, offsetT
);
7415 xtensa_fix_close_loop_end_frags (void)
7420 /* When this routine is called, all of the subsections are still intact
7421 so we walk over subsections instead of sections. */
7422 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7423 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7427 fragS
*current_target
= NULL
;
7429 /* Walk over all of the fragments in a subsection. */
7430 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7432 if (fragP
->fr_type
== rs_machine_dependent
7433 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7434 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7435 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7438 && fragP
->fr_type
== rs_machine_dependent
7439 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7442 int bytes_added
= 0;
7444 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7445 /* Max out at 12. */
7446 min_bytes
= min_bytes_to_other_loop_end
7447 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7449 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7451 if (fragP
->tc_frag_data
.is_no_transform
)
7452 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7455 while (min_bytes
+ bytes_added
7456 < REQUIRED_LOOP_DIVIDING_BYTES
)
7460 if (fragP
->fr_var
< length
)
7461 as_fatal (_("fr_var %lu < length %d"),
7462 (long) fragP
->fr_var
, length
);
7465 assemble_nop (length
,
7466 fragP
->fr_literal
+ fragP
->fr_fix
);
7467 fragP
->fr_fix
+= length
;
7468 fragP
->fr_var
-= length
;
7470 bytes_added
+= length
;
7476 assert (fragP
->fr_type
!= rs_machine_dependent
7477 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7483 static offsetT
unrelaxed_frag_min_size (fragS
*);
7486 min_bytes_to_other_loop_end (fragS
*fragP
,
7487 fragS
*current_target
,
7491 fragS
*current_fragP
;
7493 for (current_fragP
= fragP
;
7495 current_fragP
= current_fragP
->fr_next
)
7497 if (current_fragP
->tc_frag_data
.is_loop_target
7498 && current_fragP
!= current_target
)
7501 offset
+= unrelaxed_frag_min_size (current_fragP
);
7503 if (offset
>= max_size
)
7511 unrelaxed_frag_min_size (fragS
*fragP
)
7513 offsetT size
= fragP
->fr_fix
;
7515 /* Add fill size. */
7516 if (fragP
->fr_type
== rs_fill
)
7517 size
+= fragP
->fr_offset
;
7524 unrelaxed_frag_max_size (fragS
*fragP
)
7526 offsetT size
= fragP
->fr_fix
;
7527 switch (fragP
->fr_type
)
7530 /* Empty frags created by the obstack allocation scheme
7531 end up with type 0. */
7536 size
+= fragP
->fr_offset
;
7544 /* No further adjustments needed. */
7546 case rs_machine_dependent
:
7547 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7548 size
+= fragP
->fr_var
;
7551 /* We had darn well better know how big it is. */
7560 /* Re-process all of the fragments looking to convert all
7561 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7564 1) the instruction size count to the loop end label
7565 is too short (<= 2 instructions),
7566 2) loop has a jump or branch in it
7569 1) workaround_all_short_loops is TRUE
7570 2) The generating loop was a 'loopgtz' or 'loopnez'
7571 3) the instruction size count to the loop end label is too short
7573 then convert this frag (and maybe the next one) to generate a NOP.
7574 In any case close it off with a .fill 0. */
7576 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7577 static bfd_boolean
branch_before_loop_end (fragS
*);
7580 xtensa_fix_short_loop_frags (void)
7585 /* When this routine is called, all of the subsections are still intact
7586 so we walk over subsections instead of sections. */
7587 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7588 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7591 fragS
*current_target
= NULL
;
7592 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7594 /* Walk over all of the fragments in a subsection. */
7595 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7597 if (fragP
->fr_type
== rs_machine_dependent
7598 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7599 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7602 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7603 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7604 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7605 current_opcode
= t_insn
.opcode
;
7606 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7607 current_opcode
) == 1);
7610 if (fragP
->fr_type
== rs_machine_dependent
7611 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7613 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7614 && (branch_before_loop_end (fragP
->fr_next
)
7615 || (workaround_all_short_loops
7616 && current_opcode
!= XTENSA_UNDEFINED
7617 && current_opcode
!= xtensa_loop_opcode
)))
7619 if (fragP
->tc_frag_data
.is_no_transform
)
7620 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7622 relax_frag_add_nop (fragP
);
7631 static int unrelaxed_frag_min_insn_count (fragS
*);
7634 count_insns_to_loop_end (fragS
*base_fragP
,
7635 bfd_boolean count_relax_add
,
7638 fragS
*fragP
= NULL
;
7643 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7645 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7646 if (insn_count
>= max_count
)
7649 if (count_relax_add
)
7651 if (fragP
->fr_type
== rs_machine_dependent
7652 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7654 /* In order to add the appropriate number of
7655 NOPs, we count an instruction for downstream
7658 if (insn_count
>= max_count
)
7668 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7670 xtensa_isa isa
= xtensa_default_isa
;
7671 static xtensa_insnbuf insnbuf
= NULL
;
7675 if (!fragP
->tc_frag_data
.is_insn
)
7679 insnbuf
= xtensa_insnbuf_alloc (isa
);
7681 /* Decode the fixed instructions. */
7682 while (offset
< fragP
->fr_fix
)
7686 xtensa_insnbuf_from_chars
7687 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7688 fmt
= xtensa_format_decode (isa
, insnbuf
);
7690 if (fmt
== XTENSA_UNDEFINED
)
7692 as_fatal (_("undecodable instruction in instruction frag"));
7695 offset
+= xtensa_format_length (isa
, fmt
);
7703 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7706 branch_before_loop_end (fragS
*base_fragP
)
7710 for (fragP
= base_fragP
;
7711 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7712 fragP
= fragP
->fr_next
)
7714 if (unrelaxed_frag_has_b_j (fragP
))
7722 unrelaxed_frag_has_b_j (fragS
*fragP
)
7724 static xtensa_insnbuf insnbuf
= NULL
;
7725 xtensa_isa isa
= xtensa_default_isa
;
7728 if (!fragP
->tc_frag_data
.is_insn
)
7732 insnbuf
= xtensa_insnbuf_alloc (isa
);
7734 /* Decode the fixed instructions. */
7735 while (offset
< fragP
->fr_fix
)
7740 xtensa_insnbuf_from_chars
7741 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7742 fmt
= xtensa_format_decode (isa
, insnbuf
);
7743 if (fmt
== XTENSA_UNDEFINED
)
7746 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7748 xtensa_opcode opcode
=
7749 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7750 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7751 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7754 offset
+= xtensa_format_length (isa
, fmt
);
7760 /* Checks to be made after initial assembly but before relaxation. */
7762 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7763 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7766 xtensa_sanity_check (void)
7773 as_where (&file_name
, &line
);
7774 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7775 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7779 /* Walk over all of the fragments in a subsection. */
7780 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7782 if (fragP
->fr_type
== rs_machine_dependent
7783 && fragP
->fr_subtype
== RELAX_SLOTS
7784 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7786 static xtensa_insnbuf insnbuf
= NULL
;
7789 if (fragP
->fr_opcode
!= NULL
)
7792 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7793 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7794 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7796 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7797 t_insn
.opcode
) == 1)
7799 if (is_empty_loop (&t_insn
, fragP
))
7801 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7802 as_bad (_("invalid empty loop"));
7804 if (!is_local_forward_loop (&t_insn
, fragP
))
7806 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7807 as_bad (_("loop target does not follow "
7808 "loop instruction in section"));
7815 new_logical_line (file_name
, line
);
7819 #define LOOP_IMMED_OPN 1
7821 /* Return TRUE if the loop target is the next non-zero fragment. */
7824 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7826 const expressionS
*expr
;
7830 if (insn
->insn_type
!= ITYPE_INSN
)
7833 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7836 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7839 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7841 if (expr
->X_op
!= O_symbol
)
7844 symbolP
= expr
->X_add_symbol
;
7848 if (symbol_get_frag (symbolP
) == NULL
)
7851 if (S_GET_VALUE (symbolP
) != 0)
7854 /* Walk through the zero-size fragments from this one. If we find
7855 the target fragment, then this is a zero-size loop. */
7857 for (next_fragP
= fragP
->fr_next
;
7859 next_fragP
= next_fragP
->fr_next
)
7861 if (next_fragP
== symbol_get_frag (symbolP
))
7863 if (next_fragP
->fr_fix
!= 0)
7871 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7873 const expressionS
*expr
;
7877 if (insn
->insn_type
!= ITYPE_INSN
)
7880 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7883 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7886 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7888 if (expr
->X_op
!= O_symbol
)
7891 symbolP
= expr
->X_add_symbol
;
7895 if (symbol_get_frag (symbolP
) == NULL
)
7898 /* Walk through fragments until we find the target.
7899 If we do not find the target, then this is an invalid loop. */
7901 for (next_fragP
= fragP
->fr_next
;
7903 next_fragP
= next_fragP
->fr_next
)
7905 if (next_fragP
== symbol_get_frag (symbolP
))
7913 #define XTINFO_NAME "Xtensa_Info"
7914 #define XTINFO_NAMESZ 12
7915 #define XTINFO_TYPE 1
7918 xtensa_add_config_info (void)
7924 info_sec
= subseg_new (".xtensa.info", 0);
7925 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7927 data
= xmalloc (100);
7928 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7929 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
7930 sz
= strlen (data
) + 1;
7932 /* Add enough null terminators to pad to a word boundary. */
7935 while ((sz
& 3) != 0);
7937 /* Follow the standard note section layout:
7938 First write the length of the name string. */
7940 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
7942 /* Next comes the length of the "descriptor", i.e., the actual data. */
7944 md_number_to_chars (p
, (valueT
) sz
, 4);
7946 /* Write the note type. */
7948 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
7950 /* Write the name field. */
7951 p
= frag_more (XTINFO_NAMESZ
);
7952 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
7954 /* Finally, write the descriptor. */
7956 memcpy (p
, data
, sz
);
7962 /* Alignment Functions. */
7965 get_text_align_power (unsigned target_size
)
7967 if (target_size
<= 4)
7969 assert (target_size
== 8);
7975 get_text_align_max_fill_size (int align_pow
,
7976 bfd_boolean use_nops
,
7977 bfd_boolean use_no_density
)
7980 return (1 << align_pow
);
7982 return 3 * (1 << align_pow
);
7984 return 1 + (1 << align_pow
);
7988 /* Calculate the minimum bytes of fill needed at "address" to align a
7989 target instruction of size "target_size" so that it does not cross a
7990 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7991 the fill can be an arbitrary number of bytes. Otherwise, the space must
7992 be filled by NOP instructions. */
7995 get_text_align_fill_size (addressT address
,
7998 bfd_boolean use_nops
,
7999 bfd_boolean use_no_density
)
8001 addressT alignment
, fill
, fill_limit
, fill_step
;
8002 bfd_boolean skip_one
= FALSE
;
8004 alignment
= (1 << align_pow
);
8005 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8009 fill_limit
= alignment
;
8012 else if (!use_no_density
)
8014 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8015 fill_limit
= alignment
* 2;
8021 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8022 fill_limit
= alignment
* 3;
8026 /* Try all fill sizes until finding one that works. */
8027 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8029 if (skip_one
&& fill
== 1)
8031 if ((address
+ fill
) >> align_pow
8032 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8041 branch_align_power (segT sec
)
8043 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8044 is aligned to at least an 8-byte boundary, then a branch target need
8045 only fit within an 8-byte aligned block of memory to avoid a stall.
8046 Otherwise, try to fit branch targets within 4-byte aligned blocks
8047 (which may be insufficient, e.g., if the section has no alignment, but
8048 it's good enough). */
8049 if (xtensa_fetch_width
== 8)
8051 if (get_recorded_alignment (sec
) >= 3)
8055 assert (xtensa_fetch_width
== 4);
8061 /* This will assert if it is not possible. */
8064 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8070 assert (fill_size
% 3 == 0);
8071 return (fill_size
/ 3);
8074 assert (fill_size
!= 1); /* Bad argument. */
8076 while (fill_size
> 1)
8079 if (fill_size
== 2 || fill_size
== 4)
8081 fill_size
-= insn_size
;
8084 assert (fill_size
!= 1); /* Bad algorithm. */
8090 get_text_align_nth_nop_size (offsetT fill_size
,
8092 bfd_boolean use_no_density
)
8099 assert (fill_size
!= 1); /* Bad argument. */
8101 while (fill_size
> 1)
8104 if (fill_size
== 2 || fill_size
== 4)
8106 fill_size
-= insn_size
;
8116 /* For the given fragment, find the appropriate address
8117 for it to begin at if we are using NOPs to align it. */
8120 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8122 /* The rule is: get next fragment's FIRST instruction. Find
8123 the smallest number of bytes that need to be added to
8124 ensure that the next fragment's FIRST instruction will fit
8127 E.G., 2 bytes : 0, 1, 2 mod 4
8130 If the FIRST instruction MIGHT be relaxed,
8131 assume that it will become a 3-byte instruction.
8133 Note again here that LOOP instructions are not bundleable,
8134 and this relaxation only applies to LOOP opcodes. */
8137 int first_insn_size
;
8139 addressT pre_opcode_bytes
;
8142 xtensa_opcode opcode
;
8143 bfd_boolean is_loop
;
8145 assert (fragP
->fr_type
== rs_machine_dependent
);
8146 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8148 /* Find the loop frag. */
8149 first_insn
= next_non_empty_frag (fragP
);
8150 /* Now find the first insn frag. */
8151 first_insn
= next_non_empty_frag (first_insn
);
8153 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8155 loop_insn_size
= xg_get_single_size (opcode
);
8157 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8158 pre_opcode_bytes
+= loop_insn_size
;
8160 /* For loops, the alignment depends on the size of the
8161 instruction following the loop, not the LOOP instruction. */
8163 if (first_insn
== NULL
)
8164 first_insn_size
= xtensa_fetch_width
;
8166 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8168 /* If it was 8, then we'll need a larger alignment for the section. */
8169 align_power
= get_text_align_power (first_insn_size
);
8170 record_alignment (now_seg
, align_power
);
8172 fill_size
= get_text_align_fill_size
8173 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8174 fragP
->tc_frag_data
.is_no_density
);
8176 return address
+ fill_size
;
8180 /* 3 mechanisms for relaxing an alignment:
8182 Align to a power of 2.
8183 Align so the next fragment's instruction does not cross a word boundary.
8184 Align the current instruction so that if the next instruction
8185 were 3 bytes, it would not cross a word boundary.
8189 zeros - This is easy; always insert zeros.
8190 nops - 3-byte and 2-byte instructions
8194 >=5 : 3-byte instruction + fn (n-3)
8195 widening - widen previous instructions. */
8198 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8200 addressT target_address
, loop_insn_offset
;
8202 xtensa_opcode loop_opcode
;
8203 bfd_boolean is_loop
;
8206 offsetT branch_align
;
8208 assert (fragP
->fr_type
== rs_machine_dependent
);
8209 switch (fragP
->fr_subtype
)
8211 case RELAX_DESIRE_ALIGN
:
8212 target_size
= next_frag_format_size (fragP
);
8213 if (target_size
== XTENSA_UNDEFINED
)
8215 align_power
= branch_align_power (now_seg
);
8216 branch_align
= 1 << align_power
;
8217 /* Don't count on the section alignment being as large as the target. */
8218 if (target_size
> branch_align
)
8219 target_size
= branch_align
;
8220 opt_diff
= get_text_align_fill_size (address
, align_power
,
8221 target_size
, FALSE
, FALSE
);
8223 *max_diff
= (opt_diff
+ branch_align
8224 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8225 assert (*max_diff
>= opt_diff
);
8228 case RELAX_ALIGN_NEXT_OPCODE
:
8229 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8230 loop_insn_offset
= 0;
8231 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8234 /* If the loop has been expanded then the LOOP instruction
8235 could be at an offset from this fragment. */
8236 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8238 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8240 /* In an ideal world, which is what we are shooting for here,
8241 we wouldn't need to use any NOPs immediately prior to the
8242 LOOP instruction. If this approach fails, relax_frag_loop_align
8243 will call get_noop_aligned_address. */
8245 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8246 align_power
= get_text_align_power (target_size
),
8247 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8248 target_size
, FALSE
, FALSE
);
8250 *max_diff
= xtensa_fetch_width
8251 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8252 - target_size
+ opt_diff
;
8253 assert (*max_diff
>= opt_diff
);
8264 /* md_relax_frag Hook and Helper Functions. */
8266 static long relax_frag_loop_align (fragS
*, long);
8267 static long relax_frag_for_align (fragS
*, long);
8268 static long relax_frag_immed
8269 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8272 /* Return the number of bytes added to this fragment, given that the
8273 input has been stretched already by "stretch". */
8276 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8278 xtensa_isa isa
= xtensa_default_isa
;
8279 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8280 long new_stretch
= 0;
8284 static xtensa_insnbuf vbuf
= NULL
;
8285 int slot
, num_slots
;
8288 as_where (&file_name
, &line
);
8289 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8291 fragP
->tc_frag_data
.unreported_expansion
= 0;
8293 switch (fragP
->fr_subtype
)
8295 case RELAX_ALIGN_NEXT_OPCODE
:
8296 /* Always convert. */
8297 if (fragP
->tc_frag_data
.relax_seen
)
8298 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8301 case RELAX_LOOP_END
:
8305 case RELAX_LOOP_END_ADD_NOP
:
8306 /* Add a NOP and switch to .fill 0. */
8307 new_stretch
= relax_frag_add_nop (fragP
);
8311 case RELAX_DESIRE_ALIGN
:
8312 /* Do nothing. The narrowing before this frag will either align
8317 case RELAX_LITERAL_FINAL
:
8320 case RELAX_LITERAL_NR
:
8322 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8323 assert (unreported
== lit_size
);
8324 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8325 fragP
->fr_var
-= lit_size
;
8326 fragP
->fr_fix
+= lit_size
;
8332 vbuf
= xtensa_insnbuf_alloc (isa
);
8334 xtensa_insnbuf_from_chars
8335 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8336 fmt
= xtensa_format_decode (isa
, vbuf
);
8337 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8339 for (slot
= 0; slot
< num_slots
; slot
++)
8341 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8344 if (fragP
->tc_frag_data
.relax_seen
)
8345 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8349 case RELAX_IMMED_STEP1
:
8350 case RELAX_IMMED_STEP2
:
8351 case RELAX_IMMED_STEP3
:
8352 /* Place the immediate. */
8353 new_stretch
+= relax_frag_immed
8354 (now_seg
, fragP
, stretch
,
8355 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8356 fmt
, slot
, stretched_p
, FALSE
);
8360 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8366 case RELAX_LITERAL_POOL_BEGIN
:
8367 case RELAX_LITERAL_POOL_END
:
8368 case RELAX_MAYBE_UNREACHABLE
:
8369 case RELAX_MAYBE_DESIRE_ALIGN
:
8370 /* No relaxation required. */
8373 case RELAX_FILL_NOP
:
8374 case RELAX_UNREACHABLE
:
8375 if (fragP
->tc_frag_data
.relax_seen
)
8376 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8380 as_bad (_("bad relaxation state"));
8383 /* Tell gas we need another relaxation pass. */
8384 if (! fragP
->tc_frag_data
.relax_seen
)
8386 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8390 new_logical_line (file_name
, line
);
8396 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8398 addressT old_address
, old_next_address
, old_size
;
8399 addressT new_address
, new_next_address
, new_size
;
8402 /* All the frags with relax_frag_for_alignment prior to this one in the
8403 section have been done, hopefully eliminating the need for a NOP here.
8404 But, this will put it in if necessary. */
8406 /* Calculate the old address of this fragment and the next fragment. */
8407 old_address
= fragP
->fr_address
- stretch
;
8408 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8409 fragP
->tc_frag_data
.text_expansion
[0]);
8410 old_size
= old_next_address
- old_address
;
8412 /* Calculate the new address of this fragment and the next fragment. */
8413 new_address
= fragP
->fr_address
;
8415 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8416 new_size
= new_next_address
- new_address
;
8418 growth
= new_size
- old_size
;
8420 /* Fix up the text_expansion field and return the new growth. */
8421 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8426 /* Add a NOP instruction. */
8429 relax_frag_add_nop (fragS
*fragP
)
8431 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8432 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8433 assemble_nop (length
, nop_buf
);
8434 fragP
->tc_frag_data
.is_insn
= TRUE
;
8436 if (fragP
->fr_var
< length
)
8438 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8442 fragP
->fr_fix
+= length
;
8443 fragP
->fr_var
-= length
;
8448 static long future_alignment_required (fragS
*, long);
8451 relax_frag_for_align (fragS
*fragP
, long stretch
)
8453 /* Overview of the relaxation procedure for alignment:
8454 We can widen with NOPs or by widening instructions or by filling
8455 bytes after jump instructions. Find the opportune places and widen
8456 them if necessary. */
8461 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8462 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8463 || (fragP
->fr_subtype
== RELAX_SLOTS
8464 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8466 stretch_me
= future_alignment_required (fragP
, stretch
);
8467 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8473 /* We expanded on a previous pass. Can we shrink now? */
8474 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8475 if (shrink
<= stretch
&& stretch
> 0)
8477 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8483 /* Below here, diff > 0. */
8484 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8490 /* Return the address of the next frag that should be aligned.
8492 By "address" we mean the address it _would_ be at if there
8493 is no action taken to align it between here and the target frag.
8494 In other words, if no narrows and no fill nops are used between
8495 here and the frag to align, _even_if_ some of the frags we use
8496 to align targets have already expanded on a previous relaxation
8499 Also, count each frag that may be used to help align the target.
8501 Return 0 if there are no frags left in the chain that need to be
8505 find_address_of_next_align_frag (fragS
**fragPP
,
8509 bfd_boolean
*paddable
)
8511 fragS
*fragP
= *fragPP
;
8512 addressT address
= fragP
->fr_address
;
8514 /* Do not reset the counts to 0. */
8518 /* Limit this to a small search. */
8519 if (*widens
>= (int) xtensa_fetch_width
)
8524 address
+= fragP
->fr_fix
;
8526 if (fragP
->fr_type
== rs_fill
)
8527 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8528 else if (fragP
->fr_type
== rs_machine_dependent
)
8530 switch (fragP
->fr_subtype
)
8532 case RELAX_UNREACHABLE
:
8536 case RELAX_FILL_NOP
:
8538 if (!fragP
->tc_frag_data
.is_no_density
)
8543 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8548 address
+= total_frag_text_expansion (fragP
);;
8552 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8555 case RELAX_ALIGN_NEXT_OPCODE
:
8556 case RELAX_DESIRE_ALIGN
:
8560 case RELAX_MAYBE_UNREACHABLE
:
8561 case RELAX_MAYBE_DESIRE_ALIGN
:
8566 /* Just punt if we don't know the type. */
8573 /* Just punt if we don't know the type. */
8577 fragP
= fragP
->fr_next
;
8585 static long bytes_to_stretch (fragS
*, int, int, int, int);
8588 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8590 fragS
*this_frag
= fragP
;
8594 int narrow_nops
= 0;
8595 bfd_boolean paddable
= FALSE
;
8596 offsetT local_opt_diff
;
8599 int stretch_amount
= 0;
8600 int local_stretch_amount
;
8601 int global_stretch_amount
;
8603 address
= find_address_of_next_align_frag
8604 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8608 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8609 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8611 frag_wane (this_frag
);
8615 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8616 opt_diff
= local_opt_diff
;
8617 assert (opt_diff
>= 0);
8618 assert (max_diff
>= opt_diff
);
8623 fragP
= fragP
->fr_next
;
8625 while (fragP
&& opt_diff
< max_diff
&& address
)
8627 /* We only use these to determine if we can exit early
8628 because there will be plenty of ways to align future
8630 int glob_widens
= 0;
8633 bfd_boolean glob_pad
= 0;
8634 address
= find_address_of_next_align_frag
8635 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8636 /* If there is a padable portion, then skip. */
8637 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8642 offsetT next_m_diff
;
8643 offsetT next_o_diff
;
8645 /* Downrange frags haven't had stretch added to them yet. */
8648 /* The address also includes any text expansion from this
8649 frag in a previous pass, but we don't want that. */
8650 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8652 /* Assume we are going to move at least opt_diff. In
8653 reality, we might not be able to, but assuming that
8654 we will helps catch cases where moving opt_diff pushes
8655 the next target from aligned to unaligned. */
8656 address
+= opt_diff
;
8658 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8660 /* Now cleanup for the adjustments to address. */
8661 next_o_diff
+= opt_diff
;
8662 next_m_diff
+= opt_diff
;
8663 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8664 opt_diff
= next_o_diff
;
8665 if (next_m_diff
< max_diff
)
8666 max_diff
= next_m_diff
;
8667 fragP
= fragP
->fr_next
;
8671 /* If there are enough wideners in between, do it. */
8674 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8676 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8681 local_stretch_amount
8682 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8683 num_widens
, local_opt_diff
);
8684 global_stretch_amount
8685 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8686 num_widens
, opt_diff
);
8687 /* If the condition below is true, then the frag couldn't
8688 stretch the correct amount for the global case, so we just
8689 optimize locally. We'll rely on the subsequent frags to get
8690 the correct alignment in the global case. */
8691 if (global_stretch_amount
< local_stretch_amount
)
8692 stretch_amount
= local_stretch_amount
;
8694 stretch_amount
= global_stretch_amount
;
8696 if (this_frag
->fr_subtype
== RELAX_SLOTS
8697 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8698 assert (stretch_amount
<= 1);
8699 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8701 if (this_frag
->tc_frag_data
.is_no_density
)
8702 assert (stretch_amount
== 3 || stretch_amount
== 0);
8704 assert (stretch_amount
<= 3);
8707 return stretch_amount
;
8711 /* The idea: widen everything you can to get a target or loop aligned,
8712 then start using NOPs.
8714 When we must have a NOP, here is a table of how we decide
8715 (so you don't have to fight through the control flow below):
8717 wide_nops = the number of wide NOPs available for aligning
8718 narrow_nops = the number of narrow NOPs available for aligning
8719 (a subset of wide_nops)
8720 widens = the number of narrow instructions that should be widened
8727 b 0 1 1 (case 3a makes this case unnecessary)
8730 c 0 1 2 (case 4a makes this case unnecessary)
8733 c 0 2 1 (case 5b makes this case unnecessary)
8736 c 0 1 4 (case 6b makes this case unnecessary)
8737 d 1 1 1 (case 6a makes this case unnecessary)
8738 e 0 2 2 (case 6a makes this case unnecessary)
8739 f 0 3 0 (case 6a makes this case unnecessary)
8742 c 1 1 2 (case 7b makes this case unnecessary)
8743 d 0 1 5 (case 7a makes this case unnecessary)
8744 e 0 2 3 (case 7b makes this case unnecessary)
8745 f 0 3 1 (case 7b makes this case unnecessary)
8746 g 1 2 1 (case 7b makes this case unnecessary)
8750 bytes_to_stretch (fragS
*this_frag
,
8756 int bytes_short
= desired_diff
- num_widens
;
8758 assert (desired_diff
>= 0 && desired_diff
< 8);
8759 if (desired_diff
== 0)
8762 assert (wide_nops
> 0 || num_widens
> 0);
8764 /* Always prefer widening to NOP-filling. */
8765 if (bytes_short
< 0)
8767 /* There are enough RELAX_NARROW frags after this one
8768 to align the target without widening this frag in any way. */
8772 if (bytes_short
== 0)
8774 /* Widen every narrow between here and the align target
8775 and the align target will be properly aligned. */
8776 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8782 /* From here we will need at least one NOP to get an alignment.
8783 However, we may not be able to align at all, in which case,
8785 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8787 switch (desired_diff
)
8792 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8793 return 2; /* case 2 */
8799 return 3; /* case 3a */
8801 if (num_widens
>= 1 && wide_nops
== 1)
8802 return 3; /* case 4a */
8803 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8804 return 2; /* case 4b */
8807 if (num_widens
>= 2 && wide_nops
== 1)
8808 return 3; /* case 5a */
8809 /* We will need two nops. Are there enough nops
8810 between here and the align target? */
8811 if (wide_nops
< 2 || narrow_nops
== 0)
8813 /* Are there other nops closer that can serve instead? */
8814 if (wide_nops
> 2 && narrow_nops
> 1)
8816 /* Take the density one first, because there might not be
8817 another density one available. */
8818 if (!this_frag
->tc_frag_data
.is_no_density
)
8819 return 2; /* case 5b narrow */
8821 return 3; /* case 5b wide */
8825 return 3; /* case 6a */
8826 else if (num_widens
>= 3 && wide_nops
== 1)
8827 return 3; /* case 6b */
8830 if (wide_nops
== 1 && num_widens
>= 4)
8831 return 3; /* case 7a */
8832 else if (wide_nops
== 2 && num_widens
>= 1)
8833 return 3; /* case 7b */
8841 /* We will need a NOP no matter what, but should we widen
8842 this instruction to help?
8844 This is a RELAX_NARROW frag. */
8845 switch (desired_diff
)
8854 if (wide_nops
>= 1 && num_widens
== 1)
8855 return 1; /* case 4a */
8858 if (wide_nops
>= 1 && num_widens
== 2)
8859 return 1; /* case 5a */
8863 return 0; /* case 6a */
8864 else if (wide_nops
>= 1 && num_widens
== 3)
8865 return 1; /* case 6b */
8868 if (wide_nops
>= 1 && num_widens
== 4)
8869 return 1; /* case 7a */
8870 else if (wide_nops
>= 2 && num_widens
== 1)
8871 return 1; /* case 7b */
8884 relax_frag_immed (segT segP
,
8891 bfd_boolean estimate_only
)
8895 bfd_boolean negatable_branch
= FALSE
;
8896 bfd_boolean branch_jmp_to_next
= FALSE
;
8897 bfd_boolean wide_insn
= FALSE
;
8898 xtensa_isa isa
= xtensa_default_isa
;
8900 offsetT frag_offset
;
8903 int num_text_bytes
, num_literal_bytes
;
8904 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8906 assert (fragP
->fr_opcode
!= NULL
);
8908 xg_clear_vinsn (&cur_vinsn
);
8909 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8910 if (cur_vinsn
.num_slots
> 1)
8913 tinsn
= cur_vinsn
.slots
[slot
];
8914 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8916 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8919 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8920 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8922 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8924 old_size
= xtensa_format_length (isa
, fmt
);
8926 /* Special case: replace a branch to the next instruction with a NOP.
8927 This is required to work around a hardware bug in T1040.0 and also
8928 serves as an optimization. */
8930 if (branch_jmp_to_next
8931 && ((old_size
== 2) || (old_size
== 3))
8932 && !next_frag_is_loop_target (fragP
))
8935 /* Here is the fun stuff: Get the immediate field from this
8936 instruction. If it fits, we are done. If not, find the next
8937 instruction sequence that fits. */
8939 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8940 istack_init (&istack
);
8941 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8942 min_steps
, stretch
);
8943 if (num_steps
< min_steps
)
8945 as_fatal (_("internal error: relaxation failed"));
8949 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8951 as_fatal (_("internal error: relaxation requires too many steps"));
8955 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8957 /* Figure out the number of bytes needed. */
8959 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8961 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8963 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8965 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8968 num_text_bytes
+= old_size
;
8969 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8970 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8972 total_text_diff
= num_text_bytes
- old_size
;
8973 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8975 /* It MUST get larger. If not, we could get an infinite loop. */
8976 assert (num_text_bytes
>= 0);
8977 assert (literal_diff
>= 0);
8978 assert (total_text_diff
>= 0);
8980 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8981 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8982 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8983 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8985 /* Find the associated expandable literal for this. */
8986 if (literal_diff
!= 0)
8988 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8991 assert (literal_diff
== 4);
8992 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8994 /* We expect that the literal section state has NOT been
8996 assert (lit_fragP
->fr_type
== rs_machine_dependent
8997 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8998 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9000 /* We need to mark this section for another iteration
9006 if (negatable_branch
&& istack
.ninsn
> 1)
9007 update_next_frag_state (fragP
);
9009 return this_text_diff
;
9013 /* md_convert_frag Hook and Helper Functions. */
9015 static void convert_frag_align_next_opcode (fragS
*);
9016 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9017 static void convert_frag_fill_nop (fragS
*);
9018 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9021 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9023 static xtensa_insnbuf vbuf
= NULL
;
9024 xtensa_isa isa
= xtensa_default_isa
;
9031 as_where (&file_name
, &line
);
9032 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9034 switch (fragp
->fr_subtype
)
9036 case RELAX_ALIGN_NEXT_OPCODE
:
9037 /* Always convert. */
9038 convert_frag_align_next_opcode (fragp
);
9041 case RELAX_DESIRE_ALIGN
:
9042 /* Do nothing. If not aligned already, too bad. */
9046 case RELAX_LITERAL_FINAL
:
9051 vbuf
= xtensa_insnbuf_alloc (isa
);
9053 xtensa_insnbuf_from_chars
9054 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9055 fmt
= xtensa_format_decode (isa
, vbuf
);
9056 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9058 for (slot
= 0; slot
< num_slots
; slot
++)
9060 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9063 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9067 case RELAX_IMMED_STEP1
:
9068 case RELAX_IMMED_STEP2
:
9069 case RELAX_IMMED_STEP3
:
9070 /* Place the immediate. */
9073 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9078 /* This is OK because some slots could have
9079 relaxations and others have none. */
9085 case RELAX_UNREACHABLE
:
9086 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9087 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9088 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9092 case RELAX_MAYBE_UNREACHABLE
:
9093 case RELAX_MAYBE_DESIRE_ALIGN
:
9097 case RELAX_FILL_NOP
:
9098 convert_frag_fill_nop (fragp
);
9101 case RELAX_LITERAL_NR
:
9102 if (use_literal_section
)
9104 /* This should have been handled during relaxation. When
9105 relaxing a code segment, literals sometimes need to be
9106 added to the corresponding literal segment. If that
9107 literal segment has already been relaxed, then we end up
9108 in this situation. Marking the literal segments as data
9109 would make this happen less often (since GAS always relaxes
9110 code before data), but we could still get into trouble if
9111 there are instructions in a segment that is not marked as
9112 containing code. Until we can implement a better solution,
9113 cheat and adjust the addresses of all the following frags.
9114 This could break subsequent alignments, but the linker's
9115 literal coalescing will do that anyway. */
9118 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9119 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9120 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9123 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9127 as_bad (_("invalid relaxation fragment result"));
9132 new_logical_line (file_name
, line
);
9137 convert_frag_align_next_opcode (fragS
*fragp
)
9139 char *nop_buf
; /* Location for Writing. */
9140 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9141 addressT aligned_address
;
9145 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9147 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9148 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9149 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9151 for (nop
= 0; nop
< nop_count
; nop
++)
9154 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9156 assemble_nop (nop_size
, nop_buf
);
9157 nop_buf
+= nop_size
;
9160 fragp
->fr_fix
+= fill_size
;
9161 fragp
->fr_var
-= fill_size
;
9166 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9168 TInsn tinsn
, single_target
;
9169 int size
, old_size
, diff
;
9170 offsetT frag_offset
;
9173 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9175 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9177 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9178 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9179 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9184 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9186 /* No conversion. */
9191 assert (fragP
->fr_opcode
!= NULL
);
9193 /* Frags in this relaxation state should only contain
9194 single instruction bundles. */
9195 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9197 /* Just convert it to a wide form.... */
9199 old_size
= xg_get_single_size (tinsn
.opcode
);
9201 tinsn_init (&single_target
);
9202 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9204 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9206 as_bad (_("unable to widen instruction"));
9210 size
= xg_get_single_size (single_target
.opcode
);
9211 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9214 diff
= size
- old_size
;
9216 assert (diff
<= fragP
->fr_var
);
9217 fragP
->fr_var
-= diff
;
9218 fragP
->fr_fix
+= diff
;
9226 convert_frag_fill_nop (fragS
*fragP
)
9228 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9229 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9230 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9231 - fragP
->fr_address
- fragP
->fr_fix
));
9234 /* No conversion. */
9238 assemble_nop (size
, loc
);
9239 fragP
->tc_frag_data
.is_insn
= TRUE
;
9240 fragP
->fr_var
-= size
;
9241 fragP
->fr_fix
+= size
;
9246 static fixS
*fix_new_exp_in_seg
9247 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9248 bfd_reloc_code_real_type
);
9249 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9252 convert_frag_immed (segT segP
,
9258 char *immed_instr
= fragP
->fr_opcode
;
9260 bfd_boolean expanded
= FALSE
;
9261 bfd_boolean branch_jmp_to_next
= FALSE
;
9262 char *fr_opcode
= fragP
->fr_opcode
;
9263 xtensa_isa isa
= xtensa_default_isa
;
9264 bfd_boolean wide_insn
= FALSE
;
9266 bfd_boolean is_loop
;
9268 assert (fr_opcode
!= NULL
);
9270 xg_clear_vinsn (&cur_vinsn
);
9272 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9273 if (cur_vinsn
.num_slots
> 1)
9276 orig_tinsn
= cur_vinsn
.slots
[slot
];
9277 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9279 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9281 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9282 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9284 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9286 /* Conversion just inserts a NOP and marks the fix as completed. */
9287 bytes
= xtensa_format_length (isa
, fmt
);
9290 cur_vinsn
.slots
[slot
].opcode
=
9291 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9292 cur_vinsn
.slots
[slot
].ntok
= 0;
9296 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9297 assert (bytes
== 2 || bytes
== 3);
9298 build_nop (&cur_vinsn
.slots
[0], bytes
);
9299 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9301 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9302 xtensa_insnbuf_to_chars
9303 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9308 /* Here is the fun stuff: Get the immediate field from this
9309 instruction. If it fits, we're done. If not, find the next
9310 instruction sequence that fits. */
9314 symbolS
*lit_sym
= NULL
;
9316 int target_offset
= 0;
9319 symbolS
*gen_label
= NULL
;
9320 offsetT frag_offset
;
9321 bfd_boolean first
= TRUE
;
9322 bfd_boolean last_is_jump
;
9324 /* It does not fit. Find something that does and
9325 convert immediately. */
9326 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9327 istack_init (&istack
);
9328 xg_assembly_relax (&istack
, &orig_tinsn
,
9329 segP
, fragP
, frag_offset
, min_steps
, 0);
9331 old_size
= xtensa_format_length (isa
, fmt
);
9333 /* Assemble this right inline. */
9335 /* First, create the mapping from a label name to the REAL label. */
9337 for (i
= 0; i
< istack
.ninsn
; i
++)
9339 TInsn
*tinsn
= &istack
.insn
[i
];
9342 switch (tinsn
->insn_type
)
9345 if (lit_sym
!= NULL
)
9346 as_bad (_("multiple literals in expansion"));
9347 /* First find the appropriate space in the literal pool. */
9348 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9349 if (lit_frag
== NULL
)
9350 as_bad (_("no registered fragment for literal"));
9351 if (tinsn
->ntok
!= 1)
9352 as_bad (_("number of literal tokens != 1"));
9354 /* Set the literal symbol and add a fixup. */
9355 lit_sym
= lit_frag
->fr_symbol
;
9359 if (align_targets
&& !is_loop
)
9361 fragS
*unreach
= fragP
->fr_next
;
9362 while (!(unreach
->fr_type
== rs_machine_dependent
9363 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9364 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9366 unreach
= unreach
->fr_next
;
9369 assert (unreach
->fr_type
== rs_machine_dependent
9370 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9371 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9373 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9375 assert (gen_label
== NULL
);
9376 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9377 fr_opcode
- fragP
->fr_literal
9378 + target_offset
, fragP
);
9382 if (first
&& wide_insn
)
9384 target_offset
+= xtensa_format_length (isa
, fmt
);
9386 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9387 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9390 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9397 last_is_jump
= FALSE
;
9398 for (i
= 0; i
< istack
.ninsn
; i
++)
9400 TInsn
*tinsn
= &istack
.insn
[i
];
9404 bfd_reloc_code_real_type reloc_type
;
9406 switch (tinsn
->insn_type
)
9409 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9410 /* Already checked. */
9411 assert (lit_frag
!= NULL
);
9412 assert (lit_sym
!= NULL
);
9413 assert (tinsn
->ntok
== 1);
9415 target_seg
= S_GET_SEGMENT (lit_sym
);
9416 assert (target_seg
);
9417 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9418 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9419 &tinsn
->tok
[0], FALSE
, reloc_type
);
9426 xg_resolve_labels (tinsn
, gen_label
);
9427 xg_resolve_literals (tinsn
, lit_sym
);
9428 if (wide_insn
&& first
)
9431 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9433 cur_vinsn
.slots
[slot
] = *tinsn
;
9437 cur_vinsn
.slots
[slot
].opcode
=
9438 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9439 cur_vinsn
.slots
[slot
].ntok
= 0;
9441 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9442 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9443 (unsigned char *) immed_instr
, 0);
9444 fragP
->tc_frag_data
.is_insn
= TRUE
;
9445 size
= xtensa_format_length (isa
, fmt
);
9446 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9449 (tinsn
, immed_instr
+ size
, fragP
,
9450 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9451 size
+= xg_get_single_size (tinsn
->opcode
);
9456 size
= xg_get_single_size (tinsn
->opcode
);
9457 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9458 immed_instr
- fragP
->fr_literal
, TRUE
);
9460 immed_instr
+= size
;
9466 diff
= total_size
- old_size
;
9470 assert (diff
<= fragP
->fr_var
);
9471 fragP
->fr_var
-= diff
;
9472 fragP
->fr_fix
+= diff
;
9475 /* Check for undefined immediates in LOOP instructions. */
9479 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9480 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9482 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9485 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9486 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9488 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9493 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9494 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9496 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9498 /* Add an expansion note on the expanded instruction. */
9499 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9500 &orig_tinsn
.tok
[0], TRUE
,
9501 BFD_RELOC_XTENSA_ASM_EXPAND
);
9506 /* Add a new fix expression into the desired segment. We have to
9507 switch to that segment to do this. */
9510 fix_new_exp_in_seg (segT new_seg
,
9517 bfd_reloc_code_real_type r_type
)
9521 subsegT subseg
= now_subseg
;
9523 assert (new_seg
!= 0);
9524 subseg_set (new_seg
, new_subseg
);
9526 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9527 subseg_set (seg
, subseg
);
9532 /* Relax a loop instruction so that it can span loop >256 bytes.
9538 addi as, as, lo8 (label-.L1)
9539 addmi as, as, mid8 (label-.L1)
9550 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9555 unsigned long target
;
9556 static xtensa_insnbuf insnbuf
= NULL
;
9557 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9558 xtensa_isa isa
= xtensa_default_isa
;
9559 addressT loop_offset
;
9560 addressT addi_offset
= 9;
9561 addressT addmi_offset
= 12;
9566 insnbuf
= xtensa_insnbuf_alloc (isa
);
9568 /* Get the loop offset. */
9569 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9571 /* Validate that there really is a LOOP at the loop_offset. Because
9572 loops are not bundleable, we can assume that the instruction will be
9574 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9575 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9577 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9578 addi_offset
+= loop_offset
;
9579 addmi_offset
+= loop_offset
;
9581 assert (tinsn
->ntok
== 2);
9582 if (tinsn
->tok
[1].X_op
== O_constant
)
9583 target
= tinsn
->tok
[1].X_add_number
;
9584 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9586 /* Find the fragment. */
9587 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9588 assert (S_GET_SEGMENT (sym
) == segP
9589 || S_GET_SEGMENT (sym
) == absolute_section
);
9590 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9594 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9598 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9599 loop_length_hi
= loop_length
& ~0x0ff;
9600 loop_length_lo
= loop_length
& 0x0ff;
9601 if (loop_length_lo
>= 128)
9603 loop_length_lo
-= 256;
9604 loop_length_hi
+= 256;
9607 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9608 32512. If the loop is larger than that, then we just fail. */
9609 if (loop_length_hi
> 32512)
9610 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9611 _("loop too long for LOOP instruction"));
9613 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9614 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9616 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9617 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9619 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9620 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9622 fragP
->tc_frag_data
.is_insn
= TRUE
;
9623 xtensa_insnbuf_to_chars
9624 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9626 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9627 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9628 xtensa_insnbuf_to_chars
9629 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9631 /* Walk through all of the frags from here to the loop end
9632 and mark them as no_transform to keep them from being modified
9633 by the linker. If we ever have a relocation for the
9634 addi/addmi of the difference of two symbols we can remove this. */
9637 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9638 next_fragP
= next_fragP
->fr_next
)
9640 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9641 if (next_fragP
->tc_frag_data
.is_loop_target
)
9643 if (target_count
== 2)
9649 /* A map that keeps information on a per-subsegment basis. This is
9650 maintained during initial assembly, but is invalid once the
9651 subsegments are smashed together. I.E., it cannot be used during
9654 typedef struct subseg_map_struct
9662 float total_freq
; /* fall-through + branch target frequency */
9663 float target_freq
; /* branch target frequency alone */
9665 struct subseg_map_struct
*next
;
9669 static subseg_map
*sseg_map
= NULL
;
9672 get_subseg_info (segT seg
, subsegT subseg
)
9674 subseg_map
*subseg_e
;
9676 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9678 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9686 add_subseg_info (segT seg
, subsegT subseg
)
9688 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9689 memset (subseg_e
, 0, sizeof (subseg_map
));
9690 subseg_e
->seg
= seg
;
9691 subseg_e
->subseg
= subseg
;
9692 subseg_e
->flags
= 0;
9693 /* Start off considering every branch target very important. */
9694 subseg_e
->target_freq
= 1.0;
9695 subseg_e
->total_freq
= 1.0;
9696 subseg_e
->next
= sseg_map
;
9697 sseg_map
= subseg_e
;
9703 get_last_insn_flags (segT seg
, subsegT subseg
)
9705 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9707 return subseg_e
->flags
;
9713 set_last_insn_flags (segT seg
,
9718 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9720 subseg_e
= add_subseg_info (seg
, subseg
);
9722 subseg_e
->flags
|= fl
;
9724 subseg_e
->flags
&= ~fl
;
9729 get_subseg_total_freq (segT seg
, subsegT subseg
)
9731 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9733 return subseg_e
->total_freq
;
9739 get_subseg_target_freq (segT seg
, subsegT subseg
)
9741 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9743 return subseg_e
->target_freq
;
9749 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9751 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9753 subseg_e
= add_subseg_info (seg
, subseg
);
9754 subseg_e
->total_freq
= total_f
;
9755 subseg_e
->target_freq
= target_f
;
9759 /* Segment Lists and emit_state Stuff. */
9762 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9767 segT literal_section
= head
->seg
;
9769 /* Move the literal section to the front of the section list. */
9770 assert (literal_section
);
9771 if (literal_section
!= stdoutput
->sections
)
9773 bfd_section_list_remove (stdoutput
, literal_section
);
9774 bfd_section_list_prepend (stdoutput
, literal_section
);
9781 static void mark_literal_frags (seg_list
*);
9784 xtensa_move_literals (void)
9787 frchainS
*frchain_from
, *frchain_to
;
9788 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9789 fragS
**frag_splice
;
9792 fixS
*fix
, *next_fix
, **fix_splice
;
9795 mark_literal_frags (literal_head
->next
);
9797 if (use_literal_section
)
9800 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9802 /* Keep the literals for .init and .fini in separate sections. */
9803 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9804 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9807 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9808 search_frag
= frchain_from
->frch_root
;
9809 literal_pool
= NULL
;
9811 frag_splice
= &(frchain_from
->frch_root
);
9813 while (!search_frag
->tc_frag_data
.literal_frag
)
9815 assert (search_frag
->fr_fix
== 0
9816 || search_frag
->fr_type
== rs_align
);
9817 search_frag
= search_frag
->fr_next
;
9820 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9821 == RELAX_LITERAL_POOL_BEGIN
);
9822 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9824 /* Make sure that all the frags in this series are closed, and
9825 that there is at least one left over of zero-size. This
9826 prevents us from making a segment with an frchain without any
9828 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9829 xtensa_set_frag_assembly_state (frag_now
);
9830 last_frag
= frag_now
;
9831 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9832 xtensa_set_frag_assembly_state (frag_now
);
9834 while (search_frag
!= frag_now
)
9836 next_frag
= search_frag
->fr_next
;
9838 /* First, move the frag out of the literal section and
9839 to the appropriate place. */
9840 if (search_frag
->tc_frag_data
.literal_frag
)
9842 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9843 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9844 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9845 assert (frchain_to
);
9847 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
9848 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9850 *frag_splice
= next_frag
;
9851 search_frag
->fr_next
= insert_after
->fr_next
;
9852 insert_after
->fr_next
= search_frag
;
9853 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9854 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
9856 /* Now move any fixups associated with this frag to the
9858 fix
= frchain_from
->fix_root
;
9859 fix_splice
= &(frchain_from
->fix_root
);
9862 next_fix
= fix
->fx_next
;
9863 if (fix
->fx_frag
== search_frag
)
9865 *fix_splice
= next_fix
;
9866 fix
->fx_next
= frchain_to
->fix_root
;
9867 frchain_to
->fix_root
= fix
;
9868 if (frchain_to
->fix_tail
== NULL
)
9869 frchain_to
->fix_tail
= fix
;
9872 fix_splice
= &(fix
->fx_next
);
9875 search_frag
= next_frag
;
9878 if (frchain_from
->fix_root
!= NULL
)
9880 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9881 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9883 assert (frchain_from
->fix_root
== NULL
);
9885 frchain_from
->fix_tail
= NULL
;
9886 xtensa_restore_emit_state (&state
);
9889 /* Now fix up the SEGMENT value for all the literal symbols. */
9890 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9892 symbolS
*lit_sym
= lit
->sym
;
9893 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9895 S_SET_SEGMENT (lit_sym
, dest_seg
);
9900 /* Walk over all the frags for segments in a list and mark them as
9901 containing literals. As clunky as this is, we can't rely on frag_var
9902 and frag_variant to get called in all situations. */
9905 mark_literal_frags (seg_list
*segment
)
9907 frchainS
*frchain_from
;
9912 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9913 search_frag
= frchain_from
->frch_root
;
9916 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9917 search_frag
= search_frag
->fr_next
;
9919 segment
= segment
->next
;
9925 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9927 /* Move all of the sections in the section list to come
9928 after "after" in the gnu segment list. */
9933 segT literal_section
= head
->seg
;
9935 /* Move the literal section after "after". */
9936 assert (literal_section
);
9937 if (literal_section
!= after
)
9939 bfd_section_list_remove (stdoutput
, literal_section
);
9940 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9948 /* Push all the literal segments to the end of the gnu list. */
9951 xtensa_reorder_segments (void)
9958 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9964 /* Now that we have the last section, push all the literal
9965 sections to the end. */
9966 xtensa_reorder_seg_list (literal_head
, last_sec
);
9968 /* Now perform the final error check. */
9969 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9971 assert (new_count
== old_count
);
9975 /* Change the emit state (seg, subseg, and frag related stuff) to the
9976 correct location. Return a emit_state which can be passed to
9977 xtensa_restore_emit_state to return to current fragment. */
9980 xtensa_switch_to_literal_fragment (emit_state
*result
)
9982 if (directive_state
[directive_absolute_literals
])
9984 segT lit4_seg
= cache_literal_section (TRUE
);
9985 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
9988 xtensa_switch_to_non_abs_literal_fragment (result
);
9990 /* Do a 4-byte align here. */
9991 frag_align (2, 0, 0);
9992 record_alignment (now_seg
, 2);
9997 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9999 static bfd_boolean recursive
= FALSE
;
10000 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10002 bfd_boolean is_init
=
10003 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10004 bfd_boolean is_fini
=
10005 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10007 if (pool_location
== NULL
10008 && !use_literal_section
10010 && !is_init
&& ! is_fini
)
10012 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10014 /* When we mark a literal pool location, we want to put a frag in
10015 the literal pool that points to it. But to do that, we want to
10016 switch_to_literal_fragment. But literal sections don't have
10017 literal pools, so their location is always null, so we would
10018 recurse forever. This is kind of hacky, but it works. */
10021 xtensa_mark_literal_pool_location ();
10025 lit_seg
= cache_literal_section (FALSE
);
10026 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10028 if (!use_literal_section
10029 && !is_init
&& !is_fini
10030 && get_literal_pool_location (now_seg
) != pool_location
)
10032 /* Close whatever frag is there. */
10033 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10034 xtensa_set_frag_assembly_state (frag_now
);
10035 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10036 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10037 xtensa_set_frag_assembly_state (frag_now
);
10042 /* Call this function before emitting data into the literal section.
10043 This is a helper function for xtensa_switch_to_literal_fragment.
10044 This is similar to a .section new_now_seg subseg. */
10047 xtensa_switch_section_emit_state (emit_state
*state
,
10049 subsegT new_now_subseg
)
10051 state
->name
= now_seg
->name
;
10052 state
->now_seg
= now_seg
;
10053 state
->now_subseg
= now_subseg
;
10054 state
->generating_literals
= generating_literals
;
10055 generating_literals
++;
10056 subseg_set (new_now_seg
, new_now_subseg
);
10060 /* Use to restore the emitting into the normal place. */
10063 xtensa_restore_emit_state (emit_state
*state
)
10065 generating_literals
= state
->generating_literals
;
10066 subseg_set (state
->now_seg
, state
->now_subseg
);
10070 /* Predicate function used to look up a section in a particular group. */
10073 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10075 const char *gname
= inf
;
10076 const char *group_name
= elf_group_name (sec
);
10078 return (group_name
== gname
10079 || (group_name
!= NULL
10081 && strcmp (group_name
, gname
) == 0));
10085 /* Get the literal section to be used for the current text section.
10086 The result may be cached in the default_lit_sections structure. */
10089 cache_literal_section (bfd_boolean use_abs_literals
)
10091 const char *text_name
, *group_name
= 0;
10092 char *base_name
, *name
, *suffix
;
10094 segT seg
, current_section
;
10095 int current_subsec
;
10096 bfd_boolean linkonce
= FALSE
;
10098 /* Save the current section/subsection. */
10099 current_section
= now_seg
;
10100 current_subsec
= now_subseg
;
10102 /* Clear the cached values if they are no longer valid. */
10103 if (now_seg
!= default_lit_sections
.current_text_seg
)
10105 default_lit_sections
.current_text_seg
= now_seg
;
10106 default_lit_sections
.lit_seg
= NULL
;
10107 default_lit_sections
.lit4_seg
= NULL
;
10110 /* Check if the literal section is already cached. */
10111 if (use_abs_literals
)
10112 pcached
= &default_lit_sections
.lit4_seg
;
10114 pcached
= &default_lit_sections
.lit_seg
;
10119 text_name
= default_lit_sections
.lit_prefix
;
10120 if (! text_name
|| ! *text_name
)
10122 text_name
= segment_name (current_section
);
10123 group_name
= elf_group_name (current_section
);
10124 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10127 base_name
= use_abs_literals
? ".lit4" : ".literal";
10130 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10131 sprintf (name
, "%s.%s", base_name
, group_name
);
10133 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10135 suffix
= strchr (text_name
+ linkonce_len
, '.');
10137 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10138 + (suffix
? strlen (suffix
) : 0));
10139 strcpy (name
, ".gnu.linkonce");
10140 strcat (name
, base_name
);
10142 strcat (name
, suffix
);
10147 /* If the section name ends with ".text", then replace that suffix
10148 instead of appending an additional suffix. */
10149 size_t len
= strlen (text_name
);
10150 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10153 name
= xmalloc (len
+ strlen (base_name
) + 1);
10154 strcpy (name
, text_name
);
10155 strcpy (name
+ len
, base_name
);
10158 /* Canonicalize section names to allow renaming literal sections.
10159 The group name, if any, came from the current text section and
10160 has already been canonicalized. */
10161 name
= tc_canonicalize_symbol_name (name
);
10163 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10164 (void *) group_name
);
10169 seg
= subseg_force_new (name
, 0);
10171 if (! use_abs_literals
)
10173 /* Add the newly created literal segment to the list. */
10174 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10176 n
->next
= literal_head
->next
;
10177 literal_head
->next
= n
;
10180 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10181 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10182 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10184 elf_group_name (seg
) = group_name
;
10186 bfd_set_section_flags (stdoutput
, seg
, flags
);
10187 bfd_set_section_alignment (stdoutput
, seg
, 2);
10191 subseg_set (current_section
, current_subsec
);
10196 /* Property Tables Stuff. */
10198 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10199 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10200 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10202 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10203 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10205 static bfd_boolean
get_frag_is_literal (const fragS
*);
10206 static void xtensa_create_property_segments
10207 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10208 static void xtensa_create_xproperty_segments
10209 (frag_flags_fn
, const char *, xt_section_type
);
10210 static segment_info_type
*retrieve_segment_info (segT
);
10211 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10212 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10213 static void add_xt_block_frags
10214 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10215 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10216 static void xtensa_frag_flags_init (frag_flags
*);
10217 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10218 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10219 static void add_xt_prop_frags
10220 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10222 /* Set up property tables after relaxation. */
10225 xtensa_post_relax_hook (void)
10227 xtensa_move_seg_list_to_beginning (literal_head
);
10229 xtensa_find_unmarked_state_frags ();
10230 xtensa_mark_frags_for_org ();
10232 xtensa_create_property_segments (get_frag_is_literal
,
10234 XTENSA_LIT_SEC_NAME
,
10236 xtensa_create_xproperty_segments (get_frag_property_flags
,
10237 XTENSA_PROP_SEC_NAME
,
10240 if (warn_unaligned_branch_targets
)
10241 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10242 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10246 /* This function is only meaningful after xtensa_move_literals. */
10249 get_frag_is_literal (const fragS
*fragP
)
10251 assert (fragP
!= NULL
);
10252 return fragP
->tc_frag_data
.is_literal
;
10257 xtensa_create_property_segments (frag_predicate property_function
,
10258 frag_predicate end_property_function
,
10259 const char *section_name_base
,
10260 xt_section_type sec_type
)
10264 /* Walk over all of the current segments.
10265 Walk over each fragment
10266 For each non-empty fragment,
10267 Build a property record (append where possible). */
10269 for (seclist
= &stdoutput
->sections
;
10270 seclist
&& *seclist
;
10271 seclist
= &(*seclist
)->next
)
10273 segT sec
= *seclist
;
10276 flags
= bfd_get_section_flags (stdoutput
, sec
);
10277 if (flags
& SEC_DEBUGGING
)
10279 if (!(flags
& SEC_ALLOC
))
10282 if (section_has_property (sec
, property_function
))
10285 xtensa_get_property_section (sec
, section_name_base
);
10286 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10287 xtensa_block_info
**xt_blocks
=
10288 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10289 /* Walk over all of the frchains here and add new sections. */
10290 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10291 end_property_function
);
10295 /* Now we fill them out.... */
10297 for (seclist
= &stdoutput
->sections
;
10298 seclist
&& *seclist
;
10299 seclist
= &(*seclist
)->next
)
10301 segment_info_type
*seginfo
;
10302 xtensa_block_info
*block
;
10303 segT sec
= *seclist
;
10305 seginfo
= seg_info (sec
);
10306 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10310 xtensa_block_info
*cur_block
;
10311 /* This is a section with some data. */
10313 bfd_size_type rec_size
;
10315 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10318 rec_size
= num_recs
* 8;
10319 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10321 /* In order to make this work with the assembler, we have to
10322 build some frags and then build the "fixups" for it. It
10323 would be easier to just set the contents then set the
10328 /* Allocate a fragment and leak it. */
10330 bfd_size_type frag_size
;
10332 frchainS
*frchainP
;
10336 frag_size
= sizeof (fragS
) + rec_size
;
10337 fragP
= (fragS
*) xmalloc (frag_size
);
10339 memset (fragP
, 0, frag_size
);
10340 fragP
->fr_address
= 0;
10341 fragP
->fr_next
= NULL
;
10342 fragP
->fr_fix
= rec_size
;
10344 fragP
->fr_type
= rs_fill
;
10345 /* The rest are zeros. */
10347 frchainP
= seginfo
->frchainP
;
10348 frchainP
->frch_root
= fragP
;
10349 frchainP
->frch_last
= fragP
;
10351 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10352 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10354 seginfo
->fix_root
= fixes
;
10355 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10357 frag_data
= &fragP
->fr_literal
[0];
10358 for (i
= 0; i
< num_recs
; i
++)
10360 fixS
*fix
= &fixes
[i
];
10361 assert (cur_block
);
10363 /* Write the fixup. */
10364 if (i
!= num_recs
- 1)
10365 fix
->fx_next
= &fixes
[i
+ 1];
10367 fix
->fx_next
= NULL
;
10370 fix
->fx_frag
= fragP
;
10371 fix
->fx_where
= i
* 8;
10372 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10373 fix
->fx_offset
= cur_block
->offset
;
10374 fix
->fx_r_type
= BFD_RELOC_32
;
10375 fix
->fx_file
= "Internal Assembly";
10378 /* Write the length. */
10379 md_number_to_chars (&frag_data
[4 + 8 * i
],
10380 cur_block
->size
, 4);
10381 cur_block
= cur_block
->next
;
10390 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10391 const char *section_name_base
,
10392 xt_section_type sec_type
)
10396 /* Walk over all of the current segments.
10397 Walk over each fragment.
10398 For each fragment that has instructions,
10399 build an instruction record (append where possible). */
10401 for (seclist
= &stdoutput
->sections
;
10402 seclist
&& *seclist
;
10403 seclist
= &(*seclist
)->next
)
10405 segT sec
= *seclist
;
10408 flags
= bfd_get_section_flags (stdoutput
, sec
);
10409 if ((flags
& SEC_DEBUGGING
)
10410 || !(flags
& SEC_ALLOC
)
10411 || (flags
& SEC_MERGE
))
10414 if (section_has_xproperty (sec
, flag_fn
))
10417 xtensa_get_property_section (sec
, section_name_base
);
10418 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10419 xtensa_block_info
**xt_blocks
=
10420 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10421 /* Walk over all of the frchains here and add new sections. */
10422 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10426 /* Now we fill them out.... */
10428 for (seclist
= &stdoutput
->sections
;
10429 seclist
&& *seclist
;
10430 seclist
= &(*seclist
)->next
)
10432 segment_info_type
*seginfo
;
10433 xtensa_block_info
*block
;
10434 segT sec
= *seclist
;
10436 seginfo
= seg_info (sec
);
10437 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10441 xtensa_block_info
*cur_block
;
10442 /* This is a section with some data. */
10444 bfd_size_type rec_size
;
10446 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10449 rec_size
= num_recs
* (8 + 4);
10450 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10452 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10454 /* In order to make this work with the assembler, we have to build
10455 some frags then build the "fixups" for it. It would be easier to
10456 just set the contents then set the arlents. */
10460 /* Allocate a fragment and (unfortunately) leak it. */
10462 bfd_size_type frag_size
;
10464 frchainS
*frchainP
;
10468 frag_size
= sizeof (fragS
) + rec_size
;
10469 fragP
= (fragS
*) xmalloc (frag_size
);
10471 memset (fragP
, 0, frag_size
);
10472 fragP
->fr_address
= 0;
10473 fragP
->fr_next
= NULL
;
10474 fragP
->fr_fix
= rec_size
;
10476 fragP
->fr_type
= rs_fill
;
10477 /* The rest are zeros. */
10479 frchainP
= seginfo
->frchainP
;
10480 frchainP
->frch_root
= fragP
;
10481 frchainP
->frch_last
= fragP
;
10483 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10484 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10486 seginfo
->fix_root
= fixes
;
10487 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10489 frag_data
= &fragP
->fr_literal
[0];
10490 for (i
= 0; i
< num_recs
; i
++)
10492 fixS
*fix
= &fixes
[i
];
10493 assert (cur_block
);
10495 /* Write the fixup. */
10496 if (i
!= num_recs
- 1)
10497 fix
->fx_next
= &fixes
[i
+ 1];
10499 fix
->fx_next
= NULL
;
10502 fix
->fx_frag
= fragP
;
10503 fix
->fx_where
= i
* (8 + 4);
10504 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10505 fix
->fx_offset
= cur_block
->offset
;
10506 fix
->fx_r_type
= BFD_RELOC_32
;
10507 fix
->fx_file
= "Internal Assembly";
10510 /* Write the length. */
10511 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10512 cur_block
->size
, 4);
10513 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10514 frag_flags_to_number (&cur_block
->flags
),
10516 cur_block
= cur_block
->next
;
10524 static segment_info_type
*
10525 retrieve_segment_info (segT seg
)
10527 segment_info_type
*seginfo
;
10528 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10531 frchainS
*frchainP
;
10533 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10534 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10535 seginfo
->fix_root
= NULL
;
10536 seginfo
->fix_tail
= NULL
;
10537 seginfo
->bfd_section
= seg
;
10539 /* We will not be dealing with these, only our special ones. */
10540 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10542 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10543 frchainP
->frch_root
= NULL
;
10544 frchainP
->frch_last
= NULL
;
10545 frchainP
->frch_next
= NULL
;
10546 frchainP
->frch_subseg
= 0;
10547 frchainP
->fix_root
= NULL
;
10548 frchainP
->fix_tail
= NULL
;
10549 /* Do not init the objstack. */
10550 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10551 /* frchainP->frch_frag_now = fragP; */
10552 frchainP
->frch_frag_now
= NULL
;
10554 seginfo
->frchainP
= frchainP
;
10562 section_has_property (segT sec
, frag_predicate property_function
)
10564 segment_info_type
*seginfo
= seg_info (sec
);
10567 if (seginfo
&& seginfo
->frchainP
)
10569 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10571 if (property_function (fragP
)
10572 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10581 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10583 segment_info_type
*seginfo
= seg_info (sec
);
10586 if (seginfo
&& seginfo
->frchainP
)
10588 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10590 frag_flags prop_flags
;
10591 property_function (fragP
, &prop_flags
);
10592 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10600 /* Two types of block sections exist right now: literal and insns. */
10603 add_xt_block_frags (segT sec
,
10605 xtensa_block_info
**xt_block
,
10606 frag_predicate property_function
,
10607 frag_predicate end_property_function
)
10609 segment_info_type
*seg_info
;
10610 segment_info_type
*xt_seg_info
;
10611 bfd_vma seg_offset
;
10614 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10615 seg_info
= retrieve_segment_info (sec
);
10617 /* Build it if needed. */
10618 while (*xt_block
!= NULL
)
10619 xt_block
= &(*xt_block
)->next
;
10620 /* We are either at NULL at the beginning or at the end. */
10622 /* Walk through the frags. */
10625 if (seg_info
->frchainP
)
10627 for (fragP
= seg_info
->frchainP
->frch_root
;
10629 fragP
= fragP
->fr_next
)
10631 if (property_function (fragP
)
10632 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10634 if (*xt_block
!= NULL
)
10636 if ((*xt_block
)->offset
+ (*xt_block
)->size
10637 == fragP
->fr_address
)
10638 (*xt_block
)->size
+= fragP
->fr_fix
;
10640 xt_block
= &((*xt_block
)->next
);
10642 if (*xt_block
== NULL
)
10644 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10645 xmalloc (sizeof (xtensa_block_info
));
10646 new_block
->sec
= sec
;
10647 new_block
->offset
= fragP
->fr_address
;
10648 new_block
->size
= fragP
->fr_fix
;
10649 new_block
->next
= NULL
;
10650 xtensa_frag_flags_init (&new_block
->flags
);
10651 *xt_block
= new_block
;
10653 if (end_property_function
10654 && end_property_function (fragP
))
10656 xt_block
= &((*xt_block
)->next
);
10664 /* Break the encapsulation of add_xt_prop_frags here. */
10667 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10669 if (prop_flags
->is_literal
10670 || prop_flags
->is_insn
10671 || prop_flags
->is_data
10672 || prop_flags
->is_unreachable
)
10679 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10681 memset (prop_flags
, 0, sizeof (frag_flags
));
10686 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10688 xtensa_frag_flags_init (prop_flags
);
10689 if (fragP
->tc_frag_data
.is_literal
)
10690 prop_flags
->is_literal
= TRUE
;
10691 if (fragP
->tc_frag_data
.is_specific_opcode
10692 || fragP
->tc_frag_data
.is_no_transform
)
10693 prop_flags
->is_no_transform
= TRUE
;
10694 if (fragP
->tc_frag_data
.is_unreachable
)
10695 prop_flags
->is_unreachable
= TRUE
;
10696 else if (fragP
->tc_frag_data
.is_insn
)
10698 prop_flags
->is_insn
= TRUE
;
10699 if (fragP
->tc_frag_data
.is_loop_target
)
10700 prop_flags
->insn
.is_loop_target
= TRUE
;
10701 if (fragP
->tc_frag_data
.is_branch_target
)
10702 prop_flags
->insn
.is_branch_target
= TRUE
;
10703 if (fragP
->tc_frag_data
.is_no_density
)
10704 prop_flags
->insn
.is_no_density
= TRUE
;
10705 if (fragP
->tc_frag_data
.use_absolute_literals
)
10706 prop_flags
->insn
.is_abslit
= TRUE
;
10708 if (fragP
->tc_frag_data
.is_align
)
10710 prop_flags
->is_align
= TRUE
;
10711 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10712 if (xtensa_frag_flags_is_empty (prop_flags
))
10713 prop_flags
->is_data
= TRUE
;
10719 frag_flags_to_number (const frag_flags
*prop_flags
)
10722 if (prop_flags
->is_literal
)
10723 num
|= XTENSA_PROP_LITERAL
;
10724 if (prop_flags
->is_insn
)
10725 num
|= XTENSA_PROP_INSN
;
10726 if (prop_flags
->is_data
)
10727 num
|= XTENSA_PROP_DATA
;
10728 if (prop_flags
->is_unreachable
)
10729 num
|= XTENSA_PROP_UNREACHABLE
;
10730 if (prop_flags
->insn
.is_loop_target
)
10731 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10732 if (prop_flags
->insn
.is_branch_target
)
10734 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10735 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10738 if (prop_flags
->insn
.is_no_density
)
10739 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10740 if (prop_flags
->is_no_transform
)
10741 num
|= XTENSA_PROP_NO_TRANSFORM
;
10742 if (prop_flags
->insn
.is_no_reorder
)
10743 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10744 if (prop_flags
->insn
.is_abslit
)
10745 num
|= XTENSA_PROP_INSN_ABSLIT
;
10747 if (prop_flags
->is_align
)
10749 num
|= XTENSA_PROP_ALIGN
;
10750 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10758 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10759 const frag_flags
*prop_flags_2
)
10761 /* Cannot combine with an end marker. */
10763 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10765 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10767 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10770 if (prop_flags_1
->is_insn
)
10772 /* Properties of the beginning of the frag. */
10773 if (prop_flags_2
->insn
.is_loop_target
)
10775 if (prop_flags_2
->insn
.is_branch_target
)
10777 if (prop_flags_1
->insn
.is_no_density
!=
10778 prop_flags_2
->insn
.is_no_density
)
10780 if (prop_flags_1
->is_no_transform
!=
10781 prop_flags_2
->is_no_transform
)
10783 if (prop_flags_1
->insn
.is_no_reorder
!=
10784 prop_flags_2
->insn
.is_no_reorder
)
10786 if (prop_flags_1
->insn
.is_abslit
!=
10787 prop_flags_2
->insn
.is_abslit
)
10791 if (prop_flags_1
->is_align
)
10799 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10802 unsigned align_bits
;
10804 if (!xt_block
->flags
.is_align
)
10805 return xt_block
->size
;
10807 end_addr
= xt_block
->offset
+ xt_block
->size
;
10808 align_bits
= xt_block
->flags
.alignment
;
10809 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10810 return end_addr
- xt_block
->offset
;
10815 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10816 const xtensa_block_info
*xt_block_2
)
10818 if (xt_block
->sec
!= xt_block_2
->sec
)
10820 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10821 != xt_block_2
->offset
)
10824 if (xt_block_2
->size
== 0
10825 && (!xt_block_2
->flags
.is_unreachable
10826 || xt_block
->flags
.is_unreachable
))
10828 if (xt_block_2
->flags
.is_align
10829 && xt_block
->flags
.is_align
)
10831 /* Nothing needed. */
10832 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10837 if (xt_block_2
->flags
.is_align
)
10839 /* Push alignment to previous entry. */
10840 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10841 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10846 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10847 &xt_block_2
->flags
))
10850 xt_block
->size
+= xt_block_2
->size
;
10852 if (xt_block_2
->flags
.is_align
)
10854 xt_block
->flags
.is_align
= TRUE
;
10855 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10863 add_xt_prop_frags (segT sec
,
10865 xtensa_block_info
**xt_block
,
10866 frag_flags_fn property_function
)
10868 segment_info_type
*seg_info
;
10869 segment_info_type
*xt_seg_info
;
10870 bfd_vma seg_offset
;
10873 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10874 seg_info
= retrieve_segment_info (sec
);
10875 /* Build it if needed. */
10876 while (*xt_block
!= NULL
)
10878 xt_block
= &(*xt_block
)->next
;
10880 /* We are either at NULL at the beginning or at the end. */
10882 /* Walk through the frags. */
10885 if (seg_info
->frchainP
)
10887 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10888 fragP
= fragP
->fr_next
)
10890 xtensa_block_info tmp_block
;
10891 tmp_block
.sec
= sec
;
10892 tmp_block
.offset
= fragP
->fr_address
;
10893 tmp_block
.size
= fragP
->fr_fix
;
10894 tmp_block
.next
= NULL
;
10895 property_function (fragP
, &tmp_block
.flags
);
10897 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10898 /* && fragP->fr_fix != 0) */
10900 if ((*xt_block
) == NULL
10901 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10903 xtensa_block_info
*new_block
;
10904 if ((*xt_block
) != NULL
)
10905 xt_block
= &(*xt_block
)->next
;
10906 new_block
= (xtensa_block_info
*)
10907 xmalloc (sizeof (xtensa_block_info
));
10908 *new_block
= tmp_block
;
10909 *xt_block
= new_block
;
10917 /* op_placement_info_table */
10919 /* op_placement_info makes it easier to determine which
10920 ops can go in which slots. */
10923 init_op_placement_info_table (void)
10925 xtensa_isa isa
= xtensa_default_isa
;
10926 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10927 xtensa_opcode opcode
;
10930 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10932 op_placement_table
= (op_placement_info_table
)
10933 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10934 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10936 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10938 op_placement_info
*opi
= &op_placement_table
[opcode
];
10939 /* FIXME: Make tinsn allocation dynamic. */
10940 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10941 as_fatal (_("too many operands in instruction"));
10942 opi
->narrowest
= XTENSA_UNDEFINED
;
10943 opi
->narrowest_size
= 0x7F;
10944 opi
->narrowest_slot
= 0;
10946 opi
->num_formats
= 0;
10948 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10950 opi
->slots
[fmt
] = 0;
10951 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10953 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10955 int fmt_length
= xtensa_format_length (isa
, fmt
);
10957 set_bit (fmt
, opi
->formats
);
10958 set_bit (slot
, opi
->slots
[fmt
]);
10959 if (fmt_length
< opi
->narrowest_size
10960 || (fmt_length
== opi
->narrowest_size
10961 && (xtensa_format_num_slots (isa
, fmt
)
10962 < xtensa_format_num_slots (isa
,
10965 opi
->narrowest
= fmt
;
10966 opi
->narrowest_size
= fmt_length
;
10967 opi
->narrowest_slot
= slot
;
10972 opi
->num_formats
++;
10975 xtensa_insnbuf_free (isa
, ibuf
);
10980 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10982 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10986 /* If the opcode is available in a single slot format, return its size. */
10989 xg_get_single_size (xtensa_opcode opcode
)
10991 return op_placement_table
[opcode
].narrowest_size
;
10995 static xtensa_format
10996 xg_get_single_format (xtensa_opcode opcode
)
10998 return op_placement_table
[opcode
].narrowest
;
11003 xg_get_single_slot (xtensa_opcode opcode
)
11005 return op_placement_table
[opcode
].narrowest_slot
;
11009 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11012 istack_init (IStack
*stack
)
11014 memset (stack
, 0, sizeof (IStack
));
11020 istack_empty (IStack
*stack
)
11022 return (stack
->ninsn
== 0);
11027 istack_full (IStack
*stack
)
11029 return (stack
->ninsn
== MAX_ISTACK
);
11033 /* Return a pointer to the top IStack entry.
11034 It is an error to call this if istack_empty () is TRUE. */
11037 istack_top (IStack
*stack
)
11039 int rec
= stack
->ninsn
- 1;
11040 assert (!istack_empty (stack
));
11041 return &stack
->insn
[rec
];
11045 /* Add a new TInsn to an IStack.
11046 It is an error to call this if istack_full () is TRUE. */
11049 istack_push (IStack
*stack
, TInsn
*insn
)
11051 int rec
= stack
->ninsn
;
11052 assert (!istack_full (stack
));
11053 stack
->insn
[rec
] = *insn
;
11058 /* Clear space for the next TInsn on the IStack and return a pointer
11059 to it. It is an error to call this if istack_full () is TRUE. */
11062 istack_push_space (IStack
*stack
)
11064 int rec
= stack
->ninsn
;
11066 assert (!istack_full (stack
));
11067 insn
= &stack
->insn
[rec
];
11074 /* Remove the last pushed instruction. It is an error to call this if
11075 istack_empty () returns TRUE. */
11078 istack_pop (IStack
*stack
)
11080 int rec
= stack
->ninsn
- 1;
11081 assert (!istack_empty (stack
));
11083 tinsn_init (&stack
->insn
[rec
]);
11087 /* TInsn functions. */
11090 tinsn_init (TInsn
*dst
)
11092 memset (dst
, 0, sizeof (TInsn
));
11096 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11099 tinsn_has_symbolic_operands (const TInsn
*insn
)
11102 int n
= insn
->ntok
;
11104 assert (insn
->insn_type
== ITYPE_INSN
);
11106 for (i
= 0; i
< n
; ++i
)
11108 switch (insn
->tok
[i
].X_op
)
11122 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11124 xtensa_isa isa
= xtensa_default_isa
;
11126 int n
= insn
->ntok
;
11128 assert (insn
->insn_type
== ITYPE_INSN
);
11130 for (i
= 0; i
< n
; ++i
)
11132 switch (insn
->tok
[i
].X_op
)
11140 /* Errors for these types are caught later. */
11145 /* Symbolic immediates are only allowed on the last immediate
11146 operand. At this time, CONST16 is the only opcode where we
11147 support non-PC-relative relocations. */
11148 if (i
!= get_relaxable_immed (insn
->opcode
)
11149 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11150 && insn
->opcode
!= xtensa_const16_opcode
))
11152 as_bad (_("invalid symbolic operand"));
11161 /* For assembly code with complex expressions (e.g. subtraction),
11162 we have to build them in the literal pool so that
11163 their results are calculated correctly after relaxation.
11164 The relaxation only handles expressions that
11165 boil down to SYMBOL + OFFSET. */
11168 tinsn_has_complex_operands (const TInsn
*insn
)
11171 int n
= insn
->ntok
;
11172 assert (insn
->insn_type
== ITYPE_INSN
);
11173 for (i
= 0; i
< n
; ++i
)
11175 switch (insn
->tok
[i
].X_op
)
11191 /* Encode a TInsn opcode and its constant operands into slotbuf.
11192 Return TRUE if there is a symbol in the immediate field. This
11193 function assumes that:
11194 1) The number of operands are correct.
11195 2) The insn_type is ITYPE_INSN.
11196 3) The opcode can be encoded in the specified format and slot.
11197 4) Operands are either O_constant or O_symbol, and all constants fit. */
11200 tinsn_to_slotbuf (xtensa_format fmt
,
11203 xtensa_insnbuf slotbuf
)
11205 xtensa_isa isa
= xtensa_default_isa
;
11206 xtensa_opcode opcode
= tinsn
->opcode
;
11207 bfd_boolean has_fixup
= FALSE
;
11208 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11211 assert (tinsn
->insn_type
== ITYPE_INSN
);
11212 if (noperands
!= tinsn
->ntok
)
11213 as_fatal (_("operand number mismatch"));
11215 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11217 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11218 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11222 for (i
= 0; i
< noperands
; i
++)
11224 expressionS
*expr
= &tinsn
->tok
[i
];
11230 switch (expr
->X_op
)
11233 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11235 /* The register number has already been checked in
11236 expression_maybe_register, so we don't need to check here. */
11237 opnd_value
= expr
->X_add_number
;
11238 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11239 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11242 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11246 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11248 as_where (&file_name
, &line
);
11249 /* It is a constant and we called this function
11250 then we have to try to fit it. */
11251 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11252 expr
->X_add_number
, file_name
, line
);
11265 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11266 into a multi-slot instruction, fill the other slots with NOPs.
11267 Return TRUE if there is a symbol in the immediate field. See also the
11268 assumptions listed for tinsn_to_slotbuf. */
11271 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11273 static xtensa_insnbuf slotbuf
= 0;
11274 static vliw_insn vinsn
;
11275 xtensa_isa isa
= xtensa_default_isa
;
11276 bfd_boolean has_fixup
= FALSE
;
11281 slotbuf
= xtensa_insnbuf_alloc (isa
);
11282 xg_init_vinsn (&vinsn
);
11285 xg_clear_vinsn (&vinsn
);
11287 bundle_tinsn (tinsn
, &vinsn
);
11289 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11291 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11293 /* Only one slot may have a fix-up because the rest contains NOPs. */
11295 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11296 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11303 /* Check the instruction arguments. Return TRUE on failure. */
11306 tinsn_check_arguments (const TInsn
*insn
)
11308 xtensa_isa isa
= xtensa_default_isa
;
11309 xtensa_opcode opcode
= insn
->opcode
;
11311 if (opcode
== XTENSA_UNDEFINED
)
11313 as_bad (_("invalid opcode"));
11317 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11319 as_bad (_("too few operands"));
11323 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11325 as_bad (_("too many operands"));
11332 /* Load an instruction from its encoded form. */
11335 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11339 xg_init_vinsn (&vinsn
);
11340 vinsn_from_chars (&vinsn
, f
);
11342 *tinsn
= vinsn
.slots
[slot
];
11343 xg_free_vinsn (&vinsn
);
11348 tinsn_from_insnbuf (TInsn
*tinsn
,
11349 xtensa_insnbuf slotbuf
,
11354 xtensa_isa isa
= xtensa_default_isa
;
11356 /* Find the immed. */
11357 tinsn_init (tinsn
);
11358 tinsn
->insn_type
= ITYPE_INSN
;
11359 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11360 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11361 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11362 for (i
= 0; i
< tinsn
->ntok
; i
++)
11364 set_expr_const (&tinsn
->tok
[i
],
11365 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11366 tinsn
->opcode
, i
));
11371 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11374 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11376 xtensa_opcode opcode
= tinsn
->opcode
;
11379 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11381 opnum
= get_relaxable_immed (opcode
);
11382 assert (opnum
>= 0);
11383 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11384 fragP
->tc_frag_data
.slot_symbols
[slot
],
11385 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11391 get_num_stack_text_bytes (IStack
*istack
)
11394 int text_bytes
= 0;
11396 for (i
= 0; i
< istack
->ninsn
; i
++)
11398 TInsn
*tinsn
= &istack
->insn
[i
];
11399 if (tinsn
->insn_type
== ITYPE_INSN
)
11400 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11407 get_num_stack_literal_bytes (IStack
*istack
)
11412 for (i
= 0; i
< istack
->ninsn
; i
++)
11414 TInsn
*tinsn
= &istack
->insn
[i
];
11415 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11422 /* vliw_insn functions. */
11425 xg_init_vinsn (vliw_insn
*v
)
11428 xtensa_isa isa
= xtensa_default_isa
;
11430 xg_clear_vinsn (v
);
11432 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11433 if (v
->insnbuf
== NULL
)
11434 as_fatal (_("out of memory"));
11436 for (i
= 0; i
< MAX_SLOTS
; i
++)
11438 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11439 if (v
->slotbuf
[i
] == NULL
)
11440 as_fatal (_("out of memory"));
11446 xg_clear_vinsn (vliw_insn
*v
)
11450 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11452 v
->format
= XTENSA_UNDEFINED
;
11454 v
->inside_bundle
= FALSE
;
11456 if (xt_saved_debug_type
!= DEBUG_NONE
)
11457 debug_type
= xt_saved_debug_type
;
11459 for (i
= 0; i
< MAX_SLOTS
; i
++)
11460 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11465 vinsn_has_specific_opcodes (vliw_insn
*v
)
11469 for (i
= 0; i
< v
->num_slots
; i
++)
11471 if (v
->slots
[i
].is_specific_opcode
)
11479 xg_free_vinsn (vliw_insn
*v
)
11482 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11483 for (i
= 0; i
< MAX_SLOTS
; i
++)
11484 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11488 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11489 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11492 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11495 bfd_boolean record_fixup
)
11497 xtensa_isa isa
= xtensa_default_isa
;
11498 xtensa_format fmt
= vinsn
->format
;
11499 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11501 bfd_boolean has_fixup
= FALSE
;
11503 xtensa_format_encode (isa
, fmt
, insnbuf
);
11505 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11507 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11508 bfd_boolean tinsn_has_fixup
=
11509 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11510 vinsn
->slotbuf
[slot
]);
11512 xtensa_format_set_slot (isa
, fmt
, slot
,
11513 insnbuf
, vinsn
->slotbuf
[slot
]);
11514 if (tinsn_has_fixup
)
11517 xtensa_opcode opcode
= tinsn
->opcode
;
11518 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11521 for (i
= 0; i
< noperands
; i
++)
11523 expressionS
* expr
= &tinsn
->tok
[i
];
11524 switch (expr
->X_op
)
11529 if (get_relaxable_immed (opcode
) == i
)
11531 /* Add a fix record for the instruction, except if this
11532 function is being called prior to relaxation, i.e.,
11533 if record_fixup is false, and the instruction might
11534 be relaxed later. */
11536 || tinsn
->is_specific_opcode
11537 || !xg_is_relaxable_insn (tinsn
, 0))
11539 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11540 frag_offset
- fragP
->fr_literal
);
11544 if (expr
->X_op
!= O_symbol
)
11545 as_bad (_("invalid operand"));
11546 tinsn
->symbol
= expr
->X_add_symbol
;
11547 tinsn
->offset
= expr
->X_add_number
;
11551 as_bad (_("symbolic operand not allowed"));
11559 as_bad (_("expression too complex"));
11571 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11573 static xtensa_insnbuf insnbuf
= NULL
;
11574 static xtensa_insnbuf slotbuf
= NULL
;
11577 xtensa_isa isa
= xtensa_default_isa
;
11581 insnbuf
= xtensa_insnbuf_alloc (isa
);
11582 slotbuf
= xtensa_insnbuf_alloc (isa
);
11585 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11586 fmt
= xtensa_format_decode (isa
, insnbuf
);
11587 if (fmt
== XTENSA_UNDEFINED
)
11588 as_fatal (_("cannot decode instruction format"));
11589 vinsn
->format
= fmt
;
11590 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11592 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11594 TInsn
*tinsn
= &vinsn
->slots
[i
];
11595 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11596 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11601 /* Expression utilities. */
11603 /* Return TRUE if the expression is an integer constant. */
11606 expr_is_const (const expressionS
*s
)
11608 return (s
->X_op
== O_constant
);
11612 /* Get the expression constant.
11613 Calling this is illegal if expr_is_const () returns TRUE. */
11616 get_expr_const (const expressionS
*s
)
11618 assert (expr_is_const (s
));
11619 return s
->X_add_number
;
11623 /* Set the expression to a constant value. */
11626 set_expr_const (expressionS
*s
, offsetT val
)
11628 s
->X_op
= O_constant
;
11629 s
->X_add_number
= val
;
11630 s
->X_add_symbol
= NULL
;
11631 s
->X_op_symbol
= NULL
;
11636 expr_is_register (const expressionS
*s
)
11638 return (s
->X_op
== O_register
);
11642 /* Get the expression constant.
11643 Calling this is illegal if expr_is_const () returns TRUE. */
11646 get_expr_register (const expressionS
*s
)
11648 assert (expr_is_register (s
));
11649 return s
->X_add_number
;
11653 /* Set the expression to a symbol + constant offset. */
11656 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11658 s
->X_op
= O_symbol
;
11659 s
->X_add_symbol
= sym
;
11660 s
->X_op_symbol
= NULL
; /* unused */
11661 s
->X_add_number
= offset
;
11665 /* Return TRUE if the two expressions are equal. */
11668 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11670 if (s1
->X_op
!= s2
->X_op
)
11672 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11674 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11676 if (s1
->X_add_number
!= s2
->X_add_number
)
11683 copy_expr (expressionS
*dst
, const expressionS
*src
)
11685 memcpy (dst
, src
, sizeof (expressionS
));
11689 /* Support for the "--rename-section" option. */
11691 struct rename_section_struct
11695 struct rename_section_struct
*next
;
11698 static struct rename_section_struct
*section_rename
;
11701 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11702 entries to the section_rename list. Note: Specifying multiple
11703 renamings separated by colons is not documented and is retained only
11704 for backward compatibility. */
11707 build_section_rename (const char *arg
)
11709 struct rename_section_struct
*r
;
11710 char *this_arg
= NULL
;
11711 char *next_arg
= NULL
;
11713 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11715 char *old_name
, *new_name
;
11719 next_arg
= strchr (this_arg
, ':');
11727 old_name
= this_arg
;
11728 new_name
= strchr (this_arg
, '=');
11730 if (*old_name
== '\0')
11732 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11735 if (!new_name
|| new_name
[1] == '\0')
11737 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11744 /* Check for invalid section renaming. */
11745 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11747 if (strcmp (r
->old_name
, old_name
) == 0)
11748 as_bad (_("section %s renamed multiple times"), old_name
);
11749 if (strcmp (r
->new_name
, new_name
) == 0)
11750 as_bad (_("multiple sections remapped to output section %s"),
11755 r
= (struct rename_section_struct
*)
11756 xmalloc (sizeof (struct rename_section_struct
));
11757 r
->old_name
= xstrdup (old_name
);
11758 r
->new_name
= xstrdup (new_name
);
11759 r
->next
= section_rename
;
11760 section_rename
= r
;
11766 xtensa_section_rename (char *name
)
11768 struct rename_section_struct
*r
= section_rename
;
11770 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11772 if (strcmp (r
->old_name
, name
) == 0)
11773 return r
->new_name
;