1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 /* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
357 #define O_pcrel O_md4 /* value is a PC-relative offset */
359 struct suffix_reloc_map
363 bfd_reloc_code_real_type reloc
;
364 unsigned char operator;
367 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
369 static struct suffix_reloc_map suffix_relocs
[] =
371 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
372 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
373 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
374 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
375 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
389 directive_literal_prefix
,
391 directive_absolute_literals
,
392 directive_last_directive
398 bfd_boolean can_be_negated
;
401 const directive_infoS directive_info
[] =
404 { "literal", FALSE
},
406 { "transform", TRUE
},
407 { "freeregs", FALSE
},
408 { "longcalls", TRUE
},
409 { "literal_prefix", FALSE
},
410 { "schedule", TRUE
},
411 { "absolute-literals", TRUE
}
414 bfd_boolean directive_state
[] =
418 #if !XCHAL_HAVE_DENSITY
423 TRUE
, /* transform */
424 FALSE
, /* freeregs */
425 FALSE
, /* longcalls */
426 FALSE
, /* literal_prefix */
427 FALSE
, /* schedule */
428 #if XSHAL_USE_ABSOLUTE_LITERALS
429 TRUE
/* absolute_literals */
431 FALSE
/* absolute_literals */
436 /* Directive functions. */
438 static void xtensa_begin_directive (int);
439 static void xtensa_end_directive (int);
440 static void xtensa_literal_prefix (void);
441 static void xtensa_literal_position (int);
442 static void xtensa_literal_pseudo (int);
443 static void xtensa_frequency_pseudo (int);
444 static void xtensa_elf_cons (int);
445 static void xtensa_leb128 (int);
447 /* Parsing and Idiom Translation. */
449 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
451 /* Various Other Internal Functions. */
453 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
454 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
455 static void xtensa_mark_literal_pool_location (void);
456 static addressT
get_expanded_loop_offset (xtensa_opcode
);
457 static fragS
*get_literal_pool_location (segT
);
458 static void set_literal_pool_location (segT
, fragS
*);
459 static void xtensa_set_frag_assembly_state (fragS
*);
460 static void finish_vinsn (vliw_insn
*);
461 static bfd_boolean
emit_single_op (TInsn
*);
462 static int total_frag_text_expansion (fragS
*);
464 /* Alignment Functions. */
466 static int get_text_align_power (unsigned);
467 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
468 static int branch_align_power (segT
);
470 /* Helpers for xtensa_relax_frag(). */
472 static long relax_frag_add_nop (fragS
*);
474 /* Accessors for additional per-subsegment information. */
476 static unsigned get_last_insn_flags (segT
, subsegT
);
477 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
478 static float get_subseg_total_freq (segT
, subsegT
);
479 static float get_subseg_target_freq (segT
, subsegT
);
480 static void set_subseg_freq (segT
, subsegT
, float, float);
482 /* Segment list functions. */
484 static void xtensa_move_literals (void);
485 static void xtensa_reorder_segments (void);
486 static void xtensa_switch_to_literal_fragment (emit_state
*);
487 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
488 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
489 static void xtensa_restore_emit_state (emit_state
*);
490 static segT
cache_literal_section (bfd_boolean
);
492 /* Import from elf32-xtensa.c in BFD library. */
494 extern asection
*xtensa_get_property_section (asection
*, const char *);
496 /* op_placement_info functions. */
498 static void init_op_placement_info_table (void);
499 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
500 static int xg_get_single_size (xtensa_opcode
);
501 static xtensa_format
xg_get_single_format (xtensa_opcode
);
502 static int xg_get_single_slot (xtensa_opcode
);
504 /* TInsn and IStack functions. */
506 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
507 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
508 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
509 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
510 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
511 static void tinsn_from_chars (TInsn
*, char *, int);
512 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
513 static int get_num_stack_text_bytes (IStack
*);
514 static int get_num_stack_literal_bytes (IStack
*);
516 /* vliw_insn functions. */
518 static void xg_init_vinsn (vliw_insn
*);
519 static void xg_clear_vinsn (vliw_insn
*);
520 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
521 static void xg_free_vinsn (vliw_insn
*);
522 static bfd_boolean vinsn_to_insnbuf
523 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
524 static void vinsn_from_chars (vliw_insn
*, char *);
526 /* Expression Utilities. */
528 bfd_boolean
expr_is_const (const expressionS
*);
529 offsetT
get_expr_const (const expressionS
*);
530 void set_expr_const (expressionS
*, offsetT
);
531 bfd_boolean
expr_is_register (const expressionS
*);
532 offsetT
get_expr_register (const expressionS
*);
533 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
534 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
535 static void copy_expr (expressionS
*, const expressionS
*);
537 /* Section renaming. */
539 static void build_section_rename (const char *);
542 /* ISA imported from bfd. */
543 extern xtensa_isa xtensa_default_isa
;
545 extern int target_big_endian
;
547 static xtensa_opcode xtensa_addi_opcode
;
548 static xtensa_opcode xtensa_addmi_opcode
;
549 static xtensa_opcode xtensa_call0_opcode
;
550 static xtensa_opcode xtensa_call4_opcode
;
551 static xtensa_opcode xtensa_call8_opcode
;
552 static xtensa_opcode xtensa_call12_opcode
;
553 static xtensa_opcode xtensa_callx0_opcode
;
554 static xtensa_opcode xtensa_callx4_opcode
;
555 static xtensa_opcode xtensa_callx8_opcode
;
556 static xtensa_opcode xtensa_callx12_opcode
;
557 static xtensa_opcode xtensa_const16_opcode
;
558 static xtensa_opcode xtensa_entry_opcode
;
559 static xtensa_opcode xtensa_extui_opcode
;
560 static xtensa_opcode xtensa_movi_opcode
;
561 static xtensa_opcode xtensa_movi_n_opcode
;
562 static xtensa_opcode xtensa_isync_opcode
;
563 static xtensa_opcode xtensa_jx_opcode
;
564 static xtensa_opcode xtensa_l32r_opcode
;
565 static xtensa_opcode xtensa_loop_opcode
;
566 static xtensa_opcode xtensa_loopnez_opcode
;
567 static xtensa_opcode xtensa_loopgtz_opcode
;
568 static xtensa_opcode xtensa_nop_opcode
;
569 static xtensa_opcode xtensa_nop_n_opcode
;
570 static xtensa_opcode xtensa_or_opcode
;
571 static xtensa_opcode xtensa_ret_opcode
;
572 static xtensa_opcode xtensa_ret_n_opcode
;
573 static xtensa_opcode xtensa_retw_opcode
;
574 static xtensa_opcode xtensa_retw_n_opcode
;
575 static xtensa_opcode xtensa_rsr_lcount_opcode
;
576 static xtensa_opcode xtensa_waiti_opcode
;
579 /* Command-line Options. */
581 bfd_boolean use_literal_section
= TRUE
;
582 static bfd_boolean align_targets
= TRUE
;
583 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
584 static bfd_boolean has_a0_b_retw
= FALSE
;
585 static bfd_boolean workaround_a0_b_retw
= FALSE
;
586 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
587 static bfd_boolean workaround_short_loop
= FALSE
;
588 static bfd_boolean maybe_has_short_loop
= FALSE
;
589 static bfd_boolean workaround_close_loop_end
= FALSE
;
590 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
591 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
593 /* When workaround_short_loops is TRUE, all loops with early exits must
594 have at least 3 instructions. workaround_all_short_loops is a modifier
595 to the workaround_short_loop flag. In addition to the
596 workaround_short_loop actions, all straightline loopgtz and loopnez
597 must have at least 3 instructions. */
599 static bfd_boolean workaround_all_short_loops
= FALSE
;
603 xtensa_setup_hw_workarounds (int earliest
, int latest
)
605 if (earliest
> latest
)
606 as_fatal (_("illegal range of target hardware versions"));
608 /* Enable all workarounds for pre-T1050.0 hardware. */
609 if (earliest
< 105000 || latest
< 105000)
611 workaround_a0_b_retw
|= TRUE
;
612 workaround_b_j_loop_end
|= TRUE
;
613 workaround_short_loop
|= TRUE
;
614 workaround_close_loop_end
|= TRUE
;
615 workaround_all_short_loops
|= TRUE
;
616 enforce_three_byte_loop_align
= TRUE
;
623 option_density
= OPTION_MD_BASE
,
630 option_no_link_relax
,
638 option_text_section_literals
,
639 option_no_text_section_literals
,
641 option_absolute_literals
,
642 option_no_absolute_literals
,
644 option_align_targets
,
645 option_no_align_targets
,
647 option_warn_unaligned_targets
,
652 option_workaround_a0_b_retw
,
653 option_no_workaround_a0_b_retw
,
655 option_workaround_b_j_loop_end
,
656 option_no_workaround_b_j_loop_end
,
658 option_workaround_short_loop
,
659 option_no_workaround_short_loop
,
661 option_workaround_all_short_loops
,
662 option_no_workaround_all_short_loops
,
664 option_workaround_close_loop_end
,
665 option_no_workaround_close_loop_end
,
667 option_no_workarounds
,
669 option_rename_section_name
,
672 option_prefer_const16
,
674 option_target_hardware
677 const char *md_shortopts
= "";
679 struct option md_longopts
[] =
681 { "density", no_argument
, NULL
, option_density
},
682 { "no-density", no_argument
, NULL
, option_no_density
},
684 /* Both "relax" and "generics" are deprecated and treated as equivalent
685 to the "transform" option. */
686 { "relax", no_argument
, NULL
, option_relax
},
687 { "no-relax", no_argument
, NULL
, option_no_relax
},
688 { "generics", no_argument
, NULL
, option_generics
},
689 { "no-generics", no_argument
, NULL
, option_no_generics
},
691 { "transform", no_argument
, NULL
, option_transform
},
692 { "no-transform", no_argument
, NULL
, option_no_transform
},
693 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
694 { "no-text-section-literals", no_argument
, NULL
,
695 option_no_text_section_literals
},
696 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
697 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
698 /* This option was changed from -align-target to -target-align
699 because it conflicted with the "-al" option. */
700 { "target-align", no_argument
, NULL
, option_align_targets
},
701 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
702 { "warn-unaligned-targets", no_argument
, NULL
,
703 option_warn_unaligned_targets
},
704 { "longcalls", no_argument
, NULL
, option_longcalls
},
705 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
707 { "no-workaround-a0-b-retw", no_argument
, NULL
,
708 option_no_workaround_a0_b_retw
},
709 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
711 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
712 option_no_workaround_b_j_loop_end
},
713 { "workaround-b-j-loop-end", no_argument
, NULL
,
714 option_workaround_b_j_loop_end
},
716 { "no-workaround-short-loops", no_argument
, NULL
,
717 option_no_workaround_short_loop
},
718 { "workaround-short-loops", no_argument
, NULL
,
719 option_workaround_short_loop
},
721 { "no-workaround-all-short-loops", no_argument
, NULL
,
722 option_no_workaround_all_short_loops
},
723 { "workaround-all-short-loop", no_argument
, NULL
,
724 option_workaround_all_short_loops
},
726 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
727 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
729 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
731 { "no-workaround-close-loop-end", no_argument
, NULL
,
732 option_no_workaround_close_loop_end
},
733 { "workaround-close-loop-end", no_argument
, NULL
,
734 option_workaround_close_loop_end
},
736 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
738 { "link-relax", no_argument
, NULL
, option_link_relax
},
739 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
741 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
743 { NULL
, no_argument
, NULL
, 0 }
746 size_t md_longopts_size
= sizeof md_longopts
;
750 md_parse_option (int c
, char *arg
)
755 as_warn (_("--density option is ignored"));
757 case option_no_density
:
758 as_warn (_("--no-density option is ignored"));
760 case option_link_relax
:
763 case option_no_link_relax
:
766 case option_generics
:
767 as_warn (_("--generics is deprecated; use --transform instead"));
768 return md_parse_option (option_transform
, arg
);
769 case option_no_generics
:
770 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
771 return md_parse_option (option_no_transform
, arg
);
773 as_warn (_("--relax is deprecated; use --transform instead"));
774 return md_parse_option (option_transform
, arg
);
775 case option_no_relax
:
776 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
777 return md_parse_option (option_no_transform
, arg
);
778 case option_longcalls
:
779 directive_state
[directive_longcalls
] = TRUE
;
781 case option_no_longcalls
:
782 directive_state
[directive_longcalls
] = FALSE
;
784 case option_text_section_literals
:
785 use_literal_section
= FALSE
;
787 case option_no_text_section_literals
:
788 use_literal_section
= TRUE
;
790 case option_absolute_literals
:
791 if (!absolute_literals_supported
)
793 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
796 directive_state
[directive_absolute_literals
] = TRUE
;
798 case option_no_absolute_literals
:
799 directive_state
[directive_absolute_literals
] = FALSE
;
802 case option_workaround_a0_b_retw
:
803 workaround_a0_b_retw
= TRUE
;
805 case option_no_workaround_a0_b_retw
:
806 workaround_a0_b_retw
= FALSE
;
808 case option_workaround_b_j_loop_end
:
809 workaround_b_j_loop_end
= TRUE
;
811 case option_no_workaround_b_j_loop_end
:
812 workaround_b_j_loop_end
= FALSE
;
815 case option_workaround_short_loop
:
816 workaround_short_loop
= TRUE
;
818 case option_no_workaround_short_loop
:
819 workaround_short_loop
= FALSE
;
822 case option_workaround_all_short_loops
:
823 workaround_all_short_loops
= TRUE
;
825 case option_no_workaround_all_short_loops
:
826 workaround_all_short_loops
= FALSE
;
829 case option_workaround_close_loop_end
:
830 workaround_close_loop_end
= TRUE
;
832 case option_no_workaround_close_loop_end
:
833 workaround_close_loop_end
= FALSE
;
836 case option_no_workarounds
:
837 workaround_a0_b_retw
= FALSE
;
838 workaround_b_j_loop_end
= FALSE
;
839 workaround_short_loop
= FALSE
;
840 workaround_all_short_loops
= FALSE
;
841 workaround_close_loop_end
= FALSE
;
844 case option_align_targets
:
845 align_targets
= TRUE
;
847 case option_no_align_targets
:
848 align_targets
= FALSE
;
851 case option_warn_unaligned_targets
:
852 warn_unaligned_branch_targets
= TRUE
;
855 case option_rename_section_name
:
856 build_section_rename (arg
);
860 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
861 should be emitted or not. FIXME: Not implemented. */
864 case option_prefer_l32r
:
866 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
870 case option_prefer_const16
:
872 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
876 case option_target_hardware
:
878 int earliest
, latest
= 0;
879 if (*arg
== 0 || *arg
== '-')
880 as_fatal (_("invalid target hardware version"));
882 earliest
= strtol (arg
, &arg
, 0);
886 else if (*arg
== '-')
889 as_fatal (_("invalid target hardware version"));
890 latest
= strtol (arg
, &arg
, 0);
893 as_fatal (_("invalid target hardware version"));
895 xtensa_setup_hw_workarounds (earliest
, latest
);
899 case option_transform
:
900 /* This option has no affect other than to use the defaults,
901 which are already set. */
904 case option_no_transform
:
905 /* This option turns off all transformations of any kind.
906 However, because we want to preserve the state of other
907 directives, we only change its own field. Thus, before
908 you perform any transformation, always check if transform
909 is available. If you use the functions we provide for this
910 purpose, you will be ok. */
911 directive_state
[directive_transform
] = FALSE
;
921 md_show_usage (FILE *stream
)
925 --[no-]text-section-literals\n\
926 [Do not] put literals in the text section\n\
927 --[no-]absolute-literals\n\
928 [Do not] default to use non-PC-relative literals\n\
929 --[no-]target-align [Do not] try to align branch targets\n\
930 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
931 --[no-]transform [Do not] transform instructions\n\
932 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
936 /* Functions related to the list of current label symbols. */
939 xtensa_add_insn_label (symbolS
*sym
)
943 if (!free_insn_labels
)
944 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
947 l
= free_insn_labels
;
948 free_insn_labels
= l
->next
;
952 l
->next
= insn_labels
;
958 xtensa_clear_insn_labels (void)
962 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
970 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
974 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
976 symbolS
*lit_sym
= lit
->sym
;
977 S_SET_VALUE (lit_sym
, new_offset
);
978 symbol_set_frag (lit_sym
, new_frag
);
983 /* Directive data and functions. */
985 typedef struct state_stackS_struct
987 directiveE directive
;
989 bfd_boolean old_state
;
993 struct state_stackS_struct
*prev
;
996 state_stackS
*directive_state_stack
;
998 const pseudo_typeS md_pseudo_table
[] =
1000 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1001 { "literal_position", xtensa_literal_position
, 0 },
1002 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1003 { "long", xtensa_elf_cons
, 4 },
1004 { "word", xtensa_elf_cons
, 4 },
1005 { "4byte", xtensa_elf_cons
, 4 },
1006 { "short", xtensa_elf_cons
, 2 },
1007 { "2byte", xtensa_elf_cons
, 2 },
1008 { "sleb128", xtensa_leb128
, 1},
1009 { "uleb128", xtensa_leb128
, 0},
1010 { "begin", xtensa_begin_directive
, 0 },
1011 { "end", xtensa_end_directive
, 0 },
1012 { "literal", xtensa_literal_pseudo
, 0 },
1013 { "frequency", xtensa_frequency_pseudo
, 0 },
1019 use_transform (void)
1021 /* After md_end, you should be checking frag by frag, rather
1022 than state directives. */
1023 assert (!past_xtensa_end
);
1024 return directive_state
[directive_transform
];
1029 do_align_targets (void)
1031 /* Do not use this function after md_end; just look at align_targets
1032 instead. There is no target-align directive, so alignment is either
1033 enabled for all frags or not done at all. */
1034 assert (!past_xtensa_end
);
1035 return align_targets
&& use_transform ();
1040 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1044 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1046 as_where (&file
, &line
);
1048 stack
->directive
= directive
;
1049 stack
->negated
= negated
;
1050 stack
->old_state
= directive_state
[directive
];
1053 stack
->datum
= datum
;
1054 stack
->prev
= directive_state_stack
;
1055 directive_state_stack
= stack
;
1057 directive_state
[directive
] = !negated
;
1062 directive_pop (directiveE
*directive
,
1063 bfd_boolean
*negated
,
1068 state_stackS
*top
= directive_state_stack
;
1070 if (!directive_state_stack
)
1072 as_bad (_("unmatched end directive"));
1073 *directive
= directive_none
;
1077 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1078 *directive
= top
->directive
;
1079 *negated
= top
->negated
;
1082 *datum
= top
->datum
;
1083 directive_state_stack
= top
->prev
;
1089 directive_balance (void)
1091 while (directive_state_stack
)
1093 directiveE directive
;
1094 bfd_boolean negated
;
1099 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1100 as_warn_where ((char *) file
, line
,
1101 _(".begin directive with no matching .end directive"));
1107 inside_directive (directiveE dir
)
1109 state_stackS
*top
= directive_state_stack
;
1111 while (top
&& top
->directive
!= dir
)
1114 return (top
!= NULL
);
1119 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1123 char *directive_string
;
1125 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1130 input_line_pointer
+= 3;
1133 len
= strspn (input_line_pointer
,
1134 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1136 /* This code is a hack to make .begin [no-][generics|relax] exactly
1137 equivalent to .begin [no-]transform. We should remove it when
1138 we stop accepting those options. */
1140 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1142 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1143 directive_string
= "transform";
1145 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1147 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1148 directive_string
= "transform";
1151 directive_string
= input_line_pointer
;
1153 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1155 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1157 input_line_pointer
+= len
;
1158 *directive
= (directiveE
) i
;
1159 if (*negated
&& !directive_info
[i
].can_be_negated
)
1160 as_bad (_("directive %s cannot be negated"),
1161 directive_info
[i
].name
);
1166 as_bad (_("unknown directive"));
1167 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1172 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1174 directiveE directive
;
1175 bfd_boolean negated
;
1179 get_directive (&directive
, &negated
);
1180 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1182 discard_rest_of_line ();
1186 if (cur_vinsn
.inside_bundle
)
1187 as_bad (_("directives are not valid inside bundles"));
1191 case directive_literal
:
1192 if (!inside_directive (directive_literal
))
1194 /* Previous labels go with whatever follows this directive, not with
1195 the literal, so save them now. */
1196 saved_insn_labels
= insn_labels
;
1199 as_warn (_(".begin literal is deprecated; use .literal instead"));
1200 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1201 xtensa_switch_to_literal_fragment (state
);
1202 directive_push (directive_literal
, negated
, state
);
1205 case directive_literal_prefix
:
1206 /* Have to flush pending output because a movi relaxed to an l32r
1207 might produce a literal. */
1208 md_flush_pending_output ();
1209 /* Check to see if the current fragment is a literal
1210 fragment. If it is, then this operation is not allowed. */
1211 if (generating_literals
)
1213 as_bad (_("cannot set literal_prefix inside literal fragment"));
1217 /* Allocate the literal state for this section and push
1218 onto the directive stack. */
1219 ls
= xmalloc (sizeof (lit_state
));
1222 *ls
= default_lit_sections
;
1223 directive_push (directive_literal_prefix
, negated
, ls
);
1225 /* Process the new prefix. */
1226 xtensa_literal_prefix ();
1229 case directive_freeregs
:
1230 /* This information is currently unused, but we'll accept the statement
1231 and just discard the rest of the line. This won't check the syntax,
1232 but it will accept every correct freeregs directive. */
1233 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1234 directive_push (directive_freeregs
, negated
, 0);
1237 case directive_schedule
:
1238 md_flush_pending_output ();
1239 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1240 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1241 directive_push (directive_schedule
, negated
, 0);
1242 xtensa_set_frag_assembly_state (frag_now
);
1245 case directive_density
:
1246 as_warn (_(".begin [no-]density is ignored"));
1249 case directive_absolute_literals
:
1250 md_flush_pending_output ();
1251 if (!absolute_literals_supported
&& !negated
)
1253 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1256 xtensa_set_frag_assembly_state (frag_now
);
1257 directive_push (directive
, negated
, 0);
1261 md_flush_pending_output ();
1262 xtensa_set_frag_assembly_state (frag_now
);
1263 directive_push (directive
, negated
, 0);
1267 demand_empty_rest_of_line ();
1272 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1274 directiveE begin_directive
, end_directive
;
1275 bfd_boolean begin_negated
, end_negated
;
1279 emit_state
**state_ptr
;
1282 if (cur_vinsn
.inside_bundle
)
1283 as_bad (_("directives are not valid inside bundles"));
1285 get_directive (&end_directive
, &end_negated
);
1287 md_flush_pending_output ();
1289 switch (end_directive
)
1291 case (directiveE
) XTENSA_UNDEFINED
:
1292 discard_rest_of_line ();
1295 case directive_density
:
1296 as_warn (_(".end [no-]density is ignored"));
1297 demand_empty_rest_of_line ();
1300 case directive_absolute_literals
:
1301 if (!absolute_literals_supported
&& !end_negated
)
1303 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1304 demand_empty_rest_of_line ();
1313 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1314 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1315 (const void **) state_ptr
);
1317 if (begin_directive
!= directive_none
)
1319 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1321 as_bad (_("does not match begin %s%s at %s:%d"),
1322 begin_negated
? "no-" : "",
1323 directive_info
[begin_directive
].name
, file
, line
);
1327 switch (end_directive
)
1329 case directive_literal
:
1330 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1331 xtensa_restore_emit_state (state
);
1332 xtensa_set_frag_assembly_state (frag_now
);
1334 if (!inside_directive (directive_literal
))
1336 /* Restore the list of current labels. */
1337 xtensa_clear_insn_labels ();
1338 insn_labels
= saved_insn_labels
;
1342 case directive_literal_prefix
:
1343 /* Restore the default collection sections from saved state. */
1344 s
= (lit_state
*) state
;
1346 default_lit_sections
= *s
;
1348 /* Free the state storage. */
1349 free (s
->lit_prefix
);
1353 case directive_schedule
:
1354 case directive_freeregs
:
1358 xtensa_set_frag_assembly_state (frag_now
);
1364 demand_empty_rest_of_line ();
1368 /* Place an aligned literal fragment at the current location. */
1371 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1373 md_flush_pending_output ();
1375 if (inside_directive (directive_literal
))
1376 as_warn (_(".literal_position inside literal directive; ignoring"));
1377 xtensa_mark_literal_pool_location ();
1379 demand_empty_rest_of_line ();
1380 xtensa_clear_insn_labels ();
1384 /* Support .literal label, expr, ... */
1387 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1390 char *p
, *base_name
;
1394 if (inside_directive (directive_literal
))
1396 as_bad (_(".literal not allowed inside .begin literal region"));
1397 ignore_rest_of_line ();
1401 md_flush_pending_output ();
1403 /* Previous labels go with whatever follows this directive, not with
1404 the literal, so save them now. */
1405 saved_insn_labels
= insn_labels
;
1408 /* If we are using text-section literals, then this is the right value... */
1411 base_name
= input_line_pointer
;
1413 xtensa_switch_to_literal_fragment (&state
);
1415 /* ...but if we aren't using text-section-literals, then we
1416 need to put them in the section we just switched to. */
1417 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1420 /* All literals are aligned to four-byte boundaries. */
1421 frag_align (2, 0, 0);
1422 record_alignment (now_seg
, 2);
1424 c
= get_symbol_end ();
1425 /* Just after name is now '\0'. */
1426 p
= input_line_pointer
;
1430 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1432 as_bad (_("expected comma or colon after symbol name; "
1433 "rest of line ignored"));
1434 ignore_rest_of_line ();
1435 xtensa_restore_emit_state (&state
);
1443 input_line_pointer
++; /* skip ',' or ':' */
1445 xtensa_elf_cons (4);
1447 xtensa_restore_emit_state (&state
);
1449 /* Restore the list of current labels. */
1450 xtensa_clear_insn_labels ();
1451 insn_labels
= saved_insn_labels
;
1456 xtensa_literal_prefix (void)
1461 /* Parse the new prefix from the input_line_pointer. */
1463 len
= strspn (input_line_pointer
,
1464 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1465 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1467 /* Get a null-terminated copy of the name. */
1468 name
= xmalloc (len
+ 1);
1470 strncpy (name
, input_line_pointer
, len
);
1473 /* Skip the name in the input line. */
1474 input_line_pointer
+= len
;
1476 default_lit_sections
.lit_prefix
= name
;
1478 /* Clear cached literal sections, since the prefix has changed. */
1479 default_lit_sections
.lit_seg
= NULL
;
1480 default_lit_sections
.lit4_seg
= NULL
;
1484 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1487 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1489 float fall_through_f
, target_f
;
1491 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1492 if (fall_through_f
< 0)
1494 as_bad (_("fall through frequency must be greater than 0"));
1495 ignore_rest_of_line ();
1499 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1502 as_bad (_("branch target frequency must be greater than 0"));
1503 ignore_rest_of_line ();
1507 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1509 demand_empty_rest_of_line ();
1513 /* Like normal .long/.short/.word, except support @plt, etc.
1514 Clobbers input_line_pointer, checks end-of-line. */
1517 xtensa_elf_cons (int nbytes
)
1520 bfd_reloc_code_real_type reloc
;
1522 md_flush_pending_output ();
1524 if (cur_vinsn
.inside_bundle
)
1525 as_bad (_("directives are not valid inside bundles"));
1527 if (is_it_end_of_statement ())
1529 demand_empty_rest_of_line ();
1536 if (exp
.X_op
== O_symbol
1537 && *input_line_pointer
== '@'
1538 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1541 reloc_howto_type
*reloc_howto
=
1542 bfd_reloc_type_lookup (stdoutput
, reloc
);
1544 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1545 as_bad (_("unsupported relocation"));
1546 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1547 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1548 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1549 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1550 as_bad (_("opcode-specific %s relocation used outside "
1551 "an instruction"), reloc_howto
->name
);
1552 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1553 as_bad (_("%s relocations do not fit in %d bytes"),
1554 reloc_howto
->name
, nbytes
);
1557 char *p
= frag_more ((int) nbytes
);
1558 xtensa_set_frag_assembly_state (frag_now
);
1559 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1560 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1565 xtensa_set_frag_assembly_state (frag_now
);
1566 emit_expr (&exp
, (unsigned int) nbytes
);
1569 while (*input_line_pointer
++ == ',');
1571 input_line_pointer
--; /* Put terminator back into stream. */
1572 demand_empty_rest_of_line ();
1575 static bfd_boolean is_leb128_expr
;
1578 xtensa_leb128 (int sign
)
1580 is_leb128_expr
= TRUE
;
1582 is_leb128_expr
= FALSE
;
1586 /* Parsing and Idiom Translation. */
1588 /* Parse @plt, etc. and return the desired relocation. */
1589 static bfd_reloc_code_real_type
1590 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1597 struct suffix_reloc_map
*ptr
;
1600 return BFD_RELOC_NONE
;
1602 for (ch
= *str
, str2
= ident
;
1603 (str2
< ident
+ sizeof (ident
) - 1
1604 && (ISALNUM (ch
) || ch
== '@'));
1607 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1614 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1615 if (ch
== ptr
->suffix
[0]
1616 && len
== ptr
->length
1617 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1619 /* Now check for "identifier@suffix+constant". */
1620 if (*str
== '-' || *str
== '+')
1622 char *orig_line
= input_line_pointer
;
1623 expressionS new_exp
;
1625 input_line_pointer
= str
;
1626 expression (&new_exp
);
1627 if (new_exp
.X_op
== O_constant
)
1629 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1630 str
= input_line_pointer
;
1633 if (&input_line_pointer
!= str_p
)
1634 input_line_pointer
= orig_line
;
1641 return BFD_RELOC_UNUSED
;
1645 /* Find the matching operator type. */
1646 static unsigned char
1647 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1649 struct suffix_reloc_map
*sfx
;
1650 unsigned char operator = (unsigned char) -1;
1652 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1654 if (sfx
->reloc
== reloc
)
1656 operator = sfx
->operator;
1660 assert (operator != (unsigned char) -1);
1665 /* Find the matching reloc type. */
1666 static bfd_reloc_code_real_type
1667 map_operator_to_reloc (unsigned char operator)
1669 struct suffix_reloc_map
*sfx
;
1670 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1672 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1674 if (sfx
->operator == operator)
1681 if (reloc
== BFD_RELOC_UNUSED
)
1682 return BFD_RELOC_32
;
1689 expression_end (const char *name
)
1712 #define ERROR_REG_NUM ((unsigned) -1)
1715 tc_get_register (const char *prefix
)
1718 const char *next_expr
;
1719 const char *old_line_pointer
;
1722 old_line_pointer
= input_line_pointer
;
1724 if (*input_line_pointer
== '$')
1725 ++input_line_pointer
;
1727 /* Accept "sp" as a synonym for "a1". */
1728 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1729 && expression_end (input_line_pointer
+ 2))
1731 input_line_pointer
+= 2;
1732 return 1; /* AR[1] */
1735 while (*input_line_pointer
++ == *prefix
++)
1737 --input_line_pointer
;
1742 as_bad (_("bad register name: %s"), old_line_pointer
);
1743 return ERROR_REG_NUM
;
1746 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1748 as_bad (_("bad register number: %s"), input_line_pointer
);
1749 return ERROR_REG_NUM
;
1754 while (ISDIGIT ((int) *input_line_pointer
))
1755 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1757 if (!(next_expr
= expression_end (input_line_pointer
)))
1759 as_bad (_("bad register name: %s"), old_line_pointer
);
1760 return ERROR_REG_NUM
;
1763 input_line_pointer
= (char *) next_expr
;
1770 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1772 xtensa_isa isa
= xtensa_default_isa
;
1774 /* Check if this is an immediate operand. */
1775 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1777 bfd_reloc_code_real_type reloc
;
1778 segT t
= expression (tok
);
1779 if (t
== absolute_section
1780 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1782 assert (tok
->X_op
== O_constant
);
1783 tok
->X_op
= O_symbol
;
1784 tok
->X_add_symbol
= &abs_symbol
;
1787 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1788 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1793 case BFD_RELOC_LO16
:
1794 if (tok
->X_op
== O_constant
)
1796 tok
->X_add_number
&= 0xffff;
1800 case BFD_RELOC_HI16
:
1801 if (tok
->X_op
== O_constant
)
1803 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1807 case BFD_RELOC_UNUSED
:
1808 as_bad (_("unsupported relocation"));
1810 case BFD_RELOC_32_PCREL
:
1811 as_bad (_("pcrel relocation not allowed in an instruction"));
1816 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1821 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1822 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1824 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1827 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1828 as_bad (_("register number out of range"));
1831 tok
->X_op
= O_register
;
1832 tok
->X_add_symbol
= 0;
1833 tok
->X_add_number
= reg
;
1838 /* Split up the arguments for an opcode or pseudo-op. */
1841 tokenize_arguments (char **args
, char *str
)
1843 char *old_input_line_pointer
;
1844 bfd_boolean saw_comma
= FALSE
;
1845 bfd_boolean saw_arg
= FALSE
;
1846 bfd_boolean saw_colon
= FALSE
;
1848 char *arg_end
, *arg
;
1851 /* Save and restore input_line_pointer around this function. */
1852 old_input_line_pointer
= input_line_pointer
;
1853 input_line_pointer
= str
;
1855 while (*input_line_pointer
)
1858 switch (*input_line_pointer
)
1865 input_line_pointer
++;
1866 if (saw_comma
|| saw_colon
|| !saw_arg
)
1872 input_line_pointer
++;
1873 if (saw_comma
|| saw_colon
|| !saw_arg
)
1879 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1882 arg_end
= input_line_pointer
+ 1;
1883 while (!expression_end (arg_end
))
1886 arg_len
= arg_end
- input_line_pointer
;
1887 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1888 args
[num_args
] = arg
;
1892 strncpy (arg
, input_line_pointer
, arg_len
);
1893 arg
[arg_len
] = '\0';
1895 input_line_pointer
= arg_end
;
1905 if (saw_comma
|| saw_colon
)
1907 input_line_pointer
= old_input_line_pointer
;
1912 as_bad (_("extra comma"));
1914 as_bad (_("extra colon"));
1916 as_bad (_("missing argument"));
1918 as_bad (_("missing comma or colon"));
1919 input_line_pointer
= old_input_line_pointer
;
1924 /* Parse the arguments to an opcode. Return TRUE on error. */
1927 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1929 expressionS
*tok
, *last_tok
;
1930 xtensa_opcode opcode
= insn
->opcode
;
1931 bfd_boolean had_error
= TRUE
;
1932 xtensa_isa isa
= xtensa_default_isa
;
1933 int n
, num_regs
= 0;
1934 int opcode_operand_count
;
1935 int opnd_cnt
, last_opnd_cnt
;
1936 unsigned int next_reg
= 0;
1937 char *old_input_line_pointer
;
1939 if (insn
->insn_type
== ITYPE_LITERAL
)
1940 opcode_operand_count
= 1;
1942 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1945 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1947 /* Save and restore input_line_pointer around this function. */
1948 old_input_line_pointer
= input_line_pointer
;
1954 /* Skip invisible operands. */
1955 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1961 for (n
= 0; n
< num_args
; n
++)
1963 input_line_pointer
= arg_strings
[n
];
1964 if (*input_line_pointer
== ':')
1966 xtensa_regfile opnd_rf
;
1967 input_line_pointer
++;
1970 assert (opnd_cnt
> 0);
1972 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1974 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1975 as_warn (_("incorrect register number, ignoring"));
1980 if (opnd_cnt
>= opcode_operand_count
)
1982 as_warn (_("too many arguments"));
1985 assert (opnd_cnt
< MAX_INSN_ARGS
);
1987 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1988 next_reg
= tok
->X_add_number
+ 1;
1990 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1992 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1994 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1995 /* minus 1 because we are seeing one right now */
2001 last_opnd_cnt
= opnd_cnt
;
2008 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2012 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2015 insn
->ntok
= tok
- insn
->tok
;
2019 input_line_pointer
= old_input_line_pointer
;
2025 get_invisible_operands (TInsn
*insn
)
2027 xtensa_isa isa
= xtensa_default_isa
;
2028 static xtensa_insnbuf slotbuf
= NULL
;
2030 xtensa_opcode opc
= insn
->opcode
;
2031 int slot
, opnd
, fmt_found
;
2035 slotbuf
= xtensa_insnbuf_alloc (isa
);
2037 /* Find format/slot where this can be encoded. */
2040 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2042 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2044 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2050 if (fmt_found
) break;
2055 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2059 /* First encode all the visible operands
2060 (to deal with shared field operands). */
2061 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2063 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2064 && (insn
->tok
[opnd
].X_op
== O_register
2065 || insn
->tok
[opnd
].X_op
== O_constant
))
2067 val
= insn
->tok
[opnd
].X_add_number
;
2068 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2069 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2073 /* Then pull out the values for the invisible ones. */
2074 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2076 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2078 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2079 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2080 insn
->tok
[opnd
].X_add_number
= val
;
2081 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2082 insn
->tok
[opnd
].X_op
= O_register
;
2084 insn
->tok
[opnd
].X_op
= O_constant
;
2093 xg_reverse_shift_count (char **cnt_argp
)
2095 char *cnt_arg
, *new_arg
;
2096 cnt_arg
= *cnt_argp
;
2098 /* replace the argument with "31-(argument)" */
2099 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2100 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2103 *cnt_argp
= new_arg
;
2107 /* If "arg" is a constant expression, return non-zero with the value
2111 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2114 char *save_ptr
= input_line_pointer
;
2116 input_line_pointer
= arg
;
2118 input_line_pointer
= save_ptr
;
2120 if (exp
.X_op
== O_constant
)
2122 *valp
= exp
.X_add_number
;
2131 xg_replace_opname (char **popname
, char *newop
)
2134 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2135 strcpy (*popname
, newop
);
2140 xg_check_num_args (int *pnum_args
,
2145 int num_args
= *pnum_args
;
2147 if (num_args
< expected_num
)
2149 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2150 num_args
, opname
, expected_num
);
2154 if (num_args
> expected_num
)
2156 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2157 num_args
, opname
, expected_num
);
2158 while (num_args
-- > expected_num
)
2160 free (arg_strings
[num_args
]);
2161 arg_strings
[num_args
] = 0;
2163 *pnum_args
= expected_num
;
2171 /* If the register is not specified as part of the opcode,
2172 then get it from the operand and move it to the opcode. */
2175 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2177 xtensa_isa isa
= xtensa_default_isa
;
2179 char *opname
, *new_opname
;
2180 const char *sr_name
;
2181 int is_user
, is_write
;
2186 is_user
= (opname
[1] == 'u');
2187 is_write
= (opname
[0] == 'w');
2189 /* Opname == [rw]ur or [rwx]sr... */
2191 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2194 /* Check if the argument is a symbolic register name. */
2195 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2196 /* Handle WSR to "INTSET" as a special case. */
2197 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2198 && !strcasecmp (arg_strings
[1], "intset"))
2199 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2200 if (sr
== XTENSA_UNDEFINED
2201 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2203 /* Maybe it's a register number.... */
2205 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2207 as_bad (_("invalid register '%s' for '%s' instruction"),
2208 arg_strings
[1], opname
);
2211 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2212 if (sr
== XTENSA_UNDEFINED
)
2214 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2215 (long) val
, opname
);
2220 /* Remove the last argument, which is now part of the opcode. */
2221 free (arg_strings
[1]);
2225 /* Translate the opcode. */
2226 sr_name
= xtensa_sysreg_name (isa
, sr
);
2227 /* Another special case for "WSR.INTSET".... */
2228 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2230 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2231 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2233 *popname
= new_opname
;
2240 xtensa_translate_old_userreg_ops (char **popname
)
2242 xtensa_isa isa
= xtensa_default_isa
;
2244 char *opname
, *new_opname
;
2245 const char *sr_name
;
2246 bfd_boolean has_underbar
= FALSE
;
2249 if (opname
[0] == '_')
2251 has_underbar
= TRUE
;
2255 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2256 if (sr
!= XTENSA_UNDEFINED
)
2258 /* The new default name ("nnn") is different from the old default
2259 name ("URnnn"). The old default is handled below, and we don't
2260 want to recognize [RW]nnn, so do nothing if the name is the (new)
2262 static char namebuf
[10];
2263 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2264 if (strcmp (namebuf
, opname
+ 1) == 0)
2272 /* Only continue if the reg name is "URnnn". */
2273 if (opname
[1] != 'u' || opname
[2] != 'r')
2275 val
= strtoul (opname
+ 3, &end
, 10);
2279 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2280 if (sr
== XTENSA_UNDEFINED
)
2282 as_bad (_("invalid register number (%ld) for '%s'"),
2283 (long) val
, opname
);
2288 /* Translate the opcode. */
2289 sr_name
= xtensa_sysreg_name (isa
, sr
);
2290 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2291 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2292 opname
[0], sr_name
);
2294 *popname
= new_opname
;
2301 xtensa_translate_zero_immed (char *old_op
,
2311 assert (opname
[0] != '_');
2313 if (strcmp (opname
, old_op
) != 0)
2316 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2318 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2320 xg_replace_opname (popname
, new_op
);
2321 free (arg_strings
[1]);
2322 arg_strings
[1] = arg_strings
[2];
2331 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2332 Returns non-zero if an error was found. */
2335 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2337 char *opname
= *popname
;
2338 bfd_boolean has_underbar
= FALSE
;
2342 has_underbar
= TRUE
;
2346 if (strcmp (opname
, "mov") == 0)
2348 if (use_transform () && !has_underbar
&& density_supported
)
2349 xg_replace_opname (popname
, "mov.n");
2352 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2354 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2355 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2356 strcpy (arg_strings
[2], arg_strings
[1]);
2362 if (strcmp (opname
, "bbsi.l") == 0)
2364 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2366 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2367 if (target_big_endian
)
2368 xg_reverse_shift_count (&arg_strings
[1]);
2372 if (strcmp (opname
, "bbci.l") == 0)
2374 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2376 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2377 if (target_big_endian
)
2378 xg_reverse_shift_count (&arg_strings
[1]);
2382 /* Don't do anything special with NOPs inside FLIX instructions. They
2383 are handled elsewhere. Real NOP instructions are always available
2384 in configurations with FLIX, so this should never be an issue but
2385 check for it anyway. */
2386 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2387 && strcmp (opname
, "nop") == 0)
2389 if (use_transform () && !has_underbar
&& density_supported
)
2390 xg_replace_opname (popname
, "nop.n");
2393 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2395 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2396 arg_strings
[0] = (char *) xmalloc (3);
2397 arg_strings
[1] = (char *) xmalloc (3);
2398 arg_strings
[2] = (char *) xmalloc (3);
2399 strcpy (arg_strings
[0], "a1");
2400 strcpy (arg_strings
[1], "a1");
2401 strcpy (arg_strings
[2], "a1");
2407 /* Recognize [RW]UR and [RWX]SR. */
2408 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2409 && (opname
[1] == 'u' || opname
[1] == 's'))
2410 || (opname
[0] == 'x' && opname
[1] == 's'))
2412 && opname
[3] == '\0')
2413 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2415 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2416 [RW]<name> if <name> is the non-default name of a user register. */
2417 if ((opname
[0] == 'r' || opname
[0] == 'w')
2418 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2419 return xtensa_translate_old_userreg_ops (popname
);
2421 /* Relax branches that don't allow comparisons against an immediate value
2422 of zero to the corresponding branches with implicit zero immediates. */
2423 if (!has_underbar
&& use_transform ())
2425 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2426 pnum_args
, arg_strings
))
2429 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2430 pnum_args
, arg_strings
))
2433 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2434 pnum_args
, arg_strings
))
2437 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2438 pnum_args
, arg_strings
))
2446 /* Functions for dealing with the Xtensa ISA. */
2448 /* Currently the assembler only allows us to use a single target per
2449 fragment. Because of this, only one operand for a given
2450 instruction may be symbolic. If there is a PC-relative operand,
2451 the last one is chosen. Otherwise, the result is the number of the
2452 last immediate operand, and if there are none of those, we fail and
2456 get_relaxable_immed (xtensa_opcode opcode
)
2458 int last_immed
= -1;
2461 if (opcode
== XTENSA_UNDEFINED
)
2464 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2465 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2467 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2469 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2471 if (last_immed
== -1
2472 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2479 static xtensa_opcode
2480 get_opcode_from_buf (const char *buf
, int slot
)
2482 static xtensa_insnbuf insnbuf
= NULL
;
2483 static xtensa_insnbuf slotbuf
= NULL
;
2484 xtensa_isa isa
= xtensa_default_isa
;
2489 insnbuf
= xtensa_insnbuf_alloc (isa
);
2490 slotbuf
= xtensa_insnbuf_alloc (isa
);
2493 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2494 fmt
= xtensa_format_decode (isa
, insnbuf
);
2495 if (fmt
== XTENSA_UNDEFINED
)
2496 return XTENSA_UNDEFINED
;
2498 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2499 return XTENSA_UNDEFINED
;
2501 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2502 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2506 #ifdef TENSILICA_DEBUG
2508 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2511 xtensa_print_insn_table (void)
2513 int num_opcodes
, num_operands
;
2514 xtensa_opcode opcode
;
2515 xtensa_isa isa
= xtensa_default_isa
;
2517 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2518 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2521 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2522 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2523 for (opn
= 0; opn
< num_operands
; opn
++)
2525 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2527 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2529 xtensa_regfile opnd_rf
=
2530 xtensa_operand_regfile (isa
, opcode
, opn
);
2531 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2533 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2534 fputs ("[lLr] ", stderr
);
2536 fputs ("i ", stderr
);
2538 fprintf (stderr
, "\n");
2544 print_vliw_insn (xtensa_insnbuf vbuf
)
2546 xtensa_isa isa
= xtensa_default_isa
;
2547 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2548 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2551 fprintf (stderr
, "format = %d\n", f
);
2553 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2555 xtensa_opcode opcode
;
2559 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2560 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2561 opname
= xtensa_opcode_name (isa
, opcode
);
2563 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2564 fprintf (stderr
, " operands = ");
2566 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2570 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2572 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2573 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2574 fprintf (stderr
, "%d ", val
);
2576 fprintf (stderr
, "\n");
2578 xtensa_insnbuf_free (isa
, sbuf
);
2581 #endif /* TENSILICA_DEBUG */
2585 is_direct_call_opcode (xtensa_opcode opcode
)
2587 xtensa_isa isa
= xtensa_default_isa
;
2588 int n
, num_operands
;
2590 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2593 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2594 for (n
= 0; n
< num_operands
; n
++)
2596 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2597 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2604 /* Convert from BFD relocation type code to slot and operand number.
2605 Returns non-zero on failure. */
2608 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2610 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2611 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2613 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2616 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2617 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2619 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2629 /* Convert from slot number to BFD relocation type code for the
2630 standard PC-relative relocations. Return BFD_RELOC_NONE on
2633 static bfd_reloc_code_real_type
2634 encode_reloc (int slot
)
2636 if (slot
< 0 || slot
> 14)
2637 return BFD_RELOC_NONE
;
2639 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2643 /* Convert from slot numbers to BFD relocation type code for the
2644 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2646 static bfd_reloc_code_real_type
2647 encode_alt_reloc (int slot
)
2649 if (slot
< 0 || slot
> 14)
2650 return BFD_RELOC_NONE
;
2652 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2657 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2660 xtensa_opcode opcode
,
2666 uint32 valbuf
= value
;
2668 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2670 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2672 as_bad_where ((char *) file
, line
,
2673 _("operand %d of '%s' has out of range value '%u'"),
2675 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2678 as_bad_where ((char *) file
, line
,
2679 _("operand %d of '%s' has invalid value '%u'"),
2681 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2686 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2692 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2695 xtensa_opcode opcode
,
2699 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2700 fmt
, slot
, slotbuf
, &val
);
2701 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2706 /* Checks for rules from xtensa-relax tables. */
2708 /* The routine xg_instruction_matches_option_term must return TRUE
2709 when a given option term is true. The meaning of all of the option
2710 terms is given interpretation by this function. This is needed when
2711 an option depends on the state of a directive, but there are no such
2712 options in use right now. */
2715 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2716 const ReqOrOption
*option
)
2718 if (strcmp (option
->option_name
, "realnop") == 0
2719 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2721 /* These conditions were evaluated statically when building the
2722 relaxation table. There's no need to reevaluate them now. */
2727 as_fatal (_("internal error: unknown option name '%s'"),
2728 option
->option_name
);
2734 xg_instruction_matches_or_options (TInsn
*insn
,
2735 const ReqOrOptionList
*or_option
)
2737 const ReqOrOption
*option
;
2738 /* Must match each of the AND terms. */
2739 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2741 if (xg_instruction_matches_option_term (insn
, option
))
2749 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2751 const ReqOption
*req_options
;
2752 /* Must match each of the AND terms. */
2753 for (req_options
= options
;
2754 req_options
!= NULL
;
2755 req_options
= req_options
->next
)
2757 /* Must match one of the OR clauses. */
2758 if (!xg_instruction_matches_or_options (insn
,
2759 req_options
->or_option_terms
))
2766 /* Return the transition rule that matches or NULL if none matches. */
2769 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2771 PreconditionList
*condition_l
;
2773 if (rule
->opcode
!= insn
->opcode
)
2776 for (condition_l
= rule
->conditions
;
2777 condition_l
!= NULL
;
2778 condition_l
= condition_l
->next
)
2782 Precondition
*cond
= condition_l
->precond
;
2787 /* The expression must be the constant. */
2788 assert (cond
->op_num
< insn
->ntok
);
2789 exp1
= &insn
->tok
[cond
->op_num
];
2790 if (expr_is_const (exp1
))
2795 if (get_expr_const (exp1
) != cond
->op_data
)
2799 if (get_expr_const (exp1
) == cond
->op_data
)
2806 else if (expr_is_register (exp1
))
2811 if (get_expr_register (exp1
) != cond
->op_data
)
2815 if (get_expr_register (exp1
) == cond
->op_data
)
2827 assert (cond
->op_num
< insn
->ntok
);
2828 assert (cond
->op_data
< insn
->ntok
);
2829 exp1
= &insn
->tok
[cond
->op_num
];
2830 exp2
= &insn
->tok
[cond
->op_data
];
2835 if (!expr_is_equal (exp1
, exp2
))
2839 if (expr_is_equal (exp1
, exp2
))
2851 if (!xg_instruction_matches_options (insn
, rule
->options
))
2859 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2861 bfd_boolean a_greater
= FALSE
;
2862 bfd_boolean b_greater
= FALSE
;
2864 ReqOptionList
*l_a
= a
->options
;
2865 ReqOptionList
*l_b
= b
->options
;
2867 /* We only care if they both are the same except for
2868 a const16 vs. an l32r. */
2870 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2872 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2873 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2874 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2876 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2878 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2880 /* This is the case we care about. */
2881 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2882 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2889 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2890 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2900 l_or_a
= l_or_a
->next
;
2901 l_or_b
= l_or_b
->next
;
2903 if (l_or_a
|| l_or_b
)
2912 /* Incomparable if the substitution was used differently in two cases. */
2913 if (a_greater
&& b_greater
)
2925 static TransitionRule
*
2926 xg_instruction_match (TInsn
*insn
)
2928 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2930 assert (insn
->opcode
< table
->num_opcodes
);
2932 /* Walk through all of the possible transitions. */
2933 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2935 TransitionRule
*rule
= l
->rule
;
2936 if (xg_instruction_matches_rule (insn
, rule
))
2943 /* Various Other Internal Functions. */
2946 is_unique_insn_expansion (TransitionRule
*r
)
2948 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2950 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2956 /* Check if there is exactly one relaxation for INSN that converts it to
2957 another instruction of equal or larger size. If so, and if TARG is
2958 non-null, go ahead and generate the relaxed instruction into TARG. If
2959 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2960 instruction, i.e., ignore relaxations that convert to an instruction of
2961 equal size. In some contexts where this function is used, only
2962 a single widening is allowed and the NARROW_ONLY argument is used to
2963 exclude cases like ADDI being "widened" to an ADDMI, which may
2964 later be relaxed to an ADDMI/ADDI pair. */
2967 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2969 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2971 TransitionRule
*match
= 0;
2973 assert (insn
->insn_type
== ITYPE_INSN
);
2974 assert (insn
->opcode
< table
->num_opcodes
);
2976 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2978 TransitionRule
*rule
= l
->rule
;
2980 if (xg_instruction_matches_rule (insn
, rule
)
2981 && is_unique_insn_expansion (rule
)
2982 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2983 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2994 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2999 /* Return the maximum number of bytes this opcode can expand to. */
3002 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3004 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3006 int max_size
= xg_get_single_size (opcode
);
3008 assert (opcode
< table
->num_opcodes
);
3010 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3012 TransitionRule
*rule
= l
->rule
;
3013 BuildInstr
*build_list
;
3018 build_list
= rule
->to_instr
;
3019 if (is_unique_insn_expansion (rule
))
3021 assert (build_list
->typ
== INSTR_INSTR
);
3022 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3025 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3027 switch (build_list
->typ
)
3030 this_size
+= xg_get_single_size (build_list
->opcode
);
3032 case INSTR_LITERAL_DEF
:
3033 case INSTR_LABEL_DEF
:
3038 if (this_size
> max_size
)
3039 max_size
= this_size
;
3045 /* Return the maximum number of literal bytes this opcode can generate. */
3048 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3050 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3054 assert (opcode
< table
->num_opcodes
);
3056 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3058 TransitionRule
*rule
= l
->rule
;
3059 BuildInstr
*build_list
;
3064 build_list
= rule
->to_instr
;
3065 if (is_unique_insn_expansion (rule
))
3067 assert (build_list
->typ
== INSTR_INSTR
);
3068 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3071 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3073 switch (build_list
->typ
)
3075 case INSTR_LITERAL_DEF
:
3076 /* Hard-coded 4-byte literal. */
3080 case INSTR_LABEL_DEF
:
3085 if (this_size
> max_size
)
3086 max_size
= this_size
;
3093 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3095 int steps_taken
= 0;
3096 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3099 assert (insn
->insn_type
== ITYPE_INSN
);
3100 assert (insn
->opcode
< table
->num_opcodes
);
3102 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3104 TransitionRule
*rule
= l
->rule
;
3106 if (xg_instruction_matches_rule (insn
, rule
))
3108 if (steps_taken
== lateral_steps
)
3118 get_special_literal_symbol (void)
3120 static symbolS
*sym
= NULL
;
3123 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3129 get_special_label_symbol (void)
3131 static symbolS
*sym
= NULL
;
3134 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3140 xg_valid_literal_expression (const expressionS
*exp
)
3158 /* This will check to see if the value can be converted into the
3159 operand type. It will return TRUE if it does not fit. */
3162 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3164 uint32 valbuf
= value
;
3165 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3171 /* Assumes: All immeds are constants. Check that all constants fit
3172 into their immeds; return FALSE if not. */
3175 xg_immeds_fit (const TInsn
*insn
)
3177 xtensa_isa isa
= xtensa_default_isa
;
3181 assert (insn
->insn_type
== ITYPE_INSN
);
3182 for (i
= 0; i
< n
; ++i
)
3184 const expressionS
*expr
= &insn
->tok
[i
];
3185 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3192 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3197 /* The symbol should have a fixup associated with it. */
3206 /* This should only be called after we have an initial
3207 estimate of the addresses. */
3210 xg_symbolic_immeds_fit (const TInsn
*insn
,
3216 xtensa_isa isa
= xtensa_default_isa
;
3224 assert (insn
->insn_type
== ITYPE_INSN
);
3226 for (i
= 0; i
< n
; ++i
)
3228 const expressionS
*expr
= &insn
->tok
[i
];
3229 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3236 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3242 /* Check for the worst case. */
3243 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3248 /* We only allow symbols for PC-relative references.
3249 If pc_frag == 0, then we don't have frag locations yet. */
3251 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3254 /* If it is a weak symbol or a symbol in a different section,
3255 it cannot be known to fit at assembly time. */
3256 if (S_IS_WEAK (expr
->X_add_symbol
)
3257 || S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3259 /* For a direct call with --no-longcalls, be optimistic and
3260 assume it will be in range. If the symbol is weak and
3261 undefined, it may remain undefined at link-time, in which
3262 case it will have a zero value and almost certainly be out
3263 of range for a direct call; thus, relax for undefined weak
3264 symbols even if longcalls is not enabled. */
3265 if (is_direct_call_opcode (insn
->opcode
)
3266 && ! pc_frag
->tc_frag_data
.use_longcalls
3267 && (! S_IS_WEAK (expr
->X_add_symbol
)
3268 || S_IS_DEFINED (expr
->X_add_symbol
)))
3274 symbolP
= expr
->X_add_symbol
;
3275 sym_frag
= symbol_get_frag (symbolP
);
3276 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3277 pc
= pc_frag
->fr_address
+ pc_offset
;
3279 /* If frag has yet to be reached on this pass, assume it
3280 will move by STRETCH just as we did. If this is not so,
3281 it will be because some frag between grows, and that will
3282 force another pass. Beware zero-length frags. There
3283 should be a faster way to do this. */
3286 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3287 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3292 new_offset
= target
;
3293 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3294 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3299 /* The symbol should have a fixup associated with it. */
3308 /* Return TRUE on success. */
3311 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3317 targ
->debug_line
= insn
->debug_line
;
3318 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3323 targ
->opcode
= bi
->opcode
;
3324 targ
->insn_type
= ITYPE_INSN
;
3325 targ
->is_specific_opcode
= FALSE
;
3327 for (; op
!= NULL
; op
= op
->next
)
3329 int op_num
= op
->op_num
;
3330 int op_data
= op
->op_data
;
3332 assert (op
->op_num
< MAX_INSN_ARGS
);
3334 if (targ
->ntok
<= op_num
)
3335 targ
->ntok
= op_num
+ 1;
3340 set_expr_const (&targ
->tok
[op_num
], op_data
);
3343 assert (op_data
< insn
->ntok
);
3344 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3347 sym
= get_special_literal_symbol ();
3348 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3351 sym
= get_special_label_symbol ();
3352 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3354 case OP_OPERAND_HI16U
:
3355 case OP_OPERAND_LOW16U
:
3356 assert (op_data
< insn
->ntok
);
3357 if (expr_is_const (&insn
->tok
[op_data
]))
3360 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3361 val
= xg_apply_userdef_op_fn (op
->typ
,
3364 targ
->tok
[op_num
].X_add_number
= val
;
3368 /* For const16 we can create relocations for these. */
3369 if (targ
->opcode
== XTENSA_UNDEFINED
3370 || (targ
->opcode
!= xtensa_const16_opcode
))
3372 assert (op_data
< insn
->ntok
);
3373 /* Need to build a O_lo16 or O_hi16. */
3374 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3375 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3377 if (op
->typ
== OP_OPERAND_HI16U
)
3378 targ
->tok
[op_num
].X_op
= O_hi16
;
3379 else if (op
->typ
== OP_OPERAND_LOW16U
)
3380 targ
->tok
[op_num
].X_op
= O_lo16
;
3387 /* currently handles:
3390 OP_OPERAND_F32MINUS */
3391 if (xg_has_userdef_op_fn (op
->typ
))
3393 assert (op_data
< insn
->ntok
);
3394 if (expr_is_const (&insn
->tok
[op_data
]))
3397 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3398 val
= xg_apply_userdef_op_fn (op
->typ
,
3401 targ
->tok
[op_num
].X_add_number
= val
;
3404 return FALSE
; /* We cannot use a relocation for this. */
3413 case INSTR_LITERAL_DEF
:
3415 targ
->opcode
= XTENSA_UNDEFINED
;
3416 targ
->insn_type
= ITYPE_LITERAL
;
3417 targ
->is_specific_opcode
= FALSE
;
3418 for (; op
!= NULL
; op
= op
->next
)
3420 int op_num
= op
->op_num
;
3421 int op_data
= op
->op_data
;
3422 assert (op
->op_num
< MAX_INSN_ARGS
);
3424 if (targ
->ntok
<= op_num
)
3425 targ
->ntok
= op_num
+ 1;
3430 assert (op_data
< insn
->ntok
);
3431 /* We can only pass resolvable literals through. */
3432 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3434 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3446 case INSTR_LABEL_DEF
:
3448 targ
->opcode
= XTENSA_UNDEFINED
;
3449 targ
->insn_type
= ITYPE_LABEL
;
3450 targ
->is_specific_opcode
= FALSE
;
3451 /* Literal with no ops is a label? */
3452 assert (op
== NULL
);
3463 /* Return TRUE on success. */
3466 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3468 for (; bi
!= NULL
; bi
= bi
->next
)
3470 TInsn
*next_insn
= istack_push_space (istack
);
3472 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3479 /* Return TRUE on valid expansion. */
3482 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3484 int stack_size
= istack
->ninsn
;
3485 int steps_taken
= 0;
3486 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3489 assert (insn
->insn_type
== ITYPE_INSN
);
3490 assert (insn
->opcode
< table
->num_opcodes
);
3492 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3494 TransitionRule
*rule
= l
->rule
;
3496 if (xg_instruction_matches_rule (insn
, rule
))
3498 if (lateral_steps
== steps_taken
)
3502 /* This is it. Expand the rule to the stack. */
3503 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3506 /* Check to see if it fits. */
3507 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3509 TInsn
*insn
= &istack
->insn
[i
];
3511 if (insn
->insn_type
== ITYPE_INSN
3512 && !tinsn_has_symbolic_operands (insn
)
3513 && !xg_immeds_fit (insn
))
3515 istack
->ninsn
= stack_size
;
3528 /* Relax the assembly instruction at least "min_steps".
3529 Return the number of steps taken.
3531 For relaxation to correctly terminate, every relaxation chain must
3532 terminate in one of two ways:
3534 1. If the chain from one instruction to the next consists entirely of
3535 single instructions, then the chain *must* handle all possible
3536 immediates without failing. It must not ever fail because an
3537 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3538 chain is one example. L32R loads 32 bits, and there cannot be an
3539 immediate larger than 32 bits, so it satisfies this condition.
3540 Single instruction relaxation chains are as defined by
3541 xg_is_single_relaxable_instruction.
3543 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3544 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3546 Strictly speaking, in most cases you can violate condition 1 and be OK
3547 -- in particular when the last two instructions have the same single
3548 size. But nevertheless, you should guarantee the above two conditions.
3550 We could fix this so that single-instruction expansions correctly
3551 terminate when they can't handle the range, but the error messages are
3552 worse, and it actually turns out that in every case but one (18-bit wide
3553 branches), you need a multi-instruction expansion to get the full range
3554 anyway. And because 18-bit branches are handled identically to 15-bit
3555 branches, there isn't any point in changing it. */
3558 xg_assembly_relax (IStack
*istack
,
3561 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3562 offsetT pc_offset
, /* offset in fragment */
3563 int min_steps
, /* minimum conversion steps */
3564 long stretch
) /* number of bytes stretched so far */
3566 int steps_taken
= 0;
3568 /* Some of its immeds don't fit. Try to build a relaxed version.
3569 This may go through a couple of stages of single instruction
3570 transformations before we get there. */
3572 TInsn single_target
;
3574 int lateral_steps
= 0;
3575 int istack_size
= istack
->ninsn
;
3577 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3578 && steps_taken
>= min_steps
)
3580 istack_push (istack
, insn
);
3583 current_insn
= *insn
;
3585 /* Walk through all of the single instruction expansions. */
3586 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3589 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3592 if (steps_taken
>= min_steps
)
3594 istack_push (istack
, &single_target
);
3598 current_insn
= single_target
;
3601 /* Now check for a multi-instruction expansion. */
3602 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3604 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3607 if (steps_taken
>= min_steps
)
3609 istack_push (istack
, ¤t_insn
);
3614 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3616 if (steps_taken
>= min_steps
)
3620 istack
->ninsn
= istack_size
;
3623 /* It's not going to work -- use the original. */
3624 istack_push (istack
, insn
);
3630 xg_finish_frag (char *last_insn
,
3631 enum xtensa_relax_statesE frag_state
,
3632 enum xtensa_relax_statesE slot0_state
,
3634 bfd_boolean is_insn
)
3636 /* Finish off this fragment so that it has at LEAST the desired
3637 max_growth. If it doesn't fit in this fragment, close this one
3638 and start a new one. In either case, return a pointer to the
3639 beginning of the growth area. */
3643 frag_grow (max_growth
);
3644 old_frag
= frag_now
;
3646 frag_now
->fr_opcode
= last_insn
;
3648 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3650 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3651 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3653 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3654 xtensa_set_frag_assembly_state (frag_now
);
3656 /* Just to make sure that we did not split it up. */
3657 assert (old_frag
->fr_next
== frag_now
);
3661 /* Return TRUE if the target frag is one of the next non-empty frags. */
3664 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3669 for (; fragP
; fragP
= fragP
->fr_next
)
3671 if (fragP
== target
)
3673 if (fragP
->fr_fix
!= 0)
3675 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3677 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3678 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3680 if (fragP
->fr_type
== rs_space
)
3688 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3690 xtensa_isa isa
= xtensa_default_isa
;
3692 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3697 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3698 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3701 for (i
= 0; i
< num_ops
; i
++)
3703 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3709 if (target_op
== -1)
3712 if (insn
->ntok
<= target_op
)
3715 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3718 sym
= insn
->tok
[target_op
].X_add_symbol
;
3722 if (insn
->tok
[target_op
].X_add_number
!= 0)
3725 target_frag
= symbol_get_frag (sym
);
3726 if (target_frag
== NULL
)
3729 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3730 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3738 xg_add_branch_and_loop_targets (TInsn
*insn
)
3740 xtensa_isa isa
= xtensa_default_isa
;
3741 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3743 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3746 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3747 && insn
->tok
[i
].X_op
== O_symbol
)
3748 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3752 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3753 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3757 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3759 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3760 && insn
->tok
[i
].X_op
== O_symbol
)
3762 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3763 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3764 if (S_IS_DEFINED (sym
))
3765 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3772 /* Return FALSE if no error. */
3775 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3780 switch (instr_spec
->typ
)
3783 new_insn
->insn_type
= ITYPE_INSN
;
3784 new_insn
->opcode
= instr_spec
->opcode
;
3786 case INSTR_LITERAL_DEF
:
3787 new_insn
->insn_type
= ITYPE_LITERAL
;
3788 new_insn
->opcode
= XTENSA_UNDEFINED
;
3790 case INSTR_LABEL_DEF
:
3793 new_insn
->is_specific_opcode
= FALSE
;
3794 new_insn
->debug_line
= old_insn
->debug_line
;
3795 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3797 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3800 const expressionS
*src_exp
;
3806 /* The expression must be the constant. */
3807 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3808 exp
= &new_insn
->tok
[b_op
->op_num
];
3809 set_expr_const (exp
, b_op
->op_data
);
3813 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3814 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3815 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3816 exp
= &new_insn
->tok
[b_op
->op_num
];
3817 copy_expr (exp
, src_exp
);
3822 as_bad (_("can't handle generation of literal/labels yet"));
3826 as_bad (_("can't handle undefined OP TYPE"));
3831 new_insn
->ntok
= num_ops
;
3836 /* Return TRUE if it was simplified. */
3839 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3841 TransitionRule
*rule
;
3842 BuildInstr
*insn_spec
;
3844 if (old_insn
->is_specific_opcode
|| !density_supported
)
3847 rule
= xg_instruction_match (old_insn
);
3851 insn_spec
= rule
->to_instr
;
3852 /* There should only be one. */
3853 assert (insn_spec
!= NULL
);
3854 assert (insn_spec
->next
== NULL
);
3855 if (insn_spec
->next
!= NULL
)
3858 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3864 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3865 l32i.n. (2) Check the number of operands. (3) Place the instruction
3866 tokens into the stack or relax it and place multiple
3867 instructions/literals onto the stack. Return FALSE if no error. */
3870 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3874 bfd_boolean do_expand
;
3876 tinsn_init (&new_insn
);
3878 /* Narrow it if we can. xg_simplify_insn now does all the
3879 appropriate checking (e.g., for the density option). */
3880 if (xg_simplify_insn (orig_insn
, &new_insn
))
3881 orig_insn
= &new_insn
;
3883 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3885 if (orig_insn
->ntok
< noperands
)
3887 as_bad (_("found %d operands for '%s': Expected %d"),
3889 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3893 if (orig_insn
->ntok
> noperands
)
3894 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3896 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3899 /* If there are not enough operands, we will assert above. If there
3900 are too many, just cut out the extras here. */
3901 orig_insn
->ntok
= noperands
;
3903 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3906 /* Special case for extui opcode which has constraints not handled
3907 by the ordinary operand encoding checks. The number of operands
3908 and related syntax issues have already been checked. */
3909 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3911 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3912 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3913 if (shiftimm
+ maskimm
> 32)
3915 as_bad (_("immediate operands sum to greater than 32"));
3920 /* If the instruction will definitely need to be relaxed, it is better
3921 to expand it now for better scheduling. Decide whether to expand
3923 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3925 /* Calls should be expanded to longcalls only in the backend relaxation
3926 so that the assembly scheduler will keep the L32R/CALLX instructions
3928 if (is_direct_call_opcode (orig_insn
->opcode
))
3931 if (tinsn_has_symbolic_operands (orig_insn
))
3933 /* The values of symbolic operands are not known yet, so only expand
3934 now if an operand is "complex" (e.g., difference of symbols) and
3935 will have to be stored as a literal regardless of the value. */
3936 if (!tinsn_has_complex_operands (orig_insn
))
3939 else if (xg_immeds_fit (orig_insn
))
3943 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3945 istack_push (istack
, orig_insn
);
3951 /* Return TRUE if the section flags are marked linkonce
3952 or the name is .gnu.linkonce.*. */
3954 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3957 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3959 flagword flags
, link_once_flags
;
3961 flags
= bfd_get_section_flags (abfd
, sec
);
3962 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3964 /* Flags might not be set yet. */
3965 if (!link_once_flags
3966 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3967 link_once_flags
= SEC_LINK_ONCE
;
3969 return (link_once_flags
!= 0);
3974 xtensa_add_literal_sym (symbolS
*sym
)
3978 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3980 l
->next
= literal_syms
;
3986 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3988 static int lit_num
= 0;
3989 static char name
[256];
3992 sprintf (name
, ".L_lit_sym%d", lit_num
);
3994 /* Create a local symbol. If it is in a linkonce section, we have to
3995 be careful to make sure that if it is used in a relocation that the
3996 symbol will be in the output file. */
3997 if (get_is_linkonce_section (stdoutput
, sec
))
3999 symbolP
= symbol_new (name
, sec
, 0, frag
);
4000 S_CLEAR_EXTERNAL (symbolP
);
4001 /* symbolP->local = 1; */
4004 symbolP
= symbol_new (name
, sec
, 0, frag
);
4006 xtensa_add_literal_sym (symbolP
);
4013 /* Currently all literals that are generated here are 32-bit L32R targets. */
4016 xg_assemble_literal (/* const */ TInsn
*insn
)
4019 symbolS
*lit_sym
= NULL
;
4020 bfd_reloc_code_real_type reloc
;
4021 bfd_boolean pcrel
= FALSE
;
4024 /* size = 4 for L32R. It could easily be larger when we move to
4025 larger constants. Add a parameter later. */
4026 offsetT litsize
= 4;
4027 offsetT litalign
= 2; /* 2^2 = 4 */
4028 expressionS saved_loc
;
4029 expressionS
* emit_val
;
4031 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4033 assert (insn
->insn_type
== ITYPE_LITERAL
);
4034 assert (insn
->ntok
== 1); /* must be only one token here */
4036 xtensa_switch_to_literal_fragment (&state
);
4038 emit_val
= &insn
->tok
[0];
4039 if (emit_val
->X_op
== O_big
)
4041 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4044 /* This happens when someone writes a "movi a2, big_number". */
4045 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4046 _("invalid immediate"));
4047 xtensa_restore_emit_state (&state
);
4052 /* Force a 4-byte align here. Note that this opens a new frag, so all
4053 literals done with this function have a frag to themselves. That's
4054 important for the way text section literals work. */
4055 frag_align (litalign
, 0, 0);
4056 record_alignment (now_seg
, litalign
);
4058 switch (emit_val
->X_op
)
4064 p
= frag_more (litsize
);
4065 xtensa_set_frag_assembly_state (frag_now
);
4066 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4067 if (emit_val
->X_add_symbol
)
4068 emit_val
->X_op
= O_symbol
;
4070 emit_val
->X_op
= O_constant
;
4071 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4072 litsize
, emit_val
, pcrel
, reloc
);
4076 emit_expr (emit_val
, litsize
);
4080 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4081 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4082 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4083 lit_sym
= frag_now
->fr_symbol
;
4086 xtensa_restore_emit_state (&state
);
4092 xg_assemble_literal_space (/* const */ int size
, int slot
)
4095 /* We might have to do something about this alignment. It only
4096 takes effect if something is placed here. */
4097 offsetT litalign
= 2; /* 2^2 = 4 */
4098 fragS
*lit_saved_frag
;
4100 assert (size
% 4 == 0);
4102 xtensa_switch_to_literal_fragment (&state
);
4104 /* Force a 4-byte align here. */
4105 frag_align (litalign
, 0, 0);
4106 record_alignment (now_seg
, litalign
);
4110 lit_saved_frag
= frag_now
;
4111 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4112 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4113 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4116 xtensa_restore_emit_state (&state
);
4117 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4121 /* Put in a fixup record based on the opcode.
4122 Return TRUE on success. */
4125 xg_add_opcode_fix (TInsn
*tinsn
,
4133 xtensa_opcode opcode
= tinsn
->opcode
;
4134 bfd_reloc_code_real_type reloc
;
4135 reloc_howto_type
*howto
;
4139 reloc
= BFD_RELOC_NONE
;
4141 /* First try the special cases for "alternate" relocs. */
4142 if (opcode
== xtensa_l32r_opcode
)
4144 if (fragP
->tc_frag_data
.use_absolute_literals
)
4145 reloc
= encode_alt_reloc (slot
);
4147 else if (opcode
== xtensa_const16_opcode
)
4149 if (expr
->X_op
== O_lo16
)
4151 reloc
= encode_reloc (slot
);
4152 expr
->X_op
= O_symbol
;
4154 else if (expr
->X_op
== O_hi16
)
4156 reloc
= encode_alt_reloc (slot
);
4157 expr
->X_op
= O_symbol
;
4161 if (opnum
!= get_relaxable_immed (opcode
))
4163 as_bad (_("invalid relocation for operand %i of '%s'"),
4164 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4168 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4169 into the symbol table where the generic portions of the assembler
4170 won't know what to do with them. */
4171 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4173 as_bad (_("invalid expression for operand %i of '%s'"),
4174 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4178 /* Next try the generic relocs. */
4179 if (reloc
== BFD_RELOC_NONE
)
4180 reloc
= encode_reloc (slot
);
4181 if (reloc
== BFD_RELOC_NONE
)
4183 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4187 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4190 as_bad (_("undefined symbol for opcode \"%s\""),
4191 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4195 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4196 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4197 howto
->pc_relative
, reloc
);
4198 the_fix
->fx_no_overflow
= 1;
4199 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4200 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4201 the_fix
->tc_fix_data
.slot
= slot
;
4208 xg_emit_insn_to_buf (TInsn
*tinsn
,
4212 bfd_boolean build_fix
)
4214 static xtensa_insnbuf insnbuf
= NULL
;
4215 bfd_boolean has_symbolic_immed
= FALSE
;
4216 bfd_boolean ok
= TRUE
;
4219 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4221 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4222 if (has_symbolic_immed
&& build_fix
)
4225 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4226 int slot
= xg_get_single_slot (tinsn
->opcode
);
4227 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4228 expressionS
*exp
= &tinsn
->tok
[opnum
];
4230 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4233 fragP
->tc_frag_data
.is_insn
= TRUE
;
4234 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4235 (unsigned char *) buf
, 0);
4241 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4243 symbolS
*sym
= get_special_literal_symbol ();
4247 assert (insn
->insn_type
== ITYPE_INSN
);
4248 for (i
= 0; i
< insn
->ntok
; i
++)
4249 if (insn
->tok
[i
].X_add_symbol
== sym
)
4250 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4256 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4258 symbolS
*sym
= get_special_label_symbol ();
4260 for (i
= 0; i
< insn
->ntok
; i
++)
4261 if (insn
->tok
[i
].X_add_symbol
== sym
)
4262 insn
->tok
[i
].X_add_symbol
= label_sym
;
4267 /* Return TRUE if the instruction can write to the specified
4268 integer register. */
4271 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4275 xtensa_isa isa
= xtensa_default_isa
;
4277 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4279 for (i
= 0; i
< num_ops
; i
++)
4282 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4283 if ((inout
== 'o' || inout
== 'm')
4284 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4286 xtensa_regfile opnd_rf
=
4287 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4288 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4290 if ((insn
->tok
[i
].X_op
== O_register
)
4291 && (insn
->tok
[i
].X_add_number
== regnum
))
4301 is_bad_loopend_opcode (const TInsn
*tinsn
)
4303 xtensa_opcode opcode
= tinsn
->opcode
;
4305 if (opcode
== XTENSA_UNDEFINED
)
4308 if (opcode
== xtensa_call0_opcode
4309 || opcode
== xtensa_callx0_opcode
4310 || opcode
== xtensa_call4_opcode
4311 || opcode
== xtensa_callx4_opcode
4312 || opcode
== xtensa_call8_opcode
4313 || opcode
== xtensa_callx8_opcode
4314 || opcode
== xtensa_call12_opcode
4315 || opcode
== xtensa_callx12_opcode
4316 || opcode
== xtensa_isync_opcode
4317 || opcode
== xtensa_ret_opcode
4318 || opcode
== xtensa_ret_n_opcode
4319 || opcode
== xtensa_retw_opcode
4320 || opcode
== xtensa_retw_n_opcode
4321 || opcode
== xtensa_waiti_opcode
4322 || opcode
== xtensa_rsr_lcount_opcode
)
4329 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4330 This allows the debugger to add unaligned labels.
4331 Also, the assembler generates stabs labels that need
4332 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4335 is_unaligned_label (symbolS
*sym
)
4337 const char *name
= S_GET_NAME (sym
);
4338 static size_t fake_size
= 0;
4342 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4345 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4347 fake_size
= strlen (FAKE_LABEL_NAME
);
4350 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4351 && (name
[fake_size
] == 'F'
4352 || name
[fake_size
] == 'L'
4353 || (name
[fake_size
] == 'e'
4354 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4362 next_non_empty_frag (const fragS
*fragP
)
4364 fragS
*next_fragP
= fragP
->fr_next
;
4366 /* Sometimes an empty will end up here due storage allocation issues.
4367 So we have to skip until we find something legit. */
4368 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4369 next_fragP
= next_fragP
->fr_next
;
4371 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4379 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4381 xtensa_opcode out_opcode
;
4382 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4384 if (next_fragP
== NULL
)
4387 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4388 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4390 *opcode
= out_opcode
;
4398 frag_format_size (const fragS
*fragP
)
4400 static xtensa_insnbuf insnbuf
= NULL
;
4401 xtensa_isa isa
= xtensa_default_isa
;
4406 insnbuf
= xtensa_insnbuf_alloc (isa
);
4409 return XTENSA_UNDEFINED
;
4411 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4412 (unsigned char *) fragP
->fr_literal
, 0);
4414 fmt
= xtensa_format_decode (isa
, insnbuf
);
4415 if (fmt
== XTENSA_UNDEFINED
)
4416 return XTENSA_UNDEFINED
;
4417 fmt_size
= xtensa_format_length (isa
, fmt
);
4419 /* If the next format won't be changing due to relaxation, just
4420 return the length of the first format. */
4421 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4424 /* If during relaxation we have to pull an instruction out of a
4425 multi-slot instruction, we will return the more conservative
4426 number. This works because alignment on bigger instructions
4427 is more restrictive than alignment on smaller instructions.
4428 This is more conservative than we would like, but it happens
4431 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4434 /* If we aren't doing one of our own relaxations or it isn't
4435 slot-based, then the insn size won't change. */
4436 if (fragP
->fr_type
!= rs_machine_dependent
)
4438 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4441 /* If an instruction is about to grow, return the longer size. */
4442 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4443 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4444 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4446 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4447 instruction in the relaxed version is of length 3. (The case
4448 where we have to pull the instruction out of a FLIX bundle
4449 is handled conservatively above.) However, frags with opcodes
4450 that are expanding to wide branches end up having formats that
4451 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4452 we can't tell directly what format the relaxer picked. This
4453 is a wart in the design of the relaxer that should someday be
4454 fixed, but would require major changes, or at least should
4455 be accompanied by major changes to make use of that data.
4457 In any event, we can tell that we are expanding from a single-slot
4458 three-byte format to a wider one with the logic below. */
4460 if (fmt_size
<= 3 && fragP
->tc_frag_data
.text_expansion
[0] != 3)
4461 return 3 + fragP
->tc_frag_data
.text_expansion
[0];
4466 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4467 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4474 next_frag_format_size (const fragS
*fragP
)
4476 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4477 return frag_format_size (next_fragP
);
4481 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4482 required two-byte instructions to be treated as three-byte instructions
4483 for loop instruction alignment. This restriction was removed beginning
4484 with Xtensa LX. Now the only requirement on loop instruction alignment
4485 is that the first instruction of the loop must appear at an address that
4486 does not cross a fetch boundary. */
4489 get_loop_align_size (int insn_size
)
4491 if (insn_size
== XTENSA_UNDEFINED
)
4492 return xtensa_fetch_width
;
4494 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4501 /* If the next legit fragment is an end-of-loop marker,
4502 switch its state so it will instantiate a NOP. */
4505 update_next_frag_state (fragS
*fragP
)
4507 fragS
*next_fragP
= fragP
->fr_next
;
4508 fragS
*new_target
= NULL
;
4512 /* We are guaranteed there will be one of these... */
4513 while (!(next_fragP
->fr_type
== rs_machine_dependent
4514 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4515 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4516 next_fragP
= next_fragP
->fr_next
;
4518 assert (next_fragP
->fr_type
== rs_machine_dependent
4519 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4520 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4522 /* ...and one of these. */
4523 new_target
= next_fragP
->fr_next
;
4524 while (!(new_target
->fr_type
== rs_machine_dependent
4525 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4526 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4527 new_target
= new_target
->fr_next
;
4529 assert (new_target
->fr_type
== rs_machine_dependent
4530 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4531 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4534 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4536 if (next_fragP
->fr_type
== rs_machine_dependent
4537 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4539 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4543 next_fragP
= next_fragP
->fr_next
;
4549 next_frag_is_branch_target (const fragS
*fragP
)
4551 /* Sometimes an empty will end up here due to storage allocation issues,
4552 so we have to skip until we find something legit. */
4553 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4555 if (fragP
->tc_frag_data
.is_branch_target
)
4557 if (fragP
->fr_fix
!= 0)
4565 next_frag_is_loop_target (const fragS
*fragP
)
4567 /* Sometimes an empty will end up here due storage allocation issues.
4568 So we have to skip until we find something legit. */
4569 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4571 if (fragP
->tc_frag_data
.is_loop_target
)
4573 if (fragP
->fr_fix
!= 0)
4581 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4583 const fragS
*next_fragp
= fragp
->fr_next
;
4584 xtensa_opcode next_opcode
;
4586 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4589 /* Sometimes an empty will end up here due to storage allocation issues,
4590 so we have to skip until we find something legit. */
4591 while (next_fragp
->fr_fix
== 0)
4592 next_fragp
= next_fragp
->fr_next
;
4594 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4597 /* There is some implicit knowledge encoded in here.
4598 The LOOP instructions that are NOT RELAX_IMMED have
4599 been relaxed. Note that we can assume that the LOOP
4600 instruction is in slot 0 because loops aren't bundleable. */
4601 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4602 return get_expanded_loop_offset (next_opcode
);
4608 /* Mark a location where we can later insert literal frags. Update
4609 the section's literal_pool_loc, so subsequent literals can be
4610 placed nearest to their use. */
4613 xtensa_mark_literal_pool_location (void)
4615 /* Any labels pointing to the current location need
4616 to be adjusted to after the literal pool. */
4618 fragS
*pool_location
;
4620 if (use_literal_section
)
4623 /* We stash info in these frags so we can later move the literal's
4624 fixes into this frchain's fix list. */
4625 pool_location
= frag_now
;
4626 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4627 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4628 frag_variant (rs_machine_dependent
, 0, 0,
4629 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4630 xtensa_set_frag_assembly_state (frag_now
);
4631 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4632 frag_variant (rs_machine_dependent
, 0, 0,
4633 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4634 xtensa_set_frag_assembly_state (frag_now
);
4636 /* Now put a frag into the literal pool that points to this location. */
4637 set_literal_pool_location (now_seg
, pool_location
);
4638 xtensa_switch_to_non_abs_literal_fragment (&s
);
4639 frag_align (2, 0, 0);
4640 record_alignment (now_seg
, 2);
4642 /* Close whatever frag is there. */
4643 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4644 xtensa_set_frag_assembly_state (frag_now
);
4645 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4646 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4647 xtensa_restore_emit_state (&s
);
4648 xtensa_set_frag_assembly_state (frag_now
);
4652 /* Build a nop of the correct size into tinsn. */
4655 build_nop (TInsn
*tinsn
, int size
)
4661 tinsn
->opcode
= xtensa_nop_n_opcode
;
4663 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4664 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4668 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4670 tinsn
->opcode
= xtensa_or_opcode
;
4671 set_expr_const (&tinsn
->tok
[0], 1);
4672 set_expr_const (&tinsn
->tok
[1], 1);
4673 set_expr_const (&tinsn
->tok
[2], 1);
4677 tinsn
->opcode
= xtensa_nop_opcode
;
4679 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4684 /* Assemble a NOP of the requested size in the buffer. User must have
4685 allocated "buf" with at least "size" bytes. */
4688 assemble_nop (int size
, char *buf
)
4690 static xtensa_insnbuf insnbuf
= NULL
;
4693 build_nop (&tinsn
, size
);
4696 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4698 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4699 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4700 (unsigned char *) buf
, 0);
4704 /* Return the number of bytes for the offset of the expanded loop
4705 instruction. This should be incorporated into the relaxation
4706 specification but is hard-coded here. This is used to auto-align
4707 the loop instruction. It is invalid to call this function if the
4708 configuration does not have loops or if the opcode is not a loop
4712 get_expanded_loop_offset (xtensa_opcode opcode
)
4714 /* This is the OFFSET of the loop instruction in the expanded loop.
4715 This MUST correspond directly to the specification of the loop
4716 expansion. It will be validated on fragment conversion. */
4717 assert (opcode
!= XTENSA_UNDEFINED
);
4718 if (opcode
== xtensa_loop_opcode
)
4720 if (opcode
== xtensa_loopnez_opcode
)
4722 if (opcode
== xtensa_loopgtz_opcode
)
4724 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4730 get_literal_pool_location (segT seg
)
4732 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4737 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4739 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4743 /* Set frag assembly state should be called when a new frag is
4744 opened and after a frag has been closed. */
4747 xtensa_set_frag_assembly_state (fragS
*fragP
)
4749 if (!density_supported
)
4750 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4752 /* This function is called from subsegs_finish, which is called
4753 after xtensa_end, so we can't use "use_transform" or
4754 "use_schedule" here. */
4755 if (!directive_state
[directive_transform
])
4756 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4757 if (directive_state
[directive_longcalls
])
4758 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4759 fragP
->tc_frag_data
.use_absolute_literals
=
4760 directive_state
[directive_absolute_literals
];
4761 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4766 relaxable_section (asection
*sec
)
4768 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4769 && strcmp (sec
->name
, ".eh_frame") != 0);
4774 xtensa_mark_frags_for_org (void)
4778 /* Walk over each fragment of all of the current segments. If we find
4779 a .org frag in any of the segments, mark all frags prior to it as
4780 "no transform", which will prevent linker optimizations from messing
4781 up the .org distance. This should be done after
4782 xtensa_find_unmarked_state_frags, because we don't want to worry here
4783 about that function trashing the data we save here. */
4785 for (seclist
= &stdoutput
->sections
;
4786 seclist
&& *seclist
;
4787 seclist
= &(*seclist
)->next
)
4789 segT sec
= *seclist
;
4790 segment_info_type
*seginfo
;
4793 flags
= bfd_get_section_flags (stdoutput
, sec
);
4794 if (flags
& SEC_DEBUGGING
)
4796 if (!(flags
& SEC_ALLOC
))
4799 seginfo
= seg_info (sec
);
4800 if (seginfo
&& seginfo
->frchainP
)
4802 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4803 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4804 fragP
= fragP
->fr_next
)
4806 /* cvt_frag_to_fill has changed the fr_type of org frags to
4807 rs_fill, so use the value as cached in rs_subtype here. */
4808 if (fragP
->fr_subtype
== RELAX_ORG
)
4810 while (last_fragP
!= fragP
->fr_next
)
4812 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4813 last_fragP
= last_fragP
->fr_next
;
4823 xtensa_find_unmarked_state_frags (void)
4827 /* Walk over each fragment of all of the current segments. For each
4828 unmarked fragment, mark it with the same info as the previous
4830 for (seclist
= &stdoutput
->sections
;
4831 seclist
&& *seclist
;
4832 seclist
= &(*seclist
)->next
)
4834 segT sec
= *seclist
;
4835 segment_info_type
*seginfo
;
4838 flags
= bfd_get_section_flags (stdoutput
, sec
);
4839 if (flags
& SEC_DEBUGGING
)
4841 if (!(flags
& SEC_ALLOC
))
4844 seginfo
= seg_info (sec
);
4845 if (seginfo
&& seginfo
->frchainP
)
4847 fragS
*last_fragP
= 0;
4848 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4849 fragP
= fragP
->fr_next
)
4851 if (fragP
->fr_fix
!= 0
4852 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4854 if (last_fragP
== 0)
4856 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4857 _("assembly state not set for first frag in section %s"),
4862 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4863 fragP
->tc_frag_data
.is_no_density
=
4864 last_fragP
->tc_frag_data
.is_no_density
;
4865 fragP
->tc_frag_data
.is_no_transform
=
4866 last_fragP
->tc_frag_data
.is_no_transform
;
4867 fragP
->tc_frag_data
.use_longcalls
=
4868 last_fragP
->tc_frag_data
.use_longcalls
;
4869 fragP
->tc_frag_data
.use_absolute_literals
=
4870 last_fragP
->tc_frag_data
.use_absolute_literals
;
4873 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4882 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4884 void *unused ATTRIBUTE_UNUSED
)
4886 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4887 segment_info_type
*seginfo
= seg_info (sec
);
4888 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4890 if (flags
& SEC_CODE
)
4892 xtensa_isa isa
= xtensa_default_isa
;
4893 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4894 while (frag
!= NULL
)
4896 if (frag
->tc_frag_data
.is_branch_target
)
4899 addressT branch_align
, frag_addr
;
4902 xtensa_insnbuf_from_chars
4903 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4904 fmt
= xtensa_format_decode (isa
, insnbuf
);
4905 op_size
= xtensa_format_length (isa
, fmt
);
4906 branch_align
= 1 << branch_align_power (sec
);
4907 frag_addr
= frag
->fr_address
% branch_align
;
4908 if (frag_addr
+ op_size
> branch_align
)
4909 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4910 _("unaligned branch target: %d bytes at 0x%lx"),
4911 op_size
, (long) frag
->fr_address
);
4913 frag
= frag
->fr_next
;
4915 xtensa_insnbuf_free (isa
, insnbuf
);
4921 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4923 void *unused ATTRIBUTE_UNUSED
)
4925 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4926 segment_info_type
*seginfo
= seg_info (sec
);
4927 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4928 xtensa_isa isa
= xtensa_default_isa
;
4930 if (flags
& SEC_CODE
)
4932 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4933 while (frag
!= NULL
)
4935 if (frag
->tc_frag_data
.is_first_loop_insn
)
4941 xtensa_insnbuf_from_chars
4942 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4943 fmt
= xtensa_format_decode (isa
, insnbuf
);
4944 op_size
= xtensa_format_length (isa
, fmt
);
4945 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4947 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4948 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4949 _("unaligned loop: %d bytes at 0x%lx"),
4950 op_size
, (long) frag
->fr_address
);
4952 frag
= frag
->fr_next
;
4954 xtensa_insnbuf_free (isa
, insnbuf
);
4960 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4962 xtensa_isa isa
= xtensa_default_isa
;
4963 static xtensa_insnbuf insnbuf
= NULL
;
4964 static xtensa_insnbuf slotbuf
= NULL
;
4967 bfd_boolean alt_reloc
;
4968 xtensa_opcode opcode
;
4969 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4971 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4973 as_fatal (_("unexpected fix"));
4977 insnbuf
= xtensa_insnbuf_alloc (isa
);
4978 slotbuf
= xtensa_insnbuf_alloc (isa
);
4981 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4982 fmt
= xtensa_format_decode (isa
, insnbuf
);
4983 if (fmt
== XTENSA_UNDEFINED
)
4984 as_fatal (_("undecodable fix"));
4985 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4986 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4987 if (opcode
== XTENSA_UNDEFINED
)
4988 as_fatal (_("undecodable fix"));
4990 /* CONST16 immediates are not PC-relative, despite the fact that we
4991 reuse the normal PC-relative operand relocations for the low part
4992 of a CONST16 operand. */
4993 if (opcode
== xtensa_const16_opcode
)
4996 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4997 get_relaxable_immed (opcode
), val
,
4998 fixP
->fx_file
, fixP
->fx_line
);
5000 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5001 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5007 /* External Functions and Other GAS Hooks. */
5010 xtensa_target_format (void)
5012 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5017 xtensa_file_arch_init (bfd
*abfd
)
5019 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5024 md_number_to_chars (char *buf
, valueT val
, int n
)
5026 if (target_big_endian
)
5027 number_to_chars_bigendian (buf
, val
, n
);
5029 number_to_chars_littleendian (buf
, val
, n
);
5033 /* This function is called once, at assembler startup time. It should
5034 set up all the tables, etc. that the MD part of the assembler will
5040 segT current_section
= now_seg
;
5041 int current_subsec
= now_subseg
;
5044 xtensa_default_isa
= xtensa_isa_init (0, 0);
5045 isa
= xtensa_default_isa
;
5049 /* Set up the literal sections. */
5050 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5052 subseg_set (current_section
, current_subsec
);
5054 xg_init_vinsn (&cur_vinsn
);
5056 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5057 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5058 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5059 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5060 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5061 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5062 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5063 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5064 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5065 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5066 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5067 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5068 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5069 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5070 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5071 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5072 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5073 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5074 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5075 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5076 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5077 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5078 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5079 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5080 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5081 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5082 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5083 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5084 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5085 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5087 init_op_placement_info_table ();
5089 /* Set up the assembly state. */
5090 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5091 xtensa_set_frag_assembly_state (frag_now
);
5095 /* TC_INIT_FIX_DATA hook */
5098 xtensa_init_fix_data (fixS
*x
)
5100 x
->tc_fix_data
.slot
= 0;
5101 x
->tc_fix_data
.X_add_symbol
= NULL
;
5102 x
->tc_fix_data
.X_add_number
= 0;
5106 /* tc_frob_label hook */
5109 xtensa_frob_label (symbolS
*sym
)
5113 if (cur_vinsn
.inside_bundle
)
5115 as_bad (_("labels are not valid inside bundles"));
5119 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5121 /* Since the label was already attached to a frag associated with the
5122 previous basic block, it now needs to be reset to the current frag. */
5123 symbol_set_frag (sym
, frag_now
);
5124 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5126 if (generating_literals
)
5127 xtensa_add_literal_sym (sym
);
5129 xtensa_add_insn_label (sym
);
5131 if (symbol_get_tc (sym
)->is_loop_target
)
5133 if ((get_last_insn_flags (now_seg
, now_subseg
)
5134 & FLAG_IS_BAD_LOOPEND
) != 0)
5135 as_bad (_("invalid last instruction for a zero-overhead loop"));
5137 xtensa_set_frag_assembly_state (frag_now
);
5138 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5139 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5141 xtensa_set_frag_assembly_state (frag_now
);
5142 xtensa_move_labels (frag_now
, 0);
5145 /* No target aligning in the absolute section. */
5146 if (now_seg
!= absolute_section
5147 && do_align_targets ()
5148 && !is_unaligned_label (sym
)
5149 && !generating_literals
)
5151 xtensa_set_frag_assembly_state (frag_now
);
5153 frag_var (rs_machine_dependent
,
5155 RELAX_DESIRE_ALIGN_IF_TARGET
,
5156 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5157 xtensa_set_frag_assembly_state (frag_now
);
5158 xtensa_move_labels (frag_now
, 0);
5161 /* We need to mark the following properties even if we aren't aligning. */
5163 /* If the label is already known to be a branch target, i.e., a
5164 forward branch, mark the frag accordingly. Backward branches
5165 are handled by xg_add_branch_and_loop_targets. */
5166 if (symbol_get_tc (sym
)->is_branch_target
)
5167 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5169 /* Loops only go forward, so they can be identified here. */
5170 if (symbol_get_tc (sym
)->is_loop_target
)
5171 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5173 dwarf2_emit_label (sym
);
5177 /* tc_unrecognized_line hook */
5180 xtensa_unrecognized_line (int ch
)
5185 if (cur_vinsn
.inside_bundle
== 0)
5187 /* PR8110: Cannot emit line number info inside a FLIX bundle
5188 when using --gstabs. Temporarily disable debug info. */
5189 generate_lineno_debug ();
5190 if (debug_type
== DEBUG_STABS
)
5192 xt_saved_debug_type
= debug_type
;
5193 debug_type
= DEBUG_NONE
;
5196 cur_vinsn
.inside_bundle
= 1;
5200 as_bad (_("extra opening brace"));
5206 if (cur_vinsn
.inside_bundle
)
5207 finish_vinsn (&cur_vinsn
);
5210 as_bad (_("extra closing brace"));
5215 as_bad (_("syntax error"));
5222 /* md_flush_pending_output hook */
5225 xtensa_flush_pending_output (void)
5227 /* This line fixes a bug where automatically generated gstabs info
5228 separates a function label from its entry instruction, ending up
5229 with the literal position between the function label and the entry
5230 instruction and crashing code. It only happens with --gstabs and
5231 --text-section-literals, and when several other obscure relaxation
5232 conditions are met. */
5233 if (outputting_stabs_line_debug
)
5236 if (cur_vinsn
.inside_bundle
)
5237 as_bad (_("missing closing brace"));
5239 /* If there is a non-zero instruction fragment, close it. */
5240 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5242 frag_wane (frag_now
);
5244 xtensa_set_frag_assembly_state (frag_now
);
5246 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5248 xtensa_clear_insn_labels ();
5252 /* We had an error while parsing an instruction. The string might look
5253 like this: "insn arg1, arg2 }". If so, we need to see the closing
5254 brace and reset some fields. Otherwise, the vinsn never gets closed
5255 and the num_slots field will grow past the end of the array of slots,
5256 and bad things happen. */
5259 error_reset_cur_vinsn (void)
5261 if (cur_vinsn
.inside_bundle
)
5263 if (*input_line_pointer
== '}'
5264 || *(input_line_pointer
- 1) == '}'
5265 || *(input_line_pointer
- 2) == '}')
5266 xg_clear_vinsn (&cur_vinsn
);
5272 md_assemble (char *str
)
5274 xtensa_isa isa
= xtensa_default_isa
;
5277 bfd_boolean has_underbar
= FALSE
;
5278 char *arg_strings
[MAX_INSN_ARGS
];
5280 TInsn orig_insn
; /* Original instruction from the input. */
5282 tinsn_init (&orig_insn
);
5284 /* Split off the opcode. */
5285 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5286 opname
= xmalloc (opnamelen
+ 1);
5287 memcpy (opname
, str
, opnamelen
);
5288 opname
[opnamelen
] = '\0';
5290 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5293 as_bad (_("syntax error"));
5297 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5300 /* Check for an underbar prefix. */
5303 has_underbar
= TRUE
;
5307 orig_insn
.insn_type
= ITYPE_INSN
;
5309 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5311 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5312 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5314 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5315 if (fmt
== XTENSA_UNDEFINED
)
5317 as_bad (_("unknown opcode or format name '%s'"), opname
);
5318 error_reset_cur_vinsn ();
5321 if (!cur_vinsn
.inside_bundle
)
5323 as_bad (_("format names only valid inside bundles"));
5324 error_reset_cur_vinsn ();
5327 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5328 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5330 cur_vinsn
.format
= fmt
;
5331 free (has_underbar
? opname
- 1 : opname
);
5332 error_reset_cur_vinsn ();
5336 /* Parse the arguments. */
5337 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5339 as_bad (_("syntax error"));
5340 error_reset_cur_vinsn ();
5344 /* Free the opcode and argument strings, now that they've been parsed. */
5345 free (has_underbar
? opname
- 1 : opname
);
5347 while (num_args
-- > 0)
5348 free (arg_strings
[num_args
]);
5350 /* Get expressions for invisible operands. */
5351 if (get_invisible_operands (&orig_insn
))
5353 error_reset_cur_vinsn ();
5357 /* Check for the right number and type of arguments. */
5358 if (tinsn_check_arguments (&orig_insn
))
5360 error_reset_cur_vinsn ();
5364 /* Record the line number for each TInsn, because a FLIX bundle may be
5365 spread across multiple input lines and individual instructions may be
5366 moved around in some cases. */
5367 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5368 dwarf2_where (&orig_insn
.debug_line
);
5369 dwarf2_consume_line_info ();
5371 xg_add_branch_and_loop_targets (&orig_insn
);
5373 /* Check that immediate value for ENTRY is >= 16. */
5374 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5376 expressionS
*exp
= &orig_insn
.tok
[2];
5377 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5378 as_warn (_("entry instruction with stack decrement < 16"));
5382 assemble_tokens (opcode, tok, ntok);
5383 expand the tokens from the orig_insn into the
5384 stack of instructions that will not expand
5385 unless required at relaxation time. */
5387 if (!cur_vinsn
.inside_bundle
)
5388 emit_single_op (&orig_insn
);
5389 else /* We are inside a bundle. */
5391 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5392 cur_vinsn
.num_slots
++;
5393 if (*input_line_pointer
== '}'
5394 || *(input_line_pointer
- 1) == '}'
5395 || *(input_line_pointer
- 2) == '}')
5396 finish_vinsn (&cur_vinsn
);
5399 /* We've just emitted a new instruction so clear the list of labels. */
5400 xtensa_clear_insn_labels ();
5404 /* HANDLE_ALIGN hook */
5406 /* For a .align directive, we mark the previous block with the alignment
5407 information. This will be placed in the object file in the
5408 property section corresponding to this section. */
5411 xtensa_handle_align (fragS
*fragP
)
5414 && ! fragP
->tc_frag_data
.is_literal
5415 && (fragP
->fr_type
== rs_align
5416 || fragP
->fr_type
== rs_align_code
)
5417 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5418 && fragP
->fr_offset
> 0
5419 && now_seg
!= bss_section
)
5421 fragP
->tc_frag_data
.is_align
= TRUE
;
5422 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5425 if (fragP
->fr_type
== rs_align_test
)
5428 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5430 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5431 _("unaligned entry instruction"));
5434 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5435 fragP
->fr_subtype
= RELAX_ORG
;
5439 /* TC_FRAG_INIT hook */
5442 xtensa_frag_init (fragS
*frag
)
5444 xtensa_set_frag_assembly_state (frag
);
5449 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5455 /* Round up a section size to the appropriate boundary. */
5458 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5460 return size
; /* Byte alignment is fine. */
5465 md_pcrel_from (fixS
*fixP
)
5468 static xtensa_insnbuf insnbuf
= NULL
;
5469 static xtensa_insnbuf slotbuf
= NULL
;
5472 xtensa_opcode opcode
;
5475 xtensa_isa isa
= xtensa_default_isa
;
5476 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5477 bfd_boolean alt_reloc
;
5479 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5482 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5487 insnbuf
= xtensa_insnbuf_alloc (isa
);
5488 slotbuf
= xtensa_insnbuf_alloc (isa
);
5491 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5492 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5493 fmt
= xtensa_format_decode (isa
, insnbuf
);
5495 if (fmt
== XTENSA_UNDEFINED
)
5496 as_fatal (_("bad instruction format"));
5498 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5499 as_fatal (_("invalid relocation"));
5501 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5502 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5504 /* Check for "alternate" relocations (operand not specified). None
5505 of the current uses for these are really PC-relative. */
5506 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5508 if (opcode
!= xtensa_l32r_opcode
5509 && opcode
!= xtensa_const16_opcode
)
5510 as_fatal (_("invalid relocation for '%s' instruction"),
5511 xtensa_opcode_name (isa
, opcode
));
5515 opnum
= get_relaxable_immed (opcode
);
5517 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5518 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5520 as_bad_where (fixP
->fx_file
,
5522 _("invalid relocation for operand %d of '%s'"),
5523 opnum
, xtensa_opcode_name (isa
, opcode
));
5526 return 0 - opnd_value
;
5530 /* TC_FORCE_RELOCATION hook */
5533 xtensa_force_relocation (fixS
*fix
)
5535 switch (fix
->fx_r_type
)
5537 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5538 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5539 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5540 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5541 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5542 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5543 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5544 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5545 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5546 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5547 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5548 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5549 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5550 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5551 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5552 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5558 if (linkrelax
&& fix
->fx_addsy
5559 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5562 return generic_force_reloc (fix
);
5566 /* TC_VALIDATE_FIX_SUB hook */
5569 xtensa_validate_fix_sub (fixS
*fix
)
5571 segT add_symbol_segment
, sub_symbol_segment
;
5573 /* The difference of two symbols should be resolved by the assembler when
5574 linkrelax is not set. If the linker may relax the section containing
5575 the symbols, then an Xtensa DIFF relocation must be generated so that
5576 the linker knows to adjust the difference value. */
5577 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5580 /* Make sure both symbols are in the same segment, and that segment is
5581 "normal" and relaxable. If the segment is not "normal", then the
5582 fix is not valid. If the segment is not "relaxable", then the fix
5583 should have been handled earlier. */
5584 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5585 if (! SEG_NORMAL (add_symbol_segment
) ||
5586 ! relaxable_section (add_symbol_segment
))
5588 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5589 return (sub_symbol_segment
== add_symbol_segment
);
5593 /* NO_PSEUDO_DOT hook */
5595 /* This function has nothing to do with pseudo dots, but this is the
5596 nearest macro to where the check needs to take place. FIXME: This
5600 xtensa_check_inside_bundle (void)
5602 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5603 as_bad (_("directives are not valid inside bundles"));
5605 /* This function must always return FALSE because it is called via a
5606 macro that has nothing to do with bundling. */
5611 /* md_elf_section_change_hook */
5614 xtensa_elf_section_change_hook (void)
5616 /* Set up the assembly state. */
5617 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5618 xtensa_set_frag_assembly_state (frag_now
);
5622 /* tc_fix_adjustable hook */
5625 xtensa_fix_adjustable (fixS
*fixP
)
5627 /* An offset is not allowed in combination with the difference of two
5628 symbols, but that cannot be easily detected after a local symbol
5629 has been adjusted to a (section+offset) form. Return 0 so that such
5630 an fix will not be adjusted. */
5631 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5632 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5635 /* We need the symbol name for the VTABLE entries. */
5636 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5637 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5644 /* tc_symbol_new_hook */
5646 symbolS
*expr_symbols
= NULL
;
5649 xtensa_symbol_new_hook (symbolS
*sym
)
5651 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5653 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5660 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5662 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5665 /* Subtracted symbols are only allowed for a few relocation types, and
5666 unless linkrelax is enabled, they should not make it to this point. */
5667 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5668 || fixP
->fx_r_type
== BFD_RELOC_16
5669 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5670 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5672 switch (fixP
->fx_r_type
)
5674 case BFD_RELOC_32_PCREL
:
5680 switch (fixP
->fx_r_type
)
5683 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5686 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5689 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5695 /* An offset is only allowed when it results from adjusting a
5696 local symbol into a section-relative offset. If the offset
5697 came from the original expression, tc_fix_adjustable will have
5698 prevented the fix from being converted to a section-relative
5699 form so that we can flag the error here. */
5700 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5701 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5702 _("cannot represent subtraction with an offset"));
5704 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5705 - S_GET_VALUE (fixP
->fx_subsy
));
5707 /* The difference value gets written out, and the DIFF reloc
5708 identifies the address of the subtracted symbol (i.e., the one
5709 with the lowest address). */
5711 fixP
->fx_offset
-= val
;
5712 fixP
->fx_subsy
= NULL
;
5714 else if (! fixP
->fx_addsy
)
5721 case BFD_RELOC_XTENSA_PLT
:
5722 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5723 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5726 case BFD_RELOC_XTENSA_SLOT0_OP
:
5727 case BFD_RELOC_XTENSA_SLOT1_OP
:
5728 case BFD_RELOC_XTENSA_SLOT2_OP
:
5729 case BFD_RELOC_XTENSA_SLOT3_OP
:
5730 case BFD_RELOC_XTENSA_SLOT4_OP
:
5731 case BFD_RELOC_XTENSA_SLOT5_OP
:
5732 case BFD_RELOC_XTENSA_SLOT6_OP
:
5733 case BFD_RELOC_XTENSA_SLOT7_OP
:
5734 case BFD_RELOC_XTENSA_SLOT8_OP
:
5735 case BFD_RELOC_XTENSA_SLOT9_OP
:
5736 case BFD_RELOC_XTENSA_SLOT10_OP
:
5737 case BFD_RELOC_XTENSA_SLOT11_OP
:
5738 case BFD_RELOC_XTENSA_SLOT12_OP
:
5739 case BFD_RELOC_XTENSA_SLOT13_OP
:
5740 case BFD_RELOC_XTENSA_SLOT14_OP
:
5743 /* Write the tentative value of a PC-relative relocation to a
5744 local symbol into the instruction. The value will be ignored
5745 by the linker, and it makes the object file disassembly
5746 readable when all branch targets are encoded in relocations. */
5748 assert (fixP
->fx_addsy
);
5749 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5750 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5752 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5753 - md_pcrel_from (fixP
));
5754 (void) xg_apply_fix_value (fixP
, val
);
5757 else if (! fixP
->fx_addsy
)
5760 if (xg_apply_fix_value (fixP
, val
))
5765 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5766 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5767 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5768 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5769 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5770 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5771 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5772 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5773 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5774 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5775 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5776 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5777 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5778 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5779 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5780 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5781 /* These all need to be resolved at link-time. Do nothing now. */
5784 case BFD_RELOC_VTABLE_INHERIT
:
5785 case BFD_RELOC_VTABLE_ENTRY
:
5790 as_bad (_("unhandled local relocation fix %s"),
5791 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5797 md_atof (int type
, char *litP
, int *sizeP
)
5799 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5804 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5806 return total_frag_text_expansion (fragP
);
5810 /* Translate internal representation of relocation info to BFD target
5814 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5818 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5819 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5820 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5821 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5823 /* Make sure none of our internal relocations make it this far.
5824 They'd better have been fully resolved by this point. */
5825 assert ((int) fixp
->fx_r_type
> 0);
5827 reloc
->addend
= fixp
->fx_offset
;
5829 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5830 if (reloc
->howto
== NULL
)
5832 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5833 _("cannot represent `%s' relocation in object file"),
5834 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5835 free (reloc
->sym_ptr_ptr
);
5840 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5841 as_fatal (_("internal error; cannot generate `%s' relocation"),
5842 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5848 /* Checks for resource conflicts between instructions. */
5850 /* The func unit stuff could be implemented as bit-vectors rather
5851 than the iterative approach here. If it ends up being too
5852 slow, we will switch it. */
5855 new_resource_table (void *data
,
5858 unit_num_copies_func uncf
,
5859 opcode_num_units_func onuf
,
5860 opcode_funcUnit_use_unit_func ouuf
,
5861 opcode_funcUnit_use_stage_func ousf
)
5864 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5866 rt
->cycles
= cycles
;
5867 rt
->allocated_cycles
= cycles
;
5869 rt
->unit_num_copies
= uncf
;
5870 rt
->opcode_num_units
= onuf
;
5871 rt
->opcode_unit_use
= ouuf
;
5872 rt
->opcode_unit_stage
= ousf
;
5874 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5875 for (i
= 0; i
< cycles
; i
++)
5876 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5883 clear_resource_table (resource_table
*rt
)
5886 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5887 for (j
= 0; j
< rt
->num_units
; j
++)
5888 rt
->units
[i
][j
] = 0;
5892 /* We never shrink it, just fake it into thinking so. */
5895 resize_resource_table (resource_table
*rt
, int cycles
)
5899 rt
->cycles
= cycles
;
5900 if (cycles
<= rt
->allocated_cycles
)
5903 old_cycles
= rt
->allocated_cycles
;
5904 rt
->allocated_cycles
= cycles
;
5906 rt
->units
= xrealloc (rt
->units
,
5907 rt
->allocated_cycles
* sizeof (unsigned char *));
5908 for (i
= 0; i
< old_cycles
; i
++)
5909 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5910 rt
->num_units
* sizeof (unsigned char));
5911 for (i
= old_cycles
; i
< cycles
; i
++)
5912 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5917 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5920 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5922 for (i
= 0; i
< uses
; i
++)
5924 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5925 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5926 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5927 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5928 if (copies_in_use
>= copies
)
5936 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5939 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5941 for (i
= 0; i
< uses
; i
++)
5943 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5944 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5945 /* Note that this allows resources to be oversubscribed. That's
5946 essential to the way the optional scheduler works.
5947 resources_available reports when a resource is over-subscribed,
5948 so it's easy to tell. */
5949 rt
->units
[stage
+ cycle
][unit
]++;
5955 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5958 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5960 for (i
= 0; i
< uses
; i
++)
5962 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5963 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5964 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5965 rt
->units
[stage
+ cycle
][unit
]--;
5970 /* Wrapper functions make parameterized resource reservation
5974 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5976 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5982 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5984 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5989 /* Note that this function does not check issue constraints, but
5990 solely whether the hardware is available to execute the given
5991 instructions together. It also doesn't check if the tinsns
5992 write the same state, or access the same tieports. That is
5993 checked by check_t1_t2_reads_and_writes. */
5996 resources_conflict (vliw_insn
*vinsn
)
5999 static resource_table
*rt
= NULL
;
6001 /* This is the most common case by far. Optimize it. */
6002 if (vinsn
->num_slots
== 1)
6007 xtensa_isa isa
= xtensa_default_isa
;
6008 rt
= new_resource_table
6009 (isa
, xtensa_isa_num_pipe_stages (isa
),
6010 xtensa_isa_num_funcUnits (isa
),
6011 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6012 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6013 opcode_funcUnit_use_unit
,
6014 opcode_funcUnit_use_stage
);
6017 clear_resource_table (rt
);
6019 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6021 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6023 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6030 /* finish_vinsn, emit_single_op and helper functions. */
6032 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6033 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6034 static void xg_assemble_vliw_tokens (vliw_insn
*);
6037 /* We have reached the end of a bundle; emit into the frag. */
6040 finish_vinsn (vliw_insn
*vinsn
)
6047 if (find_vinsn_conflicts (vinsn
))
6049 xg_clear_vinsn (vinsn
);
6053 /* First, find a format that works. */
6054 if (vinsn
->format
== XTENSA_UNDEFINED
)
6055 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6057 if (vinsn
->format
== XTENSA_UNDEFINED
)
6059 as_where (&file_name
, &line
);
6060 as_bad_where (file_name
, line
,
6061 _("couldn't find a valid instruction format"));
6062 fprintf (stderr
, _(" ops were: "));
6063 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6064 fprintf (stderr
, _(" %s;"),
6065 xtensa_opcode_name (xtensa_default_isa
,
6066 vinsn
->slots
[i
].opcode
));
6067 fprintf (stderr
, _("\n"));
6068 xg_clear_vinsn (vinsn
);
6072 if (vinsn
->num_slots
6073 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6075 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6076 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6077 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6079 xg_clear_vinsn (vinsn
);
6083 if (resources_conflict (vinsn
))
6085 as_where (&file_name
, &line
);
6086 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6087 fprintf (stderr
, " ops were: ");
6088 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6089 fprintf (stderr
, " %s;",
6090 xtensa_opcode_name (xtensa_default_isa
,
6091 vinsn
->slots
[i
].opcode
));
6092 fprintf (stderr
, "\n");
6093 xg_clear_vinsn (vinsn
);
6097 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6099 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6101 symbolS
*lit_sym
= NULL
;
6103 bfd_boolean e
= FALSE
;
6104 bfd_boolean saved_density
= density_supported
;
6106 /* We don't want to narrow ops inside multi-slot bundles. */
6107 if (vinsn
->num_slots
> 1)
6108 density_supported
= FALSE
;
6110 istack_init (&slotstack
);
6111 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6113 vinsn
->slots
[i
].opcode
=
6114 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6116 vinsn
->slots
[i
].ntok
= 0;
6119 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6125 density_supported
= saved_density
;
6129 xg_clear_vinsn (vinsn
);
6133 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6135 TInsn
*insn
= &slotstack
.insn
[j
];
6136 if (insn
->insn_type
== ITYPE_LITERAL
)
6138 assert (lit_sym
== NULL
);
6139 lit_sym
= xg_assemble_literal (insn
);
6143 assert (insn
->insn_type
== ITYPE_INSN
);
6145 xg_resolve_literals (insn
, lit_sym
);
6146 if (j
!= slotstack
.ninsn
- 1)
6147 emit_single_op (insn
);
6151 if (vinsn
->num_slots
> 1)
6153 if (opcode_fits_format_slot
6154 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6157 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6161 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6162 if (vinsn
->format
== XTENSA_UNDEFINED
)
6163 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6165 vinsn
->slots
[i
].opcode
6166 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6169 vinsn
->slots
[i
].ntok
= 0;
6174 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6175 vinsn
->format
= XTENSA_UNDEFINED
;
6180 /* Now check resource conflicts on the modified bundle. */
6181 if (resources_conflict (vinsn
))
6183 as_where (&file_name
, &line
);
6184 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6185 fprintf (stderr
, " ops were: ");
6186 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6187 fprintf (stderr
, " %s;",
6188 xtensa_opcode_name (xtensa_default_isa
,
6189 vinsn
->slots
[i
].opcode
));
6190 fprintf (stderr
, "\n");
6191 xg_clear_vinsn (vinsn
);
6195 /* First, find a format that works. */
6196 if (vinsn
->format
== XTENSA_UNDEFINED
)
6197 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6199 xg_assemble_vliw_tokens (vinsn
);
6201 xg_clear_vinsn (vinsn
);
6205 /* Given an vliw instruction, what conflicts are there in register
6206 usage and in writes to states and queues?
6208 This function does two things:
6209 1. Reports an error when a vinsn contains illegal combinations
6210 of writes to registers states or queues.
6211 2. Marks individual tinsns as not relaxable if the combination
6212 contains antidependencies.
6214 Job 2 handles things like swap semantics in instructions that need
6215 to be relaxed. For example,
6219 normally would be relaxed to
6224 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6226 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6228 then we can't relax it into
6231 { add a0, a1, a0 ; add a2, a0, a4 ; }
6233 because the value of a0 is trashed before the second add can read it. */
6235 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6238 find_vinsn_conflicts (vliw_insn
*vinsn
)
6242 xtensa_isa isa
= xtensa_default_isa
;
6244 assert (!past_xtensa_end
);
6246 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6248 TInsn
*op1
= &vinsn
->slots
[i
];
6249 if (op1
->is_specific_opcode
)
6250 op1
->keep_wide
= TRUE
;
6252 op1
->keep_wide
= FALSE
;
6255 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6257 TInsn
*op1
= &vinsn
->slots
[i
];
6259 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6262 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6266 TInsn
*op2
= &vinsn
->slots
[j
];
6267 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6268 switch (conflict_type
)
6271 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6272 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6273 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6276 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6277 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6278 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6281 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6282 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6283 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6286 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6287 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6288 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6291 /* Everything is OK. */
6294 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6295 || conflict_type
== 'a');
6302 as_bad (_("multiple branches or jumps in the same bundle"));
6310 /* Check how the state used by t1 and t2 relate.
6313 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6314 case B: no relationship between what is read and written (both could
6315 read the same reg though)
6316 case C: t1 writes a register t2 writes (a register conflict within a
6318 case D: t1 writes a state that t2 also writes
6319 case E: t1 writes a tie queue that t2 also writes
6320 case F: two volatile queue accesses
6324 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6326 xtensa_isa isa
= xtensa_default_isa
;
6327 xtensa_regfile t1_regfile
, t2_regfile
;
6329 int t1_base_reg
, t1_last_reg
;
6330 int t2_base_reg
, t2_last_reg
;
6331 char t1_inout
, t2_inout
;
6333 char conflict
= 'b';
6338 bfd_boolean t1_volatile
= FALSE
;
6339 bfd_boolean t2_volatile
= FALSE
;
6341 /* Check registers. */
6342 for (j
= 0; j
< t2
->ntok
; j
++)
6344 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6347 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6348 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6349 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6351 for (i
= 0; i
< t1
->ntok
; i
++)
6353 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6356 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6358 if (t1_regfile
!= t2_regfile
)
6361 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6362 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6364 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6365 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6367 if (t1_inout
== 'm' || t1_inout
== 'o'
6368 || t2_inout
== 'm' || t2_inout
== 'o')
6375 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6376 t1_last_reg
= (t1_base_reg
6377 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6379 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6381 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6383 if (t1_reg
!= t2_reg
)
6386 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6392 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6398 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6406 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6407 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6408 for (j
= 0; j
< t2_states
; j
++)
6410 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6411 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6412 for (i
= 0; i
< t1_states
; i
++)
6414 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6415 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6419 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6425 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6431 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6436 /* Check tieports. */
6437 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6438 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6439 for (j
= 0; j
< t2_interfaces
; j
++)
6441 xtensa_interface t2_int
6442 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6443 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6445 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6446 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6449 for (i
= 0; i
< t1_interfaces
; i
++)
6451 xtensa_interface t1_int
6452 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6453 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6455 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6456 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6459 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6462 if (t1_int
!= t2_int
)
6465 if (t2_inout
== 'i' && t1_inout
== 'o')
6471 if (t1_inout
== 'i' && t2_inout
== 'o')
6477 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6486 static xtensa_format
6487 xg_find_narrowest_format (vliw_insn
*vinsn
)
6489 /* Right now we assume that the ops within the vinsn are properly
6490 ordered for the slots that the programmer wanted them in. In
6491 other words, we don't rearrange the ops in hopes of finding a
6492 better format. The scheduler handles that. */
6494 xtensa_isa isa
= xtensa_default_isa
;
6495 xtensa_format format
;
6496 vliw_insn v_copy
= *vinsn
;
6497 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6499 if (vinsn
->num_slots
== 1)
6500 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6502 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6505 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6509 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6511 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6513 v_copy
.slots
[slot
].opcode
=
6514 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6515 v_copy
.slots
[slot
].ntok
= 0;
6518 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6521 else if (v_copy
.num_slots
> 1)
6524 /* Try the widened version. */
6525 if (!v_copy
.slots
[slot
].keep_wide
6526 && !v_copy
.slots
[slot
].is_specific_opcode
6527 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6529 && opcode_fits_format_slot (widened
.opcode
,
6532 v_copy
.slots
[slot
] = widened
;
6537 if (fit
== v_copy
.num_slots
)
6540 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6541 vinsn
->format
= format
;
6547 if (format
== xtensa_isa_num_formats (isa
))
6548 return XTENSA_UNDEFINED
;
6554 /* Return the additional space needed in a frag
6555 for possible relaxations of any ops in a VLIW insn.
6556 Also fill out the relaxations that might be required of
6557 each tinsn in the vinsn. */
6560 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6562 bfd_boolean finish_frag
= FALSE
;
6563 int extra_space
= 0;
6566 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6568 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6569 if (!tinsn_has_symbolic_operands (tinsn
))
6571 /* A narrow instruction could be widened later to help
6572 alignment issues. */
6573 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6574 && !tinsn
->is_specific_opcode
6575 && vinsn
->num_slots
== 1)
6577 /* Difference in bytes between narrow and wide insns... */
6579 tinsn
->subtype
= RELAX_NARROW
;
6584 if (workaround_b_j_loop_end
6585 && tinsn
->opcode
== xtensa_jx_opcode
6586 && use_transform ())
6588 /* Add 2 of these. */
6589 extra_space
+= 3; /* for the nop size */
6590 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6593 /* Need to assemble it with space for the relocation. */
6594 if (xg_is_relaxable_insn (tinsn
, 0)
6595 && !tinsn
->is_specific_opcode
)
6597 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6598 int max_literal_size
=
6599 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6601 tinsn
->literal_space
= max_literal_size
;
6603 tinsn
->subtype
= RELAX_IMMED
;
6604 extra_space
+= max_size
;
6608 /* A fix record will be added for this instruction prior
6609 to relaxation, so make it end the frag. */
6614 *pfinish_frag
= finish_frag
;
6620 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6622 xtensa_isa isa
= xtensa_default_isa
;
6623 int slot
, chosen_slot
;
6625 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6626 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6627 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6629 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6630 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6632 if (slot
== chosen_slot
)
6633 vinsn
->slots
[slot
] = *tinsn
;
6636 vinsn
->slots
[slot
].opcode
=
6637 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6638 vinsn
->slots
[slot
].ntok
= 0;
6639 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6646 emit_single_op (TInsn
*orig_insn
)
6649 IStack istack
; /* put instructions into here */
6650 symbolS
*lit_sym
= NULL
;
6651 symbolS
*label_sym
= NULL
;
6653 istack_init (&istack
);
6655 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6656 Because the scheduling and bundling characteristics of movi and
6657 l32r or const16 are so different, we can do much better if we relax
6658 it prior to scheduling and bundling, rather than after. */
6659 if ((orig_insn
->opcode
== xtensa_movi_opcode
6660 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6661 && !cur_vinsn
.inside_bundle
6662 && (orig_insn
->tok
[1].X_op
== O_symbol
6663 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6664 && !orig_insn
->is_specific_opcode
&& use_transform ())
6665 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6667 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6670 for (i
= 0; i
< istack
.ninsn
; i
++)
6672 TInsn
*insn
= &istack
.insn
[i
];
6673 switch (insn
->insn_type
)
6676 assert (lit_sym
== NULL
);
6677 lit_sym
= xg_assemble_literal (insn
);
6681 static int relaxed_sym_idx
= 0;
6682 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6683 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6685 assert (label_sym
== NULL
);
6686 label_sym
= symbol_find_or_make (label
);
6695 xg_resolve_literals (insn
, lit_sym
);
6697 xg_resolve_labels (insn
, label_sym
);
6699 bundle_tinsn (insn
, &v
);
6714 total_frag_text_expansion (fragS
*fragP
)
6717 int total_expansion
= 0;
6719 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6720 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6722 return total_expansion
;
6726 /* Emit a vliw instruction to the current fragment. */
6729 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6731 bfd_boolean finish_frag
;
6732 bfd_boolean is_jump
= FALSE
;
6733 bfd_boolean is_branch
= FALSE
;
6734 xtensa_isa isa
= xtensa_default_isa
;
6739 struct dwarf2_line_info debug_line
;
6740 bfd_boolean loc_directive_seen
= FALSE
;
6743 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6745 if (generating_literals
)
6747 static int reported
= 0;
6749 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6750 _("cannot assemble into a literal fragment"));
6757 if (frag_now_fix () != 0
6758 && (! frag_now
->tc_frag_data
.is_insn
6759 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6760 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6761 || (directive_state
[directive_longcalls
]
6762 != frag_now
->tc_frag_data
.use_longcalls
)
6763 || (directive_state
[directive_absolute_literals
]
6764 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6766 frag_wane (frag_now
);
6768 xtensa_set_frag_assembly_state (frag_now
);
6771 if (workaround_a0_b_retw
6772 && vinsn
->num_slots
== 1
6773 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6774 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6775 && use_transform ())
6777 has_a0_b_retw
= TRUE
;
6779 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6780 After the first assembly pass we will check all of them and
6781 add a nop if needed. */
6782 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6783 frag_var (rs_machine_dependent
, 4, 4,
6784 RELAX_ADD_NOP_IF_A0_B_RETW
,
6785 frag_now
->fr_symbol
,
6786 frag_now
->fr_offset
,
6788 xtensa_set_frag_assembly_state (frag_now
);
6789 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6790 frag_var (rs_machine_dependent
, 4, 4,
6791 RELAX_ADD_NOP_IF_A0_B_RETW
,
6792 frag_now
->fr_symbol
,
6793 frag_now
->fr_offset
,
6795 xtensa_set_frag_assembly_state (frag_now
);
6798 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6800 tinsn
= &vinsn
->slots
[slot
];
6802 /* See if the instruction implies an aligned section. */
6803 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6804 record_alignment (now_seg
, 2);
6806 /* Determine the best line number for debug info. */
6807 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6808 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6809 || tinsn
->debug_line
.line
< debug_line
.line
6810 || tinsn
->debug_line
.column
< debug_line
.column
))
6811 debug_line
= tinsn
->debug_line
;
6812 if (tinsn
->loc_directive_seen
)
6813 loc_directive_seen
= TRUE
;
6816 /* Special cases for instructions that force an alignment... */
6817 /* None of these opcodes are bundle-able. */
6818 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6822 /* Remember the symbol that marks the end of the loop in the frag
6823 that marks the start of the loop. This way we can easily find
6824 the end of the loop at the beginning, without adding special code
6825 to mark the loop instructions themselves. */
6826 symbolS
*target_sym
= NULL
;
6827 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6828 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6830 xtensa_set_frag_assembly_state (frag_now
);
6831 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6833 max_fill
= get_text_align_max_fill_size
6834 (get_text_align_power (xtensa_fetch_width
),
6835 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6837 if (use_transform ())
6838 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6839 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6841 frag_var (rs_machine_dependent
, 0, 0,
6842 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6843 xtensa_set_frag_assembly_state (frag_now
);
6846 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6847 && !vinsn
->slots
[0].is_specific_opcode
)
6849 xtensa_mark_literal_pool_location ();
6850 xtensa_move_labels (frag_now
, 0);
6851 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6854 if (vinsn
->num_slots
== 1)
6856 if (workaround_a0_b_retw
&& use_transform ())
6857 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6858 is_register_writer (&vinsn
->slots
[0], "a", 0));
6860 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6861 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6864 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6866 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6868 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6870 /* vinsn_to_insnbuf will produce the error. */
6871 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6873 f
= frag_more (insn_size
+ extra_space
);
6874 xtensa_set_frag_assembly_state (frag_now
);
6875 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6878 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6879 if (vinsn
->format
== XTENSA_UNDEFINED
)
6882 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6884 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
6885 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
6888 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6890 tinsn
= &vinsn
->slots
[slot
];
6891 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6892 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6893 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6894 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6895 if (tinsn
->literal_space
!= 0)
6896 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6898 if (tinsn
->subtype
== RELAX_NARROW
)
6899 assert (vinsn
->num_slots
== 1);
6900 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6902 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6905 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6906 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6910 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6911 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6915 frag_variant (rs_machine_dependent
,
6916 extra_space
, extra_space
, RELAX_SLOTS
,
6917 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6918 xtensa_set_frag_assembly_state (frag_now
);
6921 /* Special cases for loops:
6922 close_loop_end should be inserted AFTER short_loop.
6923 Make sure that CLOSE loops are processed BEFORE short_loops
6924 when converting them. */
6926 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6927 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6928 && !vinsn
->slots
[0].is_specific_opcode
)
6930 if (workaround_short_loop
&& use_transform ())
6932 maybe_has_short_loop
= TRUE
;
6933 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6934 frag_var (rs_machine_dependent
, 4, 4,
6935 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6936 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6937 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6938 frag_var (rs_machine_dependent
, 4, 4,
6939 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6940 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6943 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6944 loop at least 12 bytes away from another loop's end. */
6945 if (workaround_close_loop_end
&& use_transform ())
6947 maybe_has_close_loop_end
= TRUE
;
6948 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6949 frag_var (rs_machine_dependent
, 12, 12,
6950 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6951 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6955 if (use_transform ())
6959 assert (finish_frag
);
6960 frag_var (rs_machine_dependent
,
6961 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6963 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6964 xtensa_set_frag_assembly_state (frag_now
);
6966 else if (is_branch
&& do_align_targets ())
6968 assert (finish_frag
);
6969 frag_var (rs_machine_dependent
,
6970 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6971 RELAX_MAYBE_UNREACHABLE
,
6972 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6973 xtensa_set_frag_assembly_state (frag_now
);
6974 frag_var (rs_machine_dependent
,
6976 RELAX_MAYBE_DESIRE_ALIGN
,
6977 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6978 xtensa_set_frag_assembly_state (frag_now
);
6982 /* Now, if the original opcode was a call... */
6983 if (do_align_targets ()
6984 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6986 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6987 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6988 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6989 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6990 xtensa_set_frag_assembly_state (frag_now
);
6993 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6995 frag_wane (frag_now
);
6997 xtensa_set_frag_assembly_state (frag_now
);
7002 /* xtensa_end and helper functions. */
7004 static void xtensa_cleanup_align_frags (void);
7005 static void xtensa_fix_target_frags (void);
7006 static void xtensa_mark_narrow_branches (void);
7007 static void xtensa_mark_zcl_first_insns (void);
7008 static void xtensa_mark_difference_of_two_symbols (void);
7009 static void xtensa_fix_a0_b_retw_frags (void);
7010 static void xtensa_fix_b_j_loop_end_frags (void);
7011 static void xtensa_fix_close_loop_end_frags (void);
7012 static void xtensa_fix_short_loop_frags (void);
7013 static void xtensa_sanity_check (void);
7014 static void xtensa_add_config_info (void);
7019 directive_balance ();
7020 xtensa_flush_pending_output ();
7022 past_xtensa_end
= TRUE
;
7024 xtensa_move_literals ();
7026 xtensa_reorder_segments ();
7027 xtensa_cleanup_align_frags ();
7028 xtensa_fix_target_frags ();
7029 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7030 xtensa_fix_a0_b_retw_frags ();
7031 if (workaround_b_j_loop_end
)
7032 xtensa_fix_b_j_loop_end_frags ();
7034 /* "close_loop_end" should be processed BEFORE "short_loop". */
7035 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7036 xtensa_fix_close_loop_end_frags ();
7038 if (workaround_short_loop
&& maybe_has_short_loop
)
7039 xtensa_fix_short_loop_frags ();
7041 xtensa_mark_narrow_branches ();
7042 xtensa_mark_zcl_first_insns ();
7044 xtensa_sanity_check ();
7046 xtensa_add_config_info ();
7051 xtensa_cleanup_align_frags (void)
7056 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7057 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7060 /* Walk over all of the fragments in a subsection. */
7061 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7063 if ((fragP
->fr_type
== rs_align
7064 || fragP
->fr_type
== rs_align_code
7065 || (fragP
->fr_type
== rs_machine_dependent
7066 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7067 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7068 && fragP
->fr_fix
== 0)
7070 fragS
*next
= fragP
->fr_next
;
7073 && next
->fr_fix
== 0
7074 && next
->fr_type
== rs_machine_dependent
7075 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7078 next
= next
->fr_next
;
7081 /* If we don't widen branch targets, then they
7082 will be easier to align. */
7083 if (fragP
->tc_frag_data
.is_branch_target
7084 && fragP
->fr_opcode
== fragP
->fr_literal
7085 && fragP
->fr_type
== rs_machine_dependent
7086 && fragP
->fr_subtype
== RELAX_SLOTS
7087 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7089 if (fragP
->fr_type
== rs_machine_dependent
7090 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7091 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7097 /* Re-process all of the fragments looking to convert all of the
7098 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7099 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7100 Otherwise, convert to a .fill 0. */
7103 xtensa_fix_target_frags (void)
7108 /* When this routine is called, all of the subsections are still intact
7109 so we walk over subsections instead of sections. */
7110 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7111 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7115 /* Walk over all of the fragments in a subsection. */
7116 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7118 if (fragP
->fr_type
== rs_machine_dependent
7119 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7121 if (next_frag_is_branch_target (fragP
))
7122 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7131 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7134 xtensa_mark_narrow_branches (void)
7139 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7140 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7143 /* Walk over all of the fragments in a subsection. */
7144 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7146 if (fragP
->fr_type
== rs_machine_dependent
7147 && fragP
->fr_subtype
== RELAX_SLOTS
7148 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7152 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7153 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7155 if (vinsn
.num_slots
== 1
7156 && xtensa_opcode_is_branch (xtensa_default_isa
,
7157 vinsn
.slots
[0].opcode
) == 1
7158 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7159 && is_narrow_branch_guaranteed_in_range (fragP
,
7162 fragP
->fr_subtype
= RELAX_SLOTS
;
7163 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7164 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7172 /* A branch is typically widened only when its target is out of
7173 range. However, we would like to widen them to align a subsequent
7174 branch target when possible.
7176 Because the branch relaxation code is so convoluted, the optimal solution
7177 (combining the two cases) is difficult to get right in all circumstances.
7178 We therefore go with an "almost as good" solution, where we only
7179 use for alignment narrow branches that definitely will not expand to a
7180 jump and a branch. These functions find and mark these cases. */
7182 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7183 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7184 We start counting beginning with the frag after the 2-byte branch, so the
7185 maximum offset is (4 - 2) + 63 = 65. */
7186 #define MAX_IMMED6 65
7188 static offsetT
unrelaxed_frag_max_size (fragS
*);
7191 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7193 const expressionS
*expr
= &tinsn
->tok
[1];
7194 symbolS
*symbolP
= expr
->X_add_symbol
;
7195 offsetT max_distance
= expr
->X_add_number
;
7198 if (expr
->X_op
!= O_symbol
)
7201 target_frag
= symbol_get_frag (symbolP
);
7203 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7204 if (is_branch_jmp_to_next (tinsn
, fragP
))
7207 /* The branch doesn't branch over it's own frag,
7208 but over the subsequent ones. */
7209 fragP
= fragP
->fr_next
;
7210 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7212 max_distance
+= unrelaxed_frag_max_size (fragP
);
7213 fragP
= fragP
->fr_next
;
7215 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7222 xtensa_mark_zcl_first_insns (void)
7227 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7228 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7231 /* Walk over all of the fragments in a subsection. */
7232 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7234 if (fragP
->fr_type
== rs_machine_dependent
7235 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7236 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7238 /* Find the loop frag. */
7239 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7240 /* Find the first insn frag. */
7241 targ_frag
= next_non_empty_frag (targ_frag
);
7243 /* Of course, sometimes (mostly for toy test cases) a
7244 zero-cost loop instruction is the last in a section. */
7247 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7248 /* Do not widen a frag that is the first instruction of a
7249 zero-cost loop. It makes that loop harder to align. */
7250 if (targ_frag
->fr_type
== rs_machine_dependent
7251 && targ_frag
->fr_subtype
== RELAX_SLOTS
7252 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7255 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7256 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7259 frag_wane (targ_frag
);
7260 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7264 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7272 /* When a difference-of-symbols expression is encoded as a uleb128 or
7273 sleb128 value, the linker is unable to adjust that value to account for
7274 link-time relaxation. Mark all the code between such symbols so that
7275 its size cannot be changed by linker relaxation. */
7278 xtensa_mark_difference_of_two_symbols (void)
7282 for (expr_sym
= expr_symbols
; expr_sym
;
7283 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7285 expressionS
*expr
= symbol_get_value_expression (expr_sym
);
7287 if (expr
->X_op
== O_subtract
)
7289 symbolS
*left
= expr
->X_add_symbol
;
7290 symbolS
*right
= expr
->X_op_symbol
;
7292 /* Difference of two symbols not in the same section
7293 are handled with relocations in the linker. */
7294 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7299 if (symbol_get_frag (left
)->fr_address
7300 <= symbol_get_frag (right
)->fr_address
)
7302 start
= symbol_get_frag (left
);
7303 end
= symbol_get_frag (right
);
7307 start
= symbol_get_frag (right
);
7308 end
= symbol_get_frag (left
);
7312 start
->tc_frag_data
.is_no_transform
= 1;
7313 start
= start
->fr_next
;
7315 while (start
&& start
->fr_address
< end
->fr_address
);
7322 /* Re-process all of the fragments looking to convert all of the
7323 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7324 conditional branch or a retw/retw.n, convert this frag to one that
7325 will generate a NOP. In any case close it off with a .fill 0. */
7327 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7330 xtensa_fix_a0_b_retw_frags (void)
7335 /* When this routine is called, all of the subsections are still intact
7336 so we walk over subsections instead of sections. */
7337 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7338 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7342 /* Walk over all of the fragments in a subsection. */
7343 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7345 if (fragP
->fr_type
== rs_machine_dependent
7346 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7348 if (next_instrs_are_b_retw (fragP
))
7350 if (fragP
->tc_frag_data
.is_no_transform
)
7351 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7353 relax_frag_add_nop (fragP
);
7363 next_instrs_are_b_retw (fragS
*fragP
)
7365 xtensa_opcode opcode
;
7367 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7368 static xtensa_insnbuf insnbuf
= NULL
;
7369 static xtensa_insnbuf slotbuf
= NULL
;
7370 xtensa_isa isa
= xtensa_default_isa
;
7373 bfd_boolean branch_seen
= FALSE
;
7377 insnbuf
= xtensa_insnbuf_alloc (isa
);
7378 slotbuf
= xtensa_insnbuf_alloc (isa
);
7381 if (next_fragP
== NULL
)
7384 /* Check for the conditional branch. */
7385 xtensa_insnbuf_from_chars
7386 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7387 fmt
= xtensa_format_decode (isa
, insnbuf
);
7388 if (fmt
== XTENSA_UNDEFINED
)
7391 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7393 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7394 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7396 branch_seen
= (branch_seen
7397 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7403 offset
+= xtensa_format_length (isa
, fmt
);
7404 if (offset
== next_fragP
->fr_fix
)
7406 next_fragP
= next_non_empty_frag (next_fragP
);
7410 if (next_fragP
== NULL
)
7413 /* Check for the retw/retw.n. */
7414 xtensa_insnbuf_from_chars
7415 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7416 fmt
= xtensa_format_decode (isa
, insnbuf
);
7418 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7419 have no problems. */
7420 if (fmt
== XTENSA_UNDEFINED
7421 || xtensa_format_num_slots (isa
, fmt
) != 1)
7424 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7425 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7427 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7434 /* Re-process all of the fragments looking to convert all of the
7435 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7436 loop end label, convert this frag to one that will generate a NOP.
7437 In any case close it off with a .fill 0. */
7439 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7442 xtensa_fix_b_j_loop_end_frags (void)
7447 /* When this routine is called, all of the subsections are still intact
7448 so we walk over subsections instead of sections. */
7449 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7450 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7454 /* Walk over all of the fragments in a subsection. */
7455 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7457 if (fragP
->fr_type
== rs_machine_dependent
7458 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7460 if (next_instr_is_loop_end (fragP
))
7462 if (fragP
->tc_frag_data
.is_no_transform
)
7463 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7465 relax_frag_add_nop (fragP
);
7475 next_instr_is_loop_end (fragS
*fragP
)
7477 const fragS
*next_fragP
;
7479 if (next_frag_is_loop_target (fragP
))
7482 next_fragP
= next_non_empty_frag (fragP
);
7483 if (next_fragP
== NULL
)
7486 if (!next_frag_is_loop_target (next_fragP
))
7489 /* If the size is >= 3 then there is more than one instruction here.
7490 The hardware bug will not fire. */
7491 if (next_fragP
->fr_fix
> 3)
7498 /* Re-process all of the fragments looking to convert all of the
7499 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7500 not MY loop's loop end within 12 bytes, add enough nops here to
7501 make it at least 12 bytes away. In any case close it off with a
7504 static offsetT min_bytes_to_other_loop_end
7505 (fragS
*, fragS
*, offsetT
);
7508 xtensa_fix_close_loop_end_frags (void)
7513 /* When this routine is called, all of the subsections are still intact
7514 so we walk over subsections instead of sections. */
7515 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7516 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7520 fragS
*current_target
= NULL
;
7522 /* Walk over all of the fragments in a subsection. */
7523 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7525 if (fragP
->fr_type
== rs_machine_dependent
7526 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7527 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7528 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7531 && fragP
->fr_type
== rs_machine_dependent
7532 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7535 int bytes_added
= 0;
7537 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7538 /* Max out at 12. */
7539 min_bytes
= min_bytes_to_other_loop_end
7540 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7542 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7544 if (fragP
->tc_frag_data
.is_no_transform
)
7545 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7548 while (min_bytes
+ bytes_added
7549 < REQUIRED_LOOP_DIVIDING_BYTES
)
7553 if (fragP
->fr_var
< length
)
7554 as_fatal (_("fr_var %lu < length %d"),
7555 (long) fragP
->fr_var
, length
);
7558 assemble_nop (length
,
7559 fragP
->fr_literal
+ fragP
->fr_fix
);
7560 fragP
->fr_fix
+= length
;
7561 fragP
->fr_var
-= length
;
7563 bytes_added
+= length
;
7569 assert (fragP
->fr_type
!= rs_machine_dependent
7570 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7576 static offsetT
unrelaxed_frag_min_size (fragS
*);
7579 min_bytes_to_other_loop_end (fragS
*fragP
,
7580 fragS
*current_target
,
7584 fragS
*current_fragP
;
7586 for (current_fragP
= fragP
;
7588 current_fragP
= current_fragP
->fr_next
)
7590 if (current_fragP
->tc_frag_data
.is_loop_target
7591 && current_fragP
!= current_target
)
7594 offset
+= unrelaxed_frag_min_size (current_fragP
);
7596 if (offset
>= max_size
)
7604 unrelaxed_frag_min_size (fragS
*fragP
)
7606 offsetT size
= fragP
->fr_fix
;
7608 /* Add fill size. */
7609 if (fragP
->fr_type
== rs_fill
)
7610 size
+= fragP
->fr_offset
;
7617 unrelaxed_frag_max_size (fragS
*fragP
)
7619 offsetT size
= fragP
->fr_fix
;
7620 switch (fragP
->fr_type
)
7623 /* Empty frags created by the obstack allocation scheme
7624 end up with type 0. */
7629 size
+= fragP
->fr_offset
;
7637 /* No further adjustments needed. */
7639 case rs_machine_dependent
:
7640 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7641 size
+= fragP
->fr_var
;
7644 /* We had darn well better know how big it is. */
7653 /* Re-process all of the fragments looking to convert all
7654 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7657 1) the instruction size count to the loop end label
7658 is too short (<= 2 instructions),
7659 2) loop has a jump or branch in it
7662 1) workaround_all_short_loops is TRUE
7663 2) The generating loop was a 'loopgtz' or 'loopnez'
7664 3) the instruction size count to the loop end label is too short
7666 then convert this frag (and maybe the next one) to generate a NOP.
7667 In any case close it off with a .fill 0. */
7669 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7670 static bfd_boolean
branch_before_loop_end (fragS
*);
7673 xtensa_fix_short_loop_frags (void)
7678 /* When this routine is called, all of the subsections are still intact
7679 so we walk over subsections instead of sections. */
7680 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7681 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7684 fragS
*current_target
= NULL
;
7685 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7687 /* Walk over all of the fragments in a subsection. */
7688 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7690 if (fragP
->fr_type
== rs_machine_dependent
7691 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7692 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7695 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7696 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7697 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7698 current_opcode
= t_insn
.opcode
;
7699 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7700 current_opcode
) == 1);
7703 if (fragP
->fr_type
== rs_machine_dependent
7704 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7706 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7707 && (branch_before_loop_end (fragP
->fr_next
)
7708 || (workaround_all_short_loops
7709 && current_opcode
!= XTENSA_UNDEFINED
7710 && current_opcode
!= xtensa_loop_opcode
)))
7712 if (fragP
->tc_frag_data
.is_no_transform
)
7713 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7715 relax_frag_add_nop (fragP
);
7724 static int unrelaxed_frag_min_insn_count (fragS
*);
7727 count_insns_to_loop_end (fragS
*base_fragP
,
7728 bfd_boolean count_relax_add
,
7731 fragS
*fragP
= NULL
;
7736 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7738 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7739 if (insn_count
>= max_count
)
7742 if (count_relax_add
)
7744 if (fragP
->fr_type
== rs_machine_dependent
7745 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7747 /* In order to add the appropriate number of
7748 NOPs, we count an instruction for downstream
7751 if (insn_count
>= max_count
)
7761 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7763 xtensa_isa isa
= xtensa_default_isa
;
7764 static xtensa_insnbuf insnbuf
= NULL
;
7768 if (!fragP
->tc_frag_data
.is_insn
)
7772 insnbuf
= xtensa_insnbuf_alloc (isa
);
7774 /* Decode the fixed instructions. */
7775 while (offset
< fragP
->fr_fix
)
7779 xtensa_insnbuf_from_chars
7780 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7781 fmt
= xtensa_format_decode (isa
, insnbuf
);
7783 if (fmt
== XTENSA_UNDEFINED
)
7785 as_fatal (_("undecodable instruction in instruction frag"));
7788 offset
+= xtensa_format_length (isa
, fmt
);
7796 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7799 branch_before_loop_end (fragS
*base_fragP
)
7803 for (fragP
= base_fragP
;
7804 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7805 fragP
= fragP
->fr_next
)
7807 if (unrelaxed_frag_has_b_j (fragP
))
7815 unrelaxed_frag_has_b_j (fragS
*fragP
)
7817 static xtensa_insnbuf insnbuf
= NULL
;
7818 xtensa_isa isa
= xtensa_default_isa
;
7821 if (!fragP
->tc_frag_data
.is_insn
)
7825 insnbuf
= xtensa_insnbuf_alloc (isa
);
7827 /* Decode the fixed instructions. */
7828 while (offset
< fragP
->fr_fix
)
7833 xtensa_insnbuf_from_chars
7834 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7835 fmt
= xtensa_format_decode (isa
, insnbuf
);
7836 if (fmt
== XTENSA_UNDEFINED
)
7839 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7841 xtensa_opcode opcode
=
7842 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7843 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7844 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7847 offset
+= xtensa_format_length (isa
, fmt
);
7853 /* Checks to be made after initial assembly but before relaxation. */
7855 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7856 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7859 xtensa_sanity_check (void)
7866 as_where (&file_name
, &line
);
7867 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7868 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7872 /* Walk over all of the fragments in a subsection. */
7873 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7875 if (fragP
->fr_type
== rs_machine_dependent
7876 && fragP
->fr_subtype
== RELAX_SLOTS
7877 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7879 static xtensa_insnbuf insnbuf
= NULL
;
7882 if (fragP
->fr_opcode
!= NULL
)
7885 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7886 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7887 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7889 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7890 t_insn
.opcode
) == 1)
7892 if (is_empty_loop (&t_insn
, fragP
))
7894 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7895 as_bad (_("invalid empty loop"));
7897 if (!is_local_forward_loop (&t_insn
, fragP
))
7899 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7900 as_bad (_("loop target does not follow "
7901 "loop instruction in section"));
7908 new_logical_line (file_name
, line
);
7912 #define LOOP_IMMED_OPN 1
7914 /* Return TRUE if the loop target is the next non-zero fragment. */
7917 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7919 const expressionS
*expr
;
7923 if (insn
->insn_type
!= ITYPE_INSN
)
7926 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7929 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7932 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7934 if (expr
->X_op
!= O_symbol
)
7937 symbolP
= expr
->X_add_symbol
;
7941 if (symbol_get_frag (symbolP
) == NULL
)
7944 if (S_GET_VALUE (symbolP
) != 0)
7947 /* Walk through the zero-size fragments from this one. If we find
7948 the target fragment, then this is a zero-size loop. */
7950 for (next_fragP
= fragP
->fr_next
;
7952 next_fragP
= next_fragP
->fr_next
)
7954 if (next_fragP
== symbol_get_frag (symbolP
))
7956 if (next_fragP
->fr_fix
!= 0)
7964 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7966 const expressionS
*expr
;
7970 if (insn
->insn_type
!= ITYPE_INSN
)
7973 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7976 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7979 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7981 if (expr
->X_op
!= O_symbol
)
7984 symbolP
= expr
->X_add_symbol
;
7988 if (symbol_get_frag (symbolP
) == NULL
)
7991 /* Walk through fragments until we find the target.
7992 If we do not find the target, then this is an invalid loop. */
7994 for (next_fragP
= fragP
->fr_next
;
7996 next_fragP
= next_fragP
->fr_next
)
7998 if (next_fragP
== symbol_get_frag (symbolP
))
8006 #define XTINFO_NAME "Xtensa_Info"
8007 #define XTINFO_NAMESZ 12
8008 #define XTINFO_TYPE 1
8011 xtensa_add_config_info (void)
8017 info_sec
= subseg_new (".xtensa.info", 0);
8018 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8020 data
= xmalloc (100);
8021 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8022 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8023 sz
= strlen (data
) + 1;
8025 /* Add enough null terminators to pad to a word boundary. */
8028 while ((sz
& 3) != 0);
8030 /* Follow the standard note section layout:
8031 First write the length of the name string. */
8033 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8035 /* Next comes the length of the "descriptor", i.e., the actual data. */
8037 md_number_to_chars (p
, (valueT
) sz
, 4);
8039 /* Write the note type. */
8041 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8043 /* Write the name field. */
8044 p
= frag_more (XTINFO_NAMESZ
);
8045 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8047 /* Finally, write the descriptor. */
8049 memcpy (p
, data
, sz
);
8055 /* Alignment Functions. */
8058 get_text_align_power (unsigned target_size
)
8060 if (target_size
<= 4)
8062 assert (target_size
== 8);
8068 get_text_align_max_fill_size (int align_pow
,
8069 bfd_boolean use_nops
,
8070 bfd_boolean use_no_density
)
8073 return (1 << align_pow
);
8075 return 3 * (1 << align_pow
);
8077 return 1 + (1 << align_pow
);
8081 /* Calculate the minimum bytes of fill needed at "address" to align a
8082 target instruction of size "target_size" so that it does not cross a
8083 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8084 the fill can be an arbitrary number of bytes. Otherwise, the space must
8085 be filled by NOP instructions. */
8088 get_text_align_fill_size (addressT address
,
8091 bfd_boolean use_nops
,
8092 bfd_boolean use_no_density
)
8094 addressT alignment
, fill
, fill_limit
, fill_step
;
8095 bfd_boolean skip_one
= FALSE
;
8097 alignment
= (1 << align_pow
);
8098 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8102 fill_limit
= alignment
;
8105 else if (!use_no_density
)
8107 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8108 fill_limit
= alignment
* 2;
8114 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8115 fill_limit
= alignment
* 3;
8119 /* Try all fill sizes until finding one that works. */
8120 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8122 if (skip_one
&& fill
== 1)
8124 if ((address
+ fill
) >> align_pow
8125 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8134 branch_align_power (segT sec
)
8136 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8137 is aligned to at least an 8-byte boundary, then a branch target need
8138 only fit within an 8-byte aligned block of memory to avoid a stall.
8139 Otherwise, try to fit branch targets within 4-byte aligned blocks
8140 (which may be insufficient, e.g., if the section has no alignment, but
8141 it's good enough). */
8142 if (xtensa_fetch_width
== 8)
8144 if (get_recorded_alignment (sec
) >= 3)
8148 assert (xtensa_fetch_width
== 4);
8154 /* This will assert if it is not possible. */
8157 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8163 assert (fill_size
% 3 == 0);
8164 return (fill_size
/ 3);
8167 assert (fill_size
!= 1); /* Bad argument. */
8169 while (fill_size
> 1)
8172 if (fill_size
== 2 || fill_size
== 4)
8174 fill_size
-= insn_size
;
8177 assert (fill_size
!= 1); /* Bad algorithm. */
8183 get_text_align_nth_nop_size (offsetT fill_size
,
8185 bfd_boolean use_no_density
)
8192 assert (fill_size
!= 1); /* Bad argument. */
8194 while (fill_size
> 1)
8197 if (fill_size
== 2 || fill_size
== 4)
8199 fill_size
-= insn_size
;
8209 /* For the given fragment, find the appropriate address
8210 for it to begin at if we are using NOPs to align it. */
8213 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8215 /* The rule is: get next fragment's FIRST instruction. Find
8216 the smallest number of bytes that need to be added to
8217 ensure that the next fragment's FIRST instruction will fit
8220 E.G., 2 bytes : 0, 1, 2 mod 4
8223 If the FIRST instruction MIGHT be relaxed,
8224 assume that it will become a 3-byte instruction.
8226 Note again here that LOOP instructions are not bundleable,
8227 and this relaxation only applies to LOOP opcodes. */
8230 int first_insn_size
;
8232 addressT pre_opcode_bytes
;
8235 xtensa_opcode opcode
;
8236 bfd_boolean is_loop
;
8238 assert (fragP
->fr_type
== rs_machine_dependent
);
8239 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8241 /* Find the loop frag. */
8242 first_insn
= next_non_empty_frag (fragP
);
8243 /* Now find the first insn frag. */
8244 first_insn
= next_non_empty_frag (first_insn
);
8246 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8248 loop_insn_size
= xg_get_single_size (opcode
);
8250 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8251 pre_opcode_bytes
+= loop_insn_size
;
8253 /* For loops, the alignment depends on the size of the
8254 instruction following the loop, not the LOOP instruction. */
8256 if (first_insn
== NULL
)
8257 first_insn_size
= xtensa_fetch_width
;
8259 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8261 /* If it was 8, then we'll need a larger alignment for the section. */
8262 align_power
= get_text_align_power (first_insn_size
);
8263 record_alignment (now_seg
, align_power
);
8265 fill_size
= get_text_align_fill_size
8266 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8267 fragP
->tc_frag_data
.is_no_density
);
8269 return address
+ fill_size
;
8273 /* 3 mechanisms for relaxing an alignment:
8275 Align to a power of 2.
8276 Align so the next fragment's instruction does not cross a word boundary.
8277 Align the current instruction so that if the next instruction
8278 were 3 bytes, it would not cross a word boundary.
8282 zeros - This is easy; always insert zeros.
8283 nops - 3-byte and 2-byte instructions
8287 >=5 : 3-byte instruction + fn (n-3)
8288 widening - widen previous instructions. */
8291 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8293 addressT target_address
, loop_insn_offset
;
8295 xtensa_opcode loop_opcode
;
8296 bfd_boolean is_loop
;
8299 offsetT branch_align
;
8302 assert (fragP
->fr_type
== rs_machine_dependent
);
8303 switch (fragP
->fr_subtype
)
8305 case RELAX_DESIRE_ALIGN
:
8306 target_size
= next_frag_format_size (fragP
);
8307 if (target_size
== XTENSA_UNDEFINED
)
8309 align_power
= branch_align_power (now_seg
);
8310 branch_align
= 1 << align_power
;
8311 /* Don't count on the section alignment being as large as the target. */
8312 if (target_size
> branch_align
)
8313 target_size
= branch_align
;
8314 opt_diff
= get_text_align_fill_size (address
, align_power
,
8315 target_size
, FALSE
, FALSE
);
8317 *max_diff
= (opt_diff
+ branch_align
8318 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8319 assert (*max_diff
>= opt_diff
);
8322 case RELAX_ALIGN_NEXT_OPCODE
:
8323 /* The next non-empty frag after this one holds the LOOP instruction
8324 that needs to be aligned. The required alignment depends on the
8325 size of the next non-empty frag after the loop frag, i.e., the
8326 first instruction in the loop. */
8327 loop_frag
= next_non_empty_frag (fragP
);
8328 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8329 loop_insn_offset
= 0;
8330 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8333 /* If the loop has been expanded then the LOOP instruction
8334 could be at an offset from this fragment. */
8335 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8336 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8338 /* In an ideal world, which is what we are shooting for here,
8339 we wouldn't need to use any NOPs immediately prior to the
8340 LOOP instruction. If this approach fails, relax_frag_loop_align
8341 will call get_noop_aligned_address. */
8343 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8344 align_power
= get_text_align_power (target_size
);
8345 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8346 target_size
, FALSE
, FALSE
);
8348 *max_diff
= xtensa_fetch_width
8349 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8350 - target_size
+ opt_diff
;
8351 assert (*max_diff
>= opt_diff
);
8362 /* md_relax_frag Hook and Helper Functions. */
8364 static long relax_frag_loop_align (fragS
*, long);
8365 static long relax_frag_for_align (fragS
*, long);
8366 static long relax_frag_immed
8367 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8370 /* Return the number of bytes added to this fragment, given that the
8371 input has been stretched already by "stretch". */
8374 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8376 xtensa_isa isa
= xtensa_default_isa
;
8377 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8378 long new_stretch
= 0;
8382 static xtensa_insnbuf vbuf
= NULL
;
8383 int slot
, num_slots
;
8386 as_where (&file_name
, &line
);
8387 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8389 fragP
->tc_frag_data
.unreported_expansion
= 0;
8391 switch (fragP
->fr_subtype
)
8393 case RELAX_ALIGN_NEXT_OPCODE
:
8394 /* Always convert. */
8395 if (fragP
->tc_frag_data
.relax_seen
)
8396 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8399 case RELAX_LOOP_END
:
8403 case RELAX_LOOP_END_ADD_NOP
:
8404 /* Add a NOP and switch to .fill 0. */
8405 new_stretch
= relax_frag_add_nop (fragP
);
8409 case RELAX_DESIRE_ALIGN
:
8410 /* Do nothing. The narrowing before this frag will either align
8415 case RELAX_LITERAL_FINAL
:
8418 case RELAX_LITERAL_NR
:
8420 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8421 assert (unreported
== lit_size
);
8422 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8423 fragP
->fr_var
-= lit_size
;
8424 fragP
->fr_fix
+= lit_size
;
8430 vbuf
= xtensa_insnbuf_alloc (isa
);
8432 xtensa_insnbuf_from_chars
8433 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8434 fmt
= xtensa_format_decode (isa
, vbuf
);
8435 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8437 for (slot
= 0; slot
< num_slots
; slot
++)
8439 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8442 if (fragP
->tc_frag_data
.relax_seen
)
8443 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8447 case RELAX_IMMED_STEP1
:
8448 case RELAX_IMMED_STEP2
:
8449 case RELAX_IMMED_STEP3
:
8450 /* Place the immediate. */
8451 new_stretch
+= relax_frag_immed
8452 (now_seg
, fragP
, stretch
,
8453 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8454 fmt
, slot
, stretched_p
, FALSE
);
8458 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8464 case RELAX_LITERAL_POOL_BEGIN
:
8465 case RELAX_LITERAL_POOL_END
:
8466 case RELAX_MAYBE_UNREACHABLE
:
8467 case RELAX_MAYBE_DESIRE_ALIGN
:
8468 /* No relaxation required. */
8471 case RELAX_FILL_NOP
:
8472 case RELAX_UNREACHABLE
:
8473 if (fragP
->tc_frag_data
.relax_seen
)
8474 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8478 as_bad (_("bad relaxation state"));
8481 /* Tell gas we need another relaxation pass. */
8482 if (! fragP
->tc_frag_data
.relax_seen
)
8484 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8488 new_logical_line (file_name
, line
);
8494 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8496 addressT old_address
, old_next_address
, old_size
;
8497 addressT new_address
, new_next_address
, new_size
;
8500 /* All the frags with relax_frag_for_alignment prior to this one in the
8501 section have been done, hopefully eliminating the need for a NOP here.
8502 But, this will put it in if necessary. */
8504 /* Calculate the old address of this fragment and the next fragment. */
8505 old_address
= fragP
->fr_address
- stretch
;
8506 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8507 fragP
->tc_frag_data
.text_expansion
[0]);
8508 old_size
= old_next_address
- old_address
;
8510 /* Calculate the new address of this fragment and the next fragment. */
8511 new_address
= fragP
->fr_address
;
8513 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8514 new_size
= new_next_address
- new_address
;
8516 growth
= new_size
- old_size
;
8518 /* Fix up the text_expansion field and return the new growth. */
8519 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8524 /* Add a NOP instruction. */
8527 relax_frag_add_nop (fragS
*fragP
)
8529 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8530 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8531 assemble_nop (length
, nop_buf
);
8532 fragP
->tc_frag_data
.is_insn
= TRUE
;
8534 if (fragP
->fr_var
< length
)
8536 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8540 fragP
->fr_fix
+= length
;
8541 fragP
->fr_var
-= length
;
8546 static long future_alignment_required (fragS
*, long);
8549 relax_frag_for_align (fragS
*fragP
, long stretch
)
8551 /* Overview of the relaxation procedure for alignment:
8552 We can widen with NOPs or by widening instructions or by filling
8553 bytes after jump instructions. Find the opportune places and widen
8554 them if necessary. */
8559 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8560 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8561 || (fragP
->fr_subtype
== RELAX_SLOTS
8562 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8564 stretch_me
= future_alignment_required (fragP
, stretch
);
8565 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8571 /* We expanded on a previous pass. Can we shrink now? */
8572 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8573 if (shrink
<= stretch
&& stretch
> 0)
8575 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8581 /* Below here, diff > 0. */
8582 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8588 /* Return the address of the next frag that should be aligned.
8590 By "address" we mean the address it _would_ be at if there
8591 is no action taken to align it between here and the target frag.
8592 In other words, if no narrows and no fill nops are used between
8593 here and the frag to align, _even_if_ some of the frags we use
8594 to align targets have already expanded on a previous relaxation
8597 Also, count each frag that may be used to help align the target.
8599 Return 0 if there are no frags left in the chain that need to be
8603 find_address_of_next_align_frag (fragS
**fragPP
,
8607 bfd_boolean
*paddable
)
8609 fragS
*fragP
= *fragPP
;
8610 addressT address
= fragP
->fr_address
;
8612 /* Do not reset the counts to 0. */
8616 /* Limit this to a small search. */
8617 if (*widens
>= (int) xtensa_fetch_width
)
8622 address
+= fragP
->fr_fix
;
8624 if (fragP
->fr_type
== rs_fill
)
8625 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8626 else if (fragP
->fr_type
== rs_machine_dependent
)
8628 switch (fragP
->fr_subtype
)
8630 case RELAX_UNREACHABLE
:
8634 case RELAX_FILL_NOP
:
8636 if (!fragP
->tc_frag_data
.is_no_density
)
8641 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8646 address
+= total_frag_text_expansion (fragP
);;
8650 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8653 case RELAX_ALIGN_NEXT_OPCODE
:
8654 case RELAX_DESIRE_ALIGN
:
8658 case RELAX_MAYBE_UNREACHABLE
:
8659 case RELAX_MAYBE_DESIRE_ALIGN
:
8664 /* Just punt if we don't know the type. */
8671 /* Just punt if we don't know the type. */
8675 fragP
= fragP
->fr_next
;
8683 static long bytes_to_stretch (fragS
*, int, int, int, int);
8686 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8688 fragS
*this_frag
= fragP
;
8692 int narrow_nops
= 0;
8693 bfd_boolean paddable
= FALSE
;
8694 offsetT local_opt_diff
;
8697 int stretch_amount
= 0;
8698 int local_stretch_amount
;
8699 int global_stretch_amount
;
8701 address
= find_address_of_next_align_frag
8702 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8706 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8707 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8709 frag_wane (this_frag
);
8713 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8714 opt_diff
= local_opt_diff
;
8715 assert (opt_diff
>= 0);
8716 assert (max_diff
>= opt_diff
);
8721 fragP
= fragP
->fr_next
;
8723 while (fragP
&& opt_diff
< max_diff
&& address
)
8725 /* We only use these to determine if we can exit early
8726 because there will be plenty of ways to align future
8728 int glob_widens
= 0;
8731 bfd_boolean glob_pad
= 0;
8732 address
= find_address_of_next_align_frag
8733 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8734 /* If there is a padable portion, then skip. */
8735 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8740 offsetT next_m_diff
;
8741 offsetT next_o_diff
;
8743 /* Downrange frags haven't had stretch added to them yet. */
8746 /* The address also includes any text expansion from this
8747 frag in a previous pass, but we don't want that. */
8748 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8750 /* Assume we are going to move at least opt_diff. In
8751 reality, we might not be able to, but assuming that
8752 we will helps catch cases where moving opt_diff pushes
8753 the next target from aligned to unaligned. */
8754 address
+= opt_diff
;
8756 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8758 /* Now cleanup for the adjustments to address. */
8759 next_o_diff
+= opt_diff
;
8760 next_m_diff
+= opt_diff
;
8761 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8762 opt_diff
= next_o_diff
;
8763 if (next_m_diff
< max_diff
)
8764 max_diff
= next_m_diff
;
8765 fragP
= fragP
->fr_next
;
8769 /* If there are enough wideners in between, do it. */
8772 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8774 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8779 local_stretch_amount
8780 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8781 num_widens
, local_opt_diff
);
8782 global_stretch_amount
8783 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8784 num_widens
, opt_diff
);
8785 /* If the condition below is true, then the frag couldn't
8786 stretch the correct amount for the global case, so we just
8787 optimize locally. We'll rely on the subsequent frags to get
8788 the correct alignment in the global case. */
8789 if (global_stretch_amount
< local_stretch_amount
)
8790 stretch_amount
= local_stretch_amount
;
8792 stretch_amount
= global_stretch_amount
;
8794 if (this_frag
->fr_subtype
== RELAX_SLOTS
8795 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8796 assert (stretch_amount
<= 1);
8797 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8799 if (this_frag
->tc_frag_data
.is_no_density
)
8800 assert (stretch_amount
== 3 || stretch_amount
== 0);
8802 assert (stretch_amount
<= 3);
8805 return stretch_amount
;
8809 /* The idea: widen everything you can to get a target or loop aligned,
8810 then start using NOPs.
8812 When we must have a NOP, here is a table of how we decide
8813 (so you don't have to fight through the control flow below):
8815 wide_nops = the number of wide NOPs available for aligning
8816 narrow_nops = the number of narrow NOPs available for aligning
8817 (a subset of wide_nops)
8818 widens = the number of narrow instructions that should be widened
8825 b 0 1 1 (case 3a makes this case unnecessary)
8828 c 0 1 2 (case 4a makes this case unnecessary)
8831 c 0 2 1 (case 5b makes this case unnecessary)
8834 c 0 1 4 (case 6b makes this case unnecessary)
8835 d 1 1 1 (case 6a makes this case unnecessary)
8836 e 0 2 2 (case 6a makes this case unnecessary)
8837 f 0 3 0 (case 6a makes this case unnecessary)
8840 c 1 1 2 (case 7b makes this case unnecessary)
8841 d 0 1 5 (case 7a makes this case unnecessary)
8842 e 0 2 3 (case 7b makes this case unnecessary)
8843 f 0 3 1 (case 7b makes this case unnecessary)
8844 g 1 2 1 (case 7b makes this case unnecessary)
8848 bytes_to_stretch (fragS
*this_frag
,
8854 int bytes_short
= desired_diff
- num_widens
;
8856 assert (desired_diff
>= 0 && desired_diff
< 8);
8857 if (desired_diff
== 0)
8860 assert (wide_nops
> 0 || num_widens
> 0);
8862 /* Always prefer widening to NOP-filling. */
8863 if (bytes_short
< 0)
8865 /* There are enough RELAX_NARROW frags after this one
8866 to align the target without widening this frag in any way. */
8870 if (bytes_short
== 0)
8872 /* Widen every narrow between here and the align target
8873 and the align target will be properly aligned. */
8874 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8880 /* From here we will need at least one NOP to get an alignment.
8881 However, we may not be able to align at all, in which case,
8883 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8885 switch (desired_diff
)
8890 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8891 return 2; /* case 2 */
8897 return 3; /* case 3a */
8899 if (num_widens
>= 1 && wide_nops
== 1)
8900 return 3; /* case 4a */
8901 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8902 return 2; /* case 4b */
8905 if (num_widens
>= 2 && wide_nops
== 1)
8906 return 3; /* case 5a */
8907 /* We will need two nops. Are there enough nops
8908 between here and the align target? */
8909 if (wide_nops
< 2 || narrow_nops
== 0)
8911 /* Are there other nops closer that can serve instead? */
8912 if (wide_nops
> 2 && narrow_nops
> 1)
8914 /* Take the density one first, because there might not be
8915 another density one available. */
8916 if (!this_frag
->tc_frag_data
.is_no_density
)
8917 return 2; /* case 5b narrow */
8919 return 3; /* case 5b wide */
8923 return 3; /* case 6a */
8924 else if (num_widens
>= 3 && wide_nops
== 1)
8925 return 3; /* case 6b */
8928 if (wide_nops
== 1 && num_widens
>= 4)
8929 return 3; /* case 7a */
8930 else if (wide_nops
== 2 && num_widens
>= 1)
8931 return 3; /* case 7b */
8939 /* We will need a NOP no matter what, but should we widen
8940 this instruction to help?
8942 This is a RELAX_NARROW frag. */
8943 switch (desired_diff
)
8952 if (wide_nops
>= 1 && num_widens
== 1)
8953 return 1; /* case 4a */
8956 if (wide_nops
>= 1 && num_widens
== 2)
8957 return 1; /* case 5a */
8961 return 0; /* case 6a */
8962 else if (wide_nops
>= 1 && num_widens
== 3)
8963 return 1; /* case 6b */
8966 if (wide_nops
>= 1 && num_widens
== 4)
8967 return 1; /* case 7a */
8968 else if (wide_nops
>= 2 && num_widens
== 1)
8969 return 1; /* case 7b */
8982 relax_frag_immed (segT segP
,
8989 bfd_boolean estimate_only
)
8993 bfd_boolean negatable_branch
= FALSE
;
8994 bfd_boolean branch_jmp_to_next
= FALSE
;
8995 bfd_boolean from_wide_insn
= FALSE
;
8996 xtensa_isa isa
= xtensa_default_isa
;
8998 offsetT frag_offset
;
9001 int num_text_bytes
, num_literal_bytes
;
9002 int literal_diff
, total_text_diff
, this_text_diff
, first
;
9004 assert (fragP
->fr_opcode
!= NULL
);
9006 xg_clear_vinsn (&cur_vinsn
);
9007 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9008 if (cur_vinsn
.num_slots
> 1)
9009 from_wide_insn
= TRUE
;
9011 tinsn
= cur_vinsn
.slots
[slot
];
9012 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9014 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9017 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9018 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9020 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9022 old_size
= xtensa_format_length (isa
, fmt
);
9024 /* Special case: replace a branch to the next instruction with a NOP.
9025 This is required to work around a hardware bug in T1040.0 and also
9026 serves as an optimization. */
9028 if (branch_jmp_to_next
9029 && ((old_size
== 2) || (old_size
== 3))
9030 && !next_frag_is_loop_target (fragP
))
9033 /* Here is the fun stuff: Get the immediate field from this
9034 instruction. If it fits, we are done. If not, find the next
9035 instruction sequence that fits. */
9037 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9038 istack_init (&istack
);
9039 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9040 min_steps
, stretch
);
9041 if (num_steps
< min_steps
)
9043 as_fatal (_("internal error: relaxation failed"));
9047 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
9049 as_fatal (_("internal error: relaxation requires too many steps"));
9053 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9055 /* Figure out the number of bytes needed. */
9057 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9059 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9061 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9064 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9068 num_text_bytes
+= old_size
;
9069 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9070 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9073 total_text_diff
= num_text_bytes
- old_size
;
9074 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9076 /* It MUST get larger. If not, we could get an infinite loop. */
9077 assert (num_text_bytes
>= 0);
9078 assert (literal_diff
>= 0);
9079 assert (total_text_diff
>= 0);
9081 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9082 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9083 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9084 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9086 /* Find the associated expandable literal for this. */
9087 if (literal_diff
!= 0)
9089 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9092 assert (literal_diff
== 4);
9093 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9095 /* We expect that the literal section state has NOT been
9097 assert (lit_fragP
->fr_type
== rs_machine_dependent
9098 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9099 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9101 /* We need to mark this section for another iteration
9107 if (negatable_branch
&& istack
.ninsn
> 1)
9108 update_next_frag_state (fragP
);
9110 return this_text_diff
;
9114 /* md_convert_frag Hook and Helper Functions. */
9116 static void convert_frag_align_next_opcode (fragS
*);
9117 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9118 static void convert_frag_fill_nop (fragS
*);
9119 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9122 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9124 static xtensa_insnbuf vbuf
= NULL
;
9125 xtensa_isa isa
= xtensa_default_isa
;
9132 as_where (&file_name
, &line
);
9133 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9135 switch (fragp
->fr_subtype
)
9137 case RELAX_ALIGN_NEXT_OPCODE
:
9138 /* Always convert. */
9139 convert_frag_align_next_opcode (fragp
);
9142 case RELAX_DESIRE_ALIGN
:
9143 /* Do nothing. If not aligned already, too bad. */
9147 case RELAX_LITERAL_FINAL
:
9152 vbuf
= xtensa_insnbuf_alloc (isa
);
9154 xtensa_insnbuf_from_chars
9155 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9156 fmt
= xtensa_format_decode (isa
, vbuf
);
9157 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9159 for (slot
= 0; slot
< num_slots
; slot
++)
9161 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9164 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9168 case RELAX_IMMED_STEP1
:
9169 case RELAX_IMMED_STEP2
:
9170 case RELAX_IMMED_STEP3
:
9171 /* Place the immediate. */
9174 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9179 /* This is OK because some slots could have
9180 relaxations and others have none. */
9186 case RELAX_UNREACHABLE
:
9187 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9188 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9189 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9193 case RELAX_MAYBE_UNREACHABLE
:
9194 case RELAX_MAYBE_DESIRE_ALIGN
:
9198 case RELAX_FILL_NOP
:
9199 convert_frag_fill_nop (fragp
);
9202 case RELAX_LITERAL_NR
:
9203 if (use_literal_section
)
9205 /* This should have been handled during relaxation. When
9206 relaxing a code segment, literals sometimes need to be
9207 added to the corresponding literal segment. If that
9208 literal segment has already been relaxed, then we end up
9209 in this situation. Marking the literal segments as data
9210 would make this happen less often (since GAS always relaxes
9211 code before data), but we could still get into trouble if
9212 there are instructions in a segment that is not marked as
9213 containing code. Until we can implement a better solution,
9214 cheat and adjust the addresses of all the following frags.
9215 This could break subsequent alignments, but the linker's
9216 literal coalescing will do that anyway. */
9219 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9220 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9221 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9224 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9228 as_bad (_("invalid relaxation fragment result"));
9233 new_logical_line (file_name
, line
);
9238 convert_frag_align_next_opcode (fragS
*fragp
)
9240 char *nop_buf
; /* Location for Writing. */
9241 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9242 addressT aligned_address
;
9246 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9248 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9249 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9250 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9252 for (nop
= 0; nop
< nop_count
; nop
++)
9255 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9257 assemble_nop (nop_size
, nop_buf
);
9258 nop_buf
+= nop_size
;
9261 fragp
->fr_fix
+= fill_size
;
9262 fragp
->fr_var
-= fill_size
;
9267 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9269 TInsn tinsn
, single_target
;
9270 int size
, old_size
, diff
;
9271 offsetT frag_offset
;
9274 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9276 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9278 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9279 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9280 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9285 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9287 /* No conversion. */
9292 assert (fragP
->fr_opcode
!= NULL
);
9294 /* Frags in this relaxation state should only contain
9295 single instruction bundles. */
9296 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9298 /* Just convert it to a wide form.... */
9300 old_size
= xg_get_single_size (tinsn
.opcode
);
9302 tinsn_init (&single_target
);
9303 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9305 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9307 as_bad (_("unable to widen instruction"));
9311 size
= xg_get_single_size (single_target
.opcode
);
9312 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9315 diff
= size
- old_size
;
9317 assert (diff
<= fragP
->fr_var
);
9318 fragP
->fr_var
-= diff
;
9319 fragP
->fr_fix
+= diff
;
9327 convert_frag_fill_nop (fragS
*fragP
)
9329 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9330 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9331 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9332 - fragP
->fr_address
- fragP
->fr_fix
));
9335 /* No conversion. */
9339 assemble_nop (size
, loc
);
9340 fragP
->tc_frag_data
.is_insn
= TRUE
;
9341 fragP
->fr_var
-= size
;
9342 fragP
->fr_fix
+= size
;
9347 static fixS
*fix_new_exp_in_seg
9348 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9349 bfd_reloc_code_real_type
);
9350 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9353 convert_frag_immed (segT segP
,
9359 char *immed_instr
= fragP
->fr_opcode
;
9361 bfd_boolean expanded
= FALSE
;
9362 bfd_boolean branch_jmp_to_next
= FALSE
;
9363 char *fr_opcode
= fragP
->fr_opcode
;
9364 xtensa_isa isa
= xtensa_default_isa
;
9365 bfd_boolean from_wide_insn
= FALSE
;
9367 bfd_boolean is_loop
;
9369 assert (fr_opcode
!= NULL
);
9371 xg_clear_vinsn (&cur_vinsn
);
9373 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9374 if (cur_vinsn
.num_slots
> 1)
9375 from_wide_insn
= TRUE
;
9377 orig_tinsn
= cur_vinsn
.slots
[slot
];
9378 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9380 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9382 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9383 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9385 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9387 /* Conversion just inserts a NOP and marks the fix as completed. */
9388 bytes
= xtensa_format_length (isa
, fmt
);
9391 cur_vinsn
.slots
[slot
].opcode
=
9392 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9393 cur_vinsn
.slots
[slot
].ntok
= 0;
9397 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9398 assert (bytes
== 2 || bytes
== 3);
9399 build_nop (&cur_vinsn
.slots
[0], bytes
);
9400 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9402 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9403 xtensa_insnbuf_to_chars
9404 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9409 /* Here is the fun stuff: Get the immediate field from this
9410 instruction. If it fits, we're done. If not, find the next
9411 instruction sequence that fits. */
9415 symbolS
*lit_sym
= NULL
;
9417 int target_offset
= 0;
9420 symbolS
*gen_label
= NULL
;
9421 offsetT frag_offset
;
9422 bfd_boolean first
= TRUE
;
9423 bfd_boolean last_is_jump
;
9425 /* It does not fit. Find something that does and
9426 convert immediately. */
9427 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9428 istack_init (&istack
);
9429 xg_assembly_relax (&istack
, &orig_tinsn
,
9430 segP
, fragP
, frag_offset
, min_steps
, 0);
9432 old_size
= xtensa_format_length (isa
, fmt
);
9434 /* Assemble this right inline. */
9436 /* First, create the mapping from a label name to the REAL label. */
9438 for (i
= 0; i
< istack
.ninsn
; i
++)
9440 TInsn
*tinsn
= &istack
.insn
[i
];
9443 switch (tinsn
->insn_type
)
9446 if (lit_sym
!= NULL
)
9447 as_bad (_("multiple literals in expansion"));
9448 /* First find the appropriate space in the literal pool. */
9449 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9450 if (lit_frag
== NULL
)
9451 as_bad (_("no registered fragment for literal"));
9452 if (tinsn
->ntok
!= 1)
9453 as_bad (_("number of literal tokens != 1"));
9455 /* Set the literal symbol and add a fixup. */
9456 lit_sym
= lit_frag
->fr_symbol
;
9460 if (align_targets
&& !is_loop
)
9462 fragS
*unreach
= fragP
->fr_next
;
9463 while (!(unreach
->fr_type
== rs_machine_dependent
9464 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9465 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9467 unreach
= unreach
->fr_next
;
9470 assert (unreach
->fr_type
== rs_machine_dependent
9471 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9472 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9474 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9476 assert (gen_label
== NULL
);
9477 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9478 fr_opcode
- fragP
->fr_literal
9479 + target_offset
, fragP
);
9483 if (first
&& from_wide_insn
)
9485 target_offset
+= xtensa_format_length (isa
, fmt
);
9487 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9488 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9491 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9498 last_is_jump
= FALSE
;
9499 for (i
= 0; i
< istack
.ninsn
; i
++)
9501 TInsn
*tinsn
= &istack
.insn
[i
];
9505 bfd_reloc_code_real_type reloc_type
;
9507 switch (tinsn
->insn_type
)
9510 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9511 /* Already checked. */
9512 assert (lit_frag
!= NULL
);
9513 assert (lit_sym
!= NULL
);
9514 assert (tinsn
->ntok
== 1);
9516 target_seg
= S_GET_SEGMENT (lit_sym
);
9517 assert (target_seg
);
9518 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9519 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9520 &tinsn
->tok
[0], FALSE
, reloc_type
);
9527 xg_resolve_labels (tinsn
, gen_label
);
9528 xg_resolve_literals (tinsn
, lit_sym
);
9529 if (from_wide_insn
&& first
)
9532 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9534 cur_vinsn
.slots
[slot
] = *tinsn
;
9538 cur_vinsn
.slots
[slot
].opcode
=
9539 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9540 cur_vinsn
.slots
[slot
].ntok
= 0;
9542 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9543 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9544 (unsigned char *) immed_instr
, 0);
9545 fragP
->tc_frag_data
.is_insn
= TRUE
;
9546 size
= xtensa_format_length (isa
, fmt
);
9547 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9550 (tinsn
, immed_instr
+ size
, fragP
,
9551 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9552 size
+= xg_get_single_size (tinsn
->opcode
);
9557 size
= xg_get_single_size (tinsn
->opcode
);
9558 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9559 immed_instr
- fragP
->fr_literal
, TRUE
);
9561 immed_instr
+= size
;
9567 diff
= total_size
- old_size
;
9571 assert (diff
<= fragP
->fr_var
);
9572 fragP
->fr_var
-= diff
;
9573 fragP
->fr_fix
+= diff
;
9576 /* Check for undefined immediates in LOOP instructions. */
9580 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9581 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9583 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9586 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9587 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9589 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9594 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9595 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9597 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9599 /* Add an expansion note on the expanded instruction. */
9600 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9601 &orig_tinsn
.tok
[0], TRUE
,
9602 BFD_RELOC_XTENSA_ASM_EXPAND
);
9607 /* Add a new fix expression into the desired segment. We have to
9608 switch to that segment to do this. */
9611 fix_new_exp_in_seg (segT new_seg
,
9618 bfd_reloc_code_real_type r_type
)
9622 subsegT subseg
= now_subseg
;
9624 assert (new_seg
!= 0);
9625 subseg_set (new_seg
, new_subseg
);
9627 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9628 subseg_set (seg
, subseg
);
9633 /* Relax a loop instruction so that it can span loop >256 bytes.
9639 addi as, as, lo8 (label-.L1)
9640 addmi as, as, mid8 (label-.L1)
9651 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9656 unsigned long target
;
9657 static xtensa_insnbuf insnbuf
= NULL
;
9658 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9659 xtensa_isa isa
= xtensa_default_isa
;
9660 addressT loop_offset
;
9661 addressT addi_offset
= 9;
9662 addressT addmi_offset
= 12;
9667 insnbuf
= xtensa_insnbuf_alloc (isa
);
9669 /* Get the loop offset. */
9670 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9672 /* Validate that there really is a LOOP at the loop_offset. Because
9673 loops are not bundleable, we can assume that the instruction will be
9675 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9676 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9678 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9679 addi_offset
+= loop_offset
;
9680 addmi_offset
+= loop_offset
;
9682 assert (tinsn
->ntok
== 2);
9683 if (tinsn
->tok
[1].X_op
== O_constant
)
9684 target
= tinsn
->tok
[1].X_add_number
;
9685 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9687 /* Find the fragment. */
9688 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9689 assert (S_GET_SEGMENT (sym
) == segP
9690 || S_GET_SEGMENT (sym
) == absolute_section
);
9691 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9695 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9699 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9700 loop_length_hi
= loop_length
& ~0x0ff;
9701 loop_length_lo
= loop_length
& 0x0ff;
9702 if (loop_length_lo
>= 128)
9704 loop_length_lo
-= 256;
9705 loop_length_hi
+= 256;
9708 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9709 32512. If the loop is larger than that, then we just fail. */
9710 if (loop_length_hi
> 32512)
9711 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9712 _("loop too long for LOOP instruction"));
9714 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9715 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9717 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9718 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9720 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9721 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9723 fragP
->tc_frag_data
.is_insn
= TRUE
;
9724 xtensa_insnbuf_to_chars
9725 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9727 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9728 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9729 xtensa_insnbuf_to_chars
9730 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9732 /* Walk through all of the frags from here to the loop end
9733 and mark them as no_transform to keep them from being modified
9734 by the linker. If we ever have a relocation for the
9735 addi/addmi of the difference of two symbols we can remove this. */
9738 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9739 next_fragP
= next_fragP
->fr_next
)
9741 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9742 if (next_fragP
->tc_frag_data
.is_loop_target
)
9744 if (target_count
== 2)
9750 /* A map that keeps information on a per-subsegment basis. This is
9751 maintained during initial assembly, but is invalid once the
9752 subsegments are smashed together. I.E., it cannot be used during
9755 typedef struct subseg_map_struct
9763 float total_freq
; /* fall-through + branch target frequency */
9764 float target_freq
; /* branch target frequency alone */
9766 struct subseg_map_struct
*next
;
9770 static subseg_map
*sseg_map
= NULL
;
9773 get_subseg_info (segT seg
, subsegT subseg
)
9775 subseg_map
*subseg_e
;
9777 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9779 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9787 add_subseg_info (segT seg
, subsegT subseg
)
9789 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9790 memset (subseg_e
, 0, sizeof (subseg_map
));
9791 subseg_e
->seg
= seg
;
9792 subseg_e
->subseg
= subseg
;
9793 subseg_e
->flags
= 0;
9794 /* Start off considering every branch target very important. */
9795 subseg_e
->target_freq
= 1.0;
9796 subseg_e
->total_freq
= 1.0;
9797 subseg_e
->next
= sseg_map
;
9798 sseg_map
= subseg_e
;
9804 get_last_insn_flags (segT seg
, subsegT subseg
)
9806 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9808 return subseg_e
->flags
;
9814 set_last_insn_flags (segT seg
,
9819 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9821 subseg_e
= add_subseg_info (seg
, subseg
);
9823 subseg_e
->flags
|= fl
;
9825 subseg_e
->flags
&= ~fl
;
9830 get_subseg_total_freq (segT seg
, subsegT subseg
)
9832 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9834 return subseg_e
->total_freq
;
9840 get_subseg_target_freq (segT seg
, subsegT subseg
)
9842 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9844 return subseg_e
->target_freq
;
9850 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9852 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9854 subseg_e
= add_subseg_info (seg
, subseg
);
9855 subseg_e
->total_freq
= total_f
;
9856 subseg_e
->target_freq
= target_f
;
9860 /* Segment Lists and emit_state Stuff. */
9863 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9868 segT literal_section
= head
->seg
;
9870 /* Move the literal section to the front of the section list. */
9871 assert (literal_section
);
9872 if (literal_section
!= stdoutput
->sections
)
9874 bfd_section_list_remove (stdoutput
, literal_section
);
9875 bfd_section_list_prepend (stdoutput
, literal_section
);
9882 static void mark_literal_frags (seg_list
*);
9885 xtensa_move_literals (void)
9888 frchainS
*frchain_from
, *frchain_to
;
9889 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9890 fragS
**frag_splice
;
9893 fixS
*fix
, *next_fix
, **fix_splice
;
9896 mark_literal_frags (literal_head
->next
);
9898 if (use_literal_section
)
9901 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9903 /* Keep the literals for .init and .fini in separate sections. */
9904 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9905 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9908 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9909 search_frag
= frchain_from
->frch_root
;
9910 literal_pool
= NULL
;
9912 frag_splice
= &(frchain_from
->frch_root
);
9914 while (!search_frag
->tc_frag_data
.literal_frag
)
9916 assert (search_frag
->fr_fix
== 0
9917 || search_frag
->fr_type
== rs_align
);
9918 search_frag
= search_frag
->fr_next
;
9921 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9922 == RELAX_LITERAL_POOL_BEGIN
);
9923 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9925 /* Make sure that all the frags in this series are closed, and
9926 that there is at least one left over of zero-size. This
9927 prevents us from making a segment with an frchain without any
9929 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9930 xtensa_set_frag_assembly_state (frag_now
);
9931 last_frag
= frag_now
;
9932 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9933 xtensa_set_frag_assembly_state (frag_now
);
9935 while (search_frag
!= frag_now
)
9937 next_frag
= search_frag
->fr_next
;
9939 /* First, move the frag out of the literal section and
9940 to the appropriate place. */
9941 if (search_frag
->tc_frag_data
.literal_frag
)
9943 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9944 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9945 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9946 assert (frchain_to
);
9948 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
9949 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9951 *frag_splice
= next_frag
;
9952 search_frag
->fr_next
= insert_after
->fr_next
;
9953 insert_after
->fr_next
= search_frag
;
9954 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9955 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
9957 /* Now move any fixups associated with this frag to the
9959 fix
= frchain_from
->fix_root
;
9960 fix_splice
= &(frchain_from
->fix_root
);
9963 next_fix
= fix
->fx_next
;
9964 if (fix
->fx_frag
== search_frag
)
9966 *fix_splice
= next_fix
;
9967 fix
->fx_next
= frchain_to
->fix_root
;
9968 frchain_to
->fix_root
= fix
;
9969 if (frchain_to
->fix_tail
== NULL
)
9970 frchain_to
->fix_tail
= fix
;
9973 fix_splice
= &(fix
->fx_next
);
9976 search_frag
= next_frag
;
9979 if (frchain_from
->fix_root
!= NULL
)
9981 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9982 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9984 assert (frchain_from
->fix_root
== NULL
);
9986 frchain_from
->fix_tail
= NULL
;
9987 xtensa_restore_emit_state (&state
);
9990 /* Now fix up the SEGMENT value for all the literal symbols. */
9991 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9993 symbolS
*lit_sym
= lit
->sym
;
9994 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9996 S_SET_SEGMENT (lit_sym
, dest_seg
);
10001 /* Walk over all the frags for segments in a list and mark them as
10002 containing literals. As clunky as this is, we can't rely on frag_var
10003 and frag_variant to get called in all situations. */
10006 mark_literal_frags (seg_list
*segment
)
10008 frchainS
*frchain_from
;
10009 fragS
*search_frag
;
10013 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10014 search_frag
= frchain_from
->frch_root
;
10015 while (search_frag
)
10017 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10018 search_frag
= search_frag
->fr_next
;
10020 segment
= segment
->next
;
10026 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10028 /* Move all of the sections in the section list to come
10029 after "after" in the gnu segment list. */
10034 segT literal_section
= head
->seg
;
10036 /* Move the literal section after "after". */
10037 assert (literal_section
);
10038 if (literal_section
!= after
)
10040 bfd_section_list_remove (stdoutput
, literal_section
);
10041 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10049 /* Push all the literal segments to the end of the gnu list. */
10052 xtensa_reorder_segments (void)
10059 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10065 /* Now that we have the last section, push all the literal
10066 sections to the end. */
10067 xtensa_reorder_seg_list (literal_head
, last_sec
);
10069 /* Now perform the final error check. */
10070 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10072 assert (new_count
== old_count
);
10076 /* Change the emit state (seg, subseg, and frag related stuff) to the
10077 correct location. Return a emit_state which can be passed to
10078 xtensa_restore_emit_state to return to current fragment. */
10081 xtensa_switch_to_literal_fragment (emit_state
*result
)
10083 if (directive_state
[directive_absolute_literals
])
10085 segT lit4_seg
= cache_literal_section (TRUE
);
10086 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10089 xtensa_switch_to_non_abs_literal_fragment (result
);
10091 /* Do a 4-byte align here. */
10092 frag_align (2, 0, 0);
10093 record_alignment (now_seg
, 2);
10098 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10100 static bfd_boolean recursive
= FALSE
;
10101 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10103 bfd_boolean is_init
=
10104 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10105 bfd_boolean is_fini
=
10106 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10108 if (pool_location
== NULL
10109 && !use_literal_section
10111 && !is_init
&& ! is_fini
)
10113 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10115 /* When we mark a literal pool location, we want to put a frag in
10116 the literal pool that points to it. But to do that, we want to
10117 switch_to_literal_fragment. But literal sections don't have
10118 literal pools, so their location is always null, so we would
10119 recurse forever. This is kind of hacky, but it works. */
10122 xtensa_mark_literal_pool_location ();
10126 lit_seg
= cache_literal_section (FALSE
);
10127 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10129 if (!use_literal_section
10130 && !is_init
&& !is_fini
10131 && get_literal_pool_location (now_seg
) != pool_location
)
10133 /* Close whatever frag is there. */
10134 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10135 xtensa_set_frag_assembly_state (frag_now
);
10136 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10137 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10138 xtensa_set_frag_assembly_state (frag_now
);
10143 /* Call this function before emitting data into the literal section.
10144 This is a helper function for xtensa_switch_to_literal_fragment.
10145 This is similar to a .section new_now_seg subseg. */
10148 xtensa_switch_section_emit_state (emit_state
*state
,
10150 subsegT new_now_subseg
)
10152 state
->name
= now_seg
->name
;
10153 state
->now_seg
= now_seg
;
10154 state
->now_subseg
= now_subseg
;
10155 state
->generating_literals
= generating_literals
;
10156 generating_literals
++;
10157 subseg_set (new_now_seg
, new_now_subseg
);
10161 /* Use to restore the emitting into the normal place. */
10164 xtensa_restore_emit_state (emit_state
*state
)
10166 generating_literals
= state
->generating_literals
;
10167 subseg_set (state
->now_seg
, state
->now_subseg
);
10171 /* Predicate function used to look up a section in a particular group. */
10174 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10176 const char *gname
= inf
;
10177 const char *group_name
= elf_group_name (sec
);
10179 return (group_name
== gname
10180 || (group_name
!= NULL
10182 && strcmp (group_name
, gname
) == 0));
10186 /* Get the literal section to be used for the current text section.
10187 The result may be cached in the default_lit_sections structure. */
10190 cache_literal_section (bfd_boolean use_abs_literals
)
10192 const char *text_name
, *group_name
= 0;
10193 char *base_name
, *name
, *suffix
;
10195 segT seg
, current_section
;
10196 int current_subsec
;
10197 bfd_boolean linkonce
= FALSE
;
10199 /* Save the current section/subsection. */
10200 current_section
= now_seg
;
10201 current_subsec
= now_subseg
;
10203 /* Clear the cached values if they are no longer valid. */
10204 if (now_seg
!= default_lit_sections
.current_text_seg
)
10206 default_lit_sections
.current_text_seg
= now_seg
;
10207 default_lit_sections
.lit_seg
= NULL
;
10208 default_lit_sections
.lit4_seg
= NULL
;
10211 /* Check if the literal section is already cached. */
10212 if (use_abs_literals
)
10213 pcached
= &default_lit_sections
.lit4_seg
;
10215 pcached
= &default_lit_sections
.lit_seg
;
10220 text_name
= default_lit_sections
.lit_prefix
;
10221 if (! text_name
|| ! *text_name
)
10223 text_name
= segment_name (current_section
);
10224 group_name
= elf_group_name (current_section
);
10225 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10228 base_name
= use_abs_literals
? ".lit4" : ".literal";
10231 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10232 sprintf (name
, "%s.%s", base_name
, group_name
);
10234 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10236 suffix
= strchr (text_name
+ linkonce_len
, '.');
10238 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10239 + (suffix
? strlen (suffix
) : 0));
10240 strcpy (name
, ".gnu.linkonce");
10241 strcat (name
, base_name
);
10243 strcat (name
, suffix
);
10248 /* If the section name ends with ".text", then replace that suffix
10249 instead of appending an additional suffix. */
10250 size_t len
= strlen (text_name
);
10251 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10254 name
= xmalloc (len
+ strlen (base_name
) + 1);
10255 strcpy (name
, text_name
);
10256 strcpy (name
+ len
, base_name
);
10259 /* Canonicalize section names to allow renaming literal sections.
10260 The group name, if any, came from the current text section and
10261 has already been canonicalized. */
10262 name
= tc_canonicalize_symbol_name (name
);
10264 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10265 (void *) group_name
);
10270 seg
= subseg_force_new (name
, 0);
10272 if (! use_abs_literals
)
10274 /* Add the newly created literal segment to the list. */
10275 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10277 n
->next
= literal_head
->next
;
10278 literal_head
->next
= n
;
10281 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10282 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10283 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10285 elf_group_name (seg
) = group_name
;
10287 bfd_set_section_flags (stdoutput
, seg
, flags
);
10288 bfd_set_section_alignment (stdoutput
, seg
, 2);
10292 subseg_set (current_section
, current_subsec
);
10297 /* Property Tables Stuff. */
10299 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10300 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10301 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10303 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10304 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10306 static bfd_boolean
get_frag_is_literal (const fragS
*);
10307 static void xtensa_create_property_segments
10308 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10309 static void xtensa_create_xproperty_segments
10310 (frag_flags_fn
, const char *, xt_section_type
);
10311 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10312 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10313 static void add_xt_block_frags
10314 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10315 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10316 static void xtensa_frag_flags_init (frag_flags
*);
10317 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10318 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10319 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10321 /* Set up property tables after relaxation. */
10324 xtensa_post_relax_hook (void)
10326 xtensa_move_seg_list_to_beginning (literal_head
);
10328 xtensa_find_unmarked_state_frags ();
10329 xtensa_mark_frags_for_org ();
10330 xtensa_mark_difference_of_two_symbols ();
10332 xtensa_create_property_segments (get_frag_is_literal
,
10334 XTENSA_LIT_SEC_NAME
,
10336 xtensa_create_xproperty_segments (get_frag_property_flags
,
10337 XTENSA_PROP_SEC_NAME
,
10340 if (warn_unaligned_branch_targets
)
10341 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10342 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10346 /* This function is only meaningful after xtensa_move_literals. */
10349 get_frag_is_literal (const fragS
*fragP
)
10351 assert (fragP
!= NULL
);
10352 return fragP
->tc_frag_data
.is_literal
;
10357 xtensa_create_property_segments (frag_predicate property_function
,
10358 frag_predicate end_property_function
,
10359 const char *section_name_base
,
10360 xt_section_type sec_type
)
10364 /* Walk over all of the current segments.
10365 Walk over each fragment
10366 For each non-empty fragment,
10367 Build a property record (append where possible). */
10369 for (seclist
= &stdoutput
->sections
;
10370 seclist
&& *seclist
;
10371 seclist
= &(*seclist
)->next
)
10373 segT sec
= *seclist
;
10376 flags
= bfd_get_section_flags (stdoutput
, sec
);
10377 if (flags
& SEC_DEBUGGING
)
10379 if (!(flags
& SEC_ALLOC
))
10382 if (section_has_property (sec
, property_function
))
10384 segment_info_type
*xt_seg_info
;
10385 xtensa_block_info
**xt_blocks
;
10386 segT prop_sec
= xtensa_get_property_section (sec
, section_name_base
);
10388 prop_sec
->output_section
= prop_sec
;
10389 subseg_set (prop_sec
, 0);
10390 xt_seg_info
= seg_info (prop_sec
);
10391 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10393 /* Walk over all of the frchains here and add new sections. */
10394 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10395 end_property_function
);
10399 /* Now we fill them out.... */
10401 for (seclist
= &stdoutput
->sections
;
10402 seclist
&& *seclist
;
10403 seclist
= &(*seclist
)->next
)
10405 segment_info_type
*seginfo
;
10406 xtensa_block_info
*block
;
10407 segT sec
= *seclist
;
10409 seginfo
= seg_info (sec
);
10410 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10414 xtensa_block_info
*cur_block
;
10416 bfd_size_type rec_size
;
10418 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10421 rec_size
= num_recs
* 8;
10422 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10429 subseg_set (sec
, 0);
10430 frag_data
= frag_more (rec_size
);
10432 for (i
= 0; i
< num_recs
; i
++)
10436 /* Write the fixup. */
10437 assert (cur_block
);
10438 fix
= fix_new (frag_now
, i
* 8, 4,
10439 section_symbol (cur_block
->sec
),
10441 FALSE
, BFD_RELOC_32
);
10442 fix
->fx_file
= "<internal>";
10445 /* Write the length. */
10446 md_number_to_chars (&frag_data
[4 + i
* 8],
10447 cur_block
->size
, 4);
10448 cur_block
= cur_block
->next
;
10450 frag_wane (frag_now
);
10452 frag_wane (frag_now
);
10460 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10461 const char *section_name_base
,
10462 xt_section_type sec_type
)
10466 /* Walk over all of the current segments.
10467 Walk over each fragment.
10468 For each fragment that has instructions,
10469 build an instruction record (append where possible). */
10471 for (seclist
= &stdoutput
->sections
;
10472 seclist
&& *seclist
;
10473 seclist
= &(*seclist
)->next
)
10475 segT sec
= *seclist
;
10478 flags
= bfd_get_section_flags (stdoutput
, sec
);
10479 if ((flags
& SEC_DEBUGGING
)
10480 || !(flags
& SEC_ALLOC
)
10481 || (flags
& SEC_MERGE
))
10484 if (section_has_xproperty (sec
, flag_fn
))
10486 segment_info_type
*xt_seg_info
;
10487 xtensa_block_info
**xt_blocks
;
10488 segT prop_sec
= xtensa_get_property_section (sec
, section_name_base
);
10490 prop_sec
->output_section
= prop_sec
;
10491 subseg_set (prop_sec
, 0);
10492 xt_seg_info
= seg_info (prop_sec
);
10493 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10495 /* Walk over all of the frchains here and add new sections. */
10496 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10500 /* Now we fill them out.... */
10502 for (seclist
= &stdoutput
->sections
;
10503 seclist
&& *seclist
;
10504 seclist
= &(*seclist
)->next
)
10506 segment_info_type
*seginfo
;
10507 xtensa_block_info
*block
;
10508 segT sec
= *seclist
;
10510 seginfo
= seg_info (sec
);
10511 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10515 xtensa_block_info
*cur_block
;
10517 bfd_size_type rec_size
;
10519 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10522 rec_size
= num_recs
* (8 + 4);
10523 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10524 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10531 subseg_set (sec
, 0);
10532 frag_data
= frag_more (rec_size
);
10534 for (i
= 0; i
< num_recs
; i
++)
10538 /* Write the fixup. */
10539 assert (cur_block
);
10540 fix
= fix_new (frag_now
, i
* 12, 4,
10541 section_symbol (cur_block
->sec
),
10543 FALSE
, BFD_RELOC_32
);
10544 fix
->fx_file
= "<internal>";
10547 /* Write the length. */
10548 md_number_to_chars (&frag_data
[4 + i
* 12],
10549 cur_block
->size
, 4);
10550 md_number_to_chars (&frag_data
[8 + i
* 12],
10551 frag_flags_to_number (&cur_block
->flags
),
10553 cur_block
= cur_block
->next
;
10555 frag_wane (frag_now
);
10557 frag_wane (frag_now
);
10565 section_has_property (segT sec
, frag_predicate property_function
)
10567 segment_info_type
*seginfo
= seg_info (sec
);
10570 if (seginfo
&& seginfo
->frchainP
)
10572 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10574 if (property_function (fragP
)
10575 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10584 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10586 segment_info_type
*seginfo
= seg_info (sec
);
10589 if (seginfo
&& seginfo
->frchainP
)
10591 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10593 frag_flags prop_flags
;
10594 property_function (fragP
, &prop_flags
);
10595 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10603 /* Two types of block sections exist right now: literal and insns. */
10606 add_xt_block_frags (segT sec
,
10607 xtensa_block_info
**xt_block
,
10608 frag_predicate property_function
,
10609 frag_predicate end_property_function
)
10611 bfd_vma seg_offset
;
10614 /* Build it if needed. */
10615 while (*xt_block
!= NULL
)
10616 xt_block
= &(*xt_block
)->next
;
10617 /* We are either at NULL at the beginning or at the end. */
10619 /* Walk through the frags. */
10622 if (seg_info (sec
)->frchainP
)
10624 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10626 fragP
= fragP
->fr_next
)
10628 if (property_function (fragP
)
10629 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10631 if (*xt_block
!= NULL
)
10633 if ((*xt_block
)->offset
+ (*xt_block
)->size
10634 == fragP
->fr_address
)
10635 (*xt_block
)->size
+= fragP
->fr_fix
;
10637 xt_block
= &((*xt_block
)->next
);
10639 if (*xt_block
== NULL
)
10641 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10642 xmalloc (sizeof (xtensa_block_info
));
10643 new_block
->sec
= sec
;
10644 new_block
->offset
= fragP
->fr_address
;
10645 new_block
->size
= fragP
->fr_fix
;
10646 new_block
->next
= NULL
;
10647 xtensa_frag_flags_init (&new_block
->flags
);
10648 *xt_block
= new_block
;
10650 if (end_property_function
10651 && end_property_function (fragP
))
10653 xt_block
= &((*xt_block
)->next
);
10661 /* Break the encapsulation of add_xt_prop_frags here. */
10664 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10666 if (prop_flags
->is_literal
10667 || prop_flags
->is_insn
10668 || prop_flags
->is_data
10669 || prop_flags
->is_unreachable
)
10676 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10678 memset (prop_flags
, 0, sizeof (frag_flags
));
10683 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10685 xtensa_frag_flags_init (prop_flags
);
10686 if (fragP
->tc_frag_data
.is_literal
)
10687 prop_flags
->is_literal
= TRUE
;
10688 if (fragP
->tc_frag_data
.is_specific_opcode
10689 || fragP
->tc_frag_data
.is_no_transform
)
10691 prop_flags
->is_no_transform
= TRUE
;
10692 if (xtensa_frag_flags_is_empty (prop_flags
))
10693 prop_flags
->is_data
= TRUE
;
10695 if (fragP
->tc_frag_data
.is_unreachable
)
10696 prop_flags
->is_unreachable
= TRUE
;
10697 else if (fragP
->tc_frag_data
.is_insn
)
10699 prop_flags
->is_insn
= TRUE
;
10700 if (fragP
->tc_frag_data
.is_loop_target
)
10701 prop_flags
->insn
.is_loop_target
= TRUE
;
10702 if (fragP
->tc_frag_data
.is_branch_target
)
10703 prop_flags
->insn
.is_branch_target
= TRUE
;
10704 if (fragP
->tc_frag_data
.is_no_density
)
10705 prop_flags
->insn
.is_no_density
= TRUE
;
10706 if (fragP
->tc_frag_data
.use_absolute_literals
)
10707 prop_flags
->insn
.is_abslit
= TRUE
;
10709 if (fragP
->tc_frag_data
.is_align
)
10711 prop_flags
->is_align
= TRUE
;
10712 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10713 if (xtensa_frag_flags_is_empty (prop_flags
))
10714 prop_flags
->is_data
= TRUE
;
10720 frag_flags_to_number (const frag_flags
*prop_flags
)
10723 if (prop_flags
->is_literal
)
10724 num
|= XTENSA_PROP_LITERAL
;
10725 if (prop_flags
->is_insn
)
10726 num
|= XTENSA_PROP_INSN
;
10727 if (prop_flags
->is_data
)
10728 num
|= XTENSA_PROP_DATA
;
10729 if (prop_flags
->is_unreachable
)
10730 num
|= XTENSA_PROP_UNREACHABLE
;
10731 if (prop_flags
->insn
.is_loop_target
)
10732 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10733 if (prop_flags
->insn
.is_branch_target
)
10735 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10736 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10739 if (prop_flags
->insn
.is_no_density
)
10740 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10741 if (prop_flags
->is_no_transform
)
10742 num
|= XTENSA_PROP_NO_TRANSFORM
;
10743 if (prop_flags
->insn
.is_no_reorder
)
10744 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10745 if (prop_flags
->insn
.is_abslit
)
10746 num
|= XTENSA_PROP_INSN_ABSLIT
;
10748 if (prop_flags
->is_align
)
10750 num
|= XTENSA_PROP_ALIGN
;
10751 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10759 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10760 const frag_flags
*prop_flags_2
)
10762 /* Cannot combine with an end marker. */
10764 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10766 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10768 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10771 if (prop_flags_1
->is_insn
)
10773 /* Properties of the beginning of the frag. */
10774 if (prop_flags_2
->insn
.is_loop_target
)
10776 if (prop_flags_2
->insn
.is_branch_target
)
10778 if (prop_flags_1
->insn
.is_no_density
!=
10779 prop_flags_2
->insn
.is_no_density
)
10781 if (prop_flags_1
->is_no_transform
!=
10782 prop_flags_2
->is_no_transform
)
10784 if (prop_flags_1
->insn
.is_no_reorder
!=
10785 prop_flags_2
->insn
.is_no_reorder
)
10787 if (prop_flags_1
->insn
.is_abslit
!=
10788 prop_flags_2
->insn
.is_abslit
)
10792 if (prop_flags_1
->is_align
)
10800 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10803 unsigned align_bits
;
10805 if (!xt_block
->flags
.is_align
)
10806 return xt_block
->size
;
10808 end_addr
= xt_block
->offset
+ xt_block
->size
;
10809 align_bits
= xt_block
->flags
.alignment
;
10810 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10811 return end_addr
- xt_block
->offset
;
10816 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10817 const xtensa_block_info
*xt_block_2
)
10819 if (xt_block
->sec
!= xt_block_2
->sec
)
10821 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10822 != xt_block_2
->offset
)
10825 if (xt_block_2
->size
== 0
10826 && (!xt_block_2
->flags
.is_unreachable
10827 || xt_block
->flags
.is_unreachable
))
10829 if (xt_block_2
->flags
.is_align
10830 && xt_block
->flags
.is_align
)
10832 /* Nothing needed. */
10833 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10838 if (xt_block_2
->flags
.is_align
)
10840 /* Push alignment to previous entry. */
10841 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10842 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10847 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10848 &xt_block_2
->flags
))
10851 xt_block
->size
+= xt_block_2
->size
;
10853 if (xt_block_2
->flags
.is_align
)
10855 xt_block
->flags
.is_align
= TRUE
;
10856 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10864 add_xt_prop_frags (segT sec
,
10865 xtensa_block_info
**xt_block
,
10866 frag_flags_fn property_function
)
10868 bfd_vma seg_offset
;
10871 /* Build it if needed. */
10872 while (*xt_block
!= NULL
)
10874 xt_block
= &(*xt_block
)->next
;
10876 /* We are either at NULL at the beginning or at the end. */
10878 /* Walk through the frags. */
10881 if (seg_info (sec
)->frchainP
)
10883 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
10884 fragP
= fragP
->fr_next
)
10886 xtensa_block_info tmp_block
;
10887 tmp_block
.sec
= sec
;
10888 tmp_block
.offset
= fragP
->fr_address
;
10889 tmp_block
.size
= fragP
->fr_fix
;
10890 tmp_block
.next
= NULL
;
10891 property_function (fragP
, &tmp_block
.flags
);
10893 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10894 /* && fragP->fr_fix != 0) */
10896 if ((*xt_block
) == NULL
10897 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10899 xtensa_block_info
*new_block
;
10900 if ((*xt_block
) != NULL
)
10901 xt_block
= &(*xt_block
)->next
;
10902 new_block
= (xtensa_block_info
*)
10903 xmalloc (sizeof (xtensa_block_info
));
10904 *new_block
= tmp_block
;
10905 *xt_block
= new_block
;
10913 /* op_placement_info_table */
10915 /* op_placement_info makes it easier to determine which
10916 ops can go in which slots. */
10919 init_op_placement_info_table (void)
10921 xtensa_isa isa
= xtensa_default_isa
;
10922 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10923 xtensa_opcode opcode
;
10926 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10928 op_placement_table
= (op_placement_info_table
)
10929 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10930 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10932 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10934 op_placement_info
*opi
= &op_placement_table
[opcode
];
10935 /* FIXME: Make tinsn allocation dynamic. */
10936 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10937 as_fatal (_("too many operands in instruction"));
10938 opi
->narrowest
= XTENSA_UNDEFINED
;
10939 opi
->narrowest_size
= 0x7F;
10940 opi
->narrowest_slot
= 0;
10942 opi
->num_formats
= 0;
10944 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10946 opi
->slots
[fmt
] = 0;
10947 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10949 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10951 int fmt_length
= xtensa_format_length (isa
, fmt
);
10953 set_bit (fmt
, opi
->formats
);
10954 set_bit (slot
, opi
->slots
[fmt
]);
10955 if (fmt_length
< opi
->narrowest_size
10956 || (fmt_length
== opi
->narrowest_size
10957 && (xtensa_format_num_slots (isa
, fmt
)
10958 < xtensa_format_num_slots (isa
,
10961 opi
->narrowest
= fmt
;
10962 opi
->narrowest_size
= fmt_length
;
10963 opi
->narrowest_slot
= slot
;
10968 opi
->num_formats
++;
10971 xtensa_insnbuf_free (isa
, ibuf
);
10976 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10978 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10982 /* If the opcode is available in a single slot format, return its size. */
10985 xg_get_single_size (xtensa_opcode opcode
)
10987 return op_placement_table
[opcode
].narrowest_size
;
10991 static xtensa_format
10992 xg_get_single_format (xtensa_opcode opcode
)
10994 return op_placement_table
[opcode
].narrowest
;
10999 xg_get_single_slot (xtensa_opcode opcode
)
11001 return op_placement_table
[opcode
].narrowest_slot
;
11005 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11008 istack_init (IStack
*stack
)
11010 memset (stack
, 0, sizeof (IStack
));
11016 istack_empty (IStack
*stack
)
11018 return (stack
->ninsn
== 0);
11023 istack_full (IStack
*stack
)
11025 return (stack
->ninsn
== MAX_ISTACK
);
11029 /* Return a pointer to the top IStack entry.
11030 It is an error to call this if istack_empty () is TRUE. */
11033 istack_top (IStack
*stack
)
11035 int rec
= stack
->ninsn
- 1;
11036 assert (!istack_empty (stack
));
11037 return &stack
->insn
[rec
];
11041 /* Add a new TInsn to an IStack.
11042 It is an error to call this if istack_full () is TRUE. */
11045 istack_push (IStack
*stack
, TInsn
*insn
)
11047 int rec
= stack
->ninsn
;
11048 assert (!istack_full (stack
));
11049 stack
->insn
[rec
] = *insn
;
11054 /* Clear space for the next TInsn on the IStack and return a pointer
11055 to it. It is an error to call this if istack_full () is TRUE. */
11058 istack_push_space (IStack
*stack
)
11060 int rec
= stack
->ninsn
;
11062 assert (!istack_full (stack
));
11063 insn
= &stack
->insn
[rec
];
11070 /* Remove the last pushed instruction. It is an error to call this if
11071 istack_empty () returns TRUE. */
11074 istack_pop (IStack
*stack
)
11076 int rec
= stack
->ninsn
- 1;
11077 assert (!istack_empty (stack
));
11079 tinsn_init (&stack
->insn
[rec
]);
11083 /* TInsn functions. */
11086 tinsn_init (TInsn
*dst
)
11088 memset (dst
, 0, sizeof (TInsn
));
11092 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11095 tinsn_has_symbolic_operands (const TInsn
*insn
)
11098 int n
= insn
->ntok
;
11100 assert (insn
->insn_type
== ITYPE_INSN
);
11102 for (i
= 0; i
< n
; ++i
)
11104 switch (insn
->tok
[i
].X_op
)
11118 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11120 xtensa_isa isa
= xtensa_default_isa
;
11122 int n
= insn
->ntok
;
11124 assert (insn
->insn_type
== ITYPE_INSN
);
11126 for (i
= 0; i
< n
; ++i
)
11128 switch (insn
->tok
[i
].X_op
)
11136 /* Errors for these types are caught later. */
11141 /* Symbolic immediates are only allowed on the last immediate
11142 operand. At this time, CONST16 is the only opcode where we
11143 support non-PC-relative relocations. */
11144 if (i
!= get_relaxable_immed (insn
->opcode
)
11145 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11146 && insn
->opcode
!= xtensa_const16_opcode
))
11148 as_bad (_("invalid symbolic operand"));
11157 /* For assembly code with complex expressions (e.g. subtraction),
11158 we have to build them in the literal pool so that
11159 their results are calculated correctly after relaxation.
11160 The relaxation only handles expressions that
11161 boil down to SYMBOL + OFFSET. */
11164 tinsn_has_complex_operands (const TInsn
*insn
)
11167 int n
= insn
->ntok
;
11168 assert (insn
->insn_type
== ITYPE_INSN
);
11169 for (i
= 0; i
< n
; ++i
)
11171 switch (insn
->tok
[i
].X_op
)
11187 /* Encode a TInsn opcode and its constant operands into slotbuf.
11188 Return TRUE if there is a symbol in the immediate field. This
11189 function assumes that:
11190 1) The number of operands are correct.
11191 2) The insn_type is ITYPE_INSN.
11192 3) The opcode can be encoded in the specified format and slot.
11193 4) Operands are either O_constant or O_symbol, and all constants fit. */
11196 tinsn_to_slotbuf (xtensa_format fmt
,
11199 xtensa_insnbuf slotbuf
)
11201 xtensa_isa isa
= xtensa_default_isa
;
11202 xtensa_opcode opcode
= tinsn
->opcode
;
11203 bfd_boolean has_fixup
= FALSE
;
11204 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11207 assert (tinsn
->insn_type
== ITYPE_INSN
);
11208 if (noperands
!= tinsn
->ntok
)
11209 as_fatal (_("operand number mismatch"));
11211 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11213 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11214 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11218 for (i
= 0; i
< noperands
; i
++)
11220 expressionS
*expr
= &tinsn
->tok
[i
];
11226 switch (expr
->X_op
)
11229 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11231 /* The register number has already been checked in
11232 expression_maybe_register, so we don't need to check here. */
11233 opnd_value
= expr
->X_add_number
;
11234 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11235 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11238 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11242 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11244 as_where (&file_name
, &line
);
11245 /* It is a constant and we called this function
11246 then we have to try to fit it. */
11247 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11248 expr
->X_add_number
, file_name
, line
);
11261 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11262 into a multi-slot instruction, fill the other slots with NOPs.
11263 Return TRUE if there is a symbol in the immediate field. See also the
11264 assumptions listed for tinsn_to_slotbuf. */
11267 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11269 static xtensa_insnbuf slotbuf
= 0;
11270 static vliw_insn vinsn
;
11271 xtensa_isa isa
= xtensa_default_isa
;
11272 bfd_boolean has_fixup
= FALSE
;
11277 slotbuf
= xtensa_insnbuf_alloc (isa
);
11278 xg_init_vinsn (&vinsn
);
11281 xg_clear_vinsn (&vinsn
);
11283 bundle_tinsn (tinsn
, &vinsn
);
11285 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11287 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11289 /* Only one slot may have a fix-up because the rest contains NOPs. */
11291 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11292 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11299 /* Check the instruction arguments. Return TRUE on failure. */
11302 tinsn_check_arguments (const TInsn
*insn
)
11304 xtensa_isa isa
= xtensa_default_isa
;
11305 xtensa_opcode opcode
= insn
->opcode
;
11307 if (opcode
== XTENSA_UNDEFINED
)
11309 as_bad (_("invalid opcode"));
11313 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11315 as_bad (_("too few operands"));
11319 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11321 as_bad (_("too many operands"));
11328 /* Load an instruction from its encoded form. */
11331 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11335 xg_init_vinsn (&vinsn
);
11336 vinsn_from_chars (&vinsn
, f
);
11338 *tinsn
= vinsn
.slots
[slot
];
11339 xg_free_vinsn (&vinsn
);
11344 tinsn_from_insnbuf (TInsn
*tinsn
,
11345 xtensa_insnbuf slotbuf
,
11350 xtensa_isa isa
= xtensa_default_isa
;
11352 /* Find the immed. */
11353 tinsn_init (tinsn
);
11354 tinsn
->insn_type
= ITYPE_INSN
;
11355 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11356 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11357 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11358 for (i
= 0; i
< tinsn
->ntok
; i
++)
11360 set_expr_const (&tinsn
->tok
[i
],
11361 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11362 tinsn
->opcode
, i
));
11367 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11370 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11372 xtensa_opcode opcode
= tinsn
->opcode
;
11375 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11377 opnum
= get_relaxable_immed (opcode
);
11378 assert (opnum
>= 0);
11379 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11380 fragP
->tc_frag_data
.slot_symbols
[slot
],
11381 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11387 get_num_stack_text_bytes (IStack
*istack
)
11390 int text_bytes
= 0;
11392 for (i
= 0; i
< istack
->ninsn
; i
++)
11394 TInsn
*tinsn
= &istack
->insn
[i
];
11395 if (tinsn
->insn_type
== ITYPE_INSN
)
11396 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11403 get_num_stack_literal_bytes (IStack
*istack
)
11408 for (i
= 0; i
< istack
->ninsn
; i
++)
11410 TInsn
*tinsn
= &istack
->insn
[i
];
11411 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11418 /* vliw_insn functions. */
11421 xg_init_vinsn (vliw_insn
*v
)
11424 xtensa_isa isa
= xtensa_default_isa
;
11426 xg_clear_vinsn (v
);
11428 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11429 if (v
->insnbuf
== NULL
)
11430 as_fatal (_("out of memory"));
11432 for (i
= 0; i
< MAX_SLOTS
; i
++)
11434 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11435 if (v
->slotbuf
[i
] == NULL
)
11436 as_fatal (_("out of memory"));
11442 xg_clear_vinsn (vliw_insn
*v
)
11446 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11448 v
->format
= XTENSA_UNDEFINED
;
11450 v
->inside_bundle
= FALSE
;
11452 if (xt_saved_debug_type
!= DEBUG_NONE
)
11453 debug_type
= xt_saved_debug_type
;
11455 for (i
= 0; i
< MAX_SLOTS
; i
++)
11456 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11461 vinsn_has_specific_opcodes (vliw_insn
*v
)
11465 for (i
= 0; i
< v
->num_slots
; i
++)
11467 if (v
->slots
[i
].is_specific_opcode
)
11475 xg_free_vinsn (vliw_insn
*v
)
11478 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11479 for (i
= 0; i
< MAX_SLOTS
; i
++)
11480 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11484 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11485 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11488 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11491 bfd_boolean record_fixup
)
11493 xtensa_isa isa
= xtensa_default_isa
;
11494 xtensa_format fmt
= vinsn
->format
;
11495 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11497 bfd_boolean has_fixup
= FALSE
;
11499 xtensa_format_encode (isa
, fmt
, insnbuf
);
11501 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11503 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11504 bfd_boolean tinsn_has_fixup
=
11505 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11506 vinsn
->slotbuf
[slot
]);
11508 xtensa_format_set_slot (isa
, fmt
, slot
,
11509 insnbuf
, vinsn
->slotbuf
[slot
]);
11510 if (tinsn_has_fixup
)
11513 xtensa_opcode opcode
= tinsn
->opcode
;
11514 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11517 for (i
= 0; i
< noperands
; i
++)
11519 expressionS
* expr
= &tinsn
->tok
[i
];
11520 switch (expr
->X_op
)
11525 if (get_relaxable_immed (opcode
) == i
)
11527 /* Add a fix record for the instruction, except if this
11528 function is being called prior to relaxation, i.e.,
11529 if record_fixup is false, and the instruction might
11530 be relaxed later. */
11532 || tinsn
->is_specific_opcode
11533 || !xg_is_relaxable_insn (tinsn
, 0))
11535 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11536 frag_offset
- fragP
->fr_literal
);
11540 if (expr
->X_op
!= O_symbol
)
11541 as_bad (_("invalid operand"));
11542 tinsn
->symbol
= expr
->X_add_symbol
;
11543 tinsn
->offset
= expr
->X_add_number
;
11547 as_bad (_("symbolic operand not allowed"));
11555 as_bad (_("expression too complex"));
11567 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11569 static xtensa_insnbuf insnbuf
= NULL
;
11570 static xtensa_insnbuf slotbuf
= NULL
;
11573 xtensa_isa isa
= xtensa_default_isa
;
11577 insnbuf
= xtensa_insnbuf_alloc (isa
);
11578 slotbuf
= xtensa_insnbuf_alloc (isa
);
11581 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11582 fmt
= xtensa_format_decode (isa
, insnbuf
);
11583 if (fmt
== XTENSA_UNDEFINED
)
11584 as_fatal (_("cannot decode instruction format"));
11585 vinsn
->format
= fmt
;
11586 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11588 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11590 TInsn
*tinsn
= &vinsn
->slots
[i
];
11591 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11592 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11597 /* Expression utilities. */
11599 /* Return TRUE if the expression is an integer constant. */
11602 expr_is_const (const expressionS
*s
)
11604 return (s
->X_op
== O_constant
);
11608 /* Get the expression constant.
11609 Calling this is illegal if expr_is_const () returns TRUE. */
11612 get_expr_const (const expressionS
*s
)
11614 assert (expr_is_const (s
));
11615 return s
->X_add_number
;
11619 /* Set the expression to a constant value. */
11622 set_expr_const (expressionS
*s
, offsetT val
)
11624 s
->X_op
= O_constant
;
11625 s
->X_add_number
= val
;
11626 s
->X_add_symbol
= NULL
;
11627 s
->X_op_symbol
= NULL
;
11632 expr_is_register (const expressionS
*s
)
11634 return (s
->X_op
== O_register
);
11638 /* Get the expression constant.
11639 Calling this is illegal if expr_is_const () returns TRUE. */
11642 get_expr_register (const expressionS
*s
)
11644 assert (expr_is_register (s
));
11645 return s
->X_add_number
;
11649 /* Set the expression to a symbol + constant offset. */
11652 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11654 s
->X_op
= O_symbol
;
11655 s
->X_add_symbol
= sym
;
11656 s
->X_op_symbol
= NULL
; /* unused */
11657 s
->X_add_number
= offset
;
11661 /* Return TRUE if the two expressions are equal. */
11664 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11666 if (s1
->X_op
!= s2
->X_op
)
11668 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11670 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11672 if (s1
->X_add_number
!= s2
->X_add_number
)
11679 copy_expr (expressionS
*dst
, const expressionS
*src
)
11681 memcpy (dst
, src
, sizeof (expressionS
));
11685 /* Support for the "--rename-section" option. */
11687 struct rename_section_struct
11691 struct rename_section_struct
*next
;
11694 static struct rename_section_struct
*section_rename
;
11697 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11698 entries to the section_rename list. Note: Specifying multiple
11699 renamings separated by colons is not documented and is retained only
11700 for backward compatibility. */
11703 build_section_rename (const char *arg
)
11705 struct rename_section_struct
*r
;
11706 char *this_arg
= NULL
;
11707 char *next_arg
= NULL
;
11709 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11711 char *old_name
, *new_name
;
11715 next_arg
= strchr (this_arg
, ':');
11723 old_name
= this_arg
;
11724 new_name
= strchr (this_arg
, '=');
11726 if (*old_name
== '\0')
11728 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11731 if (!new_name
|| new_name
[1] == '\0')
11733 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11740 /* Check for invalid section renaming. */
11741 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11743 if (strcmp (r
->old_name
, old_name
) == 0)
11744 as_bad (_("section %s renamed multiple times"), old_name
);
11745 if (strcmp (r
->new_name
, new_name
) == 0)
11746 as_bad (_("multiple sections remapped to output section %s"),
11751 r
= (struct rename_section_struct
*)
11752 xmalloc (sizeof (struct rename_section_struct
));
11753 r
->old_name
= xstrdup (old_name
);
11754 r
->new_name
= xstrdup (new_name
);
11755 r
->next
= section_rename
;
11756 section_rename
= r
;
11762 xtensa_section_rename (char *name
)
11764 struct rename_section_struct
*r
= section_rename
;
11766 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11768 if (strcmp (r
->old_name
, name
) == 0)
11769 return r
->new_name
;