gas/config/tc-xtensa.c

   1 /* tc-xtensa.c -- Assemble Xtensa instructions.
   2    Copyright 2003, 2004 Free Software Foundation, Inc.
   3
   4    This file is part of GAS, the GNU Assembler.
   5
   6    GAS is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2, or (at your option)
   9    any later version.
  10
  11    GAS is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to
  18    the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  19    MA 02111-1307, USA.  */
  20
  21 #include <string.h>
  22 #include <limits.h>
  23 #include "as.h"
  24 #include "sb.h"
  25 #include "safe-ctype.h"
  26 #include "tc-xtensa.h"
  27 #include "frags.h"
  28 #include "subsegs.h"
  29 #include "xtensa-relax.h"
  30 #include "xtensa-istack.h"
  31 #include "dwarf2dbg.h"
  32 #include "struc-symbol.h"
  33 #include "xtensa-config.h"
  34
  35 #ifndef uint32
  36 #define uint32 unsigned int
  37 #endif
  38 #ifndef int32
  39 #define int32 signed int
  40 #endif
  41
  42 /* Notes:
  43
  44    Naming conventions (used somewhat inconsistently):
  45       The xtensa_ functions are exported
  46       The xg_ functions are internal
  47
  48    We also have a couple of different extensibility mechanisms.
  49    1) The idiom replacement:
  50       This is used when a line is first parsed to
  51       replace an instruction pattern with another instruction
  52       It is currently limited to replacements of instructions
  53       with constant operands.
  54    2) The xtensa-relax.c mechanism that has stronger instruction
  55       replacement patterns.  When an instruction's immediate field
  56       does not fit the next instruction sequence is attempted.
  57       In addition, "narrow" opcodes are supported this way.  */
  58
  59
  60 /* Define characters with special meanings to GAS.  */
  61 const char comment_chars[] = "#";
  62 const char line_comment_chars[] = "#";
  63 const char line_separator_chars[] = ";";
  64 const char EXP_CHARS[] = "eE";
  65 const char FLT_CHARS[] = "rRsSfFdDxXpP";
  66
  67
  68 /* Flags to indicate whether the hardware supports the density and
  69    absolute literals options.  */
  70
  71 bfd_boolean density_supported = XCHAL_HAVE_DENSITY;
  72 bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
  73
  74 /* Maximum width we would pad an unreachable frag to get alignment.  */
  75 #define UNREACHABLE_MAX_WIDTH  8
  76
  77 static vliw_insn cur_vinsn;
  78
  79 size_t xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
  80
  81 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
  82
  83 /* Some functions are only valid in the front end.  This variable
  84    allows us to assert that we haven't crossed over into the
  85    back end.  */
  86 static bfd_boolean past_xtensa_end = FALSE;
  87
  88 /* Flags for properties of the last instruction in a segment.  */
  89 #define FLAG_IS_A0_WRITER       0x1
  90 #define FLAG_IS_BAD_LOOPEND     0x2
  91
  92
  93 /* We define a special segment names ".literal" to place literals
  94    into.  The .fini and .init sections are special because they
  95    contain code that is moved together by the linker.  We give them
  96    their own special .fini.literal and .init.literal sections.  */
  97
  98 #define LITERAL_SECTION_NAME            xtensa_section_rename (".literal")
  99 #define LIT4_SECTION_NAME               xtensa_section_rename (".lit4")
 100 #define FINI_SECTION_NAME               xtensa_section_rename (".fini")
 101 #define INIT_SECTION_NAME               xtensa_section_rename (".init")
 102 #define FINI_LITERAL_SECTION_NAME       xtensa_section_rename (".fini.literal")
 103 #define INIT_LITERAL_SECTION_NAME       xtensa_section_rename (".init.literal")
 104
 105
 106 /* This type is used for the directive_stack to keep track of the
 107    state of the literal collection pools.  */
 108
 109 typedef struct lit_state_struct
 110 {
 111   const char *lit_seg_name;
 112   const char *lit4_seg_name;
 113   const char *init_lit_seg_name;
 114   const char *fini_lit_seg_name;
 115   segT lit_seg;
 116   segT lit4_seg;
 117   segT init_lit_seg;
 118   segT fini_lit_seg;
 119 } lit_state;
 120
 121 static lit_state default_lit_sections;
 122
 123
 124 /* We keep lists of literal segments.  The seg_list type is the node
 125    for such a list.  The *_literal_head locals are the heads of the
 126    various lists.  All of these lists have a dummy node at the start.  */
 127
 128 typedef struct seg_list_struct
 129 {
 130   struct seg_list_struct *next;
 131   segT seg;
 132 } seg_list;
 133
 134 static seg_list literal_head_h;
 135 static seg_list *literal_head = &literal_head_h;
 136 static seg_list init_literal_head_h;
 137 static seg_list *init_literal_head = &init_literal_head_h;
 138 static seg_list fini_literal_head_h;
 139 static seg_list *fini_literal_head = &fini_literal_head_h;
 140
 141
 142 /* Lists of symbols.  We keep a list of symbols that label the current
 143    instruction, so that we can adjust the symbols when inserting alignment
 144    for various instructions.  We also keep a list of all the symbols on
 145    literals, so that we can fix up those symbols when the literals are
 146    later moved into the text sections.  */
 147
 148 typedef struct sym_list_struct
 149 {
 150   struct sym_list_struct *next;
 151   symbolS *sym;
 152 } sym_list;
 153
 154 static sym_list *insn_labels = NULL;
 155 static sym_list *free_insn_labels = NULL;
 156 static sym_list *saved_insn_labels = NULL;
 157
 158 static sym_list *literal_syms;
 159
 160
 161 /* Flags to determine whether to prefer const16 or l32r
 162    if both options are available.  */
 163 int prefer_const16 = 0;
 164 int prefer_l32r = 0;
 165
 166 /* Global flag to indicate when we are emitting literals.  */
 167 int generating_literals = 0;
 168
 169 /* The following PROPERTY table definitions are copied from
 170    <elf/xtensa.h> and must be kept in sync with the code there.  */
 171
 172 /* Flags in the property tables to specify whether blocks of memory
 173    are literals, instructions, data, or unreachable.  For
 174    instructions, blocks that begin loop targets and branch targets are
 175    designated.  Blocks that do not allow density, instruction
 176    reordering or transformation are also specified.  Finally, for
 177    branch targets, branch target alignment priority is included.
 178    Alignment of the next block is specified in the current block
 179    and the size of the current block does not include any fill required
 180    to align to the next block.  */
 181
 182 #define XTENSA_PROP_LITERAL             0x00000001
 183 #define XTENSA_PROP_INSN                0x00000002
 184 #define XTENSA_PROP_DATA                0x00000004
 185 #define XTENSA_PROP_UNREACHABLE         0x00000008
 186 /* Instruction only properties at beginning of code.  */
 187 #define XTENSA_PROP_INSN_LOOP_TARGET    0x00000010
 188 #define XTENSA_PROP_INSN_BRANCH_TARGET  0x00000020
 189 /* Instruction only properties about code.  */
 190 #define XTENSA_PROP_INSN_NO_DENSITY     0x00000040
 191 #define XTENSA_PROP_INSN_NO_REORDER     0x00000080
 192 #define XTENSA_PROP_INSN_NO_TRANSFORM   0x00000100
 193
 194 /*  Branch target alignment information.  This transmits information
 195     to the linker optimization about the priority of aligning a
 196     particular block for branch target alignment: None, low priority,
 197     high priority, or required.  These only need to be checked in
 198     instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
 199     Common usage is
 200
 201     switch (GET_XTENSA_PROP_BT_ALIGN (flags))
 202     case XTENSA_PROP_BT_ALIGN_NONE:
 203     case XTENSA_PROP_BT_ALIGN_LOW:
 204     case XTENSA_PROP_BT_ALIGN_HIGH:
 205     case XTENSA_PROP_BT_ALIGN_REQUIRE:
 206 */
 207 #define XTENSA_PROP_BT_ALIGN_MASK       0x00000600
 208
 209 /* No branch target alignment.  */
 210 #define XTENSA_PROP_BT_ALIGN_NONE       0x0
 211 /* Low priority branch target alignment.  */
 212 #define XTENSA_PROP_BT_ALIGN_LOW        0x1
 213 /* High priority branch target alignment.  */
 214 #define XTENSA_PROP_BT_ALIGN_HIGH       0x2
 215 /* Required branch target alignment.  */
 216 #define XTENSA_PROP_BT_ALIGN_REQUIRE    0x3
 217
 218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
 219   (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
 220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
 221   (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
 222     (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
 223
 224
 225 /* Alignment is specified in the block BEFORE the one that needs
 226    alignment.  Up to 5 bits.  Use GET_XTENSA_PROP_ALIGNMENT(flags) to
 227    get the required alignment specified as a power of 2.  Use
 228    SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
 229    alignment.  Be careful of side effects since the SET will evaluate
 230    flags twice.  Also, note that the SIZE of a block in the property
 231    table does not include the alignment size, so the alignment fill
 232    must be calculated to determine if two blocks are contiguous.
 233    TEXT_ALIGN is not currently implemented but is a placeholder for a
 234    possible future implementation.  */
 235
 236 #define XTENSA_PROP_ALIGN               0x00000800
 237
 238 #define XTENSA_PROP_ALIGNMENT_MASK      0x0001f000
 239
 240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
 241   (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
 242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
 243   (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
 244     (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
 245
 246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
 247
 248
 249 /* Structure for saving instruction and alignment per-fragment data
 250    that will be written to the object file.  This structure is
 251    equivalent to the actual data that will be written out to the file
 252    but is easier to use.   We provide a conversion to file flags
 253    in frag_flags_to_number.  */
 254
 255 typedef struct frag_flags_struct frag_flags;
 256
 257 struct frag_flags_struct
 258 {
 259   /* is_literal should only be used after xtensa_move_literals.
 260      If you need to check if you are generating a literal fragment,
 261      then use the generating_literals global.  */
 262
 263   unsigned is_literal : 1;
 264   unsigned is_insn : 1;
 265   unsigned is_data : 1;
 266   unsigned is_unreachable : 1;
 267
 268   struct
 269   {
 270     unsigned is_loop_target : 1;
 271     unsigned is_branch_target : 1; /* Branch targets have a priority.  */
 272     unsigned bt_align_priority : 2;
 273
 274     unsigned is_no_density : 1;
 275     /* no_longcalls flag does not need to be placed in the object file.  */
 276     /* is_specific_opcode implies no_transform.  */
 277     unsigned is_no_transform : 1;
 278
 279     unsigned is_no_reorder : 1;
 280
 281     /* Uses absolute literal addressing for l32r.  */
 282     unsigned is_abslit : 1;
 283   } insn;
 284   unsigned is_align : 1;
 285   unsigned alignment : 5;
 286 };
 287
 288
 289 /* Structure for saving information about a block of property data
 290    for frags that have the same flags.  */
 291 struct xtensa_block_info_struct
 292 {
 293   segT sec;
 294   bfd_vma offset;
 295   size_t size;
 296   frag_flags flags;
 297   struct xtensa_block_info_struct *next;
 298 };
 299
 300
 301 /* Structure for saving the current state before emitting literals.  */
 302 typedef struct emit_state_struct
 303 {
 304   const char *name;
 305   segT now_seg;
 306   subsegT now_subseg;
 307   int generating_literals;
 308 } emit_state;
 309
 310
 311 /* A map that keeps information on a per-subsegment basis.  This is
 312    maintained during initial assembly, but is invalid once the
 313    subsegments are smashed together.  I.E., it cannot be used during
 314    the relaxation.  */
 315
 316 typedef struct subseg_map_struct
 317 {
 318   /* the key */
 319   segT seg;
 320   subsegT subseg;
 321
 322   /* the data */
 323   unsigned flags;
 324   /* the fall-through frequency + the branch target frequency
 325      typically used for the instruction after a call */
 326   float cur_total_freq;
 327   /* the branch target frequency alone */
 328   float cur_target_freq;
 329
 330   struct subseg_map_struct *next;
 331 } subseg_map;
 332
 333
 334 /* Opcode placement information */
 335
 336 typedef unsigned long long bitfield;
 337 #define bit_is_set(bit, bf)     ((bf) & (0x01ll << (bit)))
 338 #define set_bit(bit, bf)        ((bf) |= (0x01ll << (bit)))
 339 #define clear_bit(bit, bf)      ((bf) &= ~(0x01ll << (bit)))
 340
 341 #define MAX_FORMATS 32
 342
 343 typedef struct op_placement_info_struct
 344 {
 345   int num_formats;
 346   /* A number describing how restrictive the issue is for this
 347      opcode.  For example, an opcode that fits lots of different
 348      formats has a high freedom, as does an opcode that fits
 349      only one format but many slots in that format.  The most
 350      restrictive is the opcode that fits only one slot in one
 351      format.  */
 352   int issuef;
 353   /* The single format (i.e., if the op can live in a bundle by itself),
 354      narrowest format, and widest format the op can be bundled in
 355      and their sizes:  */
 356   xtensa_format single;
 357   xtensa_format narrowest;
 358   xtensa_format widest;
 359   char narrowest_size;
 360   char widest_size;
 361   char single_size;
 362
 363   /* formats is a bitfield with the Nth bit set
 364      if the opcode fits in the Nth xtensa_format.  */
 365   bitfield formats;
 366
 367   /* slots[N]'s Mth bit is set if the op fits in the
 368      Mth slot of the Nth xtensa_format.  */
 369   bitfield slots[MAX_FORMATS];
 370
 371   /* A count of the number of slots in a given format
 372      an op can fit (i.e., the bitcount of the slot field above).  */
 373   char slots_in_format[MAX_FORMATS];
 374
 375 } op_placement_info, *op_placement_info_table;
 376
 377 op_placement_info_table op_placement_table;
 378
 379
 380 /* Extra expression types.  */
 381
 382 #define O_pltrel        O_md1   /* like O_symbol but use a PLT reloc */
 383 #define O_hi16          O_md2   /* use high 16 bits of symbolic value */
 384 #define O_lo16          O_md3   /* use low 16 bits of symbolic value */
 385
 386
 387 /* Directives.  */
 388
 389 typedef enum
 390 {
 391   directive_none = 0,
 392   directive_literal,
 393   directive_density,
 394   directive_transform,
 395   directive_freeregs,
 396   directive_longcalls,
 397   directive_literal_prefix,
 398   directive_schedule,
 399   directive_absolute_literals,
 400   directive_last_directive
 401 } directiveE;
 402
 403 typedef struct
 404 {
 405   const char *name;
 406   bfd_boolean can_be_negated;
 407 } directive_infoS;
 408
 409 const directive_infoS directive_info[] =
 410 {
 411   { "none",             FALSE },
 412   { "literal",          FALSE },
 413   { "density",          TRUE },
 414   { "transform",        TRUE },
 415   { "freeregs",         FALSE },
 416   { "longcalls",        TRUE },
 417   { "literal_prefix",   FALSE },
 418   { "schedule",         TRUE },
 419   { "absolute-literals", TRUE }
 420 };
 421
 422 bfd_boolean directive_state[] =
 423 {
 424   FALSE,                        /* none */
 425   FALSE,                        /* literal */
 426 #if !XCHAL_HAVE_DENSITY
 427   FALSE,                        /* density */
 428 #else
 429   TRUE,                         /* density */
 430 #endif
 431   TRUE,                         /* transform */
 432   FALSE,                        /* freeregs */
 433   FALSE,                        /* longcalls */
 434   FALSE,                        /* literal_prefix */
 435   TRUE,                         /* schedule */
 436 #if XSHAL_USE_ABSOLUTE_LITERALS
 437   TRUE                          /* absolute_literals */
 438 #else
 439   FALSE                         /* absolute_literals */
 440 #endif
 441 };
 442
 443
 444 /* Directive functions.  */
 445
 446 static void xtensa_begin_directive (int);
 447 static void xtensa_end_directive (int);
 448 static void xtensa_dwarf2_directive_loc (int);
 449 static void xtensa_literal_prefix (char const *, int);
 450 static void xtensa_literal_position (int);
 451 static void xtensa_literal_pseudo (int);
 452 static void xtensa_frequency_pseudo (int);
 453 static void xtensa_elf_cons (int);
 454
 455 /* Parsing and Idiom Translation.  */
 456
 457 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
 458
 459 /* Various Other Internal Functions.  */
 460
 461 static void xtensa_mark_literal_pool_location (void);
 462 static addressT get_expanded_loop_offset (xtensa_opcode);
 463 static fragS *get_literal_pool_location (segT);
 464 static void set_literal_pool_location (segT, fragS *);
 465 static void xtensa_set_frag_assembly_state (fragS *);
 466 static void finish_vinsn (vliw_insn *);
 467 static bfd_boolean emit_single_op (TInsn *);
 468
 469 /* Alignment Functions.  */
 470
 471 static size_t get_text_align_power (int);
 472 static addressT get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
 473
 474 /* Helpers for xtensa_relax_frag().  */
 475
 476 static long relax_frag_add_nop (fragS *);
 477
 478 /* Flags for the Last Instruction in Each Subsegment.  */
 479
 480 static subseg_map *get_subseg_info (segT, subsegT);
 481 static unsigned get_last_insn_flags (segT, subsegT);
 482 static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
 483
 484 /* Segment list functions.  */
 485
 486 static void xtensa_move_literals (void);
 487 static void xtensa_reorder_segments (void);
 488 static void xtensa_switch_to_literal_fragment (emit_state *);
 489 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
 490 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
 491 static void xtensa_restore_emit_state (emit_state *);
 492 static void cache_literal_section
 493   (seg_list *, const char *, segT *, bfd_boolean);
 494
 495 /* Property flags on fragments and conversion to object file flags.  */
 496
 497 static bfd_boolean get_frag_is_literal (const fragS *);
 498 static bfd_boolean get_frag_is_insn (const fragS *);
 499 static bfd_boolean get_frag_is_no_transform (fragS *);
 500 static void set_frag_is_specific_opcode (fragS *, bfd_boolean);
 501 static void set_frag_is_no_transform (fragS *, bfd_boolean);
 502
 503 /* Import from elf32-xtensa.c in BFD library.  */
 504
 505 extern char *xtensa_get_property_section_name (asection *, const char *);
 506
 507 /* op_placement_info functions.  */
 508
 509 static void init_op_placement_info_table (void);
 510 extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
 511 static int xg_get_single_size (xtensa_opcode);
 512 static xtensa_format xg_get_single_format (xtensa_opcode);
 513
 514 /* TInsn and IStack functions.  */
 515
 516 static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
 517 static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
 518 static bfd_boolean tinsn_has_complex_operands (const TInsn *);
 519 static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
 520 static bfd_boolean tinsn_check_arguments (const TInsn *);
 521 static void tinsn_from_chars (TInsn *, char *, int);
 522 static void tinsn_immed_from_frag (TInsn *, fragS *, int);
 523 static int get_num_stack_text_bytes (IStack *);
 524 static int get_num_stack_literal_bytes (IStack *);
 525
 526 /* vliw_insn functions.  */
 527
 528 static void xg_init_vinsn (vliw_insn *);
 529 static void xg_clear_vinsn (vliw_insn *);
 530 static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
 531 static void xg_free_vinsn (vliw_insn *);
 532 static bfd_boolean vinsn_to_insnbuf
 533   (vliw_insn *, char *, fragS *, bfd_boolean);
 534 static void vinsn_from_chars (vliw_insn *, char *);
 535
 536 /* Expression Utilities.  */
 537
 538 bfd_boolean expr_is_const (const expressionS *);
 539 offsetT get_expr_const (const expressionS *);
 540 void set_expr_const (expressionS *, offsetT);
 541 bfd_boolean expr_is_register (const expressionS *);
 542 offsetT get_expr_register (const expressionS *);
 543 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
 544 static void set_expr_symbol_offset_diff
 545   (expressionS *, symbolS *, symbolS *, offsetT);
 546 bfd_boolean expr_is_equal (expressionS *, expressionS *);
 547 static void copy_expr (expressionS *, const expressionS *);
 548
 549 #ifdef XTENSA_SECTION_RENAME
 550 static void build_section_rename (const char *);
 551 static void add_section_rename (char *, char *);
 552 #endif
 553
 554
 555 /* ISA imported from bfd.  */
 556 extern xtensa_isa xtensa_default_isa;
 557
 558 extern int target_big_endian;
 559
 560 static xtensa_opcode xtensa_addi_opcode;
 561 static xtensa_opcode xtensa_addmi_opcode;
 562 static xtensa_opcode xtensa_call0_opcode;
 563 static xtensa_opcode xtensa_call4_opcode;
 564 static xtensa_opcode xtensa_call8_opcode;
 565 static xtensa_opcode xtensa_call12_opcode;
 566 static xtensa_opcode xtensa_callx0_opcode;
 567 static xtensa_opcode xtensa_callx4_opcode;
 568 static xtensa_opcode xtensa_callx8_opcode;
 569 static xtensa_opcode xtensa_callx12_opcode;
 570 static xtensa_opcode xtensa_const16_opcode;
 571 static xtensa_opcode xtensa_entry_opcode;
 572 static xtensa_opcode xtensa_movi_opcode;
 573 static xtensa_opcode xtensa_movi_n_opcode;
 574 static xtensa_opcode xtensa_isync_opcode;
 575 static xtensa_opcode xtensa_jx_opcode;
 576 static xtensa_opcode xtensa_l32r_opcode;
 577 static xtensa_opcode xtensa_loop_opcode;
 578 static xtensa_opcode xtensa_loopnez_opcode;
 579 static xtensa_opcode xtensa_loopgtz_opcode;
 580 static xtensa_opcode xtensa_nop_opcode;
 581 static xtensa_opcode xtensa_nop_n_opcode;
 582 static xtensa_opcode xtensa_or_opcode;
 583 static xtensa_opcode xtensa_ret_opcode;
 584 static xtensa_opcode xtensa_ret_n_opcode;
 585 static xtensa_opcode xtensa_retw_opcode;
 586 static xtensa_opcode xtensa_retw_n_opcode;
 587 static xtensa_opcode xtensa_rsr_lcount_opcode;
 588 static xtensa_opcode xtensa_waiti_opcode;
 589
 590 \f
 591 /* Command-line Options.  */
 592
 593 bfd_boolean use_literal_section = TRUE;
 594 static bfd_boolean align_targets = TRUE;
 595 static bfd_boolean warn_unaligned_branch_targets = FALSE;
 596 static bfd_boolean has_a0_b_retw = FALSE;
 597 static bfd_boolean workaround_a0_b_retw = FALSE;
 598 static bfd_boolean workaround_b_j_loop_end = FALSE;
 599 static bfd_boolean workaround_short_loop = FALSE;
 600 static bfd_boolean maybe_has_short_loop = FALSE;
 601 static bfd_boolean workaround_close_loop_end = FALSE;
 602 static bfd_boolean maybe_has_close_loop_end = FALSE;
 603
 604 /* When workaround_short_loops is TRUE, all loops with early exits must
 605    have at least 3 instructions.  workaround_all_short_loops is a modifier
 606    to the workaround_short_loop flag.  In addition to the
 607    workaround_short_loop actions, all straightline loopgtz and loopnez
 608    must have at least 3 instructions.  */
 609
 610 static bfd_boolean workaround_all_short_loops = FALSE;
 611
 612
 613 static void
 614 xtensa_setup_hw_workarounds (int earliest, int latest)
 615 {
 616   if (earliest > latest)
 617     as_fatal (_("illegal range of target hardware versions"));
 618
 619   /* Enable all workarounds for pre-T1050.0 hardware.  */
 620   if (earliest < 105000 || latest < 105000)
 621     {
 622       workaround_a0_b_retw |= TRUE;
 623       workaround_b_j_loop_end |= TRUE;
 624       workaround_short_loop |= TRUE;
 625       workaround_close_loop_end |= TRUE;
 626       workaround_all_short_loops |= TRUE;
 627     }
 628 }
 629
 630
 631 enum
 632 {
 633   option_density = OPTION_MD_BASE,
 634   option_no_density,
 635
 636   option_relax,
 637   option_no_relax,
 638
 639   option_link_relax,
 640   option_no_link_relax,
 641
 642   option_generics,
 643   option_no_generics,
 644
 645   option_transform,
 646   option_no_transform,
 647
 648   option_text_section_literals,
 649   option_no_text_section_literals,
 650
 651   option_absolute_literals,
 652   option_no_absolute_literals,
 653
 654   option_align_targets,
 655   option_no_align_targets,
 656
 657   option_warn_unaligned_targets,
 658
 659   option_longcalls,
 660   option_no_longcalls,
 661
 662   option_workaround_a0_b_retw,
 663   option_no_workaround_a0_b_retw,
 664
 665   option_workaround_b_j_loop_end,
 666   option_no_workaround_b_j_loop_end,
 667
 668   option_workaround_short_loop,
 669   option_no_workaround_short_loop,
 670
 671   option_workaround_all_short_loops,
 672   option_no_workaround_all_short_loops,
 673
 674   option_workaround_close_loop_end,
 675   option_no_workaround_close_loop_end,
 676
 677   option_no_workarounds,
 678
 679 #ifdef XTENSA_SECTION_RENAME
 680   option_rename_section_name,
 681 #endif
 682
 683   option_prefer_l32r,
 684   option_prefer_const16,
 685
 686   option_target_hardware
 687 };
 688
 689 const char *md_shortopts = "";
 690
 691 struct option md_longopts[] =
 692 {
 693   { "density", no_argument, NULL, option_density },
 694   { "no-density", no_argument, NULL, option_no_density },
 695
 696   /* Both "relax" and "generics" are deprecated and treated as equivalent
 697      to the "transform" option.  */
 698   { "relax", no_argument, NULL, option_relax },
 699   { "no-relax", no_argument, NULL, option_no_relax },
 700   { "generics", no_argument, NULL, option_generics },
 701   { "no-generics", no_argument, NULL, option_no_generics },
 702
 703   { "transform", no_argument, NULL, option_transform },
 704   { "no-transform", no_argument, NULL, option_no_transform },
 705   { "text-section-literals", no_argument, NULL, option_text_section_literals },
 706   { "no-text-section-literals", no_argument, NULL,
 707     option_no_text_section_literals },
 708   { "absolute-literals", no_argument, NULL, option_absolute_literals },
 709   { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
 710   /* This option was changed from -align-target to -target-align
 711      because it conflicted with the "-al" option.  */
 712   { "target-align", no_argument, NULL, option_align_targets },
 713   { "no-target-align", no_argument, NULL, option_no_align_targets },
 714   { "warn-unaligned-targets", no_argument, NULL,
 715     option_warn_unaligned_targets },
 716   { "longcalls", no_argument, NULL, option_longcalls },
 717   { "no-longcalls", no_argument, NULL, option_no_longcalls },
 718
 719   { "no-workaround-a0-b-retw", no_argument, NULL,
 720     option_no_workaround_a0_b_retw },
 721   { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
 722
 723   { "no-workaround-b-j-loop-end", no_argument, NULL,
 724     option_no_workaround_b_j_loop_end },
 725   { "workaround-b-j-loop-end", no_argument, NULL,
 726     option_workaround_b_j_loop_end },
 727
 728   { "no-workaround-short-loops", no_argument, NULL,
 729     option_no_workaround_short_loop },
 730   { "workaround-short-loops", no_argument, NULL,
 731     option_workaround_short_loop },
 732
 733   { "no-workaround-all-short-loops", no_argument, NULL,
 734     option_no_workaround_all_short_loops },
 735   { "workaround-all-short-loop", no_argument, NULL,
 736     option_workaround_all_short_loops },
 737
 738   { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
 739   { "prefer-const16", no_argument, NULL, option_prefer_const16 },
 740
 741   { "no-workarounds", no_argument, NULL, option_no_workarounds },
 742
 743   { "no-workaround-close-loop-end", no_argument, NULL,
 744     option_no_workaround_close_loop_end },
 745   { "workaround-close-loop-end", no_argument, NULL,
 746     option_workaround_close_loop_end },
 747
 748 #ifdef XTENSA_SECTION_RENAME
 749   { "rename-section", required_argument, NULL, option_rename_section_name },
 750 #endif /* XTENSA_SECTION_RENAME */
 751
 752   { "link-relax", no_argument, NULL, option_link_relax },
 753   { "no-link-relax", no_argument, NULL, option_no_link_relax },
 754
 755   { "target-hardware", required_argument, NULL, option_target_hardware },
 756
 757   { NULL, no_argument, NULL, 0 }
 758 };
 759
 760 size_t md_longopts_size = sizeof md_longopts;
 761
 762
 763 int
 764 md_parse_option (int c, char *arg)
 765 {
 766   switch (c)
 767     {
 768     case option_density:
 769       as_warn (_("--density option is ignored"));
 770       return 1;
 771     case option_no_density:
 772       as_warn (_("--no-density option is ignored"));
 773       return 1;
 774     case option_link_relax:
 775       linkrelax = 1;
 776       return 1;
 777     case option_no_link_relax:
 778       linkrelax = 0;
 779       return 1;
 780     case option_generics:
 781       as_warn (_("--generics is deprecated; use --transform instead"));
 782       return md_parse_option (option_transform, arg);
 783     case option_no_generics:
 784       as_warn (_("--no-generics is deprecated; use --no-transform instead"));
 785       return md_parse_option (option_no_transform, arg);
 786     case option_relax:
 787       as_warn (_("--relax is deprecated; use --transform instead"));
 788       return md_parse_option (option_transform, arg);
 789     case option_no_relax:
 790       as_warn (_("--no-relax is deprecated; use --no-transform instead"));
 791       return md_parse_option (option_no_transform, arg);
 792     case option_longcalls:
 793       directive_state[directive_longcalls] = TRUE;
 794       return 1;
 795     case option_no_longcalls:
 796       directive_state[directive_longcalls] = FALSE;
 797       return 1;
 798     case option_text_section_literals:
 799       use_literal_section = FALSE;
 800       return 1;
 801     case option_no_text_section_literals:
 802       use_literal_section = TRUE;
 803       return 1;
 804     case option_absolute_literals:
 805       if (!absolute_literals_supported)
 806         {
 807           as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
 808           return 0;
 809         }
 810       directive_state[directive_absolute_literals] = TRUE;
 811       return 1;
 812     case option_no_absolute_literals:
 813       directive_state[directive_absolute_literals] = FALSE;
 814       return 1;
 815
 816     case option_workaround_a0_b_retw:
 817       workaround_a0_b_retw = TRUE;
 818       return 1;
 819     case option_no_workaround_a0_b_retw:
 820       workaround_a0_b_retw = FALSE;
 821       return 1;
 822     case option_workaround_b_j_loop_end:
 823       workaround_b_j_loop_end = TRUE;
 824       return 1;
 825     case option_no_workaround_b_j_loop_end:
 826       workaround_b_j_loop_end = FALSE;
 827       return 1;
 828
 829     case option_workaround_short_loop:
 830       workaround_short_loop = TRUE;
 831       return 1;
 832     case option_no_workaround_short_loop:
 833       workaround_short_loop = FALSE;
 834       return 1;
 835
 836     case option_workaround_all_short_loops:
 837       workaround_all_short_loops = TRUE;
 838       return 1;
 839     case option_no_workaround_all_short_loops:
 840       workaround_all_short_loops = FALSE;
 841       return 1;
 842
 843     case option_workaround_close_loop_end:
 844       workaround_close_loop_end = TRUE;
 845       return 1;
 846     case option_no_workaround_close_loop_end:
 847       workaround_close_loop_end = FALSE;
 848       return 1;
 849
 850     case option_no_workarounds:
 851       workaround_a0_b_retw = FALSE;
 852       workaround_b_j_loop_end = FALSE;
 853       workaround_short_loop = FALSE;
 854       workaround_all_short_loops = FALSE;
 855       workaround_close_loop_end = FALSE;
 856       return 1;
 857
 858     case option_align_targets:
 859       align_targets = TRUE;
 860       return 1;
 861     case option_no_align_targets:
 862       align_targets = FALSE;
 863       return 1;
 864
 865     case option_warn_unaligned_targets:
 866       warn_unaligned_branch_targets = TRUE;
 867       return 1;
 868
 869 #ifdef XTENSA_SECTION_RENAME
 870     case option_rename_section_name:
 871       build_section_rename (arg);
 872       return 1;
 873 #endif /* XTENSA_SECTION_RENAME */
 874
 875     case 'Q':
 876       /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
 877          should be emitted or not.  FIXME: Not implemented.  */
 878       return 1;
 879
 880     case option_prefer_l32r:
 881       if (prefer_const16)
 882         as_fatal (_("prefer-l32r conflicts with prefer-const16"));
 883       prefer_l32r = 1;
 884       return 1;
 885
 886     case option_prefer_const16:
 887       if (prefer_l32r)
 888         as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
 889       prefer_const16 = 1;
 890       return 1;
 891
 892     case option_target_hardware:
 893       {
 894         int earliest, latest = 0;
 895         if (*arg == 0 || *arg == '-')
 896           as_fatal (_("invalid target hardware version"));
 897
 898         earliest = strtol (arg, &arg, 0);
 899
 900         if (*arg == 0)
 901           latest = earliest;
 902         else if (*arg == '-')
 903           {
 904             if (*++arg == 0)
 905               as_fatal (_("invalid target hardware version"));
 906             latest = strtol (arg, &arg, 0);
 907           }
 908         if (*arg != 0)
 909           as_fatal (_("invalid target hardware version"));
 910
 911         xtensa_setup_hw_workarounds (earliest, latest);
 912         return 1;
 913       }
 914
 915     case option_transform:
 916       /* This option has no affect other than to use the defaults,
 917          which are already set.  */
 918       return 1;
 919
 920     case option_no_transform:
 921       /* This option turns off all transformations of any kind.
 922          However, because we want to preserve the state of other
 923          directives, we only change its own field.  Thus, before
 924          you perform any transformation, always check if transform
 925          is available.  If you use the functions we provide for this
 926          purpose, you will be ok.  */
 927       directive_state[directive_transform] = FALSE;
 928       return 1;
 929
 930     default:
 931       return 0;
 932     }
 933 }
 934
 935
 936 void
 937 md_show_usage (FILE *stream)
 938 {
 939   fputs ("\n\
 940 Xtensa options:\n\
 941 --[no-]text-section-literals\n\
 942                         [Do not] put literals in the text section\n\
 943 --[no-]absolute-literals\n\
 944                         [Do not] default to use non-PC-relative literals\n\
 945 --[no-]target-align     [Do not] try to align branch targets\n\
 946 --[no-]longcalls        [Do not] emit 32-bit call sequences\n\
 947 --[no-]transform        [Do not] transform instructions\n"
 948 #ifdef XTENSA_SECTION_RENAME
 949 "--rename-section old=new(:old1=new1)*\n\
 950                         Rename section 'old' to 'new'\n"
 951 #endif /* XTENSA_SECTION_RENAME */
 952          , stream);
 953 }
 954
 955 \f
 956 /* Functions related to the list of current label symbols.  */
 957
 958 static void
 959 xtensa_add_insn_label (symbolS *sym)
 960 {
 961   sym_list *l;
 962
 963   if (!free_insn_labels)
 964     l = (sym_list *) xmalloc (sizeof (sym_list));
 965   else
 966     {
 967       l = free_insn_labels;
 968       free_insn_labels = l->next;
 969     }
 970
 971   l->sym = sym;
 972   l->next = insn_labels;
 973   insn_labels = l;
 974 }
 975
 976
 977 static void
 978 xtensa_clear_insn_labels (void)
 979 {
 980   sym_list **pl;
 981
 982   for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
 983     ;
 984   *pl = insn_labels;
 985   insn_labels = NULL;
 986 }
 987
 988
 989 /* The "loops_ok" argument is provided to allow ignoring labels that
 990    define loop ends.  This fixes a bug where the NOPs to align a
 991    loop opcode were included in a previous zero-cost loop:
 992
 993    loop a0, loopend
 994      <loop1 body>
 995    loopend:
 996
 997    loop a2, loopend2
 998      <loop2 body>
 999
1000    would become:
1001
1002    loop a0, loopend
1003      <loop1 body>
1004      nop.n <===== bad!
1005    loopend:
1006
1007    loop a2, loopend2
1008      <loop2 body>
1009
1010    This argument is used to prevent moving the NOP to before the
1011    loop-end label, which is what you want in this special case.  */
1012
1013 static void
1014 xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok)
1015 {
1016   sym_list *lit;
1017
1018   for (lit = insn_labels; lit; lit = lit->next)
1019     {
1020       symbolS *lit_sym = lit->sym;
1021       if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target)
1022         {
1023           S_SET_VALUE (lit_sym, new_offset);
1024           symbol_set_frag (lit_sym, new_frag);
1025         }
1026     }
1027 }
1028
1029 \f
1030 /* Directive data and functions.  */
1031
1032 typedef struct state_stackS_struct
1033 {
1034   directiveE directive;
1035   bfd_boolean negated;
1036   bfd_boolean old_state;
1037   const char *file;
1038   unsigned int line;
1039   const void *datum;
1040   struct state_stackS_struct *prev;
1041 } state_stackS;
1042
1043 state_stackS *directive_state_stack;
1044
1045 const pseudo_typeS md_pseudo_table[] =
1046 {
1047   { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
1048   { "literal_position", xtensa_literal_position, 0 },
1049   { "frame", s_ignore, 0 },     /* Formerly used for STABS debugging.  */
1050   { "long", xtensa_elf_cons, 4 },
1051   { "word", xtensa_elf_cons, 4 },
1052   { "short", xtensa_elf_cons, 2 },
1053   { "begin", xtensa_begin_directive, 0 },
1054   { "end", xtensa_end_directive, 0 },
1055   { "loc", xtensa_dwarf2_directive_loc, 0 },
1056   { "literal", xtensa_literal_pseudo, 0 },
1057   { "frequency", xtensa_frequency_pseudo, 0 },
1058   { NULL, 0, 0 },
1059 };
1060
1061
1062 static bfd_boolean
1063 use_transform (void)
1064 {
1065   /* After md_end, you should be checking frag by frag, rather
1066      than state directives.  */
1067   assert (!past_xtensa_end);
1068   return directive_state[directive_transform];
1069 }
1070
1071
1072 static bfd_boolean
1073 use_longcalls (void)
1074 {
1075   /* After md_end, you should be checking frag by frag, rather
1076      than state directives.  */
1077   assert (!past_xtensa_end);
1078   return directive_state[directive_longcalls] && use_transform ();
1079 }
1080
1081
1082 static bfd_boolean
1083 do_align_targets (void)
1084 {
1085   /* After md_end, you should be checking frag by frag, rather
1086      than state directives.  */
1087   assert (!past_xtensa_end);
1088   return align_targets && use_transform ();
1089 }
1090
1091
1092 static void
1093 directive_push (directiveE directive, bfd_boolean negated, const void *datum)
1094 {
1095   char *file;
1096   unsigned int line;
1097   state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS));
1098
1099   as_where (&file, &line);
1100
1101   stack->directive = directive;
1102   stack->negated = negated;
1103   stack->old_state = directive_state[directive];
1104   stack->file = file;
1105   stack->line = line;
1106   stack->datum = datum;
1107   stack->prev = directive_state_stack;
1108   directive_state_stack = stack;
1109
1110   directive_state[directive] = !negated;
1111 }
1112
1113
1114 static void
1115 directive_pop (directiveE *directive,
1116                bfd_boolean *negated,
1117                const char **file,
1118                unsigned int *line,
1119                const void **datum)
1120 {
1121   state_stackS *top = directive_state_stack;
1122
1123   if (!directive_state_stack)
1124     {
1125       as_bad (_("unmatched end directive"));
1126       *directive = directive_none;
1127       return;
1128     }
1129
1130   directive_state[directive_state_stack->directive] = top->old_state;
1131   *directive = top->directive;
1132   *negated = top->negated;
1133   *file = top->file;
1134   *line = top->line;
1135   *datum = top->datum;
1136   directive_state_stack = top->prev;
1137   free (top);
1138 }
1139
1140
1141 static void
1142 directive_balance (void)
1143 {
1144   while (directive_state_stack)
1145     {
1146       directiveE directive;
1147       bfd_boolean negated;
1148       const char *file;
1149       unsigned int line;
1150       const void *datum;
1151
1152       directive_pop (&directive, &negated, &file, &line, &datum);
1153       as_warn_where ((char *) file, line,
1154                      _(".begin directive with no matching .end directive"));
1155     }
1156 }
1157
1158
1159 static bfd_boolean
1160 inside_directive (directiveE dir)
1161 {
1162   state_stackS *top = directive_state_stack;
1163
1164   while (top && top->directive != dir)
1165     top = top->prev;
1166
1167   return (top != NULL);
1168 }
1169
1170
1171 static void
1172 get_directive (directiveE *directive, bfd_boolean *negated)
1173 {
1174   int len;
1175   unsigned i;
1176   char *directive_string;
1177
1178   if (strncmp (input_line_pointer, "no-", 3) != 0)
1179     *negated = FALSE;
1180   else
1181     {
1182       *negated = TRUE;
1183       input_line_pointer += 3;
1184     }
1185
1186   len = strspn (input_line_pointer,
1187                 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1188
1189   /* This code is a hack to make .begin [no-][generics|relax] exactly
1190      equivalent to .begin [no-]transform.  We should remove it when
1191      we stop accepting those options.  */
1192
1193   if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1194     {
1195       as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1196       directive_string = "transform";
1197     }
1198   else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1199     {
1200       as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1201       directive_string = "transform";
1202     }
1203   else
1204     directive_string = input_line_pointer;
1205
1206   for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1207     {
1208       if (strncmp (directive_string, directive_info[i].name, len) == 0)
1209         {
1210           input_line_pointer += len;
1211           *directive = (directiveE) i;
1212           if (*negated && !directive_info[i].can_be_negated)
1213             as_bad (_("directive %s cannot be negated"),
1214                     directive_info[i].name);
1215           return;
1216         }
1217     }
1218
1219   as_bad (_("unknown directive"));
1220   *directive = (directiveE) XTENSA_UNDEFINED;
1221 }
1222
1223
1224 static void
1225 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
1226 {
1227   directiveE directive;
1228   bfd_boolean negated;
1229   emit_state *state;
1230   int len;
1231   lit_state *ls;
1232
1233   get_directive (&directive, &negated);
1234   if (directive == (directiveE) XTENSA_UNDEFINED)
1235     {
1236       discard_rest_of_line ();
1237       return;
1238     }
1239
1240   if (cur_vinsn.inside_bundle)
1241     as_bad (_("directives are not valid inside bundles"));
1242
1243   switch (directive)
1244     {
1245     case directive_literal:
1246       if (!inside_directive (directive_literal))
1247         {
1248           /* Previous labels go with whatever follows this directive, not with
1249              the literal, so save them now.  */
1250           saved_insn_labels = insn_labels;
1251           insn_labels = NULL;
1252         }
1253       as_warn (_(".begin literal is deprecated; use .literal instead"));
1254       state = (emit_state *) xmalloc (sizeof (emit_state));
1255       xtensa_switch_to_literal_fragment (state);
1256       directive_push (directive_literal, negated, state);
1257       break;
1258
1259     case directive_literal_prefix:
1260       /* Have to flush pending output because a movi relaxed to an l32r
1261          might produce a literal.  */
1262       md_flush_pending_output ();
1263       /* Check to see if the current fragment is a literal
1264          fragment.  If it is, then this operation is not allowed.  */
1265       if (generating_literals)
1266         {
1267           as_bad (_("cannot set literal_prefix inside literal fragment"));
1268           return;
1269         }
1270
1271       /* Allocate the literal state for this section and push
1272          onto the directive stack.  */
1273       ls = xmalloc (sizeof (lit_state));
1274       assert (ls);
1275
1276       *ls = default_lit_sections;
1277
1278       directive_push (directive_literal_prefix, negated, ls);
1279
1280       /* Parse the new prefix from the input_line_pointer.  */
1281       SKIP_WHITESPACE ();
1282       len = strspn (input_line_pointer,
1283                     "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1284                     "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1285
1286       /* Process the new prefix.  */
1287       xtensa_literal_prefix (input_line_pointer, len);
1288
1289       /* Skip the name in the input line.  */
1290       input_line_pointer += len;
1291       break;
1292
1293     case directive_freeregs:
1294       /* This information is currently unused, but we'll accept the statement
1295          and just discard the rest of the line.  This won't check the syntax,
1296          but it will accept every correct freeregs directive.  */
1297       input_line_pointer += strcspn (input_line_pointer, "\n");
1298       directive_push (directive_freeregs, negated, 0);
1299       break;
1300
1301     case directive_schedule:
1302       md_flush_pending_output ();
1303       frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1304                 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1305       directive_push (directive_schedule, negated, 0);
1306       xtensa_set_frag_assembly_state (frag_now);
1307       break;
1308
1309     case directive_density:
1310       as_warn (_(".begin [no-]density is ignored"));
1311       break;
1312
1313     case directive_absolute_literals:
1314       md_flush_pending_output ();
1315       if (!absolute_literals_supported && !negated)
1316         {
1317           as_warn (_("Xtensa absolute literals option not supported; ignored"));
1318           break;
1319         }
1320       xtensa_set_frag_assembly_state (frag_now);
1321       directive_push (directive, negated, 0);
1322       break;
1323
1324     default:
1325       md_flush_pending_output ();
1326       xtensa_set_frag_assembly_state (frag_now);
1327       directive_push (directive, negated, 0);
1328       break;
1329     }
1330
1331   demand_empty_rest_of_line ();
1332 }
1333
1334
1335 static void
1336 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
1337 {
1338   directiveE begin_directive, end_directive;
1339   bfd_boolean begin_negated, end_negated;
1340   const char *file;
1341   unsigned int line;
1342   emit_state *state;
1343   emit_state **state_ptr;
1344   lit_state *s;
1345
1346   if (cur_vinsn.inside_bundle)
1347     as_bad (_("directives are not valid inside bundles"));
1348
1349   get_directive (&end_directive, &end_negated);
1350
1351   md_flush_pending_output ();
1352
1353   switch (end_directive)
1354     {
1355     case (directiveE) XTENSA_UNDEFINED:
1356       discard_rest_of_line ();
1357       return;
1358
1359     case directive_density:
1360       as_warn (_(".end [no-]density is ignored"));
1361       demand_empty_rest_of_line ();
1362       break;
1363
1364     case directive_absolute_literals:
1365       if (!absolute_literals_supported && !end_negated)
1366         {
1367           as_warn (_("Xtensa absolute literals option not supported; ignored"));
1368           demand_empty_rest_of_line ();
1369           return;
1370         }
1371       break;
1372
1373     default:
1374       break;
1375     }
1376
1377   state_ptr = &state; /* use state_ptr to avoid type-punning warning */
1378   directive_pop (&begin_directive, &begin_negated, &file, &line,
1379                  (const void **) state_ptr);
1380
1381   if (begin_directive != directive_none)
1382     {
1383       if (begin_directive != end_directive || begin_negated != end_negated)
1384         {
1385           as_bad (_("does not match begin %s%s at %s:%d"),
1386                   begin_negated ? "no-" : "",
1387                   directive_info[begin_directive].name, file, line);
1388         }
1389       else
1390         {
1391           switch (end_directive)
1392             {
1393             case directive_literal:
1394               frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1395               xtensa_restore_emit_state (state);
1396               xtensa_set_frag_assembly_state (frag_now);
1397               free (state);
1398               if (!inside_directive (directive_literal))
1399                 {
1400                   /* Restore the list of current labels.  */
1401                   xtensa_clear_insn_labels ();
1402                   insn_labels = saved_insn_labels;
1403                 }
1404               break;
1405
1406             case directive_literal_prefix:
1407               /* Restore the default collection sections from saved state.  */
1408               s = (lit_state *) state;
1409               assert (s);
1410
1411               if (use_literal_section)
1412                 default_lit_sections = *s;
1413
1414               /* free the state storage */
1415               free (s);
1416               break;
1417
1418             case directive_schedule:
1419             case directive_freeregs:
1420               break;
1421
1422             default:
1423               xtensa_set_frag_assembly_state (frag_now);
1424               break;
1425             }
1426         }
1427     }
1428
1429   demand_empty_rest_of_line ();
1430 }
1431
1432
1433 /* Wrap dwarf2 functions so that we correctly support the .loc directive.  */
1434
1435 static bfd_boolean xtensa_loc_directive_seen = FALSE;
1436
1437 static void
1438 xtensa_dwarf2_directive_loc (int x)
1439 {
1440   xtensa_loc_directive_seen = TRUE;
1441   dwarf2_directive_loc (x);
1442 }
1443
1444
1445 static void
1446 xtensa_dwarf2_emit_insn (int size, struct dwarf2_line_info *loc)
1447 {
1448   if (debug_type != DEBUG_DWARF2 && ! xtensa_loc_directive_seen)
1449     return;
1450   xtensa_loc_directive_seen = FALSE;
1451   dwarf2_gen_line_info (frag_now_fix () - size, loc);
1452 }
1453
1454
1455 /* Place an aligned literal fragment at the current location.  */
1456
1457 static void
1458 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
1459 {
1460   md_flush_pending_output ();
1461
1462   if (inside_directive (directive_literal))
1463     as_warn (_(".literal_position inside literal directive; ignoring"));
1464   xtensa_mark_literal_pool_location ();
1465
1466   demand_empty_rest_of_line ();
1467   xtensa_clear_insn_labels ();
1468 }
1469
1470
1471 /* Support .literal label, expr, ...  */
1472
1473 static void
1474 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
1475 {
1476   emit_state state;
1477   char *p, *base_name;
1478   char c;
1479   segT dest_seg;
1480
1481   if (inside_directive (directive_literal))
1482     {
1483       as_bad (_(".literal not allowed inside .begin literal region"));
1484       ignore_rest_of_line ();
1485       return;
1486     }
1487
1488   md_flush_pending_output ();
1489
1490   /* Previous labels go with whatever follows this directive, not with
1491      the literal, so save them now.  */
1492   saved_insn_labels = insn_labels;
1493   insn_labels = NULL;
1494
1495   /* If we are using text-section literals, then this is the right value... */
1496   dest_seg = now_seg;
1497
1498   base_name = input_line_pointer;
1499
1500   xtensa_switch_to_literal_fragment (&state);
1501
1502   /* ...but if we aren't using text-section-literals, then we
1503      need to put them in the section we just switched to.  */
1504   if (use_literal_section || directive_state[directive_absolute_literals])
1505     dest_seg = now_seg;
1506
1507   /* All literals are aligned to four-byte boundaries.  */
1508   frag_align (2, 0, 0);
1509   record_alignment (now_seg, 2);
1510
1511   c = get_symbol_end ();
1512   /* Just after name is now '\0'.  */
1513   p = input_line_pointer;
1514   *p = c;
1515   SKIP_WHITESPACE ();
1516
1517   if (*input_line_pointer != ',' && *input_line_pointer != ':')
1518     {
1519       as_bad (_("expected comma or colon after symbol name; "
1520                 "rest of line ignored"));
1521       ignore_rest_of_line ();
1522       xtensa_restore_emit_state (&state);
1523       return;
1524     }
1525   *p = 0;
1526
1527   colon (base_name);
1528
1529   *p = c;
1530   input_line_pointer++;         /* skip ',' or ':' */
1531
1532   xtensa_elf_cons (4);
1533
1534   xtensa_restore_emit_state (&state);
1535
1536   /* Restore the list of current labels.  */
1537   xtensa_clear_insn_labels ();
1538   insn_labels = saved_insn_labels;
1539 }
1540
1541
1542 static void
1543 xtensa_literal_prefix (char const *start, int len)
1544 {
1545   char *name, *linkonce_suffix;
1546   char *newname, *newname4;
1547   size_t linkonce_len;
1548
1549   /* Get a null-terminated copy of the name.  */
1550   name = xmalloc (len + 1);
1551   assert (name);
1552
1553   strncpy (name, start, len);
1554   name[len] = 0;
1555
1556   /* Allocate the sections (interesting note: the memory pointing to
1557      the name is actually used for the name by the new section). */
1558
1559   newname = xmalloc (len + strlen (".literal") + 1);
1560   newname4 = xmalloc (len + strlen (".lit4") + 1);
1561
1562   linkonce_len = sizeof (".gnu.linkonce.") - 1;
1563   if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0
1564       && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0)
1565     {
1566       strcpy (newname, ".gnu.linkonce.literal");
1567       strcpy (newname4, ".gnu.linkonce.lit4");
1568
1569       strcat (newname, linkonce_suffix);
1570       strcat (newname4, linkonce_suffix);
1571     }
1572   else
1573     {
1574       int suffix_pos = len;
1575
1576       /* If the section name ends with ".text", then replace that suffix
1577          instead of appending an additional suffix.  */
1578       if (len >= 5 && strcmp (name + len - 5, ".text") == 0)
1579         suffix_pos -= 5;
1580
1581       strcpy (newname, name);
1582       strcpy (newname4, name);
1583
1584       strcpy (newname + suffix_pos, ".literal");
1585       strcpy (newname4 + suffix_pos, ".lit4");
1586     }
1587
1588   /* Note that retrieve_literal_seg does not create a segment if
1589      it already exists.  */
1590   default_lit_sections.lit_seg = NULL;
1591   default_lit_sections.lit4_seg = NULL;
1592
1593   /* Canonicalizing section names allows renaming literal
1594      sections to occur correctly.  */
1595   default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname);
1596   default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4);
1597
1598   free (name);
1599 }
1600
1601
1602 /* Support ".frequency branch_target_frequency fall_through_frequency".  */
1603
1604 static void
1605 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
1606 {
1607   float fall_through_f, target_f;
1608   subseg_map *seginfo;
1609
1610   fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1611   if (fall_through_f < 0)
1612     {
1613       as_bad (_("fall through frequency must be greater than 0"));
1614       ignore_rest_of_line ();
1615       return;
1616     }
1617
1618   target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1619   if (target_f < 0)
1620     {
1621       as_bad (_("branch target frequency must be greater than 0"));
1622       ignore_rest_of_line ();
1623       return;
1624     }
1625
1626   seginfo = get_subseg_info (now_seg, now_subseg);
1627   seginfo->cur_target_freq = target_f;
1628   seginfo->cur_total_freq = target_f + fall_through_f;
1629
1630   demand_empty_rest_of_line ();
1631 }
1632
1633
1634 /* Like normal .long/.short/.word, except support @plt, etc.
1635    Clobbers input_line_pointer, checks end-of-line.  */
1636
1637 static void
1638 xtensa_elf_cons (int nbytes)
1639 {
1640   expressionS exp;
1641   bfd_reloc_code_real_type reloc;
1642
1643   md_flush_pending_output ();
1644
1645   if (cur_vinsn.inside_bundle)
1646     as_bad (_("directives are not valid inside bundles"));
1647
1648   if (is_it_end_of_statement ())
1649     {
1650       demand_empty_rest_of_line ();
1651       return;
1652     }
1653
1654   do
1655     {
1656       expression (&exp);
1657       if (exp.X_op == O_symbol
1658           && *input_line_pointer == '@'
1659           && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1660               != BFD_RELOC_NONE))
1661         {
1662           reloc_howto_type *reloc_howto =
1663             bfd_reloc_type_lookup (stdoutput, reloc);
1664
1665           if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1666             as_bad (_("unsupported relocation"));
1667           else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1668                     && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1669                    || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1670                        && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1671             as_bad (_("opcode-specific %s relocation used outside "
1672                       "an instruction"), reloc_howto->name);
1673           else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1674             as_bad (_("%s relocations do not fit in %d bytes"),
1675                     reloc_howto->name, nbytes);
1676           else
1677             {
1678               char *p = frag_more ((int) nbytes);
1679               xtensa_set_frag_assembly_state (frag_now);
1680               fix_new_exp (frag_now, p - frag_now->fr_literal,
1681                            nbytes, &exp, 0, reloc);
1682             }
1683         }
1684       else
1685         emit_expr (&exp, (unsigned int) nbytes);
1686     }
1687   while (*input_line_pointer++ == ',');
1688
1689   input_line_pointer--;         /* Put terminator back into stream.  */
1690   demand_empty_rest_of_line ();
1691 }
1692
1693 \f
1694 /* Parsing and Idiom Translation.  */
1695
1696 /* Parse @plt, etc. and return the desired relocation.  */
1697 static bfd_reloc_code_real_type
1698 xtensa_elf_suffix (char **str_p, expressionS *exp_p)
1699 {
1700   struct map_bfd
1701   {
1702     char *string;
1703     int length;
1704     bfd_reloc_code_real_type reloc;
1705   };
1706
1707   char ident[20];
1708   char *str = *str_p;
1709   char *str2;
1710   int ch;
1711   int len;
1712   struct map_bfd *ptr;
1713
1714 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1715
1716   static struct map_bfd mapping[] =
1717   {
1718     MAP ("l",           BFD_RELOC_LO16),
1719     MAP ("h",           BFD_RELOC_HI16),
1720     MAP ("plt",         BFD_RELOC_XTENSA_PLT),
1721     { (char *) 0, 0,    BFD_RELOC_UNUSED }
1722   };
1723
1724   if (*str++ != '@')
1725     return BFD_RELOC_NONE;
1726
1727   for (ch = *str, str2 = ident;
1728        (str2 < ident + sizeof (ident) - 1
1729         && (ISALNUM (ch) || ch == '@'));
1730        ch = *++str)
1731     {
1732       *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1733     }
1734
1735   *str2 = '\0';
1736   len = str2 - ident;
1737
1738   ch = ident[0];
1739   for (ptr = &mapping[0]; ptr->length > 0; ptr++)
1740     if (ch == ptr->string[0]
1741         && len == ptr->length
1742         && memcmp (ident, ptr->string, ptr->length) == 0)
1743       {
1744         /* Now check for "identifier@suffix+constant".  */
1745         if (*str == '-' || *str == '+')
1746           {
1747             char *orig_line = input_line_pointer;
1748             expressionS new_exp;
1749
1750             input_line_pointer = str;
1751             expression (&new_exp);
1752             if (new_exp.X_op == O_constant)
1753               {
1754                 exp_p->X_add_number += new_exp.X_add_number;
1755                 str = input_line_pointer;
1756               }
1757
1758             if (&input_line_pointer != str_p)
1759               input_line_pointer = orig_line;
1760           }
1761
1762         *str_p = str;
1763         return ptr->reloc;
1764       }
1765
1766   return BFD_RELOC_UNUSED;
1767 }
1768
1769
1770 static const char *
1771 expression_end (const char *name)
1772 {
1773   while (1)
1774     {
1775       switch (*name)
1776         {
1777         case '}':
1778         case ';':
1779         case '\0':
1780         case ',':
1781         case ':':
1782           return name;
1783         case ' ':
1784         case '\t':
1785           ++name;
1786           continue;
1787         default:
1788           return 0;
1789         }
1790     }
1791 }
1792
1793
1794 #define ERROR_REG_NUM ((unsigned) -1)
1795
1796 static unsigned
1797 tc_get_register (const char *prefix)
1798 {
1799   unsigned reg;
1800   const char *next_expr;
1801   const char *old_line_pointer;
1802
1803   SKIP_WHITESPACE ();
1804   old_line_pointer = input_line_pointer;
1805
1806   if (*input_line_pointer == '$')
1807     ++input_line_pointer;
1808
1809   /* Accept "sp" as a synonym for "a1".  */
1810   if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1811       && expression_end (input_line_pointer + 2))
1812     {
1813       input_line_pointer += 2;
1814       return 1;  /* AR[1] */
1815     }
1816
1817   while (*input_line_pointer++ == *prefix++)
1818     ;
1819   --input_line_pointer;
1820   --prefix;
1821
1822   if (*prefix)
1823     {
1824       as_bad (_("bad register name: %s"), old_line_pointer);
1825       return ERROR_REG_NUM;
1826     }
1827
1828   if (!ISDIGIT ((unsigned char) *input_line_pointer))
1829     {
1830       as_bad (_("bad register number: %s"), input_line_pointer);
1831       return ERROR_REG_NUM;
1832     }
1833
1834   reg = 0;
1835
1836   while (ISDIGIT ((int) *input_line_pointer))
1837     reg = reg * 10 + *input_line_pointer++ - '0';
1838
1839   if (!(next_expr = expression_end (input_line_pointer)))
1840     {
1841       as_bad (_("bad register name: %s"), old_line_pointer);
1842       return ERROR_REG_NUM;
1843     }
1844
1845   input_line_pointer = (char *) next_expr;
1846
1847   return reg;
1848 }
1849
1850
1851 static void
1852 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
1853 {
1854   xtensa_isa isa = xtensa_default_isa;
1855
1856   /* Check if this is an immediate operand.  */
1857   if (xtensa_operand_is_register (isa, opc, opnd) == 0)
1858     {
1859       bfd_reloc_code_real_type reloc;
1860       segT t = expression (tok);
1861       if (t == absolute_section
1862           && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
1863         {
1864           assert (tok->X_op == O_constant);
1865           tok->X_op = O_symbol;
1866           tok->X_add_symbol = &abs_symbol;
1867         }
1868
1869       if ((tok->X_op == O_constant || tok->X_op == O_symbol)
1870           && (reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1871           && (reloc != BFD_RELOC_NONE))
1872         {
1873           switch (reloc)
1874             {
1875               default:
1876               case BFD_RELOC_UNUSED:
1877                 as_bad (_("unsupported relocation"));
1878                 break;
1879
1880               case BFD_RELOC_XTENSA_PLT:
1881                 tok->X_op = O_pltrel;
1882                 break;
1883
1884               case BFD_RELOC_LO16:
1885                 if (tok->X_op == O_constant)
1886                   tok->X_add_number &= 0xffff;
1887                 else
1888                   tok->X_op = O_lo16;
1889                 break;
1890
1891               case BFD_RELOC_HI16:
1892                 if (tok->X_op == O_constant)
1893                   tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
1894                 else
1895                   tok->X_op = O_hi16;
1896                 break;
1897             }
1898         }
1899     }
1900   else
1901     {
1902       xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1903       unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
1904
1905       if (reg != ERROR_REG_NUM) /* Already errored */
1906         {
1907           uint32 buf = reg;
1908           if (xtensa_operand_encode (isa, opc, opnd, &buf))
1909             as_bad (_("register number out of range"));
1910         }
1911
1912       tok->X_op = O_register;
1913       tok->X_add_symbol = 0;
1914       tok->X_add_number = reg;
1915     }
1916 }
1917
1918
1919 /* Split up the arguments for an opcode or pseudo-op.  */
1920
1921 static int
1922 tokenize_arguments (char **args, char *str)
1923 {
1924   char *old_input_line_pointer;
1925   bfd_boolean saw_comma = FALSE;
1926   bfd_boolean saw_arg = FALSE;
1927   bfd_boolean saw_colon = FALSE;
1928   int num_args = 0;
1929   char *arg_end, *arg;
1930   int arg_len;
1931
1932   /* Save and restore input_line_pointer around this function.  */
1933   old_input_line_pointer = input_line_pointer;
1934   input_line_pointer = str;
1935
1936   while (*input_line_pointer)
1937     {
1938       SKIP_WHITESPACE ();
1939       switch (*input_line_pointer)
1940         {
1941         case '\0':
1942         case '}':
1943           goto fini;
1944
1945         case ':':
1946           input_line_pointer++;
1947           if (saw_comma || saw_colon || !saw_arg)
1948             goto err;
1949           saw_colon = TRUE;
1950           break;
1951
1952         case ',':
1953           input_line_pointer++;
1954           if (saw_comma || saw_colon || !saw_arg)
1955             goto err;
1956           saw_comma = TRUE;
1957           break;
1958
1959         default:
1960           if (!saw_comma && !saw_colon && saw_arg)
1961             goto err;
1962
1963           arg_end = input_line_pointer + 1;
1964           while (!expression_end (arg_end))
1965             arg_end += 1;
1966
1967           arg_len = arg_end - input_line_pointer;
1968           arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1);
1969           args[num_args] = arg;
1970
1971           if (saw_colon)
1972             *arg++ = ':';
1973           strncpy (arg, input_line_pointer, arg_len);
1974           arg[arg_len] = '\0';
1975
1976           input_line_pointer = arg_end;
1977           num_args += 1;
1978           saw_comma = FALSE;
1979           saw_colon = FALSE;
1980           saw_arg = TRUE;
1981           break;
1982         }
1983     }
1984
1985 fini:
1986   if (saw_comma || saw_colon)
1987     goto err;
1988   input_line_pointer = old_input_line_pointer;
1989   return num_args;
1990
1991 err:
1992   if (saw_comma)
1993     as_bad (_("extra comma"));
1994   else if (saw_colon)
1995     as_bad (_("extra colon"));
1996   else if (!saw_arg)
1997     as_bad (_("missing argument"));
1998   else
1999     as_bad (_("missing comma or colon"));
2000   input_line_pointer = old_input_line_pointer;
2001   return -1;
2002 }
2003
2004
2005 /* Parse the arguments to an opcode.  Return TRUE on error.  */
2006
2007 static bfd_boolean
2008 parse_arguments (TInsn *insn, int num_args, char **arg_strings)
2009 {
2010   expressionS *tok, *last_tok;
2011   xtensa_opcode opcode = insn->opcode;
2012   bfd_boolean had_error = TRUE;
2013   xtensa_isa isa = xtensa_default_isa;
2014   int n, num_regs = 0;
2015   int opcode_operand_count;
2016   int opnd_cnt, last_opnd_cnt;
2017   unsigned int next_reg = 0;
2018   char *old_input_line_pointer;
2019
2020   if (insn->insn_type == ITYPE_LITERAL)
2021     opcode_operand_count = 1;
2022   else
2023     opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
2024
2025   tok = insn->tok;
2026   memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
2027
2028   /* Save and restore input_line_pointer around this function.  */
2029   old_input_line_pointer = input_line_pointer;
2030
2031   last_tok = 0;
2032   last_opnd_cnt = -1;
2033   opnd_cnt = 0;
2034
2035   /* Skip invisible operands.  */
2036   while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
2037     {
2038       opnd_cnt += 1;
2039       tok++;
2040     }
2041
2042   for (n = 0; n < num_args; n++)
2043     {
2044       input_line_pointer = arg_strings[n];
2045       if (*input_line_pointer == ':')
2046         {
2047           xtensa_regfile opnd_rf;
2048           input_line_pointer++;
2049           if (num_regs == 0)
2050             goto err;
2051           assert (opnd_cnt > 0);
2052           num_regs--;
2053           opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2054           if (next_reg
2055               != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2056             as_warn (_("incorrect register number, ignoring"));
2057           next_reg++;
2058         }
2059       else
2060         {
2061           if (opnd_cnt >= opcode_operand_count)
2062             {
2063               as_warn (_("too many arguments"));
2064               goto err;
2065             }
2066           assert (opnd_cnt < MAX_INSN_ARGS);
2067
2068           expression_maybe_register (opcode, opnd_cnt, tok);
2069           next_reg = tok->X_add_number + 1;
2070
2071           if (tok->X_op == O_illegal || tok->X_op == O_absent)
2072             goto err;
2073           if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2074             {
2075               num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2076               /* minus 1 because we are seeing one right now */
2077             }
2078           else
2079             num_regs = 0;
2080
2081           last_tok = tok;
2082           last_opnd_cnt = opnd_cnt;
2083
2084           do
2085             {
2086               opnd_cnt += 1;
2087               tok++;
2088             }
2089           while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2090         }
2091     }
2092
2093   if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2094     goto err;
2095
2096   insn->ntok = tok - insn->tok;
2097   had_error = FALSE;
2098
2099  err:
2100   input_line_pointer = old_input_line_pointer;
2101   return had_error;
2102 }
2103
2104
2105 static int
2106 get_invisible_operands (TInsn *insn)
2107 {
2108   xtensa_isa isa = xtensa_default_isa;
2109   static xtensa_insnbuf slotbuf = NULL;
2110   xtensa_format fmt;
2111   xtensa_opcode opc = insn->opcode;
2112   int slot, opnd, fmt_found;
2113   unsigned val;
2114
2115   if (!slotbuf)
2116     slotbuf = xtensa_insnbuf_alloc (isa);
2117
2118   /* Find format/slot where this can be encoded.  */
2119   fmt_found = 0;
2120   slot = 0;
2121   for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2122     {
2123       for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2124         {
2125           if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2126             {
2127               fmt_found = 1;
2128               break;
2129             }
2130         }
2131       if (fmt_found) break;
2132     }
2133
2134   if (!fmt_found)
2135     {
2136       as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2137       return -1;
2138     }
2139
2140   /* First encode all the visible operands
2141      (to deal with shared field operands).  */
2142   for (opnd = 0; opnd < insn->ntok; opnd++)
2143     {
2144       if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2145           && (insn->tok[opnd].X_op == O_register
2146               || insn->tok[opnd].X_op == O_constant))
2147         {
2148           val = insn->tok[opnd].X_add_number;
2149           xtensa_operand_encode (isa, opc, opnd, &val);
2150           xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2151         }
2152     }
2153
2154   /* Then pull out the values for the invisible ones.  */
2155   for (opnd = 0; opnd < insn->ntok; opnd++)
2156     {
2157       if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2158         {
2159           xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2160           xtensa_operand_decode (isa, opc, opnd, &val);
2161           insn->tok[opnd].X_add_number = val;
2162           if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2163             insn->tok[opnd].X_op = O_register;
2164           else
2165             insn->tok[opnd].X_op = O_constant;
2166         }
2167     }
2168
2169   return 0;
2170 }
2171
2172
2173 static void
2174 xg_reverse_shift_count (char **cnt_argp)
2175 {
2176   char *cnt_arg, *new_arg;
2177   cnt_arg = *cnt_argp;
2178
2179   /* replace the argument with "31-(argument)" */
2180   new_arg = (char *) xmalloc (strlen (cnt_arg) + 6);
2181   sprintf (new_arg, "31-(%s)", cnt_arg);
2182
2183   free (cnt_arg);
2184   *cnt_argp = new_arg;
2185 }
2186
2187
2188 /* If "arg" is a constant expression, return non-zero with the value
2189    in *valp.  */
2190
2191 static int
2192 xg_arg_is_constant (char *arg, offsetT *valp)
2193 {
2194   expressionS exp;
2195   char *save_ptr = input_line_pointer;
2196
2197   input_line_pointer = arg;
2198   expression (&exp);
2199   input_line_pointer = save_ptr;
2200
2201   if (exp.X_op == O_constant)
2202     {
2203       *valp = exp.X_add_number;
2204       return 1;
2205     }
2206
2207   return 0;
2208 }
2209
2210
2211 static void
2212 xg_replace_opname (char **popname, char *newop)
2213 {
2214   free (*popname);
2215   *popname = (char *) xmalloc (strlen (newop) + 1);
2216   strcpy (*popname, newop);
2217 }
2218
2219
2220 static int
2221 xg_check_num_args (int *pnum_args,
2222                    int expected_num,
2223                    char *opname,
2224                    char **arg_strings)
2225 {
2226   int num_args = *pnum_args;
2227
2228   if (num_args < expected_num)
2229     {
2230       as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2231               num_args, opname, expected_num);
2232       return -1;
2233     }
2234
2235   if (num_args > expected_num)
2236     {
2237       as_warn (_("too many operands (%d) for '%s'; expected %d"),
2238                num_args, opname, expected_num);
2239       while (num_args-- > expected_num)
2240         {
2241           free (arg_strings[num_args]);
2242           arg_strings[num_args] = 0;
2243         }
2244       *pnum_args = expected_num;
2245       return -1;
2246     }
2247
2248   return 0;
2249 }
2250
2251
2252 /* If the register is not specified as part of the opcode,
2253    then get it from the operand and move it to the opcode.  */
2254
2255 static int
2256 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
2257 {
2258   xtensa_isa isa = xtensa_default_isa;
2259   xtensa_sysreg sr;
2260   char *opname, *new_opname;
2261   const char *sr_name;
2262   int is_user, is_write;
2263   bfd_boolean has_underbar = FALSE;
2264
2265   opname = *popname;
2266   if (*opname == '_')
2267     {
2268       has_underbar = TRUE;
2269       opname += 1;
2270     }
2271   is_user = (opname[1] == 'u');
2272   is_write = (opname[0] == 'w');
2273
2274   /* Opname == [rw]ur or [rwx]sr... */
2275
2276   if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2277     return -1;
2278
2279   /* Check if the argument is a symbolic register name.  */
2280   sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2281   /* Handle WSR to "INTSET" as a special case.  */
2282   if (sr == XTENSA_UNDEFINED && is_write && !is_user
2283       && !strcasecmp (arg_strings[1], "intset"))
2284     sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2285   if (sr == XTENSA_UNDEFINED
2286       || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2287     {
2288       /* Maybe it's a register number.... */
2289       offsetT val;
2290       if (!xg_arg_is_constant (arg_strings[1], &val))
2291         {
2292           as_bad (_("invalid register '%s' for '%s' instruction"),
2293                   arg_strings[1], opname);
2294           return -1;
2295         }
2296       sr = xtensa_sysreg_lookup (isa, val, is_user);
2297       if (sr == XTENSA_UNDEFINED)
2298         {
2299           as_bad (_("invalid register number (%ld) for '%s' instruction"),
2300                   val, opname);
2301           return -1;
2302         }
2303     }
2304
2305   /* Remove the last argument, which is now part of the opcode.  */
2306   free (arg_strings[1]);
2307   arg_strings[1] = 0;
2308   *pnum_args = 1;
2309
2310   /* Translate the opcode.  */
2311   sr_name = xtensa_sysreg_name (isa, sr);
2312   /* Another special case for "WSR.INTSET"....  */
2313   if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2314     sr_name = "intset";
2315   new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2316   sprintf (new_opname, "%s%s.%s", (has_underbar ? "_" : ""),
2317            *popname, sr_name);
2318   free (*popname);
2319   *popname = new_opname;
2320
2321   return 0;
2322 }
2323
2324
2325 static int
2326 xtensa_translate_old_userreg_ops (char **popname)
2327 {
2328   xtensa_isa isa = xtensa_default_isa;
2329   xtensa_sysreg sr;
2330   char *opname, *new_opname;
2331   const char *sr_name;
2332   bfd_boolean has_underbar = FALSE;
2333
2334   opname = *popname;
2335   if (opname[0] == '_')
2336     {
2337       has_underbar = TRUE;
2338       opname += 1;
2339     }
2340
2341   sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2342   if (sr != XTENSA_UNDEFINED)
2343     {
2344       /* The new default name ("nnn") is different from the old default
2345          name ("URnnn").  The old default is handled below, and we don't
2346          want to recognize [RW]nnn, so do nothing if the name is the (new)
2347          default.  */
2348       static char namebuf[10];
2349       sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2350       if (strcmp (namebuf, opname + 1) == 0)
2351         return 0;
2352     }
2353   else
2354     {
2355       offsetT val;
2356       char *end;
2357
2358       /* Only continue if the reg name is "URnnn".  */
2359       if (opname[1] != 'u' || opname[2] != 'r')
2360         return 0;
2361       val = strtoul (opname + 3, &end, 10);
2362       if (*end != '\0')
2363         return 0;
2364
2365       sr = xtensa_sysreg_lookup (isa, val, 1);
2366       if (sr == XTENSA_UNDEFINED)
2367         {
2368           as_bad (_("invalid register number (%ld) for '%s'"),
2369                   val, opname);
2370           return -1;
2371         }
2372     }
2373
2374   /* Translate the opcode.  */
2375   sr_name = xtensa_sysreg_name (isa, sr);
2376   new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2377   sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2378            opname[0], sr_name);
2379   free (*popname);
2380   *popname = new_opname;
2381
2382   return 0;
2383 }
2384
2385
2386 static int
2387 xtensa_translate_zero_immed (char *old_op,
2388                              char *new_op,
2389                              char **popname,
2390                              int *pnum_args,
2391                              char **arg_strings)
2392 {
2393   char *opname;
2394   offsetT val;
2395
2396   opname = *popname;
2397   assert (opname[0] != '_');
2398
2399   if (strcmp (opname, old_op) != 0)
2400     return 0;
2401
2402   if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2403     return -1;
2404   if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2405     {
2406       xg_replace_opname (popname, new_op);
2407       free (arg_strings[1]);
2408       arg_strings[1] = arg_strings[2];
2409       arg_strings[2] = 0;
2410       *pnum_args = 2;
2411     }
2412
2413   return 0;
2414 }
2415
2416
2417 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2418    Returns non-zero if an error was found.  */
2419
2420 static int
2421 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
2422 {
2423   char *opname = *popname;
2424   bfd_boolean has_underbar = FALSE;
2425
2426   if (cur_vinsn.inside_bundle)
2427     return 0;
2428
2429   if (*opname == '_')
2430     {
2431       has_underbar = TRUE;
2432       opname += 1;
2433     }
2434
2435   if (strcmp (opname, "mov") == 0)
2436     {
2437       if (use_transform () && !has_underbar && density_supported)
2438         xg_replace_opname (popname, "mov.n");
2439       else
2440         {
2441           if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2442             return -1;
2443           xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2444           arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1);
2445           strcpy (arg_strings[2], arg_strings[1]);
2446           *pnum_args = 3;
2447         }
2448       return 0;
2449     }
2450
2451   if (strcmp (opname, "bbsi.l") == 0)
2452     {
2453       if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2454         return -1;
2455       xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2456       if (target_big_endian)
2457         xg_reverse_shift_count (&arg_strings[1]);
2458       return 0;
2459     }
2460
2461   if (strcmp (opname, "bbci.l") == 0)
2462     {
2463       if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2464         return -1;
2465       xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2466       if (target_big_endian)
2467         xg_reverse_shift_count (&arg_strings[1]);
2468       return 0;
2469     }
2470
2471   if (xtensa_nop_opcode == XTENSA_UNDEFINED
2472       && strcmp (opname, "nop") == 0)
2473     {
2474       if (use_transform () && !has_underbar && density_supported)
2475         xg_replace_opname (popname, "nop.n");
2476       else
2477         {
2478           if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2479             return -1;
2480           xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2481           arg_strings[0] = (char *) xmalloc (3);
2482           arg_strings[1] = (char *) xmalloc (3);
2483           arg_strings[2] = (char *) xmalloc (3);
2484           strcpy (arg_strings[0], "a1");
2485           strcpy (arg_strings[1], "a1");
2486           strcpy (arg_strings[2], "a1");
2487           *pnum_args = 3;
2488         }
2489       return 0;
2490     }
2491
2492   /* Recognize [RW]UR and [RWX]SR.  */
2493   if ((((opname[0] == 'r' || opname[0] == 'w')
2494         && (opname[1] == 'u' || opname[1] == 's'))
2495        || (opname[0] == 'x' && opname[1] == 's'))
2496       && opname[2] == 'r'
2497       && opname[3] == '\0')
2498     return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2499
2500   /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2501      [RW]<name> if <name> is the non-default name of a user register.  */
2502   if ((opname[0] == 'r' || opname[0] == 'w')
2503       && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2504     return xtensa_translate_old_userreg_ops (popname);
2505
2506   /* Relax branches that don't allow comparisons against an immediate value
2507      of zero to the corresponding branches with implicit zero immediates.  */
2508   if (!has_underbar && use_transform ())
2509     {
2510       if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2511                                        pnum_args, arg_strings))
2512         return -1;
2513
2514       if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2515                                        pnum_args, arg_strings))
2516         return -1;
2517
2518       if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2519                                        pnum_args, arg_strings))
2520         return -1;
2521
2522       if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2523                                        pnum_args, arg_strings))
2524         return -1;
2525     }
2526
2527   return 0;
2528 }
2529
2530 \f
2531 /* Functions for dealing with the Xtensa ISA.  */
2532
2533 /* Currently the assembler only allows us to use a single target per
2534    fragment.  Because of this, only one operand for a given
2535    instruction may be symbolic.  If there is a PC-relative operand,
2536    the last one is chosen.  Otherwise, the result is the number of the
2537    last immediate operand, and if there are none of those, we fail and
2538    return -1.  */
2539
2540 static int
2541 get_relaxable_immed (xtensa_opcode opcode)
2542 {
2543   int last_immed = -1;
2544   int noperands, opi;
2545
2546   if (opcode == XTENSA_UNDEFINED)
2547     return -1;
2548
2549   noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2550   for (opi = noperands - 1; opi >= 0; opi--)
2551     {
2552       if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2553         continue;
2554       if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2555         return opi;
2556       if (last_immed == -1
2557           && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2558         last_immed = opi;
2559     }
2560   return last_immed;
2561 }
2562
2563
2564 static xtensa_opcode
2565 get_opcode_from_buf (const char *buf, int slot)
2566 {
2567   static xtensa_insnbuf insnbuf = NULL;
2568   static xtensa_insnbuf slotbuf = NULL;
2569   xtensa_isa isa = xtensa_default_isa;
2570   xtensa_format fmt;
2571
2572   if (!insnbuf)
2573     {
2574       insnbuf = xtensa_insnbuf_alloc (isa);
2575       slotbuf = xtensa_insnbuf_alloc (isa);
2576     }
2577
2578   xtensa_insnbuf_from_chars (isa, insnbuf, buf, 0);
2579   fmt = xtensa_format_decode (isa, insnbuf);
2580   if (fmt == XTENSA_UNDEFINED)
2581     return XTENSA_UNDEFINED;
2582
2583   if (slot >= xtensa_format_num_slots (isa, fmt))
2584     return XTENSA_UNDEFINED;
2585
2586   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2587   return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
2588 }
2589
2590
2591 #ifdef TENSILICA_DEBUG
2592
2593 /* For debugging, print out the mapping of opcode numbers to opcodes.  */
2594
2595 static void
2596 xtensa_print_insn_table (void)
2597 {
2598   int num_opcodes, num_operands;
2599   xtensa_opcode opcode;
2600   xtensa_isa isa = xtensa_default_isa;
2601
2602   num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2603   for (opcode = 0; opcode < num_opcodes; opcode++)
2604     {
2605       int opn;
2606       fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2607       num_operands = xtensa_opcode_num_operands (isa, opcode);
2608       for (opn = 0; opn < num_operands; opn++)
2609         {
2610           if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2611             continue;
2612           if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2613             {
2614               xtensa_regfile opnd_rf =
2615                 xtensa_operand_regfile (isa, opcode, opn);
2616               fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2617             }
2618           else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2619             fputs ("[lLr] ", stderr);
2620           else
2621             fputs ("i ", stderr);
2622         }
2623       fprintf (stderr, "\n");
2624     }
2625 }
2626
2627
2628 static void
2629 print_vliw_insn (xtensa_insnbuf vbuf)
2630 {
2631   xtensa_isa isa = xtensa_default_isa;
2632   xtensa_format f = xtensa_format_decode (isa, vbuf);
2633   xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2634   int op;
2635
2636   fprintf (stderr, "format = %d\n", f);
2637
2638   for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2639     {
2640       xtensa_opcode opcode;
2641       const char *opname;
2642       int operands;
2643
2644       xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2645       opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2646       opname = xtensa_opcode_name (isa, opcode);
2647
2648       fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2649       fprintf (stderr, "   operands = ");
2650       for (operands = 0;
2651            operands < xtensa_opcode_num_operands (isa, opcode);
2652            operands++)
2653         {
2654           unsigned int val;
2655           if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2656             continue;
2657           xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2658           xtensa_operand_decode (isa, opcode, operands, &val);
2659           fprintf (stderr, "%d ", val);
2660         }
2661       fprintf (stderr, "\n");
2662     }
2663   xtensa_insnbuf_free (isa, sbuf);
2664 }
2665
2666 #endif /* TENSILICA_DEBUG */
2667
2668
2669 static bfd_boolean
2670 is_direct_call_opcode (xtensa_opcode opcode)
2671 {
2672   xtensa_isa isa = xtensa_default_isa;
2673   int n, num_operands;
2674
2675   if (xtensa_opcode_is_call (isa, opcode) == 0)
2676     return FALSE;
2677
2678   num_operands = xtensa_opcode_num_operands (isa, opcode);
2679   for (n = 0; n < num_operands; n++)
2680     {
2681       if (xtensa_operand_is_register (isa, opcode, n) == 0
2682           && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2683         return TRUE;
2684     }
2685   return FALSE;
2686 }
2687
2688
2689 /* Return TRUE if the opcode is an entry opcode.  This is used because
2690    "entry" adds an implicit ".align 4" and also the entry instruction
2691    has an extra check for an operand value.  */
2692
2693 static bfd_boolean
2694 is_entry_opcode (xtensa_opcode opcode)
2695 {
2696   if (opcode == XTENSA_UNDEFINED)
2697     return FALSE;
2698
2699   return (opcode == xtensa_entry_opcode);
2700 }
2701
2702
2703 /* Return TRUE if the opcode is a movi or movi.n opcode.  This is
2704    so we can relax "movi aX, foo" in the front end.  */
2705
2706 static bfd_boolean
2707 is_movi_opcode (xtensa_opcode opcode)
2708 {
2709   if (opcode == XTENSA_UNDEFINED)
2710     return FALSE;
2711
2712   return (opcode == xtensa_movi_opcode)
2713     || (opcode == xtensa_movi_n_opcode);
2714 }
2715
2716
2717 static bfd_boolean
2718 is_the_loop_opcode (xtensa_opcode opcode)
2719 {
2720   if (opcode == XTENSA_UNDEFINED)
2721     return FALSE;
2722
2723   return (opcode == xtensa_loop_opcode);
2724 }
2725
2726
2727 static bfd_boolean
2728 is_jx_opcode (xtensa_opcode opcode)
2729 {
2730   if (opcode == XTENSA_UNDEFINED)
2731     return FALSE;
2732
2733   return (opcode == xtensa_jx_opcode);
2734 }
2735
2736
2737 /* Return TRUE if the opcode is a retw or retw.n.
2738    Needed to add nops to avoid a hardware interlock issue.  */
2739
2740 static bfd_boolean
2741 is_windowed_return_opcode (xtensa_opcode opcode)
2742 {
2743   if (opcode == XTENSA_UNDEFINED)
2744     return FALSE;
2745
2746   return (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode);
2747 }
2748
2749
2750 /* Convert from BFD relocation type code to slot and operand number.
2751    Returns non-zero on failure.  */
2752
2753 static int
2754 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
2755 {
2756   if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2757       && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
2758     {
2759       *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2760       *is_alt = FALSE;
2761     }
2762   else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2763       && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
2764     {
2765       *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2766       *is_alt = TRUE;
2767     }
2768   else
2769     return -1;
2770
2771   return 0;
2772 }
2773
2774
2775 /* Convert from slot number to BFD relocation type code for the
2776    standard PC-relative relocations.  Return BFD_RELOC_NONE on
2777    failure.  */
2778
2779 static bfd_reloc_code_real_type
2780 encode_reloc (int slot)
2781 {
2782   if (slot < 0 || slot > 14)
2783     return BFD_RELOC_NONE;
2784
2785   return BFD_RELOC_XTENSA_SLOT0_OP + slot;
2786 }
2787
2788
2789 /* Convert from slot numbers to BFD relocation type code for the
2790    "alternate" relocations.  Return BFD_RELOC_NONE on failure.  */
2791
2792 static bfd_reloc_code_real_type
2793 encode_alt_reloc (int slot)
2794 {
2795   if (slot < 0 || slot > 14)
2796     return BFD_RELOC_NONE;
2797
2798   return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
2799 }
2800
2801
2802 static void
2803 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2804                             xtensa_format fmt,
2805                             int slot,
2806                             xtensa_opcode opcode,
2807                             int operand,
2808                             uint32 value,
2809                             const char *file,
2810                             unsigned int line)
2811 {
2812   uint32 valbuf = value;
2813
2814   if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
2815     {
2816       if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2817           == 1)
2818         as_bad_where ((char *) file, line,
2819                       _("operand %u is out of range for '%s'"), value,
2820                       xtensa_opcode_name (xtensa_default_isa, opcode));
2821       else
2822         as_bad_where ((char *) file, line,
2823                       _("operand %u is invalid for '%s'"), value,
2824                       xtensa_opcode_name (xtensa_default_isa, opcode));
2825       return;
2826     }
2827
2828   xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2829                             slotbuf, valbuf);
2830 }
2831
2832
2833 static uint32
2834 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2835                             xtensa_format fmt,
2836                             int slot,
2837                             xtensa_opcode opcode,
2838                             int opnum)
2839 {
2840   uint32 val = 0;
2841   (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2842                                    fmt, slot, slotbuf, &val);
2843   (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2844   return val;
2845 }
2846
2847 \f
2848 /* Checks for rules from xtensa-relax tables.  */
2849
2850 /* The routine xg_instruction_matches_option_term must return TRUE
2851    when a given option term is true.  The meaning of all of the option
2852    terms is given interpretation by this function.  This is needed when
2853    an option depends on the state of a directive, but there are no such
2854    options in use right now.  */
2855
2856 static bfd_boolean
2857 xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED,
2858                                     const ReqOrOption *option)
2859 {
2860   if (strcmp (option->option_name, "realnop") == 0
2861       || strncmp (option->option_name, "IsaUse", 6) == 0)
2862     {
2863       /* These conditions were evaluated statically when building the
2864          relaxation table.  There's no need to reevaluate them now.  */
2865       return TRUE;
2866     }
2867   else
2868     {
2869       as_fatal (_("internal error: unknown option name '%s'"),
2870                 option->option_name);
2871     }
2872 }
2873
2874
2875 static bfd_boolean
2876 xg_instruction_matches_or_options (TInsn *insn,
2877                                    const ReqOrOptionList *or_option)
2878 {
2879   const ReqOrOption *option;
2880   /* Must match each of the AND terms.  */
2881   for (option = or_option; option != NULL; option = option->next)
2882     {
2883       if (xg_instruction_matches_option_term (insn, option))
2884         return TRUE;
2885     }
2886   return FALSE;
2887 }
2888
2889
2890 static bfd_boolean
2891 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
2892 {
2893   const ReqOption *req_options;
2894   /* Must match each of the AND terms.  */
2895   for (req_options = options;
2896        req_options != NULL;
2897        req_options = req_options->next)
2898     {
2899       /* Must match one of the OR clauses.  */
2900       if (!xg_instruction_matches_or_options (insn,
2901                                               req_options->or_option_terms))
2902         return FALSE;
2903     }
2904   return TRUE;
2905 }
2906
2907
2908 /* Return the transition rule that matches or NULL if none matches.  */
2909
2910 static bfd_boolean
2911 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
2912 {
2913   PreconditionList *condition_l;
2914
2915   if (rule->opcode != insn->opcode)
2916     return FALSE;
2917
2918   for (condition_l = rule->conditions;
2919        condition_l != NULL;
2920        condition_l = condition_l->next)
2921     {
2922       expressionS *exp1;
2923       expressionS *exp2;
2924       Precondition *cond = condition_l->precond;
2925
2926       switch (cond->typ)
2927         {
2928         case OP_CONSTANT:
2929           /* The expression must be the constant.  */
2930           assert (cond->op_num < insn->ntok);
2931           exp1 = &insn->tok[cond->op_num];
2932           if (expr_is_const (exp1))
2933             {
2934               switch (cond->cmp)
2935                 {
2936                 case OP_EQUAL:
2937                   if (get_expr_const (exp1) != cond->op_data)
2938                     return FALSE;
2939                   break;
2940                 case OP_NOTEQUAL:
2941                   if (get_expr_const (exp1) == cond->op_data)
2942                     return FALSE;
2943                   break;
2944                 default:
2945                   return FALSE;
2946                 }
2947             }
2948           else if (expr_is_register (exp1))
2949             {
2950               switch (cond->cmp)
2951                 {
2952                 case OP_EQUAL:
2953                   if (get_expr_register (exp1) != cond->op_data)
2954                     return FALSE;
2955                   break;
2956                 case OP_NOTEQUAL:
2957                   if (get_expr_register (exp1) == cond->op_data)
2958                     return FALSE;
2959                   break;
2960                 default:
2961                   return FALSE;
2962                 }
2963             }
2964           else
2965             return FALSE;
2966           break;
2967
2968         case OP_OPERAND:
2969           assert (cond->op_num < insn->ntok);
2970           assert (cond->op_data < insn->ntok);
2971           exp1 = &insn->tok[cond->op_num];
2972           exp2 = &insn->tok[cond->op_data];
2973
2974           switch (cond->cmp)
2975             {
2976             case OP_EQUAL:
2977               if (!expr_is_equal (exp1, exp2))
2978                 return FALSE;
2979               break;
2980             case OP_NOTEQUAL:
2981               if (expr_is_equal (exp1, exp2))
2982                 return FALSE;
2983               break;
2984             }
2985           break;
2986
2987         case OP_LITERAL:
2988         case OP_LABEL:
2989         default:
2990           return FALSE;
2991         }
2992     }
2993   if (!xg_instruction_matches_options (insn, rule->options))
2994     return FALSE;
2995
2996   return TRUE;
2997 }
2998
2999
3000 static int
3001 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
3002 {
3003   bfd_boolean a_greater = FALSE;
3004   bfd_boolean b_greater = FALSE;
3005
3006   ReqOptionList *l_a = a->options;
3007   ReqOptionList *l_b = b->options;
3008
3009   /* We only care if they both are the same except for
3010      a const16 vs. an l32r.  */
3011
3012   while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
3013     {
3014       ReqOrOptionList *l_or_a = l_a->or_option_terms;
3015       ReqOrOptionList *l_or_b = l_b->or_option_terms;
3016       while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
3017         {
3018           if (l_or_a->is_true != l_or_b->is_true)
3019             return 0;
3020           if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
3021             {
3022               /* This is the case we care about.  */
3023               if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
3024                   && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
3025                 {
3026                   if (prefer_const16)
3027                     a_greater = TRUE;
3028                   else
3029                     b_greater = TRUE;
3030                 }
3031               else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
3032                        && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
3033                 {
3034                   if (prefer_const16)
3035                     b_greater = TRUE;
3036                   else
3037                     a_greater = TRUE;
3038                 }
3039               else
3040                 return 0;
3041             }
3042           l_or_a = l_or_a->next;
3043           l_or_b = l_or_b->next;
3044         }
3045       if (l_or_a || l_or_b)
3046         return 0;
3047
3048       l_a = l_a->next;
3049       l_b = l_b->next;
3050     }
3051   if (l_a || l_b)
3052     return 0;
3053
3054   /* Incomparable if the substitution was used differently in two cases.  */
3055   if (a_greater && b_greater)
3056     return 0;
3057
3058   if (b_greater)
3059     return 1;
3060   if (a_greater)
3061     return -1;
3062
3063   return 0;
3064 }
3065
3066
3067 static TransitionRule *
3068 xg_instruction_match (TInsn *insn)
3069 {
3070   TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
3071   TransitionList *l;
3072   assert (insn->opcode < table->num_opcodes);
3073
3074   /* Walk through all of the possible transitions.  */
3075   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3076     {
3077       TransitionRule *rule = l->rule;
3078       if (xg_instruction_matches_rule (insn, rule))
3079         return rule;
3080     }
3081   return NULL;
3082 }
3083
3084 \f
3085 /* Various Other Internal Functions.  */
3086
3087 static bfd_boolean
3088 is_unique_insn_expansion (TransitionRule *r)
3089 {
3090   if (!r->to_instr || r->to_instr->next != NULL)
3091     return FALSE;
3092   if (r->to_instr->typ != INSTR_INSTR)
3093     return FALSE;
3094   return TRUE;
3095 }
3096
3097
3098 static int
3099 xg_get_build_instr_size (BuildInstr *insn)
3100 {
3101   assert (insn->typ == INSTR_INSTR);
3102   return xg_get_single_size (insn->opcode);
3103 }
3104
3105
3106 static bfd_boolean
3107 xg_is_narrow_insn (TInsn *insn)
3108 {
3109   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3110   TransitionList *l;
3111   int num_match = 0;
3112   assert (insn->insn_type == ITYPE_INSN);
3113   assert (insn->opcode < table->num_opcodes);
3114
3115   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3116     {
3117       TransitionRule *rule = l->rule;
3118
3119       if (xg_instruction_matches_rule (insn, rule)
3120           && is_unique_insn_expansion (rule))
3121         {
3122           /* It only generates one instruction... */
3123           assert (insn->insn_type == ITYPE_INSN);
3124           /* ...and it is a larger instruction.  */
3125           if (xg_get_single_size (insn->opcode)
3126               < xg_get_build_instr_size (rule->to_instr))
3127             {
3128               num_match++;
3129               if (num_match > 1)
3130                 return FALSE;
3131             }
3132         }
3133     }
3134   return (num_match == 1);
3135 }
3136
3137
3138 static bfd_boolean
3139 xg_is_single_relaxable_insn (TInsn *insn)
3140 {
3141   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3142   TransitionList *l;
3143   int num_match = 0;
3144   assert (insn->insn_type == ITYPE_INSN);
3145   assert (insn->opcode < table->num_opcodes);
3146
3147   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3148     {
3149       TransitionRule *rule = l->rule;
3150
3151       if (xg_instruction_matches_rule (insn, rule)
3152           && is_unique_insn_expansion (rule))
3153         {
3154           /* It only generates one instruction... */
3155           assert (insn->insn_type == ITYPE_INSN);
3156           /* ... and it is a larger instruction.  */
3157           if (xg_get_single_size (insn->opcode)
3158               <= xg_get_build_instr_size (rule->to_instr))
3159             {
3160               num_match++;
3161               if (num_match > 1)
3162                 return FALSE;
3163             }
3164         }
3165     }
3166   return (num_match == 1);
3167 }
3168
3169
3170 /* Return the maximum number of bytes this opcode can expand to.  */
3171
3172 static int
3173 xg_get_max_insn_widen_size (xtensa_opcode opcode)
3174 {
3175   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3176   TransitionList *l;
3177   int max_size = xg_get_single_size (opcode);
3178
3179   assert (opcode < table->num_opcodes);
3180
3181   for (l = table->table[opcode]; l != NULL; l = l->next)
3182     {
3183       TransitionRule *rule = l->rule;
3184       BuildInstr *build_list;
3185       int this_size = 0;
3186
3187       if (!rule)
3188         continue;
3189       build_list = rule->to_instr;
3190       if (is_unique_insn_expansion (rule))
3191         {
3192           assert (build_list->typ == INSTR_INSTR);
3193           this_size = xg_get_max_insn_widen_size (build_list->opcode);
3194         }
3195       else
3196         for (; build_list != NULL; build_list = build_list->next)
3197           {
3198             switch (build_list->typ)
3199               {
3200               case INSTR_INSTR:
3201                 this_size += xg_get_single_size (build_list->opcode);
3202                 break;
3203               case INSTR_LITERAL_DEF:
3204               case INSTR_LABEL_DEF:
3205               default:
3206                 break;
3207               }
3208           }
3209       if (this_size > max_size)
3210         max_size = this_size;
3211     }
3212   return max_size;
3213 }
3214
3215
3216 /* Return the maximum number of literal bytes this opcode can generate.  */
3217
3218 static int
3219 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
3220 {
3221   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3222   TransitionList *l;
3223   int max_size = 0;
3224
3225   assert (opcode < table->num_opcodes);
3226
3227   for (l = table->table[opcode]; l != NULL; l = l->next)
3228     {
3229       TransitionRule *rule = l->rule;
3230       BuildInstr *build_list;
3231       int this_size = 0;
3232
3233       if (!rule)
3234         continue;
3235       build_list = rule->to_instr;
3236       if (is_unique_insn_expansion (rule))
3237         {
3238           assert (build_list->typ == INSTR_INSTR);
3239           this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3240         }
3241       else
3242         for (; build_list != NULL; build_list = build_list->next)
3243           {
3244             switch (build_list->typ)
3245               {
3246               case INSTR_LITERAL_DEF:
3247                 /* Hard-coded 4-byte literal.  */
3248                 this_size += 4;
3249                 break;
3250               case INSTR_INSTR:
3251               case INSTR_LABEL_DEF:
3252               default:
3253                 break;
3254               }
3255           }
3256       if (this_size > max_size)
3257         max_size = this_size;
3258     }
3259   return max_size;
3260 }
3261
3262
3263 static bfd_boolean
3264 xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3265 {
3266   int steps_taken = 0;
3267   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3268   TransitionList *l;
3269
3270   assert (insn->insn_type == ITYPE_INSN);
3271   assert (insn->opcode < table->num_opcodes);
3272
3273   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3274     {
3275       TransitionRule *rule = l->rule;
3276
3277       if (xg_instruction_matches_rule (insn, rule))
3278         {
3279           if (steps_taken == lateral_steps)
3280             return TRUE;
3281           steps_taken++;
3282         }
3283     }
3284   return FALSE;
3285 }
3286
3287
3288 static symbolS *
3289 get_special_literal_symbol (void)
3290 {
3291   static symbolS *sym = NULL;
3292
3293   if (sym == NULL)
3294     sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3295   return sym;
3296 }
3297
3298
3299 static symbolS *
3300 get_special_label_symbol (void)
3301 {
3302   static symbolS *sym = NULL;
3303
3304   if (sym == NULL)
3305     sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3306   return sym;
3307 }
3308
3309
3310 static bfd_boolean
3311 xg_valid_literal_expression (const expressionS *exp)
3312 {
3313   switch (exp->X_op)
3314     {
3315     case O_constant:
3316     case O_symbol:
3317     case O_big:
3318     case O_uminus:
3319     case O_subtract:
3320     case O_pltrel:
3321       return TRUE;
3322     default:
3323       return FALSE;
3324     }
3325 }
3326
3327
3328 /* This will check to see if the value can be converted into the
3329    operand type.  It will return TRUE if it does not fit.  */
3330
3331 static bfd_boolean
3332 xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3333 {
3334   uint32 valbuf = value;
3335   if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3336     return TRUE;
3337   return FALSE;
3338 }
3339
3340
3341 /* Assumes: All immeds are constants.  Check that all constants fit
3342    into their immeds; return FALSE if not.  */
3343
3344 static bfd_boolean
3345 xg_immeds_fit (const TInsn *insn)
3346 {
3347   xtensa_isa isa = xtensa_default_isa;
3348   int i;
3349
3350   int n = insn->ntok;
3351   assert (insn->insn_type == ITYPE_INSN);
3352   for (i = 0; i < n; ++i)
3353     {
3354       const expressionS *expr = &insn->tok[i];
3355       if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3356         continue;
3357
3358       switch (expr->X_op)
3359         {
3360         case O_register:
3361         case O_constant:
3362           if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3363             return FALSE;
3364           break;
3365
3366         default:
3367           /* The symbol should have a fixup associated with it.  */
3368           assert (FALSE);
3369           break;
3370         }
3371     }
3372   return TRUE;
3373 }
3374
3375
3376 /* This should only be called after we have an initial
3377    estimate of the addresses.  */
3378
3379 static bfd_boolean
3380 xg_symbolic_immeds_fit (const TInsn *insn,
3381                         segT pc_seg,
3382                         fragS *pc_frag,
3383                         offsetT pc_offset,
3384                         long stretch)
3385 {
3386   xtensa_isa isa = xtensa_default_isa;
3387   symbolS *symbolP;
3388   fragS *sym_frag;
3389   offsetT target, pc;
3390   uint32 new_offset;
3391   int i;
3392   int n = insn->ntok;
3393
3394   assert (insn->insn_type == ITYPE_INSN);
3395
3396   for (i = 0; i < n; ++i)
3397     {
3398       const expressionS *expr = &insn->tok[i];
3399       if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3400         continue;
3401
3402       switch (expr->X_op)
3403         {
3404         case O_register:
3405         case O_constant:
3406           if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3407             return FALSE;
3408           break;
3409
3410         case O_lo16:
3411         case O_hi16:
3412           /* Check for the worst case.  */
3413           if (xg_check_operand (0xffff, insn->opcode, i))
3414             return FALSE;
3415           break;
3416
3417         case O_symbol:
3418           /* We only allow symbols for pc-relative stuff.
3419              If pc_frag == 0, then we don't have frag locations yet.  */
3420           if (pc_frag == 0)
3421             return FALSE;
3422
3423           /* If it is PC-relative and the symbol is not in the same
3424              segment as the PC.... */
3425           if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0
3426               || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
3427             return FALSE;
3428
3429           /* If it is a weak symbol, then assume it won't reach.  This will
3430              only affect calls when longcalls are enabled, because if
3431              longcalls are disabled, then the call is marked as a specific
3432              opcode.  */
3433           if (S_IS_WEAK (expr->X_add_symbol))
3434             return FALSE;
3435
3436           symbolP = expr->X_add_symbol;
3437           sym_frag = symbol_get_frag (symbolP);
3438           target = S_GET_VALUE (symbolP) + expr->X_add_number;
3439           pc = pc_frag->fr_address + pc_offset;
3440
3441           /* If frag has yet to be reached on this pass, assume it
3442              will move by STRETCH just as we did.  If this is not so,
3443              it will be because some frag between grows, and that will
3444              force another pass.  Beware zero-length frags.  There
3445              should be a faster way to do this.  */
3446
3447           if (stretch != 0
3448               && sym_frag->relax_marker != pc_frag->relax_marker
3449               && S_GET_SEGMENT (symbolP) == pc_seg)
3450             {
3451               target += stretch;
3452             }
3453
3454           new_offset = target;
3455           xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3456           if (xg_check_operand (new_offset, insn->opcode, i))
3457             return FALSE;
3458           break;
3459
3460         default:
3461           /* The symbol should have a fixup associated with it.  */
3462           return FALSE;
3463         }
3464     }
3465
3466   return TRUE;
3467 }
3468
3469
3470 /* Return TRUE on success.  */
3471
3472 static bfd_boolean
3473 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
3474 {
3475   BuildOp *op;
3476   symbolS *sym;
3477
3478   memset (targ, 0, sizeof (TInsn));
3479   targ->loc = insn->loc;
3480   switch (bi->typ)
3481     {
3482     case INSTR_INSTR:
3483       op = bi->ops;
3484       targ->opcode = bi->opcode;
3485       targ->insn_type = ITYPE_INSN;
3486       targ->is_specific_opcode = FALSE;
3487
3488       for (; op != NULL; op = op->next)
3489         {
3490           int op_num = op->op_num;
3491           int op_data = op->op_data;
3492
3493           assert (op->op_num < MAX_INSN_ARGS);
3494
3495           if (targ->ntok <= op_num)
3496             targ->ntok = op_num + 1;
3497
3498           switch (op->typ)
3499             {
3500             case OP_CONSTANT:
3501               set_expr_const (&targ->tok[op_num], op_data);
3502               break;
3503             case OP_OPERAND:
3504               assert (op_data < insn->ntok);
3505               copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3506               break;
3507             case OP_LITERAL:
3508               sym = get_special_literal_symbol ();
3509               set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3510               break;
3511             case OP_LABEL:
3512               sym = get_special_label_symbol ();
3513               set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3514               break;
3515             case OP_OPERAND_HI16U:
3516             case OP_OPERAND_LOW16U:
3517               assert (op_data < insn->ntok);
3518               if (expr_is_const (&insn->tok[op_data]))
3519                 {
3520                   long val;
3521                   copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3522                   val = xg_apply_userdef_op_fn (op->typ,
3523                                                 targ->tok[op_num].
3524                                                 X_add_number);
3525                   targ->tok[op_num].X_add_number = val;
3526                 }
3527               else
3528                 {
3529                   /* For const16 we can create relocations for these.  */
3530                   if (targ->opcode == XTENSA_UNDEFINED
3531                       || (targ->opcode != xtensa_const16_opcode))
3532                     return FALSE;
3533                   assert (op_data < insn->ntok);
3534                   /* Need to build a O_lo16 or O_hi16.  */
3535                   copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3536                   if (targ->tok[op_num].X_op == O_symbol)
3537                     {
3538                       if (op->typ == OP_OPERAND_HI16U)
3539                         targ->tok[op_num].X_op = O_hi16;
3540                       else if (op->typ == OP_OPERAND_LOW16U)
3541                         targ->tok[op_num].X_op = O_lo16;
3542                       else
3543                         return FALSE;
3544                     }
3545                 }
3546               break;
3547             default:
3548               /* currently handles:
3549                  OP_OPERAND_LOW8
3550                  OP_OPERAND_HI24S
3551                  OP_OPERAND_F32MINUS */
3552               if (xg_has_userdef_op_fn (op->typ))
3553                 {
3554                   assert (op_data < insn->ntok);
3555                   if (expr_is_const (&insn->tok[op_data]))
3556                     {
3557                       long val;
3558                       copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3559                       val = xg_apply_userdef_op_fn (op->typ,
3560                                                     targ->tok[op_num].
3561                                                     X_add_number);
3562                       targ->tok[op_num].X_add_number = val;
3563                     }
3564                   else
3565                     return FALSE; /* We cannot use a relocation for this.  */
3566                   break;
3567                 }
3568               assert (0);
3569               break;
3570             }
3571         }
3572       break;
3573
3574     case INSTR_LITERAL_DEF:
3575       op = bi->ops;
3576       targ->opcode = XTENSA_UNDEFINED;
3577       targ->insn_type = ITYPE_LITERAL;
3578       targ->is_specific_opcode = FALSE;
3579       for (; op != NULL; op = op->next)
3580         {
3581           int op_num = op->op_num;
3582           int op_data = op->op_data;
3583           assert (op->op_num < MAX_INSN_ARGS);
3584
3585           if (targ->ntok <= op_num)
3586             targ->ntok = op_num + 1;
3587
3588           switch (op->typ)
3589             {
3590             case OP_OPERAND:
3591               assert (op_data < insn->ntok);
3592               /* We can only pass resolvable literals through.  */
3593               if (!xg_valid_literal_expression (&insn->tok[op_data]))
3594                 return FALSE;
3595               copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3596               break;
3597             case OP_LITERAL:
3598             case OP_CONSTANT:
3599             case OP_LABEL:
3600             default:
3601               assert (0);
3602               break;
3603             }
3604         }
3605       break;
3606
3607     case INSTR_LABEL_DEF:
3608       op = bi->ops;
3609       targ->opcode = XTENSA_UNDEFINED;
3610       targ->insn_type = ITYPE_LABEL;
3611       targ->is_specific_opcode = FALSE;
3612       /* Literal with no ops is a label?  */
3613       assert (op == NULL);
3614       break;
3615
3616     default:
3617       assert (0);
3618     }
3619
3620   return TRUE;
3621 }
3622
3623
3624 /* Return TRUE on success.  */
3625
3626 static bfd_boolean
3627 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
3628 {
3629   for (; bi != NULL; bi = bi->next)
3630     {
3631       TInsn *next_insn = istack_push_space (istack);
3632
3633       if (!xg_build_to_insn (next_insn, insn, bi))
3634         return FALSE;
3635     }
3636   return TRUE;
3637 }
3638
3639
3640 /* Return TRUE on valid expansion.  */
3641
3642 static bfd_boolean
3643 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
3644 {
3645   int stack_size = istack->ninsn;
3646   int steps_taken = 0;
3647   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3648   TransitionList *l;
3649
3650   assert (insn->insn_type == ITYPE_INSN);
3651   assert (insn->opcode < table->num_opcodes);
3652
3653   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3654     {
3655       TransitionRule *rule = l->rule;
3656
3657       if (xg_instruction_matches_rule (insn, rule))
3658         {
3659           if (lateral_steps == steps_taken)
3660             {
3661               int i;
3662
3663               /* This is it.  Expand the rule to the stack.  */
3664               if (!xg_build_to_stack (istack, insn, rule->to_instr))
3665                 return FALSE;
3666
3667               /* Check to see if it fits.  */
3668               for (i = stack_size; i < istack->ninsn; i++)
3669                 {
3670                   TInsn *insn = &istack->insn[i];
3671
3672                   if (insn->insn_type == ITYPE_INSN
3673                       && !tinsn_has_symbolic_operands (insn)
3674                       && !xg_immeds_fit (insn))
3675                     {
3676                       istack->ninsn = stack_size;
3677                       return FALSE;
3678                     }
3679                 }
3680               return TRUE;
3681             }
3682           steps_taken++;
3683         }
3684     }
3685   return FALSE;
3686 }
3687
3688
3689 static bfd_boolean
3690 xg_expand_narrow (TInsn *targ, TInsn *insn)
3691 {
3692   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3693   TransitionList *l;
3694
3695   assert (insn->insn_type == ITYPE_INSN);
3696   assert (insn->opcode < table->num_opcodes);
3697
3698   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3699     {
3700       TransitionRule *rule = l->rule;
3701       if (xg_instruction_matches_rule (insn, rule)
3702           && is_unique_insn_expansion (rule))
3703         {
3704           /* Is it a larger instruction?  */
3705           if (xg_get_single_size (insn->opcode)
3706               <= xg_get_build_instr_size (rule->to_instr))
3707             {
3708               xg_build_to_insn (targ, insn, rule->to_instr);
3709               return FALSE;
3710             }
3711         }
3712     }
3713   return TRUE;
3714 }
3715
3716 \f
3717 /* Relax the assembly instruction at least "min_steps".
3718    Return the number of steps taken.  */
3719
3720 static int
3721 xg_assembly_relax (IStack *istack,
3722                    TInsn *insn,
3723                    segT pc_seg,
3724                    fragS *pc_frag,      /* if pc_frag == 0, not pc-relative */
3725                    offsetT pc_offset,   /* offset in fragment */
3726                    int min_steps,       /* minimum conversion steps */
3727                    long stretch)        /* number of bytes stretched so far */
3728 {
3729   int steps_taken = 0;
3730
3731   /* assert (has no symbolic operands)
3732      Some of its immeds don't fit.
3733      Try to build a relaxed version.
3734      This may go through a couple of stages
3735      of single instruction transformations before
3736      we get there.  */
3737
3738   TInsn single_target;
3739   TInsn current_insn;
3740   int lateral_steps = 0;
3741   int istack_size = istack->ninsn;
3742
3743   if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3744       && steps_taken >= min_steps)
3745     {
3746       istack_push (istack, insn);
3747       return steps_taken;
3748     }
3749   current_insn = *insn;
3750
3751   /* Walk through all of the single instruction expansions. */
3752   while (xg_is_single_relaxable_insn (&current_insn))
3753     {
3754       int error_val = xg_expand_narrow (&single_target, &current_insn);
3755
3756       assert (!error_val);
3757
3758       if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3759                                   stretch))
3760         {
3761           steps_taken++;
3762           if (steps_taken >= min_steps)
3763             {
3764               istack_push (istack, &single_target);
3765               return steps_taken;
3766             }
3767         }
3768       current_insn = single_target;
3769     }
3770
3771   /* Now check for a multi-instruction expansion.  */
3772   while (xg_is_relaxable_insn (&current_insn, lateral_steps))
3773     {
3774       if (xg_symbolic_immeds_fit (&current_insn, pc_seg, pc_frag, pc_offset,
3775                                   stretch))
3776         {
3777           if (steps_taken >= min_steps)
3778             {
3779               istack_push (istack, &current_insn);
3780               return steps_taken;
3781             }
3782         }
3783       steps_taken++;
3784       if (xg_expand_to_stack (istack, &current_insn, lateral_steps))
3785         {
3786           if (steps_taken >= min_steps)
3787             return steps_taken;
3788         }
3789       lateral_steps++;
3790       istack->ninsn = istack_size;
3791     }
3792
3793   /* It's not going to work -- use the original.  */
3794   istack_push (istack, insn);
3795   return steps_taken;
3796 }
3797
3798
3799 static void
3800 xg_force_frag_space (int size)
3801 {
3802   /* This may have the side effect of creating a new fragment for the
3803      space to go into.  I just do not like the name of the "frag"
3804      functions.  */
3805   frag_grow (size);
3806 }
3807
3808
3809 static void
3810 xg_finish_frag (char *last_insn,
3811                 enum xtensa_relax_statesE frag_state,
3812                 enum xtensa_relax_statesE slot0_state,
3813                 int max_growth,
3814                 bfd_boolean is_insn)
3815 {
3816   /* Finish off this fragment so that it has at LEAST the desired
3817      max_growth.  If it doesn't fit in this fragment, close this one
3818      and start a new one.  In either case, return a pointer to the
3819      beginning of the growth area.  */
3820
3821   fragS *old_frag;
3822
3823   xg_force_frag_space (max_growth);
3824
3825   old_frag = frag_now;
3826
3827   frag_now->fr_opcode = last_insn;
3828   if (is_insn)
3829     frag_now->tc_frag_data.is_insn = TRUE;
3830
3831   frag_var (rs_machine_dependent, max_growth, max_growth,
3832             frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3833
3834   old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3835   xtensa_set_frag_assembly_state (frag_now);
3836
3837   /* Just to make sure that we did not split it up.  */
3838   assert (old_frag->fr_next == frag_now);
3839 }
3840
3841
3842 /* Return TRUE if the target frag is one of the next non-empty frags.  */
3843
3844 static bfd_boolean
3845 is_next_frag_target (const fragS *fragP, const fragS *target)
3846 {
3847   if (fragP == NULL)
3848     return FALSE;
3849
3850   for (; fragP; fragP = fragP->fr_next)
3851     {
3852       if (fragP == target)
3853         return TRUE;
3854       if (fragP->fr_fix != 0)
3855         return FALSE;
3856       if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3857         return FALSE;
3858       if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3859           && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3860         return FALSE;
3861       if (fragP->fr_type == rs_space)
3862         return FALSE;
3863     }
3864   return FALSE;
3865 }
3866
3867
3868 static bfd_boolean
3869 is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
3870 {
3871   xtensa_isa isa = xtensa_default_isa;
3872   int i;
3873   int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3874   int target_op = -1;
3875   symbolS *sym;
3876   fragS *target_frag;
3877
3878   if (xtensa_opcode_is_branch (isa, insn->opcode) == 0
3879       && xtensa_opcode_is_jump (isa, insn->opcode) == 0)
3880     return FALSE;
3881
3882   for (i = 0; i < num_ops; i++)
3883     {
3884       if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
3885         {
3886           target_op = i;
3887           break;
3888         }
3889     }
3890   if (target_op == -1)
3891     return FALSE;
3892
3893   if (insn->ntok <= target_op)
3894     return FALSE;
3895
3896   if (insn->tok[target_op].X_op != O_symbol)
3897     return FALSE;
3898
3899   sym = insn->tok[target_op].X_add_symbol;
3900   if (sym == NULL)
3901     return FALSE;
3902
3903   if (insn->tok[target_op].X_add_number != 0)
3904     return FALSE;
3905
3906   target_frag = symbol_get_frag (sym);
3907   if (target_frag == NULL)
3908     return FALSE;
3909
3910   if (is_next_frag_target (fragP->fr_next, target_frag)
3911       && S_GET_VALUE (sym) == target_frag->fr_address)
3912     return TRUE;
3913
3914   return FALSE;
3915 }
3916
3917
3918 static void
3919 xg_add_branch_and_loop_targets (TInsn *insn)
3920 {
3921   xtensa_isa isa = xtensa_default_isa;
3922   int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3923
3924   if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3925     {
3926       int i = 1;
3927       if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3928           && insn->tok[i].X_op == O_symbol)
3929         symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
3930       return;
3931     }
3932
3933   if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3934       || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3935     {
3936       int i;
3937
3938       for (i = 0; i < insn->ntok && i < num_ops; i++)
3939         {
3940           if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3941               && insn->tok[i].X_op == O_symbol)
3942             {
3943               symbolS *sym = insn->tok[i].X_add_symbol;
3944               symbol_get_tc (sym)->is_branch_target = TRUE;
3945               if (S_IS_DEFINED (sym))
3946                 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
3947             }
3948         }
3949     }
3950 }
3951
3952
3953 /* Return FALSE if no error.  */
3954
3955 static bfd_boolean
3956 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
3957 {
3958   int num_ops = 0;
3959   BuildOp *b_op;
3960
3961   switch (instr_spec->typ)
3962     {
3963     case INSTR_INSTR:
3964       new_insn->insn_type = ITYPE_INSN;
3965       new_insn->opcode = instr_spec->opcode;
3966       new_insn->is_specific_opcode = FALSE;
3967       new_insn->loc = old_insn->loc;
3968       break;
3969     case INSTR_LITERAL_DEF:
3970       new_insn->insn_type = ITYPE_LITERAL;
3971       new_insn->opcode = XTENSA_UNDEFINED;
3972       new_insn->is_specific_opcode = FALSE;
3973       new_insn->loc = old_insn->loc;
3974       break;
3975     case INSTR_LABEL_DEF:
3976       as_bad (_("INSTR_LABEL_DEF not supported yet"));
3977       break;
3978     }
3979
3980   for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3981     {
3982       expressionS *exp;
3983       const expressionS *src_exp;
3984
3985       num_ops++;
3986       switch (b_op->typ)
3987         {
3988         case OP_CONSTANT:
3989           /* The expression must be the constant.  */
3990           assert (b_op->op_num < MAX_INSN_ARGS);
3991           exp = &new_insn->tok[b_op->op_num];
3992           set_expr_const (exp, b_op->op_data);
3993           break;
3994
3995         case OP_OPERAND:
3996           assert (b_op->op_num < MAX_INSN_ARGS);
3997           assert (b_op->op_data < (unsigned) old_insn->ntok);
3998           src_exp = &old_insn->tok[b_op->op_data];
3999           exp = &new_insn->tok[b_op->op_num];
4000           copy_expr (exp, src_exp);
4001           break;
4002
4003         case OP_LITERAL:
4004         case OP_LABEL:
4005           as_bad (_("can't handle generation of literal/labels yet"));
4006           assert (0);
4007
4008         default:
4009           as_bad (_("can't handle undefined OP TYPE"));
4010           assert (0);
4011         }
4012     }
4013
4014   new_insn->ntok = num_ops;
4015   return FALSE;
4016 }
4017
4018
4019 /* Return TRUE if it was simplified.  */
4020
4021 static bfd_boolean
4022 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
4023 {
4024   TransitionRule *rule;
4025   BuildInstr *insn_spec;
4026
4027   if (old_insn->is_specific_opcode || !density_supported)
4028     return FALSE;
4029
4030   rule = xg_instruction_match (old_insn);
4031   if (rule == NULL)
4032     return FALSE;
4033
4034   insn_spec = rule->to_instr;
4035   /* There should only be one.  */
4036   assert (insn_spec != NULL);
4037   assert (insn_spec->next == NULL);
4038   if (insn_spec->next != NULL)
4039     return FALSE;
4040
4041   xg_build_token_insn (insn_spec, old_insn, new_insn);
4042
4043   return TRUE;
4044 }
4045
4046
4047 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4048    l32i.n. (2) Check the number of operands.  (3) Place the instruction
4049    tokens into the stack or if we can relax it at assembly time, place
4050    multiple instructions/literals onto the stack.  Return FALSE if no
4051    error.  */
4052
4053 static bfd_boolean
4054 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
4055 {
4056   int noperands;
4057   TInsn new_insn;
4058   memset (&new_insn, 0, sizeof (TInsn));
4059
4060   /* Narrow it if we can.  xg_simplify_insn now does all the
4061      appropriate checking (e.g., for the density option).  */
4062   if (xg_simplify_insn (orig_insn, &new_insn))
4063     orig_insn = &new_insn;
4064
4065   noperands = xtensa_opcode_num_operands (xtensa_default_isa,
4066                                           orig_insn->opcode);
4067   if (orig_insn->ntok < noperands)
4068     {
4069       as_bad (_("found %d operands for '%s':  Expected %d"),
4070               orig_insn->ntok,
4071               xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4072               noperands);
4073       return TRUE;
4074     }
4075   if (orig_insn->ntok > noperands)
4076     as_warn (_("found too many (%d) operands for '%s':  Expected %d"),
4077              orig_insn->ntok,
4078              xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4079              noperands);
4080
4081   /* If there are not enough operands, we will assert above.  If there
4082      are too many, just cut out the extras here.  */
4083
4084   orig_insn->ntok = noperands;
4085
4086   /* Cases:
4087
4088      Instructions with all constant immeds:
4089      Assemble them and relax the instruction if possible.
4090      Give error if not possible; no fixup needed.
4091
4092      Instructions with symbolic immeds:
4093      Assemble them with a Fix up (that may cause instruction expansion).
4094      Also close out the fragment if the fixup may cause instruction expansion.
4095
4096      There are some other special cases where we need alignment.
4097      1) before certain instructions with required alignment (OPCODE_ALIGN)
4098      2) before labels that have jumps (LABEL_ALIGN)
4099      3) after call instructions (RETURN_ALIGN)
4100         Multiple of these may be possible on the same fragment.
4101         If so, make sure to satisfy the required alignment.
4102         Then try to get the desired alignment.  */
4103
4104   if (tinsn_has_invalid_symbolic_operands (orig_insn))
4105     return TRUE;
4106
4107   if (orig_insn->is_specific_opcode || !use_transform ())
4108     {
4109       istack_push (istack, orig_insn);
4110       return FALSE;
4111     }
4112
4113   if (tinsn_has_symbolic_operands (orig_insn))
4114     {
4115       if (tinsn_has_complex_operands (orig_insn))
4116         xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4117       else
4118         istack_push (istack, orig_insn);
4119     }
4120   else
4121     {
4122       if (xg_immeds_fit (orig_insn))
4123         istack_push (istack, orig_insn);
4124       else
4125         xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4126     }
4127
4128   return FALSE;
4129 }
4130
4131
4132 /* Return TRUE if the section flags are marked linkonce
4133    or the name is .gnu.linkonce*.  */
4134
4135 static bfd_boolean
4136 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
4137 {
4138   flagword flags, link_once_flags;
4139
4140   flags = bfd_get_section_flags (abfd, sec);
4141   link_once_flags = (flags & SEC_LINK_ONCE);
4142
4143   /* Flags might not be set yet.  */
4144   if (!link_once_flags)
4145     {
4146       static size_t len = sizeof ".gnu.linkonce.t.";
4147
4148       if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0)
4149         link_once_flags = SEC_LINK_ONCE;
4150     }
4151   return (link_once_flags != 0);
4152 }
4153
4154
4155 static void
4156 xtensa_add_literal_sym (symbolS *sym)
4157 {
4158   sym_list *l;
4159
4160   l = (sym_list *) xmalloc (sizeof (sym_list));
4161   l->sym = sym;
4162   l->next = literal_syms;
4163   literal_syms = l;
4164 }
4165
4166
4167 static symbolS *
4168 xtensa_create_literal_symbol (segT sec, fragS *frag)
4169 {
4170   static int lit_num = 0;
4171   static char name[256];
4172   symbolS *symbolP;
4173
4174   sprintf (name, ".L_lit_sym%d", lit_num);
4175
4176   /* Create a local symbol.  If it is in a linkonce section, we have to
4177      be careful to make sure that if it is used in a relocation that the
4178      symbol will be in the output file.  */
4179   if (get_is_linkonce_section (stdoutput, sec))
4180     {
4181       symbolP = symbol_new (name, sec, 0, frag);
4182       S_CLEAR_EXTERNAL (symbolP);
4183       /* symbolP->local = 1; */
4184     }
4185   else
4186     symbolP = symbol_new (name, sec, 0, frag);
4187
4188   xtensa_add_literal_sym (symbolP);
4189
4190   frag->tc_frag_data.is_literal = TRUE;
4191   lit_num++;
4192   return symbolP;
4193 }
4194
4195
4196 /* Currently all literals that are generated here are 32-bit L32R targets.  */
4197
4198 static symbolS *
4199 xg_assemble_literal (/* const */ TInsn *insn)
4200 {
4201   emit_state state;
4202   symbolS *lit_sym = NULL;
4203
4204   /* size = 4 for L32R.  It could easily be larger when we move to
4205      larger constants.  Add a parameter later.  */
4206   offsetT litsize = 4;
4207   offsetT litalign = 2;         /* 2^2 = 4 */
4208   expressionS saved_loc;
4209   expressionS * emit_val;
4210
4211   set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4212
4213   assert (insn->insn_type == ITYPE_LITERAL);
4214   assert (insn->ntok == 1);     /* must be only one token here */
4215
4216   xtensa_switch_to_literal_fragment (&state);
4217
4218   emit_val = &insn->tok[0];
4219   if (emit_val->X_op == O_big)
4220     {
4221       int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4222       if (size > litsize)
4223         {
4224           /* This happens when someone writes a "movi a2, big_number".  */
4225           as_bad_where (frag_now->fr_file, frag_now->fr_line,
4226                         _("invalid immediate"));
4227           xtensa_restore_emit_state (&state);
4228           return NULL;
4229         }
4230     }
4231
4232   /* Force a 4-byte align here.  Note that this opens a new frag, so all
4233      literals done with this function have a frag to themselves.  That's
4234      important for the way text section literals work.  */
4235   frag_align (litalign, 0, 0);
4236   record_alignment (now_seg, litalign);
4237
4238   if (emit_val->X_op == O_pltrel)
4239     {
4240       char *p = frag_more (litsize);
4241       xtensa_set_frag_assembly_state (frag_now);
4242       if (emit_val->X_add_symbol)
4243         emit_val->X_op = O_symbol;
4244       else
4245         emit_val->X_op = O_constant;
4246       fix_new_exp (frag_now, p - frag_now->fr_literal,
4247                    litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT);
4248     }
4249   else
4250     emit_expr (emit_val, litsize);
4251
4252   assert (frag_now->tc_frag_data.literal_frag == NULL);
4253   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4254   frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4255   lit_sym = frag_now->fr_symbol;
4256   frag_now->tc_frag_data.is_literal = TRUE;
4257
4258   /* Go back.  */
4259   xtensa_restore_emit_state (&state);
4260   return lit_sym;
4261 }
4262
4263
4264 static void
4265 xg_assemble_literal_space (/* const */ int size, int slot)
4266 {
4267   emit_state state;
4268   /* We might have to do something about this alignment.  It only
4269      takes effect if something is placed here.  */
4270   offsetT litalign = 2;         /* 2^2 = 4 */
4271   fragS *lit_saved_frag;
4272
4273   assert (size % 4 == 0);
4274
4275   xtensa_switch_to_literal_fragment (&state);
4276
4277   /* Force a 4-byte align here.  */
4278   frag_align (litalign, 0, 0);
4279   record_alignment (now_seg, litalign);
4280
4281   xg_force_frag_space (size);
4282
4283   lit_saved_frag = frag_now;
4284   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4285   frag_now->tc_frag_data.is_literal = TRUE;
4286   frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4287   xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
4288
4289   /* Go back.  */
4290   xtensa_restore_emit_state (&state);
4291   frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
4292 }
4293
4294
4295 /* Put in a fixup record based on the opcode.
4296    Return TRUE on success.  */
4297
4298 static bfd_boolean
4299 xg_add_opcode_fix (TInsn *tinsn,
4300                    int opnum,
4301                    xtensa_format fmt,
4302                    int slot,
4303                    expressionS *expr,
4304                    fragS *fragP,
4305                    offsetT offset)
4306 {
4307   xtensa_opcode opcode = tinsn->opcode;
4308   bfd_reloc_code_real_type reloc;
4309   reloc_howto_type *howto;
4310   int fmt_length;
4311   fixS *the_fix;
4312
4313   reloc = BFD_RELOC_NONE;
4314
4315   /* First try the special cases for "alternate" relocs.  */
4316   if (opcode == xtensa_l32r_opcode)
4317     {
4318       if (fragP->tc_frag_data.use_absolute_literals)
4319         reloc = encode_alt_reloc (slot);
4320     }
4321   else if (opcode == xtensa_const16_opcode)
4322     {
4323       if (expr->X_op == O_lo16)
4324         {
4325           reloc = encode_reloc (slot);
4326           expr->X_op = O_symbol;
4327         }
4328       else if (expr->X_op == O_hi16)
4329         {
4330           reloc = encode_alt_reloc (slot);
4331           expr->X_op = O_symbol;
4332         }
4333     }
4334
4335   if (opnum != get_relaxable_immed (opcode))
4336     {
4337       as_bad (_("invalid relocation for operand %i of '%s'"),
4338               opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4339       return FALSE;
4340     }
4341
4342   /* Handle erroneous "@h" and "@l" expressions here before they propagate
4343      into the symbol table where the generic portions of the assembler
4344      won't know what to do with them.  */
4345   if (expr->X_op == O_lo16 || expr->X_op == O_hi16)
4346     {
4347       as_bad (_("invalid expression for operand %i of '%s'"),
4348               opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4349       return FALSE;
4350     }
4351
4352   /* Next try the generic relocs.  */
4353   if (reloc == BFD_RELOC_NONE)
4354     reloc = encode_reloc (slot);
4355   if (reloc == BFD_RELOC_NONE)
4356     {
4357       as_bad (_("invalid relocation in instruction slot %i"), slot);
4358       return FALSE;
4359     }
4360
4361   howto = bfd_reloc_type_lookup (stdoutput, reloc);
4362   if (!howto)
4363     {
4364       as_bad (_("undefined symbol for opcode \"%s\""),
4365               xtensa_opcode_name (xtensa_default_isa, opcode));
4366       return FALSE;
4367     }
4368
4369   fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4370   the_fix = fix_new_exp (fragP, offset, fmt_length, expr,
4371                          howto->pc_relative, reloc);
4372
4373   if (expr->X_add_symbol
4374       && (S_IS_EXTERNAL (expr->X_add_symbol)
4375           || S_IS_WEAK (expr->X_add_symbol)))
4376     the_fix->fx_plt = TRUE;
4377
4378   the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol;
4379   the_fix->tc_fix_data.X_add_number = expr->X_add_number;
4380   the_fix->tc_fix_data.slot = slot;
4381
4382   return TRUE;
4383 }
4384
4385
4386 static bfd_boolean
4387 xg_emit_insn_to_buf (TInsn *tinsn,
4388                      xtensa_format fmt,
4389                      char *buf,
4390                      fragS *fragP,
4391                      offsetT offset,
4392                      bfd_boolean build_fix)
4393 {
4394   static xtensa_insnbuf insnbuf = NULL;
4395   bfd_boolean has_symbolic_immed = FALSE;
4396   bfd_boolean ok = TRUE;
4397   if (!insnbuf)
4398     insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4399
4400   has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4401   if (has_symbolic_immed && build_fix)
4402     {
4403       /* Add a fixup.  */
4404       int opnum = get_relaxable_immed (tinsn->opcode);
4405       expressionS *exp = &tinsn->tok[opnum];
4406
4407       if (!xg_add_opcode_fix (tinsn, opnum, fmt, 0, exp, fragP, offset))
4408         ok = FALSE;
4409     }
4410   fragP->tc_frag_data.is_insn = TRUE;
4411   xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf, 0);
4412   return ok;
4413 }
4414
4415
4416 static void
4417 xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
4418 {
4419   symbolS *sym = get_special_literal_symbol ();
4420   int i;
4421   if (lit_sym == 0)
4422     return;
4423   assert (insn->insn_type == ITYPE_INSN);
4424   for (i = 0; i < insn->ntok; i++)
4425     if (insn->tok[i].X_add_symbol == sym)
4426       insn->tok[i].X_add_symbol = lit_sym;
4427
4428 }
4429
4430
4431 static void
4432 xg_resolve_labels (TInsn *insn, symbolS *label_sym)
4433 {
4434   symbolS *sym = get_special_label_symbol ();
4435   int i;
4436   /* assert (!insn->is_literal); */
4437   for (i = 0; i < insn->ntok; i++)
4438     if (insn->tok[i].X_add_symbol == sym)
4439       insn->tok[i].X_add_symbol = label_sym;
4440
4441 }
4442
4443
4444 /* Return TRUE if the instruction can write to the specified
4445    integer register.  */
4446
4447 static bfd_boolean
4448 is_register_writer (const TInsn *insn, const char *regset, int regnum)
4449 {
4450   int i;
4451   int num_ops;
4452   xtensa_isa isa = xtensa_default_isa;
4453
4454   num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
4455
4456   for (i = 0; i < num_ops; i++)
4457     {
4458       char inout;
4459       inout = xtensa_operand_inout (isa, insn->opcode, i);
4460       if ((inout == 'o' || inout == 'm')
4461           && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
4462         {
4463           xtensa_regfile opnd_rf =
4464             xtensa_operand_regfile (isa, insn->opcode, i);
4465           if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
4466             {
4467               if ((insn->tok[i].X_op == O_register)
4468                   && (insn->tok[i].X_add_number == regnum))
4469                 return TRUE;
4470             }
4471         }
4472     }
4473   return FALSE;
4474 }
4475
4476
4477 static bfd_boolean
4478 is_bad_loopend_opcode (const TInsn *tinsn)
4479 {
4480   xtensa_opcode opcode = tinsn->opcode;
4481
4482   if (opcode == XTENSA_UNDEFINED)
4483     return FALSE;
4484
4485   if (opcode == xtensa_call0_opcode
4486       || opcode == xtensa_callx0_opcode
4487       || opcode == xtensa_call4_opcode
4488       || opcode == xtensa_callx4_opcode
4489       || opcode == xtensa_call8_opcode
4490       || opcode == xtensa_callx8_opcode
4491       || opcode == xtensa_call12_opcode
4492       || opcode == xtensa_callx12_opcode
4493       || opcode == xtensa_isync_opcode
4494       || opcode == xtensa_ret_opcode
4495       || opcode == xtensa_ret_n_opcode
4496       || opcode == xtensa_retw_opcode
4497       || opcode == xtensa_retw_n_opcode
4498       || opcode == xtensa_waiti_opcode
4499       || opcode == xtensa_rsr_lcount_opcode)
4500     return TRUE;
4501
4502   return FALSE;
4503 }
4504
4505
4506 /* Labels that begin with ".Ln" or ".LM"  are unaligned.
4507    This allows the debugger to add unaligned labels.
4508    Also, the assembler generates stabs labels that need
4509    not be aligned:  FAKE_LABEL_NAME . {"F", "L", "endfunc"}.  */
4510
4511 static bfd_boolean
4512 is_unaligned_label (symbolS *sym)
4513 {
4514   const char *name = S_GET_NAME (sym);
4515   static size_t fake_size = 0;
4516
4517   if (name
4518       && name[0] == '.'
4519       && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4520     return TRUE;
4521
4522   /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4523   if (fake_size == 0)
4524     fake_size = strlen (FAKE_LABEL_NAME);
4525
4526   if (name
4527       && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4528       && (name[fake_size] == 'F'
4529           || name[fake_size] == 'L'
4530           || (name[fake_size] == 'e'
4531               && strncmp ("endfunc", name+fake_size, 7) == 0)))
4532     return TRUE;
4533
4534   return FALSE;
4535 }
4536
4537
4538 static fragS *
4539 next_non_empty_frag (const fragS *fragP)
4540 {
4541   fragS *next_fragP = fragP->fr_next;
4542
4543   /* Sometimes an empty will end up here due storage allocation issues.
4544      So we have to skip until we find something legit.  */
4545   while (next_fragP && next_fragP->fr_fix == 0)
4546     next_fragP = next_fragP->fr_next;
4547
4548   if (next_fragP == NULL || next_fragP->fr_fix == 0)
4549     return NULL;
4550
4551   return next_fragP;
4552 }
4553
4554
4555 static bfd_boolean
4556 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
4557 {
4558   xtensa_opcode out_opcode;
4559   const fragS *next_fragP = next_non_empty_frag (fragP);
4560
4561   if (next_fragP == NULL)
4562     return FALSE;
4563
4564   out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4565   if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4566     {
4567       *opcode = out_opcode;
4568       return TRUE;
4569     }
4570   return FALSE;
4571 }
4572
4573
4574 static int
4575 frag_format_size (const fragS *fragP)
4576 {
4577   static xtensa_insnbuf insnbuf = NULL;
4578   xtensa_isa isa = xtensa_default_isa;
4579   xtensa_format fmt;
4580   int fmt_size;
4581
4582   if (!insnbuf)
4583     insnbuf = xtensa_insnbuf_alloc (isa);
4584
4585   if (fragP == NULL)
4586     return XTENSA_UNDEFINED;
4587
4588   xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal, 0);
4589
4590   fmt = xtensa_format_decode (isa, insnbuf);
4591   if (fmt == XTENSA_UNDEFINED)
4592     return XTENSA_UNDEFINED;
4593   fmt_size = xtensa_format_length (isa, fmt);
4594
4595   /* If the next format won't be changing due to relaxation, just
4596      return the length of the first format.  */
4597   if (fragP->fr_opcode != fragP->fr_literal)
4598     return fmt_size;
4599
4600   /* If during relaxation we have to pull an instruction out of a
4601      multi-slot instruction, we will return the more conservative
4602      number.  This works because alignment on bigger instructions
4603      is more restrictive than alignment on smaller instructions.
4604      This is more conservative than we would like, but it happens
4605      infrequently.  */
4606
4607   if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4608     return fmt_size;
4609
4610   /* If we aren't doing one of our own relaxations or it isn't
4611      slot-based, then the insn size won't change.  */
4612   if (fragP->fr_type != rs_machine_dependent)
4613     return fmt_size;
4614   if (fragP->fr_subtype != RELAX_SLOTS)
4615     return fmt_size;
4616
4617   /* If an instruction is about to grow, return the longer size.  */
4618   if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
4619       || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2)
4620     return 3;
4621
4622   if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4623     return 2 + fragP->tc_frag_data.text_expansion[0];
4624
4625   return fmt_size;
4626 }
4627
4628
4629 static int
4630 next_frag_format_size (const fragS *fragP)
4631 {
4632   const fragS *next_fragP = next_non_empty_frag (fragP);
4633   return frag_format_size (next_fragP);
4634 }
4635
4636
4637 /* If the next legit fragment is an end-of-loop marker,
4638    switch its state so it will instantiate a NOP.  */
4639
4640 static void
4641 update_next_frag_state (fragS *fragP, bfd_boolean unreachable)
4642 {
4643   fragS *next_fragP = fragP->fr_next;
4644   fragS *new_target = NULL;
4645
4646   if (align_targets)
4647     {
4648       /* We are guaranteed there will be one of these...   */
4649       while (!(next_fragP->fr_type == rs_machine_dependent
4650                && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4651                    || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4652         next_fragP = next_fragP->fr_next;
4653
4654       assert (next_fragP->fr_type == rs_machine_dependent
4655               && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4656                   || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4657
4658       /* ...and one of these.  */
4659       new_target = next_fragP->fr_next;
4660       while (!(new_target->fr_type == rs_machine_dependent
4661                && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4662                    || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4663         new_target = new_target->fr_next;
4664
4665       assert (new_target->fr_type == rs_machine_dependent
4666               && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4667                   || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4668     }
4669   if (unreachable)
4670     {
4671       if (align_targets)
4672         {
4673           next_fragP->fr_subtype = RELAX_UNREACHABLE;
4674           next_fragP->tc_frag_data.is_unreachable = TRUE;
4675           new_target->fr_subtype = RELAX_DESIRE_ALIGN;
4676           new_target->tc_frag_data.is_branch_target = TRUE;
4677         }
4678       while (next_fragP && next_fragP->fr_fix == 0)
4679         {
4680           if (next_fragP->fr_type == rs_machine_dependent
4681               && next_fragP->fr_subtype == RELAX_LOOP_END)
4682             {
4683               next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4684               return;
4685             }
4686
4687           next_fragP = next_fragP->fr_next;
4688         }
4689     }
4690   else
4691     {
4692       if (align_targets)
4693         {
4694           next_fragP->fr_subtype = RELAX_MAYBE_UNREACHABLE;
4695           next_fragP->tc_frag_data.is_unreachable = FALSE;
4696           new_target->fr_subtype = RELAX_MAYBE_DESIRE_ALIGN;
4697           new_target->tc_frag_data.is_branch_target = FALSE;
4698         }
4699     }
4700 }
4701
4702
4703 static bfd_boolean
4704 next_frag_is_branch_target (const fragS *fragP)
4705 {
4706   /* Sometimes an empty will end up here due to storage allocation issues,
4707      so we have to skip until we find something legit.  */
4708   for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4709     {
4710       if (fragP->tc_frag_data.is_branch_target)
4711         return TRUE;
4712       if (fragP->fr_fix != 0)
4713         break;
4714     }
4715   return FALSE;
4716 }
4717
4718
4719 static bfd_boolean
4720 next_frag_is_loop_target (const fragS *fragP)
4721 {
4722   /* Sometimes an empty will end up here due storage allocation issues.
4723      So we have to skip until we find something legit. */
4724   for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4725     {
4726       if (fragP->tc_frag_data.is_loop_target)
4727         return TRUE;
4728       if (fragP->fr_fix != 0)
4729         break;
4730     }
4731   return FALSE;
4732 }
4733
4734
4735 static addressT
4736 next_frag_pre_opcode_bytes (const fragS *fragp)
4737 {
4738   const fragS *next_fragp = fragp->fr_next;
4739   xtensa_opcode next_opcode;
4740
4741   if (!next_frag_opcode_is_loop (fragp, &next_opcode))
4742     return 0;
4743
4744   /* Sometimes an empty will end up here due to storage allocation issues,
4745      so we have to skip until we find something legit.  */
4746   while (next_fragp->fr_fix == 0)
4747     next_fragp = next_fragp->fr_next;
4748
4749   if (next_fragp->fr_type != rs_machine_dependent)
4750     return 0;
4751
4752   /* There is some implicit knowledge encoded in here.
4753      The LOOP instructions that are NOT RELAX_IMMED have
4754      been relaxed.  Note that we can assume that the LOOP
4755      instruction is in slot 0 because loops aren't bundleable.  */
4756   if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
4757       return get_expanded_loop_offset (next_opcode);
4758
4759   return 0;
4760 }
4761
4762
4763 /* Mark a location where we can later insert literal frags.  Update
4764    the section's literal_pool_loc, so subsequent literals can be
4765    placed nearest to their use.  */
4766
4767 static void
4768 xtensa_mark_literal_pool_location (void)
4769 {
4770   /* Any labels pointing to the current location need
4771      to be adjusted to after the literal pool.  */
4772   emit_state s;
4773   fragS *pool_location;
4774
4775   if (use_literal_section && !directive_state[directive_absolute_literals])
4776     return;
4777
4778   frag_align (2, 0, 0);
4779   record_alignment (now_seg, 2);
4780
4781   /* We stash info in the fr_var of these frags
4782      so we can later move the literal's fixes into this
4783      frchain's fix list.  We can use fr_var because fr_var's
4784      interpretation depends solely on the fr_type and subtype.  */
4785   pool_location = frag_now;
4786   frag_variant (rs_machine_dependent, 0, (int) frchain_now,
4787                 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
4788   xtensa_set_frag_assembly_state (frag_now);
4789   frag_variant (rs_machine_dependent, 0, (int) now_seg,
4790                 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
4791   xtensa_set_frag_assembly_state (frag_now);
4792
4793   /* Now put a frag into the literal pool that points to this location.  */
4794   set_literal_pool_location (now_seg, pool_location);
4795   xtensa_switch_to_non_abs_literal_fragment (&s);
4796   frag_align (2, 0, 0);
4797   record_alignment (now_seg, 2);
4798
4799   /* Close whatever frag is there.  */
4800   frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4801   xtensa_set_frag_assembly_state (frag_now);
4802   frag_now->tc_frag_data.literal_frag = pool_location;
4803   frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4804   xtensa_restore_emit_state (&s);
4805   xtensa_set_frag_assembly_state (frag_now);
4806 }
4807
4808
4809 /* Build a nop of the correct size into tinsn.  */
4810
4811 static void
4812 build_nop (TInsn *tinsn, int size)
4813 {
4814   tinsn_init (tinsn);
4815   switch (size)
4816     {
4817     case 2:
4818       tinsn->opcode = xtensa_nop_n_opcode;
4819       tinsn->ntok = 0;
4820       if (tinsn->opcode == XTENSA_UNDEFINED)
4821         as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4822       break;
4823
4824     case 3:
4825       if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4826         {
4827           tinsn->opcode = xtensa_or_opcode;
4828           set_expr_const (&tinsn->tok[0], 1);
4829           set_expr_const (&tinsn->tok[1], 1);
4830           set_expr_const (&tinsn->tok[2], 1);
4831           tinsn->ntok = 3;
4832         }
4833       else
4834         tinsn->opcode = xtensa_nop_opcode;
4835
4836       assert (tinsn->opcode != XTENSA_UNDEFINED);
4837     }
4838 }
4839
4840
4841 /* Assemble a NOP of the requested size in the buffer.  User must have
4842    allocated "buf" with at least "size" bytes.  */
4843
4844 static void
4845 assemble_nop (size_t size, char *buf)
4846 {
4847   static xtensa_insnbuf insnbuf = NULL;
4848   TInsn tinsn;
4849
4850   build_nop (&tinsn, size);
4851
4852   if (!insnbuf)
4853     insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4854
4855   tinsn_to_insnbuf (&tinsn, insnbuf);
4856   xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf, 0);
4857 }
4858
4859
4860 /* Return the number of bytes for the offset of the expanded loop
4861    instruction.  This should be incorporated into the relaxation
4862    specification but is hard-coded here.  This is used to auto-align
4863    the loop instruction.  It is invalid to call this function if the
4864    configuration does not have loops or if the opcode is not a loop
4865    opcode.  */
4866
4867 static addressT
4868 get_expanded_loop_offset (xtensa_opcode opcode)
4869 {
4870   /* This is the OFFSET of the loop instruction in the expanded loop.
4871      This MUST correspond directly to the specification of the loop
4872      expansion.  It will be validated on fragment conversion.  */
4873   assert (opcode != XTENSA_UNDEFINED);
4874   if (opcode == xtensa_loop_opcode)
4875     return 0;
4876   if (opcode == xtensa_loopnez_opcode)
4877     return 3;
4878   if (opcode == xtensa_loopgtz_opcode)
4879     return 6;
4880   as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4881   return 0;
4882 }
4883
4884
4885 static fragS *
4886 get_literal_pool_location (segT seg)
4887 {
4888   return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4889 }
4890
4891
4892 static void
4893 set_literal_pool_location (segT seg, fragS *literal_pool_loc)
4894 {
4895   seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4896 }
4897
4898
4899 /* Set frag assembly state should be called when a new frag is
4900    opened and after a frag has been closed.  */
4901
4902 static void
4903 xtensa_set_frag_assembly_state (fragS *fragP)
4904 {
4905   if (!density_supported)
4906     fragP->tc_frag_data.is_no_density = TRUE;
4907
4908   /* This function is called from subsegs_finish, which is called
4909      after xtensa_end, so we can't use "use_transform" or
4910      "use_schedule" here.  */
4911   if (!directive_state[directive_transform])
4912     fragP->tc_frag_data.is_no_transform = TRUE;
4913   fragP->tc_frag_data.use_absolute_literals =
4914     directive_state[directive_absolute_literals];
4915   fragP->tc_frag_data.is_assembly_state_set = TRUE;
4916 }
4917
4918
4919 static bfd_boolean
4920 relaxable_section (asection *sec)
4921 {
4922   return (sec->flags & SEC_DEBUGGING) == 0;
4923 }
4924
4925
4926 static void
4927 xtensa_find_unmarked_state_frags (void)
4928 {
4929   segT *seclist;
4930
4931   /* Walk over each fragment of all of the current segments.  For each
4932      unmarked fragment, mark it with the same info as the previous
4933      fragment.  */
4934   for (seclist = &stdoutput->sections;
4935        seclist && *seclist;
4936        seclist = &(*seclist)->next)
4937     {
4938       segT sec = *seclist;
4939       segment_info_type *seginfo;
4940       fragS *fragP;
4941       flagword flags;
4942       flags = bfd_get_section_flags (stdoutput, sec);
4943       if (flags & SEC_DEBUGGING)
4944         continue;
4945       if (!(flags & SEC_ALLOC))
4946         continue;
4947
4948       seginfo = seg_info (sec);
4949       if (seginfo && seginfo->frchainP)
4950         {
4951           fragS *last_fragP = 0;
4952           for (fragP = seginfo->frchainP->frch_root; fragP;
4953                fragP = fragP->fr_next)
4954             {
4955               if (fragP->fr_fix != 0
4956                   && !fragP->tc_frag_data.is_assembly_state_set)
4957                 {
4958                   if (last_fragP == 0)
4959                     {
4960                       as_warn_where (fragP->fr_file, fragP->fr_line,
4961                                      _("assembly state not set for first frag in section %s"),
4962                                      sec->name);
4963                     }
4964                   else
4965                     {
4966                       fragP->tc_frag_data.is_assembly_state_set = TRUE;
4967                       fragP->tc_frag_data.is_no_density =
4968                         last_fragP->tc_frag_data.is_no_density;
4969                       fragP->tc_frag_data.is_no_transform =
4970                         last_fragP->tc_frag_data.is_no_transform;
4971                       fragP->tc_frag_data.use_absolute_literals =
4972                         last_fragP->tc_frag_data.use_absolute_literals;
4973                     }
4974                 }
4975               if (fragP->tc_frag_data.is_assembly_state_set)
4976                 last_fragP = fragP;
4977             }
4978         }
4979     }
4980 }
4981
4982
4983 static void
4984 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
4985                                       asection *sec,
4986                                       void *unused ATTRIBUTE_UNUSED)
4987 {
4988   flagword flags = bfd_get_section_flags (abfd, sec);
4989   segment_info_type *seginfo = seg_info (sec);
4990   fragS *frag = seginfo->frchainP->frch_root;
4991
4992   if (flags & SEC_CODE)
4993     {
4994       xtensa_isa isa = xtensa_default_isa;
4995       xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4996       while (frag != NULL)
4997         {
4998           if (frag->tc_frag_data.is_branch_target)
4999             {
5000               int op_size;
5001               int frag_addr;
5002               xtensa_format fmt;
5003
5004               xtensa_insnbuf_from_chars (isa, insnbuf, frag->fr_literal, 0);
5005               fmt = xtensa_format_decode (isa, insnbuf);
5006               op_size = xtensa_format_length (isa, fmt);
5007               frag_addr = frag->fr_address % xtensa_fetch_width;
5008               if (frag_addr + op_size > (int) xtensa_fetch_width)
5009                 as_warn_where (frag->fr_file, frag->fr_line,
5010                                _("unaligned branch target: %d bytes at 0x%lx"),
5011                                op_size, frag->fr_address);
5012             }
5013           frag = frag->fr_next;
5014         }
5015       xtensa_insnbuf_free (isa, insnbuf);
5016     }
5017 }
5018
5019
5020 static void
5021 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
5022                              asection *sec,
5023                              void *unused ATTRIBUTE_UNUSED)
5024 {
5025   flagword flags = bfd_get_section_flags (abfd, sec);
5026   segment_info_type *seginfo = seg_info (sec);
5027   fragS *frag = seginfo->frchainP->frch_root;
5028   xtensa_isa isa = xtensa_default_isa;
5029
5030   if (flags & SEC_CODE)
5031     {
5032       xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5033       while (frag != NULL)
5034         {
5035           if (frag->tc_frag_data.is_first_loop_insn)
5036             {
5037               int op_size;
5038               int frag_addr;
5039               xtensa_format fmt;
5040
5041               xtensa_insnbuf_from_chars (isa, insnbuf, frag->fr_literal, 0);
5042               fmt = xtensa_format_decode (isa, insnbuf);
5043               op_size = xtensa_format_length (isa, fmt);
5044               frag_addr = frag->fr_address % xtensa_fetch_width;
5045
5046               if (frag_addr + op_size > (signed) xtensa_fetch_width)
5047                 as_warn_where (frag->fr_file, frag->fr_line,
5048                                _("unaligned loop: %d bytes at 0x%lx"),
5049                                op_size, frag->fr_address);
5050             }
5051           frag = frag->fr_next;
5052         }
5053       xtensa_insnbuf_free (isa, insnbuf);
5054     }
5055 }
5056
5057
5058 static void
5059 xg_apply_tentative_value (fixS *fixP, valueT val)
5060 {
5061   xtensa_isa isa = xtensa_default_isa;
5062   static xtensa_insnbuf insnbuf = NULL;
5063   static xtensa_insnbuf slotbuf = NULL;
5064   xtensa_format fmt;
5065   int slot;
5066   bfd_boolean alt_reloc;
5067   xtensa_opcode opcode;
5068   char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5069
5070   (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc);
5071   if (alt_reloc)
5072     as_fatal (_("unexpected fix"));
5073
5074   if (!insnbuf)
5075     {
5076       insnbuf = xtensa_insnbuf_alloc (isa);
5077       slotbuf = xtensa_insnbuf_alloc (isa);
5078     }
5079
5080   xtensa_insnbuf_from_chars (isa, insnbuf, fixpos, 0);
5081   fmt = xtensa_format_decode (isa, insnbuf);
5082   if (fmt == XTENSA_UNDEFINED)
5083     as_fatal (_("undecodable fix"));
5084   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5085   opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5086   if (opcode == XTENSA_UNDEFINED)
5087     as_fatal (_("undecodable fix"));
5088
5089   /* CONST16 immediates are not PC-relative, despite the fact that we
5090      reuse the normal PC-relative operand relocations for the low part
5091      of a CONST16 operand.  The code in tc_gen_reloc does not decode
5092      the opcodes so it is more convenient to detect this special case
5093      here.  */
5094   if (opcode == xtensa_const16_opcode)
5095     return;
5096
5097   xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
5098                               get_relaxable_immed (opcode), val,
5099                               fixP->fx_file, fixP->fx_line);
5100
5101   xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
5102   xtensa_insnbuf_to_chars (isa, insnbuf, fixpos, 0);
5103 }
5104
5105 \f
5106 /* External Functions and Other GAS Hooks.  */
5107
5108 const char *
5109 xtensa_target_format (void)
5110 {
5111   return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
5112 }
5113
5114
5115 void
5116 xtensa_file_arch_init (bfd *abfd)
5117 {
5118   bfd_set_private_flags (abfd, 0x100 | 0x200);
5119 }
5120
5121
5122 void
5123 md_number_to_chars (char *buf, valueT val, int n)
5124 {
5125   if (target_big_endian)
5126     number_to_chars_bigendian (buf, val, n);
5127   else
5128     number_to_chars_littleendian (buf, val, n);
5129 }
5130
5131
5132 /* This function is called once, at assembler startup time.  It should
5133    set up all the tables, etc. that the MD part of the assembler will
5134    need.  */
5135
5136 void
5137 md_begin (void)
5138 {
5139   segT current_section = now_seg;
5140   int current_subsec = now_subseg;
5141   xtensa_isa isa;
5142
5143   xtensa_default_isa = xtensa_isa_init (0, 0);
5144   isa = xtensa_default_isa;
5145
5146   linkrelax = 1;
5147
5148   /* Set up the .literal, .fini.literal and .init.literal sections.  */
5149   memset (&default_lit_sections, 0, sizeof (default_lit_sections));
5150   default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME;
5151   default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME;
5152   default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME;
5153   default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME;
5154
5155   subseg_set (current_section, current_subsec);
5156
5157   xg_init_vinsn (&cur_vinsn);
5158
5159   xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5160   xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5161   xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5162   xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5163   xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5164   xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5165   xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5166   xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5167   xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5168   xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
5169   xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
5170   xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
5171   xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5172   xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
5173   xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
5174   xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
5175   xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
5176   xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5177   xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5178   xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
5179   xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
5180   xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5181   xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5182   xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5183   xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5184   xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5185   xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
5186   xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
5187   xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
5188
5189   init_op_placement_info_table ();
5190
5191   /* Set up the assembly state.  */
5192   if (!frag_now->tc_frag_data.is_assembly_state_set)
5193     xtensa_set_frag_assembly_state (frag_now);
5194 }
5195
5196
5197 /* TC_INIT_FIX_DATA hook */
5198
5199 void
5200 xtensa_init_fix_data (fixS *x)
5201 {
5202   x->tc_fix_data.slot = 0;
5203   x->tc_fix_data.X_add_symbol = NULL;
5204   x->tc_fix_data.X_add_number = 0;
5205 }
5206
5207
5208 /* tc_frob_label hook */
5209
5210 void
5211 xtensa_frob_label (symbolS *sym)
5212 {
5213   /* Since the label was already attached to a frag associated with the
5214      previous basic block, it now needs to be reset to the current frag.  */
5215   symbol_set_frag (sym, frag_now);
5216   S_SET_VALUE (sym, (valueT) frag_now_fix ());
5217
5218   if (generating_literals)
5219     xtensa_add_literal_sym (sym);
5220   else
5221     xtensa_add_insn_label (sym);
5222
5223   if (symbol_get_tc (sym)->is_loop_target
5224       && (get_last_insn_flags (now_seg, now_subseg)
5225           & FLAG_IS_BAD_LOOPEND) != 0)
5226     as_bad (_("invalid last instruction for a zero-overhead loop"));
5227
5228   /* No target aligning in the absolute section.  */
5229   if (now_seg != absolute_section
5230       && do_align_targets ()
5231       && !is_unaligned_label (sym)
5232       && !generating_literals)
5233     {
5234       float freq = get_subseg_info (now_seg, now_subseg)->cur_target_freq;
5235       xtensa_set_frag_assembly_state (frag_now);
5236
5237       /* The only time this type of frag grows is when there is a
5238          negatable branch that needs to be relaxed as the last
5239          instruction in a zero-overhead loop.  Because alignment frags
5240          are so common, marking them all as possibly growing four
5241          bytes makes any worst-case analysis appear much worse than it
5242          is.  So, we make fr_var not actually reflect the amount of
5243          memory allocated at the end of this frag, but rather the
5244          amount of memory this frag might grow.  The "4, 0" below
5245          allocates four bytes at the end of the frag for room to grow
5246          if we need to relax a loop end with a NOP.  Frags prior to
5247          this one might grow to align this one, but the frag itself
5248          won't grow unless it meets the condition above.  */
5249
5250 #define RELAX_LOOP_END_BYTES 4
5251
5252       frag_var (rs_machine_dependent,
5253                 RELAX_LOOP_END_BYTES, (int) freq,
5254                 RELAX_DESIRE_ALIGN_IF_TARGET,
5255                 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5256       xtensa_set_frag_assembly_state (frag_now);
5257       xtensa_move_labels (frag_now, 0, TRUE);
5258     }
5259
5260   /* We need to mark the following properties even if we aren't aligning.  */
5261
5262   /* If the label is already known to be a branch target, i.e., a
5263      forward branch, mark the frag accordingly.  Backward branches
5264      are handled by xg_add_branch_and_loop_targets.  */
5265   if (symbol_get_tc (sym)->is_branch_target)
5266     symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5267
5268   /* Loops only go forward, so they can be identified here.  */
5269   if (symbol_get_tc (sym)->is_loop_target)
5270     symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
5271 }
5272
5273
5274 /* tc_unrecognized_line hook */
5275
5276 int
5277 xtensa_unrecognized_line (int ch)
5278 {
5279   switch (ch)
5280     {
5281     case '{' :
5282       if (cur_vinsn.inside_bundle == 0)
5283         {
5284           /* PR8110: Cannot emit line number info inside a FLIX bundle
5285              when using --gstabs.  Temporarily disable debug info.  */
5286           generate_lineno_debug ();
5287           if (debug_type == DEBUG_STABS)
5288             {
5289               xt_saved_debug_type = debug_type;
5290               debug_type = DEBUG_NONE;
5291             }
5292
5293           cur_vinsn.inside_bundle = 1;
5294         }
5295       else
5296         {
5297           as_bad (_("extra opening brace"));
5298           return 0;
5299         }
5300       break;
5301
5302     case '}' :
5303       if (cur_vinsn.inside_bundle)
5304         finish_vinsn (&cur_vinsn);
5305       else
5306         {
5307           as_bad (_("extra closing brace"));
5308           return 0;
5309         }
5310       break;
5311     default:
5312       as_bad (_("syntax error"));
5313       return 0;
5314     }
5315   return 1;
5316 }
5317
5318
5319 /* md_flush_pending_output hook */
5320
5321 void
5322 xtensa_flush_pending_output (void)
5323 {
5324   if (cur_vinsn.inside_bundle)
5325     as_bad (_("missing closing brace"));
5326
5327   /* If there is a non-zero instruction fragment, close it.  */
5328   if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5329     {
5330       frag_wane (frag_now);
5331       frag_new (0);
5332       xtensa_set_frag_assembly_state (frag_now);
5333     }
5334   frag_now->tc_frag_data.is_insn = FALSE;
5335
5336   xtensa_clear_insn_labels ();
5337 }
5338
5339
5340 /* We had an error while parsing an instruction.  The string might look
5341    like this: "insn arg1, arg2 }".  If so, we need to see the closing
5342    brace and reset some fields.  Otherwise, the vinsn never gets closed
5343    and the num_slots field will grow past the end of the array of slots,
5344    and bad things happen.  */
5345
5346 static void
5347 error_reset_cur_vinsn (void)
5348 {
5349   if (cur_vinsn.inside_bundle)
5350     {
5351       if (*input_line_pointer == '}'
5352           || *(input_line_pointer - 1) == '}'
5353           || *(input_line_pointer - 2) == '}')
5354         xg_clear_vinsn (&cur_vinsn);
5355     }
5356 }
5357
5358
5359 void
5360 md_assemble (char *str)
5361 {
5362   xtensa_isa isa = xtensa_default_isa;
5363   char *opname;
5364   unsigned opnamelen;
5365   bfd_boolean has_underbar = FALSE;
5366   char *arg_strings[MAX_INSN_ARGS];
5367   int num_args;
5368   TInsn orig_insn;              /* Original instruction from the input.  */
5369
5370   tinsn_init (&orig_insn);
5371
5372   /* Split off the opcode.  */
5373   opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5374   opname = xmalloc (opnamelen + 1);
5375   memcpy (opname, str, opnamelen);
5376   opname[opnamelen] = '\0';
5377
5378   num_args = tokenize_arguments (arg_strings, str + opnamelen);
5379   if (num_args == -1)
5380     {
5381       as_bad (_("syntax error"));
5382       return;
5383     }
5384
5385   if (xg_translate_idioms (&opname, &num_args, arg_strings))
5386     return;
5387
5388   /* Check for an underbar prefix.  */
5389   if (*opname == '_')
5390     {
5391       has_underbar = TRUE;
5392       opname += 1;
5393     }
5394
5395   orig_insn.insn_type = ITYPE_INSN;
5396   orig_insn.ntok = 0;
5397   orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
5398
5399   orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5400   if (orig_insn.opcode == XTENSA_UNDEFINED)
5401     {
5402       xtensa_format fmt = xtensa_format_lookup (isa, opname);
5403       if (fmt == XTENSA_UNDEFINED)
5404         {
5405           as_bad (_("unknown opcode or format name '%s'"), opname);
5406           error_reset_cur_vinsn ();
5407           return;
5408         }
5409       if (!cur_vinsn.inside_bundle)
5410         {
5411           as_bad (_("format names only valid inside bundles"));
5412           error_reset_cur_vinsn ();
5413           return;
5414         }
5415       if (cur_vinsn.format != XTENSA_UNDEFINED)
5416         as_warn (_("multiple formats specified for one bundle; using '%s'"),
5417                  opname);
5418       cur_vinsn.format = fmt;
5419       free (has_underbar ? opname - 1 : opname);
5420       error_reset_cur_vinsn ();
5421       return;
5422     }
5423
5424   /* Special case: The call instructions should be marked "specific opcode"
5425      to keep them from expanding.  */
5426   if (!use_longcalls () && is_direct_call_opcode (orig_insn.opcode))
5427     orig_insn.is_specific_opcode = TRUE;
5428
5429   /* Parse the arguments.  */
5430   if (parse_arguments (&orig_insn, num_args, arg_strings))
5431     {
5432       as_bad (_("syntax error"));
5433       error_reset_cur_vinsn ();
5434       return;
5435     }
5436
5437   /* Free the opcode and argument strings, now that they've been parsed.  */
5438   free (has_underbar ? opname - 1 : opname);
5439   opname = 0;
5440   while (num_args-- > 0)
5441     free (arg_strings[num_args]);
5442
5443   /* Get expressions for invisible operands.  */
5444   if (get_invisible_operands (&orig_insn))
5445     {
5446       error_reset_cur_vinsn ();
5447       return;
5448     }
5449
5450   /* Check for the right number and type of arguments.  */
5451   if (tinsn_check_arguments (&orig_insn))
5452     {
5453       error_reset_cur_vinsn ();
5454       return;
5455     }
5456
5457   dwarf2_where (&orig_insn.loc);
5458
5459   xg_add_branch_and_loop_targets (&orig_insn);
5460
5461   /* Special-case for "entry" instruction.  */
5462   if (is_entry_opcode (orig_insn.opcode))
5463     {
5464       /* Check that the third opcode (#2) is >= 16.  */
5465       if (orig_insn.ntok >= 3)
5466         {
5467           expressionS *exp = &orig_insn.tok[2];
5468           switch (exp->X_op)
5469             {
5470             case O_constant:
5471               if (exp->X_add_number < 16)
5472                 as_warn (_("entry instruction with stack decrement < 16"));
5473               break;
5474
5475             default:
5476               as_warn (_("entry instruction with non-constant decrement"));
5477             }
5478         }
5479     }
5480
5481   /* Finish it off:
5482      assemble_tokens (opcode, tok, ntok);
5483      expand the tokens from the orig_insn into the
5484      stack of instructions that will not expand
5485      unless required at relaxation time.  */
5486
5487   if (!cur_vinsn.inside_bundle)
5488     emit_single_op (&orig_insn);
5489   else /* We are inside a bundle.  */
5490     {
5491       cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5492       cur_vinsn.num_slots++;
5493       if (*input_line_pointer == '}'
5494           || *(input_line_pointer - 1) == '}'
5495           || *(input_line_pointer - 2) == '}')
5496         finish_vinsn (&cur_vinsn);
5497     }
5498
5499   /* We've just emitted a new instruction so clear the list of labels.  */
5500   xtensa_clear_insn_labels ();
5501 }
5502
5503
5504 /* HANDLE_ALIGN hook */
5505
5506 /* For a .align directive, we mark the previous block with the alignment
5507    information.  This will be placed in the object file in the
5508    property section corresponding to this section.  */
5509
5510 void
5511 xtensa_handle_align (fragS *fragP)
5512 {
5513   if (linkrelax
5514       && !get_frag_is_literal (fragP)
5515       && (fragP->fr_type == rs_align
5516           || fragP->fr_type == rs_align_code)
5517       && fragP->fr_address + fragP->fr_fix > 0
5518       && fragP->fr_offset > 0
5519       && now_seg != bss_section)
5520     {
5521       fragP->tc_frag_data.is_align = TRUE;
5522       fragP->tc_frag_data.alignment = fragP->fr_offset;
5523     }
5524
5525   if (fragP->fr_type == rs_align_test)
5526     {
5527       int count;
5528       count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5529       if (count != 0)
5530         as_bad_where (fragP->fr_file, fragP->fr_line,
5531                       _("unaligned entry instruction"));
5532     }
5533 }
5534
5535
5536 /* TC_FRAG_INIT hook */
5537
5538 void
5539 xtensa_frag_init (fragS *frag)
5540 {
5541   xtensa_set_frag_assembly_state (frag);
5542 }
5543
5544
5545 symbolS *
5546 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5547 {
5548   return NULL;
5549 }
5550
5551
5552 /* Round up a section size to the appropriate boundary.  */
5553
5554 valueT
5555 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5556 {
5557   return size;                  /* Byte alignment is fine.  */
5558 }
5559
5560
5561 long
5562 md_pcrel_from (fixS *fixP)
5563 {
5564   char *insn_p;
5565   static xtensa_insnbuf insnbuf = NULL;
5566   static xtensa_insnbuf slotbuf = NULL;
5567   int opnum;
5568   uint32 opnd_value;
5569   xtensa_opcode opcode;
5570   xtensa_format fmt;
5571   int slot;
5572   xtensa_isa isa = xtensa_default_isa;
5573   valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
5574   bfd_boolean alt_reloc;
5575
5576   if (fixP->fx_done)
5577     return addr;
5578
5579   if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
5580     return addr;
5581
5582   if (!insnbuf)
5583     {
5584       insnbuf = xtensa_insnbuf_alloc (isa);
5585       slotbuf = xtensa_insnbuf_alloc (isa);
5586     }
5587
5588   insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
5589   xtensa_insnbuf_from_chars (isa, insnbuf, insn_p, 0);
5590   fmt = xtensa_format_decode (isa, insnbuf);
5591
5592   if (fmt == XTENSA_UNDEFINED)
5593     as_fatal (_("bad instruction format"));
5594
5595   if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5596     as_fatal (_("invalid relocation"));
5597
5598   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5599   opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5600
5601   /* Check for "alternate" relocation (operand not specified).  */
5602   if (alt_reloc || opcode == xtensa_const16_opcode)
5603     {
5604       if (opcode != xtensa_l32r_opcode
5605           && opcode != xtensa_const16_opcode)
5606         as_fatal (_("invalid relocation for '%s' instruction"),
5607                   xtensa_opcode_name (isa, opcode));
5608       return addr;
5609     }
5610
5611   opnum = get_relaxable_immed (opcode);
5612   opnd_value = 0;
5613   if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5614       || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
5615     {
5616       as_bad_where (fixP->fx_file,
5617                     fixP->fx_line,
5618                     _("invalid relocation for operand %d of '%s'"),
5619                     opnum, xtensa_opcode_name (isa, opcode));
5620       return addr;
5621     }
5622   return 0 - opnd_value;
5623 }
5624
5625
5626 /* TC_FORCE_RELOCATION hook */
5627
5628 int
5629 xtensa_force_relocation (fixS *fix)
5630 {
5631   switch (fix->fx_r_type)
5632    {
5633     case BFD_RELOC_XTENSA_SLOT0_ALT:
5634     case BFD_RELOC_XTENSA_SLOT1_ALT:
5635     case BFD_RELOC_XTENSA_SLOT2_ALT:
5636     case BFD_RELOC_XTENSA_SLOT3_ALT:
5637     case BFD_RELOC_XTENSA_SLOT4_ALT:
5638     case BFD_RELOC_XTENSA_SLOT5_ALT:
5639     case BFD_RELOC_XTENSA_SLOT6_ALT:
5640     case BFD_RELOC_XTENSA_SLOT7_ALT:
5641     case BFD_RELOC_XTENSA_SLOT8_ALT:
5642     case BFD_RELOC_XTENSA_SLOT9_ALT:
5643     case BFD_RELOC_XTENSA_SLOT10_ALT:
5644     case BFD_RELOC_XTENSA_SLOT11_ALT:
5645     case BFD_RELOC_XTENSA_SLOT12_ALT:
5646     case BFD_RELOC_XTENSA_SLOT13_ALT:
5647     case BFD_RELOC_XTENSA_SLOT14_ALT:
5648     case BFD_RELOC_VTABLE_INHERIT:
5649     case BFD_RELOC_VTABLE_ENTRY:
5650       return 1;
5651     default:
5652       break;
5653     }
5654
5655   if (linkrelax && fix->fx_addsy
5656       && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5657     return 1;
5658
5659   return generic_force_reloc (fix);
5660 }
5661
5662
5663 /* NO_PSEUDO_DOT hook */
5664
5665 /* This function has nothing to do with pseudo dots, but this is the
5666    nearest macro to where the check needs to take place.  FIXME: This
5667    seems wrong.  */
5668
5669 bfd_boolean
5670 xtensa_check_inside_bundle (void)
5671 {
5672   if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5673     as_bad (_("directives are not valid inside bundles"));
5674
5675   /* This function must always return FALSE because it is called via a
5676      macro that has nothing to do with bundling.  */
5677   return FALSE;
5678 }
5679
5680
5681 /* md_elf_section_change_hook */
5682
5683 void
5684 xtensa_elf_section_change_hook (void)
5685 {
5686   /* Set up the assembly state.  */
5687   if (!frag_now->tc_frag_data.is_assembly_state_set)
5688     xtensa_set_frag_assembly_state (frag_now);
5689 }
5690
5691
5692 /* tc_fix_adjustable hook */
5693
5694 bfd_boolean
5695 xtensa_fix_adjustable (fixS *fixP)
5696 {
5697   /* An offset is not allowed in combination with the difference of two
5698      symbols, but that cannot be easily detected after a local symbol
5699      has been adjusted to a (section+offset) form.  Return 0 so that such
5700      an fix will not be adjusted.  */
5701   if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset
5702       && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy)))
5703     return 0;
5704
5705   /* We need the symbol name for the VTABLE entries.  */
5706   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5707       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5708     return 0;
5709
5710   if (fixP->fx_addsy
5711       && (S_IS_EXTERNAL (fixP->fx_addsy) || S_IS_WEAK (fixP->fx_addsy)))
5712     return 0;
5713
5714 #if 0
5715   /* We may someday want to enable this code to preserve relocations for
5716      non-PC-relative fixes, possibly under control of a PIC flag.  */
5717   return (fixP->fx_pcrel
5718           || (fixP->fx_subsy != NULL
5719               && (S_GET_SEGMENT (fixP->fx_subsy)
5720                   == S_GET_SEGMENT (fixP->fx_addsy)))
5721           || S_IS_LOCAL (fixP->fx_addsy));
5722 #else
5723   return 1;
5724 #endif
5725 }
5726
5727
5728 void
5729 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
5730 {
5731   if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
5732     {
5733       char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5734
5735       switch (fixP->fx_r_type)
5736         {
5737         case BFD_RELOC_XTENSA_ASM_EXPAND:
5738           fixP->fx_done = 1;
5739           break;
5740
5741         case BFD_RELOC_XTENSA_ASM_SIMPLIFY:
5742           as_bad (_("unhandled local relocation fix %s"),
5743                   bfd_get_reloc_code_name (fixP->fx_r_type));
5744           break;
5745
5746         case BFD_RELOC_32:
5747         case BFD_RELOC_16:
5748         case BFD_RELOC_8:
5749           /* The only one we support that isn't an instruction field.  */
5750           md_number_to_chars (fixpos, *valP, fixP->fx_size);
5751           fixP->fx_done = 1;
5752           break;
5753
5754         case BFD_RELOC_VTABLE_INHERIT:
5755         case BFD_RELOC_VTABLE_ENTRY:
5756           fixP->fx_done = 0;
5757           break;
5758
5759         default:
5760           as_bad (_("unhandled local relocation fix %s"),
5761                   bfd_get_reloc_code_name (fixP->fx_r_type));
5762         }
5763     }
5764 }
5765
5766
5767 char *
5768 md_atof (int type, char *litP, int *sizeP)
5769 {
5770   int prec;
5771   LITTLENUM_TYPE words[4];
5772   char *t;
5773   int i;
5774
5775   switch (type)
5776     {
5777     case 'f':
5778       prec = 2;
5779       break;
5780
5781     case 'd':
5782       prec = 4;
5783       break;
5784
5785     default:
5786       *sizeP = 0;
5787       return "bad call to md_atof";
5788     }
5789
5790   t = atof_ieee (input_line_pointer, type, words);
5791   if (t)
5792     input_line_pointer = t;
5793
5794   *sizeP = prec * 2;
5795
5796   for (i = prec - 1; i >= 0; i--)
5797     {
5798       int idx = i;
5799       if (target_big_endian)
5800         idx = (prec - 1 - i);
5801
5802       md_number_to_chars (litP, (valueT) words[idx], 2);
5803       litP += 2;
5804     }
5805
5806   return NULL;
5807 }
5808
5809
5810 int
5811 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
5812 {
5813   return fragP->tc_frag_data.text_expansion[0];
5814 }
5815
5816
5817 /* Translate internal representation of relocation info to BFD target
5818    format.  */
5819
5820 arelent *
5821 tc_gen_reloc (asection *section, fixS *fixp)
5822 {
5823   arelent *reloc;
5824   bfd_boolean apply_tentative_value = FALSE;
5825
5826   reloc = (arelent *) xmalloc (sizeof (arelent));
5827   reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5828   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5829   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5830
5831   /* Make sure none of our internal relocations make it this far.
5832      They'd better have been fully resolved by this point.  */
5833   assert ((int) fixp->fx_r_type > 0);
5834
5835   if (linkrelax && fixp->fx_subsy
5836       && (fixp->fx_r_type == BFD_RELOC_8
5837           || fixp->fx_r_type == BFD_RELOC_16
5838           || fixp->fx_r_type == BFD_RELOC_32))
5839     {
5840       int diff_size = 0;
5841       bfd_vma diff_value, diff_mask = 0;
5842
5843       switch (fixp->fx_r_type)
5844         {
5845         case BFD_RELOC_8:
5846           fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
5847           diff_size = 1;
5848           diff_mask = 0xff;
5849           break;
5850         case BFD_RELOC_16:
5851           fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
5852           diff_size = 2;
5853           diff_mask = 0xffff;
5854           break;
5855         case BFD_RELOC_32:
5856           fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
5857           diff_size = 4;
5858           diff_mask = 0xffffffff;
5859           break;
5860         default:
5861           break;
5862         }
5863
5864       /* An offset is only allowed when it results from adjusting a local
5865          symbol into a section-relative offset.  If the offset came from the
5866          original expression, tc_fix_adjustable will have prevented the fix
5867          from being converted to a section-relative form so that we can flag
5868          the error here.  */
5869       if (fixp->fx_offset != 0 && !symbol_section_p (fixp->fx_addsy))
5870         {
5871           as_bad_where (fixp->fx_file, fixp->fx_line,
5872                         _("cannot represent subtraction with an offset"));
5873           free (reloc->sym_ptr_ptr);
5874           free (reloc);
5875           return NULL;
5876         }
5877
5878       assert (S_GET_SEGMENT (fixp->fx_addsy)
5879               == S_GET_SEGMENT (fixp->fx_subsy));
5880
5881       diff_value = (S_GET_VALUE (fixp->fx_addsy) + fixp->fx_offset
5882                     - S_GET_VALUE (fixp->fx_subsy));
5883
5884       /* Check for overflow.  */
5885       if ((diff_value & ~diff_mask) != 0)
5886         {
5887           as_bad_where (fixp->fx_file, fixp->fx_line,
5888                         _("value of %ld too large"), diff_value);
5889           free (reloc->sym_ptr_ptr);
5890           free (reloc);
5891           return NULL;
5892         }
5893
5894       md_number_to_chars (fixp->fx_frag->fr_literal + fixp->fx_where,
5895                           diff_value, diff_size);
5896       reloc->addend = fixp->fx_offset - diff_value;
5897     }
5898   else
5899     {
5900       reloc->addend = fixp->fx_offset;
5901
5902       switch (fixp->fx_r_type)
5903         {
5904         case BFD_RELOC_XTENSA_SLOT0_OP:
5905         case BFD_RELOC_XTENSA_SLOT1_OP:
5906         case BFD_RELOC_XTENSA_SLOT2_OP:
5907         case BFD_RELOC_XTENSA_SLOT3_OP:
5908         case BFD_RELOC_XTENSA_SLOT4_OP:
5909         case BFD_RELOC_XTENSA_SLOT5_OP:
5910         case BFD_RELOC_XTENSA_SLOT6_OP:
5911         case BFD_RELOC_XTENSA_SLOT7_OP:
5912         case BFD_RELOC_XTENSA_SLOT8_OP:
5913         case BFD_RELOC_XTENSA_SLOT9_OP:
5914         case BFD_RELOC_XTENSA_SLOT10_OP:
5915         case BFD_RELOC_XTENSA_SLOT11_OP:
5916         case BFD_RELOC_XTENSA_SLOT12_OP:
5917         case BFD_RELOC_XTENSA_SLOT13_OP:
5918         case BFD_RELOC_XTENSA_SLOT14_OP:
5919           /* As a special case, the immediate value for a CONST16 opcode
5920              should not be applied, since this kind of relocation is
5921              handled specially for CONST16 and is not really PC-relative.
5922              Rather than decode the opcode here, just wait and handle it
5923              in xg_apply_tentative_value.  */
5924           apply_tentative_value = TRUE;
5925           break;
5926
5927         case BFD_RELOC_XTENSA_SLOT0_ALT:
5928         case BFD_RELOC_XTENSA_SLOT1_ALT:
5929         case BFD_RELOC_XTENSA_SLOT2_ALT:
5930         case BFD_RELOC_XTENSA_SLOT3_ALT:
5931         case BFD_RELOC_XTENSA_SLOT4_ALT:
5932         case BFD_RELOC_XTENSA_SLOT5_ALT:
5933         case BFD_RELOC_XTENSA_SLOT6_ALT:
5934         case BFD_RELOC_XTENSA_SLOT7_ALT:
5935         case BFD_RELOC_XTENSA_SLOT8_ALT:
5936         case BFD_RELOC_XTENSA_SLOT9_ALT:
5937         case BFD_RELOC_XTENSA_SLOT10_ALT:
5938         case BFD_RELOC_XTENSA_SLOT11_ALT:
5939         case BFD_RELOC_XTENSA_SLOT12_ALT:
5940         case BFD_RELOC_XTENSA_SLOT13_ALT:
5941         case BFD_RELOC_XTENSA_SLOT14_ALT:
5942         case BFD_RELOC_XTENSA_ASM_EXPAND:
5943         case BFD_RELOC_32:
5944         case BFD_RELOC_XTENSA_PLT:
5945         case BFD_RELOC_VTABLE_INHERIT:
5946         case BFD_RELOC_VTABLE_ENTRY:
5947           break;
5948
5949         case BFD_RELOC_XTENSA_ASM_SIMPLIFY:
5950           as_warn (_("emitting simplification relocation"));
5951           break;
5952
5953         default:
5954           as_warn (_("emitting unknown relocation"));
5955         }
5956     }
5957
5958   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
5959   if (reloc->howto == NULL)
5960     {
5961       as_bad_where (fixp->fx_file, fixp->fx_line,
5962                     _("cannot represent `%s' relocation in object file"),
5963                     bfd_get_reloc_code_name (fixp->fx_r_type));
5964       free (reloc->sym_ptr_ptr);
5965       free (reloc);
5966       return NULL;
5967     }
5968
5969   if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
5970     as_fatal (_("internal error? cannot generate `%s' relocation"),
5971               bfd_get_reloc_code_name (fixp->fx_r_type));
5972
5973   /* Write the tentative value of a PC-relative relocation to a local symbol
5974      into the instruction.  The value will be ignored by the linker, and it
5975      makes the object file disassembly readable when the linkrelax flag is
5976      set and all branch targets are encoded in relocations.  */
5977
5978   if (linkrelax && apply_tentative_value && fixp->fx_pcrel)
5979     {
5980       valueT val;
5981       assert (fixp->fx_addsy);
5982       if (S_GET_SEGMENT (fixp->fx_addsy) == section && !fixp->fx_plt
5983           && !S_FORCE_RELOC (fixp->fx_addsy, 1))
5984         {
5985           val = (S_GET_VALUE (fixp->fx_addsy) + fixp->fx_offset
5986                  - md_pcrel_from (fixp));
5987           xg_apply_tentative_value (fixp, val);
5988         }
5989     }
5990
5991   return reloc;
5992 }
5993
5994 \f
5995 /* Checks for resource conflicts between instructions.  */
5996
5997 /* The func unit stuff could be implemented as bit-vectors rather
5998    than the iterative approach here.  If it ends up being too
5999    slow, we will switch it.  */
6000
6001 resource_table *
6002 new_resource_table (void *data,
6003                     int cycles,
6004                     int nu,
6005                     unit_num_copies_func uncf,
6006                     opcode_num_units_func onuf,
6007                     opcode_funcUnit_use_unit_func ouuf,
6008                     opcode_funcUnit_use_stage_func ousf)
6009 {
6010   int i;
6011   resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table));
6012   rt->data = data;
6013   rt->cycles = cycles;
6014   rt->allocated_cycles = cycles;
6015   rt->num_units = nu;
6016   rt->unit_num_copies = uncf;
6017   rt->opcode_num_units = onuf;
6018   rt->opcode_unit_use = ouuf;
6019   rt->opcode_unit_stage = ousf;
6020
6021   rt->units = (char **) xcalloc (cycles, sizeof (char *));
6022   for (i = 0; i < cycles; i++)
6023     rt->units[i] = (char *) xcalloc (nu, sizeof (char));
6024
6025   return rt;
6026 }
6027
6028
6029 void
6030 clear_resource_table (resource_table *rt)
6031 {
6032   int i, j;
6033   for (i = 0; i < rt->allocated_cycles; i++)
6034     for (j = 0; j < rt->num_units; j++)
6035       rt->units[i][j] = 0;
6036 }
6037
6038
6039 /* We never shrink it, just fake it into thinking so.  */
6040
6041 void
6042 resize_resource_table (resource_table *rt, int cycles)
6043 {
6044   int i, old_cycles;
6045
6046   rt->cycles = cycles;
6047   if (cycles <= rt->allocated_cycles)
6048     return;
6049
6050   old_cycles = rt->allocated_cycles;
6051   rt->allocated_cycles = cycles;
6052
6053   rt->units = xrealloc (rt->units, sizeof (char *) * rt->allocated_cycles);
6054   for (i = 0; i < old_cycles; i++)
6055     rt->units[i] = xrealloc (rt->units[i], sizeof (char) * rt->num_units);
6056   for (i = old_cycles; i < cycles; i++)
6057     rt->units[i] = xcalloc (rt->num_units, sizeof (char));
6058 }
6059
6060
6061 bfd_boolean
6062 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
6063 {
6064   int i;
6065   int uses = (rt->opcode_num_units) (rt->data, opcode);
6066
6067   for (i = 0; i < uses; i++)
6068     {
6069       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6070       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6071       int copies_in_use = rt->units[stage + cycle][unit];
6072       int copies = (rt->unit_num_copies) (rt->data, unit);
6073       if (copies_in_use >= copies)
6074         return FALSE;
6075     }
6076   return TRUE;
6077 }
6078
6079
6080 void
6081 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6082 {
6083   int i;
6084   int uses = (rt->opcode_num_units) (rt->data, opcode);
6085
6086   for (i = 0; i < uses; i++)
6087     {
6088       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6089       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6090       /* Note that this allows resources to be oversubscribed.  That's
6091          essential to the way the optional scheduler works.
6092          resources_available reports when a resource is over-subscribed,
6093          so it's easy to tell.  */
6094       rt->units[stage + cycle][unit]++;
6095     }
6096 }
6097
6098
6099 void
6100 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6101 {
6102   int i;
6103   int uses = (rt->opcode_num_units) (rt->data, opcode);
6104
6105   for (i = 0; i < uses; i++)
6106     {
6107       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6108       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6109       rt->units[stage + cycle][unit]--;
6110       assert (rt->units[stage + cycle][unit] >= 0);
6111     }
6112 }
6113
6114
6115 /* Wrapper functions make parameterized resource reservation
6116    more convenient.  */
6117
6118 int
6119 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
6120 {
6121   xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6122   return use->unit;
6123 }
6124
6125
6126 int
6127 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
6128 {
6129   xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6130   return use->stage;
6131 }
6132
6133
6134 /* Note that this function does not check issue constraints, but
6135    solely whether the hardware is available to execute the given
6136    instructions together.  It also doesn't check if the tinsns
6137    write the same state, or access the same tieports.  That is
6138    checked by check_t1_t2_read_write.  */
6139
6140 static bfd_boolean
6141 resources_conflict (vliw_insn *vinsn)
6142 {
6143   int i;
6144   static resource_table *rt = NULL;
6145
6146   /* This is the most common case by far.  Optimize it.  */
6147   if (vinsn->num_slots == 1)
6148     return FALSE;
6149
6150   if (rt == NULL)
6151     {
6152       xtensa_isa isa = xtensa_default_isa;
6153       rt = new_resource_table
6154         (isa, xtensa_isa_num_pipe_stages (isa),
6155          xtensa_isa_num_funcUnits (isa),
6156          (unit_num_copies_func) xtensa_funcUnit_num_copies,
6157          (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
6158          opcode_funcUnit_use_unit,
6159          opcode_funcUnit_use_stage);
6160     }
6161
6162   clear_resource_table (rt);
6163
6164   for (i = 0; i < vinsn->num_slots; i++)
6165     {
6166       if (!resources_available (rt, vinsn->slots[i].opcode, 0))
6167         return TRUE;
6168       reserve_resources (rt, vinsn->slots[i].opcode, 0);
6169     }
6170
6171   return FALSE;
6172 }
6173
6174 \f
6175 /* finish_vinsn, emit_single_op and helper functions.  */
6176
6177 static bfd_boolean find_vinsn_conflicts (vliw_insn *);
6178 static xtensa_format xg_find_narrowest_format (vliw_insn *);
6179 static void bundle_single_op (TInsn *);
6180 static void xg_assemble_vliw_tokens (vliw_insn *);
6181
6182
6183 /* We have reached the end of a bundle; emit into the frag.  */
6184
6185 static void
6186 finish_vinsn (vliw_insn *vinsn)
6187 {
6188   IStack slotstack;
6189   int i;
6190   char *file_name;
6191   int line;
6192
6193   if (find_vinsn_conflicts (vinsn))
6194     return;
6195
6196   /* First, find a format that works.  */
6197   if (vinsn->format == XTENSA_UNDEFINED)
6198     vinsn->format = xg_find_narrowest_format (vinsn);
6199
6200   if (vinsn->format == XTENSA_UNDEFINED)
6201     {
6202       as_where (&file_name, &line);
6203       as_bad_where (file_name, line,
6204                     _("couldn't find a valid instruction format"));
6205       fprintf (stderr, _("    ops were: "));
6206       for (i = 0; i < vinsn->num_slots; i++)
6207         fprintf (stderr, _(" %s;"),
6208                  xtensa_opcode_name (xtensa_default_isa,
6209                                      vinsn->slots[i].opcode));
6210       fprintf (stderr, _("\n"));
6211       xg_clear_vinsn (vinsn);
6212       return;
6213     }
6214
6215   if (vinsn->num_slots
6216       != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
6217     {
6218       as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6219               xtensa_format_name (xtensa_default_isa, vinsn->format),
6220               xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
6221               vinsn->num_slots);
6222       xg_clear_vinsn (vinsn);
6223       return;
6224     }
6225
6226   if (resources_conflict (vinsn))
6227     {
6228       as_where (&file_name, &line);
6229       as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6230       fprintf (stderr, "    ops were: ");
6231       for (i = 0; i < vinsn->num_slots; i++)
6232         fprintf (stderr, " %s;",
6233                  xtensa_opcode_name (xtensa_default_isa,
6234                                      vinsn->slots[i].opcode));
6235       fprintf (stderr, "\n");
6236       xg_clear_vinsn (vinsn);
6237       return;
6238     }
6239
6240   for (i = 0; i < vinsn->num_slots; i++)
6241     {
6242       if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
6243         {
6244           symbolS *lit_sym = NULL;
6245           int j;
6246           bfd_boolean e = FALSE;
6247           bfd_boolean saved_density = density_supported;
6248
6249           /* We don't want to narrow ops inside multi-slot bundles.  */
6250           if (vinsn->num_slots > 1)
6251             density_supported = FALSE;
6252
6253           istack_init (&slotstack);
6254           if (vinsn->slots[i].opcode == xtensa_nop_opcode)
6255             {
6256               vinsn->slots[i].opcode =
6257                 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6258                                                vinsn->format, i);
6259               vinsn->slots[i].ntok = 0;
6260             }
6261
6262           if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6263             {
6264               e = TRUE;
6265               continue;
6266             }
6267
6268           density_supported = saved_density;
6269
6270           if (e)
6271             {
6272               xg_clear_vinsn (vinsn);
6273               return;
6274             }
6275
6276           for (j = 0; j < slotstack.ninsn - 1; j++)
6277             {
6278               TInsn *insn = &slotstack.insn[j];
6279               if (insn->insn_type == ITYPE_LITERAL)
6280                 {
6281                   assert (lit_sym == NULL);
6282                   lit_sym = xg_assemble_literal (insn);
6283                 }
6284               else
6285                 {
6286                   if (lit_sym)
6287                     xg_resolve_literals (insn, lit_sym);
6288                   emit_single_op (insn);
6289                 }
6290             }
6291
6292           if (vinsn->num_slots > 1)
6293             {
6294               if (opcode_fits_format_slot
6295                   (slotstack.insn[slotstack.ninsn - 1].opcode,
6296                    vinsn->format, i))
6297                 {
6298                   vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6299                 }
6300               else
6301                 {
6302                   bundle_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6303                   if (vinsn->format == XTENSA_UNDEFINED)
6304                     vinsn->slots[i].opcode = xtensa_nop_opcode;
6305                   else
6306                     vinsn->slots[i].opcode
6307                       = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6308                                                        vinsn->format, i);
6309
6310                   vinsn->slots[i].ntok = 0;
6311                 }
6312             }
6313           else
6314             {
6315               vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6316               vinsn->format = XTENSA_UNDEFINED;
6317             }
6318         }
6319     }
6320
6321   /* Now check resource conflicts on the modified bundle.  */
6322   if (resources_conflict (vinsn))
6323     {
6324       as_where (&file_name, &line);
6325       as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6326       fprintf (stderr, "    ops were: ");
6327       for (i = 0; i < vinsn->num_slots; i++)
6328         fprintf (stderr, " %s;",
6329                  xtensa_opcode_name (xtensa_default_isa,
6330                                      vinsn->slots[i].opcode));
6331       fprintf (stderr, "\n");
6332       xg_clear_vinsn (vinsn);
6333       return;
6334     }
6335
6336   /* First, find a format that works.  */
6337   if (vinsn->format == XTENSA_UNDEFINED)
6338       vinsn->format = xg_find_narrowest_format (vinsn);
6339
6340   xg_assemble_vliw_tokens (vinsn);
6341
6342   xg_clear_vinsn (vinsn);
6343 }
6344
6345
6346 /* Given an vliw instruction, what conflicts are there in register
6347    usage and in writes to states and queues?
6348
6349    This function does two things:
6350    1. Reports an error when a vinsn contains illegal combinations
6351       of writes to registers states or queues.
6352    2. Marks individual tinsns as not relaxable if the combination
6353       contains antidependencies.
6354
6355    Job 2 handles things like swap semantics in instructions that need
6356    to be relaxed.  For example,
6357
6358         addi a0, a1, 100000
6359
6360    normally would be relaxed to
6361
6362         l32r a0, some_label
6363         add a0, a1, a0
6364
6365    _but_, if the above instruction is bundled with an a0 reader, e.g.,
6366
6367         { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6368
6369    then we can't relax it into
6370
6371         l32r a0, some_label
6372         { add a0, a1, a0 ; add a2, a0, a4 ; }
6373
6374    because the value of a0 is trashed before the second add can read it.  */
6375
6376 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6377
6378 static bfd_boolean
6379 find_vinsn_conflicts (vliw_insn *vinsn)
6380 {
6381   int i, j;
6382   int branches = 0;
6383   xtensa_isa isa = xtensa_default_isa;
6384
6385   assert (!past_xtensa_end);
6386
6387   for (i = 0 ; i < vinsn->num_slots; i++)
6388     {
6389       TInsn *op1 = &vinsn->slots[i];
6390       if (op1->is_specific_opcode)
6391         op1->keep_wide = TRUE;
6392       else
6393         op1->keep_wide = FALSE;
6394     }
6395
6396   for (i = 0 ; i < vinsn->num_slots; i++)
6397     {
6398       TInsn *op1 = &vinsn->slots[i];
6399
6400       if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6401         branches++;
6402
6403       for (j = 0; j < vinsn->num_slots; j++)
6404         {
6405           if (i != j)
6406             {
6407               TInsn *op2 = &vinsn->slots[j];
6408               char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6409               switch (conflict_type)
6410                 {
6411                 case 'c':
6412                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6413                           xtensa_opcode_name (isa, op1->opcode), i,
6414                           xtensa_opcode_name (isa, op2->opcode), j);
6415                   return TRUE;
6416                 case 'd':
6417                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6418                           xtensa_opcode_name (isa, op1->opcode), i,
6419                           xtensa_opcode_name (isa, op2->opcode), j);
6420                   return TRUE;
6421                 case 'e':
6422                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6423                           xtensa_opcode_name (isa, op1->opcode), i,
6424                           xtensa_opcode_name (isa, op2->opcode), j);
6425                   return TRUE;
6426                 case 'f':
6427                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6428                           xtensa_opcode_name (isa, op1->opcode), i,
6429                           xtensa_opcode_name (isa, op2->opcode), j);
6430                   return TRUE;
6431                 default:
6432                   /* Everything is OK.  */
6433                   break;
6434                 }
6435               op2->is_specific_opcode = (op2->is_specific_opcode
6436                                          || conflict_type == 'a');
6437             }
6438         }
6439     }
6440
6441   if (branches > 1)
6442     {
6443       as_bad (_("multiple branches or jumps in the same bundle"));
6444       return TRUE;
6445     }
6446
6447   return FALSE;
6448 }
6449
6450
6451 /* Check how the result registers of t1 and t2 relate.
6452    Cases found are:
6453
6454    case A: t1 reads a register t2 writes (an antidependency within a bundle)
6455    case B: no relationship between what is read and written (both could
6456            read the same reg though)
6457    case C: t1 writes a register t2 writes (a register conflict within a
6458            bundle)
6459    case D: t1 writes a state that t2 also writes
6460    case E: t1 writes a tie queue that t2 also writes
6461    case F: two volatile queue writes
6462 */
6463
6464 static char
6465 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
6466 {
6467   xtensa_isa isa = xtensa_default_isa;
6468   xtensa_regfile t1_regfile, t2_regfile;
6469   int t1_reg, t2_reg;
6470   int t1_base_reg, t1_last_reg;
6471   int t2_base_reg, t2_last_reg;
6472   char t1_inout, t2_inout;
6473   int i, j;
6474   char conflict = 'b';
6475   int t1_states;
6476   int t2_states;
6477   int t1_interfaces;
6478   int t2_interfaces;
6479   bfd_boolean t1_volatile = FALSE;
6480   bfd_boolean t2_volatile = FALSE;
6481
6482   /* Check registers.  */
6483   for (j = 0; j < t2->ntok; j++)
6484     {
6485       if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6486         continue;
6487
6488       t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6489       t2_base_reg = t2->tok[j].X_add_number;
6490       t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6491
6492       for (i = 0; i < t1->ntok; i++)
6493         {
6494           if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6495             continue;
6496
6497           t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6498
6499           if (t1_regfile != t2_regfile)
6500             continue;
6501
6502           t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6503           t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6504
6505           if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6506               || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6507             {
6508               if (t1_inout == 'm' || t1_inout == 'o'
6509                   || t2_inout == 'm' || t2_inout == 'o')
6510                 {
6511                   conflict = 'a';
6512                   continue;
6513                 }
6514             }
6515
6516           t1_base_reg = t1->tok[i].X_add_number;
6517           t1_last_reg = (t1_base_reg
6518                          + xtensa_operand_num_regs (isa, t1->opcode, i));
6519
6520           for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6521             {
6522               for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6523                 {
6524                   if (t1_reg != t2_reg)
6525                     continue;
6526
6527                   if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6528                     {
6529                       conflict = 'a';
6530                       continue;
6531                     }
6532
6533                   if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6534                     {
6535                       conflict = 'a';
6536                       continue;
6537                     }
6538
6539                   if (t1_inout != 'i' && t2_inout != 'i')
6540                     return 'c';
6541                 }
6542             }
6543         }
6544     }
6545
6546   /* Check states.  */
6547   t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6548   t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6549   for (j = 0; j < t2_states; j++)
6550     {
6551       xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6552       t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6553       for (i = 0; i < t1_states; i++)
6554         {
6555           xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6556           t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
6557           if (t1_so != t2_so)
6558             continue;
6559
6560           if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6561             {
6562               conflict = 'a';
6563               continue;
6564             }
6565
6566           if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6567             {
6568               conflict = 'a';
6569               continue;
6570             }
6571
6572           if (t1_inout != 'i' && t2_inout != 'i')
6573             return 'd';
6574         }
6575     }
6576
6577   /* Check tieports.  */
6578   t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6579   t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
6580   for (j = 0; j < t2_interfaces; j++)
6581     {
6582       xtensa_interface t2_int
6583         = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
6584       t2_inout = xtensa_interface_inout (isa, j);
6585       if (xtensa_interface_has_side_effect (isa, t2_int) == 1
6586           && t2_inout != 'i')
6587         t2_volatile = TRUE;
6588       for (i = 0; i < t1_interfaces; i++)
6589         {
6590           xtensa_interface t1_int
6591             = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
6592           t1_inout = xtensa_interface_inout (isa, i);
6593           if (xtensa_interface_has_side_effect (isa, t1_int) == 1
6594               && t1_inout != 'i')
6595             t1_volatile = TRUE;
6596
6597           if (t1_int != t2_int)
6598             continue;
6599
6600           if (t2_inout == 'i' && t1_inout == 'o')
6601             {
6602               conflict = 'a';
6603               continue;
6604             }
6605
6606           if (t1_inout == 'i' && t2_inout == 'o')
6607             {
6608               conflict = 'a';
6609               continue;
6610             }
6611
6612           if (t1_inout != 'i' && t2_inout != 'i')
6613             return 'e';
6614         }
6615     }
6616
6617   if (t1_volatile && t2_volatile)
6618     return 'f';
6619
6620   return conflict;
6621 }
6622
6623
6624 static xtensa_format
6625 xg_find_narrowest_format (vliw_insn *vinsn)
6626 {
6627   /* Right now we assume that the ops within the vinsn are properly
6628      ordered for the slots that the programmer wanted them in.  In
6629      other words, we don't rearrange the ops in hopes of finding a
6630      better format.  The scheduler handles that.  */
6631
6632   xtensa_isa isa = xtensa_default_isa;
6633   xtensa_format format;
6634   vliw_insn v_copy = *vinsn;
6635   xtensa_opcode nop_opcode = xtensa_nop_opcode;
6636
6637   for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6638     {
6639       v_copy = *vinsn;
6640       if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6641         {
6642           int slot;
6643           int fit = 0;
6644           for (slot = 0; slot < v_copy.num_slots; slot++)
6645             {
6646               if (v_copy.slots[slot].opcode == nop_opcode)
6647                 {
6648                   v_copy.slots[slot].opcode =
6649                     xtensa_format_slot_nop_opcode (isa, format, slot);
6650                   v_copy.slots[slot].ntok = 0;
6651                 }
6652
6653               if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6654                                            format, slot))
6655                 fit++;
6656               else if (v_copy.num_slots > 1)
6657                 {
6658                   TInsn widened;
6659                   /* Try the widened version.  */
6660                   if (!v_copy.slots[slot].keep_wide
6661                       && !v_copy.slots[slot].is_specific_opcode
6662                       && xg_is_narrow_insn (&v_copy.slots[slot])
6663                       && !xg_expand_narrow (&widened, &v_copy.slots[slot])
6664                       && opcode_fits_format_slot (widened.opcode,
6665                                                   format, slot))
6666                     {
6667                       /* The xg_is_narrow clause requires some explanation:
6668
6669                          addi can be "widened" to an addmi, which is then
6670                          expanded to an addmi/addi pair if the immediate
6671                          requires it, but here we must have a single widen
6672                          only.
6673
6674                          xg_is_narrow tells us that addi isn't really
6675                          narrow.  The widen_spec_list says that there are
6676                          other cases.  */
6677
6678                       v_copy.slots[slot] = widened;
6679                       fit++;
6680                     }
6681                 }
6682             }
6683           if (fit == v_copy.num_slots)
6684             {
6685               *vinsn = v_copy;
6686               xtensa_format_encode (isa, format, vinsn->insnbuf);
6687               vinsn->format = format;
6688               break;
6689             }
6690         }
6691     }
6692
6693   if (format == xtensa_isa_num_formats (isa))
6694     return XTENSA_UNDEFINED;
6695
6696   return format;
6697 }
6698
6699
6700 /* Return the additional space needed in a frag
6701    for possible relaxations of any ops in a VLIW insn.
6702    Also fill out the relaxations that might be required of
6703    each tinsn in the vinsn.  */
6704
6705 static int
6706 relaxation_requirements (vliw_insn *vinsn)
6707 {
6708   int extra_space = 0;
6709   int slot;
6710
6711   for (slot = 0; slot < vinsn->num_slots; slot++)
6712     {
6713       TInsn *tinsn = &vinsn->slots[slot];
6714       if (!tinsn_has_symbolic_operands (tinsn))
6715         {
6716           /* A narrow instruction could be widened later to help
6717              alignment issues.  */
6718           if (xg_is_narrow_insn (tinsn)
6719               && !tinsn->is_specific_opcode
6720               && vinsn->num_slots == 1)
6721             {
6722               /* Difference in bytes between narrow and wide insns...  */
6723               extra_space += 1;
6724               tinsn->subtype = RELAX_NARROW;
6725               tinsn->record_fix = TRUE;
6726               break;
6727             }
6728           else
6729             {
6730               tinsn->record_fix = FALSE;
6731               /* No extra_space needed.  */
6732             }
6733         }
6734       else
6735         {
6736           if (workaround_b_j_loop_end && is_jx_opcode (tinsn->opcode)
6737               && use_transform ())
6738             {
6739               /* Add 2 of these.  */
6740               extra_space += 3; /* for the nop size */
6741               tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6742             }
6743
6744           /* Need to assemble it with space for the relocation.  */
6745           if (xg_is_relaxable_insn (tinsn, 0)
6746               && !tinsn->is_specific_opcode)
6747             {
6748               int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6749               int max_literal_size =
6750                 xg_get_max_insn_widen_literal_size (tinsn->opcode);
6751
6752               tinsn->literal_space = max_literal_size;
6753
6754               tinsn->subtype = RELAX_IMMED;
6755               tinsn->record_fix = FALSE;
6756               extra_space += max_size;
6757             }
6758           else
6759             {
6760               tinsn->record_fix = TRUE;
6761               /* No extra space needed.  */
6762             }
6763         }
6764     }
6765   return extra_space;
6766 }
6767
6768
6769 static void
6770 bundle_single_op (TInsn *orig_insn)
6771 {
6772   xtensa_isa isa = xtensa_default_isa;
6773   vliw_insn v;
6774   int slot;
6775
6776   xg_init_vinsn (&v);
6777   v.format = op_placement_table[orig_insn->opcode].narrowest;
6778   assert (v.format != XTENSA_UNDEFINED);
6779   v.num_slots = xtensa_format_num_slots (isa, v.format);
6780
6781   for (slot = 0;
6782        !opcode_fits_format_slot (orig_insn->opcode, v.format, slot);
6783        slot++)
6784     {
6785       v.slots[slot].opcode =
6786         xtensa_format_slot_nop_opcode (isa, v.format, slot);
6787       v.slots[slot].ntok = 0;
6788       v.slots[slot].insn_type = ITYPE_INSN;
6789     }
6790
6791   v.slots[slot] = *orig_insn;
6792   slot++;
6793
6794   for ( ; slot < v.num_slots; slot++)
6795     {
6796       v.slots[slot].opcode =
6797         xtensa_format_slot_nop_opcode (isa, v.format, slot);
6798       v.slots[slot].ntok = 0;
6799       v.slots[slot].insn_type = ITYPE_INSN;
6800     }
6801
6802   finish_vinsn (&v);
6803   xg_free_vinsn (&v);
6804 }
6805
6806
6807 static bfd_boolean
6808 emit_single_op (TInsn *orig_insn)
6809 {
6810   int i;
6811   IStack istack;                /* put instructions into here */
6812   symbolS *lit_sym = NULL;
6813   symbolS *label_sym = NULL;
6814
6815   istack_init (&istack);
6816
6817   /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6818      Because the scheduling and bundling characteristics of movi and
6819      l32r or const16 are so different, we can do much better if we relax
6820      it prior to scheduling and bundling, rather than after.  */
6821   if (is_movi_opcode (orig_insn->opcode) && !cur_vinsn.inside_bundle
6822       && (orig_insn->tok[1].X_op == O_symbol
6823           || orig_insn->tok[1].X_op == O_pltrel))
6824     xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
6825   else
6826     if (xg_expand_assembly_insn (&istack, orig_insn))
6827       return TRUE;
6828
6829   for (i = 0; i < istack.ninsn; i++)
6830     {
6831       TInsn *insn = &istack.insn[i];
6832       switch (insn->insn_type)
6833         {
6834         case ITYPE_LITERAL:
6835           assert (lit_sym == NULL);
6836           lit_sym = xg_assemble_literal (insn);
6837           break;
6838         case ITYPE_LABEL:
6839           {
6840             static int relaxed_sym_idx = 0;
6841             char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12);
6842             sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
6843             colon (label);
6844             assert (label_sym == NULL);
6845             label_sym = symbol_find_or_make (label);
6846             assert (label_sym);
6847             free (label);
6848           }
6849           break;
6850         case ITYPE_INSN:
6851           if (lit_sym)
6852             xg_resolve_literals (insn, lit_sym);
6853           if (label_sym)
6854             xg_resolve_labels (insn, label_sym);
6855           bundle_single_op (insn);
6856           break;
6857         default:
6858           assert (0);
6859           break;
6860         }
6861     }
6862   return FALSE;
6863 }
6864
6865
6866 /* Emit a vliw instruction to the current fragment.  */
6867
6868 static void
6869 xg_assemble_vliw_tokens (vliw_insn *vinsn)
6870 {
6871   bfd_boolean finish_frag = FALSE;
6872   bfd_boolean is_jump = FALSE;
6873   bfd_boolean is_branch = FALSE;
6874   xtensa_isa isa = xtensa_default_isa;
6875   int i;
6876   int insn_size;
6877   int extra_space;
6878   char *f = NULL;
6879   int slot;
6880   struct dwarf2_line_info best_loc;
6881
6882   best_loc.line = INT_MAX;
6883
6884   if (generating_literals)
6885     {
6886       static int reported = 0;
6887       if (reported < 4)
6888         as_bad_where (frag_now->fr_file, frag_now->fr_line,
6889                       _("cannot assemble into a literal fragment"));
6890       if (reported == 3)
6891         as_bad (_("..."));
6892       reported++;
6893       return;
6894     }
6895
6896   if (frag_now_fix () != 0
6897       && (!get_frag_is_insn (frag_now)
6898           || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
6899           || !use_transform () != get_frag_is_no_transform (frag_now)
6900           || (directive_state[directive_absolute_literals]
6901               != frag_now->tc_frag_data.use_absolute_literals)))
6902     {
6903       frag_wane (frag_now);
6904       frag_new (0);
6905       xtensa_set_frag_assembly_state (frag_now);
6906     }
6907
6908   if (workaround_a0_b_retw
6909       && vinsn->num_slots == 1
6910       && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
6911       && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
6912       && use_transform ())
6913     {
6914       has_a0_b_retw = TRUE;
6915
6916       /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6917          After the first assembly pass we will check all of them and
6918          add a nop if needed.  */
6919       frag_now->tc_frag_data.is_insn = TRUE;
6920       frag_var (rs_machine_dependent, 4, 4,
6921                 RELAX_ADD_NOP_IF_A0_B_RETW,
6922                 frag_now->fr_symbol,
6923                 frag_now->fr_offset,
6924                 NULL);
6925       xtensa_set_frag_assembly_state (frag_now);
6926       frag_now->tc_frag_data.is_insn = TRUE;
6927       frag_var (rs_machine_dependent, 4, 4,
6928                 RELAX_ADD_NOP_IF_A0_B_RETW,
6929                 frag_now->fr_symbol,
6930                 frag_now->fr_offset,
6931                 NULL);
6932       xtensa_set_frag_assembly_state (frag_now);
6933     }
6934
6935   for (i = 0; i < vinsn->num_slots; i++)
6936     {
6937       /* See if the instruction implies an aligned section.  */
6938       if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1)
6939         record_alignment (now_seg, 2);
6940
6941       /* Also determine the best line number for debug info.  */
6942       best_loc = vinsn->slots[i].loc.line < best_loc.line
6943         ? vinsn->slots[i].loc : best_loc;
6944     }
6945
6946   /* Special cases for instructions that force an alignment... */
6947   /* None of these opcodes are bundle-able.  */
6948   if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
6949     {
6950       size_t max_fill;
6951
6952       xtensa_set_frag_assembly_state (frag_now);
6953       frag_now->tc_frag_data.is_insn = TRUE;
6954
6955       max_fill = get_text_align_max_fill_size
6956         (get_text_align_power (xtensa_fetch_width),
6957          TRUE, frag_now->tc_frag_data.is_no_density);
6958
6959       if (use_transform ())
6960         frag_var (rs_machine_dependent, max_fill, max_fill,
6961                   RELAX_ALIGN_NEXT_OPCODE,
6962                   frag_now->fr_symbol,
6963                   frag_now->fr_offset,
6964                   NULL);
6965       else
6966         frag_var (rs_machine_dependent, 0, 0,
6967                   RELAX_CHECK_ALIGN_NEXT_OPCODE, 0, 0, NULL);
6968       xtensa_set_frag_assembly_state (frag_now);
6969
6970       xtensa_move_labels (frag_now, 0, FALSE);
6971     }
6972
6973   if (is_entry_opcode (vinsn->slots[0].opcode)
6974       && !vinsn->slots[0].is_specific_opcode)
6975     {
6976       xtensa_mark_literal_pool_location ();
6977       xtensa_move_labels (frag_now, 0, TRUE);
6978       frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
6979     }
6980
6981   if (vinsn->num_slots == 1)
6982     {
6983       if (workaround_a0_b_retw && use_transform ())
6984         set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
6985                              is_register_writer (&vinsn->slots[0], "a", 0));
6986
6987       set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
6988                            is_bad_loopend_opcode (&vinsn->slots[0]));
6989     }
6990   else
6991     set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
6992
6993   insn_size = xtensa_format_length (isa, vinsn->format);
6994
6995   extra_space = relaxation_requirements (vinsn);
6996
6997   /* vinsn_to_insnbuf will produce the error.  */
6998   if (vinsn->format != XTENSA_UNDEFINED)
6999     {
7000       f = (char *) frag_more (insn_size + extra_space);
7001       xtensa_set_frag_assembly_state (frag_now);
7002       frag_now->tc_frag_data.is_insn = TRUE;
7003     }
7004
7005   vinsn_to_insnbuf (vinsn, f, frag_now, TRUE);
7006   if (vinsn->format == XTENSA_UNDEFINED)
7007     return;
7008
7009   xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, f, 0);
7010
7011   xtensa_dwarf2_emit_insn (insn_size - extra_space, &best_loc);
7012
7013   for (slot = 0; slot < vinsn->num_slots; slot++)
7014     {
7015       TInsn *tinsn = &vinsn->slots[slot];
7016       frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
7017       frag_now->tc_frag_data.slot_symbols[slot] =  tinsn->symbol;
7018       frag_now->tc_frag_data.slot_sub_symbols[slot] =  tinsn->sub_symbol;
7019       frag_now->tc_frag_data.slot_offsets[slot] =  tinsn->offset;
7020       frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
7021       if (tinsn->literal_space != 0)
7022         xg_assemble_literal_space (tinsn->literal_space, slot);
7023
7024       if (tinsn->subtype == RELAX_NARROW)
7025         assert (vinsn->num_slots == 1);
7026       if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
7027         is_jump = TRUE;
7028       if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
7029         is_branch = TRUE;
7030
7031       if (tinsn->subtype || tinsn->symbol || tinsn->record_fix
7032           || tinsn->offset || tinsn->literal_frag || is_jump || is_branch)
7033         finish_frag = TRUE;
7034     }
7035
7036   if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7037     set_frag_is_specific_opcode (frag_now, TRUE);
7038
7039   if (finish_frag)
7040     {
7041       frag_variant (rs_machine_dependent,
7042                     extra_space, extra_space, RELAX_SLOTS,
7043                     frag_now->fr_symbol, frag_now->fr_offset, f);
7044       xtensa_set_frag_assembly_state (frag_now);
7045     }
7046
7047   /* Special cases for loops:
7048      close_loop_end should be inserted AFTER short_loop.
7049      Make sure that CLOSE loops are processed BEFORE short_loops
7050      when converting them.  */
7051
7052   /* "short_loop": Add a NOP if the loop is < 4 bytes.  */
7053   if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode)
7054       && !vinsn->slots[0].is_specific_opcode)
7055     {
7056       if (workaround_short_loop && use_transform ())
7057         {
7058           maybe_has_short_loop = TRUE;
7059           frag_now->tc_frag_data.is_insn = TRUE;
7060           frag_var (rs_machine_dependent, 4, 4,
7061                     RELAX_ADD_NOP_IF_SHORT_LOOP,
7062                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7063           frag_now->tc_frag_data.is_insn = TRUE;
7064           frag_var (rs_machine_dependent, 4, 4,
7065                     RELAX_ADD_NOP_IF_SHORT_LOOP,
7066                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7067         }
7068
7069       /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7070          loop at least 12 bytes away from another loop's end.  */
7071       if (workaround_close_loop_end && use_transform ())
7072         {
7073           maybe_has_close_loop_end = TRUE;
7074           frag_now->tc_frag_data.is_insn = TRUE;
7075           frag_var (rs_machine_dependent, 12, 12,
7076                     RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
7077                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7078         }
7079     }
7080
7081   if (use_transform ())
7082     {
7083       if (is_jump)
7084         {
7085           assert (finish_frag);
7086           frag_var (rs_machine_dependent,
7087                     UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
7088                     RELAX_UNREACHABLE,
7089                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7090           xtensa_set_frag_assembly_state (frag_now);
7091         }
7092       else if (is_branch && align_targets)
7093         {
7094           assert (finish_frag);
7095           frag_var (rs_machine_dependent,
7096                     UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
7097                     RELAX_MAYBE_UNREACHABLE,
7098                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7099           xtensa_set_frag_assembly_state (frag_now);
7100           frag_var (rs_machine_dependent,
7101                     0, 0,
7102                     RELAX_MAYBE_DESIRE_ALIGN,
7103                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7104           xtensa_set_frag_assembly_state (frag_now);
7105         }
7106     }
7107
7108   /* Now, if the original opcode was a call...  */
7109   if (do_align_targets ()
7110       && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
7111     {
7112       float freq = get_subseg_info (now_seg, now_subseg)->cur_total_freq;
7113       frag_now->tc_frag_data.is_insn = TRUE;
7114       frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
7115                 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7116       xtensa_set_frag_assembly_state (frag_now);
7117     }
7118
7119   if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7120     {
7121       frag_wane (frag_now);
7122       frag_new (0);
7123       xtensa_set_frag_assembly_state (frag_now);
7124     }
7125 }
7126
7127 \f
7128 /* xtensa_end and helper functions.  */
7129
7130 static void xtensa_cleanup_align_frags (void);
7131 static void xtensa_fix_target_frags (void);
7132 static void xtensa_mark_narrow_branches (void);
7133 static void xtensa_mark_zcl_first_insns (void);
7134 static void xtensa_fix_a0_b_retw_frags (void);
7135 static void xtensa_fix_b_j_loop_end_frags (void);
7136 static void xtensa_fix_close_loop_end_frags (void);
7137 static void xtensa_fix_short_loop_frags (void);
7138 static void xtensa_sanity_check (void);
7139
7140 void
7141 xtensa_end (void)
7142 {
7143   directive_balance ();
7144   xtensa_flush_pending_output ();
7145
7146   past_xtensa_end = TRUE;
7147
7148   xtensa_move_literals ();
7149
7150   xtensa_reorder_segments ();
7151   xtensa_cleanup_align_frags ();
7152   xtensa_fix_target_frags ();
7153   if (workaround_a0_b_retw && has_a0_b_retw)
7154     xtensa_fix_a0_b_retw_frags ();
7155   if (workaround_b_j_loop_end)
7156     xtensa_fix_b_j_loop_end_frags ();
7157
7158   /* "close_loop_end" should be processed BEFORE "short_loop".  */
7159   if (workaround_close_loop_end && maybe_has_close_loop_end)
7160     xtensa_fix_close_loop_end_frags ();
7161
7162   if (workaround_short_loop && maybe_has_short_loop)
7163     xtensa_fix_short_loop_frags ();
7164   xtensa_mark_narrow_branches ();
7165   xtensa_mark_zcl_first_insns ();
7166
7167   xtensa_sanity_check ();
7168 }
7169
7170
7171 static void
7172 xtensa_cleanup_align_frags (void)
7173 {
7174   frchainS *frchP;
7175
7176   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7177     {
7178       fragS *fragP;
7179       /* Walk over all of the fragments in a subsection.  */
7180       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7181         {
7182           if ((fragP->fr_type == rs_align
7183                || fragP->fr_type == rs_align_code
7184                || (fragP->fr_type == rs_machine_dependent
7185                    && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
7186                        || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
7187               && fragP->fr_fix == 0)
7188             {
7189               fragS *next = fragP->fr_next;
7190
7191               while (next
7192                      && next->fr_fix == 0
7193                      && next->fr_type == rs_machine_dependent
7194                      && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7195                 {
7196                   frag_wane (next);
7197                   next = next->fr_next;
7198                 }
7199             }
7200           /* If we don't widen branch targets, then they
7201              will be easier to align.  */
7202           if (fragP->tc_frag_data.is_branch_target
7203               && fragP->fr_opcode == fragP->fr_literal
7204               && fragP->fr_type == rs_machine_dependent
7205               && fragP->fr_subtype == RELAX_SLOTS
7206               && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
7207             frag_wane (fragP);
7208           if (fragP->fr_type == rs_machine_dependent
7209               && fragP->fr_subtype == RELAX_UNREACHABLE)
7210             fragP->tc_frag_data.is_unreachable = TRUE;
7211         }
7212     }
7213 }
7214
7215
7216 /* Re-process all of the fragments looking to convert all of the
7217    RELAX_DESIRE_ALIGN_IF_TARGET fragments.  If there is a branch
7218    target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7219    If the next fragment starts with a loop target, AND the previous
7220    fragment can be expanded to negate the branch, convert this to a
7221    RELAX_LOOP_END.  Otherwise, convert to a .fill 0.  */
7222
7223 static bfd_boolean frag_can_negate_branch (fragS *);
7224
7225 static void
7226 xtensa_fix_target_frags (void)
7227 {
7228   frchainS *frchP;
7229
7230   /* When this routine is called, all of the subsections are still intact
7231      so we walk over subsections instead of sections.  */
7232   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7233     {
7234       bfd_boolean prev_frag_can_negate_branch = FALSE;
7235       fragS *fragP;
7236
7237       /* Walk over all of the fragments in a subsection.  */
7238       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7239         {
7240           if (fragP->fr_type == rs_machine_dependent
7241               && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7242             {
7243               if (next_frag_is_loop_target (fragP))
7244                 {
7245                   if (prev_frag_can_negate_branch)
7246                     {
7247                       fragP->fr_subtype = RELAX_LOOP_END;
7248                       /* See the comment near the frag_var with a
7249                          RELAX_DESIRE_ALIGN to see why we do this.  */
7250                       fragP->fr_var = RELAX_LOOP_END_BYTES;
7251                     }
7252                   else
7253                     {
7254                       if (next_frag_is_branch_target (fragP))
7255                         fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7256                       else
7257                         frag_wane (fragP);
7258                     }
7259                 }
7260               else if (next_frag_is_branch_target (fragP))
7261                 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7262               else
7263                 frag_wane (fragP);
7264             }
7265           if (fragP->fr_fix != 0)
7266             prev_frag_can_negate_branch = FALSE;
7267           if (frag_can_negate_branch (fragP))
7268             prev_frag_can_negate_branch = TRUE;
7269         }
7270     }
7271 }
7272
7273
7274 static bfd_boolean
7275 frag_can_negate_branch (fragS *fragP)
7276 {
7277   xtensa_isa isa = xtensa_default_isa;
7278   vliw_insn vinsn;
7279   int slot;
7280
7281   if (fragP->fr_type != rs_machine_dependent
7282       || fragP->fr_subtype != RELAX_SLOTS)
7283     return FALSE;
7284
7285   vinsn_from_chars (&vinsn, fragP->fr_opcode);
7286
7287   for (slot = 0; slot < xtensa_format_num_slots (isa, vinsn.format); slot++)
7288     {
7289       if ((fragP->tc_frag_data.slot_subtypes[slot] == RELAX_IMMED)
7290           && xtensa_opcode_is_branch (isa, vinsn.slots[slot].opcode) == 1)
7291         return TRUE;
7292     }
7293
7294   return FALSE;
7295 }
7296
7297
7298 static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
7299
7300 static void
7301 xtensa_mark_narrow_branches (void)
7302 {
7303   frchainS *frchP;
7304
7305   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7306     {
7307       fragS *fragP;
7308       /* Walk over all of the fragments in a subsection.  */
7309       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7310         {
7311           if (fragP->fr_type == rs_machine_dependent
7312               && fragP->fr_subtype == RELAX_SLOTS
7313               && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
7314             {
7315               vliw_insn vinsn;
7316               const expressionS *expr;
7317               symbolS *symbolP;
7318
7319               vinsn_from_chars (&vinsn, fragP->fr_opcode);
7320               tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
7321
7322               expr = &vinsn.slots[0].tok[1];
7323               symbolP = expr->X_add_symbol;
7324
7325               if (vinsn.num_slots == 1
7326                   && xtensa_opcode_is_branch (xtensa_default_isa,
7327                                               vinsn.slots[0].opcode)
7328                   && xg_get_single_size (vinsn.slots[0].opcode) == 2
7329                   && is_narrow_branch_guaranteed_in_range (fragP,
7330                                                            &vinsn.slots[0]))
7331                 {
7332                   fragP->fr_subtype = RELAX_SLOTS;
7333                   fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
7334                 }
7335             }
7336         }
7337     }
7338 }
7339
7340
7341 /* A branch is typically widened only when its target is out of
7342    range.  However, we would like to widen them to align a subsequent
7343    branch target when possible.
7344
7345    Because the branch relaxation code is so convoluted, the optimal solution
7346    (combining the two cases) is difficult to get right in all circumstances.
7347    We therefore go with an "almost as good" solution, where we only
7348    use for alignment narrow branches that definitely will not expand to a
7349    jump and a branch.  These functions find and mark these cases.  */
7350
7351 /* the range in bytes of a bnez.n and beqz.n */
7352 #define MAX_IMMED6 68
7353
7354 static size_t unrelaxed_frag_max_size (fragS *);
7355
7356 static bfd_boolean
7357 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
7358 {
7359   const expressionS *expr = &tinsn->tok[1];
7360   symbolS *symbolP = expr->X_add_symbol;
7361   fragS *target_frag = symbol_get_frag (symbolP);
7362   size_t max_distance = expr->X_add_number;
7363   max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
7364   if (is_branch_jmp_to_next (tinsn, fragP))
7365     return FALSE;
7366
7367   /* The branch doesn't branch over it's own frag,
7368      but over the subsequent ones.  */
7369   fragP = fragP->fr_next;
7370   while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
7371     {
7372       max_distance += unrelaxed_frag_max_size (fragP);
7373       fragP = fragP->fr_next;
7374     }
7375   if (max_distance <= MAX_IMMED6 && fragP == target_frag)
7376     return TRUE;
7377   return FALSE;
7378 }
7379
7380
7381 static void
7382 xtensa_mark_zcl_first_insns (void)
7383 {
7384   frchainS *frchP;
7385
7386   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7387     {
7388       fragS *fragP;
7389       /* Walk over all of the fragments in a subsection.  */
7390       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7391         {
7392           if (fragP->fr_type == rs_machine_dependent
7393               && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
7394                   || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
7395             {
7396               /* Find the loop frag.  */
7397               fragS *targ_frag = next_non_empty_frag (fragP);
7398               /* Find the first insn frag.  */
7399               targ_frag = next_non_empty_frag (targ_frag);
7400
7401               /* Of course, sometimes (mostly for toy test cases) a
7402                  zero-cost loop instruction is the last in a section.  */
7403               if (targ_frag)
7404                 {
7405                   targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
7406                   if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
7407                     frag_wane (fragP);
7408                 }
7409             }
7410         }
7411     }
7412 }
7413
7414
7415 /* Re-process all of the fragments looking to convert all of the
7416    RELAX_ADD_NOP_IF_A0_B_RETW.  If the next instruction is a
7417    conditional branch or a retw/retw.n, convert this frag to one that
7418    will generate a NOP.  In any case close it off with a .fill 0.  */
7419
7420 static bfd_boolean next_instrs_are_b_retw (fragS *);
7421
7422 static void
7423 xtensa_fix_a0_b_retw_frags (void)
7424 {
7425   frchainS *frchP;
7426
7427   /* When this routine is called, all of the subsections are still intact
7428      so we walk over subsections instead of sections.  */
7429   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7430     {
7431       fragS *fragP;
7432
7433       /* Walk over all of the fragments in a subsection.  */
7434       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7435         {
7436           if (fragP->fr_type == rs_machine_dependent
7437               && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
7438             {
7439               if (next_instrs_are_b_retw (fragP))
7440                 {
7441                   if (get_frag_is_no_transform (fragP))
7442                     as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7443                   else
7444                     relax_frag_add_nop (fragP);
7445                 }
7446               frag_wane (fragP);
7447             }
7448         }
7449     }
7450 }
7451
7452
7453 static bfd_boolean
7454 next_instrs_are_b_retw (fragS *fragP)
7455 {
7456   xtensa_opcode opcode;
7457   xtensa_format fmt;
7458   const fragS *next_fragP = next_non_empty_frag (fragP);
7459   static xtensa_insnbuf insnbuf = NULL;
7460   static xtensa_insnbuf slotbuf = NULL;
7461   xtensa_isa isa = xtensa_default_isa;
7462   int offset = 0;
7463   int slot;
7464   bfd_boolean branch_seen = FALSE;
7465
7466   if (!insnbuf)
7467     {
7468       insnbuf = xtensa_insnbuf_alloc (isa);
7469       slotbuf = xtensa_insnbuf_alloc (isa);
7470     }
7471
7472   if (next_fragP == NULL)
7473     return FALSE;
7474
7475   /* Check for the conditional branch.  */
7476   xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset], 0);
7477   fmt = xtensa_format_decode (isa, insnbuf);
7478   if (fmt == XTENSA_UNDEFINED)
7479     return FALSE;
7480
7481   for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
7482     {
7483       xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
7484       opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
7485
7486       branch_seen = (branch_seen
7487                      || xtensa_opcode_is_branch (isa, opcode) == 1);
7488     }
7489
7490   if (!branch_seen)
7491     return FALSE;
7492
7493   offset += xtensa_format_length (isa, fmt);
7494   if (offset == next_fragP->fr_fix)
7495     {
7496       next_fragP = next_non_empty_frag (next_fragP);
7497       offset = 0;
7498     }
7499
7500   if (next_fragP == NULL)
7501     return FALSE;
7502
7503   /* Check for the retw/retw.n.  */
7504   xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset], 0);
7505   fmt = xtensa_format_decode (isa, insnbuf);
7506
7507   /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7508      have no problems.  */
7509   if (fmt == XTENSA_UNDEFINED
7510       || xtensa_format_num_slots (isa, fmt) != 1)
7511     return FALSE;
7512
7513   xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
7514   opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
7515
7516   if (is_windowed_return_opcode (opcode))
7517     return TRUE;
7518
7519   return FALSE;
7520 }
7521
7522
7523 /* Re-process all of the fragments looking to convert all of the
7524    RELAX_ADD_NOP_IF_PRE_LOOP_END.  If there is one instruction and a
7525    loop end label, convert this frag to one that will generate a NOP.
7526    In any case close it off with a .fill 0.  */
7527
7528 static bfd_boolean next_instr_is_loop_end (fragS *);
7529
7530 static void
7531 xtensa_fix_b_j_loop_end_frags (void)
7532 {
7533   frchainS *frchP;
7534
7535   /* When this routine is called, all of the subsections are still intact
7536      so we walk over subsections instead of sections.  */
7537   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7538     {
7539       fragS *fragP;
7540
7541       /* Walk over all of the fragments in a subsection.  */
7542       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7543         {
7544           if (fragP->fr_type == rs_machine_dependent
7545               && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
7546             {
7547               if (next_instr_is_loop_end (fragP))
7548                 {
7549                   if (get_frag_is_no_transform (fragP))
7550                     as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7551                   else
7552                     relax_frag_add_nop (fragP);
7553                 }
7554               frag_wane (fragP);
7555             }
7556         }
7557     }
7558 }
7559
7560
7561 static bfd_boolean
7562 next_instr_is_loop_end (fragS *fragP)
7563 {
7564   const fragS *next_fragP;
7565
7566   if (next_frag_is_loop_target (fragP))
7567     return FALSE;
7568
7569   next_fragP = next_non_empty_frag (fragP);
7570   if (next_fragP == NULL)
7571     return FALSE;
7572
7573   if (!next_frag_is_loop_target (next_fragP))
7574     return FALSE;
7575
7576   /* If the size is >= 3 then there is more than one instruction here.
7577      The hardware bug will not fire.  */
7578   if (next_fragP->fr_fix > 3)
7579     return FALSE;
7580
7581   return TRUE;
7582 }
7583
7584
7585 /* Re-process all of the fragments looking to convert all of the
7586    RELAX_ADD_NOP_IF_CLOSE_LOOP_END.  If there is an loop end that is
7587    not MY loop's loop end within 12 bytes, add enough nops here to
7588    make it at least 12 bytes away.  In any case close it off with a
7589    .fill 0.  */
7590
7591 static size_t min_bytes_to_other_loop_end (fragS *, fragS *, offsetT, size_t);
7592
7593 static void
7594 xtensa_fix_close_loop_end_frags (void)
7595 {
7596   frchainS *frchP;
7597
7598   /* When this routine is called, all of the subsections are still intact
7599      so we walk over subsections instead of sections.  */
7600   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7601     {
7602       fragS *fragP;
7603
7604       fragS *current_target = NULL;
7605       offsetT current_offset = 0;
7606
7607       /* Walk over all of the fragments in a subsection.  */
7608       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7609         {
7610           if (fragP->fr_type == rs_machine_dependent
7611               && ((fragP->fr_subtype == RELAX_IMMED)
7612                   || ((fragP->fr_subtype == RELAX_SLOTS)
7613                       && (fragP->tc_frag_data.slot_subtypes[0]
7614                           == RELAX_IMMED))))
7615             {
7616               /* Read it.  If the instruction is a loop, get the target.  */
7617               TInsn t_insn;
7618               tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7619               if (xtensa_opcode_is_loop (xtensa_default_isa,
7620                                          t_insn.opcode) == 1)
7621                 {
7622                   /* Get the current fragment target.  */
7623                   if (fragP->tc_frag_data.slot_symbols[0])
7624                     {
7625                       symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
7626                       current_target = symbol_get_frag (sym);
7627                       current_offset = fragP->fr_offset;
7628                     }
7629                 }
7630             }
7631
7632           if (current_target
7633               && fragP->fr_type == rs_machine_dependent
7634               && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
7635             {
7636               size_t min_bytes;
7637               size_t bytes_added = 0;
7638
7639 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7640               /* Max out at 12.  */
7641               min_bytes = min_bytes_to_other_loop_end
7642                 (fragP->fr_next, current_target, current_offset,
7643                  REQUIRED_LOOP_DIVIDING_BYTES);
7644
7645               if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
7646                 {
7647                   if (get_frag_is_no_transform (fragP))
7648                     as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7649                   else
7650                     {
7651                       while (min_bytes + bytes_added
7652                              < REQUIRED_LOOP_DIVIDING_BYTES)
7653                         {
7654                           int length = 3;
7655
7656                           if (fragP->fr_var < length)
7657                             as_fatal (_("fr_var %lu < length %d"),
7658                                       fragP->fr_var, length);
7659                           else
7660                             {
7661                               assemble_nop (length,
7662                                             fragP->fr_literal + fragP->fr_fix);
7663                               fragP->fr_fix += length;
7664                               fragP->fr_var -= length;
7665                             }
7666                           bytes_added += length;
7667                         }
7668                     }
7669                 }
7670               frag_wane (fragP);
7671             }
7672           assert (fragP->fr_type != rs_machine_dependent
7673                   || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
7674         }
7675     }
7676 }
7677
7678
7679 static size_t unrelaxed_frag_min_size (fragS *);
7680
7681 static size_t
7682 min_bytes_to_other_loop_end (fragS *fragP,
7683                              fragS *current_target,
7684                              offsetT current_offset,
7685                              size_t max_size)
7686 {
7687   size_t offset = 0;
7688   fragS *current_fragP;
7689
7690   for (current_fragP = fragP;
7691        current_fragP;
7692        current_fragP = current_fragP->fr_next)
7693     {
7694       if (current_fragP->tc_frag_data.is_loop_target
7695           && current_fragP != current_target)
7696         return offset + current_offset;
7697
7698       offset += unrelaxed_frag_min_size (current_fragP);
7699
7700       if (offset + current_offset >= max_size)
7701         return max_size;
7702     }
7703   return max_size;
7704 }
7705
7706
7707 static size_t
7708 unrelaxed_frag_min_size (fragS *fragP)
7709 {
7710   size_t size = fragP->fr_fix;
7711
7712   /* add fill size */
7713   if (fragP->fr_type == rs_fill)
7714     size += fragP->fr_offset;
7715
7716   return size;
7717 }
7718
7719
7720 static size_t
7721 unrelaxed_frag_max_size (fragS *fragP)
7722 {
7723   size_t size = fragP->fr_fix;
7724   switch (fragP->fr_type)
7725     {
7726     case 0:
7727       /* Empty frags created by the obstack allocation scheme
7728          end up with type 0.  */
7729       break;
7730     case rs_fill:
7731     case rs_org:
7732     case rs_space:
7733       size += fragP->fr_offset;
7734       break;
7735     case rs_align:
7736     case rs_align_code:
7737     case rs_align_test:
7738     case rs_leb128:
7739     case rs_cfa:
7740     case rs_dwarf2dbg:
7741       /* No further adjustments needed.  */
7742       break;
7743     case rs_machine_dependent:
7744       if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
7745         size += fragP->fr_var;
7746       break;
7747     default:
7748       /* We had darn well better know how big it is.  */
7749       assert (0);
7750       break;
7751     }
7752
7753   return size;
7754 }
7755
7756
7757 /* Re-process all of the fragments looking to convert all
7758    of the RELAX_ADD_NOP_IF_SHORT_LOOP.  If:
7759
7760    A)
7761      1) the instruction size count to the loop end label
7762         is too short (<= 2 instructions),
7763      2) loop has a jump or branch in it
7764
7765    or B)
7766      1) workaround_all_short_loops is TRUE
7767      2) The generating loop was a  'loopgtz' or 'loopnez'
7768      3) the instruction size count to the loop end label is too short
7769         (<= 2 instructions)
7770    then convert this frag (and maybe the next one) to generate a NOP.
7771    In any case close it off with a .fill 0.  */
7772
7773 static size_t count_insns_to_loop_end (fragS *, bfd_boolean, size_t);
7774 static bfd_boolean branch_before_loop_end (fragS *);
7775
7776 static void
7777 xtensa_fix_short_loop_frags (void)
7778 {
7779   frchainS *frchP;
7780
7781   /* When this routine is called, all of the subsections are still intact
7782      so we walk over subsections instead of sections.  */
7783   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7784     {
7785       fragS *fragP;
7786       fragS *current_target = NULL;
7787       offsetT current_offset = 0;
7788       xtensa_opcode current_opcode = XTENSA_UNDEFINED;
7789
7790       /* Walk over all of the fragments in a subsection.  */
7791       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7792         {
7793           /* Check on the current loop.  */
7794           if (fragP->fr_type == rs_machine_dependent
7795               && ((fragP->fr_subtype == RELAX_IMMED)
7796                   || ((fragP->fr_subtype == RELAX_SLOTS)
7797                       && (fragP->tc_frag_data.slot_subtypes[0]
7798                           == RELAX_IMMED))))
7799             {
7800               TInsn t_insn;
7801
7802               /* Read it.  If the instruction is a loop, get the target.  */
7803               tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7804               if (xtensa_opcode_is_loop (xtensa_default_isa,
7805                                          t_insn.opcode) == 1)
7806                 {
7807                   /* Get the current fragment target.  */
7808                   if (fragP->tc_frag_data.slot_symbols[0])
7809                     {
7810                       symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
7811                       current_target = symbol_get_frag (sym);
7812                       current_offset = fragP->fr_offset;
7813                       current_opcode = t_insn.opcode;
7814                     }
7815                 }
7816             }
7817
7818           if (fragP->fr_type == rs_machine_dependent
7819               && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7820             {
7821               size_t insn_count =
7822                 count_insns_to_loop_end (fragP->fr_next, TRUE, 3);
7823               if (insn_count < 3
7824                   && (branch_before_loop_end (fragP->fr_next)
7825                       || (workaround_all_short_loops
7826                           && current_opcode != XTENSA_UNDEFINED
7827                           && !is_the_loop_opcode (current_opcode))))
7828                 {
7829                   if (get_frag_is_no_transform (fragP))
7830                     as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7831                   else
7832                     relax_frag_add_nop (fragP);
7833                 }
7834               frag_wane (fragP);
7835             }
7836         }
7837     }
7838 }
7839
7840
7841 static size_t unrelaxed_frag_min_insn_count (fragS *);
7842
7843 static size_t
7844 count_insns_to_loop_end (fragS *base_fragP,
7845                          bfd_boolean count_relax_add,
7846                          size_t max_count)
7847 {
7848   fragS *fragP = NULL;
7849   size_t insn_count = 0;
7850
7851   fragP = base_fragP;
7852
7853   for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
7854     {
7855       insn_count += unrelaxed_frag_min_insn_count (fragP);
7856       if (insn_count >= max_count)
7857         return max_count;
7858
7859       if (count_relax_add)
7860         {
7861           if (fragP->fr_type == rs_machine_dependent
7862               && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7863             {
7864               /* In order to add the appropriate number of
7865                  NOPs, we count an instruction for downstream
7866                  occurrences.  */
7867               insn_count++;
7868               if (insn_count >= max_count)
7869                 return max_count;
7870             }
7871         }
7872     }
7873   return insn_count;
7874 }
7875
7876
7877 static size_t
7878 unrelaxed_frag_min_insn_count (fragS *fragP)
7879 {
7880   xtensa_isa isa = xtensa_default_isa;
7881   static xtensa_insnbuf insnbuf = NULL;
7882   size_t insn_count = 0;
7883   int offset = 0;
7884
7885   if (!fragP->tc_frag_data.is_insn)
7886     return insn_count;
7887
7888   if (!insnbuf)
7889     insnbuf = xtensa_insnbuf_alloc (isa);
7890
7891   /* Decode the fixed instructions.  */
7892   while (offset < fragP->fr_fix)
7893     {
7894       xtensa_format fmt;
7895
7896       xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal + offset, 0);
7897       fmt = xtensa_format_decode (isa, insnbuf);
7898
7899       if (fmt == XTENSA_UNDEFINED)
7900         {
7901           as_fatal (_("undecodable instruction in instruction frag"));
7902           return insn_count;
7903         }
7904       offset += xtensa_format_length (isa, fmt);
7905       insn_count++;
7906     }
7907
7908   return insn_count;
7909 }
7910
7911
7912 static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
7913
7914 static bfd_boolean
7915 branch_before_loop_end (fragS *base_fragP)
7916 {
7917   fragS *fragP;
7918
7919   for (fragP = base_fragP;
7920        fragP && !fragP->tc_frag_data.is_loop_target;
7921        fragP = fragP->fr_next)
7922     {
7923       if (unrelaxed_frag_has_b_j (fragP))
7924         return TRUE;
7925     }
7926   return FALSE;
7927 }
7928
7929
7930 static bfd_boolean
7931 unrelaxed_frag_has_b_j (fragS *fragP)
7932 {
7933   static xtensa_insnbuf insnbuf = NULL;
7934   xtensa_isa isa = xtensa_default_isa;
7935   int offset = 0;
7936
7937   if (!fragP->tc_frag_data.is_insn)
7938     return FALSE;
7939
7940   if (!insnbuf)
7941     insnbuf = xtensa_insnbuf_alloc (isa);
7942
7943   /* Decode the fixed instructions.  */
7944   while (offset < fragP->fr_fix)
7945     {
7946       xtensa_format fmt;
7947       int slot;
7948
7949       xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal + offset, 0);
7950       fmt = xtensa_format_decode (isa, insnbuf);
7951       if (fmt == XTENSA_UNDEFINED)
7952         return FALSE;
7953
7954       for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
7955         {
7956           xtensa_opcode opcode =
7957             get_opcode_from_buf (fragP->fr_literal + offset, slot);
7958           if (xtensa_opcode_is_branch (isa, opcode) == 1
7959               || xtensa_opcode_is_jump (isa, opcode) == 1)
7960             return TRUE;
7961         }
7962       offset += xtensa_format_length (isa, fmt);
7963     }
7964   return FALSE;
7965 }
7966
7967
7968 /* Checks to be made after initial assembly but before relaxation.  */
7969
7970 static bfd_boolean is_empty_loop (const TInsn *, fragS *);
7971 static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
7972
7973 static void
7974 xtensa_sanity_check (void)
7975 {
7976   char *file_name;
7977   int line;
7978
7979   frchainS *frchP;
7980
7981   as_where (&file_name, &line);
7982   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7983     {
7984       fragS *fragP;
7985
7986       /* Walk over all of the fragments in a subsection.  */
7987       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7988         {
7989           /* Currently we only check for empty loops here.  */
7990           if (fragP->fr_type == rs_machine_dependent
7991               && fragP->fr_subtype == RELAX_IMMED)
7992             {
7993               static xtensa_insnbuf insnbuf = NULL;
7994               TInsn t_insn;
7995
7996               if (fragP->fr_opcode != NULL)
7997                 {
7998                   if (!insnbuf)
7999                     insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
8000                   tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
8001                   tinsn_immed_from_frag (&t_insn, fragP, 0);
8002
8003                   if (xtensa_opcode_is_loop (xtensa_default_isa,
8004                                              t_insn.opcode) == 1)
8005                     {
8006                       if (is_empty_loop (&t_insn, fragP))
8007                         {
8008                           new_logical_line (fragP->fr_file, fragP->fr_line);
8009                           as_bad (_("invalid empty loop"));
8010                         }
8011                       if (!is_local_forward_loop (&t_insn, fragP))
8012                         {
8013                           new_logical_line (fragP->fr_file, fragP->fr_line);
8014                           as_bad (_("loop target does not follow "
8015                                     "loop instruction in section"));
8016                         }
8017                     }
8018                 }
8019             }
8020         }
8021     }
8022   new_logical_line (file_name, line);
8023 }
8024
8025
8026 #define LOOP_IMMED_OPN 1
8027
8028 /* Return TRUE if the loop target is the next non-zero fragment.  */
8029
8030 static bfd_boolean
8031 is_empty_loop (const TInsn *insn, fragS *fragP)
8032 {
8033   const expressionS *expr;
8034   symbolS *symbolP;
8035   fragS *next_fragP;
8036
8037   if (insn->insn_type != ITYPE_INSN)
8038     return FALSE;
8039
8040   if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8041     return FALSE;
8042
8043   if (insn->ntok <= LOOP_IMMED_OPN)
8044     return FALSE;
8045
8046   expr = &insn->tok[LOOP_IMMED_OPN];
8047
8048   if (expr->X_op != O_symbol)
8049     return FALSE;
8050
8051   symbolP = expr->X_add_symbol;
8052   if (!symbolP)
8053     return FALSE;
8054
8055   if (symbol_get_frag (symbolP) == NULL)
8056     return FALSE;
8057
8058   if (S_GET_VALUE (symbolP) != 0)
8059     return FALSE;
8060
8061   /* Walk through the zero-size fragments from this one.  If we find
8062      the target fragment, then this is a zero-size loop.  */
8063
8064   for (next_fragP = fragP->fr_next;
8065        next_fragP != NULL;
8066        next_fragP = next_fragP->fr_next)
8067     {
8068       if (next_fragP == symbol_get_frag (symbolP))
8069         return TRUE;
8070       if (next_fragP->fr_fix != 0)
8071         return FALSE;
8072     }
8073   return FALSE;
8074 }
8075
8076
8077 static bfd_boolean
8078 is_local_forward_loop (const TInsn *insn, fragS *fragP)
8079 {
8080   const expressionS *expr;
8081   symbolS *symbolP;
8082   fragS *next_fragP;
8083
8084   if (insn->insn_type != ITYPE_INSN)
8085     return FALSE;
8086
8087   if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0)
8088     return FALSE;
8089
8090   if (insn->ntok <= LOOP_IMMED_OPN)
8091     return FALSE;
8092
8093   expr = &insn->tok[LOOP_IMMED_OPN];
8094
8095   if (expr->X_op != O_symbol)
8096     return FALSE;
8097
8098   symbolP = expr->X_add_symbol;
8099   if (!symbolP)
8100     return FALSE;
8101
8102   if (symbol_get_frag (symbolP) == NULL)
8103     return FALSE;
8104
8105   /* Walk through fragments until we find the target.
8106      If we do not find the target, then this is an invalid loop.  */
8107
8108   for (next_fragP = fragP->fr_next;
8109        next_fragP != NULL;
8110        next_fragP = next_fragP->fr_next)
8111     {
8112       if (next_fragP == symbol_get_frag (symbolP))
8113         return TRUE;
8114     }
8115
8116   return FALSE;
8117 }
8118
8119 \f
8120 /* Alignment Functions.  */
8121
8122 static size_t
8123 get_text_align_power (int target_size)
8124 {
8125   size_t i = 0;
8126   for (i = 0; i < sizeof (size_t); i++)
8127     {
8128       if (target_size <= (1 << i))
8129         return i;
8130     }
8131   assert (0);
8132   return 0;
8133 }
8134
8135
8136 static addressT
8137 get_text_align_max_fill_size (int align_pow,
8138                               bfd_boolean use_nops,
8139                               bfd_boolean use_no_density)
8140 {
8141   if (!use_nops)
8142     return (1 << align_pow);
8143   if (use_no_density)
8144     return 3 * (1 << align_pow);
8145
8146   return 1 + (1 << align_pow);
8147 }
8148
8149
8150 /* get_text_align_fill_size ()
8151
8152    Desired alignments:
8153       give the address
8154       target_size = size of next instruction
8155       align_pow = get_text_align_power (target_size).
8156       use_nops = 0
8157       use_no_density = 0;
8158    Loop alignments:
8159       address = current address + loop instruction size;
8160       target_size = 3 (for 2 or 3 byte target)
8161                   = 4 (for 4 byte target)
8162                   = 8 (for 8 byte target)
8163       align_pow = get_text_align_power (target_size);
8164       use_nops = 1
8165       use_no_density = set appropriately
8166    Text alignments:
8167       address = current address + loop instruction size;
8168       target_size = 0
8169       align_pow = get_text_align_power (target_size);
8170       use_nops = 0
8171       use_no_density = 0.  */
8172
8173 static addressT
8174 get_text_align_fill_size (addressT address,
8175                           int align_pow,
8176                           int target_size,
8177                           bfd_boolean use_nops,
8178                           bfd_boolean use_no_density)
8179 {
8180   /* Input arguments:
8181
8182      align_pow: log2 (required alignment).
8183
8184      target_size: alignment must allow the new_address and
8185      new_address+target_size-1.
8186
8187      use_nops: if TRUE, then we can only use 2- or 3-byte nops.
8188
8189      use_no_density: if use_nops and use_no_density, we can only use
8190      3-byte nops.
8191
8192      Usually the align_pow is the power of 2 that is greater than
8193      or equal to the target_size.  This handles the 2-byte, 3-byte
8194      and 8-byte instructions.
8195
8196      Two cases:
8197
8198      (1) aligning an instruction properly, but without using NOPs.
8199        E.G.: a 3-byte instruction can go on any address where address mod 4
8200        is zero or one.  The aligner uses this case to find the optimal
8201        number of fill bytes for relax_frag_for_align.
8202
8203      (2) aligning an instruction properly, but where we might need to use
8204        extra NOPs.  E.G.: when the aligner couldn't find enough widenings
8205        or similar to get the optimal location.  */
8206
8207   size_t alignment = (1 << align_pow);
8208
8209   assert (target_size != 0);
8210
8211   if (!use_nops)
8212     {
8213       unsigned fill_bytes;
8214       for (fill_bytes = 0; fill_bytes < alignment; fill_bytes++)
8215         {
8216           addressT end_address = address + target_size - 1 + fill_bytes;
8217           addressT start_address = address + fill_bytes;
8218           if ((end_address >> align_pow) == (start_address >> align_pow))
8219             return fill_bytes;
8220         }
8221       assert (0);
8222     }
8223
8224   /* This is the slightly harder case.  */
8225   assert ((int) alignment >= target_size);
8226   assert (target_size > 0);
8227   if (!use_no_density)
8228     {
8229       size_t i;
8230       for (i = 0; i < alignment * 2; i++)
8231         {
8232           if (i == 1)
8233             continue;
8234           if ((address + i) >> align_pow
8235               == (address + i + target_size - 1) >> align_pow)
8236             return i;
8237         }
8238     }
8239   else
8240     {
8241       size_t i;
8242
8243       /* Can only fill multiples of 3.  */
8244       for (i = 0; i <= alignment * 3; i += 3)
8245         {
8246           if ((address + i) >> align_pow
8247               == (address + i + target_size - 1) >> align_pow)
8248             return i;
8249         }
8250     }
8251   assert (0);
8252   return 0;
8253 }
8254
8255
8256 /* This will assert if it is not possible.  */
8257
8258 static size_t
8259 get_text_align_nop_count (size_t fill_size, bfd_boolean use_no_density)
8260 {
8261   size_t count = 0;
8262   if (use_no_density)
8263     {
8264       assert (fill_size % 3 == 0);
8265       return (fill_size / 3);
8266     }
8267
8268   assert (fill_size != 1);      /* Bad argument.  */
8269
8270   while (fill_size > 1)
8271     {
8272       size_t insn_size = 3;
8273       if (fill_size == 2 || fill_size == 4)
8274         insn_size = 2;
8275       fill_size -= insn_size;
8276       count++;
8277     }
8278   assert (fill_size != 1);      /* Bad algorithm.  */
8279   return count;
8280 }
8281
8282
8283 static size_t
8284 get_text_align_nth_nop_size (size_t fill_size,
8285                              size_t n,
8286                              bfd_boolean use_no_density)
8287 {
8288   size_t count = 0;
8289
8290   assert (get_text_align_nop_count (fill_size, use_no_density) > n);
8291
8292   if (use_no_density)
8293     return 3;
8294
8295   while (fill_size > 1)
8296     {
8297       size_t insn_size = 3;
8298       if (fill_size == 2 || fill_size == 4)
8299         insn_size = 2;
8300       fill_size -= insn_size;
8301       count++;
8302       if (n + 1 == count)
8303         return insn_size;
8304     }
8305   assert (0);
8306   return 0;
8307 }
8308
8309
8310 /* For the given fragment, find the appropriate address
8311    for it to begin at if we are using NOPs to align it.  */
8312
8313 static addressT
8314 get_noop_aligned_address (fragS *fragP, addressT address)
8315 {
8316   /* The rule is: get next fragment's FIRST instruction.  Find
8317      the smallest number of bytes that need to be added to
8318      ensure that the next fragment's FIRST instruction will fit
8319      in a single word.
8320
8321      E.G.,   2 bytes : 0, 1, 2 mod 4
8322              3 bytes: 0, 1 mod 4
8323
8324      If the FIRST instruction MIGHT be relaxed,
8325      assume that it will become a 3-byte instruction.
8326
8327      Note again here that LOOP instructions are not bundleable,
8328      and this relaxation only applies to LOOP opcodes.  */
8329
8330   size_t fill_size = 0;
8331   int first_insn_size;
8332   int loop_insn_size;
8333   addressT pre_opcode_bytes;
8334   size_t alignment;
8335   fragS *first_insn;
8336   xtensa_opcode opcode;
8337   bfd_boolean is_loop;
8338
8339   assert (fragP->fr_type == rs_machine_dependent);
8340   assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
8341
8342   /* Find the loop frag.  */
8343   first_insn = next_non_empty_frag (fragP);
8344   /* Now find the first insn frag.  */
8345   first_insn = next_non_empty_frag (first_insn);
8346
8347   is_loop = next_frag_opcode_is_loop (fragP, &opcode);
8348   assert (is_loop);
8349   loop_insn_size = xg_get_single_size (opcode);
8350
8351   pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
8352   pre_opcode_bytes += loop_insn_size;
8353
8354   /* For loops, the alignment depends on the size of the
8355      instruction following the loop, not the LOOP instruction.  */
8356
8357   if (first_insn == NULL)
8358     return address;
8359
8360   assert (first_insn->tc_frag_data.is_first_loop_insn);
8361
8362   first_insn_size = frag_format_size (first_insn);
8363
8364   if (first_insn_size == 2 || first_insn_size == XTENSA_UNDEFINED)
8365     first_insn_size = 3;        /* ISA specifies this */
8366
8367   /* If it was 8, then we'll need a larger alignment for the section.  */
8368   alignment = get_text_align_power (first_insn_size);
8369
8370   /* Is now_seg valid?  */
8371   record_alignment (now_seg, alignment);
8372
8373   fill_size = get_text_align_fill_size
8374     (address + pre_opcode_bytes,
8375      get_text_align_power (first_insn_size),
8376      first_insn_size, TRUE, fragP->tc_frag_data.is_no_density);
8377
8378   return address + fill_size;
8379 }
8380
8381
8382 /* 3 mechanisms for relaxing an alignment:
8383
8384    Align to a power of 2.
8385    Align so the next fragment's instruction does not cross a word boundary.
8386    Align the current instruction so that if the next instruction
8387        were 3 bytes, it would not cross a word boundary.
8388
8389    We can align with:
8390
8391    zeros    - This is easy; always insert zeros.
8392    nops     - 3-byte and 2-byte instructions
8393               2 - 2-byte nop
8394               3 - 3-byte nop
8395               4 - 2 2-byte nops
8396               >=5 : 3-byte instruction + fn (n-3)
8397    widening - widen previous instructions.  */
8398
8399 static addressT
8400 get_aligned_diff (fragS *fragP, addressT address, addressT *max_diff)
8401 {
8402   addressT target_address, loop_insn_offset;
8403   int target_size;
8404   xtensa_opcode loop_opcode;
8405   bfd_boolean is_loop;
8406   int text_align_power;
8407   addressT opt_diff;
8408
8409   assert (fragP->fr_type == rs_machine_dependent);
8410   switch (fragP->fr_subtype)
8411     {
8412     case RELAX_DESIRE_ALIGN:
8413       target_size = next_frag_format_size (fragP);
8414       if (target_size == XTENSA_UNDEFINED)
8415         target_size = 3;
8416       text_align_power = get_text_align_power (xtensa_fetch_width);
8417       opt_diff = get_text_align_fill_size (address, text_align_power,
8418                                            target_size, FALSE, FALSE);
8419
8420       *max_diff = opt_diff + xtensa_fetch_width
8421         - (target_size + ((address + opt_diff) % xtensa_fetch_width));
8422       assert (*max_diff >= opt_diff);
8423       return opt_diff;
8424
8425     case RELAX_ALIGN_NEXT_OPCODE:
8426       target_size = next_frag_format_size (fragP);
8427       loop_insn_offset = 0;
8428       is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
8429       assert (is_loop);
8430
8431       /* If the loop has been expanded then the LOOP instruction
8432          could be at an offset from this fragment.  */
8433       if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0]
8434           != RELAX_IMMED)
8435         loop_insn_offset = get_expanded_loop_offset (loop_opcode);
8436
8437       if (target_size == 2)
8438         target_size = 3; /* ISA specifies this */
8439
8440       /* In an ideal world, which is what we are shooting for here,
8441          we wouldn't need to use any NOPs immediately prior to the
8442          LOOP instruction.  If this approach fails, relax_frag_loop_align
8443          will call get_noop_aligned_address.  */
8444       target_address =
8445         address + loop_insn_offset + xg_get_single_size (loop_opcode);
8446       text_align_power = get_text_align_power (target_size),
8447       opt_diff = get_text_align_fill_size (target_address, text_align_power,
8448                                            target_size, FALSE, FALSE);
8449
8450       *max_diff = xtensa_fetch_width
8451         - ((target_address + opt_diff) % xtensa_fetch_width)
8452         - target_size + opt_diff;
8453       assert (*max_diff >= opt_diff);
8454       return opt_diff;
8455
8456     default:
8457       break;
8458     }
8459   assert (0);
8460   return 0;
8461 }
8462
8463 \f
8464 /* md_relax_frag Hook and Helper Functions.  */
8465
8466 static long relax_frag_loop_align (fragS *, long);
8467 static long relax_frag_for_align (fragS *, long);
8468 static long relax_frag_immed
8469   (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
8470
8471
8472 /* Return the number of bytes added to this fragment, given that the
8473    input has been stretched already by "stretch".  */
8474
8475 long
8476 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
8477 {
8478   xtensa_isa isa = xtensa_default_isa;
8479   int unreported = fragP->tc_frag_data.unreported_expansion;
8480   long new_stretch = 0;
8481   char *file_name;
8482   int line, lit_size;
8483   static xtensa_insnbuf vbuf = NULL;
8484   int slot, num_slots;
8485   xtensa_format fmt;
8486
8487   as_where (&file_name, &line);
8488   new_logical_line (fragP->fr_file, fragP->fr_line);
8489
8490   fragP->tc_frag_data.unreported_expansion = 0;
8491
8492   switch (fragP->fr_subtype)
8493     {
8494     case RELAX_ALIGN_NEXT_OPCODE:
8495       /* Always convert.  */
8496       if (fragP->tc_frag_data.relax_seen)
8497         new_stretch = relax_frag_loop_align (fragP, stretch);
8498       break;
8499
8500     case RELAX_LOOP_END:
8501       /* Do nothing.  */
8502       break;
8503
8504     case RELAX_LOOP_END_ADD_NOP:
8505       /* Add a NOP and switch to .fill 0.  */
8506       new_stretch = relax_frag_add_nop (fragP);
8507       frag_wane (fragP);
8508       break;
8509
8510     case RELAX_DESIRE_ALIGN:
8511       /* Do nothing. The narrowing before this frag will either align
8512          it or not.  */
8513       break;
8514
8515     case RELAX_LITERAL:
8516     case RELAX_LITERAL_FINAL:
8517       return 0;
8518
8519     case RELAX_LITERAL_NR:
8520       lit_size = 4;
8521       fragP->fr_subtype = RELAX_LITERAL_FINAL;
8522       assert (unreported == lit_size);
8523       memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
8524       fragP->fr_var -= lit_size;
8525       fragP->fr_fix += lit_size;
8526       new_stretch = 4;
8527       break;
8528
8529     case RELAX_SLOTS:
8530       if (vbuf == NULL)
8531         vbuf = xtensa_insnbuf_alloc (isa);
8532
8533       xtensa_insnbuf_from_chars (isa, vbuf, fragP->fr_opcode, 0);
8534       fmt = xtensa_format_decode (isa, vbuf);
8535       num_slots = xtensa_format_num_slots (isa, fmt);
8536
8537       for (slot = 0; slot < num_slots; slot++)
8538         {
8539           switch (fragP->tc_frag_data.slot_subtypes[slot])
8540             {
8541             case RELAX_NARROW:
8542               if (fragP->tc_frag_data.relax_seen)
8543                 new_stretch += relax_frag_for_align (fragP, stretch);
8544               break;
8545
8546             case RELAX_IMMED:
8547             case RELAX_IMMED_STEP1:
8548             case RELAX_IMMED_STEP2:
8549               /* Place the immediate.  */
8550               new_stretch += relax_frag_immed
8551                 (now_seg, fragP, stretch,
8552                  fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
8553                  fmt, slot, stretched_p, FALSE);
8554               break;
8555
8556             default:
8557               /* This is OK; see the note in xg_assemble_vliw_tokens.  */
8558               break;
8559             }
8560         }
8561       break;
8562
8563     case RELAX_LITERAL_POOL_BEGIN:
8564     case RELAX_LITERAL_POOL_END:
8565     case RELAX_MAYBE_UNREACHABLE:
8566     case RELAX_MAYBE_DESIRE_ALIGN:
8567       /* No relaxation required.  */
8568       break;
8569
8570     case RELAX_FILL_NOP:
8571     case RELAX_UNREACHABLE:
8572       if (fragP->tc_frag_data.relax_seen)
8573         new_stretch += relax_frag_for_align (fragP, stretch);
8574       break;
8575
8576     default:
8577       as_bad (_("bad relaxation state"));
8578     }
8579
8580   /* Tell gas we need another relaxation pass.  */
8581   if (! fragP->tc_frag_data.relax_seen)
8582     {
8583       fragP->tc_frag_data.relax_seen = TRUE;
8584       *stretched_p = 1;
8585     }
8586
8587   new_logical_line (file_name, line);
8588   return new_stretch;
8589 }
8590
8591
8592 static long
8593 relax_frag_loop_align (fragS *fragP, long stretch)
8594 {
8595   addressT old_address, old_next_address, old_size;
8596   addressT new_address, new_next_address, new_size;
8597   addressT growth;
8598
8599   /* All the frags with relax_frag_for_alignment prior to this one in the
8600      section have been done, hopefully eliminating the need for a NOP here.
8601      But, this will put it in if necessary.  */
8602
8603   /* Calculate the old address of this fragment and the next fragment.  */
8604   old_address = fragP->fr_address - stretch;
8605   old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
8606                       fragP->tc_frag_data.text_expansion[0]);
8607   old_size = old_next_address - old_address;
8608
8609   /* Calculate the new address of this fragment and the next fragment.  */
8610   new_address = fragP->fr_address;
8611   new_next_address =
8612     get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
8613   new_size = new_next_address - new_address;
8614
8615   growth = new_size - old_size;
8616
8617   /* Fix up the text_expansion field and return the new growth.  */
8618   fragP->tc_frag_data.text_expansion[0] += growth;
8619   return growth;
8620 }
8621
8622
8623 /* Add a NOP instruction.  */
8624
8625 static long
8626 relax_frag_add_nop (fragS *fragP)
8627 {
8628   char *nop_buf = fragP->fr_literal + fragP->fr_fix;
8629   int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
8630   assemble_nop (length, nop_buf);
8631   fragP->tc_frag_data.is_insn = TRUE;
8632
8633   if (fragP->fr_var < length)
8634     {
8635       as_fatal (_("fr_var (%ld) < length (%d)"), fragP->fr_var, length);
8636       return 0;
8637     }
8638
8639   fragP->fr_fix += length;
8640   fragP->fr_var -= length;
8641   return length;
8642 }
8643
8644
8645 static long future_alignment_required (fragS *, long);
8646
8647 static long
8648 relax_frag_for_align (fragS *fragP, long stretch)
8649 {
8650   /* Overview of the relaxation procedure for alignment:
8651      We can widen with NOPs or by widening instructions or by filling
8652      bytes after jump instructions.  Find the opportune places and widen
8653      them if necessary.  */
8654
8655   long stretch_me;
8656   long diff;
8657
8658   assert (fragP->fr_subtype == RELAX_FILL_NOP
8659           || fragP->fr_subtype == RELAX_UNREACHABLE
8660           || (fragP->fr_subtype == RELAX_SLOTS
8661               && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
8662
8663   stretch_me = future_alignment_required (fragP, stretch);
8664   diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
8665   if (diff == 0)
8666     return 0;
8667
8668   if (diff < 0)
8669     {
8670       /* We expanded on a previous pass.  Can we shrink now?  */
8671       long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
8672       if (shrink <= stretch && stretch > 0)
8673         {
8674           fragP->tc_frag_data.text_expansion[0] = stretch_me;
8675           return -shrink;
8676         }
8677       return 0;
8678     }
8679
8680   /* Below here, diff > 0.  */
8681   fragP->tc_frag_data.text_expansion[0] = stretch_me;
8682
8683   return diff;
8684 }
8685
8686
8687 /* Return the address of the next frag that should be aligned.
8688
8689    By "address" we mean the address it _would_ be at if there
8690    is no action taken to align it between here and the target frag.
8691    In other words, if no narrows and no fill nops are used between
8692    here and the frag to align, _even_if_ some of the frags we use
8693    to align targets have already expanded on a previous relaxation
8694    pass.
8695
8696    Also, count each frag that may be used to help align the target.
8697
8698    Return 0 if there are no frags left in the chain that need to be
8699    aligned.  */
8700
8701 static addressT
8702 find_address_of_next_align_frag (fragS **fragPP,
8703                                  int *wide_nops,
8704                                  int *narrow_nops,
8705                                  int *widens,
8706                                  bfd_boolean *paddable)
8707 {
8708   fragS *fragP = *fragPP;
8709   addressT address = fragP->fr_address;
8710
8711   /* Do not reset the counts to 0.  */
8712
8713   while (fragP)
8714     {
8715       /* Limit this to a small search.  */
8716       if (*widens > 8)
8717         {
8718           *fragPP = fragP;
8719           return 0;
8720         }
8721       address += fragP->fr_fix;
8722
8723       if (fragP->fr_type == rs_fill)
8724         address += fragP->fr_offset * fragP->fr_var;
8725       else if (fragP->fr_type == rs_machine_dependent)
8726         {
8727           switch (fragP->fr_subtype)
8728             {
8729             case RELAX_UNREACHABLE:
8730               *paddable = TRUE;
8731               break;
8732
8733             case RELAX_FILL_NOP:
8734               (*wide_nops)++;
8735               if (!fragP->tc_frag_data.is_no_density)
8736                 (*narrow_nops)++;
8737               break;
8738
8739             case RELAX_SLOTS:
8740               if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8741                 {
8742                   (*widens)++;
8743                   break;
8744                 }
8745               /* FIXME: shouldn't this add the expansion of all slots?  */
8746               address += fragP->tc_frag_data.text_expansion[0];
8747               break;
8748
8749             case RELAX_IMMED:
8750               address += fragP->tc_frag_data.text_expansion[0];
8751               break;
8752
8753             case RELAX_ALIGN_NEXT_OPCODE:
8754             case RELAX_DESIRE_ALIGN:
8755               *fragPP = fragP;
8756               return address;
8757
8758             case RELAX_MAYBE_UNREACHABLE:
8759             case RELAX_MAYBE_DESIRE_ALIGN:
8760               /* Do nothing.  */
8761               break;
8762
8763             default:
8764               /* Just punt if we don't know the type.  */
8765               *fragPP = fragP;
8766               return 0;
8767             }
8768         }
8769       else
8770         {
8771           /* Just punt if we don't know the type.  */
8772           *fragPP = fragP;
8773           return 0;
8774         }
8775       fragP = fragP->fr_next;
8776     }
8777
8778   *fragPP = fragP;
8779   return 0;
8780 }
8781
8782
8783 static long bytes_to_stretch (fragS *, int, int, int, int);
8784
8785 /* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8786    I'll leave this in until I am more confident this works.  */
8787
8788 #define LOOKAHEAD_ALIGNER 1
8789
8790 static long
8791 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
8792 {
8793   fragS *this_frag = fragP;
8794   long address;
8795   int num_widens = 0;
8796   int wide_nops = 0;
8797   int narrow_nops = 0;
8798   bfd_boolean paddable = FALSE;
8799   offsetT local_opt_diff;
8800   offsetT opt_diff;
8801   offsetT max_diff;
8802   int stretch_amount = 0;
8803   int local_stretch_amount;
8804   int global_stretch_amount;
8805
8806   address = find_address_of_next_align_frag
8807     (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
8808
8809   if (address)
8810     {
8811       local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
8812       opt_diff = local_opt_diff;
8813       assert (opt_diff >= 0);
8814       assert (max_diff >= opt_diff);
8815       if (max_diff == 0)
8816         return 0;
8817 #ifdef LOOKAHEAD_ALIGNER
8818       if (fragP)
8819         fragP = fragP->fr_next;
8820
8821       while (fragP && opt_diff < max_diff && address)
8822         {
8823           /* We only use these to determine if we can exit early
8824              because there will be plenty of ways to align future
8825              align frags.  */
8826           unsigned int glob_widens = 0;
8827           int dnn = 0;
8828           int dw = 0;
8829           bfd_boolean glob_pad = 0;
8830           address = find_address_of_next_align_frag
8831             (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
8832           /* If there is a padable portion, then skip.  */
8833           if (glob_pad || (glob_widens >= xtensa_fetch_width))
8834             break;
8835
8836           if (address)
8837             {
8838               offsetT next_m_diff;
8839               offsetT next_o_diff;
8840
8841               /* Downrange frags haven't had stretch added to them yet.  */
8842               address += stretch;
8843
8844               /* The address also includes any text expansion from this
8845                  frag in a previous pass, but we don't want that.  */
8846               address -= this_frag->tc_frag_data.text_expansion[0];
8847
8848               /* Assume we are going to move at least opt_diff.  In
8849                  reality, we might not be able to, but assuming that
8850                  we will helps catch cases where moving opt_diff pushes
8851                  the next target from aligned to unaligned.  */
8852               address += opt_diff;
8853
8854               next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
8855
8856               /* Now cleanup for the adjustments to address.  */
8857               next_o_diff += opt_diff;
8858               next_m_diff += opt_diff;
8859               if (next_o_diff <= max_diff && next_o_diff > opt_diff)
8860                 opt_diff = next_o_diff;
8861               if (next_m_diff < max_diff)
8862                 max_diff = next_m_diff;
8863               fragP = fragP->fr_next;
8864             }
8865         }
8866 #endif /* LOOKAHEAD_ALIGNER */
8867       /* If there are enough wideners in between, do it.  */
8868       if (paddable)
8869         {
8870           if (this_frag->fr_subtype == RELAX_UNREACHABLE)
8871             {
8872               assert (opt_diff <= UNREACHABLE_MAX_WIDTH);
8873               return opt_diff;
8874             }
8875           return 0;
8876         }
8877       local_stretch_amount
8878         = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8879                             num_widens, local_opt_diff);
8880 #ifdef LOOKAHEAD_ALIGNER
8881       global_stretch_amount
8882         = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8883                             num_widens, opt_diff);
8884       /* If the condition below is true, then the frag couldn't
8885          stretch the correct amount for the global case, so we just
8886          optimize locally.  We'll rely on the subsequent frags to get
8887          the correct alignment in the global case.  */
8888       if (global_stretch_amount < local_stretch_amount)
8889         stretch_amount = local_stretch_amount;
8890       else
8891         stretch_amount = global_stretch_amount;
8892 #else /* ! LOOKAHEAD_ALIGNER */
8893       stretch_amount = local_stretch_amount;
8894 #endif /* ! LOOKAHEAD_ALIGNER */
8895       if (this_frag->fr_subtype == RELAX_SLOTS
8896           && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8897         assert (stretch_amount <= 1);
8898       else if (this_frag->fr_subtype == RELAX_FILL_NOP)
8899         {
8900           if (this_frag->tc_frag_data.is_no_density)
8901             assert (stretch_amount == 3 || stretch_amount == 0);
8902           else
8903             assert (stretch_amount <= 3);
8904         }
8905     }
8906   return stretch_amount;
8907 }
8908
8909
8910 /* The idea: widen everything you can to get a target or loop aligned,
8911    then start using NOPs.
8912
8913    When we must have a NOP, here is a table of how we decide
8914    (so you don't have to fight through the control flow below):
8915
8916    wide_nops   = the number of wide NOPs available for aligning
8917    narrow_nops = the number of narrow NOPs available for aligning
8918                  (a subset of wide_nops)
8919    widens      = the number of narrow instructions that should be widened
8920
8921    Desired   wide   narrow
8922    Diff      nop    nop      widens
8923    1           0      0         1
8924    2           0      1         0
8925    3a          1      0         0
8926     b          0      1         1 (case 3a makes this case unnecessary)
8927    4a          1      0         1
8928     b          0      2         0
8929     c          0      1         2 (case 4a makes this case unnecessary)
8930    5a          1      0         2
8931     b          1      1         0
8932     c          0      2         1 (case 5b makes this case unnecessary)
8933    6a          2      0         0
8934     b          1      0         3
8935     c          0      1         4 (case 6b makes this case unneccesary)
8936     d          1      1         1 (case 6a makes this case unnecessary)
8937     e          0      2         2 (case 6a makes this case unnecessary)
8938     f          0      3         0 (case 6a makes this case unnecessary)
8939    7a          1      0         4
8940     b          2      0         1
8941     c          1      1         2 (case 7b makes this case unnecessary)
8942     d          0      1         5 (case 7a makes this case unnecessary)
8943     e          0      2         3 (case 7b makes this case unnecessary)
8944     f          0      3         1 (case 7b makes this case unnecessary)
8945     g          1      2         1 (case 7b makes this case unnecessary)
8946 */
8947
8948 static long
8949 bytes_to_stretch (fragS *this_frag,
8950                   int wide_nops,
8951                   int narrow_nops,
8952                   int num_widens,
8953                   int desired_diff)
8954 {
8955   int bytes_short = desired_diff - num_widens;
8956
8957   assert (desired_diff >= 0 && desired_diff < 8);
8958   if (desired_diff == 0)
8959     return 0;
8960
8961   assert (wide_nops > 0 || num_widens > 0);
8962
8963   /* Always prefer widening to NOP-filling.  */
8964   if (bytes_short < 0)
8965     {
8966       /* There are enough RELAX_NARROW frags after this one
8967          to align the target without widening this frag in any way.  */
8968       return 0;
8969     }
8970
8971   if (bytes_short == 0)
8972     {
8973       /* Widen every narrow between here and the align target
8974          and the align target will be properly aligned.  */
8975       if (this_frag->fr_subtype == RELAX_FILL_NOP)
8976         return 0;
8977       else
8978         return 1;
8979     }
8980
8981   /* From here we will need at least one NOP to get an alignment.
8982      However, we may not be able to align at all, in which case,
8983      don't widen.  */
8984   if (this_frag->fr_subtype == RELAX_FILL_NOP)
8985     {
8986       switch (desired_diff)
8987         {
8988         case 1:
8989           return 0;
8990         case 2:
8991           if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1)
8992             return 2; /* case 2 */
8993           return 0;
8994         case 3:
8995           if (wide_nops > 1)
8996             return 0;
8997           else
8998             return 3; /* case 3a */
8999         case 4:
9000           if (num_widens >= 1 && wide_nops == 1)
9001             return 3; /* case 4a */
9002           if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2)
9003             return 2; /* case 4b */
9004           return 0;
9005         case 5:
9006           if (num_widens >= 2 && wide_nops == 1)
9007             return 3; /* case 5a */
9008           /* We will need two nops.  Are there enough nops
9009              between here and the align target?  */
9010           if (wide_nops < 2 || narrow_nops == 0)
9011             return 0;
9012           /* Are there other nops closer that can serve instead?  */
9013           if (wide_nops > 2 && narrow_nops > 1)
9014             return 0;
9015           /* Take the density one first, because there might not be
9016              another density one available.  */
9017           if (!this_frag->tc_frag_data.is_no_density)
9018             return 2; /* case 5b narrow */
9019           else
9020             return 3; /* case 5b wide */
9021           return 0;
9022         case 6:
9023           if (wide_nops == 2)
9024             return 3; /* case 6a */
9025           else if (num_widens >= 3 && wide_nops == 1)
9026             return 3; /* case 6b */
9027           return 0;
9028         case 7:
9029           if (wide_nops == 1 && num_widens >= 4)
9030             return 3; /* case 7a */
9031           else if (wide_nops == 2 && num_widens >= 1)
9032             return 3; /* case 7b */
9033           return 0;
9034         default:
9035           assert (0);
9036         }
9037     }
9038   else
9039     {
9040       /* We will need a NOP no matter what, but should we widen
9041          this instruction to help?
9042
9043          This is a RELAX_FRAG_NARROW frag.  */
9044       switch (desired_diff)
9045         {
9046         case 1:
9047           assert (0);
9048           return 0;
9049         case 2:
9050         case 3:
9051           return 0;
9052         case 4:
9053           if (wide_nops >= 1 && num_widens == 1)
9054             return 1; /* case 4a */
9055           return 0;
9056         case 5:
9057           if (wide_nops >= 1 && num_widens == 2)
9058             return 1; /* case 5a */
9059           return 0;
9060         case 6:
9061           if (wide_nops >= 2)
9062             return 0; /* case 6a */
9063           else if (wide_nops >= 1 && num_widens == 3)
9064             return 1; /* case 6b */
9065           return 0;
9066         case 7:
9067           if (wide_nops >= 1 && num_widens == 4)
9068             return 1; /* case 7a */
9069           else if (wide_nops >= 2 && num_widens == 1)
9070             return 1; /* case 7b */
9071           return 0;
9072         default:
9073           assert (0);
9074           return 0;
9075         }
9076     }
9077   assert (0);
9078   return 0;
9079 }
9080
9081
9082 static long
9083 relax_frag_immed (segT segP,
9084                   fragS *fragP,
9085                   long stretch,
9086                   int min_steps,
9087                   xtensa_format fmt,
9088                   int slot,
9089                   int *stretched_p,
9090                   bfd_boolean estimate_only)
9091 {
9092   TInsn tinsn;
9093   vliw_insn orig_vinsn;
9094   int old_size;
9095   bfd_boolean negatable_branch = FALSE;
9096   bfd_boolean branch_jmp_to_next = FALSE;
9097   bfd_boolean wide_insn = FALSE;
9098   xtensa_isa isa = xtensa_default_isa;
9099   IStack istack;
9100   offsetT frag_offset;
9101   int num_steps;
9102   fragS *lit_fragP;
9103   int num_text_bytes, num_literal_bytes;
9104   int literal_diff, total_text_diff, this_text_diff, first;
9105
9106   assert (fragP->fr_opcode != NULL);
9107
9108   xg_init_vinsn (&orig_vinsn);
9109   vinsn_from_chars (&orig_vinsn, fragP->fr_opcode);
9110   if (xtensa_format_num_slots (isa, fmt) > 1)
9111     wide_insn = TRUE;
9112
9113   tinsn = orig_vinsn.slots[slot];
9114   tinsn_immed_from_frag (&tinsn, fragP, slot);
9115
9116   if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode))
9117     return 0;
9118
9119   if (workaround_b_j_loop_end && !get_frag_is_no_transform (fragP))
9120     branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
9121
9122   negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
9123
9124   old_size = xtensa_format_length (isa, fmt);
9125
9126   /* Special case: replace a branch to the next instruction with a NOP.
9127      This is required to work around a hardware bug in T1040.0 and also
9128      serves as an optimization.  */
9129
9130   if (branch_jmp_to_next
9131       && ((old_size == 2) || (old_size == 3))
9132       && !next_frag_is_loop_target (fragP))
9133     return 0;
9134
9135   /* Here is the fun stuff: Get the immediate field from this
9136      instruction.  If it fits, we are done.  If not, find the next
9137      instruction sequence that fits.  */
9138
9139   frag_offset = fragP->fr_opcode - fragP->fr_literal;
9140   istack_init (&istack);
9141   num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
9142                                  min_steps, stretch);
9143   if (num_steps < min_steps)
9144     {
9145       as_fatal (_("internal error: relaxation failed"));
9146       return 0;
9147     }
9148
9149   if (num_steps > RELAX_IMMED_MAXSTEPS)
9150     {
9151       as_fatal (_("internal error: relaxation requires too many steps"));
9152       return 0;
9153     }
9154
9155   fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
9156
9157   /* Figure out the number of bytes needed.  */
9158   lit_fragP = 0;
9159   num_literal_bytes = get_num_stack_literal_bytes (&istack);
9160   literal_diff =
9161     num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
9162   first = 0;
9163   while (istack.insn[first].opcode == XTENSA_UNDEFINED)
9164     first++;
9165   num_text_bytes = get_num_stack_text_bytes (&istack);
9166   if (wide_insn)
9167     {
9168       num_text_bytes += old_size;
9169       if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
9170         num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
9171     }
9172   total_text_diff = num_text_bytes - old_size;
9173   this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
9174
9175   /* It MUST get larger.  If not, we could get an infinite loop.  */
9176   assert (num_text_bytes >= 0);
9177   assert (literal_diff >= 0);
9178   assert (total_text_diff >= 0);
9179
9180   fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
9181   fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
9182   assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
9183   assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
9184
9185   /* Find the associated expandable literal for this.  */
9186   if (literal_diff != 0)
9187     {
9188       lit_fragP = fragP->tc_frag_data.literal_frags[slot];
9189       if (lit_fragP)
9190         {
9191           assert (literal_diff == 4);
9192           lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
9193
9194           /* We expect that the literal section state has NOT been
9195              modified yet.  */
9196           assert (lit_fragP->fr_type == rs_machine_dependent
9197                   && lit_fragP->fr_subtype == RELAX_LITERAL);
9198           lit_fragP->fr_subtype = RELAX_LITERAL_NR;
9199
9200           /* We need to mark this section for another iteration
9201              of relaxation.  */
9202           (*stretched_p)++;
9203         }
9204     }
9205
9206   /* FIXME: When a negatable branch expands and then contracts in a
9207      subsequent pass, update_next_frag_state correctly updates the
9208      type of the frag to RELAX_MAYBE_UNREACHABLE, but it doesn't undo
9209      any expansion relax_frag_for_align may have expected it to.  For
9210      now, change back to only call it when the branch expands.  */
9211   if (negatable_branch && istack.ninsn > 1)
9212     update_next_frag_state (fragP, FALSE /* istack.ninsn > 1 */);
9213
9214   return this_text_diff;
9215 }
9216
9217 \f
9218 /* md_convert_frag Hook and Helper Functions.  */
9219
9220 static void convert_frag_align_next_opcode (fragS *);
9221 static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
9222 static void convert_frag_fill_nop (fragS *);
9223 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
9224
9225 void
9226 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
9227 {
9228   static xtensa_insnbuf vbuf = NULL;
9229   xtensa_isa isa = xtensa_default_isa;
9230   int slot;
9231   int num_slots;
9232   xtensa_format fmt;
9233   char *file_name;
9234   int line;
9235
9236   as_where (&file_name, &line);
9237   new_logical_line (fragp->fr_file, fragp->fr_line);
9238
9239   switch (fragp->fr_subtype)
9240     {
9241     case RELAX_ALIGN_NEXT_OPCODE:
9242       /* Always convert.  */
9243       convert_frag_align_next_opcode (fragp);
9244       break;
9245
9246     case RELAX_DESIRE_ALIGN:
9247       /* Do nothing.  If not aligned already, too bad.  */
9248       break;
9249
9250     case RELAX_LITERAL:
9251     case RELAX_LITERAL_FINAL:
9252       break;
9253
9254     case RELAX_SLOTS:
9255       if (vbuf == NULL)
9256         vbuf = xtensa_insnbuf_alloc (isa);
9257
9258       xtensa_insnbuf_from_chars (isa, vbuf, fragp->fr_opcode, 0);
9259       fmt = xtensa_format_decode (isa, vbuf);
9260       num_slots = xtensa_format_num_slots (isa, fmt);
9261
9262       for (slot = 0; slot < num_slots; slot++)
9263         {
9264           switch (fragp->tc_frag_data.slot_subtypes[slot])
9265             {
9266             case RELAX_NARROW:
9267               convert_frag_narrow (sec, fragp, fmt, slot);
9268               break;
9269
9270             case RELAX_IMMED:
9271             case RELAX_IMMED_STEP1:
9272             case RELAX_IMMED_STEP2:
9273               /* Place the immediate.  */
9274               convert_frag_immed
9275                 (sec, fragp,
9276                  fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9277                  fmt, slot);
9278               break;
9279
9280             default:
9281               /* This is OK because some slots could have
9282                  relaxations and others have none.  */
9283               break;
9284             }
9285         }
9286       break;
9287
9288     case RELAX_UNREACHABLE:
9289       memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
9290       fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
9291       fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
9292       frag_wane (fragp);
9293       break;
9294
9295     case RELAX_MAYBE_UNREACHABLE:
9296     case RELAX_MAYBE_DESIRE_ALIGN:
9297       frag_wane (fragp);
9298       break;
9299
9300     case RELAX_FILL_NOP:
9301       convert_frag_fill_nop (fragp);
9302       break;
9303
9304     case RELAX_LITERAL_NR:
9305       if (use_literal_section)
9306         {
9307           /* This should have been handled during relaxation.  When
9308              relaxing a code segment, literals sometimes need to be
9309              added to the corresponding literal segment.  If that
9310              literal segment has already been relaxed, then we end up
9311              in this situation.  Marking the literal segments as data
9312              would make this happen less often (since GAS always relaxes
9313              code before data), but we could still get into trouble if
9314              there are instructions in a segment that is not marked as
9315              containing code.  Until we can implement a better solution,
9316              cheat and adjust the addresses of all the following frags.
9317              This could break subsequent alignments, but the linker's
9318              literal coalescing will do that anyway.  */
9319
9320           fragS *f;
9321           fragp->fr_subtype = RELAX_LITERAL_FINAL;
9322           assert (fragp->tc_frag_data.unreported_expansion == 4);
9323           memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
9324           fragp->fr_var -= 4;
9325           fragp->fr_fix += 4;
9326           for (f = fragp->fr_next; f; f = f->fr_next)
9327             f->fr_address += 4;
9328         }
9329       else
9330         as_bad (_("invalid relaxation fragment result"));
9331       break;
9332     }
9333
9334   fragp->fr_var = 0;
9335   new_logical_line (file_name, line);
9336 }
9337
9338
9339 static void
9340 convert_frag_align_next_opcode (fragS *fragp)
9341 {
9342   char *nop_buf;                /* Location for Writing.  */
9343   size_t i;
9344
9345   bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
9346   addressT aligned_address;
9347   size_t fill_size, nop_count;
9348
9349   aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
9350                                               fragp->fr_fix);
9351   fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
9352   nop_count = get_text_align_nop_count (fill_size, use_no_density);
9353   nop_buf = fragp->fr_literal + fragp->fr_fix;
9354
9355   for (i = 0; i < nop_count; i++)
9356     {
9357       size_t nop_size;
9358       nop_size = get_text_align_nth_nop_size (fill_size, i, use_no_density);
9359
9360       assemble_nop (nop_size, nop_buf);
9361       nop_buf += nop_size;
9362     }
9363
9364   fragp->fr_fix += fill_size;
9365   fragp->fr_var -= fill_size;
9366 }
9367
9368
9369 static void
9370 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
9371 {
9372   TInsn tinsn, single_target;
9373   xtensa_format single_fmt;
9374   int size, old_size, diff, error_val;
9375   offsetT frag_offset;
9376
9377   assert (slot == 0);
9378   tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
9379
9380   if (xtensa_opcode_is_branch (xtensa_default_isa, tinsn.opcode) == 1)
9381     {
9382       assert (fragP->tc_frag_data.text_expansion[0] == 1
9383               || fragP->tc_frag_data.text_expansion[0] == 0);
9384       convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
9385                           fmt, slot);
9386       return;
9387     }
9388
9389   if (fragP->tc_frag_data.text_expansion[0] == 0)
9390     {
9391       /* No conversion.  */
9392       fragP->fr_var = 0;
9393       return;
9394     }
9395
9396   assert (fragP->fr_opcode != NULL);
9397
9398   /* Frags in this relaxation state should only contain
9399      single instruction bundles.  */
9400   tinsn_immed_from_frag (&tinsn, fragP, 0);
9401
9402   /* Just convert it to a wide form....  */
9403   size = 0;
9404   old_size = xg_get_single_size (tinsn.opcode);
9405
9406   tinsn_init (&single_target);
9407   frag_offset = fragP->fr_opcode - fragP->fr_literal;
9408
9409   error_val = xg_expand_narrow (&single_target, &tinsn);
9410   if (error_val)
9411     {
9412       as_bad (_("unable to widen instruction"));
9413       return;
9414     }
9415
9416   size = xg_get_single_size (single_target.opcode);
9417   single_fmt = xg_get_single_format (single_target.opcode);
9418
9419   xg_emit_insn_to_buf (&single_target, single_fmt, fragP->fr_opcode,
9420                        fragP, frag_offset, TRUE);
9421
9422   diff = size - old_size;
9423   assert (diff >= 0);
9424   assert (diff <= fragP->fr_var);
9425   fragP->fr_var -= diff;
9426   fragP->fr_fix += diff;
9427
9428   /* clean it up */
9429   fragP->fr_var = 0;
9430 }
9431
9432
9433 static void
9434 convert_frag_fill_nop (fragS *fragP)
9435 {
9436   char *loc = &fragP->fr_literal[fragP->fr_fix];
9437   int size = fragP->tc_frag_data.text_expansion[0];
9438   assert ((unsigned) size == (fragP->fr_next->fr_address
9439                               - fragP->fr_address - fragP->fr_fix));
9440   if (size == 0)
9441     {
9442       /* No conversion.  */
9443       fragP->fr_var = 0;
9444       return;
9445     }
9446   assemble_nop (size, loc);
9447   fragP->tc_frag_data.is_insn = TRUE;
9448   fragP->fr_var -= size;
9449   fragP->fr_fix += size;
9450   frag_wane (fragP);
9451 }
9452
9453
9454 static fixS *fix_new_exp_in_seg
9455   (segT, subsegT, fragS *, int, int, expressionS *, int,
9456    bfd_reloc_code_real_type);
9457 static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *);
9458
9459 static void
9460 convert_frag_immed (segT segP,
9461                     fragS *fragP,
9462                     int min_steps,
9463                     xtensa_format fmt,
9464                     int slot)
9465 {
9466   char *immed_instr = fragP->fr_opcode;
9467   TInsn orig_tinsn;
9468   bfd_boolean expanded = FALSE;
9469   bfd_boolean branch_jmp_to_next = FALSE;
9470   char *fr_opcode = fragP->fr_opcode;
9471   vliw_insn orig_vinsn;
9472   xtensa_isa isa = xtensa_default_isa;
9473   bfd_boolean wide_insn = FALSE;
9474   int bytes;
9475   bfd_boolean is_loop;
9476
9477   assert (fr_opcode != NULL);
9478
9479   xg_init_vinsn (&orig_vinsn);
9480
9481   vinsn_from_chars (&orig_vinsn, fr_opcode);
9482   if (xtensa_format_num_slots (isa, fmt) > 1)
9483     wide_insn = TRUE;
9484
9485   orig_tinsn = orig_vinsn.slots[slot];
9486   tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
9487
9488   is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
9489
9490   if (workaround_b_j_loop_end && !get_frag_is_no_transform (fragP))
9491     branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
9492
9493   if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
9494     {
9495       /* Conversion just inserts a NOP and marks the fix as completed.  */
9496       bytes = xtensa_format_length (isa, fmt);
9497       if (bytes >= 4)
9498         {
9499           orig_vinsn.slots[slot].opcode =
9500             xtensa_format_slot_nop_opcode (isa, orig_vinsn.format, slot);
9501           orig_vinsn.slots[slot].ntok = 0;
9502         }
9503       else
9504         {
9505           bytes += fragP->tc_frag_data.text_expansion[0];
9506           assert (bytes == 2 || bytes == 3);
9507           build_nop (&orig_vinsn.slots[0], bytes);
9508           fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
9509         }
9510       vinsn_to_insnbuf (&orig_vinsn, fr_opcode, frag_now, FALSE);
9511       xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf, fr_opcode, 0);
9512       fragP->fr_var = 0;
9513     }
9514   else if (!orig_tinsn.is_specific_opcode)
9515     {
9516       /* Here is the fun stuff:  Get the immediate field from this
9517          instruction.  If it fits, we're done.  If not, find the next
9518          instruction sequence that fits.  */
9519
9520       IStack istack;
9521       int i;
9522       symbolS *lit_sym = NULL;
9523       int total_size = 0;
9524       int target_offset = 0;
9525       int old_size;
9526       int diff;
9527       symbolS *gen_label = NULL;
9528       offsetT frag_offset;
9529       bfd_boolean first = TRUE;
9530       bfd_boolean last_is_jump;
9531
9532       /* It does not fit.  Find something that does and
9533          convert immediately.  */
9534       frag_offset = fr_opcode - fragP->fr_literal;
9535       istack_init (&istack);
9536       xg_assembly_relax (&istack, &orig_tinsn,
9537                          segP, fragP, frag_offset, min_steps, 0);
9538
9539       old_size = xtensa_format_length (isa, fmt);
9540
9541       /* Assemble this right inline.  */
9542
9543       /* First, create the mapping from a label name to the REAL label.  */
9544       target_offset = 0;
9545       for (i = 0; i < istack.ninsn; i++)
9546         {
9547           TInsn *tinsn = &istack.insn[i];
9548           fragS *lit_frag;
9549
9550           switch (tinsn->insn_type)
9551             {
9552             case ITYPE_LITERAL:
9553               if (lit_sym != NULL)
9554                 as_bad (_("multiple literals in expansion"));
9555               /* First find the appropriate space in the literal pool.  */
9556               lit_frag = fragP->tc_frag_data.literal_frags[slot];
9557               if (lit_frag == NULL)
9558                 as_bad (_("no registered fragment for literal"));
9559               if (tinsn->ntok != 1)
9560                 as_bad (_("number of literal tokens != 1"));
9561
9562               /* Set the literal symbol and add a fixup.  */
9563               lit_sym = lit_frag->fr_symbol;
9564               break;
9565
9566             case ITYPE_LABEL:
9567               if (align_targets && !is_loop)
9568                 {
9569                   fragS *unreach = fragP->fr_next;
9570                   while (!(unreach->fr_type == rs_machine_dependent
9571                            && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9572                                || unreach->fr_subtype == RELAX_UNREACHABLE)))
9573                     {
9574                       unreach = unreach->fr_next;
9575                     }
9576
9577                   assert (unreach->fr_type == rs_machine_dependent
9578                           && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9579                               || unreach->fr_subtype == RELAX_UNREACHABLE));
9580
9581                   target_offset += unreach->tc_frag_data.text_expansion[0];
9582                 }
9583               assert (gen_label == NULL);
9584               gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
9585                                       fr_opcode - fragP->fr_literal
9586                                       + target_offset, fragP);
9587               break;
9588
9589             case ITYPE_INSN:
9590               if (first && wide_insn)
9591                 {
9592                   target_offset += xtensa_format_length (isa, fmt);
9593                   first = FALSE;
9594                   if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9595                     target_offset += xg_get_single_size (tinsn->opcode);
9596                 }
9597               else
9598                 target_offset += xg_get_single_size (tinsn->opcode);
9599               break;
9600             }
9601         }
9602
9603       total_size = 0;
9604       first = TRUE;
9605       last_is_jump = FALSE;
9606       for (i = 0; i < istack.ninsn; i++)
9607         {
9608           TInsn *tinsn = &istack.insn[i];
9609           fragS *lit_frag;
9610           int size;
9611           segT target_seg;
9612           bfd_reloc_code_real_type reloc_type;
9613
9614           switch (tinsn->insn_type)
9615             {
9616             case ITYPE_LITERAL:
9617               lit_frag = fragP->tc_frag_data.literal_frags[slot];
9618               /* Already checked.  */
9619               assert (lit_frag != NULL);
9620               assert (lit_sym != NULL);
9621               assert (tinsn->ntok == 1);
9622               /* Add a fixup.  */
9623               target_seg = S_GET_SEGMENT (lit_sym);
9624               assert (target_seg);
9625               if (tinsn->tok[0].X_op == O_pltrel)
9626                 reloc_type = BFD_RELOC_XTENSA_PLT;
9627               else
9628                 reloc_type = BFD_RELOC_32;
9629               fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
9630                                   &tinsn->tok[0], FALSE, reloc_type);
9631               break;
9632
9633             case ITYPE_LABEL:
9634               break;
9635
9636             case ITYPE_INSN:
9637               xg_resolve_labels (tinsn, gen_label);
9638               xg_resolve_literals (tinsn, lit_sym);
9639               if (wide_insn && first)
9640                 {
9641                   first = FALSE;
9642                   if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9643                     {
9644                       tinsn->record_fix = TRUE;
9645                       orig_vinsn.slots[slot] = *tinsn;
9646                     }
9647                   else
9648                     {
9649                       orig_vinsn.slots[slot].opcode =
9650                         xtensa_format_slot_nop_opcode (isa, fmt, slot);
9651                       orig_vinsn.slots[slot].ntok = 0;
9652                       orig_vinsn.slots[slot].record_fix = FALSE;
9653                     }
9654                   vinsn_to_insnbuf (&orig_vinsn, immed_instr, fragP, TRUE);
9655                   xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf,
9656                                            immed_instr, 0);
9657                   fragP->tc_frag_data.is_insn = TRUE;
9658                   size = xtensa_format_length (isa, fmt);
9659                   if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9660                     {
9661                       xtensa_format single_fmt =
9662                         xg_get_single_format (tinsn->opcode);
9663
9664                       xg_emit_insn_to_buf
9665                         (tinsn, single_fmt, immed_instr + size, fragP,
9666                          immed_instr - fragP->fr_literal + size, TRUE);
9667                       size += xg_get_single_size (tinsn->opcode);
9668                     }
9669                 }
9670               else
9671                 {
9672                   xtensa_format single_format;
9673                   size = xg_get_single_size (tinsn->opcode);
9674                   single_format = xg_get_single_format (tinsn->opcode);
9675                   xg_emit_insn_to_buf (tinsn, single_format, immed_instr,
9676                                        fragP,
9677                                        immed_instr - fragP->fr_literal, TRUE);
9678 #if 0
9679                   /* Code to recognize branch-around expansion
9680                      so the fragment is properly marked as ending in a
9681                      jump. */
9682                   if ((((i == istack.ninsn - 2)
9683                         && (istack.insn[istack.ninsn-1].insn_type
9684                             == ITYPE_LABEL))
9685                        || i == istack.ninsn -1)
9686                       && xtensa_opcode_is_jump (xtensa_default_isa,
9687                                                 tinsn->opcode) == 1
9688                       && fragP->fr_next != NULL
9689                       && ! fragP->fr_next->tc_frag_data.is_unreachable)
9690                     {
9691                       /* Create a new unreachable frag of zero size.  */
9692                       size_t frag_size = sizeof (fragS);
9693                       fragS *new_fragP = (fragS *) xmalloc (frag_size);
9694                       memset (new_fragP, 0, frag_size);
9695                       new_fragP->fr_address = fragP->fr_next->fr_address;
9696                       new_fragP->fr_next = fragP->fr_next;
9697                       new_fragP->fr_fix = 0;
9698                       new_fragP->fr_var = 0;
9699                       new_fragP->fr_type = rs_fill;
9700                       new_fragP->tc_frag_data.is_unreachable = TRUE;
9701                       /* The rest are zeros....  */
9702                       /* Link it in to the chain.  */
9703                       fragP->fr_next = new_fragP;
9704                     }
9705 #endif
9706                 }
9707               immed_instr += size;
9708               total_size += size;
9709               break;
9710             }
9711         }
9712
9713       diff = total_size - old_size;
9714       assert (diff >= 0);
9715       if (diff != 0)
9716         expanded = TRUE;
9717       assert (diff <= fragP->fr_var);
9718       fragP->fr_var -= diff;
9719       fragP->fr_fix += diff;
9720     }
9721
9722   /* Clean it up.  */
9723   xg_free_vinsn (&orig_vinsn);
9724
9725   /* Check for undefined immediates in LOOP instructions.  */
9726   if (is_loop)
9727     {
9728       symbolS *sym;
9729       sym = orig_tinsn.tok[1].X_add_symbol;
9730       if (sym != NULL && !S_IS_DEFINED (sym))
9731         {
9732           as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9733           return;
9734         }
9735       sym = orig_tinsn.tok[1].X_op_symbol;
9736       if (sym != NULL && !S_IS_DEFINED (sym))
9737         {
9738           as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9739           return;
9740         }
9741     }
9742
9743   if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
9744     convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
9745
9746   if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
9747     {
9748       /* Add an expansion note on the expanded instruction.  */
9749       fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
9750                           &orig_tinsn.tok[0], TRUE,
9751                           BFD_RELOC_XTENSA_ASM_EXPAND);
9752     }
9753 }
9754
9755
9756 /* Add a new fix expression into the desired segment.  We have to
9757    switch to that segment to do this.  */
9758
9759 static fixS *
9760 fix_new_exp_in_seg (segT new_seg,
9761                     subsegT new_subseg,
9762                     fragS *frag,
9763                     int where,
9764                     int size,
9765                     expressionS *exp,
9766                     int pcrel,
9767                     bfd_reloc_code_real_type r_type)
9768 {
9769   fixS *new_fix;
9770   segT seg = now_seg;
9771   subsegT subseg = now_subseg;
9772
9773   assert (new_seg != 0);
9774   subseg_set (new_seg, new_subseg);
9775
9776   new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
9777   subseg_set (seg, subseg);
9778   return new_fix;
9779 }
9780
9781
9782 /* Relax a loop instruction so that it can span loop >256 bytes.
9783
9784                   loop    as, .L1
9785           .L0:
9786                   rsr     as, LEND
9787                   wsr     as, LBEG
9788                   addi    as, as, lo8 (label-.L1)
9789                   addmi   as, as, mid8 (label-.L1)
9790                   wsr     as, LEND
9791                   isync
9792                   rsr     as, LCOUNT
9793                   addi    as, as, 1
9794           .L1:
9795                   <<body>>
9796           label:
9797 */
9798
9799 static offsetT get_expression_value (segT, expressionS *);
9800
9801 static void
9802 convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
9803 {
9804   TInsn loop_insn;
9805   TInsn addi_insn;
9806   TInsn addmi_insn;
9807   unsigned long target;
9808   static xtensa_insnbuf insnbuf = NULL;
9809   unsigned int loop_length, loop_length_hi, loop_length_lo;
9810   xtensa_isa isa = xtensa_default_isa;
9811   addressT loop_offset;
9812   addressT addi_offset = 9;
9813   addressT addmi_offset = 12;
9814   fragS *next_fragP;
9815   size_t target_count;
9816
9817   if (!insnbuf)
9818     insnbuf = xtensa_insnbuf_alloc (isa);
9819
9820   /* Get the loop offset.  */
9821   loop_offset = get_expanded_loop_offset (tinsn->opcode);
9822
9823   /* Validate that there really is a LOOP at the loop_offset.  Because
9824      loops are not bundleable, we can assume that the instruction will be
9825      in slot 0.  */
9826   tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
9827   tinsn_immed_from_frag (&loop_insn, fragP, 0);
9828
9829   assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
9830   addi_offset += loop_offset;
9831   addmi_offset += loop_offset;
9832
9833   assert (tinsn->ntok == 2);
9834   target = get_expression_value (segP, &tinsn->tok[1]);
9835
9836   know (symbolP);
9837   know (symbolP->sy_frag);
9838   know (!(S_GET_SEGMENT (symbolP) == absolute_section)
9839         || symbol_get_frag (symbolP) == &zero_address_frag);
9840
9841   loop_length = target - (fragP->fr_address + fragP->fr_fix);
9842   loop_length_hi = loop_length & ~0x0ff;
9843   loop_length_lo = loop_length & 0x0ff;
9844   if (loop_length_lo >= 128)
9845     {
9846       loop_length_lo -= 256;
9847       loop_length_hi += 256;
9848     }
9849
9850   /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9851      32512.  If the loop is larger than that, then we just fail.  */
9852   if (loop_length_hi > 32512)
9853     as_bad_where (fragP->fr_file, fragP->fr_line,
9854                   _("loop too long for LOOP instruction"));
9855
9856   tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
9857   assert (addi_insn.opcode == xtensa_addi_opcode);
9858
9859   tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
9860   assert (addmi_insn.opcode == xtensa_addmi_opcode);
9861
9862   set_expr_const (&addi_insn.tok[2], loop_length_lo);
9863   tinsn_to_insnbuf (&addi_insn, insnbuf);
9864
9865   fragP->tc_frag_data.is_insn = TRUE;
9866   xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addi_offset, 0);
9867
9868   set_expr_const (&addmi_insn.tok[2], loop_length_hi);
9869   tinsn_to_insnbuf (&addmi_insn, insnbuf);
9870   xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addmi_offset, 0);
9871
9872   /* Walk through all of the frags from here to the loop end
9873      and mark them as no_transform to keep them from being modified
9874      by the linker.  If we ever have a relocation for the
9875      addi/addmi of the difference of two symbols we can remove this.  */
9876
9877   target_count = 0;
9878   for (next_fragP = fragP; next_fragP != NULL;
9879        next_fragP = next_fragP->fr_next)
9880     {
9881       set_frag_is_no_transform (next_fragP, TRUE);
9882       if (next_fragP->tc_frag_data.is_loop_target)
9883         target_count++;
9884       if (target_count == 2)
9885         break;
9886     }
9887 }
9888
9889
9890 static offsetT
9891 get_expression_value (segT segP, expressionS *exp)
9892 {
9893   if (exp->X_op == O_constant)
9894     return exp->X_add_number;
9895   if (exp->X_op == O_symbol)
9896     {
9897       /* Find the fragment.  */
9898       symbolS *sym = exp->X_add_symbol;
9899
9900       assert (S_GET_SEGMENT (sym) == segP
9901               || S_GET_SEGMENT (sym) == absolute_section);
9902
9903       return (S_GET_VALUE (sym) + exp->X_add_number);
9904     }
9905   as_bad (_("invalid expression evaluation type %d"), exp->X_op);
9906   return 0;
9907 }
9908
9909 \f
9910 static subseg_map *sseg_map = NULL;
9911
9912 static subseg_map *
9913 get_subseg_info (segT seg, subsegT subseg)
9914 {
9915   subseg_map *subseg_e;
9916
9917   for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
9918     {
9919       if (seg == subseg_e->seg && subseg == subseg_e->subseg)
9920         return subseg_e;
9921     }
9922
9923   subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map));
9924   memset (subseg_e, 0, sizeof (subseg_map));
9925   subseg_e->seg = seg;
9926   subseg_e->subseg = subseg;
9927   subseg_e->flags = 0;
9928   /* Start off considering every branch target very important.  */
9929   subseg_e->cur_target_freq = 1.0;
9930   subseg_e->cur_total_freq = 1.0;
9931   subseg_e->next = sseg_map;
9932   sseg_map = subseg_e;
9933
9934   return subseg_e;
9935 }
9936
9937
9938 static unsigned
9939 get_last_insn_flags (segT seg, subsegT subseg)
9940 {
9941   subseg_map *subseg_e = get_subseg_info (seg, subseg);
9942   return subseg_e->flags;
9943 }
9944
9945
9946 static void
9947 set_last_insn_flags (segT seg,
9948                      subsegT subseg,
9949                      unsigned fl,
9950                      bfd_boolean val)
9951 {
9952   subseg_map *subseg_e = get_subseg_info (seg, subseg);
9953   if (val)
9954     subseg_e->flags |= fl;
9955   else
9956     subseg_e->flags &= ~fl;
9957 }
9958
9959 \f
9960 /* Segment Lists and emit_state Stuff.  */
9961
9962 /* Remove the segment from the global sections list.  */
9963
9964 static void
9965 xtensa_remove_section (segT sec)
9966 {
9967   /* Handle brain-dead bfd_section_list_remove macro, which
9968      expect the address of the prior section's "next" field, not
9969      just the address of the section to remove.  */
9970
9971   segT *ps_next_ptr = &stdoutput->sections;
9972   while (*ps_next_ptr != sec && *ps_next_ptr != NULL)
9973     ps_next_ptr = &(*ps_next_ptr)->next;
9974
9975   assert (*ps_next_ptr != NULL);
9976
9977   bfd_section_list_remove (stdoutput, ps_next_ptr);
9978 }
9979
9980
9981 static void
9982 xtensa_insert_section (segT after_sec, segT sec)
9983 {
9984   segT *after_sec_next;
9985   if (after_sec == NULL)
9986     after_sec_next = &stdoutput->sections;
9987   else
9988     after_sec_next = &after_sec->next;
9989
9990   bfd_section_list_insert (stdoutput, after_sec_next, sec);
9991 }
9992
9993
9994 static void
9995 xtensa_move_seg_list_to_beginning (seg_list *head)
9996 {
9997   head = head->next;
9998   while (head)
9999     {
10000       segT literal_section = head->seg;
10001
10002       /* Move the literal section to the front of the section list.  */
10003       assert (literal_section);
10004       xtensa_remove_section (literal_section);
10005       xtensa_insert_section (NULL, literal_section);
10006
10007       head = head->next;
10008     }
10009 }
10010
10011
10012 static void mark_literal_frags (seg_list *);
10013
10014 static void
10015 xtensa_move_literals (void)
10016 {
10017   seg_list *segment;
10018   frchainS *frchain_from, *frchain_to;
10019   fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after;
10020   fragS **frag_splice;
10021   emit_state state;
10022   segT dest_seg;
10023   fixS *fix, *next_fix, **fix_splice;
10024   sym_list *lit;
10025
10026   mark_literal_frags (literal_head->next);
10027   mark_literal_frags (init_literal_head->next);
10028   mark_literal_frags (fini_literal_head->next);
10029
10030   if (use_literal_section)
10031     return;
10032
10033   segment = literal_head->next;
10034   while (segment)
10035     {
10036       frchain_from = seg_info (segment->seg)->frchainP;
10037       search_frag = frchain_from->frch_root;
10038       literal_pool = NULL;
10039       frchain_to = NULL;
10040       frag_splice = &(frchain_from->frch_root);
10041
10042       while (!search_frag->tc_frag_data.literal_frag)
10043         {
10044           assert (search_frag->fr_fix == 0
10045                   || search_frag->fr_type == rs_align);
10046           search_frag = search_frag->fr_next;
10047         }
10048
10049       assert (search_frag->tc_frag_data.literal_frag->fr_subtype
10050               == RELAX_LITERAL_POOL_BEGIN);
10051       xtensa_switch_section_emit_state (&state, segment->seg, 0);
10052
10053       /* Make sure that all the frags in this series are closed, and
10054          that there is at least one left over of zero-size.  This
10055          prevents us from making a segment with an frchain without any
10056          frags in it.  */
10057       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
10058       xtensa_set_frag_assembly_state (frag_now);
10059       last_frag = frag_now;
10060       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
10061       xtensa_set_frag_assembly_state (frag_now);
10062
10063       while (search_frag != frag_now)
10064         {
10065           next_frag = search_frag->fr_next;
10066
10067           /* First, move the frag out of the literal section and
10068              to the appropriate place.  */
10069           if (search_frag->tc_frag_data.literal_frag)
10070             {
10071               literal_pool = search_frag->tc_frag_data.literal_frag;
10072               assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
10073               /* Note that we set this fr_var to be a fix
10074                  chain when we created the literal pool location
10075                  as RELAX_LITERAL_POOL_BEGIN.  */
10076               frchain_to = (frchainS *) literal_pool->fr_var;
10077             }
10078           insert_after = literal_pool;
10079
10080           while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END)
10081             insert_after = insert_after->fr_next;
10082
10083           dest_seg = (segT) insert_after->fr_next->fr_var;
10084
10085           *frag_splice = next_frag;
10086           search_frag->fr_next = insert_after->fr_next;
10087           insert_after->fr_next = search_frag;
10088           search_frag->tc_frag_data.lit_seg = dest_seg;
10089
10090           /* Now move any fixups associated with this frag to the
10091              right section.  */
10092           fix = frchain_from->fix_root;
10093           fix_splice = &(frchain_from->fix_root);
10094           while (fix)
10095             {
10096               next_fix = fix->fx_next;
10097               if (fix->fx_frag == search_frag)
10098                 {
10099                   *fix_splice = next_fix;
10100                   fix->fx_next = frchain_to->fix_root;
10101                   frchain_to->fix_root = fix;
10102                   if (frchain_to->fix_tail == NULL)
10103                     frchain_to->fix_tail = fix;
10104                 }
10105               else
10106                 fix_splice = &(fix->fx_next);
10107               fix = next_fix;
10108             }
10109           search_frag = next_frag;
10110         }
10111
10112       if (frchain_from->fix_root != NULL)
10113         {
10114           frchain_from = seg_info (segment->seg)->frchainP;
10115           as_warn (_("fixes not all moved from %s"), segment->seg->name);
10116
10117           assert (frchain_from->fix_root == NULL);
10118         }
10119       frchain_from->fix_tail = NULL;
10120       xtensa_restore_emit_state (&state);
10121       segment = segment->next;
10122     }
10123
10124   /* Now fix up the SEGMENT value for all the literal symbols.  */
10125   for (lit = literal_syms; lit; lit = lit->next)
10126     {
10127       symbolS *lit_sym = lit->sym;
10128       segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
10129       if (dest_seg)
10130         S_SET_SEGMENT (lit_sym, dest_seg);
10131     }
10132 }
10133
10134
10135 /* Walk over all the frags for segments in a list and mark them as
10136    containing literals.  As clunky as this is, we can't rely on frag_var
10137    and frag_variant to get called in all situations.  */
10138
10139 static void
10140 mark_literal_frags (seg_list *segment)
10141 {
10142   frchainS *frchain_from;
10143   fragS *search_frag;
10144
10145   while (segment)
10146     {
10147       frchain_from = seg_info (segment->seg)->frchainP;
10148       search_frag = frchain_from->frch_root;
10149       while (search_frag)
10150         {
10151           search_frag->tc_frag_data.is_literal = TRUE;
10152           search_frag = search_frag->fr_next;
10153         }
10154       segment = segment->next;
10155     }
10156 }
10157
10158
10159 static void
10160 xtensa_reorder_seg_list (seg_list *head, segT after)
10161 {
10162   /* Move all of the sections in the section list to come
10163      after "after" in the gnu segment list.  */
10164
10165   head = head->next;
10166   while (head)
10167     {
10168       segT literal_section = head->seg;
10169
10170       /* Move the literal section after "after".  */
10171       assert (literal_section);
10172       if (literal_section != after)
10173         {
10174           xtensa_remove_section (literal_section);
10175           xtensa_insert_section (after, literal_section);
10176         }
10177
10178       head = head->next;
10179     }
10180 }
10181
10182
10183 /* Push all the literal segments to the end of the gnu list.  */
10184
10185 static segT get_last_sec (void);
10186
10187 static void
10188 xtensa_reorder_segments (void)
10189 {
10190   segT sec;
10191   segT last_sec;
10192   int old_count = 0;
10193   int new_count = 0;
10194
10195   for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10196     old_count++;
10197
10198   /* Now that we have the last section, push all the literal
10199      sections to the end.  */
10200   last_sec = get_last_sec ();
10201   xtensa_reorder_seg_list (literal_head, last_sec);
10202   xtensa_reorder_seg_list (init_literal_head, last_sec);
10203   xtensa_reorder_seg_list (fini_literal_head, last_sec);
10204
10205   /* Now perform the final error check.  */
10206   for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10207     new_count++;
10208   assert (new_count == old_count);
10209 }
10210
10211
10212 static segT
10213 get_last_sec (void)
10214 {
10215   segT last_sec = stdoutput->sections;
10216   while (last_sec->next != NULL)
10217     last_sec = last_sec->next;
10218
10219   return last_sec;
10220 }
10221
10222
10223 /* Change the emit state (seg, subseg, and frag related stuff) to the
10224    correct location.  Return a emit_state which can be passed to
10225    xtensa_restore_emit_state to return to current fragment.  */
10226
10227 static void
10228 xtensa_switch_to_literal_fragment (emit_state *result)
10229 {
10230   if (directive_state[directive_absolute_literals])
10231     {
10232       cache_literal_section (0, default_lit_sections.lit4_seg_name,
10233                              &default_lit_sections.lit4_seg, FALSE);
10234       xtensa_switch_section_emit_state (result,
10235                                         default_lit_sections.lit4_seg, 0);
10236     }
10237   else
10238     xtensa_switch_to_non_abs_literal_fragment (result);
10239
10240   /* Do a 4-byte align here.  */
10241   frag_align (2, 0, 0);
10242   record_alignment (now_seg, 2);
10243 }
10244
10245
10246 static void
10247 xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
10248 {
10249   /* When we mark a literal pool location, we want to put a frag in
10250      the literal pool that points to it.  But to do that, we want to
10251      switch_to_literal_fragment.  But literal sections don't have
10252      literal pools, so their location is always null, so we would
10253      recurse forever.  This is kind of hacky, but it works.  */
10254
10255   static bfd_boolean recursive = FALSE;
10256   fragS *pool_location = get_literal_pool_location (now_seg);
10257   bfd_boolean is_init =
10258     (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
10259
10260   bfd_boolean is_fini =
10261     (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
10262
10263   if (pool_location == NULL
10264       && !use_literal_section
10265       && !recursive
10266       && !is_init && ! is_fini)
10267     {
10268       as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10269       recursive = TRUE;
10270       xtensa_mark_literal_pool_location ();
10271       recursive = FALSE;
10272     }
10273
10274   /* Special case: If we are in the ".fini" or ".init" section, then
10275      we will ALWAYS be generating to the ".fini.literal" and
10276      ".init.literal" sections.  */
10277
10278   if (is_init)
10279     {
10280       cache_literal_section (init_literal_head,
10281                              default_lit_sections.init_lit_seg_name,
10282                              &default_lit_sections.init_lit_seg, TRUE);
10283       xtensa_switch_section_emit_state (result,
10284                                         default_lit_sections.init_lit_seg, 0);
10285     }
10286   else if (is_fini)
10287     {
10288       cache_literal_section (fini_literal_head,
10289                              default_lit_sections.fini_lit_seg_name,
10290                              &default_lit_sections.fini_lit_seg, TRUE);
10291       xtensa_switch_section_emit_state (result,
10292                                         default_lit_sections.fini_lit_seg, 0);
10293     }
10294   else
10295     {
10296       cache_literal_section (literal_head,
10297                              default_lit_sections.lit_seg_name,
10298                              &default_lit_sections.lit_seg, TRUE);
10299       xtensa_switch_section_emit_state (result,
10300                                         default_lit_sections.lit_seg, 0);
10301     }
10302
10303   if (!use_literal_section
10304       && !is_init && !is_fini
10305       && get_literal_pool_location (now_seg) != pool_location)
10306     {
10307       /* Close whatever frag is there.  */
10308       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
10309       xtensa_set_frag_assembly_state (frag_now);
10310       frag_now->tc_frag_data.literal_frag = pool_location;
10311       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
10312       xtensa_set_frag_assembly_state (frag_now);
10313     }
10314 }
10315
10316
10317 /* Call this function before emitting data into the literal section.
10318    This is a helper function for xtensa_switch_to_literal_fragment.
10319    This is similar to a .section new_now_seg subseg. */
10320
10321 static void
10322 xtensa_switch_section_emit_state (emit_state *state,
10323                                   segT new_now_seg,
10324                                   subsegT new_now_subseg)
10325 {
10326   state->name = now_seg->name;
10327   state->now_seg = now_seg;
10328   state->now_subseg = now_subseg;
10329   state->generating_literals = generating_literals;
10330   generating_literals++;
10331   subseg_new (segment_name (new_now_seg), new_now_subseg);
10332 }
10333
10334
10335 /* Use to restore the emitting into the normal place.  */
10336
10337 static void
10338 xtensa_restore_emit_state (emit_state *state)
10339 {
10340   generating_literals = state->generating_literals;
10341   subseg_new (state->name, state->now_subseg);
10342 }
10343
10344
10345 /* Get a segment of a given name.  If the segment is already
10346    present, return it; otherwise, create a new one.  */
10347
10348 static segT retrieve_literal_seg (seg_list *, const char *, bfd_boolean);
10349
10350 static void
10351 cache_literal_section (seg_list *head,
10352                        const char *name,
10353                        segT *seg,
10354                        bfd_boolean is_code)
10355 {
10356   segT current_section = now_seg;
10357   int current_subsec = now_subseg;
10358
10359   if (*seg != 0)
10360     return;
10361   *seg = retrieve_literal_seg (head, name, is_code);
10362   subseg_set (current_section, current_subsec);
10363 }
10364
10365
10366 /* Get a segment of a given name.  If the segment is already
10367    present, return it; otherwise, create a new one.  */
10368
10369 static segT seg_present (const char *);
10370 static void add_seg_list (seg_list *, segT);
10371
10372 static segT
10373 retrieve_literal_seg (seg_list *head, const char *name, bfd_boolean is_code)
10374 {
10375   segT ret = 0;
10376
10377   ret = seg_present (name);
10378   if (!ret)
10379     {
10380       ret = subseg_new (name, (subsegT) 0);
10381       if (head)
10382         add_seg_list (head, ret);
10383       bfd_set_section_flags (stdoutput, ret, SEC_HAS_CONTENTS |
10384                              SEC_READONLY | SEC_ALLOC | SEC_LOAD
10385                              | (is_code ? SEC_CODE : SEC_DATA));
10386       bfd_set_section_alignment (stdoutput, ret, 2);
10387     }
10388
10389   return ret;
10390 }
10391
10392
10393 /* Return a segment of a given name if it is present.  */
10394
10395 static segT
10396 seg_present (const char *name)
10397 {
10398   segT seg;
10399   seg = stdoutput->sections;
10400
10401   while (seg)
10402     {
10403       if (!strcmp (segment_name (seg), name))
10404         return seg;
10405       seg = seg->next;
10406     }
10407
10408   return 0;
10409 }
10410
10411
10412 /* Add a segment to a segment list.  */
10413
10414 static void
10415 add_seg_list (seg_list *head, segT seg)
10416 {
10417   seg_list *n;
10418   n = (seg_list *) xmalloc (sizeof (seg_list));
10419   assert (n);
10420
10421   n->seg = seg;
10422   n->next = head->next;
10423   head->next = n;
10424 }
10425
10426 \f
10427 /* Property Tables Stuff.  */
10428
10429 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10430 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10431 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10432
10433 typedef bfd_boolean (*frag_predicate) (const fragS *);
10434 typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
10435
10436 static void xtensa_create_property_segments
10437   (frag_predicate, frag_predicate, const char *, xt_section_type);
10438 static void xtensa_create_xproperty_segments
10439   (frag_flags_fn, const char *, xt_section_type);
10440 static segment_info_type *retrieve_segment_info (segT);
10441 static segT retrieve_xtensa_section (char *);
10442 static bfd_boolean section_has_property (segT, frag_predicate);
10443 static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
10444 static void add_xt_block_frags
10445   (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate);
10446 static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
10447 static void xtensa_frag_flags_init (frag_flags *);
10448 static void get_frag_property_flags (const fragS *, frag_flags *);
10449 static bfd_vma frag_flags_to_number (const frag_flags *);
10450 static void add_xt_prop_frags
10451   (segT, segT, xtensa_block_info **, frag_flags_fn);
10452
10453 /* Set up property tables after relaxation.  */
10454
10455 void
10456 xtensa_post_relax_hook (void)
10457 {
10458   xtensa_move_seg_list_to_beginning (literal_head);
10459   xtensa_move_seg_list_to_beginning (init_literal_head);
10460   xtensa_move_seg_list_to_beginning (fini_literal_head);
10461
10462   xtensa_find_unmarked_state_frags ();
10463
10464   if (use_literal_section)
10465     xtensa_create_property_segments (get_frag_is_literal,
10466                                      NULL,
10467                                      XTENSA_LIT_SEC_NAME,
10468                                      xt_literal_sec);
10469   xtensa_create_xproperty_segments (get_frag_property_flags,
10470                                     XTENSA_PROP_SEC_NAME,
10471                                     xt_prop_sec);
10472
10473   if (warn_unaligned_branch_targets)
10474     bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
10475   bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
10476 }
10477
10478
10479 /* This function is only meaningful after xtensa_move_literals.  */
10480
10481 static bfd_boolean
10482 get_frag_is_literal (const fragS *fragP)
10483 {
10484   assert (fragP != NULL);
10485   return fragP->tc_frag_data.is_literal;
10486 }
10487
10488
10489 static bfd_boolean
10490 get_frag_is_insn (const fragS *fragP)
10491 {
10492   assert (fragP != NULL);
10493   return fragP->tc_frag_data.is_insn;
10494 }
10495
10496
10497 static bfd_boolean
10498 get_frag_is_no_transform (fragS *fragP)
10499 {
10500   return fragP->tc_frag_data.is_no_transform;
10501 }
10502
10503
10504 static void
10505 set_frag_is_specific_opcode (fragS *fragP, bfd_boolean is_specific_opcode)
10506 {
10507   fragP->tc_frag_data.is_specific_opcode = is_specific_opcode;
10508 }
10509
10510
10511 static void
10512 set_frag_is_no_transform (fragS *fragP, bfd_boolean is_no_transform)
10513 {
10514   fragP->tc_frag_data.is_no_transform = is_no_transform;
10515 }
10516
10517
10518 static void
10519 xtensa_create_property_segments (frag_predicate property_function,
10520                                  frag_predicate end_property_function,
10521                                  const char *section_name_base,
10522                                  xt_section_type sec_type)
10523 {
10524   segT *seclist;
10525
10526   /* Walk over all of the current segments.
10527      Walk over each fragment
10528      For each non-empty fragment,
10529      Build a property record (append where possible).  */
10530
10531   for (seclist = &stdoutput->sections;
10532        seclist && *seclist;
10533        seclist = &(*seclist)->next)
10534     {
10535       segT sec = *seclist;
10536       flagword flags;
10537
10538       flags = bfd_get_section_flags (stdoutput, sec);
10539       if (flags & SEC_DEBUGGING)
10540         continue;
10541       if (!(flags & SEC_ALLOC))
10542         continue;
10543
10544       if (section_has_property (sec, property_function))
10545         {
10546           char *property_section_name =
10547             xtensa_get_property_section_name (sec, section_name_base);
10548           segT insn_sec = retrieve_xtensa_section (property_section_name);
10549           segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
10550           xtensa_block_info **xt_blocks =
10551             &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10552           /* Walk over all of the frchains here and add new sections.  */
10553           add_xt_block_frags (sec, insn_sec, xt_blocks, property_function,
10554                               end_property_function);
10555         }
10556     }
10557
10558   /* Now we fill them out....  */
10559
10560   for (seclist = &stdoutput->sections;
10561        seclist && *seclist;
10562        seclist = &(*seclist)->next)
10563     {
10564       segment_info_type *seginfo;
10565       xtensa_block_info *block;
10566       segT sec = *seclist;
10567
10568       seginfo = seg_info (sec);
10569       block = seginfo->tc_segment_info_data.blocks[sec_type];
10570
10571       if (block)
10572         {
10573           xtensa_block_info *cur_block;
10574           /* This is a section with some data.  */
10575           int num_recs = 0;
10576           size_t rec_size;
10577
10578           for (cur_block = block; cur_block; cur_block = cur_block->next)
10579             num_recs++;
10580
10581           rec_size = num_recs * 8;
10582           bfd_set_section_size (stdoutput, sec, rec_size);
10583
10584           /* In order to make this work with the assembler, we have to
10585              build some frags and then build the "fixups" for it.  It
10586              would be easier to just set the contents then set the
10587              arlents.  */
10588
10589           if (num_recs)
10590             {
10591               /* Allocate a fragment and leak it.  */
10592               fragS *fragP;
10593               size_t frag_size;
10594               fixS *fixes;
10595               frchainS *frchainP;
10596               int i;
10597               char *frag_data;
10598
10599               frag_size = sizeof (fragS) + rec_size;
10600               fragP = (fragS *) xmalloc (frag_size);
10601
10602               memset (fragP, 0, frag_size);
10603               fragP->fr_address = 0;
10604               fragP->fr_next = NULL;
10605               fragP->fr_fix = rec_size;
10606               fragP->fr_var = 0;
10607               fragP->fr_type = rs_fill;
10608               /* The rest are zeros.  */
10609
10610               frchainP = seginfo->frchainP;
10611               frchainP->frch_root = fragP;
10612               frchainP->frch_last = fragP;
10613
10614               fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10615               memset (fixes, 0, sizeof (fixS) * num_recs);
10616
10617               seginfo->fix_root = fixes;
10618               seginfo->fix_tail = &fixes[num_recs - 1];
10619               cur_block = block;
10620               frag_data = &fragP->fr_literal[0];
10621               for (i = 0; i < num_recs; i++)
10622                 {
10623                   fixS *fix = &fixes[i];
10624                   assert (cur_block);
10625
10626                   /* Write the fixup.  */
10627                   if (i != num_recs - 1)
10628                     fix->fx_next = &fixes[i + 1];
10629                   else
10630                     fix->fx_next = NULL;
10631                   fix->fx_size = 4;
10632                   fix->fx_done = 0;
10633                   fix->fx_frag = fragP;
10634                   fix->fx_where = i * 8;
10635                   fix->fx_addsy = section_symbol (cur_block->sec);
10636                   fix->fx_offset = cur_block->offset;
10637                   fix->fx_r_type = BFD_RELOC_32;
10638                   fix->fx_file = "Internal Assembly";
10639                   fix->fx_line = 0;
10640
10641                   /* Write the length.  */
10642                   md_number_to_chars (&frag_data[4 + 8 * i],
10643                                       cur_block->size, 4);
10644                   cur_block = cur_block->next;
10645                 }
10646             }
10647         }
10648     }
10649 }
10650
10651
10652 static void
10653 xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
10654                                   const char *section_name_base,
10655                                   xt_section_type sec_type)
10656 {
10657   segT *seclist;
10658
10659   /* Walk over all of the current segments.
10660      Walk over each fragment.
10661      For each fragment that has instructions,
10662      build an instruction record (append where possible).  */
10663
10664   for (seclist = &stdoutput->sections;
10665        seclist && *seclist;
10666        seclist = &(*seclist)->next)
10667     {
10668       segT sec = *seclist;
10669       flagword flags;
10670
10671       flags = bfd_get_section_flags (stdoutput, sec);
10672       if (flags & SEC_DEBUGGING)
10673         continue;
10674       if (!(flags & SEC_ALLOC))
10675         continue;
10676
10677       if (section_has_xproperty (sec, flag_fn))
10678         {
10679           char *property_section_name =
10680             xtensa_get_property_section_name (sec, section_name_base);
10681           segT insn_sec = retrieve_xtensa_section (property_section_name);
10682           segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
10683           xtensa_block_info **xt_blocks =
10684             &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10685           /* Walk over all of the frchains here and add new sections.  */
10686           add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn);
10687         }
10688     }
10689
10690   /* Now we fill them out....  */
10691
10692   for (seclist = &stdoutput->sections;
10693        seclist && *seclist;
10694        seclist = &(*seclist)->next)
10695     {
10696       segment_info_type *seginfo;
10697       xtensa_block_info *block;
10698       segT sec = *seclist;
10699
10700       seginfo = seg_info (sec);
10701       block = seginfo->tc_segment_info_data.blocks[sec_type];
10702
10703       if (block)
10704         {
10705           xtensa_block_info *cur_block;
10706           /* This is a section with some data.  */
10707           int num_recs = 0;
10708           size_t rec_size;
10709
10710           for (cur_block = block; cur_block; cur_block = cur_block->next)
10711             num_recs++;
10712
10713           rec_size = num_recs * (8 + 4);
10714           bfd_set_section_size (stdoutput, sec, rec_size);
10715
10716           /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10717
10718           /* In order to make this work with the assembler, we have to build
10719              some frags then build the "fixups" for it.  It would be easier to
10720              just set the contents then set the arlents.  */
10721
10722           if (num_recs)
10723             {
10724               /* Allocate a fragment and (unfortunately) leak it.  */
10725               fragS *fragP;
10726               size_t frag_size;
10727               fixS *fixes;
10728               frchainS *frchainP;
10729               int i;
10730               char *frag_data;
10731
10732               frag_size = sizeof (fragS) + rec_size;
10733               fragP = (fragS *) xmalloc (frag_size);
10734
10735               memset (fragP, 0, frag_size);
10736               fragP->fr_address = 0;
10737               fragP->fr_next = NULL;
10738               fragP->fr_fix = rec_size;
10739               fragP->fr_var = 0;
10740               fragP->fr_type = rs_fill;
10741               /* The rest are zeros.  */
10742
10743               frchainP = seginfo->frchainP;
10744               frchainP->frch_root = fragP;
10745               frchainP->frch_last = fragP;
10746
10747               fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10748               memset (fixes, 0, sizeof (fixS) * num_recs);
10749
10750               seginfo->fix_root = fixes;
10751               seginfo->fix_tail = &fixes[num_recs - 1];
10752               cur_block = block;
10753               frag_data = &fragP->fr_literal[0];
10754               for (i = 0; i < num_recs; i++)
10755                 {
10756                   fixS *fix = &fixes[i];
10757                   assert (cur_block);
10758
10759                   /* Write the fixup.  */
10760                   if (i != num_recs - 1)
10761                     fix->fx_next = &fixes[i + 1];
10762                   else
10763                     fix->fx_next = NULL;
10764                   fix->fx_size = 4;
10765                   fix->fx_done = 0;
10766                   fix->fx_frag = fragP;
10767                   fix->fx_where = i * (8 + 4);
10768                   fix->fx_addsy = section_symbol (cur_block->sec);
10769                   fix->fx_offset = cur_block->offset;
10770                   fix->fx_r_type = BFD_RELOC_32;
10771                   fix->fx_file = "Internal Assembly";
10772                   fix->fx_line = 0;
10773
10774                   /* Write the length.  */
10775                   md_number_to_chars (&frag_data[4 + (8+4) * i],
10776                                       cur_block->size, 4);
10777                   md_number_to_chars (&frag_data[8 + (8+4) * i],
10778                                       frag_flags_to_number (&cur_block->flags),
10779                                       4);
10780                   cur_block = cur_block->next;
10781                 }
10782             }
10783         }
10784     }
10785 }
10786
10787
10788 static segment_info_type *
10789 retrieve_segment_info (segT seg)
10790 {
10791   segment_info_type *seginfo;
10792   seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
10793   if (!seginfo)
10794     {
10795       frchainS *frchainP;
10796
10797       seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
10798       memset ((void *) seginfo, 0, sizeof (*seginfo));
10799       seginfo->fix_root = NULL;
10800       seginfo->fix_tail = NULL;
10801       seginfo->bfd_section = seg;
10802       seginfo->sym = 0;
10803       /* We will not be dealing with these, only our special ones.  */
10804 #if 0
10805       if (seg == bfd_abs_section_ptr)
10806         abs_seg_info = seginfo;
10807       else if (seg == bfd_und_section_ptr)
10808         und_seg_info = seginfo;
10809       else
10810 #endif
10811         bfd_set_section_userdata (stdoutput, seg, (void *) seginfo);
10812 #if 0
10813       seg_fix_rootP = &segment_info[seg].fix_root;
10814       seg_fix_tailP = &segment_info[seg].fix_tail;
10815 #endif
10816
10817       frchainP = (frchainS *) xmalloc (sizeof (frchainS));
10818       frchainP->frch_root = NULL;
10819       frchainP->frch_last = NULL;
10820       frchainP->frch_next = NULL;
10821       frchainP->frch_seg = seg;
10822       frchainP->frch_subseg = 0;
10823       frchainP->fix_root = NULL;
10824       frchainP->fix_tail = NULL;
10825       /* Do not init the objstack.  */
10826       /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10827       /* frchainP->frch_frag_now = fragP; */
10828       frchainP->frch_frag_now = NULL;
10829
10830       seginfo->frchainP = frchainP;
10831     }
10832
10833   return seginfo;
10834 }
10835
10836
10837 static segT
10838 retrieve_xtensa_section (char *sec_name)
10839 {
10840   bfd *abfd = stdoutput;
10841   flagword flags, out_flags, link_once_flags;
10842   segT s;
10843
10844   flags = bfd_get_section_flags (abfd, now_seg);
10845   link_once_flags = (flags & SEC_LINK_ONCE);
10846   if (link_once_flags)
10847     link_once_flags |= (flags & SEC_LINK_DUPLICATES);
10848   out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags);
10849
10850   s = bfd_make_section_old_way (abfd, sec_name);
10851   if (s == NULL)
10852     as_bad (_("could not create section %s"), sec_name);
10853   if (!bfd_set_section_flags (abfd, s, out_flags))
10854     as_bad (_("invalid flag combination on section %s"), sec_name);
10855
10856   return s;
10857 }
10858
10859
10860 static bfd_boolean
10861 section_has_property (segT sec, frag_predicate property_function)
10862 {
10863   segment_info_type *seginfo = seg_info (sec);
10864   fragS *fragP;
10865
10866   if (seginfo && seginfo->frchainP)
10867     {
10868       for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10869         {
10870           if (property_function (fragP)
10871               && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10872             return TRUE;
10873         }
10874     }
10875   return FALSE;
10876 }
10877
10878
10879 static bfd_boolean
10880 section_has_xproperty (segT sec, frag_flags_fn property_function)
10881 {
10882   segment_info_type *seginfo = seg_info (sec);
10883   fragS *fragP;
10884
10885   if (seginfo && seginfo->frchainP)
10886     {
10887       for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10888         {
10889           frag_flags prop_flags;
10890           property_function (fragP, &prop_flags);
10891           if (!xtensa_frag_flags_is_empty (&prop_flags))
10892             return TRUE;
10893         }
10894     }
10895   return FALSE;
10896 }
10897
10898
10899 /* Two types of block sections exist right now: literal and insns.  */
10900
10901 static void
10902 add_xt_block_frags (segT sec,
10903                     segT xt_block_sec,
10904                     xtensa_block_info **xt_block,
10905                     frag_predicate property_function,
10906                     frag_predicate end_property_function)
10907 {
10908   segment_info_type *seg_info;
10909   segment_info_type *xt_seg_info;
10910   bfd_vma seg_offset;
10911   fragS *fragP;
10912
10913   xt_seg_info = retrieve_segment_info (xt_block_sec);
10914   seg_info = retrieve_segment_info (sec);
10915
10916   /* Build it if needed.  */
10917   while (*xt_block != NULL)
10918     xt_block = &(*xt_block)->next;
10919   /* We are either at NULL at the beginning or at the end.  */
10920
10921   /* Walk through the frags.  */
10922   seg_offset = 0;
10923
10924   if (seg_info->frchainP)
10925     {
10926       for (fragP = seg_info->frchainP->frch_root;
10927            fragP;
10928            fragP = fragP->fr_next)
10929         {
10930           if (property_function (fragP)
10931               && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10932             {
10933               if (*xt_block != NULL)
10934                 {
10935                   if ((*xt_block)->offset + (*xt_block)->size
10936                       == fragP->fr_address)
10937                     (*xt_block)->size += fragP->fr_fix;
10938                   else
10939                     xt_block = &((*xt_block)->next);
10940                 }
10941               if (*xt_block == NULL)
10942                 {
10943                   xtensa_block_info *new_block = (xtensa_block_info *)
10944                     xmalloc (sizeof (xtensa_block_info));
10945                   new_block->sec = sec;
10946                   new_block->offset = fragP->fr_address;
10947                   new_block->size = fragP->fr_fix;
10948                   new_block->next = NULL;
10949                   xtensa_frag_flags_init (&new_block->flags);
10950                   *xt_block = new_block;
10951                 }
10952               if (end_property_function
10953                   && end_property_function (fragP))
10954                 {
10955                   xt_block = &((*xt_block)->next);
10956                 }
10957             }
10958         }
10959     }
10960 }
10961
10962
10963 /* Break the encapsulation of add_xt_prop_frags here.  */
10964
10965 static bfd_boolean
10966 xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
10967 {
10968   if (prop_flags->is_literal
10969       || prop_flags->is_insn
10970       || prop_flags->is_data
10971       || prop_flags->is_unreachable)
10972     return FALSE;
10973   return TRUE;
10974 }
10975
10976
10977 static void
10978 xtensa_frag_flags_init (frag_flags *prop_flags)
10979 {
10980   memset (prop_flags, 0, sizeof (frag_flags));
10981 }
10982
10983
10984 static void
10985 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
10986 {
10987   xtensa_frag_flags_init (prop_flags);
10988   if (fragP->tc_frag_data.is_literal)
10989     prop_flags->is_literal = TRUE;
10990   if (fragP->tc_frag_data.is_unreachable)
10991     prop_flags->is_unreachable = TRUE;
10992   else if (fragP->tc_frag_data.is_insn)
10993     {
10994       prop_flags->is_insn = TRUE;
10995       if (fragP->tc_frag_data.is_loop_target)
10996         prop_flags->insn.is_loop_target = TRUE;
10997       if (fragP->tc_frag_data.is_branch_target)
10998         prop_flags->insn.is_branch_target = TRUE;
10999       if (fragP->tc_frag_data.is_specific_opcode
11000           || fragP->tc_frag_data.is_no_transform)
11001         prop_flags->insn.is_no_transform = TRUE;
11002       if (fragP->tc_frag_data.is_no_density)
11003         prop_flags->insn.is_no_density = TRUE;
11004       if (fragP->tc_frag_data.use_absolute_literals)
11005         prop_flags->insn.is_abslit = TRUE;
11006     }
11007   if (fragP->tc_frag_data.is_align)
11008     {
11009       prop_flags->is_align = TRUE;
11010       prop_flags->alignment = fragP->tc_frag_data.alignment;
11011       if (xtensa_frag_flags_is_empty (prop_flags))
11012         prop_flags->is_data = TRUE;
11013     }
11014 }
11015
11016
11017 static bfd_vma
11018 frag_flags_to_number (const frag_flags *prop_flags)
11019 {
11020   bfd_vma num = 0;
11021   if (prop_flags->is_literal)
11022     num |= XTENSA_PROP_LITERAL;
11023   if (prop_flags->is_insn)
11024     num |= XTENSA_PROP_INSN;
11025   if (prop_flags->is_data)
11026     num |= XTENSA_PROP_DATA;
11027   if (prop_flags->is_unreachable)
11028     num |= XTENSA_PROP_UNREACHABLE;
11029   if (prop_flags->insn.is_loop_target)
11030     num |= XTENSA_PROP_INSN_LOOP_TARGET;
11031   if (prop_flags->insn.is_branch_target)
11032     {
11033       num |= XTENSA_PROP_INSN_BRANCH_TARGET;
11034       num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
11035     }
11036
11037   if (prop_flags->insn.is_no_density)
11038     num |= XTENSA_PROP_INSN_NO_DENSITY;
11039   if (prop_flags->insn.is_no_transform)
11040     num |= XTENSA_PROP_INSN_NO_TRANSFORM;
11041   if (prop_flags->insn.is_no_reorder)
11042     num |= XTENSA_PROP_INSN_NO_REORDER;
11043   if (prop_flags->insn.is_abslit)
11044     num |= XTENSA_PROP_INSN_ABSLIT;
11045
11046   if (prop_flags->is_align)
11047     {
11048       num |= XTENSA_PROP_ALIGN;
11049       num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
11050     }
11051
11052   return num;
11053 }
11054
11055
11056 static bfd_boolean
11057 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
11058                               const frag_flags *prop_flags_2)
11059 {
11060   /* Cannot combine with an end marker.  */
11061
11062   if (prop_flags_1->is_literal != prop_flags_2->is_literal)
11063     return FALSE;
11064   if (prop_flags_1->is_insn != prop_flags_2->is_insn)
11065     return FALSE;
11066   if (prop_flags_1->is_data != prop_flags_2->is_data)
11067     return FALSE;
11068
11069   if (prop_flags_1->is_insn)
11070     {
11071       /* Properties of the beginning of the frag.  */
11072       if (prop_flags_2->insn.is_loop_target)
11073         return FALSE;
11074       if (prop_flags_2->insn.is_branch_target)
11075         return FALSE;
11076       if (prop_flags_1->insn.is_no_density !=
11077           prop_flags_2->insn.is_no_density)
11078         return FALSE;
11079       if (prop_flags_1->insn.is_no_transform !=
11080           prop_flags_2->insn.is_no_transform)
11081         return FALSE;
11082       if (prop_flags_1->insn.is_no_reorder !=
11083           prop_flags_2->insn.is_no_reorder)
11084         return FALSE;
11085       if (prop_flags_1->insn.is_abslit !=
11086           prop_flags_2->insn.is_abslit)
11087         return FALSE;
11088     }
11089
11090   if (prop_flags_1->is_align)
11091     return FALSE;
11092
11093   return TRUE;
11094 }
11095
11096
11097 static bfd_vma
11098 xt_block_aligned_size (const xtensa_block_info *xt_block)
11099 {
11100   bfd_vma end_addr;
11101   size_t align_bits;
11102
11103   if (!xt_block->flags.is_align)
11104     return xt_block->size;
11105
11106   end_addr = xt_block->offset + xt_block->size;
11107   align_bits = xt_block->flags.alignment;
11108   end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
11109   return end_addr - xt_block->offset;
11110 }
11111
11112
11113 static bfd_boolean
11114 xtensa_xt_block_combine (xtensa_block_info *xt_block,
11115                          const xtensa_block_info *xt_block_2)
11116 {
11117   if (xt_block->sec != xt_block_2->sec)
11118     return FALSE;
11119   if (xt_block->offset + xt_block_aligned_size (xt_block)
11120       != xt_block_2->offset)
11121     return FALSE;
11122
11123   if (xt_block_2->size == 0
11124       && (!xt_block_2->flags.is_unreachable
11125           || xt_block->flags.is_unreachable))
11126     {
11127       if (xt_block_2->flags.is_align
11128           && xt_block->flags.is_align)
11129         {
11130           /* Nothing needed.  */
11131           if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
11132             return TRUE;
11133         }
11134       else
11135         {
11136           if (xt_block_2->flags.is_align)
11137             {
11138               /* Push alignment to previous entry.  */
11139               xt_block->flags.is_align = xt_block_2->flags.is_align;
11140               xt_block->flags.alignment = xt_block_2->flags.alignment;
11141             }
11142           return TRUE;
11143         }
11144     }
11145   if (!xtensa_frag_flags_combinable (&xt_block->flags,
11146                                      &xt_block_2->flags))
11147     return FALSE;
11148
11149   xt_block->size += xt_block_2->size;
11150
11151   if (xt_block_2->flags.is_align)
11152     {
11153       xt_block->flags.is_align = TRUE;
11154       xt_block->flags.alignment = xt_block_2->flags.alignment;
11155     }
11156
11157   return TRUE;
11158 }
11159
11160
11161 static void
11162 add_xt_prop_frags (segT sec,
11163                    segT xt_block_sec,
11164                    xtensa_block_info **xt_block,
11165                    frag_flags_fn property_function)
11166 {
11167   segment_info_type *seg_info;
11168   segment_info_type *xt_seg_info;
11169   bfd_vma seg_offset;
11170   fragS *fragP;
11171
11172   xt_seg_info = retrieve_segment_info (xt_block_sec);
11173   seg_info = retrieve_segment_info (sec);
11174   /* Build it if needed.  */
11175   while (*xt_block != NULL)
11176     {
11177       xt_block = &(*xt_block)->next;
11178     }
11179   /* We are either at NULL at the beginning or at the end.  */
11180
11181   /* Walk through the frags.  */
11182   seg_offset = 0;
11183
11184   if (seg_info->frchainP)
11185     {
11186       for (fragP = seg_info->frchainP->frch_root; fragP;
11187            fragP = fragP->fr_next)
11188         {
11189           xtensa_block_info tmp_block;
11190           tmp_block.sec = sec;
11191           tmp_block.offset = fragP->fr_address;
11192           tmp_block.size = fragP->fr_fix;
11193           tmp_block.next = NULL;
11194           property_function (fragP, &tmp_block.flags);
11195
11196           if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
11197             /* && fragP->fr_fix != 0) */
11198             {
11199               if ((*xt_block) == NULL
11200                   || !xtensa_xt_block_combine (*xt_block, &tmp_block))
11201                 {
11202                   xtensa_block_info *new_block;
11203                   if ((*xt_block) != NULL)
11204                     xt_block = &(*xt_block)->next;
11205                   new_block = (xtensa_block_info *)
11206                     xmalloc (sizeof (xtensa_block_info));
11207                   *new_block = tmp_block;
11208                   *xt_block = new_block;
11209                 }
11210             }
11211         }
11212     }
11213 }
11214
11215 \f
11216 /* op_placement_info_table */
11217
11218 /* op_placement_info makes it easier to determine which
11219    ops can go in which slots.  */
11220
11221 static void
11222 init_op_placement_info_table (void)
11223 {
11224   xtensa_isa isa = xtensa_default_isa;
11225   xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
11226   xtensa_opcode opcode;
11227   xtensa_format fmt;
11228   int slot;
11229   int num_opcodes = xtensa_isa_num_opcodes (isa);
11230
11231   op_placement_table = (op_placement_info_table)
11232     xmalloc (sizeof (op_placement_info) * num_opcodes);
11233   assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
11234
11235   for (opcode = 0; opcode < num_opcodes; opcode++)
11236     {
11237       op_placement_info *opi = &op_placement_table[opcode];
11238       /* FIXME: Make tinsn allocation dynamic.  */
11239       if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS)
11240         as_fatal (_("too many operands in instruction"));
11241       opi->single = XTENSA_UNDEFINED;
11242       opi->single_size = 0;
11243       opi->widest = XTENSA_UNDEFINED;
11244       opi->widest_size = 0;
11245       opi->narrowest = XTENSA_UNDEFINED;
11246       opi->narrowest_size = 0x7F;
11247       opi->formats = 0;
11248       opi->num_formats = 0;
11249       opi->issuef = 0;
11250       for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
11251         {
11252           opi->slots[fmt] = 0;
11253           for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
11254             {
11255               if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
11256                 {
11257                   int fmt_length = xtensa_format_length (isa, fmt);
11258                   opi->issuef++;
11259                   set_bit (fmt, opi->formats);
11260                   set_bit (slot, opi->slots[fmt]);
11261                   /* opi->slot_count[fmt]++; */
11262                   if (fmt_length < opi->narrowest_size)
11263                     {
11264                       opi->narrowest = fmt;
11265                       opi->narrowest_size = fmt_length;
11266                     }
11267                   if (fmt_length > opi->widest_size)
11268                     {
11269                       opi->widest = fmt;
11270                       opi->widest_size = fmt_length;
11271                     }
11272                   if (xtensa_format_num_slots (isa, fmt) == 1)
11273                     {
11274                       if (opi->single_size == 0
11275                           || fmt_length < opi->single_size)
11276                         {
11277                           opi->single = fmt;
11278                           opi->single_size = fmt_length;
11279                         }
11280                     }
11281                 }
11282             }
11283           if (opi->formats)
11284             opi->num_formats++;
11285         }
11286     }
11287   xtensa_insnbuf_free (isa, ibuf);
11288 }
11289
11290
11291 bfd_boolean
11292 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
11293 {
11294   return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
11295 }
11296
11297
11298 /* If the opcode is available in a single slot format, return its size.  */
11299
11300 static int
11301 xg_get_single_size (xtensa_opcode opcode)
11302 {
11303   assert (op_placement_table[opcode].single != XTENSA_UNDEFINED);
11304   return op_placement_table[opcode].single_size;
11305 }
11306
11307
11308 static xtensa_format
11309 xg_get_single_format (xtensa_opcode opcode)
11310 {
11311   return op_placement_table[opcode].single;
11312 }
11313
11314 \f
11315 /* Instruction Stack Functions (from "xtensa-istack.h").  */
11316
11317 void
11318 istack_init (IStack *stack)
11319 {
11320   memset (stack, 0, sizeof (IStack));
11321   stack->ninsn = 0;
11322 }
11323
11324
11325 bfd_boolean
11326 istack_empty (IStack *stack)
11327 {
11328   return (stack->ninsn == 0);
11329 }
11330
11331
11332 bfd_boolean
11333 istack_full (IStack *stack)
11334 {
11335   return (stack->ninsn == MAX_ISTACK);
11336 }
11337
11338
11339 /* Return a pointer to the top IStack entry.
11340    It is an error to call this if istack_empty () is TRUE. */
11341
11342 TInsn *
11343 istack_top (IStack *stack)
11344 {
11345   int rec = stack->ninsn - 1;
11346   assert (!istack_empty (stack));
11347   return &stack->insn[rec];
11348 }
11349
11350
11351 /* Add a new TInsn to an IStack.
11352    It is an error to call this if istack_full () is TRUE.  */
11353
11354 void
11355 istack_push (IStack *stack, TInsn *insn)
11356 {
11357   int rec = stack->ninsn;
11358   assert (!istack_full (stack));
11359   stack->insn[rec] = *insn;
11360   stack->ninsn++;
11361 }
11362
11363
11364 /* Clear space for the next TInsn on the IStack and return a pointer
11365    to it.  It is an error to call this if istack_full () is TRUE.  */
11366
11367 TInsn *
11368 istack_push_space (IStack *stack)
11369 {
11370   int rec = stack->ninsn;
11371   TInsn *insn;
11372   assert (!istack_full (stack));
11373   insn = &stack->insn[rec];
11374   memset (insn, 0, sizeof (TInsn));
11375   stack->ninsn++;
11376   return insn;
11377 }
11378
11379
11380 /* Remove the last pushed instruction.  It is an error to call this if
11381    istack_empty () returns TRUE.  */
11382
11383 void
11384 istack_pop (IStack *stack)
11385 {
11386   int rec = stack->ninsn - 1;
11387   assert (!istack_empty (stack));
11388   stack->ninsn--;
11389   memset (&stack->insn[rec], 0, sizeof (TInsn));
11390 }
11391
11392 \f
11393 /* TInsn functions.  */
11394
11395 void
11396 tinsn_init (TInsn *dst)
11397 {
11398   memset (dst, 0, sizeof (TInsn));
11399 }
11400
11401
11402 /* Get the ``num''th token of the TInsn.
11403    It is illegal to call this if num > insn->ntoks.  */
11404
11405 expressionS *
11406 tinsn_get_tok (TInsn *insn, int num)
11407 {
11408   assert (num < insn->ntok);
11409   return &insn->tok[num];
11410 }
11411
11412
11413 /* Return TRUE if ANY of the operands in the insn are symbolic.  */
11414
11415 static bfd_boolean
11416 tinsn_has_symbolic_operands (const TInsn *insn)
11417 {
11418   int i;
11419   int n = insn->ntok;
11420
11421   assert (insn->insn_type == ITYPE_INSN);
11422
11423   for (i = 0; i < n; ++i)
11424     {
11425       switch (insn->tok[i].X_op)
11426         {
11427         case O_register:
11428         case O_constant:
11429           break;
11430         default:
11431           return TRUE;
11432         }
11433     }
11434   return FALSE;
11435 }
11436
11437
11438 bfd_boolean
11439 tinsn_has_invalid_symbolic_operands (const TInsn *insn)
11440 {
11441   xtensa_isa isa = xtensa_default_isa;
11442   int i;
11443   int n = insn->ntok;
11444
11445   assert (insn->insn_type == ITYPE_INSN);
11446
11447   for (i = 0; i < n; ++i)
11448     {
11449       switch (insn->tok[i].X_op)
11450         {
11451         case O_register:
11452         case O_constant:
11453           break;
11454         case O_big:
11455         case O_illegal:
11456         case O_absent:
11457           /* Errors for these types are caught later.  */
11458           break;
11459         case O_hi16:
11460         case O_lo16:
11461         default:
11462           /* Symbolic immediates are only allowed on the last immediate
11463              operand.  At this time, CONST16 is the only opcode where we
11464              support non-PC-relative relocations.  (It isn't necessary
11465              to complain about non-PC-relative relocations here, but
11466              otherwise, no error is reported until the relocations are
11467              generated, and the assembler won't get that far if there
11468              are any other errors.  It's nice to see all the problems
11469              at once.)  */
11470           if (i != get_relaxable_immed (insn->opcode)
11471               || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
11472                   && insn->opcode != xtensa_const16_opcode))
11473             {
11474               as_bad (_("invalid symbolic operand %d on '%s'"),
11475                       i, xtensa_opcode_name (isa, insn->opcode));
11476               return TRUE;
11477             }
11478         }
11479     }
11480   return FALSE;
11481 }
11482
11483
11484 /* For assembly code with complex expressions (e.g. subtraction),
11485    we have to build them in the literal pool so that
11486    their results are calculated correctly after relaxation.
11487    The relaxation only handles expressions that
11488    boil down to SYMBOL + OFFSET.  */
11489
11490 static bfd_boolean
11491 tinsn_has_complex_operands (const TInsn *insn)
11492 {
11493   int i;
11494   int n = insn->ntok;
11495   assert (insn->insn_type == ITYPE_INSN);
11496   for (i = 0; i < n; ++i)
11497     {
11498       switch (insn->tok[i].X_op)
11499         {
11500         case O_register:
11501         case O_constant:
11502         case O_symbol:
11503         case O_lo16:
11504         case O_hi16:
11505           break;
11506         default:
11507           return TRUE;
11508         }
11509     }
11510   return FALSE;
11511 }
11512
11513
11514 /* Convert the constant operands in the tinsn to insnbuf.
11515    Return TRUE if there is a symbol in the immediate field.
11516
11517    Before this is called,
11518    1) the number of operands are correct
11519    2) the tinsn is a ITYPE_INSN
11520    3) ONLY the relaxable_ is built
11521    4) All operands are O_constant, O_symbol.  All constants fit
11522    The return value tells whether there are any remaining O_symbols.  */
11523
11524 static bfd_boolean
11525 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
11526 {
11527   static xtensa_insnbuf slotbuf = 0;
11528   xtensa_isa isa = xtensa_default_isa;
11529   xtensa_opcode opcode = tinsn->opcode;
11530   xtensa_format fmt = xg_get_single_format (opcode);
11531   bfd_boolean has_fixup = FALSE;
11532   int noperands = xtensa_opcode_num_operands (isa, opcode);
11533   int i;
11534   uint32 opnd_value;
11535   char *file_name;
11536   int line;
11537
11538   if (!slotbuf)
11539     slotbuf = xtensa_insnbuf_alloc (isa);
11540
11541   assert (tinsn->insn_type == ITYPE_INSN);
11542   if (noperands != tinsn->ntok)
11543     as_fatal (_("operand number mismatch"));
11544
11545   if (xtensa_opcode_encode (isa, fmt, 0, slotbuf, opcode))
11546     as_fatal (_("cannot encode opcode"));
11547
11548   for (i = 0; i < noperands; ++i)
11549     {
11550       expressionS *expr = &tinsn->tok[i];
11551       switch (expr->X_op)
11552         {
11553         case O_register:
11554           if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11555             break;
11556           /* The register number has already been checked in
11557              expression_maybe_register, so we don't need to check here.  */
11558           opnd_value = expr->X_add_number;
11559           (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11560           xtensa_operand_set_field (isa, opcode, i, fmt, 0,
11561                                     slotbuf, opnd_value);
11562           break;
11563
11564         case O_constant:
11565           if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11566             break;
11567           as_where (&file_name, &line);
11568           /* It is a constant and we called this function,
11569              then we have to try to fit it.  */
11570           xtensa_insnbuf_set_operand (slotbuf, fmt, 0, opcode, i,
11571                                       expr->X_add_number, file_name, line);
11572           break;
11573
11574         default:
11575           has_fixup = TRUE;
11576           break;
11577         }
11578     }
11579
11580   xtensa_format_encode (isa, fmt, insnbuf);
11581   xtensa_format_set_slot (isa, fmt, 0, insnbuf, slotbuf);
11582
11583   return has_fixup;
11584 }
11585
11586
11587 /* Convert the constant operands in the tinsn to slotbuf.
11588    Return TRUE if there is a symbol in the immediate field.
11589    (Eventually this should replace tinsn_to_insnbuf.)  */
11590
11591 /* Before this is called,
11592    1) the number of operands are correct
11593    2) the tinsn is a ITYPE_INSN
11594    3) ONLY the relaxable_ is built
11595    4) All operands are
11596        O_constant, O_symbol
11597       All constants fit
11598
11599    The return value tells whether there are any remaining O_symbols.  */
11600
11601 static bfd_boolean
11602 tinsn_to_slotbuf (xtensa_format fmt,
11603                   int slot,
11604                   TInsn *tinsn,
11605                   xtensa_insnbuf slotbuf)
11606 {
11607   xtensa_isa isa = xtensa_default_isa;
11608   xtensa_opcode opcode = tinsn->opcode;
11609   bfd_boolean has_fixup = FALSE;
11610   int noperands = xtensa_opcode_num_operands (isa, opcode);
11611   int i;
11612
11613   *((int *) &slotbuf[0]) = 0;
11614   *((int *) &slotbuf[1]) = 0;
11615   assert (tinsn->insn_type == ITYPE_INSN);
11616   if (noperands != tinsn->ntok)
11617     as_fatal (_("operand number mismatch"));
11618
11619   if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
11620     {
11621       as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11622               xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
11623       return FALSE;
11624     }
11625
11626   for (i = 0; i < noperands; i++)
11627     {
11628       expressionS *expr = &tinsn->tok[i];
11629       int rc, line;
11630       char *file_name;
11631       uint32 opnd_value;
11632
11633       switch (expr->X_op)
11634         {
11635         case O_register:
11636           if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11637             break;
11638           /* The register number has already been checked in
11639              expression_maybe_register, so we don't need to check here.  */
11640           opnd_value = expr->X_add_number;
11641           (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11642           rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
11643                                          opnd_value);
11644           if (rc != 0)
11645             as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
11646           break;
11647
11648         case O_constant:
11649           if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11650             break;
11651           as_where (&file_name, &line);
11652           /* It is a constant and we called this function
11653              then we have to try to fit it.  */
11654           xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
11655                                       expr->X_add_number, file_name, line);
11656           break;
11657
11658         default:
11659           has_fixup = TRUE;
11660           break;
11661         }
11662     }
11663
11664   return has_fixup;
11665 }
11666
11667
11668 /* Check the instruction arguments.  Return TRUE on failure.  */
11669
11670 static bfd_boolean
11671 tinsn_check_arguments (const TInsn *insn)
11672 {
11673   xtensa_isa isa = xtensa_default_isa;
11674   xtensa_opcode opcode = insn->opcode;
11675
11676   if (opcode == XTENSA_UNDEFINED)
11677     {
11678       as_bad (_("invalid opcode"));
11679       return TRUE;
11680     }
11681
11682   if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
11683     {
11684       as_bad (_("too few operands"));
11685       return TRUE;
11686     }
11687
11688   if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
11689     {
11690       as_bad (_("too many operands"));
11691       return TRUE;
11692     }
11693   return FALSE;
11694 }
11695
11696
11697 /* Load an instruction from its encoded form.  */
11698
11699 static void
11700 tinsn_from_chars (TInsn *tinsn, char *f, int slot)
11701 {
11702   vliw_insn vinsn;
11703
11704   xg_init_vinsn (&vinsn);
11705   vinsn_from_chars (&vinsn, f);
11706
11707   *tinsn = vinsn.slots[slot];
11708   xg_free_vinsn (&vinsn);
11709 }
11710
11711
11712 static void
11713 tinsn_from_insnbuf (TInsn *tinsn,
11714                     xtensa_insnbuf slotbuf,
11715                     xtensa_format fmt,
11716                     int slot)
11717 {
11718   int i;
11719   xtensa_isa isa = xtensa_default_isa;
11720
11721   /* Find the immed.  */
11722   tinsn_init (tinsn);
11723   tinsn->insn_type = ITYPE_INSN;
11724   tinsn->is_specific_opcode = FALSE;    /* must not be specific */
11725   tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
11726   tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
11727   for (i = 0; i < tinsn->ntok; i++)
11728     {
11729       set_expr_const (&tinsn->tok[i],
11730                       xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
11731                                                   tinsn->opcode, i));
11732     }
11733 }
11734
11735
11736 /* Read the value of the relaxable immed from the fr_symbol and fr_offset.  */
11737
11738 static void
11739 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
11740 {
11741   xtensa_opcode opcode = tinsn->opcode;
11742   int opnum;
11743
11744   if (fragP->tc_frag_data.slot_symbols[slot])
11745     {
11746       opnum = get_relaxable_immed (opcode);
11747       assert (opnum >= 0);
11748       if (fragP->tc_frag_data.slot_sub_symbols[slot])
11749         {
11750           set_expr_symbol_offset_diff
11751             (&tinsn->tok[opnum],
11752              fragP->tc_frag_data.slot_symbols[slot],
11753              fragP->tc_frag_data.slot_sub_symbols[slot],
11754              fragP->tc_frag_data.slot_offsets[slot]);
11755         }
11756       else
11757         {
11758           set_expr_symbol_offset
11759             (&tinsn->tok[opnum],
11760              fragP->tc_frag_data.slot_symbols[slot],
11761              fragP->tc_frag_data.slot_offsets[slot]);
11762         }
11763     }
11764 }
11765
11766
11767 static int
11768 get_num_stack_text_bytes (IStack *istack)
11769 {
11770   int i;
11771   int text_bytes = 0;
11772
11773   for (i = 0; i < istack->ninsn; i++)
11774     {
11775       TInsn *tinsn = &istack->insn[i];
11776       if (tinsn->insn_type == ITYPE_INSN)
11777         text_bytes += xg_get_single_size (tinsn->opcode);
11778     }
11779   return text_bytes;
11780 }
11781
11782
11783 static int
11784 get_num_stack_literal_bytes (IStack *istack)
11785 {
11786   int i;
11787   int lit_bytes = 0;
11788
11789   for (i = 0; i < istack->ninsn; i++)
11790     {
11791       TInsn *tinsn = &istack->insn[i];
11792       if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
11793         lit_bytes += 4;
11794     }
11795   return lit_bytes;
11796 }
11797
11798 \f
11799 /* vliw_insn functions.  */
11800
11801 static void
11802 xg_init_vinsn (vliw_insn *v)
11803 {
11804   int i;
11805   xtensa_isa isa = xtensa_default_isa;
11806
11807   xg_clear_vinsn (v);
11808
11809   v->insnbuf = xtensa_insnbuf_alloc (isa);
11810   if (v->insnbuf == NULL)
11811     as_fatal (_("out of memory"));
11812
11813   for (i = 0; i < MAX_SLOTS; i++)
11814     {
11815       tinsn_init (&v->slots[i]);
11816       v->slots[i].opcode = XTENSA_UNDEFINED;
11817       v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
11818       if (v->slotbuf[i] == NULL)
11819         as_fatal (_("out of memory"));
11820     }
11821 }
11822
11823
11824 static void
11825 xg_clear_vinsn (vliw_insn *v)
11826 {
11827   int i;
11828   v->format = XTENSA_UNDEFINED;
11829   v->num_slots = 0;
11830   v->inside_bundle = FALSE;
11831
11832   if (xt_saved_debug_type != DEBUG_NONE)
11833     debug_type = xt_saved_debug_type;
11834
11835   for (i = 0; i < MAX_SLOTS; i++)
11836     {
11837       memset (&v->slots[i], 0, sizeof (TInsn));
11838       v->slots[i].opcode = XTENSA_UNDEFINED;
11839     }
11840 }
11841
11842
11843 static bfd_boolean
11844 vinsn_has_specific_opcodes (vliw_insn *v)
11845 {
11846   int i;
11847
11848   for (i = 0; i < v->num_slots; i++)
11849     {
11850       if (v->slots[i].is_specific_opcode)
11851         return TRUE;
11852     }
11853   return FALSE;
11854 }
11855
11856
11857 static void
11858 xg_free_vinsn (vliw_insn *v)
11859 {
11860   int i;
11861   xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
11862   for (i = 0; i < MAX_SLOTS; i++)
11863     xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
11864 }
11865
11866
11867 /* Before this is called, we should have
11868    filled out the following fields:
11869
11870    1) the number of operands for each opcode are correct
11871    2) the tinsn in the slots are ITYPE_INSN
11872    3) ONLY the relaxable_ is built
11873    4) All operands are
11874        O_constant, O_symbol
11875       All constants fit
11876
11877    The return value tells whether there are any remaining O_symbols.  */
11878
11879 static bfd_boolean
11880 vinsn_to_insnbuf (vliw_insn *vinsn,
11881                   char *frag_offset,
11882                   fragS *fragP,
11883                   bfd_boolean record_fixup)
11884 {
11885   xtensa_isa isa = xtensa_default_isa;
11886   xtensa_format fmt = vinsn->format;
11887   xtensa_insnbuf insnbuf = vinsn->insnbuf;
11888   int slot;
11889   bfd_boolean has_fixup = FALSE;
11890
11891   xtensa_format_encode (isa, fmt, insnbuf);
11892
11893   for (slot = 0; slot < vinsn->num_slots; slot++)
11894     {
11895       TInsn *tinsn = &vinsn->slots[slot];
11896       bfd_boolean tinsn_has_fixup =
11897         tinsn_to_slotbuf (vinsn->format, slot, tinsn,
11898                           vinsn->slotbuf[slot]);
11899
11900       xtensa_format_set_slot (isa, fmt, slot,
11901                               insnbuf, vinsn->slotbuf[slot]);
11902       /* tinsn_has_fixup tracks if there is a fixup at all.
11903          record_fixup controls globally.  I.E., we use this
11904          function from several places, some of which are after
11905          fixups have already been recorded.  Finally,
11906          tinsn->record_fixup controls based on the individual ops,
11907          which may or may not need it based on the relaxation
11908          requirements.  */
11909       if (tinsn_has_fixup && record_fixup)
11910         {
11911           int i;
11912           xtensa_opcode opcode = tinsn->opcode;
11913           int noperands = xtensa_opcode_num_operands (isa, opcode);
11914           has_fixup = TRUE;
11915
11916           for (i = 0; i < noperands; i++)
11917             {
11918               expressionS* expr = &tinsn->tok[i];
11919               switch (expr->X_op)
11920                 {
11921                 case O_symbol:
11922                 case O_lo16:
11923                 case O_hi16:
11924                   if (get_relaxable_immed (opcode) == i)
11925                     {
11926                       if (tinsn->record_fix || expr->X_op != O_symbol)
11927                         {
11928                           if (!xg_add_opcode_fix
11929                               (tinsn, i, fmt, slot, expr, fragP,
11930                                frag_offset - fragP->fr_literal))
11931                             as_bad (_("instruction with constant operands does not fit"));
11932                         }
11933                       else
11934                         {
11935                           tinsn->symbol = expr->X_add_symbol;
11936                           tinsn->offset = expr->X_add_number;
11937                         }
11938                     }
11939                   else
11940                     as_bad (_("invalid operand %d on '%s'"),
11941                             i, xtensa_opcode_name (isa, opcode));
11942                   break;
11943
11944                 case O_constant:
11945                 case O_register:
11946                   break;
11947
11948                 case O_subtract:
11949                   if (get_relaxable_immed (opcode) == i)
11950                     {
11951                       if (tinsn->record_fix)
11952                           as_bad (_("invalid subtract operand"));
11953                       else
11954                         {
11955                           tinsn->symbol = expr->X_add_symbol;
11956                           tinsn->sub_symbol = expr->X_op_symbol;
11957                           tinsn->offset = expr->X_add_number;
11958                         }
11959                     }
11960                   else
11961                     as_bad (_("invalid operand %d on '%s'"),
11962                             i, xtensa_opcode_name (isa, opcode));
11963                   break;
11964
11965                 default:
11966                   as_bad (_("invalid expression for operand %d on '%s'"),
11967                           i, xtensa_opcode_name (isa, opcode));
11968                   break;
11969                 }
11970             }
11971         }
11972     }
11973
11974   return has_fixup;
11975 }
11976
11977
11978 static void
11979 vinsn_from_chars (vliw_insn *vinsn, char *f)
11980 {
11981   static xtensa_insnbuf insnbuf = NULL;
11982   static xtensa_insnbuf slotbuf = NULL;
11983   int i;
11984   xtensa_format fmt;
11985   xtensa_isa isa = xtensa_default_isa;
11986
11987   if (!insnbuf)
11988     {
11989       insnbuf = xtensa_insnbuf_alloc (isa);
11990       slotbuf = xtensa_insnbuf_alloc (isa);
11991     }
11992
11993   xtensa_insnbuf_from_chars (isa, insnbuf, f, 0);
11994   fmt = xtensa_format_decode (isa, insnbuf);
11995   if (fmt == XTENSA_UNDEFINED)
11996     as_fatal (_("cannot decode instruction format"));
11997   vinsn->format = fmt;
11998   vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
11999
12000   for (i = 0; i < vinsn->num_slots; i++)
12001     {
12002       TInsn *tinsn = &vinsn->slots[i];
12003       xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
12004       tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
12005     }
12006 }
12007
12008 \f
12009 /* Expression utilities.  */
12010
12011 /* Return TRUE if the expression is an integer constant.  */
12012
12013 bfd_boolean
12014 expr_is_const (const expressionS *s)
12015 {
12016   return (s->X_op == O_constant);
12017 }
12018
12019
12020 /* Get the expression constant.
12021    Calling this is illegal if expr_is_const () returns TRUE.  */
12022
12023 offsetT
12024 get_expr_const (const expressionS *s)
12025 {
12026   assert (expr_is_const (s));
12027   return s->X_add_number;
12028 }
12029
12030
12031 /* Set the expression to a constant value.  */
12032
12033 void
12034 set_expr_const (expressionS *s, offsetT val)
12035 {
12036   s->X_op = O_constant;
12037   s->X_add_number = val;
12038   s->X_add_symbol = NULL;
12039   s->X_op_symbol = NULL;
12040 }
12041
12042
12043 bfd_boolean
12044 expr_is_register (const expressionS *s)
12045 {
12046   return (s->X_op == O_register);
12047 }
12048
12049
12050 /* Get the expression constant.
12051    Calling this is illegal if expr_is_const () returns TRUE.  */
12052
12053 offsetT
12054 get_expr_register (const expressionS *s)
12055 {
12056   assert (expr_is_register (s));
12057   return s->X_add_number;
12058 }
12059
12060
12061 /* Set the expression to a symbol + constant offset.  */
12062
12063 void
12064 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
12065 {
12066   s->X_op = O_symbol;
12067   s->X_add_symbol = sym;
12068   s->X_op_symbol = NULL;        /* unused */
12069   s->X_add_number = offset;
12070 }
12071
12072
12073 /* Set the expression to symbol - minus_sym + offset.  */
12074
12075 static void
12076 set_expr_symbol_offset_diff (expressionS *s,
12077                              symbolS *sym,
12078                              symbolS *minus_sym,
12079                              offsetT offset)
12080 {
12081   s->X_op = O_subtract;
12082   s->X_add_symbol = sym;
12083   s->X_op_symbol = minus_sym;   /* unused */
12084   s->X_add_number = offset;
12085 }
12086
12087
12088 /* Return TRUE if the two expressions are equal.  */
12089
12090 bfd_boolean
12091 expr_is_equal (expressionS *s1, expressionS *s2)
12092 {
12093   if (s1->X_op != s2->X_op)
12094     return FALSE;
12095   if (s1->X_add_symbol != s2->X_add_symbol)
12096     return FALSE;
12097   if (s1->X_op_symbol != s2->X_op_symbol)
12098     return FALSE;
12099   if (s1->X_add_number != s2->X_add_number)
12100     return FALSE;
12101   return TRUE;
12102 }
12103
12104
12105 static void
12106 copy_expr (expressionS *dst, const expressionS *src)
12107 {
12108   memcpy (dst, src, sizeof (expressionS));
12109 }
12110
12111 \f
12112 /* Support for Tensilica's "--rename-section" option.  */
12113
12114 #ifdef XTENSA_SECTION_RENAME
12115
12116 struct rename_section_struct
12117 {
12118   char *old_name;
12119   char *new_name;
12120   struct rename_section_struct *next;
12121 };
12122
12123 static struct rename_section_struct *section_rename;
12124
12125
12126 /* Parse the string oldname=new_name:oldname2=new_name2
12127    and call add_section_rename.  */
12128
12129 static void
12130 build_section_rename (const char *arg)
12131 {
12132   char *this_arg = NULL;
12133   char *next_arg = NULL;
12134
12135   for (this_arg = strdup (arg); this_arg != NULL; this_arg = next_arg)
12136     {
12137       if (this_arg)
12138         {
12139           next_arg = strchr (this_arg, ':');
12140           if (next_arg)
12141             {
12142               *next_arg = '\0';
12143               next_arg++;
12144             }
12145         }
12146       {
12147         char *old_name = this_arg;
12148         char *new_name = strchr (this_arg, '=');
12149
12150         if (*old_name == '\0')
12151           {
12152             as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12153             continue;
12154           }
12155         if (!new_name || new_name[1] == '\0')
12156           {
12157             as_warn (_("ignoring invalid '-rename-section' "
12158                        "specification: '%s'"), old_name);
12159             continue;
12160           }
12161         *new_name = '\0';
12162         new_name++;
12163         add_section_rename (old_name, new_name);
12164       }
12165     }
12166 }
12167
12168
12169 static void
12170 add_section_rename (char *old_name, char *new_name)
12171 {
12172   struct rename_section_struct *r = section_rename;
12173
12174   /* Check for invalid section renaming.  */
12175   for (r = section_rename; r != NULL; r = r->next)
12176     {
12177       if (strcmp (r->old_name, old_name) == 0)
12178         as_bad (_("section %s renamed multiple times"), old_name);
12179       if (strcmp (r->new_name, new_name) == 0)
12180         as_bad (_("multiple sections remapped to output section %s"),
12181                 new_name);
12182     }
12183
12184   /* Now add it.  */
12185   r = (struct rename_section_struct *)
12186     xmalloc (sizeof (struct rename_section_struct));
12187   r->old_name = strdup (old_name);
12188   r->new_name = strdup (new_name);
12189   r->next = section_rename;
12190   section_rename = r;
12191 }
12192
12193
12194 const char *
12195 xtensa_section_rename (const char *name)
12196 {
12197   struct rename_section_struct *r = section_rename;
12198
12199   for (r = section_rename; r != NULL; r = r->next)
12200     {
12201       if (strcmp (r->old_name, name) == 0)
12202         return r->new_name;
12203     }
12204
12205   return name;
12206 }
12207
12208 #endif /* XTENSA_SECTION_RENAME */