1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "xtensa-istack.h"
29 #include "dwarf2dbg.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
268 unsigned is_loop_target
: 1;
269 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
270 unsigned bt_align_priority
: 2;
272 unsigned is_no_density
: 1;
273 /* no_longcalls flag does not need to be placed in the object file. */
274 /* is_specific_opcode implies no_transform. */
275 unsigned is_no_transform
: 1;
277 unsigned is_no_reorder
: 1;
279 /* Uses absolute literal addressing for l32r. */
280 unsigned is_abslit
: 1;
282 unsigned is_align
: 1;
283 unsigned alignment
: 5;
287 /* Structure for saving information about a block of property data
288 for frags that have the same flags. */
289 struct xtensa_block_info_struct
295 struct xtensa_block_info_struct
*next
;
299 /* Structure for saving the current state before emitting literals. */
300 typedef struct emit_state_struct
305 int generating_literals
;
309 /* Opcode placement information */
311 typedef unsigned long long bitfield
;
312 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
313 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
314 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
316 #define MAX_FORMATS 32
318 typedef struct op_placement_info_struct
321 /* A number describing how restrictive the issue is for this
322 opcode. For example, an opcode that fits lots of different
323 formats has a high freedom, as does an opcode that fits
324 only one format but many slots in that format. The most
325 restrictive is the opcode that fits only one slot in one
328 xtensa_format narrowest
;
332 /* formats is a bitfield with the Nth bit set
333 if the opcode fits in the Nth xtensa_format. */
336 /* slots[N]'s Mth bit is set if the op fits in the
337 Mth slot of the Nth xtensa_format. */
338 bitfield slots
[MAX_FORMATS
];
340 /* A count of the number of slots in a given format
341 an op can fit (i.e., the bitcount of the slot field above). */
342 char slots_in_format
[MAX_FORMATS
];
344 } op_placement_info
, *op_placement_info_table
;
346 op_placement_info_table op_placement_table
;
349 /* Extra expression types. */
351 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
352 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
353 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
355 struct suffix_reloc_map
359 bfd_reloc_code_real_type reloc
;
360 unsigned char operator;
363 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
365 static struct suffix_reloc_map suffix_relocs
[] =
367 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
368 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
369 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
370 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
384 directive_literal_prefix
,
386 directive_absolute_literals
,
387 directive_last_directive
393 bfd_boolean can_be_negated
;
396 const directive_infoS directive_info
[] =
399 { "literal", FALSE
},
401 { "transform", TRUE
},
402 { "freeregs", FALSE
},
403 { "longcalls", TRUE
},
404 { "literal_prefix", FALSE
},
405 { "schedule", TRUE
},
406 { "absolute-literals", TRUE
}
409 bfd_boolean directive_state
[] =
413 #if !XCHAL_HAVE_DENSITY
418 TRUE
, /* transform */
419 FALSE
, /* freeregs */
420 FALSE
, /* longcalls */
421 FALSE
, /* literal_prefix */
422 FALSE
, /* schedule */
423 #if XSHAL_USE_ABSOLUTE_LITERALS
424 TRUE
/* absolute_literals */
426 FALSE
/* absolute_literals */
431 /* Directive functions. */
433 static void xtensa_begin_directive (int);
434 static void xtensa_end_directive (int);
435 static void xtensa_literal_prefix (void);
436 static void xtensa_literal_position (int);
437 static void xtensa_literal_pseudo (int);
438 static void xtensa_frequency_pseudo (int);
439 static void xtensa_elf_cons (int);
441 /* Parsing and Idiom Translation. */
443 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
445 /* Various Other Internal Functions. */
447 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
448 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
449 static void xtensa_mark_literal_pool_location (void);
450 static addressT
get_expanded_loop_offset (xtensa_opcode
);
451 static fragS
*get_literal_pool_location (segT
);
452 static void set_literal_pool_location (segT
, fragS
*);
453 static void xtensa_set_frag_assembly_state (fragS
*);
454 static void finish_vinsn (vliw_insn
*);
455 static bfd_boolean
emit_single_op (TInsn
*);
456 static int total_frag_text_expansion (fragS
*);
458 /* Alignment Functions. */
460 static int get_text_align_power (unsigned);
461 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
462 static int branch_align_power (segT
);
464 /* Helpers for xtensa_relax_frag(). */
466 static long relax_frag_add_nop (fragS
*);
468 /* Accessors for additional per-subsegment information. */
470 static unsigned get_last_insn_flags (segT
, subsegT
);
471 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
472 static float get_subseg_total_freq (segT
, subsegT
);
473 static float get_subseg_target_freq (segT
, subsegT
);
474 static void set_subseg_freq (segT
, subsegT
, float, float);
476 /* Segment list functions. */
478 static void xtensa_move_literals (void);
479 static void xtensa_reorder_segments (void);
480 static void xtensa_switch_to_literal_fragment (emit_state
*);
481 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
482 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
483 static void xtensa_restore_emit_state (emit_state
*);
484 static segT
cache_literal_section (bfd_boolean
);
486 /* Import from elf32-xtensa.c in BFD library. */
488 extern asection
*xtensa_get_property_section (asection
*, const char *);
490 /* op_placement_info functions. */
492 static void init_op_placement_info_table (void);
493 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
494 static int xg_get_single_size (xtensa_opcode
);
495 static xtensa_format
xg_get_single_format (xtensa_opcode
);
496 static int xg_get_single_slot (xtensa_opcode
);
498 /* TInsn and IStack functions. */
500 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
501 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
502 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
503 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
504 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
505 static void tinsn_from_chars (TInsn
*, char *, int);
506 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
507 static int get_num_stack_text_bytes (IStack
*);
508 static int get_num_stack_literal_bytes (IStack
*);
510 /* vliw_insn functions. */
512 static void xg_init_vinsn (vliw_insn
*);
513 static void xg_clear_vinsn (vliw_insn
*);
514 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
515 static void xg_free_vinsn (vliw_insn
*);
516 static bfd_boolean vinsn_to_insnbuf
517 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
518 static void vinsn_from_chars (vliw_insn
*, char *);
520 /* Expression Utilities. */
522 bfd_boolean
expr_is_const (const expressionS
*);
523 offsetT
get_expr_const (const expressionS
*);
524 void set_expr_const (expressionS
*, offsetT
);
525 bfd_boolean
expr_is_register (const expressionS
*);
526 offsetT
get_expr_register (const expressionS
*);
527 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
528 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
529 static void copy_expr (expressionS
*, const expressionS
*);
531 /* Section renaming. */
533 static void build_section_rename (const char *);
536 /* ISA imported from bfd. */
537 extern xtensa_isa xtensa_default_isa
;
539 extern int target_big_endian
;
541 static xtensa_opcode xtensa_addi_opcode
;
542 static xtensa_opcode xtensa_addmi_opcode
;
543 static xtensa_opcode xtensa_call0_opcode
;
544 static xtensa_opcode xtensa_call4_opcode
;
545 static xtensa_opcode xtensa_call8_opcode
;
546 static xtensa_opcode xtensa_call12_opcode
;
547 static xtensa_opcode xtensa_callx0_opcode
;
548 static xtensa_opcode xtensa_callx4_opcode
;
549 static xtensa_opcode xtensa_callx8_opcode
;
550 static xtensa_opcode xtensa_callx12_opcode
;
551 static xtensa_opcode xtensa_const16_opcode
;
552 static xtensa_opcode xtensa_entry_opcode
;
553 static xtensa_opcode xtensa_movi_opcode
;
554 static xtensa_opcode xtensa_movi_n_opcode
;
555 static xtensa_opcode xtensa_isync_opcode
;
556 static xtensa_opcode xtensa_jx_opcode
;
557 static xtensa_opcode xtensa_l32r_opcode
;
558 static xtensa_opcode xtensa_loop_opcode
;
559 static xtensa_opcode xtensa_loopnez_opcode
;
560 static xtensa_opcode xtensa_loopgtz_opcode
;
561 static xtensa_opcode xtensa_nop_opcode
;
562 static xtensa_opcode xtensa_nop_n_opcode
;
563 static xtensa_opcode xtensa_or_opcode
;
564 static xtensa_opcode xtensa_ret_opcode
;
565 static xtensa_opcode xtensa_ret_n_opcode
;
566 static xtensa_opcode xtensa_retw_opcode
;
567 static xtensa_opcode xtensa_retw_n_opcode
;
568 static xtensa_opcode xtensa_rsr_lcount_opcode
;
569 static xtensa_opcode xtensa_waiti_opcode
;
572 /* Command-line Options. */
574 bfd_boolean use_literal_section
= TRUE
;
575 static bfd_boolean align_targets
= TRUE
;
576 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
577 static bfd_boolean has_a0_b_retw
= FALSE
;
578 static bfd_boolean workaround_a0_b_retw
= FALSE
;
579 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
580 static bfd_boolean workaround_short_loop
= FALSE
;
581 static bfd_boolean maybe_has_short_loop
= FALSE
;
582 static bfd_boolean workaround_close_loop_end
= FALSE
;
583 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
584 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
586 /* When workaround_short_loops is TRUE, all loops with early exits must
587 have at least 3 instructions. workaround_all_short_loops is a modifier
588 to the workaround_short_loop flag. In addition to the
589 workaround_short_loop actions, all straightline loopgtz and loopnez
590 must have at least 3 instructions. */
592 static bfd_boolean workaround_all_short_loops
= FALSE
;
596 xtensa_setup_hw_workarounds (int earliest
, int latest
)
598 if (earliest
> latest
)
599 as_fatal (_("illegal range of target hardware versions"));
601 /* Enable all workarounds for pre-T1050.0 hardware. */
602 if (earliest
< 105000 || latest
< 105000)
604 workaround_a0_b_retw
|= TRUE
;
605 workaround_b_j_loop_end
|= TRUE
;
606 workaround_short_loop
|= TRUE
;
607 workaround_close_loop_end
|= TRUE
;
608 workaround_all_short_loops
|= TRUE
;
609 enforce_three_byte_loop_align
= TRUE
;
616 option_density
= OPTION_MD_BASE
,
623 option_no_link_relax
,
631 option_text_section_literals
,
632 option_no_text_section_literals
,
634 option_absolute_literals
,
635 option_no_absolute_literals
,
637 option_align_targets
,
638 option_no_align_targets
,
640 option_warn_unaligned_targets
,
645 option_workaround_a0_b_retw
,
646 option_no_workaround_a0_b_retw
,
648 option_workaround_b_j_loop_end
,
649 option_no_workaround_b_j_loop_end
,
651 option_workaround_short_loop
,
652 option_no_workaround_short_loop
,
654 option_workaround_all_short_loops
,
655 option_no_workaround_all_short_loops
,
657 option_workaround_close_loop_end
,
658 option_no_workaround_close_loop_end
,
660 option_no_workarounds
,
662 option_rename_section_name
,
665 option_prefer_const16
,
667 option_target_hardware
670 const char *md_shortopts
= "";
672 struct option md_longopts
[] =
674 { "density", no_argument
, NULL
, option_density
},
675 { "no-density", no_argument
, NULL
, option_no_density
},
677 /* Both "relax" and "generics" are deprecated and treated as equivalent
678 to the "transform" option. */
679 { "relax", no_argument
, NULL
, option_relax
},
680 { "no-relax", no_argument
, NULL
, option_no_relax
},
681 { "generics", no_argument
, NULL
, option_generics
},
682 { "no-generics", no_argument
, NULL
, option_no_generics
},
684 { "transform", no_argument
, NULL
, option_transform
},
685 { "no-transform", no_argument
, NULL
, option_no_transform
},
686 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
687 { "no-text-section-literals", no_argument
, NULL
,
688 option_no_text_section_literals
},
689 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
690 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
691 /* This option was changed from -align-target to -target-align
692 because it conflicted with the "-al" option. */
693 { "target-align", no_argument
, NULL
, option_align_targets
},
694 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
695 { "warn-unaligned-targets", no_argument
, NULL
,
696 option_warn_unaligned_targets
},
697 { "longcalls", no_argument
, NULL
, option_longcalls
},
698 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
700 { "no-workaround-a0-b-retw", no_argument
, NULL
,
701 option_no_workaround_a0_b_retw
},
702 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
704 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
705 option_no_workaround_b_j_loop_end
},
706 { "workaround-b-j-loop-end", no_argument
, NULL
,
707 option_workaround_b_j_loop_end
},
709 { "no-workaround-short-loops", no_argument
, NULL
,
710 option_no_workaround_short_loop
},
711 { "workaround-short-loops", no_argument
, NULL
,
712 option_workaround_short_loop
},
714 { "no-workaround-all-short-loops", no_argument
, NULL
,
715 option_no_workaround_all_short_loops
},
716 { "workaround-all-short-loop", no_argument
, NULL
,
717 option_workaround_all_short_loops
},
719 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
720 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
722 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
724 { "no-workaround-close-loop-end", no_argument
, NULL
,
725 option_no_workaround_close_loop_end
},
726 { "workaround-close-loop-end", no_argument
, NULL
,
727 option_workaround_close_loop_end
},
729 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
731 { "link-relax", no_argument
, NULL
, option_link_relax
},
732 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
734 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
736 { NULL
, no_argument
, NULL
, 0 }
739 size_t md_longopts_size
= sizeof md_longopts
;
743 md_parse_option (int c
, char *arg
)
748 as_warn (_("--density option is ignored"));
750 case option_no_density
:
751 as_warn (_("--no-density option is ignored"));
753 case option_link_relax
:
756 case option_no_link_relax
:
759 case option_generics
:
760 as_warn (_("--generics is deprecated; use --transform instead"));
761 return md_parse_option (option_transform
, arg
);
762 case option_no_generics
:
763 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
764 return md_parse_option (option_no_transform
, arg
);
766 as_warn (_("--relax is deprecated; use --transform instead"));
767 return md_parse_option (option_transform
, arg
);
768 case option_no_relax
:
769 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
770 return md_parse_option (option_no_transform
, arg
);
771 case option_longcalls
:
772 directive_state
[directive_longcalls
] = TRUE
;
774 case option_no_longcalls
:
775 directive_state
[directive_longcalls
] = FALSE
;
777 case option_text_section_literals
:
778 use_literal_section
= FALSE
;
780 case option_no_text_section_literals
:
781 use_literal_section
= TRUE
;
783 case option_absolute_literals
:
784 if (!absolute_literals_supported
)
786 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
789 directive_state
[directive_absolute_literals
] = TRUE
;
791 case option_no_absolute_literals
:
792 directive_state
[directive_absolute_literals
] = FALSE
;
795 case option_workaround_a0_b_retw
:
796 workaround_a0_b_retw
= TRUE
;
798 case option_no_workaround_a0_b_retw
:
799 workaround_a0_b_retw
= FALSE
;
801 case option_workaround_b_j_loop_end
:
802 workaround_b_j_loop_end
= TRUE
;
804 case option_no_workaround_b_j_loop_end
:
805 workaround_b_j_loop_end
= FALSE
;
808 case option_workaround_short_loop
:
809 workaround_short_loop
= TRUE
;
811 case option_no_workaround_short_loop
:
812 workaround_short_loop
= FALSE
;
815 case option_workaround_all_short_loops
:
816 workaround_all_short_loops
= TRUE
;
818 case option_no_workaround_all_short_loops
:
819 workaround_all_short_loops
= FALSE
;
822 case option_workaround_close_loop_end
:
823 workaround_close_loop_end
= TRUE
;
825 case option_no_workaround_close_loop_end
:
826 workaround_close_loop_end
= FALSE
;
829 case option_no_workarounds
:
830 workaround_a0_b_retw
= FALSE
;
831 workaround_b_j_loop_end
= FALSE
;
832 workaround_short_loop
= FALSE
;
833 workaround_all_short_loops
= FALSE
;
834 workaround_close_loop_end
= FALSE
;
837 case option_align_targets
:
838 align_targets
= TRUE
;
840 case option_no_align_targets
:
841 align_targets
= FALSE
;
844 case option_warn_unaligned_targets
:
845 warn_unaligned_branch_targets
= TRUE
;
848 case option_rename_section_name
:
849 build_section_rename (arg
);
853 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
854 should be emitted or not. FIXME: Not implemented. */
857 case option_prefer_l32r
:
859 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
863 case option_prefer_const16
:
865 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
869 case option_target_hardware
:
871 int earliest
, latest
= 0;
872 if (*arg
== 0 || *arg
== '-')
873 as_fatal (_("invalid target hardware version"));
875 earliest
= strtol (arg
, &arg
, 0);
879 else if (*arg
== '-')
882 as_fatal (_("invalid target hardware version"));
883 latest
= strtol (arg
, &arg
, 0);
886 as_fatal (_("invalid target hardware version"));
888 xtensa_setup_hw_workarounds (earliest
, latest
);
892 case option_transform
:
893 /* This option has no affect other than to use the defaults,
894 which are already set. */
897 case option_no_transform
:
898 /* This option turns off all transformations of any kind.
899 However, because we want to preserve the state of other
900 directives, we only change its own field. Thus, before
901 you perform any transformation, always check if transform
902 is available. If you use the functions we provide for this
903 purpose, you will be ok. */
904 directive_state
[directive_transform
] = FALSE
;
914 md_show_usage (FILE *stream
)
918 --[no-]text-section-literals\n\
919 [Do not] put literals in the text section\n\
920 --[no-]absolute-literals\n\
921 [Do not] default to use non-PC-relative literals\n\
922 --[no-]target-align [Do not] try to align branch targets\n\
923 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
924 --[no-]transform [Do not] transform instructions\n\
925 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
929 /* Functions related to the list of current label symbols. */
932 xtensa_add_insn_label (symbolS
*sym
)
936 if (!free_insn_labels
)
937 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
940 l
= free_insn_labels
;
941 free_insn_labels
= l
->next
;
945 l
->next
= insn_labels
;
951 xtensa_clear_insn_labels (void)
955 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
963 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
967 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
969 symbolS
*lit_sym
= lit
->sym
;
970 S_SET_VALUE (lit_sym
, new_offset
);
971 symbol_set_frag (lit_sym
, new_frag
);
976 /* Directive data and functions. */
978 typedef struct state_stackS_struct
980 directiveE directive
;
982 bfd_boolean old_state
;
986 struct state_stackS_struct
*prev
;
989 state_stackS
*directive_state_stack
;
991 const pseudo_typeS md_pseudo_table
[] =
993 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
994 { "literal_position", xtensa_literal_position
, 0 },
995 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
996 { "long", xtensa_elf_cons
, 4 },
997 { "word", xtensa_elf_cons
, 4 },
998 { "short", xtensa_elf_cons
, 2 },
999 { "begin", xtensa_begin_directive
, 0 },
1000 { "end", xtensa_end_directive
, 0 },
1001 { "literal", xtensa_literal_pseudo
, 0 },
1002 { "frequency", xtensa_frequency_pseudo
, 0 },
1008 use_transform (void)
1010 /* After md_end, you should be checking frag by frag, rather
1011 than state directives. */
1012 assert (!past_xtensa_end
);
1013 return directive_state
[directive_transform
];
1018 do_align_targets (void)
1020 /* Do not use this function after md_end; just look at align_targets
1021 instead. There is no target-align directive, so alignment is either
1022 enabled for all frags or not done at all. */
1023 assert (!past_xtensa_end
);
1024 return align_targets
&& use_transform ();
1029 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1033 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1035 as_where (&file
, &line
);
1037 stack
->directive
= directive
;
1038 stack
->negated
= negated
;
1039 stack
->old_state
= directive_state
[directive
];
1042 stack
->datum
= datum
;
1043 stack
->prev
= directive_state_stack
;
1044 directive_state_stack
= stack
;
1046 directive_state
[directive
] = !negated
;
1051 directive_pop (directiveE
*directive
,
1052 bfd_boolean
*negated
,
1057 state_stackS
*top
= directive_state_stack
;
1059 if (!directive_state_stack
)
1061 as_bad (_("unmatched end directive"));
1062 *directive
= directive_none
;
1066 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1067 *directive
= top
->directive
;
1068 *negated
= top
->negated
;
1071 *datum
= top
->datum
;
1072 directive_state_stack
= top
->prev
;
1078 directive_balance (void)
1080 while (directive_state_stack
)
1082 directiveE directive
;
1083 bfd_boolean negated
;
1088 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1089 as_warn_where ((char *) file
, line
,
1090 _(".begin directive with no matching .end directive"));
1096 inside_directive (directiveE dir
)
1098 state_stackS
*top
= directive_state_stack
;
1100 while (top
&& top
->directive
!= dir
)
1103 return (top
!= NULL
);
1108 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1112 char *directive_string
;
1114 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1119 input_line_pointer
+= 3;
1122 len
= strspn (input_line_pointer
,
1123 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1125 /* This code is a hack to make .begin [no-][generics|relax] exactly
1126 equivalent to .begin [no-]transform. We should remove it when
1127 we stop accepting those options. */
1129 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1131 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1132 directive_string
= "transform";
1134 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1136 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1137 directive_string
= "transform";
1140 directive_string
= input_line_pointer
;
1142 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1144 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1146 input_line_pointer
+= len
;
1147 *directive
= (directiveE
) i
;
1148 if (*negated
&& !directive_info
[i
].can_be_negated
)
1149 as_bad (_("directive %s cannot be negated"),
1150 directive_info
[i
].name
);
1155 as_bad (_("unknown directive"));
1156 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1161 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1163 directiveE directive
;
1164 bfd_boolean negated
;
1168 get_directive (&directive
, &negated
);
1169 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1171 discard_rest_of_line ();
1175 if (cur_vinsn
.inside_bundle
)
1176 as_bad (_("directives are not valid inside bundles"));
1180 case directive_literal
:
1181 if (!inside_directive (directive_literal
))
1183 /* Previous labels go with whatever follows this directive, not with
1184 the literal, so save them now. */
1185 saved_insn_labels
= insn_labels
;
1188 as_warn (_(".begin literal is deprecated; use .literal instead"));
1189 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1190 xtensa_switch_to_literal_fragment (state
);
1191 directive_push (directive_literal
, negated
, state
);
1194 case directive_literal_prefix
:
1195 /* Have to flush pending output because a movi relaxed to an l32r
1196 might produce a literal. */
1197 md_flush_pending_output ();
1198 /* Check to see if the current fragment is a literal
1199 fragment. If it is, then this operation is not allowed. */
1200 if (generating_literals
)
1202 as_bad (_("cannot set literal_prefix inside literal fragment"));
1206 /* Allocate the literal state for this section and push
1207 onto the directive stack. */
1208 ls
= xmalloc (sizeof (lit_state
));
1211 *ls
= default_lit_sections
;
1212 directive_push (directive_literal_prefix
, negated
, ls
);
1214 /* Process the new prefix. */
1215 xtensa_literal_prefix ();
1218 case directive_freeregs
:
1219 /* This information is currently unused, but we'll accept the statement
1220 and just discard the rest of the line. This won't check the syntax,
1221 but it will accept every correct freeregs directive. */
1222 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1223 directive_push (directive_freeregs
, negated
, 0);
1226 case directive_schedule
:
1227 md_flush_pending_output ();
1228 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1229 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1230 directive_push (directive_schedule
, negated
, 0);
1231 xtensa_set_frag_assembly_state (frag_now
);
1234 case directive_density
:
1235 as_warn (_(".begin [no-]density is ignored"));
1238 case directive_absolute_literals
:
1239 md_flush_pending_output ();
1240 if (!absolute_literals_supported
&& !negated
)
1242 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1245 xtensa_set_frag_assembly_state (frag_now
);
1246 directive_push (directive
, negated
, 0);
1250 md_flush_pending_output ();
1251 xtensa_set_frag_assembly_state (frag_now
);
1252 directive_push (directive
, negated
, 0);
1256 demand_empty_rest_of_line ();
1261 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1263 directiveE begin_directive
, end_directive
;
1264 bfd_boolean begin_negated
, end_negated
;
1268 emit_state
**state_ptr
;
1271 if (cur_vinsn
.inside_bundle
)
1272 as_bad (_("directives are not valid inside bundles"));
1274 get_directive (&end_directive
, &end_negated
);
1276 md_flush_pending_output ();
1278 switch (end_directive
)
1280 case (directiveE
) XTENSA_UNDEFINED
:
1281 discard_rest_of_line ();
1284 case directive_density
:
1285 as_warn (_(".end [no-]density is ignored"));
1286 demand_empty_rest_of_line ();
1289 case directive_absolute_literals
:
1290 if (!absolute_literals_supported
&& !end_negated
)
1292 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1293 demand_empty_rest_of_line ();
1302 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1303 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1304 (const void **) state_ptr
);
1306 if (begin_directive
!= directive_none
)
1308 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1310 as_bad (_("does not match begin %s%s at %s:%d"),
1311 begin_negated
? "no-" : "",
1312 directive_info
[begin_directive
].name
, file
, line
);
1316 switch (end_directive
)
1318 case directive_literal
:
1319 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1320 xtensa_restore_emit_state (state
);
1321 xtensa_set_frag_assembly_state (frag_now
);
1323 if (!inside_directive (directive_literal
))
1325 /* Restore the list of current labels. */
1326 xtensa_clear_insn_labels ();
1327 insn_labels
= saved_insn_labels
;
1331 case directive_literal_prefix
:
1332 /* Restore the default collection sections from saved state. */
1333 s
= (lit_state
*) state
;
1335 default_lit_sections
= *s
;
1337 /* Free the state storage. */
1338 free (s
->lit_prefix
);
1342 case directive_schedule
:
1343 case directive_freeregs
:
1347 xtensa_set_frag_assembly_state (frag_now
);
1353 demand_empty_rest_of_line ();
1357 /* Place an aligned literal fragment at the current location. */
1360 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1362 md_flush_pending_output ();
1364 if (inside_directive (directive_literal
))
1365 as_warn (_(".literal_position inside literal directive; ignoring"));
1366 xtensa_mark_literal_pool_location ();
1368 demand_empty_rest_of_line ();
1369 xtensa_clear_insn_labels ();
1373 /* Support .literal label, expr, ... */
1376 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1379 char *p
, *base_name
;
1383 if (inside_directive (directive_literal
))
1385 as_bad (_(".literal not allowed inside .begin literal region"));
1386 ignore_rest_of_line ();
1390 md_flush_pending_output ();
1392 /* Previous labels go with whatever follows this directive, not with
1393 the literal, so save them now. */
1394 saved_insn_labels
= insn_labels
;
1397 /* If we are using text-section literals, then this is the right value... */
1400 base_name
= input_line_pointer
;
1402 xtensa_switch_to_literal_fragment (&state
);
1404 /* ...but if we aren't using text-section-literals, then we
1405 need to put them in the section we just switched to. */
1406 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1409 /* All literals are aligned to four-byte boundaries. */
1410 frag_align (2, 0, 0);
1411 record_alignment (now_seg
, 2);
1413 c
= get_symbol_end ();
1414 /* Just after name is now '\0'. */
1415 p
= input_line_pointer
;
1419 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1421 as_bad (_("expected comma or colon after symbol name; "
1422 "rest of line ignored"));
1423 ignore_rest_of_line ();
1424 xtensa_restore_emit_state (&state
);
1432 input_line_pointer
++; /* skip ',' or ':' */
1434 xtensa_elf_cons (4);
1436 xtensa_restore_emit_state (&state
);
1438 /* Restore the list of current labels. */
1439 xtensa_clear_insn_labels ();
1440 insn_labels
= saved_insn_labels
;
1445 xtensa_literal_prefix (void)
1450 /* Parse the new prefix from the input_line_pointer. */
1452 len
= strspn (input_line_pointer
,
1453 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1454 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1456 /* Get a null-terminated copy of the name. */
1457 name
= xmalloc (len
+ 1);
1459 strncpy (name
, input_line_pointer
, len
);
1462 /* Skip the name in the input line. */
1463 input_line_pointer
+= len
;
1465 default_lit_sections
.lit_prefix
= name
;
1467 /* Clear cached literal sections, since the prefix has changed. */
1468 default_lit_sections
.lit_seg
= NULL
;
1469 default_lit_sections
.lit4_seg
= NULL
;
1473 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1476 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1478 float fall_through_f
, target_f
;
1480 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1481 if (fall_through_f
< 0)
1483 as_bad (_("fall through frequency must be greater than 0"));
1484 ignore_rest_of_line ();
1488 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1491 as_bad (_("branch target frequency must be greater than 0"));
1492 ignore_rest_of_line ();
1496 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1498 demand_empty_rest_of_line ();
1502 /* Like normal .long/.short/.word, except support @plt, etc.
1503 Clobbers input_line_pointer, checks end-of-line. */
1506 xtensa_elf_cons (int nbytes
)
1509 bfd_reloc_code_real_type reloc
;
1511 md_flush_pending_output ();
1513 if (cur_vinsn
.inside_bundle
)
1514 as_bad (_("directives are not valid inside bundles"));
1516 if (is_it_end_of_statement ())
1518 demand_empty_rest_of_line ();
1525 if (exp
.X_op
== O_symbol
1526 && *input_line_pointer
== '@'
1527 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1530 reloc_howto_type
*reloc_howto
=
1531 bfd_reloc_type_lookup (stdoutput
, reloc
);
1533 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1534 as_bad (_("unsupported relocation"));
1535 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1536 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1537 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1538 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1539 as_bad (_("opcode-specific %s relocation used outside "
1540 "an instruction"), reloc_howto
->name
);
1541 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1542 as_bad (_("%s relocations do not fit in %d bytes"),
1543 reloc_howto
->name
, nbytes
);
1546 char *p
= frag_more ((int) nbytes
);
1547 xtensa_set_frag_assembly_state (frag_now
);
1548 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1549 nbytes
, &exp
, 0, reloc
);
1553 emit_expr (&exp
, (unsigned int) nbytes
);
1555 while (*input_line_pointer
++ == ',');
1557 input_line_pointer
--; /* Put terminator back into stream. */
1558 demand_empty_rest_of_line ();
1562 /* Parsing and Idiom Translation. */
1564 /* Parse @plt, etc. and return the desired relocation. */
1565 static bfd_reloc_code_real_type
1566 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1573 struct suffix_reloc_map
*ptr
;
1576 return BFD_RELOC_NONE
;
1578 for (ch
= *str
, str2
= ident
;
1579 (str2
< ident
+ sizeof (ident
) - 1
1580 && (ISALNUM (ch
) || ch
== '@'));
1583 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1590 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1591 if (ch
== ptr
->suffix
[0]
1592 && len
== ptr
->length
1593 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1595 /* Now check for "identifier@suffix+constant". */
1596 if (*str
== '-' || *str
== '+')
1598 char *orig_line
= input_line_pointer
;
1599 expressionS new_exp
;
1601 input_line_pointer
= str
;
1602 expression (&new_exp
);
1603 if (new_exp
.X_op
== O_constant
)
1605 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1606 str
= input_line_pointer
;
1609 if (&input_line_pointer
!= str_p
)
1610 input_line_pointer
= orig_line
;
1617 return BFD_RELOC_UNUSED
;
1621 /* Find the matching operator type. */
1622 static unsigned char
1623 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1625 struct suffix_reloc_map
*sfx
;
1626 unsigned char operator = (unsigned char) -1;
1628 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1630 if (sfx
->reloc
== reloc
)
1632 operator = sfx
->operator;
1636 assert (operator != (unsigned char) -1);
1641 /* Find the matching reloc type. */
1642 static bfd_reloc_code_real_type
1643 map_operator_to_reloc (unsigned char operator)
1645 struct suffix_reloc_map
*sfx
;
1646 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1648 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1650 if (sfx
->operator == operator)
1657 if (reloc
== BFD_RELOC_UNUSED
)
1658 return BFD_RELOC_32
;
1665 expression_end (const char *name
)
1688 #define ERROR_REG_NUM ((unsigned) -1)
1691 tc_get_register (const char *prefix
)
1694 const char *next_expr
;
1695 const char *old_line_pointer
;
1698 old_line_pointer
= input_line_pointer
;
1700 if (*input_line_pointer
== '$')
1701 ++input_line_pointer
;
1703 /* Accept "sp" as a synonym for "a1". */
1704 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1705 && expression_end (input_line_pointer
+ 2))
1707 input_line_pointer
+= 2;
1708 return 1; /* AR[1] */
1711 while (*input_line_pointer
++ == *prefix
++)
1713 --input_line_pointer
;
1718 as_bad (_("bad register name: %s"), old_line_pointer
);
1719 return ERROR_REG_NUM
;
1722 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1724 as_bad (_("bad register number: %s"), input_line_pointer
);
1725 return ERROR_REG_NUM
;
1730 while (ISDIGIT ((int) *input_line_pointer
))
1731 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1733 if (!(next_expr
= expression_end (input_line_pointer
)))
1735 as_bad (_("bad register name: %s"), old_line_pointer
);
1736 return ERROR_REG_NUM
;
1739 input_line_pointer
= (char *) next_expr
;
1746 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1748 xtensa_isa isa
= xtensa_default_isa
;
1750 /* Check if this is an immediate operand. */
1751 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1753 bfd_reloc_code_real_type reloc
;
1754 segT t
= expression (tok
);
1755 if (t
== absolute_section
1756 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1758 assert (tok
->X_op
== O_constant
);
1759 tok
->X_op
= O_symbol
;
1760 tok
->X_add_symbol
= &abs_symbol
;
1763 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1764 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1767 if (reloc
== BFD_RELOC_UNUSED
)
1769 as_bad (_("unsupported relocation"));
1773 if (tok
->X_op
== O_constant
)
1777 case BFD_RELOC_LO16
:
1778 tok
->X_add_number
&= 0xffff;
1781 case BFD_RELOC_HI16
:
1782 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1789 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1794 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1795 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1797 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1800 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1801 as_bad (_("register number out of range"));
1804 tok
->X_op
= O_register
;
1805 tok
->X_add_symbol
= 0;
1806 tok
->X_add_number
= reg
;
1811 /* Split up the arguments for an opcode or pseudo-op. */
1814 tokenize_arguments (char **args
, char *str
)
1816 char *old_input_line_pointer
;
1817 bfd_boolean saw_comma
= FALSE
;
1818 bfd_boolean saw_arg
= FALSE
;
1819 bfd_boolean saw_colon
= FALSE
;
1821 char *arg_end
, *arg
;
1824 /* Save and restore input_line_pointer around this function. */
1825 old_input_line_pointer
= input_line_pointer
;
1826 input_line_pointer
= str
;
1828 while (*input_line_pointer
)
1831 switch (*input_line_pointer
)
1838 input_line_pointer
++;
1839 if (saw_comma
|| saw_colon
|| !saw_arg
)
1845 input_line_pointer
++;
1846 if (saw_comma
|| saw_colon
|| !saw_arg
)
1852 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1855 arg_end
= input_line_pointer
+ 1;
1856 while (!expression_end (arg_end
))
1859 arg_len
= arg_end
- input_line_pointer
;
1860 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1861 args
[num_args
] = arg
;
1865 strncpy (arg
, input_line_pointer
, arg_len
);
1866 arg
[arg_len
] = '\0';
1868 input_line_pointer
= arg_end
;
1878 if (saw_comma
|| saw_colon
)
1880 input_line_pointer
= old_input_line_pointer
;
1885 as_bad (_("extra comma"));
1887 as_bad (_("extra colon"));
1889 as_bad (_("missing argument"));
1891 as_bad (_("missing comma or colon"));
1892 input_line_pointer
= old_input_line_pointer
;
1897 /* Parse the arguments to an opcode. Return TRUE on error. */
1900 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1902 expressionS
*tok
, *last_tok
;
1903 xtensa_opcode opcode
= insn
->opcode
;
1904 bfd_boolean had_error
= TRUE
;
1905 xtensa_isa isa
= xtensa_default_isa
;
1906 int n
, num_regs
= 0;
1907 int opcode_operand_count
;
1908 int opnd_cnt
, last_opnd_cnt
;
1909 unsigned int next_reg
= 0;
1910 char *old_input_line_pointer
;
1912 if (insn
->insn_type
== ITYPE_LITERAL
)
1913 opcode_operand_count
= 1;
1915 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1918 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1920 /* Save and restore input_line_pointer around this function. */
1921 old_input_line_pointer
= input_line_pointer
;
1927 /* Skip invisible operands. */
1928 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1934 for (n
= 0; n
< num_args
; n
++)
1936 input_line_pointer
= arg_strings
[n
];
1937 if (*input_line_pointer
== ':')
1939 xtensa_regfile opnd_rf
;
1940 input_line_pointer
++;
1943 assert (opnd_cnt
> 0);
1945 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1947 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1948 as_warn (_("incorrect register number, ignoring"));
1953 if (opnd_cnt
>= opcode_operand_count
)
1955 as_warn (_("too many arguments"));
1958 assert (opnd_cnt
< MAX_INSN_ARGS
);
1960 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1961 next_reg
= tok
->X_add_number
+ 1;
1963 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1965 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1967 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1968 /* minus 1 because we are seeing one right now */
1974 last_opnd_cnt
= opnd_cnt
;
1981 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1985 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1988 insn
->ntok
= tok
- insn
->tok
;
1992 input_line_pointer
= old_input_line_pointer
;
1998 get_invisible_operands (TInsn
*insn
)
2000 xtensa_isa isa
= xtensa_default_isa
;
2001 static xtensa_insnbuf slotbuf
= NULL
;
2003 xtensa_opcode opc
= insn
->opcode
;
2004 int slot
, opnd
, fmt_found
;
2008 slotbuf
= xtensa_insnbuf_alloc (isa
);
2010 /* Find format/slot where this can be encoded. */
2013 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2015 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2017 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2023 if (fmt_found
) break;
2028 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2032 /* First encode all the visible operands
2033 (to deal with shared field operands). */
2034 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2036 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2037 && (insn
->tok
[opnd
].X_op
== O_register
2038 || insn
->tok
[opnd
].X_op
== O_constant
))
2040 val
= insn
->tok
[opnd
].X_add_number
;
2041 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2042 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2046 /* Then pull out the values for the invisible ones. */
2047 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2049 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2051 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2052 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2053 insn
->tok
[opnd
].X_add_number
= val
;
2054 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2055 insn
->tok
[opnd
].X_op
= O_register
;
2057 insn
->tok
[opnd
].X_op
= O_constant
;
2066 xg_reverse_shift_count (char **cnt_argp
)
2068 char *cnt_arg
, *new_arg
;
2069 cnt_arg
= *cnt_argp
;
2071 /* replace the argument with "31-(argument)" */
2072 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2073 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2076 *cnt_argp
= new_arg
;
2080 /* If "arg" is a constant expression, return non-zero with the value
2084 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2087 char *save_ptr
= input_line_pointer
;
2089 input_line_pointer
= arg
;
2091 input_line_pointer
= save_ptr
;
2093 if (exp
.X_op
== O_constant
)
2095 *valp
= exp
.X_add_number
;
2104 xg_replace_opname (char **popname
, char *newop
)
2107 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2108 strcpy (*popname
, newop
);
2113 xg_check_num_args (int *pnum_args
,
2118 int num_args
= *pnum_args
;
2120 if (num_args
< expected_num
)
2122 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2123 num_args
, opname
, expected_num
);
2127 if (num_args
> expected_num
)
2129 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2130 num_args
, opname
, expected_num
);
2131 while (num_args
-- > expected_num
)
2133 free (arg_strings
[num_args
]);
2134 arg_strings
[num_args
] = 0;
2136 *pnum_args
= expected_num
;
2144 /* If the register is not specified as part of the opcode,
2145 then get it from the operand and move it to the opcode. */
2148 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2150 xtensa_isa isa
= xtensa_default_isa
;
2152 char *opname
, *new_opname
;
2153 const char *sr_name
;
2154 int is_user
, is_write
;
2159 is_user
= (opname
[1] == 'u');
2160 is_write
= (opname
[0] == 'w');
2162 /* Opname == [rw]ur or [rwx]sr... */
2164 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2167 /* Check if the argument is a symbolic register name. */
2168 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2169 /* Handle WSR to "INTSET" as a special case. */
2170 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2171 && !strcasecmp (arg_strings
[1], "intset"))
2172 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2173 if (sr
== XTENSA_UNDEFINED
2174 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2176 /* Maybe it's a register number.... */
2178 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2180 as_bad (_("invalid register '%s' for '%s' instruction"),
2181 arg_strings
[1], opname
);
2184 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2185 if (sr
== XTENSA_UNDEFINED
)
2187 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2188 (long) val
, opname
);
2193 /* Remove the last argument, which is now part of the opcode. */
2194 free (arg_strings
[1]);
2198 /* Translate the opcode. */
2199 sr_name
= xtensa_sysreg_name (isa
, sr
);
2200 /* Another special case for "WSR.INTSET".... */
2201 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2203 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2204 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2206 *popname
= new_opname
;
2213 xtensa_translate_old_userreg_ops (char **popname
)
2215 xtensa_isa isa
= xtensa_default_isa
;
2217 char *opname
, *new_opname
;
2218 const char *sr_name
;
2219 bfd_boolean has_underbar
= FALSE
;
2222 if (opname
[0] == '_')
2224 has_underbar
= TRUE
;
2228 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2229 if (sr
!= XTENSA_UNDEFINED
)
2231 /* The new default name ("nnn") is different from the old default
2232 name ("URnnn"). The old default is handled below, and we don't
2233 want to recognize [RW]nnn, so do nothing if the name is the (new)
2235 static char namebuf
[10];
2236 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2237 if (strcmp (namebuf
, opname
+ 1) == 0)
2245 /* Only continue if the reg name is "URnnn". */
2246 if (opname
[1] != 'u' || opname
[2] != 'r')
2248 val
= strtoul (opname
+ 3, &end
, 10);
2252 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2253 if (sr
== XTENSA_UNDEFINED
)
2255 as_bad (_("invalid register number (%ld) for '%s'"),
2256 (long) val
, opname
);
2261 /* Translate the opcode. */
2262 sr_name
= xtensa_sysreg_name (isa
, sr
);
2263 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2264 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2265 opname
[0], sr_name
);
2267 *popname
= new_opname
;
2274 xtensa_translate_zero_immed (char *old_op
,
2284 assert (opname
[0] != '_');
2286 if (strcmp (opname
, old_op
) != 0)
2289 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2291 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2293 xg_replace_opname (popname
, new_op
);
2294 free (arg_strings
[1]);
2295 arg_strings
[1] = arg_strings
[2];
2304 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2305 Returns non-zero if an error was found. */
2308 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2310 char *opname
= *popname
;
2311 bfd_boolean has_underbar
= FALSE
;
2315 has_underbar
= TRUE
;
2319 if (strcmp (opname
, "mov") == 0)
2321 if (use_transform () && !has_underbar
&& density_supported
)
2322 xg_replace_opname (popname
, "mov.n");
2325 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2327 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2328 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2329 strcpy (arg_strings
[2], arg_strings
[1]);
2335 if (strcmp (opname
, "bbsi.l") == 0)
2337 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2339 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2340 if (target_big_endian
)
2341 xg_reverse_shift_count (&arg_strings
[1]);
2345 if (strcmp (opname
, "bbci.l") == 0)
2347 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2349 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2350 if (target_big_endian
)
2351 xg_reverse_shift_count (&arg_strings
[1]);
2355 /* Don't do anything special with NOPs inside FLIX instructions. They
2356 are handled elsewhere. Real NOP instructions are always available
2357 in configurations with FLIX, so this should never be an issue but
2358 check for it anyway. */
2359 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2360 && strcmp (opname
, "nop") == 0)
2362 if (use_transform () && !has_underbar
&& density_supported
)
2363 xg_replace_opname (popname
, "nop.n");
2366 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2368 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2369 arg_strings
[0] = (char *) xmalloc (3);
2370 arg_strings
[1] = (char *) xmalloc (3);
2371 arg_strings
[2] = (char *) xmalloc (3);
2372 strcpy (arg_strings
[0], "a1");
2373 strcpy (arg_strings
[1], "a1");
2374 strcpy (arg_strings
[2], "a1");
2380 /* Recognize [RW]UR and [RWX]SR. */
2381 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2382 && (opname
[1] == 'u' || opname
[1] == 's'))
2383 || (opname
[0] == 'x' && opname
[1] == 's'))
2385 && opname
[3] == '\0')
2386 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2388 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2389 [RW]<name> if <name> is the non-default name of a user register. */
2390 if ((opname
[0] == 'r' || opname
[0] == 'w')
2391 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2392 return xtensa_translate_old_userreg_ops (popname
);
2394 /* Relax branches that don't allow comparisons against an immediate value
2395 of zero to the corresponding branches with implicit zero immediates. */
2396 if (!has_underbar
&& use_transform ())
2398 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2399 pnum_args
, arg_strings
))
2402 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2403 pnum_args
, arg_strings
))
2406 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2407 pnum_args
, arg_strings
))
2410 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2411 pnum_args
, arg_strings
))
2419 /* Functions for dealing with the Xtensa ISA. */
2421 /* Currently the assembler only allows us to use a single target per
2422 fragment. Because of this, only one operand for a given
2423 instruction may be symbolic. If there is a PC-relative operand,
2424 the last one is chosen. Otherwise, the result is the number of the
2425 last immediate operand, and if there are none of those, we fail and
2429 get_relaxable_immed (xtensa_opcode opcode
)
2431 int last_immed
= -1;
2434 if (opcode
== XTENSA_UNDEFINED
)
2437 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2438 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2440 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2442 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2444 if (last_immed
== -1
2445 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2452 static xtensa_opcode
2453 get_opcode_from_buf (const char *buf
, int slot
)
2455 static xtensa_insnbuf insnbuf
= NULL
;
2456 static xtensa_insnbuf slotbuf
= NULL
;
2457 xtensa_isa isa
= xtensa_default_isa
;
2462 insnbuf
= xtensa_insnbuf_alloc (isa
);
2463 slotbuf
= xtensa_insnbuf_alloc (isa
);
2466 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2467 fmt
= xtensa_format_decode (isa
, insnbuf
);
2468 if (fmt
== XTENSA_UNDEFINED
)
2469 return XTENSA_UNDEFINED
;
2471 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2472 return XTENSA_UNDEFINED
;
2474 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2475 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2479 #ifdef TENSILICA_DEBUG
2481 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2484 xtensa_print_insn_table (void)
2486 int num_opcodes
, num_operands
;
2487 xtensa_opcode opcode
;
2488 xtensa_isa isa
= xtensa_default_isa
;
2490 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2491 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2494 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2495 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2496 for (opn
= 0; opn
< num_operands
; opn
++)
2498 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2500 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2502 xtensa_regfile opnd_rf
=
2503 xtensa_operand_regfile (isa
, opcode
, opn
);
2504 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2506 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2507 fputs ("[lLr] ", stderr
);
2509 fputs ("i ", stderr
);
2511 fprintf (stderr
, "\n");
2517 print_vliw_insn (xtensa_insnbuf vbuf
)
2519 xtensa_isa isa
= xtensa_default_isa
;
2520 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2521 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2524 fprintf (stderr
, "format = %d\n", f
);
2526 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2528 xtensa_opcode opcode
;
2532 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2533 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2534 opname
= xtensa_opcode_name (isa
, opcode
);
2536 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2537 fprintf (stderr
, " operands = ");
2539 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2543 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2545 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2546 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2547 fprintf (stderr
, "%d ", val
);
2549 fprintf (stderr
, "\n");
2551 xtensa_insnbuf_free (isa
, sbuf
);
2554 #endif /* TENSILICA_DEBUG */
2558 is_direct_call_opcode (xtensa_opcode opcode
)
2560 xtensa_isa isa
= xtensa_default_isa
;
2561 int n
, num_operands
;
2563 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2566 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2567 for (n
= 0; n
< num_operands
; n
++)
2569 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2570 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2577 /* Convert from BFD relocation type code to slot and operand number.
2578 Returns non-zero on failure. */
2581 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2583 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2584 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2586 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2589 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2590 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2592 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2602 /* Convert from slot number to BFD relocation type code for the
2603 standard PC-relative relocations. Return BFD_RELOC_NONE on
2606 static bfd_reloc_code_real_type
2607 encode_reloc (int slot
)
2609 if (slot
< 0 || slot
> 14)
2610 return BFD_RELOC_NONE
;
2612 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2616 /* Convert from slot numbers to BFD relocation type code for the
2617 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2619 static bfd_reloc_code_real_type
2620 encode_alt_reloc (int slot
)
2622 if (slot
< 0 || slot
> 14)
2623 return BFD_RELOC_NONE
;
2625 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2630 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2633 xtensa_opcode opcode
,
2639 uint32 valbuf
= value
;
2641 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2643 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2645 as_bad_where ((char *) file
, line
,
2646 _("operand %d of '%s' has out of range value '%u'"),
2648 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2651 as_bad_where ((char *) file
, line
,
2652 _("operand %d of '%s' has invalid value '%u'"),
2654 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2659 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2665 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2668 xtensa_opcode opcode
,
2672 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2673 fmt
, slot
, slotbuf
, &val
);
2674 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2679 /* Checks for rules from xtensa-relax tables. */
2681 /* The routine xg_instruction_matches_option_term must return TRUE
2682 when a given option term is true. The meaning of all of the option
2683 terms is given interpretation by this function. This is needed when
2684 an option depends on the state of a directive, but there are no such
2685 options in use right now. */
2688 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2689 const ReqOrOption
*option
)
2691 if (strcmp (option
->option_name
, "realnop") == 0
2692 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2694 /* These conditions were evaluated statically when building the
2695 relaxation table. There's no need to reevaluate them now. */
2700 as_fatal (_("internal error: unknown option name '%s'"),
2701 option
->option_name
);
2707 xg_instruction_matches_or_options (TInsn
*insn
,
2708 const ReqOrOptionList
*or_option
)
2710 const ReqOrOption
*option
;
2711 /* Must match each of the AND terms. */
2712 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2714 if (xg_instruction_matches_option_term (insn
, option
))
2722 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2724 const ReqOption
*req_options
;
2725 /* Must match each of the AND terms. */
2726 for (req_options
= options
;
2727 req_options
!= NULL
;
2728 req_options
= req_options
->next
)
2730 /* Must match one of the OR clauses. */
2731 if (!xg_instruction_matches_or_options (insn
,
2732 req_options
->or_option_terms
))
2739 /* Return the transition rule that matches or NULL if none matches. */
2742 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2744 PreconditionList
*condition_l
;
2746 if (rule
->opcode
!= insn
->opcode
)
2749 for (condition_l
= rule
->conditions
;
2750 condition_l
!= NULL
;
2751 condition_l
= condition_l
->next
)
2755 Precondition
*cond
= condition_l
->precond
;
2760 /* The expression must be the constant. */
2761 assert (cond
->op_num
< insn
->ntok
);
2762 exp1
= &insn
->tok
[cond
->op_num
];
2763 if (expr_is_const (exp1
))
2768 if (get_expr_const (exp1
) != cond
->op_data
)
2772 if (get_expr_const (exp1
) == cond
->op_data
)
2779 else if (expr_is_register (exp1
))
2784 if (get_expr_register (exp1
) != cond
->op_data
)
2788 if (get_expr_register (exp1
) == cond
->op_data
)
2800 assert (cond
->op_num
< insn
->ntok
);
2801 assert (cond
->op_data
< insn
->ntok
);
2802 exp1
= &insn
->tok
[cond
->op_num
];
2803 exp2
= &insn
->tok
[cond
->op_data
];
2808 if (!expr_is_equal (exp1
, exp2
))
2812 if (expr_is_equal (exp1
, exp2
))
2824 if (!xg_instruction_matches_options (insn
, rule
->options
))
2832 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2834 bfd_boolean a_greater
= FALSE
;
2835 bfd_boolean b_greater
= FALSE
;
2837 ReqOptionList
*l_a
= a
->options
;
2838 ReqOptionList
*l_b
= b
->options
;
2840 /* We only care if they both are the same except for
2841 a const16 vs. an l32r. */
2843 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2845 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2846 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2847 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2849 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2851 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2853 /* This is the case we care about. */
2854 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2855 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2862 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2863 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2873 l_or_a
= l_or_a
->next
;
2874 l_or_b
= l_or_b
->next
;
2876 if (l_or_a
|| l_or_b
)
2885 /* Incomparable if the substitution was used differently in two cases. */
2886 if (a_greater
&& b_greater
)
2898 static TransitionRule
*
2899 xg_instruction_match (TInsn
*insn
)
2901 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2903 assert (insn
->opcode
< table
->num_opcodes
);
2905 /* Walk through all of the possible transitions. */
2906 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2908 TransitionRule
*rule
= l
->rule
;
2909 if (xg_instruction_matches_rule (insn
, rule
))
2916 /* Various Other Internal Functions. */
2919 is_unique_insn_expansion (TransitionRule
*r
)
2921 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2923 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2929 /* Check if there is exactly one relaxation for INSN that converts it to
2930 another instruction of equal or larger size. If so, and if TARG is
2931 non-null, go ahead and generate the relaxed instruction into TARG. If
2932 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2933 instruction, i.e., ignore relaxations that convert to an instruction of
2934 equal size. In some contexts where this function is used, only
2935 a single widening is allowed and the NARROW_ONLY argument is used to
2936 exclude cases like ADDI being "widened" to an ADDMI, which may
2937 later be relaxed to an ADDMI/ADDI pair. */
2940 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2942 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2944 TransitionRule
*match
= 0;
2946 assert (insn
->insn_type
== ITYPE_INSN
);
2947 assert (insn
->opcode
< table
->num_opcodes
);
2949 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2951 TransitionRule
*rule
= l
->rule
;
2953 if (xg_instruction_matches_rule (insn
, rule
)
2954 && is_unique_insn_expansion (rule
)
2955 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2956 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2967 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2972 /* Return the maximum number of bytes this opcode can expand to. */
2975 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2977 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2979 int max_size
= xg_get_single_size (opcode
);
2981 assert (opcode
< table
->num_opcodes
);
2983 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2985 TransitionRule
*rule
= l
->rule
;
2986 BuildInstr
*build_list
;
2991 build_list
= rule
->to_instr
;
2992 if (is_unique_insn_expansion (rule
))
2994 assert (build_list
->typ
== INSTR_INSTR
);
2995 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
2998 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3000 switch (build_list
->typ
)
3003 this_size
+= xg_get_single_size (build_list
->opcode
);
3005 case INSTR_LITERAL_DEF
:
3006 case INSTR_LABEL_DEF
:
3011 if (this_size
> max_size
)
3012 max_size
= this_size
;
3018 /* Return the maximum number of literal bytes this opcode can generate. */
3021 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3023 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3027 assert (opcode
< table
->num_opcodes
);
3029 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3031 TransitionRule
*rule
= l
->rule
;
3032 BuildInstr
*build_list
;
3037 build_list
= rule
->to_instr
;
3038 if (is_unique_insn_expansion (rule
))
3040 assert (build_list
->typ
== INSTR_INSTR
);
3041 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3044 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3046 switch (build_list
->typ
)
3048 case INSTR_LITERAL_DEF
:
3049 /* Hard-coded 4-byte literal. */
3053 case INSTR_LABEL_DEF
:
3058 if (this_size
> max_size
)
3059 max_size
= this_size
;
3066 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3068 int steps_taken
= 0;
3069 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3072 assert (insn
->insn_type
== ITYPE_INSN
);
3073 assert (insn
->opcode
< table
->num_opcodes
);
3075 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3077 TransitionRule
*rule
= l
->rule
;
3079 if (xg_instruction_matches_rule (insn
, rule
))
3081 if (steps_taken
== lateral_steps
)
3091 get_special_literal_symbol (void)
3093 static symbolS
*sym
= NULL
;
3096 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3102 get_special_label_symbol (void)
3104 static symbolS
*sym
= NULL
;
3107 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3113 xg_valid_literal_expression (const expressionS
*exp
)
3130 /* This will check to see if the value can be converted into the
3131 operand type. It will return TRUE if it does not fit. */
3134 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3136 uint32 valbuf
= value
;
3137 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3143 /* Assumes: All immeds are constants. Check that all constants fit
3144 into their immeds; return FALSE if not. */
3147 xg_immeds_fit (const TInsn
*insn
)
3149 xtensa_isa isa
= xtensa_default_isa
;
3153 assert (insn
->insn_type
== ITYPE_INSN
);
3154 for (i
= 0; i
< n
; ++i
)
3156 const expressionS
*expr
= &insn
->tok
[i
];
3157 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3164 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3169 /* The symbol should have a fixup associated with it. */
3178 /* This should only be called after we have an initial
3179 estimate of the addresses. */
3182 xg_symbolic_immeds_fit (const TInsn
*insn
,
3188 xtensa_isa isa
= xtensa_default_isa
;
3196 assert (insn
->insn_type
== ITYPE_INSN
);
3198 for (i
= 0; i
< n
; ++i
)
3200 const expressionS
*expr
= &insn
->tok
[i
];
3201 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3208 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3214 /* Check for the worst case. */
3215 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3220 /* We only allow symbols for PC-relative references.
3221 If pc_frag == 0, then we don't have frag locations yet. */
3223 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3226 /* If it is a weak symbol, then assume it won't reach. */
3227 if (S_IS_WEAK (expr
->X_add_symbol
))
3230 if (is_direct_call_opcode (insn
->opcode
)
3231 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3233 /* If callee is undefined or in a different segment, be
3234 optimistic and assume it will be in range. */
3235 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3239 /* Only references within a segment can be known to fit in the
3240 operands at assembly time. */
3241 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3244 symbolP
= expr
->X_add_symbol
;
3245 sym_frag
= symbol_get_frag (symbolP
);
3246 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3247 pc
= pc_frag
->fr_address
+ pc_offset
;
3249 /* If frag has yet to be reached on this pass, assume it
3250 will move by STRETCH just as we did. If this is not so,
3251 it will be because some frag between grows, and that will
3252 force another pass. Beware zero-length frags. There
3253 should be a faster way to do this. */
3256 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3257 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3262 new_offset
= target
;
3263 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3264 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3269 /* The symbol should have a fixup associated with it. */
3278 /* Return TRUE on success. */
3281 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3287 targ
->linenum
= insn
->linenum
;
3292 targ
->opcode
= bi
->opcode
;
3293 targ
->insn_type
= ITYPE_INSN
;
3294 targ
->is_specific_opcode
= FALSE
;
3296 for (; op
!= NULL
; op
= op
->next
)
3298 int op_num
= op
->op_num
;
3299 int op_data
= op
->op_data
;
3301 assert (op
->op_num
< MAX_INSN_ARGS
);
3303 if (targ
->ntok
<= op_num
)
3304 targ
->ntok
= op_num
+ 1;
3309 set_expr_const (&targ
->tok
[op_num
], op_data
);
3312 assert (op_data
< insn
->ntok
);
3313 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3316 sym
= get_special_literal_symbol ();
3317 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3320 sym
= get_special_label_symbol ();
3321 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3323 case OP_OPERAND_HI16U
:
3324 case OP_OPERAND_LOW16U
:
3325 assert (op_data
< insn
->ntok
);
3326 if (expr_is_const (&insn
->tok
[op_data
]))
3329 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3330 val
= xg_apply_userdef_op_fn (op
->typ
,
3333 targ
->tok
[op_num
].X_add_number
= val
;
3337 /* For const16 we can create relocations for these. */
3338 if (targ
->opcode
== XTENSA_UNDEFINED
3339 || (targ
->opcode
!= xtensa_const16_opcode
))
3341 assert (op_data
< insn
->ntok
);
3342 /* Need to build a O_lo16 or O_hi16. */
3343 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3344 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3346 if (op
->typ
== OP_OPERAND_HI16U
)
3347 targ
->tok
[op_num
].X_op
= O_hi16
;
3348 else if (op
->typ
== OP_OPERAND_LOW16U
)
3349 targ
->tok
[op_num
].X_op
= O_lo16
;
3356 /* currently handles:
3359 OP_OPERAND_F32MINUS */
3360 if (xg_has_userdef_op_fn (op
->typ
))
3362 assert (op_data
< insn
->ntok
);
3363 if (expr_is_const (&insn
->tok
[op_data
]))
3366 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3367 val
= xg_apply_userdef_op_fn (op
->typ
,
3370 targ
->tok
[op_num
].X_add_number
= val
;
3373 return FALSE
; /* We cannot use a relocation for this. */
3382 case INSTR_LITERAL_DEF
:
3384 targ
->opcode
= XTENSA_UNDEFINED
;
3385 targ
->insn_type
= ITYPE_LITERAL
;
3386 targ
->is_specific_opcode
= FALSE
;
3387 for (; op
!= NULL
; op
= op
->next
)
3389 int op_num
= op
->op_num
;
3390 int op_data
= op
->op_data
;
3391 assert (op
->op_num
< MAX_INSN_ARGS
);
3393 if (targ
->ntok
<= op_num
)
3394 targ
->ntok
= op_num
+ 1;
3399 assert (op_data
< insn
->ntok
);
3400 /* We can only pass resolvable literals through. */
3401 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3403 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3415 case INSTR_LABEL_DEF
:
3417 targ
->opcode
= XTENSA_UNDEFINED
;
3418 targ
->insn_type
= ITYPE_LABEL
;
3419 targ
->is_specific_opcode
= FALSE
;
3420 /* Literal with no ops is a label? */
3421 assert (op
== NULL
);
3432 /* Return TRUE on success. */
3435 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3437 for (; bi
!= NULL
; bi
= bi
->next
)
3439 TInsn
*next_insn
= istack_push_space (istack
);
3441 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3448 /* Return TRUE on valid expansion. */
3451 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3453 int stack_size
= istack
->ninsn
;
3454 int steps_taken
= 0;
3455 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3458 assert (insn
->insn_type
== ITYPE_INSN
);
3459 assert (insn
->opcode
< table
->num_opcodes
);
3461 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3463 TransitionRule
*rule
= l
->rule
;
3465 if (xg_instruction_matches_rule (insn
, rule
))
3467 if (lateral_steps
== steps_taken
)
3471 /* This is it. Expand the rule to the stack. */
3472 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3475 /* Check to see if it fits. */
3476 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3478 TInsn
*insn
= &istack
->insn
[i
];
3480 if (insn
->insn_type
== ITYPE_INSN
3481 && !tinsn_has_symbolic_operands (insn
)
3482 && !xg_immeds_fit (insn
))
3484 istack
->ninsn
= stack_size
;
3497 /* Relax the assembly instruction at least "min_steps".
3498 Return the number of steps taken. */
3501 xg_assembly_relax (IStack
*istack
,
3504 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3505 offsetT pc_offset
, /* offset in fragment */
3506 int min_steps
, /* minimum conversion steps */
3507 long stretch
) /* number of bytes stretched so far */
3509 int steps_taken
= 0;
3511 /* assert (has no symbolic operands)
3512 Some of its immeds don't fit.
3513 Try to build a relaxed version.
3514 This may go through a couple of stages
3515 of single instruction transformations before
3518 TInsn single_target
;
3520 int lateral_steps
= 0;
3521 int istack_size
= istack
->ninsn
;
3523 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3524 && steps_taken
>= min_steps
)
3526 istack_push (istack
, insn
);
3529 current_insn
= *insn
;
3531 /* Walk through all of the single instruction expansions. */
3532 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3535 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3538 if (steps_taken
>= min_steps
)
3540 istack_push (istack
, &single_target
);
3544 current_insn
= single_target
;
3547 /* Now check for a multi-instruction expansion. */
3548 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3550 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3553 if (steps_taken
>= min_steps
)
3555 istack_push (istack
, ¤t_insn
);
3560 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3562 if (steps_taken
>= min_steps
)
3566 istack
->ninsn
= istack_size
;
3569 /* It's not going to work -- use the original. */
3570 istack_push (istack
, insn
);
3576 xg_force_frag_space (int size
)
3578 /* This may have the side effect of creating a new fragment for the
3579 space to go into. I just do not like the name of the "frag"
3586 xg_finish_frag (char *last_insn
,
3587 enum xtensa_relax_statesE frag_state
,
3588 enum xtensa_relax_statesE slot0_state
,
3590 bfd_boolean is_insn
)
3592 /* Finish off this fragment so that it has at LEAST the desired
3593 max_growth. If it doesn't fit in this fragment, close this one
3594 and start a new one. In either case, return a pointer to the
3595 beginning of the growth area. */
3599 xg_force_frag_space (max_growth
);
3601 old_frag
= frag_now
;
3603 frag_now
->fr_opcode
= last_insn
;
3605 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3607 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3608 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3610 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3611 xtensa_set_frag_assembly_state (frag_now
);
3613 /* Just to make sure that we did not split it up. */
3614 assert (old_frag
->fr_next
== frag_now
);
3618 /* Return TRUE if the target frag is one of the next non-empty frags. */
3621 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3626 for (; fragP
; fragP
= fragP
->fr_next
)
3628 if (fragP
== target
)
3630 if (fragP
->fr_fix
!= 0)
3632 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3634 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3635 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3637 if (fragP
->fr_type
== rs_space
)
3645 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3647 xtensa_isa isa
= xtensa_default_isa
;
3649 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3654 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3655 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3658 for (i
= 0; i
< num_ops
; i
++)
3660 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3666 if (target_op
== -1)
3669 if (insn
->ntok
<= target_op
)
3672 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3675 sym
= insn
->tok
[target_op
].X_add_symbol
;
3679 if (insn
->tok
[target_op
].X_add_number
!= 0)
3682 target_frag
= symbol_get_frag (sym
);
3683 if (target_frag
== NULL
)
3686 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3687 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3695 xg_add_branch_and_loop_targets (TInsn
*insn
)
3697 xtensa_isa isa
= xtensa_default_isa
;
3698 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3700 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3703 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3704 && insn
->tok
[i
].X_op
== O_symbol
)
3705 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3709 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3710 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3714 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3716 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3717 && insn
->tok
[i
].X_op
== O_symbol
)
3719 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3720 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3721 if (S_IS_DEFINED (sym
))
3722 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3729 /* Return FALSE if no error. */
3732 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3737 switch (instr_spec
->typ
)
3740 new_insn
->insn_type
= ITYPE_INSN
;
3741 new_insn
->opcode
= instr_spec
->opcode
;
3742 new_insn
->is_specific_opcode
= FALSE
;
3743 new_insn
->linenum
= old_insn
->linenum
;
3745 case INSTR_LITERAL_DEF
:
3746 new_insn
->insn_type
= ITYPE_LITERAL
;
3747 new_insn
->opcode
= XTENSA_UNDEFINED
;
3748 new_insn
->is_specific_opcode
= FALSE
;
3749 new_insn
->linenum
= old_insn
->linenum
;
3751 case INSTR_LABEL_DEF
:
3752 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3756 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3759 const expressionS
*src_exp
;
3765 /* The expression must be the constant. */
3766 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3767 exp
= &new_insn
->tok
[b_op
->op_num
];
3768 set_expr_const (exp
, b_op
->op_data
);
3772 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3773 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3774 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3775 exp
= &new_insn
->tok
[b_op
->op_num
];
3776 copy_expr (exp
, src_exp
);
3781 as_bad (_("can't handle generation of literal/labels yet"));
3785 as_bad (_("can't handle undefined OP TYPE"));
3790 new_insn
->ntok
= num_ops
;
3795 /* Return TRUE if it was simplified. */
3798 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3800 TransitionRule
*rule
;
3801 BuildInstr
*insn_spec
;
3803 if (old_insn
->is_specific_opcode
|| !density_supported
)
3806 rule
= xg_instruction_match (old_insn
);
3810 insn_spec
= rule
->to_instr
;
3811 /* There should only be one. */
3812 assert (insn_spec
!= NULL
);
3813 assert (insn_spec
->next
== NULL
);
3814 if (insn_spec
->next
!= NULL
)
3817 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3823 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3824 l32i.n. (2) Check the number of operands. (3) Place the instruction
3825 tokens into the stack or relax it and place multiple
3826 instructions/literals onto the stack. Return FALSE if no error. */
3829 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3833 bfd_boolean do_expand
;
3835 tinsn_init (&new_insn
);
3837 /* Narrow it if we can. xg_simplify_insn now does all the
3838 appropriate checking (e.g., for the density option). */
3839 if (xg_simplify_insn (orig_insn
, &new_insn
))
3840 orig_insn
= &new_insn
;
3842 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3844 if (orig_insn
->ntok
< noperands
)
3846 as_bad (_("found %d operands for '%s': Expected %d"),
3848 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3852 if (orig_insn
->ntok
> noperands
)
3853 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3855 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3858 /* If there are not enough operands, we will assert above. If there
3859 are too many, just cut out the extras here. */
3860 orig_insn
->ntok
= noperands
;
3862 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3865 /* If the instruction will definitely need to be relaxed, it is better
3866 to expand it now for better scheduling. Decide whether to expand
3868 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3870 /* Calls should be expanded to longcalls only in the backend relaxation
3871 so that the assembly scheduler will keep the L32R/CALLX instructions
3873 if (is_direct_call_opcode (orig_insn
->opcode
))
3876 if (tinsn_has_symbolic_operands (orig_insn
))
3878 /* The values of symbolic operands are not known yet, so only expand
3879 now if an operand is "complex" (e.g., difference of symbols) and
3880 will have to be stored as a literal regardless of the value. */
3881 if (!tinsn_has_complex_operands (orig_insn
))
3884 else if (xg_immeds_fit (orig_insn
))
3888 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3890 istack_push (istack
, orig_insn
);
3896 /* Return TRUE if the section flags are marked linkonce
3897 or the name is .gnu.linkonce.*. */
3899 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3902 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3904 flagword flags
, link_once_flags
;
3906 flags
= bfd_get_section_flags (abfd
, sec
);
3907 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3909 /* Flags might not be set yet. */
3910 if (!link_once_flags
3911 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3912 link_once_flags
= SEC_LINK_ONCE
;
3914 return (link_once_flags
!= 0);
3919 xtensa_add_literal_sym (symbolS
*sym
)
3923 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3925 l
->next
= literal_syms
;
3931 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3933 static int lit_num
= 0;
3934 static char name
[256];
3937 sprintf (name
, ".L_lit_sym%d", lit_num
);
3939 /* Create a local symbol. If it is in a linkonce section, we have to
3940 be careful to make sure that if it is used in a relocation that the
3941 symbol will be in the output file. */
3942 if (get_is_linkonce_section (stdoutput
, sec
))
3944 symbolP
= symbol_new (name
, sec
, 0, frag
);
3945 S_CLEAR_EXTERNAL (symbolP
);
3946 /* symbolP->local = 1; */
3949 symbolP
= symbol_new (name
, sec
, 0, frag
);
3951 xtensa_add_literal_sym (symbolP
);
3958 /* Currently all literals that are generated here are 32-bit L32R targets. */
3961 xg_assemble_literal (/* const */ TInsn
*insn
)
3964 symbolS
*lit_sym
= NULL
;
3965 bfd_reloc_code_real_type reloc
;
3968 /* size = 4 for L32R. It could easily be larger when we move to
3969 larger constants. Add a parameter later. */
3970 offsetT litsize
= 4;
3971 offsetT litalign
= 2; /* 2^2 = 4 */
3972 expressionS saved_loc
;
3973 expressionS
* emit_val
;
3975 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
3977 assert (insn
->insn_type
== ITYPE_LITERAL
);
3978 assert (insn
->ntok
== 1); /* must be only one token here */
3980 xtensa_switch_to_literal_fragment (&state
);
3982 emit_val
= &insn
->tok
[0];
3983 if (emit_val
->X_op
== O_big
)
3985 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
3988 /* This happens when someone writes a "movi a2, big_number". */
3989 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3990 _("invalid immediate"));
3991 xtensa_restore_emit_state (&state
);
3996 /* Force a 4-byte align here. Note that this opens a new frag, so all
3997 literals done with this function have a frag to themselves. That's
3998 important for the way text section literals work. */
3999 frag_align (litalign
, 0, 0);
4000 record_alignment (now_seg
, litalign
);
4002 switch (emit_val
->X_op
)
4005 p
= frag_more (litsize
);
4006 xtensa_set_frag_assembly_state (frag_now
);
4007 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4008 if (emit_val
->X_add_symbol
)
4009 emit_val
->X_op
= O_symbol
;
4011 emit_val
->X_op
= O_constant
;
4012 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4013 litsize
, emit_val
, 0, reloc
);
4017 emit_expr (emit_val
, litsize
);
4021 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4022 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4023 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4024 lit_sym
= frag_now
->fr_symbol
;
4027 xtensa_restore_emit_state (&state
);
4033 xg_assemble_literal_space (/* const */ int size
, int slot
)
4036 /* We might have to do something about this alignment. It only
4037 takes effect if something is placed here. */
4038 offsetT litalign
= 2; /* 2^2 = 4 */
4039 fragS
*lit_saved_frag
;
4041 assert (size
% 4 == 0);
4043 xtensa_switch_to_literal_fragment (&state
);
4045 /* Force a 4-byte align here. */
4046 frag_align (litalign
, 0, 0);
4047 record_alignment (now_seg
, litalign
);
4049 xg_force_frag_space (size
);
4051 lit_saved_frag
= frag_now
;
4052 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4053 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4054 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4057 xtensa_restore_emit_state (&state
);
4058 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4062 /* Put in a fixup record based on the opcode.
4063 Return TRUE on success. */
4066 xg_add_opcode_fix (TInsn
*tinsn
,
4074 xtensa_opcode opcode
= tinsn
->opcode
;
4075 bfd_reloc_code_real_type reloc
;
4076 reloc_howto_type
*howto
;
4080 reloc
= BFD_RELOC_NONE
;
4082 /* First try the special cases for "alternate" relocs. */
4083 if (opcode
== xtensa_l32r_opcode
)
4085 if (fragP
->tc_frag_data
.use_absolute_literals
)
4086 reloc
= encode_alt_reloc (slot
);
4088 else if (opcode
== xtensa_const16_opcode
)
4090 if (expr
->X_op
== O_lo16
)
4092 reloc
= encode_reloc (slot
);
4093 expr
->X_op
= O_symbol
;
4095 else if (expr
->X_op
== O_hi16
)
4097 reloc
= encode_alt_reloc (slot
);
4098 expr
->X_op
= O_symbol
;
4102 if (opnum
!= get_relaxable_immed (opcode
))
4104 as_bad (_("invalid relocation for operand %i of '%s'"),
4105 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4109 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4110 into the symbol table where the generic portions of the assembler
4111 won't know what to do with them. */
4112 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4114 as_bad (_("invalid expression for operand %i of '%s'"),
4115 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4119 /* Next try the generic relocs. */
4120 if (reloc
== BFD_RELOC_NONE
)
4121 reloc
= encode_reloc (slot
);
4122 if (reloc
== BFD_RELOC_NONE
)
4124 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4128 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4131 as_bad (_("undefined symbol for opcode \"%s\""),
4132 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4136 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4137 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4138 howto
->pc_relative
, reloc
);
4139 the_fix
->fx_no_overflow
= 1;
4140 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4141 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4142 the_fix
->tc_fix_data
.slot
= slot
;
4149 xg_emit_insn_to_buf (TInsn
*tinsn
,
4153 bfd_boolean build_fix
)
4155 static xtensa_insnbuf insnbuf
= NULL
;
4156 bfd_boolean has_symbolic_immed
= FALSE
;
4157 bfd_boolean ok
= TRUE
;
4160 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4162 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4163 if (has_symbolic_immed
&& build_fix
)
4166 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4167 int slot
= xg_get_single_slot (tinsn
->opcode
);
4168 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4169 expressionS
*exp
= &tinsn
->tok
[opnum
];
4171 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4174 fragP
->tc_frag_data
.is_insn
= TRUE
;
4175 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4176 (unsigned char *) buf
, 0);
4182 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4184 symbolS
*sym
= get_special_literal_symbol ();
4188 assert (insn
->insn_type
== ITYPE_INSN
);
4189 for (i
= 0; i
< insn
->ntok
; i
++)
4190 if (insn
->tok
[i
].X_add_symbol
== sym
)
4191 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4197 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4199 symbolS
*sym
= get_special_label_symbol ();
4201 for (i
= 0; i
< insn
->ntok
; i
++)
4202 if (insn
->tok
[i
].X_add_symbol
== sym
)
4203 insn
->tok
[i
].X_add_symbol
= label_sym
;
4208 /* Return TRUE if the instruction can write to the specified
4209 integer register. */
4212 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4216 xtensa_isa isa
= xtensa_default_isa
;
4218 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4220 for (i
= 0; i
< num_ops
; i
++)
4223 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4224 if ((inout
== 'o' || inout
== 'm')
4225 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4227 xtensa_regfile opnd_rf
=
4228 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4229 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4231 if ((insn
->tok
[i
].X_op
== O_register
)
4232 && (insn
->tok
[i
].X_add_number
== regnum
))
4242 is_bad_loopend_opcode (const TInsn
*tinsn
)
4244 xtensa_opcode opcode
= tinsn
->opcode
;
4246 if (opcode
== XTENSA_UNDEFINED
)
4249 if (opcode
== xtensa_call0_opcode
4250 || opcode
== xtensa_callx0_opcode
4251 || opcode
== xtensa_call4_opcode
4252 || opcode
== xtensa_callx4_opcode
4253 || opcode
== xtensa_call8_opcode
4254 || opcode
== xtensa_callx8_opcode
4255 || opcode
== xtensa_call12_opcode
4256 || opcode
== xtensa_callx12_opcode
4257 || opcode
== xtensa_isync_opcode
4258 || opcode
== xtensa_ret_opcode
4259 || opcode
== xtensa_ret_n_opcode
4260 || opcode
== xtensa_retw_opcode
4261 || opcode
== xtensa_retw_n_opcode
4262 || opcode
== xtensa_waiti_opcode
4263 || opcode
== xtensa_rsr_lcount_opcode
)
4270 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4271 This allows the debugger to add unaligned labels.
4272 Also, the assembler generates stabs labels that need
4273 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4276 is_unaligned_label (symbolS
*sym
)
4278 const char *name
= S_GET_NAME (sym
);
4279 static size_t fake_size
= 0;
4283 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4286 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4288 fake_size
= strlen (FAKE_LABEL_NAME
);
4291 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4292 && (name
[fake_size
] == 'F'
4293 || name
[fake_size
] == 'L'
4294 || (name
[fake_size
] == 'e'
4295 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4303 next_non_empty_frag (const fragS
*fragP
)
4305 fragS
*next_fragP
= fragP
->fr_next
;
4307 /* Sometimes an empty will end up here due storage allocation issues.
4308 So we have to skip until we find something legit. */
4309 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4310 next_fragP
= next_fragP
->fr_next
;
4312 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4320 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4322 xtensa_opcode out_opcode
;
4323 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4325 if (next_fragP
== NULL
)
4328 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4329 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4331 *opcode
= out_opcode
;
4339 frag_format_size (const fragS
*fragP
)
4341 static xtensa_insnbuf insnbuf
= NULL
;
4342 xtensa_isa isa
= xtensa_default_isa
;
4347 insnbuf
= xtensa_insnbuf_alloc (isa
);
4350 return XTENSA_UNDEFINED
;
4352 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4353 (unsigned char *) fragP
->fr_literal
, 0);
4355 fmt
= xtensa_format_decode (isa
, insnbuf
);
4356 if (fmt
== XTENSA_UNDEFINED
)
4357 return XTENSA_UNDEFINED
;
4358 fmt_size
= xtensa_format_length (isa
, fmt
);
4360 /* If the next format won't be changing due to relaxation, just
4361 return the length of the first format. */
4362 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4365 /* If during relaxation we have to pull an instruction out of a
4366 multi-slot instruction, we will return the more conservative
4367 number. This works because alignment on bigger instructions
4368 is more restrictive than alignment on smaller instructions.
4369 This is more conservative than we would like, but it happens
4372 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4375 /* If we aren't doing one of our own relaxations or it isn't
4376 slot-based, then the insn size won't change. */
4377 if (fragP
->fr_type
!= rs_machine_dependent
)
4379 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4382 /* If an instruction is about to grow, return the longer size. */
4383 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4384 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4387 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4388 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4395 next_frag_format_size (const fragS
*fragP
)
4397 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4398 return frag_format_size (next_fragP
);
4402 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4403 required two-byte instructions to be treated as three-byte instructions
4404 for loop instruction alignment. This restriction was removed beginning
4405 with Xtensa LX. Now the only requirement on loop instruction alignment
4406 is that the first instruction of the loop must appear at an address that
4407 does not cross a fetch boundary. */
4410 get_loop_align_size (int insn_size
)
4412 if (insn_size
== XTENSA_UNDEFINED
)
4413 return xtensa_fetch_width
;
4415 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4422 /* If the next legit fragment is an end-of-loop marker,
4423 switch its state so it will instantiate a NOP. */
4426 update_next_frag_state (fragS
*fragP
)
4428 fragS
*next_fragP
= fragP
->fr_next
;
4429 fragS
*new_target
= NULL
;
4433 /* We are guaranteed there will be one of these... */
4434 while (!(next_fragP
->fr_type
== rs_machine_dependent
4435 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4436 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4437 next_fragP
= next_fragP
->fr_next
;
4439 assert (next_fragP
->fr_type
== rs_machine_dependent
4440 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4441 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4443 /* ...and one of these. */
4444 new_target
= next_fragP
->fr_next
;
4445 while (!(new_target
->fr_type
== rs_machine_dependent
4446 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4447 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4448 new_target
= new_target
->fr_next
;
4450 assert (new_target
->fr_type
== rs_machine_dependent
4451 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4452 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4455 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4457 if (next_fragP
->fr_type
== rs_machine_dependent
4458 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4460 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4464 next_fragP
= next_fragP
->fr_next
;
4470 next_frag_is_branch_target (const fragS
*fragP
)
4472 /* Sometimes an empty will end up here due to storage allocation issues,
4473 so we have to skip until we find something legit. */
4474 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4476 if (fragP
->tc_frag_data
.is_branch_target
)
4478 if (fragP
->fr_fix
!= 0)
4486 next_frag_is_loop_target (const fragS
*fragP
)
4488 /* Sometimes an empty will end up here due storage allocation issues.
4489 So we have to skip until we find something legit. */
4490 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4492 if (fragP
->tc_frag_data
.is_loop_target
)
4494 if (fragP
->fr_fix
!= 0)
4502 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4504 const fragS
*next_fragp
= fragp
->fr_next
;
4505 xtensa_opcode next_opcode
;
4507 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4510 /* Sometimes an empty will end up here due to storage allocation issues,
4511 so we have to skip until we find something legit. */
4512 while (next_fragp
->fr_fix
== 0)
4513 next_fragp
= next_fragp
->fr_next
;
4515 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4518 /* There is some implicit knowledge encoded in here.
4519 The LOOP instructions that are NOT RELAX_IMMED have
4520 been relaxed. Note that we can assume that the LOOP
4521 instruction is in slot 0 because loops aren't bundleable. */
4522 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4523 return get_expanded_loop_offset (next_opcode
);
4529 /* Mark a location where we can later insert literal frags. Update
4530 the section's literal_pool_loc, so subsequent literals can be
4531 placed nearest to their use. */
4534 xtensa_mark_literal_pool_location (void)
4536 /* Any labels pointing to the current location need
4537 to be adjusted to after the literal pool. */
4539 fragS
*pool_location
;
4541 if (use_literal_section
)
4544 /* We stash info in these frags so we can later move the literal's
4545 fixes into this frchain's fix list. */
4546 pool_location
= frag_now
;
4547 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4548 frag_variant (rs_machine_dependent
, 0, 0,
4549 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4550 xtensa_set_frag_assembly_state (frag_now
);
4551 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4552 frag_variant (rs_machine_dependent
, 0, 0,
4553 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4554 xtensa_set_frag_assembly_state (frag_now
);
4556 /* Now put a frag into the literal pool that points to this location. */
4557 set_literal_pool_location (now_seg
, pool_location
);
4558 xtensa_switch_to_non_abs_literal_fragment (&s
);
4559 frag_align (2, 0, 0);
4560 record_alignment (now_seg
, 2);
4562 /* Close whatever frag is there. */
4563 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4564 xtensa_set_frag_assembly_state (frag_now
);
4565 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4566 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4567 xtensa_restore_emit_state (&s
);
4568 xtensa_set_frag_assembly_state (frag_now
);
4572 /* Build a nop of the correct size into tinsn. */
4575 build_nop (TInsn
*tinsn
, int size
)
4581 tinsn
->opcode
= xtensa_nop_n_opcode
;
4583 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4584 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4588 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4590 tinsn
->opcode
= xtensa_or_opcode
;
4591 set_expr_const (&tinsn
->tok
[0], 1);
4592 set_expr_const (&tinsn
->tok
[1], 1);
4593 set_expr_const (&tinsn
->tok
[2], 1);
4597 tinsn
->opcode
= xtensa_nop_opcode
;
4599 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4604 /* Assemble a NOP of the requested size in the buffer. User must have
4605 allocated "buf" with at least "size" bytes. */
4608 assemble_nop (int size
, char *buf
)
4610 static xtensa_insnbuf insnbuf
= NULL
;
4613 build_nop (&tinsn
, size
);
4616 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4618 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4619 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4620 (unsigned char *) buf
, 0);
4624 /* Return the number of bytes for the offset of the expanded loop
4625 instruction. This should be incorporated into the relaxation
4626 specification but is hard-coded here. This is used to auto-align
4627 the loop instruction. It is invalid to call this function if the
4628 configuration does not have loops or if the opcode is not a loop
4632 get_expanded_loop_offset (xtensa_opcode opcode
)
4634 /* This is the OFFSET of the loop instruction in the expanded loop.
4635 This MUST correspond directly to the specification of the loop
4636 expansion. It will be validated on fragment conversion. */
4637 assert (opcode
!= XTENSA_UNDEFINED
);
4638 if (opcode
== xtensa_loop_opcode
)
4640 if (opcode
== xtensa_loopnez_opcode
)
4642 if (opcode
== xtensa_loopgtz_opcode
)
4644 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4650 get_literal_pool_location (segT seg
)
4652 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4657 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4659 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4663 /* Set frag assembly state should be called when a new frag is
4664 opened and after a frag has been closed. */
4667 xtensa_set_frag_assembly_state (fragS
*fragP
)
4669 if (!density_supported
)
4670 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4672 /* This function is called from subsegs_finish, which is called
4673 after xtensa_end, so we can't use "use_transform" or
4674 "use_schedule" here. */
4675 if (!directive_state
[directive_transform
])
4676 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4677 if (directive_state
[directive_longcalls
])
4678 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4679 fragP
->tc_frag_data
.use_absolute_literals
=
4680 directive_state
[directive_absolute_literals
];
4681 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4686 relaxable_section (asection
*sec
)
4688 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4693 xtensa_find_unmarked_state_frags (void)
4697 /* Walk over each fragment of all of the current segments. For each
4698 unmarked fragment, mark it with the same info as the previous
4700 for (seclist
= &stdoutput
->sections
;
4701 seclist
&& *seclist
;
4702 seclist
= &(*seclist
)->next
)
4704 segT sec
= *seclist
;
4705 segment_info_type
*seginfo
;
4708 flags
= bfd_get_section_flags (stdoutput
, sec
);
4709 if (flags
& SEC_DEBUGGING
)
4711 if (!(flags
& SEC_ALLOC
))
4714 seginfo
= seg_info (sec
);
4715 if (seginfo
&& seginfo
->frchainP
)
4717 fragS
*last_fragP
= 0;
4718 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4719 fragP
= fragP
->fr_next
)
4721 if (fragP
->fr_fix
!= 0
4722 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4724 if (last_fragP
== 0)
4726 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4727 _("assembly state not set for first frag in section %s"),
4732 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4733 fragP
->tc_frag_data
.is_no_density
=
4734 last_fragP
->tc_frag_data
.is_no_density
;
4735 fragP
->tc_frag_data
.is_no_transform
=
4736 last_fragP
->tc_frag_data
.is_no_transform
;
4737 fragP
->tc_frag_data
.use_longcalls
=
4738 last_fragP
->tc_frag_data
.use_longcalls
;
4739 fragP
->tc_frag_data
.use_absolute_literals
=
4740 last_fragP
->tc_frag_data
.use_absolute_literals
;
4743 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4752 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4754 void *unused ATTRIBUTE_UNUSED
)
4756 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4757 segment_info_type
*seginfo
= seg_info (sec
);
4758 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4760 if (flags
& SEC_CODE
)
4762 xtensa_isa isa
= xtensa_default_isa
;
4763 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4764 while (frag
!= NULL
)
4766 if (frag
->tc_frag_data
.is_branch_target
)
4769 addressT branch_align
, frag_addr
;
4772 xtensa_insnbuf_from_chars
4773 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4774 fmt
= xtensa_format_decode (isa
, insnbuf
);
4775 op_size
= xtensa_format_length (isa
, fmt
);
4776 branch_align
= 1 << branch_align_power (sec
);
4777 frag_addr
= frag
->fr_address
% branch_align
;
4778 if (frag_addr
+ op_size
> branch_align
)
4779 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4780 _("unaligned branch target: %d bytes at 0x%lx"),
4781 op_size
, (long) frag
->fr_address
);
4783 frag
= frag
->fr_next
;
4785 xtensa_insnbuf_free (isa
, insnbuf
);
4791 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4793 void *unused ATTRIBUTE_UNUSED
)
4795 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4796 segment_info_type
*seginfo
= seg_info (sec
);
4797 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4798 xtensa_isa isa
= xtensa_default_isa
;
4800 if (flags
& SEC_CODE
)
4802 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4803 while (frag
!= NULL
)
4805 if (frag
->tc_frag_data
.is_first_loop_insn
)
4811 xtensa_insnbuf_from_chars
4812 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4813 fmt
= xtensa_format_decode (isa
, insnbuf
);
4814 op_size
= xtensa_format_length (isa
, fmt
);
4815 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4817 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4818 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4819 _("unaligned loop: %d bytes at 0x%lx"),
4820 op_size
, (long) frag
->fr_address
);
4822 frag
= frag
->fr_next
;
4824 xtensa_insnbuf_free (isa
, insnbuf
);
4830 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4832 xtensa_isa isa
= xtensa_default_isa
;
4833 static xtensa_insnbuf insnbuf
= NULL
;
4834 static xtensa_insnbuf slotbuf
= NULL
;
4837 bfd_boolean alt_reloc
;
4838 xtensa_opcode opcode
;
4839 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4841 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4843 as_fatal (_("unexpected fix"));
4847 insnbuf
= xtensa_insnbuf_alloc (isa
);
4848 slotbuf
= xtensa_insnbuf_alloc (isa
);
4851 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4852 fmt
= xtensa_format_decode (isa
, insnbuf
);
4853 if (fmt
== XTENSA_UNDEFINED
)
4854 as_fatal (_("undecodable fix"));
4855 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4856 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4857 if (opcode
== XTENSA_UNDEFINED
)
4858 as_fatal (_("undecodable fix"));
4860 /* CONST16 immediates are not PC-relative, despite the fact that we
4861 reuse the normal PC-relative operand relocations for the low part
4862 of a CONST16 operand. */
4863 if (opcode
== xtensa_const16_opcode
)
4866 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4867 get_relaxable_immed (opcode
), val
,
4868 fixP
->fx_file
, fixP
->fx_line
);
4870 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4871 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4877 /* External Functions and Other GAS Hooks. */
4880 xtensa_target_format (void)
4882 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4887 xtensa_file_arch_init (bfd
*abfd
)
4889 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4894 md_number_to_chars (char *buf
, valueT val
, int n
)
4896 if (target_big_endian
)
4897 number_to_chars_bigendian (buf
, val
, n
);
4899 number_to_chars_littleendian (buf
, val
, n
);
4903 /* This function is called once, at assembler startup time. It should
4904 set up all the tables, etc. that the MD part of the assembler will
4910 segT current_section
= now_seg
;
4911 int current_subsec
= now_subseg
;
4914 xtensa_default_isa
= xtensa_isa_init (0, 0);
4915 isa
= xtensa_default_isa
;
4919 /* Set up the literal sections. */
4920 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4922 subseg_set (current_section
, current_subsec
);
4924 xg_init_vinsn (&cur_vinsn
);
4926 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4927 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4928 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4929 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4930 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4931 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4932 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4933 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4934 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4935 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4936 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4937 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4938 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4939 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4940 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4941 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4942 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4943 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4944 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4945 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4946 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4947 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4948 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4949 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4950 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4951 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4952 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4953 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4954 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4956 init_op_placement_info_table ();
4958 /* Set up the assembly state. */
4959 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4960 xtensa_set_frag_assembly_state (frag_now
);
4964 /* TC_INIT_FIX_DATA hook */
4967 xtensa_init_fix_data (fixS
*x
)
4969 x
->tc_fix_data
.slot
= 0;
4970 x
->tc_fix_data
.X_add_symbol
= NULL
;
4971 x
->tc_fix_data
.X_add_number
= 0;
4975 /* tc_frob_label hook */
4978 xtensa_frob_label (symbolS
*sym
)
4982 if (cur_vinsn
.inside_bundle
)
4984 as_bad (_("labels are not valid inside bundles"));
4988 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
4990 /* Since the label was already attached to a frag associated with the
4991 previous basic block, it now needs to be reset to the current frag. */
4992 symbol_set_frag (sym
, frag_now
);
4993 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
4995 if (generating_literals
)
4996 xtensa_add_literal_sym (sym
);
4998 xtensa_add_insn_label (sym
);
5000 if (symbol_get_tc (sym
)->is_loop_target
)
5002 if ((get_last_insn_flags (now_seg
, now_subseg
)
5003 & FLAG_IS_BAD_LOOPEND
) != 0)
5004 as_bad (_("invalid last instruction for a zero-overhead loop"));
5006 xtensa_set_frag_assembly_state (frag_now
);
5007 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5008 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5010 xtensa_set_frag_assembly_state (frag_now
);
5011 xtensa_move_labels (frag_now
, 0);
5014 /* No target aligning in the absolute section. */
5015 if (now_seg
!= absolute_section
5016 && do_align_targets ()
5017 && !is_unaligned_label (sym
)
5018 && !generating_literals
)
5020 xtensa_set_frag_assembly_state (frag_now
);
5022 frag_var (rs_machine_dependent
,
5024 RELAX_DESIRE_ALIGN_IF_TARGET
,
5025 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5026 xtensa_set_frag_assembly_state (frag_now
);
5027 xtensa_move_labels (frag_now
, 0);
5030 /* We need to mark the following properties even if we aren't aligning. */
5032 /* If the label is already known to be a branch target, i.e., a
5033 forward branch, mark the frag accordingly. Backward branches
5034 are handled by xg_add_branch_and_loop_targets. */
5035 if (symbol_get_tc (sym
)->is_branch_target
)
5036 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5038 /* Loops only go forward, so they can be identified here. */
5039 if (symbol_get_tc (sym
)->is_loop_target
)
5040 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5042 dwarf2_emit_label (sym
);
5046 /* tc_unrecognized_line hook */
5049 xtensa_unrecognized_line (int ch
)
5054 if (cur_vinsn
.inside_bundle
== 0)
5056 /* PR8110: Cannot emit line number info inside a FLIX bundle
5057 when using --gstabs. Temporarily disable debug info. */
5058 generate_lineno_debug ();
5059 if (debug_type
== DEBUG_STABS
)
5061 xt_saved_debug_type
= debug_type
;
5062 debug_type
= DEBUG_NONE
;
5065 cur_vinsn
.inside_bundle
= 1;
5069 as_bad (_("extra opening brace"));
5075 if (cur_vinsn
.inside_bundle
)
5076 finish_vinsn (&cur_vinsn
);
5079 as_bad (_("extra closing brace"));
5084 as_bad (_("syntax error"));
5091 /* md_flush_pending_output hook */
5094 xtensa_flush_pending_output (void)
5096 /* This line fixes a bug where automatically generated gstabs info
5097 separates a function label from its entry instruction, ending up
5098 with the literal position between the function label and the entry
5099 instruction and crashing code. It only happens with --gstabs and
5100 --text-section-literals, and when several other obscure relaxation
5101 conditions are met. */
5102 if (outputting_stabs_line_debug
)
5105 if (cur_vinsn
.inside_bundle
)
5106 as_bad (_("missing closing brace"));
5108 /* If there is a non-zero instruction fragment, close it. */
5109 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5111 frag_wane (frag_now
);
5113 xtensa_set_frag_assembly_state (frag_now
);
5115 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5117 xtensa_clear_insn_labels ();
5121 /* We had an error while parsing an instruction. The string might look
5122 like this: "insn arg1, arg2 }". If so, we need to see the closing
5123 brace and reset some fields. Otherwise, the vinsn never gets closed
5124 and the num_slots field will grow past the end of the array of slots,
5125 and bad things happen. */
5128 error_reset_cur_vinsn (void)
5130 if (cur_vinsn
.inside_bundle
)
5132 if (*input_line_pointer
== '}'
5133 || *(input_line_pointer
- 1) == '}'
5134 || *(input_line_pointer
- 2) == '}')
5135 xg_clear_vinsn (&cur_vinsn
);
5141 md_assemble (char *str
)
5143 xtensa_isa isa
= xtensa_default_isa
;
5144 char *opname
, *file_name
;
5146 bfd_boolean has_underbar
= FALSE
;
5147 char *arg_strings
[MAX_INSN_ARGS
];
5149 TInsn orig_insn
; /* Original instruction from the input. */
5151 tinsn_init (&orig_insn
);
5153 /* Split off the opcode. */
5154 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5155 opname
= xmalloc (opnamelen
+ 1);
5156 memcpy (opname
, str
, opnamelen
);
5157 opname
[opnamelen
] = '\0';
5159 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5162 as_bad (_("syntax error"));
5166 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5169 /* Check for an underbar prefix. */
5172 has_underbar
= TRUE
;
5176 orig_insn
.insn_type
= ITYPE_INSN
;
5178 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5180 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5181 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5183 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5184 if (fmt
== XTENSA_UNDEFINED
)
5186 as_bad (_("unknown opcode or format name '%s'"), opname
);
5187 error_reset_cur_vinsn ();
5190 if (!cur_vinsn
.inside_bundle
)
5192 as_bad (_("format names only valid inside bundles"));
5193 error_reset_cur_vinsn ();
5196 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5197 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5199 cur_vinsn
.format
= fmt
;
5200 free (has_underbar
? opname
- 1 : opname
);
5201 error_reset_cur_vinsn ();
5205 /* Parse the arguments. */
5206 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5208 as_bad (_("syntax error"));
5209 error_reset_cur_vinsn ();
5213 /* Free the opcode and argument strings, now that they've been parsed. */
5214 free (has_underbar
? opname
- 1 : opname
);
5216 while (num_args
-- > 0)
5217 free (arg_strings
[num_args
]);
5219 /* Get expressions for invisible operands. */
5220 if (get_invisible_operands (&orig_insn
))
5222 error_reset_cur_vinsn ();
5226 /* Check for the right number and type of arguments. */
5227 if (tinsn_check_arguments (&orig_insn
))
5229 error_reset_cur_vinsn ();
5233 /* A FLIX bundle may be spread across multiple input lines. We want to
5234 report the first such line in the debug information. Record the line
5235 number for each TInsn (assume the file name doesn't change), so the
5236 first line can be found later. */
5237 as_where (&file_name
, &orig_insn
.linenum
);
5239 xg_add_branch_and_loop_targets (&orig_insn
);
5241 /* Check that immediate value for ENTRY is >= 16. */
5242 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5244 expressionS
*exp
= &orig_insn
.tok
[2];
5245 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5246 as_warn (_("entry instruction with stack decrement < 16"));
5250 assemble_tokens (opcode, tok, ntok);
5251 expand the tokens from the orig_insn into the
5252 stack of instructions that will not expand
5253 unless required at relaxation time. */
5255 if (!cur_vinsn
.inside_bundle
)
5256 emit_single_op (&orig_insn
);
5257 else /* We are inside a bundle. */
5259 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5260 cur_vinsn
.num_slots
++;
5261 if (*input_line_pointer
== '}'
5262 || *(input_line_pointer
- 1) == '}'
5263 || *(input_line_pointer
- 2) == '}')
5264 finish_vinsn (&cur_vinsn
);
5267 /* We've just emitted a new instruction so clear the list of labels. */
5268 xtensa_clear_insn_labels ();
5272 /* HANDLE_ALIGN hook */
5274 /* For a .align directive, we mark the previous block with the alignment
5275 information. This will be placed in the object file in the
5276 property section corresponding to this section. */
5279 xtensa_handle_align (fragS
*fragP
)
5282 && ! fragP
->tc_frag_data
.is_literal
5283 && (fragP
->fr_type
== rs_align
5284 || fragP
->fr_type
== rs_align_code
)
5285 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5286 && fragP
->fr_offset
> 0
5287 && now_seg
!= bss_section
)
5289 fragP
->tc_frag_data
.is_align
= TRUE
;
5290 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5293 if (fragP
->fr_type
== rs_align_test
)
5296 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5298 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5299 _("unaligned entry instruction"));
5304 /* TC_FRAG_INIT hook */
5307 xtensa_frag_init (fragS
*frag
)
5309 xtensa_set_frag_assembly_state (frag
);
5314 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5320 /* Round up a section size to the appropriate boundary. */
5323 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5325 return size
; /* Byte alignment is fine. */
5330 md_pcrel_from (fixS
*fixP
)
5333 static xtensa_insnbuf insnbuf
= NULL
;
5334 static xtensa_insnbuf slotbuf
= NULL
;
5337 xtensa_opcode opcode
;
5340 xtensa_isa isa
= xtensa_default_isa
;
5341 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5342 bfd_boolean alt_reloc
;
5344 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5349 insnbuf
= xtensa_insnbuf_alloc (isa
);
5350 slotbuf
= xtensa_insnbuf_alloc (isa
);
5353 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5354 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5355 fmt
= xtensa_format_decode (isa
, insnbuf
);
5357 if (fmt
== XTENSA_UNDEFINED
)
5358 as_fatal (_("bad instruction format"));
5360 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5361 as_fatal (_("invalid relocation"));
5363 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5364 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5366 /* Check for "alternate" relocations (operand not specified). None
5367 of the current uses for these are really PC-relative. */
5368 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5370 if (opcode
!= xtensa_l32r_opcode
5371 && opcode
!= xtensa_const16_opcode
)
5372 as_fatal (_("invalid relocation for '%s' instruction"),
5373 xtensa_opcode_name (isa
, opcode
));
5377 opnum
= get_relaxable_immed (opcode
);
5379 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5380 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5382 as_bad_where (fixP
->fx_file
,
5384 _("invalid relocation for operand %d of '%s'"),
5385 opnum
, xtensa_opcode_name (isa
, opcode
));
5388 return 0 - opnd_value
;
5392 /* TC_FORCE_RELOCATION hook */
5395 xtensa_force_relocation (fixS
*fix
)
5397 switch (fix
->fx_r_type
)
5399 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5400 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5401 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5402 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5403 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5404 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5405 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5406 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5407 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5408 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5409 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5410 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5411 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5412 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5413 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5414 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5420 if (linkrelax
&& fix
->fx_addsy
5421 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5424 return generic_force_reloc (fix
);
5428 /* TC_VALIDATE_FIX_SUB hook */
5431 xtensa_validate_fix_sub (fixS
*fix
)
5433 segT add_symbol_segment
, sub_symbol_segment
;
5435 /* The difference of two symbols should be resolved by the assembler when
5436 linkrelax is not set. If the linker may relax the section containing
5437 the symbols, then an Xtensa DIFF relocation must be generated so that
5438 the linker knows to adjust the difference value. */
5439 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5442 /* Make sure both symbols are in the same segment, and that segment is
5443 "normal" and relaxable. If the segment is not "normal", then the
5444 fix is not valid. If the segment is not "relaxable", then the fix
5445 should have been handled earlier. */
5446 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5447 if (! SEG_NORMAL (add_symbol_segment
) ||
5448 ! relaxable_section (add_symbol_segment
))
5450 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5451 return (sub_symbol_segment
== add_symbol_segment
);
5455 /* NO_PSEUDO_DOT hook */
5457 /* This function has nothing to do with pseudo dots, but this is the
5458 nearest macro to where the check needs to take place. FIXME: This
5462 xtensa_check_inside_bundle (void)
5464 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5465 as_bad (_("directives are not valid inside bundles"));
5467 /* This function must always return FALSE because it is called via a
5468 macro that has nothing to do with bundling. */
5473 /* md_elf_section_change_hook */
5476 xtensa_elf_section_change_hook (void)
5478 /* Set up the assembly state. */
5479 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5480 xtensa_set_frag_assembly_state (frag_now
);
5484 /* tc_fix_adjustable hook */
5487 xtensa_fix_adjustable (fixS
*fixP
)
5489 /* An offset is not allowed in combination with the difference of two
5490 symbols, but that cannot be easily detected after a local symbol
5491 has been adjusted to a (section+offset) form. Return 0 so that such
5492 an fix will not be adjusted. */
5493 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5494 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5497 /* We need the symbol name for the VTABLE entries. */
5498 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5499 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5507 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5509 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5512 /* Subtracted symbols are only allowed for a few relocation types, and
5513 unless linkrelax is enabled, they should not make it to this point. */
5514 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5515 || fixP
->fx_r_type
== BFD_RELOC_16
5516 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5519 switch (fixP
->fx_r_type
)
5526 switch (fixP
->fx_r_type
)
5529 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5532 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5535 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5541 /* An offset is only allowed when it results from adjusting a
5542 local symbol into a section-relative offset. If the offset
5543 came from the original expression, tc_fix_adjustable will have
5544 prevented the fix from being converted to a section-relative
5545 form so that we can flag the error here. */
5546 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5547 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5548 _("cannot represent subtraction with an offset"));
5550 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5551 - S_GET_VALUE (fixP
->fx_subsy
));
5553 /* The difference value gets written out, and the DIFF reloc
5554 identifies the address of the subtracted symbol (i.e., the one
5555 with the lowest address). */
5557 fixP
->fx_offset
-= val
;
5558 fixP
->fx_subsy
= NULL
;
5560 else if (! fixP
->fx_addsy
)
5567 case BFD_RELOC_XTENSA_PLT
:
5568 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5569 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5572 case BFD_RELOC_XTENSA_SLOT0_OP
:
5573 case BFD_RELOC_XTENSA_SLOT1_OP
:
5574 case BFD_RELOC_XTENSA_SLOT2_OP
:
5575 case BFD_RELOC_XTENSA_SLOT3_OP
:
5576 case BFD_RELOC_XTENSA_SLOT4_OP
:
5577 case BFD_RELOC_XTENSA_SLOT5_OP
:
5578 case BFD_RELOC_XTENSA_SLOT6_OP
:
5579 case BFD_RELOC_XTENSA_SLOT7_OP
:
5580 case BFD_RELOC_XTENSA_SLOT8_OP
:
5581 case BFD_RELOC_XTENSA_SLOT9_OP
:
5582 case BFD_RELOC_XTENSA_SLOT10_OP
:
5583 case BFD_RELOC_XTENSA_SLOT11_OP
:
5584 case BFD_RELOC_XTENSA_SLOT12_OP
:
5585 case BFD_RELOC_XTENSA_SLOT13_OP
:
5586 case BFD_RELOC_XTENSA_SLOT14_OP
:
5589 /* Write the tentative value of a PC-relative relocation to a
5590 local symbol into the instruction. The value will be ignored
5591 by the linker, and it makes the object file disassembly
5592 readable when all branch targets are encoded in relocations. */
5594 assert (fixP
->fx_addsy
);
5595 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5596 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5598 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5599 - md_pcrel_from (fixP
));
5600 (void) xg_apply_fix_value (fixP
, val
);
5603 else if (! fixP
->fx_addsy
)
5606 if (xg_apply_fix_value (fixP
, val
))
5611 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5612 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5613 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5614 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5615 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5616 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5617 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5618 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5619 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5620 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5621 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5622 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5623 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5624 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5625 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5626 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5627 /* These all need to be resolved at link-time. Do nothing now. */
5630 case BFD_RELOC_VTABLE_INHERIT
:
5631 case BFD_RELOC_VTABLE_ENTRY
:
5636 as_bad (_("unhandled local relocation fix %s"),
5637 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5643 md_atof (int type
, char *litP
, int *sizeP
)
5646 LITTLENUM_TYPE words
[4];
5662 return "bad call to md_atof";
5665 t
= atof_ieee (input_line_pointer
, type
, words
);
5667 input_line_pointer
= t
;
5671 for (i
= prec
- 1; i
>= 0; i
--)
5674 if (target_big_endian
)
5675 idx
= (prec
- 1 - i
);
5677 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5686 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5688 return total_frag_text_expansion (fragP
);
5692 /* Translate internal representation of relocation info to BFD target
5696 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5700 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5701 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5702 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5703 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5705 /* Make sure none of our internal relocations make it this far.
5706 They'd better have been fully resolved by this point. */
5707 assert ((int) fixp
->fx_r_type
> 0);
5709 reloc
->addend
= fixp
->fx_offset
;
5711 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5712 if (reloc
->howto
== NULL
)
5714 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5715 _("cannot represent `%s' relocation in object file"),
5716 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5717 free (reloc
->sym_ptr_ptr
);
5722 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5723 as_fatal (_("internal error? cannot generate `%s' relocation"),
5724 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5730 /* Checks for resource conflicts between instructions. */
5732 /* The func unit stuff could be implemented as bit-vectors rather
5733 than the iterative approach here. If it ends up being too
5734 slow, we will switch it. */
5737 new_resource_table (void *data
,
5740 unit_num_copies_func uncf
,
5741 opcode_num_units_func onuf
,
5742 opcode_funcUnit_use_unit_func ouuf
,
5743 opcode_funcUnit_use_stage_func ousf
)
5746 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5748 rt
->cycles
= cycles
;
5749 rt
->allocated_cycles
= cycles
;
5751 rt
->unit_num_copies
= uncf
;
5752 rt
->opcode_num_units
= onuf
;
5753 rt
->opcode_unit_use
= ouuf
;
5754 rt
->opcode_unit_stage
= ousf
;
5756 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5757 for (i
= 0; i
< cycles
; i
++)
5758 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5765 clear_resource_table (resource_table
*rt
)
5768 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5769 for (j
= 0; j
< rt
->num_units
; j
++)
5770 rt
->units
[i
][j
] = 0;
5774 /* We never shrink it, just fake it into thinking so. */
5777 resize_resource_table (resource_table
*rt
, int cycles
)
5781 rt
->cycles
= cycles
;
5782 if (cycles
<= rt
->allocated_cycles
)
5785 old_cycles
= rt
->allocated_cycles
;
5786 rt
->allocated_cycles
= cycles
;
5788 rt
->units
= xrealloc (rt
->units
,
5789 rt
->allocated_cycles
* sizeof (unsigned char *));
5790 for (i
= 0; i
< old_cycles
; i
++)
5791 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5792 rt
->num_units
* sizeof (unsigned char));
5793 for (i
= old_cycles
; i
< cycles
; i
++)
5794 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5799 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5802 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5804 for (i
= 0; i
< uses
; i
++)
5806 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5807 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5808 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5809 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5810 if (copies_in_use
>= copies
)
5818 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5821 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5823 for (i
= 0; i
< uses
; i
++)
5825 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5826 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5827 /* Note that this allows resources to be oversubscribed. That's
5828 essential to the way the optional scheduler works.
5829 resources_available reports when a resource is over-subscribed,
5830 so it's easy to tell. */
5831 rt
->units
[stage
+ cycle
][unit
]++;
5837 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5840 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5842 for (i
= 0; i
< uses
; i
++)
5844 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5845 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5846 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5847 rt
->units
[stage
+ cycle
][unit
]--;
5852 /* Wrapper functions make parameterized resource reservation
5856 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5858 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5864 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5866 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5871 /* Note that this function does not check issue constraints, but
5872 solely whether the hardware is available to execute the given
5873 instructions together. It also doesn't check if the tinsns
5874 write the same state, or access the same tieports. That is
5875 checked by check_t1_t2_reads_and_writes. */
5878 resources_conflict (vliw_insn
*vinsn
)
5881 static resource_table
*rt
= NULL
;
5883 /* This is the most common case by far. Optimize it. */
5884 if (vinsn
->num_slots
== 1)
5889 xtensa_isa isa
= xtensa_default_isa
;
5890 rt
= new_resource_table
5891 (isa
, xtensa_isa_num_pipe_stages (isa
),
5892 xtensa_isa_num_funcUnits (isa
),
5893 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5894 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5895 opcode_funcUnit_use_unit
,
5896 opcode_funcUnit_use_stage
);
5899 clear_resource_table (rt
);
5901 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5903 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5905 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5912 /* finish_vinsn, emit_single_op and helper functions. */
5914 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5915 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5916 static void xg_assemble_vliw_tokens (vliw_insn
*);
5919 /* We have reached the end of a bundle; emit into the frag. */
5922 finish_vinsn (vliw_insn
*vinsn
)
5929 if (find_vinsn_conflicts (vinsn
))
5931 xg_clear_vinsn (vinsn
);
5935 /* First, find a format that works. */
5936 if (vinsn
->format
== XTENSA_UNDEFINED
)
5937 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5939 if (vinsn
->format
== XTENSA_UNDEFINED
)
5941 as_where (&file_name
, &line
);
5942 as_bad_where (file_name
, line
,
5943 _("couldn't find a valid instruction format"));
5944 fprintf (stderr
, _(" ops were: "));
5945 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5946 fprintf (stderr
, _(" %s;"),
5947 xtensa_opcode_name (xtensa_default_isa
,
5948 vinsn
->slots
[i
].opcode
));
5949 fprintf (stderr
, _("\n"));
5950 xg_clear_vinsn (vinsn
);
5954 if (vinsn
->num_slots
5955 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5957 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5958 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5959 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5961 xg_clear_vinsn (vinsn
);
5965 if (resources_conflict (vinsn
))
5967 as_where (&file_name
, &line
);
5968 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5969 fprintf (stderr
, " ops were: ");
5970 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5971 fprintf (stderr
, " %s;",
5972 xtensa_opcode_name (xtensa_default_isa
,
5973 vinsn
->slots
[i
].opcode
));
5974 fprintf (stderr
, "\n");
5975 xg_clear_vinsn (vinsn
);
5979 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5981 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
5983 symbolS
*lit_sym
= NULL
;
5985 bfd_boolean e
= FALSE
;
5986 bfd_boolean saved_density
= density_supported
;
5988 /* We don't want to narrow ops inside multi-slot bundles. */
5989 if (vinsn
->num_slots
> 1)
5990 density_supported
= FALSE
;
5992 istack_init (&slotstack
);
5993 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
5995 vinsn
->slots
[i
].opcode
=
5996 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
5998 vinsn
->slots
[i
].ntok
= 0;
6001 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6007 density_supported
= saved_density
;
6011 xg_clear_vinsn (vinsn
);
6015 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6017 TInsn
*insn
= &slotstack
.insn
[j
];
6018 if (insn
->insn_type
== ITYPE_LITERAL
)
6020 assert (lit_sym
== NULL
);
6021 lit_sym
= xg_assemble_literal (insn
);
6025 assert (insn
->insn_type
== ITYPE_INSN
);
6027 xg_resolve_literals (insn
, lit_sym
);
6028 if (j
!= slotstack
.ninsn
- 1)
6029 emit_single_op (insn
);
6033 if (vinsn
->num_slots
> 1)
6035 if (opcode_fits_format_slot
6036 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6039 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6043 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6044 if (vinsn
->format
== XTENSA_UNDEFINED
)
6045 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6047 vinsn
->slots
[i
].opcode
6048 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6051 vinsn
->slots
[i
].ntok
= 0;
6056 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6057 vinsn
->format
= XTENSA_UNDEFINED
;
6062 /* Now check resource conflicts on the modified bundle. */
6063 if (resources_conflict (vinsn
))
6065 as_where (&file_name
, &line
);
6066 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6067 fprintf (stderr
, " ops were: ");
6068 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6069 fprintf (stderr
, " %s;",
6070 xtensa_opcode_name (xtensa_default_isa
,
6071 vinsn
->slots
[i
].opcode
));
6072 fprintf (stderr
, "\n");
6073 xg_clear_vinsn (vinsn
);
6077 /* First, find a format that works. */
6078 if (vinsn
->format
== XTENSA_UNDEFINED
)
6079 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6081 xg_assemble_vliw_tokens (vinsn
);
6083 xg_clear_vinsn (vinsn
);
6087 /* Given an vliw instruction, what conflicts are there in register
6088 usage and in writes to states and queues?
6090 This function does two things:
6091 1. Reports an error when a vinsn contains illegal combinations
6092 of writes to registers states or queues.
6093 2. Marks individual tinsns as not relaxable if the combination
6094 contains antidependencies.
6096 Job 2 handles things like swap semantics in instructions that need
6097 to be relaxed. For example,
6101 normally would be relaxed to
6106 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6108 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6110 then we can't relax it into
6113 { add a0, a1, a0 ; add a2, a0, a4 ; }
6115 because the value of a0 is trashed before the second add can read it. */
6117 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6120 find_vinsn_conflicts (vliw_insn
*vinsn
)
6124 xtensa_isa isa
= xtensa_default_isa
;
6126 assert (!past_xtensa_end
);
6128 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6130 TInsn
*op1
= &vinsn
->slots
[i
];
6131 if (op1
->is_specific_opcode
)
6132 op1
->keep_wide
= TRUE
;
6134 op1
->keep_wide
= FALSE
;
6137 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6139 TInsn
*op1
= &vinsn
->slots
[i
];
6141 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6144 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6148 TInsn
*op2
= &vinsn
->slots
[j
];
6149 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6150 switch (conflict_type
)
6153 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6154 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6155 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6158 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6159 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6160 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6163 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6164 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6165 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6168 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6169 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6170 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6173 /* Everything is OK. */
6176 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6177 || conflict_type
== 'a');
6184 as_bad (_("multiple branches or jumps in the same bundle"));
6192 /* Check how the state used by t1 and t2 relate.
6195 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6196 case B: no relationship between what is read and written (both could
6197 read the same reg though)
6198 case C: t1 writes a register t2 writes (a register conflict within a
6200 case D: t1 writes a state that t2 also writes
6201 case E: t1 writes a tie queue that t2 also writes
6202 case F: two volatile queue accesses
6206 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6208 xtensa_isa isa
= xtensa_default_isa
;
6209 xtensa_regfile t1_regfile
, t2_regfile
;
6211 int t1_base_reg
, t1_last_reg
;
6212 int t2_base_reg
, t2_last_reg
;
6213 char t1_inout
, t2_inout
;
6215 char conflict
= 'b';
6220 bfd_boolean t1_volatile
= FALSE
;
6221 bfd_boolean t2_volatile
= FALSE
;
6223 /* Check registers. */
6224 for (j
= 0; j
< t2
->ntok
; j
++)
6226 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6229 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6230 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6231 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6233 for (i
= 0; i
< t1
->ntok
; i
++)
6235 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6238 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6240 if (t1_regfile
!= t2_regfile
)
6243 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6244 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6246 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6247 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6249 if (t1_inout
== 'm' || t1_inout
== 'o'
6250 || t2_inout
== 'm' || t2_inout
== 'o')
6257 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6258 t1_last_reg
= (t1_base_reg
6259 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6261 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6263 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6265 if (t1_reg
!= t2_reg
)
6268 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6274 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6280 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6288 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6289 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6290 for (j
= 0; j
< t2_states
; j
++)
6292 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6293 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6294 for (i
= 0; i
< t1_states
; i
++)
6296 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6297 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6301 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6307 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6313 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6318 /* Check tieports. */
6319 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6320 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6321 for (j
= 0; j
< t2_interfaces
; j
++)
6323 xtensa_interface t2_int
6324 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6325 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6327 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6328 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6331 for (i
= 0; i
< t1_interfaces
; i
++)
6333 xtensa_interface t1_int
6334 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6335 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6337 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6338 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6341 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6344 if (t1_int
!= t2_int
)
6347 if (t2_inout
== 'i' && t1_inout
== 'o')
6353 if (t1_inout
== 'i' && t2_inout
== 'o')
6359 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6368 static xtensa_format
6369 xg_find_narrowest_format (vliw_insn
*vinsn
)
6371 /* Right now we assume that the ops within the vinsn are properly
6372 ordered for the slots that the programmer wanted them in. In
6373 other words, we don't rearrange the ops in hopes of finding a
6374 better format. The scheduler handles that. */
6376 xtensa_isa isa
= xtensa_default_isa
;
6377 xtensa_format format
;
6378 vliw_insn v_copy
= *vinsn
;
6379 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6381 if (vinsn
->num_slots
== 1)
6382 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6384 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6387 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6391 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6393 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6395 v_copy
.slots
[slot
].opcode
=
6396 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6397 v_copy
.slots
[slot
].ntok
= 0;
6400 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6403 else if (v_copy
.num_slots
> 1)
6406 /* Try the widened version. */
6407 if (!v_copy
.slots
[slot
].keep_wide
6408 && !v_copy
.slots
[slot
].is_specific_opcode
6409 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6411 && opcode_fits_format_slot (widened
.opcode
,
6414 v_copy
.slots
[slot
] = widened
;
6419 if (fit
== v_copy
.num_slots
)
6422 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6423 vinsn
->format
= format
;
6429 if (format
== xtensa_isa_num_formats (isa
))
6430 return XTENSA_UNDEFINED
;
6436 /* Return the additional space needed in a frag
6437 for possible relaxations of any ops in a VLIW insn.
6438 Also fill out the relaxations that might be required of
6439 each tinsn in the vinsn. */
6442 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6444 bfd_boolean finish_frag
= FALSE
;
6445 int extra_space
= 0;
6448 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6450 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6451 if (!tinsn_has_symbolic_operands (tinsn
))
6453 /* A narrow instruction could be widened later to help
6454 alignment issues. */
6455 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6456 && !tinsn
->is_specific_opcode
6457 && vinsn
->num_slots
== 1)
6459 /* Difference in bytes between narrow and wide insns... */
6461 tinsn
->subtype
= RELAX_NARROW
;
6466 if (workaround_b_j_loop_end
6467 && tinsn
->opcode
== xtensa_jx_opcode
6468 && use_transform ())
6470 /* Add 2 of these. */
6471 extra_space
+= 3; /* for the nop size */
6472 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6475 /* Need to assemble it with space for the relocation. */
6476 if (xg_is_relaxable_insn (tinsn
, 0)
6477 && !tinsn
->is_specific_opcode
)
6479 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6480 int max_literal_size
=
6481 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6483 tinsn
->literal_space
= max_literal_size
;
6485 tinsn
->subtype
= RELAX_IMMED
;
6486 extra_space
+= max_size
;
6490 /* A fix record will be added for this instruction prior
6491 to relaxation, so make it end the frag. */
6496 *pfinish_frag
= finish_frag
;
6502 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6504 xtensa_isa isa
= xtensa_default_isa
;
6505 int slot
, chosen_slot
;
6507 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6508 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6509 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6511 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6512 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6514 if (slot
== chosen_slot
)
6515 vinsn
->slots
[slot
] = *tinsn
;
6518 vinsn
->slots
[slot
].opcode
=
6519 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6520 vinsn
->slots
[slot
].ntok
= 0;
6521 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6528 emit_single_op (TInsn
*orig_insn
)
6531 IStack istack
; /* put instructions into here */
6532 symbolS
*lit_sym
= NULL
;
6533 symbolS
*label_sym
= NULL
;
6535 istack_init (&istack
);
6537 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6538 Because the scheduling and bundling characteristics of movi and
6539 l32r or const16 are so different, we can do much better if we relax
6540 it prior to scheduling and bundling, rather than after. */
6541 if ((orig_insn
->opcode
== xtensa_movi_opcode
6542 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6543 && !cur_vinsn
.inside_bundle
6544 && (orig_insn
->tok
[1].X_op
== O_symbol
6545 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6546 && !orig_insn
->is_specific_opcode
&& use_transform ())
6547 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6549 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6552 for (i
= 0; i
< istack
.ninsn
; i
++)
6554 TInsn
*insn
= &istack
.insn
[i
];
6555 switch (insn
->insn_type
)
6558 assert (lit_sym
== NULL
);
6559 lit_sym
= xg_assemble_literal (insn
);
6563 static int relaxed_sym_idx
= 0;
6564 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6565 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6567 assert (label_sym
== NULL
);
6568 label_sym
= symbol_find_or_make (label
);
6577 xg_resolve_literals (insn
, lit_sym
);
6579 xg_resolve_labels (insn
, label_sym
);
6581 bundle_tinsn (insn
, &v
);
6596 total_frag_text_expansion (fragS
*fragP
)
6599 int total_expansion
= 0;
6601 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6602 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6604 return total_expansion
;
6608 /* Emit a vliw instruction to the current fragment. */
6611 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6613 bfd_boolean finish_frag
;
6614 bfd_boolean is_jump
= FALSE
;
6615 bfd_boolean is_branch
= FALSE
;
6616 xtensa_isa isa
= xtensa_default_isa
;
6622 unsigned current_line
, best_linenum
;
6625 best_linenum
= UINT_MAX
;
6627 if (generating_literals
)
6629 static int reported
= 0;
6631 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6632 _("cannot assemble into a literal fragment"));
6639 if (frag_now_fix () != 0
6640 && (! frag_now
->tc_frag_data
.is_insn
6641 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6642 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6643 || (directive_state
[directive_longcalls
]
6644 != frag_now
->tc_frag_data
.use_longcalls
)
6645 || (directive_state
[directive_absolute_literals
]
6646 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6648 frag_wane (frag_now
);
6650 xtensa_set_frag_assembly_state (frag_now
);
6653 if (workaround_a0_b_retw
6654 && vinsn
->num_slots
== 1
6655 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6656 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6657 && use_transform ())
6659 has_a0_b_retw
= TRUE
;
6661 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6662 After the first assembly pass we will check all of them and
6663 add a nop if needed. */
6664 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6665 frag_var (rs_machine_dependent
, 4, 4,
6666 RELAX_ADD_NOP_IF_A0_B_RETW
,
6667 frag_now
->fr_symbol
,
6668 frag_now
->fr_offset
,
6670 xtensa_set_frag_assembly_state (frag_now
);
6671 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6672 frag_var (rs_machine_dependent
, 4, 4,
6673 RELAX_ADD_NOP_IF_A0_B_RETW
,
6674 frag_now
->fr_symbol
,
6675 frag_now
->fr_offset
,
6677 xtensa_set_frag_assembly_state (frag_now
);
6680 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6682 /* See if the instruction implies an aligned section. */
6683 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6684 record_alignment (now_seg
, 2);
6686 /* Also determine the best line number for debug info. */
6687 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6688 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6691 /* Special cases for instructions that force an alignment... */
6692 /* None of these opcodes are bundle-able. */
6693 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6697 /* Remember the symbol that marks the end of the loop in the frag
6698 that marks the start of the loop. This way we can easily find
6699 the end of the loop at the beginning, without adding special code
6700 to mark the loop instructions themselves. */
6701 symbolS
*target_sym
= NULL
;
6702 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6703 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6705 xtensa_set_frag_assembly_state (frag_now
);
6706 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6708 max_fill
= get_text_align_max_fill_size
6709 (get_text_align_power (xtensa_fetch_width
),
6710 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6712 if (use_transform ())
6713 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6714 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6716 frag_var (rs_machine_dependent
, 0, 0,
6717 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6718 xtensa_set_frag_assembly_state (frag_now
);
6721 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6722 && !vinsn
->slots
[0].is_specific_opcode
)
6724 xtensa_mark_literal_pool_location ();
6725 xtensa_move_labels (frag_now
, 0);
6726 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6729 if (vinsn
->num_slots
== 1)
6731 if (workaround_a0_b_retw
&& use_transform ())
6732 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6733 is_register_writer (&vinsn
->slots
[0], "a", 0));
6735 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6736 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6739 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6741 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6743 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6745 /* vinsn_to_insnbuf will produce the error. */
6746 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6748 f
= frag_more (insn_size
+ extra_space
);
6749 xtensa_set_frag_assembly_state (frag_now
);
6750 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6753 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6754 if (vinsn
->format
== XTENSA_UNDEFINED
)
6757 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6759 /* Temporarily set the logical line number to the one we want to appear
6760 in the debug information. */
6761 as_where (¤t_file
, ¤t_line
);
6762 new_logical_line (current_file
, best_linenum
);
6763 dwarf2_emit_insn (insn_size
+ extra_space
);
6764 new_logical_line (current_file
, current_line
);
6766 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6768 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6769 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6770 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6771 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6772 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6773 if (tinsn
->literal_space
!= 0)
6774 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6776 if (tinsn
->subtype
== RELAX_NARROW
)
6777 assert (vinsn
->num_slots
== 1);
6778 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6780 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6783 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6784 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6788 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6789 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6793 frag_variant (rs_machine_dependent
,
6794 extra_space
, extra_space
, RELAX_SLOTS
,
6795 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6796 xtensa_set_frag_assembly_state (frag_now
);
6799 /* Special cases for loops:
6800 close_loop_end should be inserted AFTER short_loop.
6801 Make sure that CLOSE loops are processed BEFORE short_loops
6802 when converting them. */
6804 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6805 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6806 && !vinsn
->slots
[0].is_specific_opcode
)
6808 if (workaround_short_loop
&& use_transform ())
6810 maybe_has_short_loop
= TRUE
;
6811 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6812 frag_var (rs_machine_dependent
, 4, 4,
6813 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6814 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6815 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6816 frag_var (rs_machine_dependent
, 4, 4,
6817 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6818 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6821 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6822 loop at least 12 bytes away from another loop's end. */
6823 if (workaround_close_loop_end
&& use_transform ())
6825 maybe_has_close_loop_end
= TRUE
;
6826 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6827 frag_var (rs_machine_dependent
, 12, 12,
6828 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6829 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6833 if (use_transform ())
6837 assert (finish_frag
);
6838 frag_var (rs_machine_dependent
,
6839 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6841 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6842 xtensa_set_frag_assembly_state (frag_now
);
6844 else if (is_branch
&& do_align_targets ())
6846 assert (finish_frag
);
6847 frag_var (rs_machine_dependent
,
6848 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6849 RELAX_MAYBE_UNREACHABLE
,
6850 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6851 xtensa_set_frag_assembly_state (frag_now
);
6852 frag_var (rs_machine_dependent
,
6854 RELAX_MAYBE_DESIRE_ALIGN
,
6855 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6856 xtensa_set_frag_assembly_state (frag_now
);
6860 /* Now, if the original opcode was a call... */
6861 if (do_align_targets ()
6862 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6864 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6865 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6866 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6867 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6868 xtensa_set_frag_assembly_state (frag_now
);
6871 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6873 frag_wane (frag_now
);
6875 xtensa_set_frag_assembly_state (frag_now
);
6880 /* xtensa_end and helper functions. */
6882 static void xtensa_cleanup_align_frags (void);
6883 static void xtensa_fix_target_frags (void);
6884 static void xtensa_mark_narrow_branches (void);
6885 static void xtensa_mark_zcl_first_insns (void);
6886 static void xtensa_fix_a0_b_retw_frags (void);
6887 static void xtensa_fix_b_j_loop_end_frags (void);
6888 static void xtensa_fix_close_loop_end_frags (void);
6889 static void xtensa_fix_short_loop_frags (void);
6890 static void xtensa_sanity_check (void);
6891 static void xtensa_add_config_info (void);
6896 directive_balance ();
6897 xtensa_flush_pending_output ();
6899 past_xtensa_end
= TRUE
;
6901 xtensa_move_literals ();
6903 xtensa_reorder_segments ();
6904 xtensa_cleanup_align_frags ();
6905 xtensa_fix_target_frags ();
6906 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6907 xtensa_fix_a0_b_retw_frags ();
6908 if (workaround_b_j_loop_end
)
6909 xtensa_fix_b_j_loop_end_frags ();
6911 /* "close_loop_end" should be processed BEFORE "short_loop". */
6912 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6913 xtensa_fix_close_loop_end_frags ();
6915 if (workaround_short_loop
&& maybe_has_short_loop
)
6916 xtensa_fix_short_loop_frags ();
6918 xtensa_mark_narrow_branches ();
6919 xtensa_mark_zcl_first_insns ();
6921 xtensa_sanity_check ();
6923 xtensa_add_config_info ();
6928 xtensa_cleanup_align_frags (void)
6933 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6934 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6937 /* Walk over all of the fragments in a subsection. */
6938 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6940 if ((fragP
->fr_type
== rs_align
6941 || fragP
->fr_type
== rs_align_code
6942 || (fragP
->fr_type
== rs_machine_dependent
6943 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6944 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6945 && fragP
->fr_fix
== 0)
6947 fragS
*next
= fragP
->fr_next
;
6950 && next
->fr_fix
== 0
6951 && next
->fr_type
== rs_machine_dependent
6952 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6955 next
= next
->fr_next
;
6958 /* If we don't widen branch targets, then they
6959 will be easier to align. */
6960 if (fragP
->tc_frag_data
.is_branch_target
6961 && fragP
->fr_opcode
== fragP
->fr_literal
6962 && fragP
->fr_type
== rs_machine_dependent
6963 && fragP
->fr_subtype
== RELAX_SLOTS
6964 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6966 if (fragP
->fr_type
== rs_machine_dependent
6967 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6968 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
6974 /* Re-process all of the fragments looking to convert all of the
6975 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
6976 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
6977 Otherwise, convert to a .fill 0. */
6980 xtensa_fix_target_frags (void)
6985 /* When this routine is called, all of the subsections are still intact
6986 so we walk over subsections instead of sections. */
6987 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6988 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6992 /* Walk over all of the fragments in a subsection. */
6993 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6995 if (fragP
->fr_type
== rs_machine_dependent
6996 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6998 if (next_frag_is_branch_target (fragP
))
6999 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7008 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7011 xtensa_mark_narrow_branches (void)
7016 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7017 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7020 /* Walk over all of the fragments in a subsection. */
7021 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7023 if (fragP
->fr_type
== rs_machine_dependent
7024 && fragP
->fr_subtype
== RELAX_SLOTS
7025 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7029 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7030 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7032 if (vinsn
.num_slots
== 1
7033 && xtensa_opcode_is_branch (xtensa_default_isa
,
7034 vinsn
.slots
[0].opcode
) == 1
7035 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7036 && is_narrow_branch_guaranteed_in_range (fragP
,
7039 fragP
->fr_subtype
= RELAX_SLOTS
;
7040 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7041 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7049 /* A branch is typically widened only when its target is out of
7050 range. However, we would like to widen them to align a subsequent
7051 branch target when possible.
7053 Because the branch relaxation code is so convoluted, the optimal solution
7054 (combining the two cases) is difficult to get right in all circumstances.
7055 We therefore go with an "almost as good" solution, where we only
7056 use for alignment narrow branches that definitely will not expand to a
7057 jump and a branch. These functions find and mark these cases. */
7059 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7060 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7061 We start counting beginning with the frag after the 2-byte branch, so the
7062 maximum offset is (4 - 2) + 63 = 65. */
7063 #define MAX_IMMED6 65
7065 static offsetT
unrelaxed_frag_max_size (fragS
*);
7068 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7070 const expressionS
*expr
= &tinsn
->tok
[1];
7071 symbolS
*symbolP
= expr
->X_add_symbol
;
7072 offsetT max_distance
= expr
->X_add_number
;
7075 if (expr
->X_op
!= O_symbol
)
7078 target_frag
= symbol_get_frag (symbolP
);
7080 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7081 if (is_branch_jmp_to_next (tinsn
, fragP
))
7084 /* The branch doesn't branch over it's own frag,
7085 but over the subsequent ones. */
7086 fragP
= fragP
->fr_next
;
7087 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7089 max_distance
+= unrelaxed_frag_max_size (fragP
);
7090 fragP
= fragP
->fr_next
;
7092 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7099 xtensa_mark_zcl_first_insns (void)
7104 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7105 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7108 /* Walk over all of the fragments in a subsection. */
7109 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7111 if (fragP
->fr_type
== rs_machine_dependent
7112 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7113 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7115 /* Find the loop frag. */
7116 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7117 /* Find the first insn frag. */
7118 targ_frag
= next_non_empty_frag (targ_frag
);
7120 /* Of course, sometimes (mostly for toy test cases) a
7121 zero-cost loop instruction is the last in a section. */
7124 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7125 /* Do not widen a frag that is the first instruction of a
7126 zero-cost loop. It makes that loop harder to align. */
7127 if (targ_frag
->fr_type
== rs_machine_dependent
7128 && targ_frag
->fr_subtype
== RELAX_SLOTS
7129 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7132 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7133 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7136 frag_wane (targ_frag
);
7137 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7141 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7149 /* Re-process all of the fragments looking to convert all of the
7150 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7151 conditional branch or a retw/retw.n, convert this frag to one that
7152 will generate a NOP. In any case close it off with a .fill 0. */
7154 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7157 xtensa_fix_a0_b_retw_frags (void)
7162 /* When this routine is called, all of the subsections are still intact
7163 so we walk over subsections instead of sections. */
7164 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7165 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7169 /* Walk over all of the fragments in a subsection. */
7170 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7172 if (fragP
->fr_type
== rs_machine_dependent
7173 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7175 if (next_instrs_are_b_retw (fragP
))
7177 if (fragP
->tc_frag_data
.is_no_transform
)
7178 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7180 relax_frag_add_nop (fragP
);
7190 next_instrs_are_b_retw (fragS
*fragP
)
7192 xtensa_opcode opcode
;
7194 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7195 static xtensa_insnbuf insnbuf
= NULL
;
7196 static xtensa_insnbuf slotbuf
= NULL
;
7197 xtensa_isa isa
= xtensa_default_isa
;
7200 bfd_boolean branch_seen
= FALSE
;
7204 insnbuf
= xtensa_insnbuf_alloc (isa
);
7205 slotbuf
= xtensa_insnbuf_alloc (isa
);
7208 if (next_fragP
== NULL
)
7211 /* Check for the conditional branch. */
7212 xtensa_insnbuf_from_chars
7213 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7214 fmt
= xtensa_format_decode (isa
, insnbuf
);
7215 if (fmt
== XTENSA_UNDEFINED
)
7218 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7220 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7221 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7223 branch_seen
= (branch_seen
7224 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7230 offset
+= xtensa_format_length (isa
, fmt
);
7231 if (offset
== next_fragP
->fr_fix
)
7233 next_fragP
= next_non_empty_frag (next_fragP
);
7237 if (next_fragP
== NULL
)
7240 /* Check for the retw/retw.n. */
7241 xtensa_insnbuf_from_chars
7242 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7243 fmt
= xtensa_format_decode (isa
, insnbuf
);
7245 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7246 have no problems. */
7247 if (fmt
== XTENSA_UNDEFINED
7248 || xtensa_format_num_slots (isa
, fmt
) != 1)
7251 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7252 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7254 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7261 /* Re-process all of the fragments looking to convert all of the
7262 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7263 loop end label, convert this frag to one that will generate a NOP.
7264 In any case close it off with a .fill 0. */
7266 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7269 xtensa_fix_b_j_loop_end_frags (void)
7274 /* When this routine is called, all of the subsections are still intact
7275 so we walk over subsections instead of sections. */
7276 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7277 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7281 /* Walk over all of the fragments in a subsection. */
7282 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7284 if (fragP
->fr_type
== rs_machine_dependent
7285 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7287 if (next_instr_is_loop_end (fragP
))
7289 if (fragP
->tc_frag_data
.is_no_transform
)
7290 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7292 relax_frag_add_nop (fragP
);
7302 next_instr_is_loop_end (fragS
*fragP
)
7304 const fragS
*next_fragP
;
7306 if (next_frag_is_loop_target (fragP
))
7309 next_fragP
= next_non_empty_frag (fragP
);
7310 if (next_fragP
== NULL
)
7313 if (!next_frag_is_loop_target (next_fragP
))
7316 /* If the size is >= 3 then there is more than one instruction here.
7317 The hardware bug will not fire. */
7318 if (next_fragP
->fr_fix
> 3)
7325 /* Re-process all of the fragments looking to convert all of the
7326 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7327 not MY loop's loop end within 12 bytes, add enough nops here to
7328 make it at least 12 bytes away. In any case close it off with a
7331 static offsetT min_bytes_to_other_loop_end
7332 (fragS
*, fragS
*, offsetT
);
7335 xtensa_fix_close_loop_end_frags (void)
7340 /* When this routine is called, all of the subsections are still intact
7341 so we walk over subsections instead of sections. */
7342 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7343 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7347 fragS
*current_target
= NULL
;
7349 /* Walk over all of the fragments in a subsection. */
7350 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7352 if (fragP
->fr_type
== rs_machine_dependent
7353 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7354 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7355 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7358 && fragP
->fr_type
== rs_machine_dependent
7359 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7362 int bytes_added
= 0;
7364 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7365 /* Max out at 12. */
7366 min_bytes
= min_bytes_to_other_loop_end
7367 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7369 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7371 if (fragP
->tc_frag_data
.is_no_transform
)
7372 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7375 while (min_bytes
+ bytes_added
7376 < REQUIRED_LOOP_DIVIDING_BYTES
)
7380 if (fragP
->fr_var
< length
)
7381 as_fatal (_("fr_var %lu < length %d"),
7382 (long) fragP
->fr_var
, length
);
7385 assemble_nop (length
,
7386 fragP
->fr_literal
+ fragP
->fr_fix
);
7387 fragP
->fr_fix
+= length
;
7388 fragP
->fr_var
-= length
;
7390 bytes_added
+= length
;
7396 assert (fragP
->fr_type
!= rs_machine_dependent
7397 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7403 static offsetT
unrelaxed_frag_min_size (fragS
*);
7406 min_bytes_to_other_loop_end (fragS
*fragP
,
7407 fragS
*current_target
,
7411 fragS
*current_fragP
;
7413 for (current_fragP
= fragP
;
7415 current_fragP
= current_fragP
->fr_next
)
7417 if (current_fragP
->tc_frag_data
.is_loop_target
7418 && current_fragP
!= current_target
)
7421 offset
+= unrelaxed_frag_min_size (current_fragP
);
7423 if (offset
>= max_size
)
7431 unrelaxed_frag_min_size (fragS
*fragP
)
7433 offsetT size
= fragP
->fr_fix
;
7435 /* Add fill size. */
7436 if (fragP
->fr_type
== rs_fill
)
7437 size
+= fragP
->fr_offset
;
7444 unrelaxed_frag_max_size (fragS
*fragP
)
7446 offsetT size
= fragP
->fr_fix
;
7447 switch (fragP
->fr_type
)
7450 /* Empty frags created by the obstack allocation scheme
7451 end up with type 0. */
7456 size
+= fragP
->fr_offset
;
7464 /* No further adjustments needed. */
7466 case rs_machine_dependent
:
7467 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7468 size
+= fragP
->fr_var
;
7471 /* We had darn well better know how big it is. */
7480 /* Re-process all of the fragments looking to convert all
7481 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7484 1) the instruction size count to the loop end label
7485 is too short (<= 2 instructions),
7486 2) loop has a jump or branch in it
7489 1) workaround_all_short_loops is TRUE
7490 2) The generating loop was a 'loopgtz' or 'loopnez'
7491 3) the instruction size count to the loop end label is too short
7493 then convert this frag (and maybe the next one) to generate a NOP.
7494 In any case close it off with a .fill 0. */
7496 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7497 static bfd_boolean
branch_before_loop_end (fragS
*);
7500 xtensa_fix_short_loop_frags (void)
7505 /* When this routine is called, all of the subsections are still intact
7506 so we walk over subsections instead of sections. */
7507 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7508 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7511 fragS
*current_target
= NULL
;
7512 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7514 /* Walk over all of the fragments in a subsection. */
7515 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7517 if (fragP
->fr_type
== rs_machine_dependent
7518 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7519 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7522 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7523 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7524 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7525 current_opcode
= t_insn
.opcode
;
7526 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7527 current_opcode
) == 1);
7530 if (fragP
->fr_type
== rs_machine_dependent
7531 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7533 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7534 && (branch_before_loop_end (fragP
->fr_next
)
7535 || (workaround_all_short_loops
7536 && current_opcode
!= XTENSA_UNDEFINED
7537 && current_opcode
!= xtensa_loop_opcode
)))
7539 if (fragP
->tc_frag_data
.is_no_transform
)
7540 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7542 relax_frag_add_nop (fragP
);
7551 static int unrelaxed_frag_min_insn_count (fragS
*);
7554 count_insns_to_loop_end (fragS
*base_fragP
,
7555 bfd_boolean count_relax_add
,
7558 fragS
*fragP
= NULL
;
7563 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7565 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7566 if (insn_count
>= max_count
)
7569 if (count_relax_add
)
7571 if (fragP
->fr_type
== rs_machine_dependent
7572 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7574 /* In order to add the appropriate number of
7575 NOPs, we count an instruction for downstream
7578 if (insn_count
>= max_count
)
7588 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7590 xtensa_isa isa
= xtensa_default_isa
;
7591 static xtensa_insnbuf insnbuf
= NULL
;
7595 if (!fragP
->tc_frag_data
.is_insn
)
7599 insnbuf
= xtensa_insnbuf_alloc (isa
);
7601 /* Decode the fixed instructions. */
7602 while (offset
< fragP
->fr_fix
)
7606 xtensa_insnbuf_from_chars
7607 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7608 fmt
= xtensa_format_decode (isa
, insnbuf
);
7610 if (fmt
== XTENSA_UNDEFINED
)
7612 as_fatal (_("undecodable instruction in instruction frag"));
7615 offset
+= xtensa_format_length (isa
, fmt
);
7623 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7626 branch_before_loop_end (fragS
*base_fragP
)
7630 for (fragP
= base_fragP
;
7631 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7632 fragP
= fragP
->fr_next
)
7634 if (unrelaxed_frag_has_b_j (fragP
))
7642 unrelaxed_frag_has_b_j (fragS
*fragP
)
7644 static xtensa_insnbuf insnbuf
= NULL
;
7645 xtensa_isa isa
= xtensa_default_isa
;
7648 if (!fragP
->tc_frag_data
.is_insn
)
7652 insnbuf
= xtensa_insnbuf_alloc (isa
);
7654 /* Decode the fixed instructions. */
7655 while (offset
< fragP
->fr_fix
)
7660 xtensa_insnbuf_from_chars
7661 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7662 fmt
= xtensa_format_decode (isa
, insnbuf
);
7663 if (fmt
== XTENSA_UNDEFINED
)
7666 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7668 xtensa_opcode opcode
=
7669 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7670 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7671 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7674 offset
+= xtensa_format_length (isa
, fmt
);
7680 /* Checks to be made after initial assembly but before relaxation. */
7682 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7683 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7686 xtensa_sanity_check (void)
7693 as_where (&file_name
, &line
);
7694 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7695 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7699 /* Walk over all of the fragments in a subsection. */
7700 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7702 if (fragP
->fr_type
== rs_machine_dependent
7703 && fragP
->fr_subtype
== RELAX_SLOTS
7704 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7706 static xtensa_insnbuf insnbuf
= NULL
;
7709 if (fragP
->fr_opcode
!= NULL
)
7712 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7713 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7714 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7716 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7717 t_insn
.opcode
) == 1)
7719 if (is_empty_loop (&t_insn
, fragP
))
7721 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7722 as_bad (_("invalid empty loop"));
7724 if (!is_local_forward_loop (&t_insn
, fragP
))
7726 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7727 as_bad (_("loop target does not follow "
7728 "loop instruction in section"));
7735 new_logical_line (file_name
, line
);
7739 #define LOOP_IMMED_OPN 1
7741 /* Return TRUE if the loop target is the next non-zero fragment. */
7744 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7746 const expressionS
*expr
;
7750 if (insn
->insn_type
!= ITYPE_INSN
)
7753 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7756 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7759 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7761 if (expr
->X_op
!= O_symbol
)
7764 symbolP
= expr
->X_add_symbol
;
7768 if (symbol_get_frag (symbolP
) == NULL
)
7771 if (S_GET_VALUE (symbolP
) != 0)
7774 /* Walk through the zero-size fragments from this one. If we find
7775 the target fragment, then this is a zero-size loop. */
7777 for (next_fragP
= fragP
->fr_next
;
7779 next_fragP
= next_fragP
->fr_next
)
7781 if (next_fragP
== symbol_get_frag (symbolP
))
7783 if (next_fragP
->fr_fix
!= 0)
7791 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7793 const expressionS
*expr
;
7797 if (insn
->insn_type
!= ITYPE_INSN
)
7800 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7803 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7806 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7808 if (expr
->X_op
!= O_symbol
)
7811 symbolP
= expr
->X_add_symbol
;
7815 if (symbol_get_frag (symbolP
) == NULL
)
7818 /* Walk through fragments until we find the target.
7819 If we do not find the target, then this is an invalid loop. */
7821 for (next_fragP
= fragP
->fr_next
;
7823 next_fragP
= next_fragP
->fr_next
)
7825 if (next_fragP
== symbol_get_frag (symbolP
))
7833 #define XTINFO_NAME "Xtensa_Info"
7834 #define XTINFO_NAMESZ 12
7835 #define XTINFO_TYPE 1
7838 xtensa_add_config_info (void)
7844 info_sec
= subseg_new (".xtensa.info", 0);
7845 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7847 data
= xmalloc (100);
7848 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7849 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
7850 sz
= strlen (data
) + 1;
7852 /* Add enough null terminators to pad to a word boundary. */
7855 while ((sz
& 3) != 0);
7857 /* Follow the standard note section layout:
7858 First write the length of the name string. */
7860 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
7862 /* Next comes the length of the "descriptor", i.e., the actual data. */
7864 md_number_to_chars (p
, (valueT
) sz
, 4);
7866 /* Write the note type. */
7868 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
7870 /* Write the name field. */
7871 p
= frag_more (XTINFO_NAMESZ
);
7872 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
7874 /* Finally, write the descriptor. */
7876 memcpy (p
, data
, sz
);
7882 /* Alignment Functions. */
7885 get_text_align_power (unsigned target_size
)
7887 if (target_size
<= 4)
7889 assert (target_size
== 8);
7895 get_text_align_max_fill_size (int align_pow
,
7896 bfd_boolean use_nops
,
7897 bfd_boolean use_no_density
)
7900 return (1 << align_pow
);
7902 return 3 * (1 << align_pow
);
7904 return 1 + (1 << align_pow
);
7908 /* Calculate the minimum bytes of fill needed at "address" to align a
7909 target instruction of size "target_size" so that it does not cross a
7910 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7911 the fill can be an arbitrary number of bytes. Otherwise, the space must
7912 be filled by NOP instructions. */
7915 get_text_align_fill_size (addressT address
,
7918 bfd_boolean use_nops
,
7919 bfd_boolean use_no_density
)
7921 addressT alignment
, fill
, fill_limit
, fill_step
;
7922 bfd_boolean skip_one
= FALSE
;
7924 alignment
= (1 << align_pow
);
7925 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7929 fill_limit
= alignment
;
7932 else if (!use_no_density
)
7934 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7935 fill_limit
= alignment
* 2;
7941 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7942 fill_limit
= alignment
* 3;
7946 /* Try all fill sizes until finding one that works. */
7947 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7949 if (skip_one
&& fill
== 1)
7951 if ((address
+ fill
) >> align_pow
7952 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7961 branch_align_power (segT sec
)
7963 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7964 is aligned to at least an 8-byte boundary, then a branch target need
7965 only fit within an 8-byte aligned block of memory to avoid a stall.
7966 Otherwise, try to fit branch targets within 4-byte aligned blocks
7967 (which may be insufficient, e.g., if the section has no alignment, but
7968 it's good enough). */
7969 if (xtensa_fetch_width
== 8)
7971 if (get_recorded_alignment (sec
) >= 3)
7975 assert (xtensa_fetch_width
== 4);
7981 /* This will assert if it is not possible. */
7984 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7990 assert (fill_size
% 3 == 0);
7991 return (fill_size
/ 3);
7994 assert (fill_size
!= 1); /* Bad argument. */
7996 while (fill_size
> 1)
7999 if (fill_size
== 2 || fill_size
== 4)
8001 fill_size
-= insn_size
;
8004 assert (fill_size
!= 1); /* Bad algorithm. */
8010 get_text_align_nth_nop_size (offsetT fill_size
,
8012 bfd_boolean use_no_density
)
8019 assert (fill_size
!= 1); /* Bad argument. */
8021 while (fill_size
> 1)
8024 if (fill_size
== 2 || fill_size
== 4)
8026 fill_size
-= insn_size
;
8036 /* For the given fragment, find the appropriate address
8037 for it to begin at if we are using NOPs to align it. */
8040 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8042 /* The rule is: get next fragment's FIRST instruction. Find
8043 the smallest number of bytes that need to be added to
8044 ensure that the next fragment's FIRST instruction will fit
8047 E.G., 2 bytes : 0, 1, 2 mod 4
8050 If the FIRST instruction MIGHT be relaxed,
8051 assume that it will become a 3-byte instruction.
8053 Note again here that LOOP instructions are not bundleable,
8054 and this relaxation only applies to LOOP opcodes. */
8057 int first_insn_size
;
8059 addressT pre_opcode_bytes
;
8062 xtensa_opcode opcode
;
8063 bfd_boolean is_loop
;
8065 assert (fragP
->fr_type
== rs_machine_dependent
);
8066 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8068 /* Find the loop frag. */
8069 first_insn
= next_non_empty_frag (fragP
);
8070 /* Now find the first insn frag. */
8071 first_insn
= next_non_empty_frag (first_insn
);
8073 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8075 loop_insn_size
= xg_get_single_size (opcode
);
8077 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8078 pre_opcode_bytes
+= loop_insn_size
;
8080 /* For loops, the alignment depends on the size of the
8081 instruction following the loop, not the LOOP instruction. */
8083 if (first_insn
== NULL
)
8084 first_insn_size
= xtensa_fetch_width
;
8086 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8088 /* If it was 8, then we'll need a larger alignment for the section. */
8089 align_power
= get_text_align_power (first_insn_size
);
8090 record_alignment (now_seg
, align_power
);
8092 fill_size
= get_text_align_fill_size
8093 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8094 fragP
->tc_frag_data
.is_no_density
);
8096 return address
+ fill_size
;
8100 /* 3 mechanisms for relaxing an alignment:
8102 Align to a power of 2.
8103 Align so the next fragment's instruction does not cross a word boundary.
8104 Align the current instruction so that if the next instruction
8105 were 3 bytes, it would not cross a word boundary.
8109 zeros - This is easy; always insert zeros.
8110 nops - 3-byte and 2-byte instructions
8114 >=5 : 3-byte instruction + fn (n-3)
8115 widening - widen previous instructions. */
8118 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8120 addressT target_address
, loop_insn_offset
;
8122 xtensa_opcode loop_opcode
;
8123 bfd_boolean is_loop
;
8126 offsetT branch_align
;
8128 assert (fragP
->fr_type
== rs_machine_dependent
);
8129 switch (fragP
->fr_subtype
)
8131 case RELAX_DESIRE_ALIGN
:
8132 target_size
= next_frag_format_size (fragP
);
8133 if (target_size
== XTENSA_UNDEFINED
)
8135 align_power
= branch_align_power (now_seg
);
8136 branch_align
= 1 << align_power
;
8137 /* Don't count on the section alignment being as large as the target. */
8138 if (target_size
> branch_align
)
8139 target_size
= branch_align
;
8140 opt_diff
= get_text_align_fill_size (address
, align_power
,
8141 target_size
, FALSE
, FALSE
);
8143 *max_diff
= (opt_diff
+ branch_align
8144 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8145 assert (*max_diff
>= opt_diff
);
8148 case RELAX_ALIGN_NEXT_OPCODE
:
8149 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8150 loop_insn_offset
= 0;
8151 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8154 /* If the loop has been expanded then the LOOP instruction
8155 could be at an offset from this fragment. */
8156 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8158 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8160 /* In an ideal world, which is what we are shooting for here,
8161 we wouldn't need to use any NOPs immediately prior to the
8162 LOOP instruction. If this approach fails, relax_frag_loop_align
8163 will call get_noop_aligned_address. */
8165 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8166 align_power
= get_text_align_power (target_size
),
8167 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8168 target_size
, FALSE
, FALSE
);
8170 *max_diff
= xtensa_fetch_width
8171 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8172 - target_size
+ opt_diff
;
8173 assert (*max_diff
>= opt_diff
);
8184 /* md_relax_frag Hook and Helper Functions. */
8186 static long relax_frag_loop_align (fragS
*, long);
8187 static long relax_frag_for_align (fragS
*, long);
8188 static long relax_frag_immed
8189 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8192 /* Return the number of bytes added to this fragment, given that the
8193 input has been stretched already by "stretch". */
8196 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8198 xtensa_isa isa
= xtensa_default_isa
;
8199 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8200 long new_stretch
= 0;
8204 static xtensa_insnbuf vbuf
= NULL
;
8205 int slot
, num_slots
;
8208 as_where (&file_name
, &line
);
8209 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8211 fragP
->tc_frag_data
.unreported_expansion
= 0;
8213 switch (fragP
->fr_subtype
)
8215 case RELAX_ALIGN_NEXT_OPCODE
:
8216 /* Always convert. */
8217 if (fragP
->tc_frag_data
.relax_seen
)
8218 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8221 case RELAX_LOOP_END
:
8225 case RELAX_LOOP_END_ADD_NOP
:
8226 /* Add a NOP and switch to .fill 0. */
8227 new_stretch
= relax_frag_add_nop (fragP
);
8231 case RELAX_DESIRE_ALIGN
:
8232 /* Do nothing. The narrowing before this frag will either align
8237 case RELAX_LITERAL_FINAL
:
8240 case RELAX_LITERAL_NR
:
8242 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8243 assert (unreported
== lit_size
);
8244 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8245 fragP
->fr_var
-= lit_size
;
8246 fragP
->fr_fix
+= lit_size
;
8252 vbuf
= xtensa_insnbuf_alloc (isa
);
8254 xtensa_insnbuf_from_chars
8255 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8256 fmt
= xtensa_format_decode (isa
, vbuf
);
8257 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8259 for (slot
= 0; slot
< num_slots
; slot
++)
8261 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8264 if (fragP
->tc_frag_data
.relax_seen
)
8265 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8269 case RELAX_IMMED_STEP1
:
8270 case RELAX_IMMED_STEP2
:
8271 /* Place the immediate. */
8272 new_stretch
+= relax_frag_immed
8273 (now_seg
, fragP
, stretch
,
8274 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8275 fmt
, slot
, stretched_p
, FALSE
);
8279 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8285 case RELAX_LITERAL_POOL_BEGIN
:
8286 case RELAX_LITERAL_POOL_END
:
8287 case RELAX_MAYBE_UNREACHABLE
:
8288 case RELAX_MAYBE_DESIRE_ALIGN
:
8289 /* No relaxation required. */
8292 case RELAX_FILL_NOP
:
8293 case RELAX_UNREACHABLE
:
8294 if (fragP
->tc_frag_data
.relax_seen
)
8295 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8299 as_bad (_("bad relaxation state"));
8302 /* Tell gas we need another relaxation pass. */
8303 if (! fragP
->tc_frag_data
.relax_seen
)
8305 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8309 new_logical_line (file_name
, line
);
8315 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8317 addressT old_address
, old_next_address
, old_size
;
8318 addressT new_address
, new_next_address
, new_size
;
8321 /* All the frags with relax_frag_for_alignment prior to this one in the
8322 section have been done, hopefully eliminating the need for a NOP here.
8323 But, this will put it in if necessary. */
8325 /* Calculate the old address of this fragment and the next fragment. */
8326 old_address
= fragP
->fr_address
- stretch
;
8327 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8328 fragP
->tc_frag_data
.text_expansion
[0]);
8329 old_size
= old_next_address
- old_address
;
8331 /* Calculate the new address of this fragment and the next fragment. */
8332 new_address
= fragP
->fr_address
;
8334 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8335 new_size
= new_next_address
- new_address
;
8337 growth
= new_size
- old_size
;
8339 /* Fix up the text_expansion field and return the new growth. */
8340 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8345 /* Add a NOP instruction. */
8348 relax_frag_add_nop (fragS
*fragP
)
8350 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8351 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8352 assemble_nop (length
, nop_buf
);
8353 fragP
->tc_frag_data
.is_insn
= TRUE
;
8355 if (fragP
->fr_var
< length
)
8357 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8361 fragP
->fr_fix
+= length
;
8362 fragP
->fr_var
-= length
;
8367 static long future_alignment_required (fragS
*, long);
8370 relax_frag_for_align (fragS
*fragP
, long stretch
)
8372 /* Overview of the relaxation procedure for alignment:
8373 We can widen with NOPs or by widening instructions or by filling
8374 bytes after jump instructions. Find the opportune places and widen
8375 them if necessary. */
8380 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8381 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8382 || (fragP
->fr_subtype
== RELAX_SLOTS
8383 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8385 stretch_me
= future_alignment_required (fragP
, stretch
);
8386 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8392 /* We expanded on a previous pass. Can we shrink now? */
8393 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8394 if (shrink
<= stretch
&& stretch
> 0)
8396 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8402 /* Below here, diff > 0. */
8403 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8409 /* Return the address of the next frag that should be aligned.
8411 By "address" we mean the address it _would_ be at if there
8412 is no action taken to align it between here and the target frag.
8413 In other words, if no narrows and no fill nops are used between
8414 here and the frag to align, _even_if_ some of the frags we use
8415 to align targets have already expanded on a previous relaxation
8418 Also, count each frag that may be used to help align the target.
8420 Return 0 if there are no frags left in the chain that need to be
8424 find_address_of_next_align_frag (fragS
**fragPP
,
8428 bfd_boolean
*paddable
)
8430 fragS
*fragP
= *fragPP
;
8431 addressT address
= fragP
->fr_address
;
8433 /* Do not reset the counts to 0. */
8437 /* Limit this to a small search. */
8438 if (*widens
>= (int) xtensa_fetch_width
)
8443 address
+= fragP
->fr_fix
;
8445 if (fragP
->fr_type
== rs_fill
)
8446 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8447 else if (fragP
->fr_type
== rs_machine_dependent
)
8449 switch (fragP
->fr_subtype
)
8451 case RELAX_UNREACHABLE
:
8455 case RELAX_FILL_NOP
:
8457 if (!fragP
->tc_frag_data
.is_no_density
)
8462 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8467 address
+= total_frag_text_expansion (fragP
);;
8471 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8474 case RELAX_ALIGN_NEXT_OPCODE
:
8475 case RELAX_DESIRE_ALIGN
:
8479 case RELAX_MAYBE_UNREACHABLE
:
8480 case RELAX_MAYBE_DESIRE_ALIGN
:
8485 /* Just punt if we don't know the type. */
8492 /* Just punt if we don't know the type. */
8496 fragP
= fragP
->fr_next
;
8504 static long bytes_to_stretch (fragS
*, int, int, int, int);
8507 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8509 fragS
*this_frag
= fragP
;
8513 int narrow_nops
= 0;
8514 bfd_boolean paddable
= FALSE
;
8515 offsetT local_opt_diff
;
8518 int stretch_amount
= 0;
8519 int local_stretch_amount
;
8520 int global_stretch_amount
;
8522 address
= find_address_of_next_align_frag
8523 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8527 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8528 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8530 frag_wane (this_frag
);
8534 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8535 opt_diff
= local_opt_diff
;
8536 assert (opt_diff
>= 0);
8537 assert (max_diff
>= opt_diff
);
8542 fragP
= fragP
->fr_next
;
8544 while (fragP
&& opt_diff
< max_diff
&& address
)
8546 /* We only use these to determine if we can exit early
8547 because there will be plenty of ways to align future
8549 int glob_widens
= 0;
8552 bfd_boolean glob_pad
= 0;
8553 address
= find_address_of_next_align_frag
8554 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8555 /* If there is a padable portion, then skip. */
8556 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8561 offsetT next_m_diff
;
8562 offsetT next_o_diff
;
8564 /* Downrange frags haven't had stretch added to them yet. */
8567 /* The address also includes any text expansion from this
8568 frag in a previous pass, but we don't want that. */
8569 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8571 /* Assume we are going to move at least opt_diff. In
8572 reality, we might not be able to, but assuming that
8573 we will helps catch cases where moving opt_diff pushes
8574 the next target from aligned to unaligned. */
8575 address
+= opt_diff
;
8577 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8579 /* Now cleanup for the adjustments to address. */
8580 next_o_diff
+= opt_diff
;
8581 next_m_diff
+= opt_diff
;
8582 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8583 opt_diff
= next_o_diff
;
8584 if (next_m_diff
< max_diff
)
8585 max_diff
= next_m_diff
;
8586 fragP
= fragP
->fr_next
;
8590 /* If there are enough wideners in between, do it. */
8593 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8595 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8600 local_stretch_amount
8601 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8602 num_widens
, local_opt_diff
);
8603 global_stretch_amount
8604 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8605 num_widens
, opt_diff
);
8606 /* If the condition below is true, then the frag couldn't
8607 stretch the correct amount for the global case, so we just
8608 optimize locally. We'll rely on the subsequent frags to get
8609 the correct alignment in the global case. */
8610 if (global_stretch_amount
< local_stretch_amount
)
8611 stretch_amount
= local_stretch_amount
;
8613 stretch_amount
= global_stretch_amount
;
8615 if (this_frag
->fr_subtype
== RELAX_SLOTS
8616 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8617 assert (stretch_amount
<= 1);
8618 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8620 if (this_frag
->tc_frag_data
.is_no_density
)
8621 assert (stretch_amount
== 3 || stretch_amount
== 0);
8623 assert (stretch_amount
<= 3);
8626 return stretch_amount
;
8630 /* The idea: widen everything you can to get a target or loop aligned,
8631 then start using NOPs.
8633 When we must have a NOP, here is a table of how we decide
8634 (so you don't have to fight through the control flow below):
8636 wide_nops = the number of wide NOPs available for aligning
8637 narrow_nops = the number of narrow NOPs available for aligning
8638 (a subset of wide_nops)
8639 widens = the number of narrow instructions that should be widened
8646 b 0 1 1 (case 3a makes this case unnecessary)
8649 c 0 1 2 (case 4a makes this case unnecessary)
8652 c 0 2 1 (case 5b makes this case unnecessary)
8655 c 0 1 4 (case 6b makes this case unnecessary)
8656 d 1 1 1 (case 6a makes this case unnecessary)
8657 e 0 2 2 (case 6a makes this case unnecessary)
8658 f 0 3 0 (case 6a makes this case unnecessary)
8661 c 1 1 2 (case 7b makes this case unnecessary)
8662 d 0 1 5 (case 7a makes this case unnecessary)
8663 e 0 2 3 (case 7b makes this case unnecessary)
8664 f 0 3 1 (case 7b makes this case unnecessary)
8665 g 1 2 1 (case 7b makes this case unnecessary)
8669 bytes_to_stretch (fragS
*this_frag
,
8675 int bytes_short
= desired_diff
- num_widens
;
8677 assert (desired_diff
>= 0 && desired_diff
< 8);
8678 if (desired_diff
== 0)
8681 assert (wide_nops
> 0 || num_widens
> 0);
8683 /* Always prefer widening to NOP-filling. */
8684 if (bytes_short
< 0)
8686 /* There are enough RELAX_NARROW frags after this one
8687 to align the target without widening this frag in any way. */
8691 if (bytes_short
== 0)
8693 /* Widen every narrow between here and the align target
8694 and the align target will be properly aligned. */
8695 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8701 /* From here we will need at least one NOP to get an alignment.
8702 However, we may not be able to align at all, in which case,
8704 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8706 switch (desired_diff
)
8711 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8712 return 2; /* case 2 */
8718 return 3; /* case 3a */
8720 if (num_widens
>= 1 && wide_nops
== 1)
8721 return 3; /* case 4a */
8722 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8723 return 2; /* case 4b */
8726 if (num_widens
>= 2 && wide_nops
== 1)
8727 return 3; /* case 5a */
8728 /* We will need two nops. Are there enough nops
8729 between here and the align target? */
8730 if (wide_nops
< 2 || narrow_nops
== 0)
8732 /* Are there other nops closer that can serve instead? */
8733 if (wide_nops
> 2 && narrow_nops
> 1)
8735 /* Take the density one first, because there might not be
8736 another density one available. */
8737 if (!this_frag
->tc_frag_data
.is_no_density
)
8738 return 2; /* case 5b narrow */
8740 return 3; /* case 5b wide */
8744 return 3; /* case 6a */
8745 else if (num_widens
>= 3 && wide_nops
== 1)
8746 return 3; /* case 6b */
8749 if (wide_nops
== 1 && num_widens
>= 4)
8750 return 3; /* case 7a */
8751 else if (wide_nops
== 2 && num_widens
>= 1)
8752 return 3; /* case 7b */
8760 /* We will need a NOP no matter what, but should we widen
8761 this instruction to help?
8763 This is a RELAX_NARROW frag. */
8764 switch (desired_diff
)
8773 if (wide_nops
>= 1 && num_widens
== 1)
8774 return 1; /* case 4a */
8777 if (wide_nops
>= 1 && num_widens
== 2)
8778 return 1; /* case 5a */
8782 return 0; /* case 6a */
8783 else if (wide_nops
>= 1 && num_widens
== 3)
8784 return 1; /* case 6b */
8787 if (wide_nops
>= 1 && num_widens
== 4)
8788 return 1; /* case 7a */
8789 else if (wide_nops
>= 2 && num_widens
== 1)
8790 return 1; /* case 7b */
8803 relax_frag_immed (segT segP
,
8810 bfd_boolean estimate_only
)
8814 bfd_boolean negatable_branch
= FALSE
;
8815 bfd_boolean branch_jmp_to_next
= FALSE
;
8816 bfd_boolean wide_insn
= FALSE
;
8817 xtensa_isa isa
= xtensa_default_isa
;
8819 offsetT frag_offset
;
8822 int num_text_bytes
, num_literal_bytes
;
8823 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8825 assert (fragP
->fr_opcode
!= NULL
);
8827 xg_clear_vinsn (&cur_vinsn
);
8828 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8829 if (cur_vinsn
.num_slots
> 1)
8832 tinsn
= cur_vinsn
.slots
[slot
];
8833 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8835 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8838 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8839 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8841 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8843 old_size
= xtensa_format_length (isa
, fmt
);
8845 /* Special case: replace a branch to the next instruction with a NOP.
8846 This is required to work around a hardware bug in T1040.0 and also
8847 serves as an optimization. */
8849 if (branch_jmp_to_next
8850 && ((old_size
== 2) || (old_size
== 3))
8851 && !next_frag_is_loop_target (fragP
))
8854 /* Here is the fun stuff: Get the immediate field from this
8855 instruction. If it fits, we are done. If not, find the next
8856 instruction sequence that fits. */
8858 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8859 istack_init (&istack
);
8860 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8861 min_steps
, stretch
);
8862 if (num_steps
< min_steps
)
8864 as_fatal (_("internal error: relaxation failed"));
8868 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8870 as_fatal (_("internal error: relaxation requires too many steps"));
8874 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8876 /* Figure out the number of bytes needed. */
8878 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8880 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8882 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8884 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8887 num_text_bytes
+= old_size
;
8888 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8889 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8891 total_text_diff
= num_text_bytes
- old_size
;
8892 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8894 /* It MUST get larger. If not, we could get an infinite loop. */
8895 assert (num_text_bytes
>= 0);
8896 assert (literal_diff
>= 0);
8897 assert (total_text_diff
>= 0);
8899 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8900 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8901 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8902 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8904 /* Find the associated expandable literal for this. */
8905 if (literal_diff
!= 0)
8907 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8910 assert (literal_diff
== 4);
8911 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8913 /* We expect that the literal section state has NOT been
8915 assert (lit_fragP
->fr_type
== rs_machine_dependent
8916 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8917 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8919 /* We need to mark this section for another iteration
8925 if (negatable_branch
&& istack
.ninsn
> 1)
8926 update_next_frag_state (fragP
);
8928 return this_text_diff
;
8932 /* md_convert_frag Hook and Helper Functions. */
8934 static void convert_frag_align_next_opcode (fragS
*);
8935 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8936 static void convert_frag_fill_nop (fragS
*);
8937 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8940 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8942 static xtensa_insnbuf vbuf
= NULL
;
8943 xtensa_isa isa
= xtensa_default_isa
;
8950 as_where (&file_name
, &line
);
8951 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8953 switch (fragp
->fr_subtype
)
8955 case RELAX_ALIGN_NEXT_OPCODE
:
8956 /* Always convert. */
8957 convert_frag_align_next_opcode (fragp
);
8960 case RELAX_DESIRE_ALIGN
:
8961 /* Do nothing. If not aligned already, too bad. */
8965 case RELAX_LITERAL_FINAL
:
8970 vbuf
= xtensa_insnbuf_alloc (isa
);
8972 xtensa_insnbuf_from_chars
8973 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8974 fmt
= xtensa_format_decode (isa
, vbuf
);
8975 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8977 for (slot
= 0; slot
< num_slots
; slot
++)
8979 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8982 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8986 case RELAX_IMMED_STEP1
:
8987 case RELAX_IMMED_STEP2
:
8988 /* Place the immediate. */
8991 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8996 /* This is OK because some slots could have
8997 relaxations and others have none. */
9003 case RELAX_UNREACHABLE
:
9004 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9005 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9006 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9010 case RELAX_MAYBE_UNREACHABLE
:
9011 case RELAX_MAYBE_DESIRE_ALIGN
:
9015 case RELAX_FILL_NOP
:
9016 convert_frag_fill_nop (fragp
);
9019 case RELAX_LITERAL_NR
:
9020 if (use_literal_section
)
9022 /* This should have been handled during relaxation. When
9023 relaxing a code segment, literals sometimes need to be
9024 added to the corresponding literal segment. If that
9025 literal segment has already been relaxed, then we end up
9026 in this situation. Marking the literal segments as data
9027 would make this happen less often (since GAS always relaxes
9028 code before data), but we could still get into trouble if
9029 there are instructions in a segment that is not marked as
9030 containing code. Until we can implement a better solution,
9031 cheat and adjust the addresses of all the following frags.
9032 This could break subsequent alignments, but the linker's
9033 literal coalescing will do that anyway. */
9036 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9037 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9038 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9041 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9045 as_bad (_("invalid relaxation fragment result"));
9050 new_logical_line (file_name
, line
);
9055 convert_frag_align_next_opcode (fragS
*fragp
)
9057 char *nop_buf
; /* Location for Writing. */
9058 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9059 addressT aligned_address
;
9063 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9065 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9066 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9067 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9069 for (nop
= 0; nop
< nop_count
; nop
++)
9072 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9074 assemble_nop (nop_size
, nop_buf
);
9075 nop_buf
+= nop_size
;
9078 fragp
->fr_fix
+= fill_size
;
9079 fragp
->fr_var
-= fill_size
;
9084 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9086 TInsn tinsn
, single_target
;
9087 int size
, old_size
, diff
;
9088 offsetT frag_offset
;
9091 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9093 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9095 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9096 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9097 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9102 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9104 /* No conversion. */
9109 assert (fragP
->fr_opcode
!= NULL
);
9111 /* Frags in this relaxation state should only contain
9112 single instruction bundles. */
9113 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9115 /* Just convert it to a wide form.... */
9117 old_size
= xg_get_single_size (tinsn
.opcode
);
9119 tinsn_init (&single_target
);
9120 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9122 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9124 as_bad (_("unable to widen instruction"));
9128 size
= xg_get_single_size (single_target
.opcode
);
9129 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9132 diff
= size
- old_size
;
9134 assert (diff
<= fragP
->fr_var
);
9135 fragP
->fr_var
-= diff
;
9136 fragP
->fr_fix
+= diff
;
9144 convert_frag_fill_nop (fragS
*fragP
)
9146 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9147 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9148 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9149 - fragP
->fr_address
- fragP
->fr_fix
));
9152 /* No conversion. */
9156 assemble_nop (size
, loc
);
9157 fragP
->tc_frag_data
.is_insn
= TRUE
;
9158 fragP
->fr_var
-= size
;
9159 fragP
->fr_fix
+= size
;
9164 static fixS
*fix_new_exp_in_seg
9165 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9166 bfd_reloc_code_real_type
);
9167 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9170 convert_frag_immed (segT segP
,
9176 char *immed_instr
= fragP
->fr_opcode
;
9178 bfd_boolean expanded
= FALSE
;
9179 bfd_boolean branch_jmp_to_next
= FALSE
;
9180 char *fr_opcode
= fragP
->fr_opcode
;
9181 xtensa_isa isa
= xtensa_default_isa
;
9182 bfd_boolean wide_insn
= FALSE
;
9184 bfd_boolean is_loop
;
9186 assert (fr_opcode
!= NULL
);
9188 xg_clear_vinsn (&cur_vinsn
);
9190 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9191 if (cur_vinsn
.num_slots
> 1)
9194 orig_tinsn
= cur_vinsn
.slots
[slot
];
9195 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9197 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9199 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9200 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9202 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9204 /* Conversion just inserts a NOP and marks the fix as completed. */
9205 bytes
= xtensa_format_length (isa
, fmt
);
9208 cur_vinsn
.slots
[slot
].opcode
=
9209 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9210 cur_vinsn
.slots
[slot
].ntok
= 0;
9214 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9215 assert (bytes
== 2 || bytes
== 3);
9216 build_nop (&cur_vinsn
.slots
[0], bytes
);
9217 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9219 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9220 xtensa_insnbuf_to_chars
9221 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9226 /* Here is the fun stuff: Get the immediate field from this
9227 instruction. If it fits, we're done. If not, find the next
9228 instruction sequence that fits. */
9232 symbolS
*lit_sym
= NULL
;
9234 int target_offset
= 0;
9237 symbolS
*gen_label
= NULL
;
9238 offsetT frag_offset
;
9239 bfd_boolean first
= TRUE
;
9240 bfd_boolean last_is_jump
;
9242 /* It does not fit. Find something that does and
9243 convert immediately. */
9244 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9245 istack_init (&istack
);
9246 xg_assembly_relax (&istack
, &orig_tinsn
,
9247 segP
, fragP
, frag_offset
, min_steps
, 0);
9249 old_size
= xtensa_format_length (isa
, fmt
);
9251 /* Assemble this right inline. */
9253 /* First, create the mapping from a label name to the REAL label. */
9255 for (i
= 0; i
< istack
.ninsn
; i
++)
9257 TInsn
*tinsn
= &istack
.insn
[i
];
9260 switch (tinsn
->insn_type
)
9263 if (lit_sym
!= NULL
)
9264 as_bad (_("multiple literals in expansion"));
9265 /* First find the appropriate space in the literal pool. */
9266 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9267 if (lit_frag
== NULL
)
9268 as_bad (_("no registered fragment for literal"));
9269 if (tinsn
->ntok
!= 1)
9270 as_bad (_("number of literal tokens != 1"));
9272 /* Set the literal symbol and add a fixup. */
9273 lit_sym
= lit_frag
->fr_symbol
;
9277 if (align_targets
&& !is_loop
)
9279 fragS
*unreach
= fragP
->fr_next
;
9280 while (!(unreach
->fr_type
== rs_machine_dependent
9281 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9282 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9284 unreach
= unreach
->fr_next
;
9287 assert (unreach
->fr_type
== rs_machine_dependent
9288 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9289 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9291 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9293 assert (gen_label
== NULL
);
9294 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9295 fr_opcode
- fragP
->fr_literal
9296 + target_offset
, fragP
);
9300 if (first
&& wide_insn
)
9302 target_offset
+= xtensa_format_length (isa
, fmt
);
9304 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9305 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9308 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9315 last_is_jump
= FALSE
;
9316 for (i
= 0; i
< istack
.ninsn
; i
++)
9318 TInsn
*tinsn
= &istack
.insn
[i
];
9322 bfd_reloc_code_real_type reloc_type
;
9324 switch (tinsn
->insn_type
)
9327 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9328 /* Already checked. */
9329 assert (lit_frag
!= NULL
);
9330 assert (lit_sym
!= NULL
);
9331 assert (tinsn
->ntok
== 1);
9333 target_seg
= S_GET_SEGMENT (lit_sym
);
9334 assert (target_seg
);
9335 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9336 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9337 &tinsn
->tok
[0], FALSE
, reloc_type
);
9344 xg_resolve_labels (tinsn
, gen_label
);
9345 xg_resolve_literals (tinsn
, lit_sym
);
9346 if (wide_insn
&& first
)
9349 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9351 cur_vinsn
.slots
[slot
] = *tinsn
;
9355 cur_vinsn
.slots
[slot
].opcode
=
9356 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9357 cur_vinsn
.slots
[slot
].ntok
= 0;
9359 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9360 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9361 (unsigned char *) immed_instr
, 0);
9362 fragP
->tc_frag_data
.is_insn
= TRUE
;
9363 size
= xtensa_format_length (isa
, fmt
);
9364 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9367 (tinsn
, immed_instr
+ size
, fragP
,
9368 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9369 size
+= xg_get_single_size (tinsn
->opcode
);
9374 size
= xg_get_single_size (tinsn
->opcode
);
9375 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9376 immed_instr
- fragP
->fr_literal
, TRUE
);
9378 immed_instr
+= size
;
9384 diff
= total_size
- old_size
;
9388 assert (diff
<= fragP
->fr_var
);
9389 fragP
->fr_var
-= diff
;
9390 fragP
->fr_fix
+= diff
;
9393 /* Check for undefined immediates in LOOP instructions. */
9397 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9398 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9400 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9403 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9404 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9406 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9411 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9412 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9414 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9416 /* Add an expansion note on the expanded instruction. */
9417 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9418 &orig_tinsn
.tok
[0], TRUE
,
9419 BFD_RELOC_XTENSA_ASM_EXPAND
);
9424 /* Add a new fix expression into the desired segment. We have to
9425 switch to that segment to do this. */
9428 fix_new_exp_in_seg (segT new_seg
,
9435 bfd_reloc_code_real_type r_type
)
9439 subsegT subseg
= now_subseg
;
9441 assert (new_seg
!= 0);
9442 subseg_set (new_seg
, new_subseg
);
9444 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9445 subseg_set (seg
, subseg
);
9450 /* Relax a loop instruction so that it can span loop >256 bytes.
9456 addi as, as, lo8 (label-.L1)
9457 addmi as, as, mid8 (label-.L1)
9468 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9473 unsigned long target
;
9474 static xtensa_insnbuf insnbuf
= NULL
;
9475 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9476 xtensa_isa isa
= xtensa_default_isa
;
9477 addressT loop_offset
;
9478 addressT addi_offset
= 9;
9479 addressT addmi_offset
= 12;
9484 insnbuf
= xtensa_insnbuf_alloc (isa
);
9486 /* Get the loop offset. */
9487 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9489 /* Validate that there really is a LOOP at the loop_offset. Because
9490 loops are not bundleable, we can assume that the instruction will be
9492 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9493 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9495 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9496 addi_offset
+= loop_offset
;
9497 addmi_offset
+= loop_offset
;
9499 assert (tinsn
->ntok
== 2);
9500 if (tinsn
->tok
[1].X_op
== O_constant
)
9501 target
= tinsn
->tok
[1].X_add_number
;
9502 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9504 /* Find the fragment. */
9505 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9506 assert (S_GET_SEGMENT (sym
) == segP
9507 || S_GET_SEGMENT (sym
) == absolute_section
);
9508 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9512 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9516 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9517 loop_length_hi
= loop_length
& ~0x0ff;
9518 loop_length_lo
= loop_length
& 0x0ff;
9519 if (loop_length_lo
>= 128)
9521 loop_length_lo
-= 256;
9522 loop_length_hi
+= 256;
9525 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9526 32512. If the loop is larger than that, then we just fail. */
9527 if (loop_length_hi
> 32512)
9528 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9529 _("loop too long for LOOP instruction"));
9531 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9532 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9534 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9535 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9537 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9538 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9540 fragP
->tc_frag_data
.is_insn
= TRUE
;
9541 xtensa_insnbuf_to_chars
9542 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9544 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9545 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9546 xtensa_insnbuf_to_chars
9547 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9549 /* Walk through all of the frags from here to the loop end
9550 and mark them as no_transform to keep them from being modified
9551 by the linker. If we ever have a relocation for the
9552 addi/addmi of the difference of two symbols we can remove this. */
9555 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9556 next_fragP
= next_fragP
->fr_next
)
9558 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9559 if (next_fragP
->tc_frag_data
.is_loop_target
)
9561 if (target_count
== 2)
9567 /* A map that keeps information on a per-subsegment basis. This is
9568 maintained during initial assembly, but is invalid once the
9569 subsegments are smashed together. I.E., it cannot be used during
9572 typedef struct subseg_map_struct
9580 float total_freq
; /* fall-through + branch target frequency */
9581 float target_freq
; /* branch target frequency alone */
9583 struct subseg_map_struct
*next
;
9587 static subseg_map
*sseg_map
= NULL
;
9590 get_subseg_info (segT seg
, subsegT subseg
)
9592 subseg_map
*subseg_e
;
9594 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9596 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9604 add_subseg_info (segT seg
, subsegT subseg
)
9606 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9607 memset (subseg_e
, 0, sizeof (subseg_map
));
9608 subseg_e
->seg
= seg
;
9609 subseg_e
->subseg
= subseg
;
9610 subseg_e
->flags
= 0;
9611 /* Start off considering every branch target very important. */
9612 subseg_e
->target_freq
= 1.0;
9613 subseg_e
->total_freq
= 1.0;
9614 subseg_e
->next
= sseg_map
;
9615 sseg_map
= subseg_e
;
9621 get_last_insn_flags (segT seg
, subsegT subseg
)
9623 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9625 return subseg_e
->flags
;
9631 set_last_insn_flags (segT seg
,
9636 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9638 subseg_e
= add_subseg_info (seg
, subseg
);
9640 subseg_e
->flags
|= fl
;
9642 subseg_e
->flags
&= ~fl
;
9647 get_subseg_total_freq (segT seg
, subsegT subseg
)
9649 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9651 return subseg_e
->total_freq
;
9657 get_subseg_target_freq (segT seg
, subsegT subseg
)
9659 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9661 return subseg_e
->target_freq
;
9667 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9669 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9671 subseg_e
= add_subseg_info (seg
, subseg
);
9672 subseg_e
->total_freq
= total_f
;
9673 subseg_e
->target_freq
= target_f
;
9677 /* Segment Lists and emit_state Stuff. */
9680 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9685 segT literal_section
= head
->seg
;
9687 /* Move the literal section to the front of the section list. */
9688 assert (literal_section
);
9689 if (literal_section
!= stdoutput
->sections
)
9691 bfd_section_list_remove (stdoutput
, literal_section
);
9692 bfd_section_list_prepend (stdoutput
, literal_section
);
9699 static void mark_literal_frags (seg_list
*);
9702 xtensa_move_literals (void)
9705 frchainS
*frchain_from
, *frchain_to
;
9706 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9707 fragS
**frag_splice
;
9710 fixS
*fix
, *next_fix
, **fix_splice
;
9713 mark_literal_frags (literal_head
->next
);
9715 if (use_literal_section
)
9718 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9720 /* Keep the literals for .init and .fini in separate sections. */
9721 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9722 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9725 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9726 search_frag
= frchain_from
->frch_root
;
9727 literal_pool
= NULL
;
9729 frag_splice
= &(frchain_from
->frch_root
);
9731 while (!search_frag
->tc_frag_data
.literal_frag
)
9733 assert (search_frag
->fr_fix
== 0
9734 || search_frag
->fr_type
== rs_align
);
9735 search_frag
= search_frag
->fr_next
;
9738 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9739 == RELAX_LITERAL_POOL_BEGIN
);
9740 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9742 /* Make sure that all the frags in this series are closed, and
9743 that there is at least one left over of zero-size. This
9744 prevents us from making a segment with an frchain without any
9746 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9747 xtensa_set_frag_assembly_state (frag_now
);
9748 last_frag
= frag_now
;
9749 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9750 xtensa_set_frag_assembly_state (frag_now
);
9752 while (search_frag
!= frag_now
)
9754 next_frag
= search_frag
->fr_next
;
9756 /* First, move the frag out of the literal section and
9757 to the appropriate place. */
9758 if (search_frag
->tc_frag_data
.literal_frag
)
9760 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9761 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9762 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9763 assert (frchain_to
);
9765 insert_after
= literal_pool
;
9767 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9768 insert_after
= insert_after
->fr_next
;
9770 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9772 *frag_splice
= next_frag
;
9773 search_frag
->fr_next
= insert_after
->fr_next
;
9774 insert_after
->fr_next
= search_frag
;
9775 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9777 /* Now move any fixups associated with this frag to the
9779 fix
= frchain_from
->fix_root
;
9780 fix_splice
= &(frchain_from
->fix_root
);
9783 next_fix
= fix
->fx_next
;
9784 if (fix
->fx_frag
== search_frag
)
9786 *fix_splice
= next_fix
;
9787 fix
->fx_next
= frchain_to
->fix_root
;
9788 frchain_to
->fix_root
= fix
;
9789 if (frchain_to
->fix_tail
== NULL
)
9790 frchain_to
->fix_tail
= fix
;
9793 fix_splice
= &(fix
->fx_next
);
9796 search_frag
= next_frag
;
9799 if (frchain_from
->fix_root
!= NULL
)
9801 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9802 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9804 assert (frchain_from
->fix_root
== NULL
);
9806 frchain_from
->fix_tail
= NULL
;
9807 xtensa_restore_emit_state (&state
);
9810 /* Now fix up the SEGMENT value for all the literal symbols. */
9811 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9813 symbolS
*lit_sym
= lit
->sym
;
9814 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9816 S_SET_SEGMENT (lit_sym
, dest_seg
);
9821 /* Walk over all the frags for segments in a list and mark them as
9822 containing literals. As clunky as this is, we can't rely on frag_var
9823 and frag_variant to get called in all situations. */
9826 mark_literal_frags (seg_list
*segment
)
9828 frchainS
*frchain_from
;
9833 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9834 search_frag
= frchain_from
->frch_root
;
9837 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9838 search_frag
= search_frag
->fr_next
;
9840 segment
= segment
->next
;
9846 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9848 /* Move all of the sections in the section list to come
9849 after "after" in the gnu segment list. */
9854 segT literal_section
= head
->seg
;
9856 /* Move the literal section after "after". */
9857 assert (literal_section
);
9858 if (literal_section
!= after
)
9860 bfd_section_list_remove (stdoutput
, literal_section
);
9861 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9869 /* Push all the literal segments to the end of the gnu list. */
9872 xtensa_reorder_segments (void)
9879 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9885 /* Now that we have the last section, push all the literal
9886 sections to the end. */
9887 xtensa_reorder_seg_list (literal_head
, last_sec
);
9889 /* Now perform the final error check. */
9890 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9892 assert (new_count
== old_count
);
9896 /* Change the emit state (seg, subseg, and frag related stuff) to the
9897 correct location. Return a emit_state which can be passed to
9898 xtensa_restore_emit_state to return to current fragment. */
9901 xtensa_switch_to_literal_fragment (emit_state
*result
)
9903 if (directive_state
[directive_absolute_literals
])
9905 segT lit4_seg
= cache_literal_section (TRUE
);
9906 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
9909 xtensa_switch_to_non_abs_literal_fragment (result
);
9911 /* Do a 4-byte align here. */
9912 frag_align (2, 0, 0);
9913 record_alignment (now_seg
, 2);
9918 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9920 static bfd_boolean recursive
= FALSE
;
9921 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9923 bfd_boolean is_init
=
9924 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9925 bfd_boolean is_fini
=
9926 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9928 if (pool_location
== NULL
9929 && !use_literal_section
9931 && !is_init
&& ! is_fini
)
9933 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9935 /* When we mark a literal pool location, we want to put a frag in
9936 the literal pool that points to it. But to do that, we want to
9937 switch_to_literal_fragment. But literal sections don't have
9938 literal pools, so their location is always null, so we would
9939 recurse forever. This is kind of hacky, but it works. */
9942 xtensa_mark_literal_pool_location ();
9946 lit_seg
= cache_literal_section (FALSE
);
9947 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
9949 if (!use_literal_section
9950 && !is_init
&& !is_fini
9951 && get_literal_pool_location (now_seg
) != pool_location
)
9953 /* Close whatever frag is there. */
9954 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9955 xtensa_set_frag_assembly_state (frag_now
);
9956 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9957 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9958 xtensa_set_frag_assembly_state (frag_now
);
9963 /* Call this function before emitting data into the literal section.
9964 This is a helper function for xtensa_switch_to_literal_fragment.
9965 This is similar to a .section new_now_seg subseg. */
9968 xtensa_switch_section_emit_state (emit_state
*state
,
9970 subsegT new_now_subseg
)
9972 state
->name
= now_seg
->name
;
9973 state
->now_seg
= now_seg
;
9974 state
->now_subseg
= now_subseg
;
9975 state
->generating_literals
= generating_literals
;
9976 generating_literals
++;
9977 subseg_set (new_now_seg
, new_now_subseg
);
9981 /* Use to restore the emitting into the normal place. */
9984 xtensa_restore_emit_state (emit_state
*state
)
9986 generating_literals
= state
->generating_literals
;
9987 subseg_set (state
->now_seg
, state
->now_subseg
);
9991 /* Predicate function used to look up a section in a particular group. */
9994 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
9996 const char *gname
= inf
;
9997 const char *group_name
= elf_group_name (sec
);
9999 return (group_name
== gname
10000 || (group_name
!= NULL
10002 && strcmp (group_name
, gname
) == 0));
10006 /* Get the literal section to be used for the current text section.
10007 The result may be cached in the default_lit_sections structure. */
10010 cache_literal_section (bfd_boolean use_abs_literals
)
10012 const char *text_name
, *group_name
= 0;
10013 char *base_name
, *name
, *suffix
;
10015 segT seg
, current_section
;
10016 int current_subsec
;
10017 bfd_boolean linkonce
= FALSE
;
10019 /* Save the current section/subsection. */
10020 current_section
= now_seg
;
10021 current_subsec
= now_subseg
;
10023 /* Clear the cached values if they are no longer valid. */
10024 if (now_seg
!= default_lit_sections
.current_text_seg
)
10026 default_lit_sections
.current_text_seg
= now_seg
;
10027 default_lit_sections
.lit_seg
= NULL
;
10028 default_lit_sections
.lit4_seg
= NULL
;
10031 /* Check if the literal section is already cached. */
10032 if (use_abs_literals
)
10033 pcached
= &default_lit_sections
.lit4_seg
;
10035 pcached
= &default_lit_sections
.lit_seg
;
10040 text_name
= default_lit_sections
.lit_prefix
;
10041 if (! text_name
|| ! *text_name
)
10043 text_name
= segment_name (current_section
);
10044 group_name
= elf_group_name (current_section
);
10045 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10048 base_name
= use_abs_literals
? ".lit4" : ".literal";
10051 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10052 sprintf (name
, "%s.%s", base_name
, group_name
);
10054 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10056 suffix
= strchr (text_name
+ linkonce_len
, '.');
10058 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10059 + (suffix
? strlen (suffix
) : 0));
10060 strcpy (name
, ".gnu.linkonce");
10061 strcat (name
, base_name
);
10063 strcat (name
, suffix
);
10068 /* If the section name ends with ".text", then replace that suffix
10069 instead of appending an additional suffix. */
10070 size_t len
= strlen (text_name
);
10071 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10074 name
= xmalloc (len
+ strlen (base_name
) + 1);
10075 strcpy (name
, text_name
);
10076 strcpy (name
+ len
, base_name
);
10079 /* Canonicalize section names to allow renaming literal sections.
10080 The group name, if any, came from the current text section and
10081 has already been canonicalized. */
10082 name
= tc_canonicalize_symbol_name (name
);
10084 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10085 (void *) group_name
);
10090 seg
= subseg_force_new (name
, 0);
10092 if (! use_abs_literals
)
10094 /* Add the newly created literal segment to the list. */
10095 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10097 n
->next
= literal_head
->next
;
10098 literal_head
->next
= n
;
10101 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10102 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10103 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10105 elf_group_name (seg
) = group_name
;
10107 bfd_set_section_flags (stdoutput
, seg
, flags
);
10108 bfd_set_section_alignment (stdoutput
, seg
, 2);
10112 subseg_set (current_section
, current_subsec
);
10117 /* Property Tables Stuff. */
10119 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10120 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10121 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10123 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10124 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10126 static bfd_boolean
get_frag_is_literal (const fragS
*);
10127 static void xtensa_create_property_segments
10128 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10129 static void xtensa_create_xproperty_segments
10130 (frag_flags_fn
, const char *, xt_section_type
);
10131 static segment_info_type
*retrieve_segment_info (segT
);
10132 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10133 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10134 static void add_xt_block_frags
10135 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10136 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10137 static void xtensa_frag_flags_init (frag_flags
*);
10138 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10139 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10140 static void add_xt_prop_frags
10141 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10143 /* Set up property tables after relaxation. */
10146 xtensa_post_relax_hook (void)
10148 xtensa_move_seg_list_to_beginning (literal_head
);
10150 xtensa_find_unmarked_state_frags ();
10152 xtensa_create_property_segments (get_frag_is_literal
,
10154 XTENSA_LIT_SEC_NAME
,
10156 xtensa_create_xproperty_segments (get_frag_property_flags
,
10157 XTENSA_PROP_SEC_NAME
,
10160 if (warn_unaligned_branch_targets
)
10161 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10162 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10166 /* This function is only meaningful after xtensa_move_literals. */
10169 get_frag_is_literal (const fragS
*fragP
)
10171 assert (fragP
!= NULL
);
10172 return fragP
->tc_frag_data
.is_literal
;
10177 xtensa_create_property_segments (frag_predicate property_function
,
10178 frag_predicate end_property_function
,
10179 const char *section_name_base
,
10180 xt_section_type sec_type
)
10184 /* Walk over all of the current segments.
10185 Walk over each fragment
10186 For each non-empty fragment,
10187 Build a property record (append where possible). */
10189 for (seclist
= &stdoutput
->sections
;
10190 seclist
&& *seclist
;
10191 seclist
= &(*seclist
)->next
)
10193 segT sec
= *seclist
;
10196 flags
= bfd_get_section_flags (stdoutput
, sec
);
10197 if (flags
& SEC_DEBUGGING
)
10199 if (!(flags
& SEC_ALLOC
))
10202 if (section_has_property (sec
, property_function
))
10205 xtensa_get_property_section (sec
, section_name_base
);
10206 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10207 xtensa_block_info
**xt_blocks
=
10208 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10209 /* Walk over all of the frchains here and add new sections. */
10210 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10211 end_property_function
);
10215 /* Now we fill them out.... */
10217 for (seclist
= &stdoutput
->sections
;
10218 seclist
&& *seclist
;
10219 seclist
= &(*seclist
)->next
)
10221 segment_info_type
*seginfo
;
10222 xtensa_block_info
*block
;
10223 segT sec
= *seclist
;
10225 seginfo
= seg_info (sec
);
10226 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10230 xtensa_block_info
*cur_block
;
10231 /* This is a section with some data. */
10233 bfd_size_type rec_size
;
10235 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10238 rec_size
= num_recs
* 8;
10239 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10241 /* In order to make this work with the assembler, we have to
10242 build some frags and then build the "fixups" for it. It
10243 would be easier to just set the contents then set the
10248 /* Allocate a fragment and leak it. */
10250 bfd_size_type frag_size
;
10252 frchainS
*frchainP
;
10256 frag_size
= sizeof (fragS
) + rec_size
;
10257 fragP
= (fragS
*) xmalloc (frag_size
);
10259 memset (fragP
, 0, frag_size
);
10260 fragP
->fr_address
= 0;
10261 fragP
->fr_next
= NULL
;
10262 fragP
->fr_fix
= rec_size
;
10264 fragP
->fr_type
= rs_fill
;
10265 /* The rest are zeros. */
10267 frchainP
= seginfo
->frchainP
;
10268 frchainP
->frch_root
= fragP
;
10269 frchainP
->frch_last
= fragP
;
10271 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10272 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10274 seginfo
->fix_root
= fixes
;
10275 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10277 frag_data
= &fragP
->fr_literal
[0];
10278 for (i
= 0; i
< num_recs
; i
++)
10280 fixS
*fix
= &fixes
[i
];
10281 assert (cur_block
);
10283 /* Write the fixup. */
10284 if (i
!= num_recs
- 1)
10285 fix
->fx_next
= &fixes
[i
+ 1];
10287 fix
->fx_next
= NULL
;
10290 fix
->fx_frag
= fragP
;
10291 fix
->fx_where
= i
* 8;
10292 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10293 fix
->fx_offset
= cur_block
->offset
;
10294 fix
->fx_r_type
= BFD_RELOC_32
;
10295 fix
->fx_file
= "Internal Assembly";
10298 /* Write the length. */
10299 md_number_to_chars (&frag_data
[4 + 8 * i
],
10300 cur_block
->size
, 4);
10301 cur_block
= cur_block
->next
;
10310 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10311 const char *section_name_base
,
10312 xt_section_type sec_type
)
10316 /* Walk over all of the current segments.
10317 Walk over each fragment.
10318 For each fragment that has instructions,
10319 build an instruction record (append where possible). */
10321 for (seclist
= &stdoutput
->sections
;
10322 seclist
&& *seclist
;
10323 seclist
= &(*seclist
)->next
)
10325 segT sec
= *seclist
;
10328 flags
= bfd_get_section_flags (stdoutput
, sec
);
10329 if ((flags
& SEC_DEBUGGING
)
10330 || !(flags
& SEC_ALLOC
)
10331 || (flags
& SEC_MERGE
))
10334 if (section_has_xproperty (sec
, flag_fn
))
10337 xtensa_get_property_section (sec
, section_name_base
);
10338 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10339 xtensa_block_info
**xt_blocks
=
10340 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10341 /* Walk over all of the frchains here and add new sections. */
10342 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10346 /* Now we fill them out.... */
10348 for (seclist
= &stdoutput
->sections
;
10349 seclist
&& *seclist
;
10350 seclist
= &(*seclist
)->next
)
10352 segment_info_type
*seginfo
;
10353 xtensa_block_info
*block
;
10354 segT sec
= *seclist
;
10356 seginfo
= seg_info (sec
);
10357 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10361 xtensa_block_info
*cur_block
;
10362 /* This is a section with some data. */
10364 bfd_size_type rec_size
;
10366 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10369 rec_size
= num_recs
* (8 + 4);
10370 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10372 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10374 /* In order to make this work with the assembler, we have to build
10375 some frags then build the "fixups" for it. It would be easier to
10376 just set the contents then set the arlents. */
10380 /* Allocate a fragment and (unfortunately) leak it. */
10382 bfd_size_type frag_size
;
10384 frchainS
*frchainP
;
10388 frag_size
= sizeof (fragS
) + rec_size
;
10389 fragP
= (fragS
*) xmalloc (frag_size
);
10391 memset (fragP
, 0, frag_size
);
10392 fragP
->fr_address
= 0;
10393 fragP
->fr_next
= NULL
;
10394 fragP
->fr_fix
= rec_size
;
10396 fragP
->fr_type
= rs_fill
;
10397 /* The rest are zeros. */
10399 frchainP
= seginfo
->frchainP
;
10400 frchainP
->frch_root
= fragP
;
10401 frchainP
->frch_last
= fragP
;
10403 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10404 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10406 seginfo
->fix_root
= fixes
;
10407 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10409 frag_data
= &fragP
->fr_literal
[0];
10410 for (i
= 0; i
< num_recs
; i
++)
10412 fixS
*fix
= &fixes
[i
];
10413 assert (cur_block
);
10415 /* Write the fixup. */
10416 if (i
!= num_recs
- 1)
10417 fix
->fx_next
= &fixes
[i
+ 1];
10419 fix
->fx_next
= NULL
;
10422 fix
->fx_frag
= fragP
;
10423 fix
->fx_where
= i
* (8 + 4);
10424 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10425 fix
->fx_offset
= cur_block
->offset
;
10426 fix
->fx_r_type
= BFD_RELOC_32
;
10427 fix
->fx_file
= "Internal Assembly";
10430 /* Write the length. */
10431 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10432 cur_block
->size
, 4);
10433 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10434 frag_flags_to_number (&cur_block
->flags
),
10436 cur_block
= cur_block
->next
;
10444 static segment_info_type
*
10445 retrieve_segment_info (segT seg
)
10447 segment_info_type
*seginfo
;
10448 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10451 frchainS
*frchainP
;
10453 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10454 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10455 seginfo
->fix_root
= NULL
;
10456 seginfo
->fix_tail
= NULL
;
10457 seginfo
->bfd_section
= seg
;
10459 /* We will not be dealing with these, only our special ones. */
10460 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10462 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10463 frchainP
->frch_root
= NULL
;
10464 frchainP
->frch_last
= NULL
;
10465 frchainP
->frch_next
= NULL
;
10466 frchainP
->frch_subseg
= 0;
10467 frchainP
->fix_root
= NULL
;
10468 frchainP
->fix_tail
= NULL
;
10469 /* Do not init the objstack. */
10470 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10471 /* frchainP->frch_frag_now = fragP; */
10472 frchainP
->frch_frag_now
= NULL
;
10474 seginfo
->frchainP
= frchainP
;
10482 section_has_property (segT sec
, frag_predicate property_function
)
10484 segment_info_type
*seginfo
= seg_info (sec
);
10487 if (seginfo
&& seginfo
->frchainP
)
10489 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10491 if (property_function (fragP
)
10492 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10501 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10503 segment_info_type
*seginfo
= seg_info (sec
);
10506 if (seginfo
&& seginfo
->frchainP
)
10508 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10510 frag_flags prop_flags
;
10511 property_function (fragP
, &prop_flags
);
10512 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10520 /* Two types of block sections exist right now: literal and insns. */
10523 add_xt_block_frags (segT sec
,
10525 xtensa_block_info
**xt_block
,
10526 frag_predicate property_function
,
10527 frag_predicate end_property_function
)
10529 segment_info_type
*seg_info
;
10530 segment_info_type
*xt_seg_info
;
10531 bfd_vma seg_offset
;
10534 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10535 seg_info
= retrieve_segment_info (sec
);
10537 /* Build it if needed. */
10538 while (*xt_block
!= NULL
)
10539 xt_block
= &(*xt_block
)->next
;
10540 /* We are either at NULL at the beginning or at the end. */
10542 /* Walk through the frags. */
10545 if (seg_info
->frchainP
)
10547 for (fragP
= seg_info
->frchainP
->frch_root
;
10549 fragP
= fragP
->fr_next
)
10551 if (property_function (fragP
)
10552 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10554 if (*xt_block
!= NULL
)
10556 if ((*xt_block
)->offset
+ (*xt_block
)->size
10557 == fragP
->fr_address
)
10558 (*xt_block
)->size
+= fragP
->fr_fix
;
10560 xt_block
= &((*xt_block
)->next
);
10562 if (*xt_block
== NULL
)
10564 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10565 xmalloc (sizeof (xtensa_block_info
));
10566 new_block
->sec
= sec
;
10567 new_block
->offset
= fragP
->fr_address
;
10568 new_block
->size
= fragP
->fr_fix
;
10569 new_block
->next
= NULL
;
10570 xtensa_frag_flags_init (&new_block
->flags
);
10571 *xt_block
= new_block
;
10573 if (end_property_function
10574 && end_property_function (fragP
))
10576 xt_block
= &((*xt_block
)->next
);
10584 /* Break the encapsulation of add_xt_prop_frags here. */
10587 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10589 if (prop_flags
->is_literal
10590 || prop_flags
->is_insn
10591 || prop_flags
->is_data
10592 || prop_flags
->is_unreachable
)
10599 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10601 memset (prop_flags
, 0, sizeof (frag_flags
));
10606 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10608 xtensa_frag_flags_init (prop_flags
);
10609 if (fragP
->tc_frag_data
.is_literal
)
10610 prop_flags
->is_literal
= TRUE
;
10611 if (fragP
->tc_frag_data
.is_unreachable
)
10612 prop_flags
->is_unreachable
= TRUE
;
10613 else if (fragP
->tc_frag_data
.is_insn
)
10615 prop_flags
->is_insn
= TRUE
;
10616 if (fragP
->tc_frag_data
.is_loop_target
)
10617 prop_flags
->insn
.is_loop_target
= TRUE
;
10618 if (fragP
->tc_frag_data
.is_branch_target
)
10619 prop_flags
->insn
.is_branch_target
= TRUE
;
10620 if (fragP
->tc_frag_data
.is_specific_opcode
10621 || fragP
->tc_frag_data
.is_no_transform
)
10622 prop_flags
->insn
.is_no_transform
= TRUE
;
10623 if (fragP
->tc_frag_data
.is_no_density
)
10624 prop_flags
->insn
.is_no_density
= TRUE
;
10625 if (fragP
->tc_frag_data
.use_absolute_literals
)
10626 prop_flags
->insn
.is_abslit
= TRUE
;
10628 if (fragP
->tc_frag_data
.is_align
)
10630 prop_flags
->is_align
= TRUE
;
10631 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10632 if (xtensa_frag_flags_is_empty (prop_flags
))
10633 prop_flags
->is_data
= TRUE
;
10639 frag_flags_to_number (const frag_flags
*prop_flags
)
10642 if (prop_flags
->is_literal
)
10643 num
|= XTENSA_PROP_LITERAL
;
10644 if (prop_flags
->is_insn
)
10645 num
|= XTENSA_PROP_INSN
;
10646 if (prop_flags
->is_data
)
10647 num
|= XTENSA_PROP_DATA
;
10648 if (prop_flags
->is_unreachable
)
10649 num
|= XTENSA_PROP_UNREACHABLE
;
10650 if (prop_flags
->insn
.is_loop_target
)
10651 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10652 if (prop_flags
->insn
.is_branch_target
)
10654 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10655 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10658 if (prop_flags
->insn
.is_no_density
)
10659 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10660 if (prop_flags
->insn
.is_no_transform
)
10661 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10662 if (prop_flags
->insn
.is_no_reorder
)
10663 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10664 if (prop_flags
->insn
.is_abslit
)
10665 num
|= XTENSA_PROP_INSN_ABSLIT
;
10667 if (prop_flags
->is_align
)
10669 num
|= XTENSA_PROP_ALIGN
;
10670 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10678 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10679 const frag_flags
*prop_flags_2
)
10681 /* Cannot combine with an end marker. */
10683 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10685 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10687 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10690 if (prop_flags_1
->is_insn
)
10692 /* Properties of the beginning of the frag. */
10693 if (prop_flags_2
->insn
.is_loop_target
)
10695 if (prop_flags_2
->insn
.is_branch_target
)
10697 if (prop_flags_1
->insn
.is_no_density
!=
10698 prop_flags_2
->insn
.is_no_density
)
10700 if (prop_flags_1
->insn
.is_no_transform
!=
10701 prop_flags_2
->insn
.is_no_transform
)
10703 if (prop_flags_1
->insn
.is_no_reorder
!=
10704 prop_flags_2
->insn
.is_no_reorder
)
10706 if (prop_flags_1
->insn
.is_abslit
!=
10707 prop_flags_2
->insn
.is_abslit
)
10711 if (prop_flags_1
->is_align
)
10719 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10722 unsigned align_bits
;
10724 if (!xt_block
->flags
.is_align
)
10725 return xt_block
->size
;
10727 end_addr
= xt_block
->offset
+ xt_block
->size
;
10728 align_bits
= xt_block
->flags
.alignment
;
10729 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10730 return end_addr
- xt_block
->offset
;
10735 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10736 const xtensa_block_info
*xt_block_2
)
10738 if (xt_block
->sec
!= xt_block_2
->sec
)
10740 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10741 != xt_block_2
->offset
)
10744 if (xt_block_2
->size
== 0
10745 && (!xt_block_2
->flags
.is_unreachable
10746 || xt_block
->flags
.is_unreachable
))
10748 if (xt_block_2
->flags
.is_align
10749 && xt_block
->flags
.is_align
)
10751 /* Nothing needed. */
10752 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10757 if (xt_block_2
->flags
.is_align
)
10759 /* Push alignment to previous entry. */
10760 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10761 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10766 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10767 &xt_block_2
->flags
))
10770 xt_block
->size
+= xt_block_2
->size
;
10772 if (xt_block_2
->flags
.is_align
)
10774 xt_block
->flags
.is_align
= TRUE
;
10775 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10783 add_xt_prop_frags (segT sec
,
10785 xtensa_block_info
**xt_block
,
10786 frag_flags_fn property_function
)
10788 segment_info_type
*seg_info
;
10789 segment_info_type
*xt_seg_info
;
10790 bfd_vma seg_offset
;
10793 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10794 seg_info
= retrieve_segment_info (sec
);
10795 /* Build it if needed. */
10796 while (*xt_block
!= NULL
)
10798 xt_block
= &(*xt_block
)->next
;
10800 /* We are either at NULL at the beginning or at the end. */
10802 /* Walk through the frags. */
10805 if (seg_info
->frchainP
)
10807 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10808 fragP
= fragP
->fr_next
)
10810 xtensa_block_info tmp_block
;
10811 tmp_block
.sec
= sec
;
10812 tmp_block
.offset
= fragP
->fr_address
;
10813 tmp_block
.size
= fragP
->fr_fix
;
10814 tmp_block
.next
= NULL
;
10815 property_function (fragP
, &tmp_block
.flags
);
10817 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10818 /* && fragP->fr_fix != 0) */
10820 if ((*xt_block
) == NULL
10821 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10823 xtensa_block_info
*new_block
;
10824 if ((*xt_block
) != NULL
)
10825 xt_block
= &(*xt_block
)->next
;
10826 new_block
= (xtensa_block_info
*)
10827 xmalloc (sizeof (xtensa_block_info
));
10828 *new_block
= tmp_block
;
10829 *xt_block
= new_block
;
10837 /* op_placement_info_table */
10839 /* op_placement_info makes it easier to determine which
10840 ops can go in which slots. */
10843 init_op_placement_info_table (void)
10845 xtensa_isa isa
= xtensa_default_isa
;
10846 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10847 xtensa_opcode opcode
;
10850 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10852 op_placement_table
= (op_placement_info_table
)
10853 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10854 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10856 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10858 op_placement_info
*opi
= &op_placement_table
[opcode
];
10859 /* FIXME: Make tinsn allocation dynamic. */
10860 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10861 as_fatal (_("too many operands in instruction"));
10862 opi
->narrowest
= XTENSA_UNDEFINED
;
10863 opi
->narrowest_size
= 0x7F;
10864 opi
->narrowest_slot
= 0;
10866 opi
->num_formats
= 0;
10868 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10870 opi
->slots
[fmt
] = 0;
10871 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10873 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10875 int fmt_length
= xtensa_format_length (isa
, fmt
);
10877 set_bit (fmt
, opi
->formats
);
10878 set_bit (slot
, opi
->slots
[fmt
]);
10879 if (fmt_length
< opi
->narrowest_size
10880 || (fmt_length
== opi
->narrowest_size
10881 && (xtensa_format_num_slots (isa
, fmt
)
10882 < xtensa_format_num_slots (isa
,
10885 opi
->narrowest
= fmt
;
10886 opi
->narrowest_size
= fmt_length
;
10887 opi
->narrowest_slot
= slot
;
10892 opi
->num_formats
++;
10895 xtensa_insnbuf_free (isa
, ibuf
);
10900 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10902 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10906 /* If the opcode is available in a single slot format, return its size. */
10909 xg_get_single_size (xtensa_opcode opcode
)
10911 return op_placement_table
[opcode
].narrowest_size
;
10915 static xtensa_format
10916 xg_get_single_format (xtensa_opcode opcode
)
10918 return op_placement_table
[opcode
].narrowest
;
10923 xg_get_single_slot (xtensa_opcode opcode
)
10925 return op_placement_table
[opcode
].narrowest_slot
;
10929 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10932 istack_init (IStack
*stack
)
10934 memset (stack
, 0, sizeof (IStack
));
10940 istack_empty (IStack
*stack
)
10942 return (stack
->ninsn
== 0);
10947 istack_full (IStack
*stack
)
10949 return (stack
->ninsn
== MAX_ISTACK
);
10953 /* Return a pointer to the top IStack entry.
10954 It is an error to call this if istack_empty () is TRUE. */
10957 istack_top (IStack
*stack
)
10959 int rec
= stack
->ninsn
- 1;
10960 assert (!istack_empty (stack
));
10961 return &stack
->insn
[rec
];
10965 /* Add a new TInsn to an IStack.
10966 It is an error to call this if istack_full () is TRUE. */
10969 istack_push (IStack
*stack
, TInsn
*insn
)
10971 int rec
= stack
->ninsn
;
10972 assert (!istack_full (stack
));
10973 stack
->insn
[rec
] = *insn
;
10978 /* Clear space for the next TInsn on the IStack and return a pointer
10979 to it. It is an error to call this if istack_full () is TRUE. */
10982 istack_push_space (IStack
*stack
)
10984 int rec
= stack
->ninsn
;
10986 assert (!istack_full (stack
));
10987 insn
= &stack
->insn
[rec
];
10994 /* Remove the last pushed instruction. It is an error to call this if
10995 istack_empty () returns TRUE. */
10998 istack_pop (IStack
*stack
)
11000 int rec
= stack
->ninsn
- 1;
11001 assert (!istack_empty (stack
));
11003 tinsn_init (&stack
->insn
[rec
]);
11007 /* TInsn functions. */
11010 tinsn_init (TInsn
*dst
)
11012 memset (dst
, 0, sizeof (TInsn
));
11016 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11019 tinsn_has_symbolic_operands (const TInsn
*insn
)
11022 int n
= insn
->ntok
;
11024 assert (insn
->insn_type
== ITYPE_INSN
);
11026 for (i
= 0; i
< n
; ++i
)
11028 switch (insn
->tok
[i
].X_op
)
11042 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11044 xtensa_isa isa
= xtensa_default_isa
;
11046 int n
= insn
->ntok
;
11048 assert (insn
->insn_type
== ITYPE_INSN
);
11050 for (i
= 0; i
< n
; ++i
)
11052 switch (insn
->tok
[i
].X_op
)
11060 /* Errors for these types are caught later. */
11065 /* Symbolic immediates are only allowed on the last immediate
11066 operand. At this time, CONST16 is the only opcode where we
11067 support non-PC-relative relocations. */
11068 if (i
!= get_relaxable_immed (insn
->opcode
)
11069 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11070 && insn
->opcode
!= xtensa_const16_opcode
))
11072 as_bad (_("invalid symbolic operand"));
11081 /* For assembly code with complex expressions (e.g. subtraction),
11082 we have to build them in the literal pool so that
11083 their results are calculated correctly after relaxation.
11084 The relaxation only handles expressions that
11085 boil down to SYMBOL + OFFSET. */
11088 tinsn_has_complex_operands (const TInsn
*insn
)
11091 int n
= insn
->ntok
;
11092 assert (insn
->insn_type
== ITYPE_INSN
);
11093 for (i
= 0; i
< n
; ++i
)
11095 switch (insn
->tok
[i
].X_op
)
11111 /* Encode a TInsn opcode and its constant operands into slotbuf.
11112 Return TRUE if there is a symbol in the immediate field. This
11113 function assumes that:
11114 1) The number of operands are correct.
11115 2) The insn_type is ITYPE_INSN.
11116 3) The opcode can be encoded in the specified format and slot.
11117 4) Operands are either O_constant or O_symbol, and all constants fit. */
11120 tinsn_to_slotbuf (xtensa_format fmt
,
11123 xtensa_insnbuf slotbuf
)
11125 xtensa_isa isa
= xtensa_default_isa
;
11126 xtensa_opcode opcode
= tinsn
->opcode
;
11127 bfd_boolean has_fixup
= FALSE
;
11128 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11131 assert (tinsn
->insn_type
== ITYPE_INSN
);
11132 if (noperands
!= tinsn
->ntok
)
11133 as_fatal (_("operand number mismatch"));
11135 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11137 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11138 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11142 for (i
= 0; i
< noperands
; i
++)
11144 expressionS
*expr
= &tinsn
->tok
[i
];
11150 switch (expr
->X_op
)
11153 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11155 /* The register number has already been checked in
11156 expression_maybe_register, so we don't need to check here. */
11157 opnd_value
= expr
->X_add_number
;
11158 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11159 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11162 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11166 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11168 as_where (&file_name
, &line
);
11169 /* It is a constant and we called this function
11170 then we have to try to fit it. */
11171 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11172 expr
->X_add_number
, file_name
, line
);
11185 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11186 into a multi-slot instruction, fill the other slots with NOPs.
11187 Return TRUE if there is a symbol in the immediate field. See also the
11188 assumptions listed for tinsn_to_slotbuf. */
11191 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11193 static xtensa_insnbuf slotbuf
= 0;
11194 static vliw_insn vinsn
;
11195 xtensa_isa isa
= xtensa_default_isa
;
11196 bfd_boolean has_fixup
= FALSE
;
11201 slotbuf
= xtensa_insnbuf_alloc (isa
);
11202 xg_init_vinsn (&vinsn
);
11205 xg_clear_vinsn (&vinsn
);
11207 bundle_tinsn (tinsn
, &vinsn
);
11209 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11211 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11213 /* Only one slot may have a fix-up because the rest contains NOPs. */
11215 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11216 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11223 /* Check the instruction arguments. Return TRUE on failure. */
11226 tinsn_check_arguments (const TInsn
*insn
)
11228 xtensa_isa isa
= xtensa_default_isa
;
11229 xtensa_opcode opcode
= insn
->opcode
;
11231 if (opcode
== XTENSA_UNDEFINED
)
11233 as_bad (_("invalid opcode"));
11237 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11239 as_bad (_("too few operands"));
11243 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11245 as_bad (_("too many operands"));
11252 /* Load an instruction from its encoded form. */
11255 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11259 xg_init_vinsn (&vinsn
);
11260 vinsn_from_chars (&vinsn
, f
);
11262 *tinsn
= vinsn
.slots
[slot
];
11263 xg_free_vinsn (&vinsn
);
11268 tinsn_from_insnbuf (TInsn
*tinsn
,
11269 xtensa_insnbuf slotbuf
,
11274 xtensa_isa isa
= xtensa_default_isa
;
11276 /* Find the immed. */
11277 tinsn_init (tinsn
);
11278 tinsn
->insn_type
= ITYPE_INSN
;
11279 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11280 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11281 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11282 for (i
= 0; i
< tinsn
->ntok
; i
++)
11284 set_expr_const (&tinsn
->tok
[i
],
11285 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11286 tinsn
->opcode
, i
));
11291 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11294 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11296 xtensa_opcode opcode
= tinsn
->opcode
;
11299 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11301 opnum
= get_relaxable_immed (opcode
);
11302 assert (opnum
>= 0);
11303 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11304 fragP
->tc_frag_data
.slot_symbols
[slot
],
11305 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11311 get_num_stack_text_bytes (IStack
*istack
)
11314 int text_bytes
= 0;
11316 for (i
= 0; i
< istack
->ninsn
; i
++)
11318 TInsn
*tinsn
= &istack
->insn
[i
];
11319 if (tinsn
->insn_type
== ITYPE_INSN
)
11320 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11327 get_num_stack_literal_bytes (IStack
*istack
)
11332 for (i
= 0; i
< istack
->ninsn
; i
++)
11334 TInsn
*tinsn
= &istack
->insn
[i
];
11335 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11342 /* vliw_insn functions. */
11345 xg_init_vinsn (vliw_insn
*v
)
11348 xtensa_isa isa
= xtensa_default_isa
;
11350 xg_clear_vinsn (v
);
11352 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11353 if (v
->insnbuf
== NULL
)
11354 as_fatal (_("out of memory"));
11356 for (i
= 0; i
< MAX_SLOTS
; i
++)
11358 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11359 if (v
->slotbuf
[i
] == NULL
)
11360 as_fatal (_("out of memory"));
11366 xg_clear_vinsn (vliw_insn
*v
)
11370 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11372 v
->format
= XTENSA_UNDEFINED
;
11374 v
->inside_bundle
= FALSE
;
11376 if (xt_saved_debug_type
!= DEBUG_NONE
)
11377 debug_type
= xt_saved_debug_type
;
11379 for (i
= 0; i
< MAX_SLOTS
; i
++)
11380 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11385 vinsn_has_specific_opcodes (vliw_insn
*v
)
11389 for (i
= 0; i
< v
->num_slots
; i
++)
11391 if (v
->slots
[i
].is_specific_opcode
)
11399 xg_free_vinsn (vliw_insn
*v
)
11402 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11403 for (i
= 0; i
< MAX_SLOTS
; i
++)
11404 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11408 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11409 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11412 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11415 bfd_boolean record_fixup
)
11417 xtensa_isa isa
= xtensa_default_isa
;
11418 xtensa_format fmt
= vinsn
->format
;
11419 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11421 bfd_boolean has_fixup
= FALSE
;
11423 xtensa_format_encode (isa
, fmt
, insnbuf
);
11425 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11427 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11428 bfd_boolean tinsn_has_fixup
=
11429 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11430 vinsn
->slotbuf
[slot
]);
11432 xtensa_format_set_slot (isa
, fmt
, slot
,
11433 insnbuf
, vinsn
->slotbuf
[slot
]);
11434 if (tinsn_has_fixup
)
11437 xtensa_opcode opcode
= tinsn
->opcode
;
11438 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11441 for (i
= 0; i
< noperands
; i
++)
11443 expressionS
* expr
= &tinsn
->tok
[i
];
11444 switch (expr
->X_op
)
11449 if (get_relaxable_immed (opcode
) == i
)
11451 /* Add a fix record for the instruction, except if this
11452 function is being called prior to relaxation, i.e.,
11453 if record_fixup is false, and the instruction might
11454 be relaxed later. */
11456 || tinsn
->is_specific_opcode
11457 || !xg_is_relaxable_insn (tinsn
, 0))
11459 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11460 frag_offset
- fragP
->fr_literal
);
11464 if (expr
->X_op
!= O_symbol
)
11465 as_bad (_("invalid operand"));
11466 tinsn
->symbol
= expr
->X_add_symbol
;
11467 tinsn
->offset
= expr
->X_add_number
;
11471 as_bad (_("symbolic operand not allowed"));
11479 as_bad (_("expression too complex"));
11491 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11493 static xtensa_insnbuf insnbuf
= NULL
;
11494 static xtensa_insnbuf slotbuf
= NULL
;
11497 xtensa_isa isa
= xtensa_default_isa
;
11501 insnbuf
= xtensa_insnbuf_alloc (isa
);
11502 slotbuf
= xtensa_insnbuf_alloc (isa
);
11505 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11506 fmt
= xtensa_format_decode (isa
, insnbuf
);
11507 if (fmt
== XTENSA_UNDEFINED
)
11508 as_fatal (_("cannot decode instruction format"));
11509 vinsn
->format
= fmt
;
11510 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11512 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11514 TInsn
*tinsn
= &vinsn
->slots
[i
];
11515 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11516 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11521 /* Expression utilities. */
11523 /* Return TRUE if the expression is an integer constant. */
11526 expr_is_const (const expressionS
*s
)
11528 return (s
->X_op
== O_constant
);
11532 /* Get the expression constant.
11533 Calling this is illegal if expr_is_const () returns TRUE. */
11536 get_expr_const (const expressionS
*s
)
11538 assert (expr_is_const (s
));
11539 return s
->X_add_number
;
11543 /* Set the expression to a constant value. */
11546 set_expr_const (expressionS
*s
, offsetT val
)
11548 s
->X_op
= O_constant
;
11549 s
->X_add_number
= val
;
11550 s
->X_add_symbol
= NULL
;
11551 s
->X_op_symbol
= NULL
;
11556 expr_is_register (const expressionS
*s
)
11558 return (s
->X_op
== O_register
);
11562 /* Get the expression constant.
11563 Calling this is illegal if expr_is_const () returns TRUE. */
11566 get_expr_register (const expressionS
*s
)
11568 assert (expr_is_register (s
));
11569 return s
->X_add_number
;
11573 /* Set the expression to a symbol + constant offset. */
11576 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11578 s
->X_op
= O_symbol
;
11579 s
->X_add_symbol
= sym
;
11580 s
->X_op_symbol
= NULL
; /* unused */
11581 s
->X_add_number
= offset
;
11585 /* Return TRUE if the two expressions are equal. */
11588 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11590 if (s1
->X_op
!= s2
->X_op
)
11592 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11594 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11596 if (s1
->X_add_number
!= s2
->X_add_number
)
11603 copy_expr (expressionS
*dst
, const expressionS
*src
)
11605 memcpy (dst
, src
, sizeof (expressionS
));
11609 /* Support for the "--rename-section" option. */
11611 struct rename_section_struct
11615 struct rename_section_struct
*next
;
11618 static struct rename_section_struct
*section_rename
;
11621 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11622 entries to the section_rename list. Note: Specifying multiple
11623 renamings separated by colons is not documented and is retained only
11624 for backward compatibility. */
11627 build_section_rename (const char *arg
)
11629 struct rename_section_struct
*r
;
11630 char *this_arg
= NULL
;
11631 char *next_arg
= NULL
;
11633 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11635 char *old_name
, *new_name
;
11639 next_arg
= strchr (this_arg
, ':');
11647 old_name
= this_arg
;
11648 new_name
= strchr (this_arg
, '=');
11650 if (*old_name
== '\0')
11652 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11655 if (!new_name
|| new_name
[1] == '\0')
11657 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11664 /* Check for invalid section renaming. */
11665 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11667 if (strcmp (r
->old_name
, old_name
) == 0)
11668 as_bad (_("section %s renamed multiple times"), old_name
);
11669 if (strcmp (r
->new_name
, new_name
) == 0)
11670 as_bad (_("multiple sections remapped to output section %s"),
11675 r
= (struct rename_section_struct
*)
11676 xmalloc (sizeof (struct rename_section_struct
));
11677 r
->old_name
= xstrdup (old_name
);
11678 r
->new_name
= xstrdup (new_name
);
11679 r
->next
= section_rename
;
11680 section_rename
= r
;
11686 xtensa_section_rename (char *name
)
11688 struct rename_section_struct
*r
= section_rename
;
11690 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11692 if (strcmp (r
->old_name
, name
) == 0)
11693 return r
->new_name
;