1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
28 #include "xtensa-relax.h"
29 #include "dwarf2dbg.h"
30 #include "xtensa-istack.h"
31 #include "struc-symbol.h"
32 #include "xtensa-config.h"
34 /* Provide default values for new configuration settings. */
40 #define uint32 unsigned int
43 #define int32 signed int
48 Naming conventions (used somewhat inconsistently):
49 The xtensa_ functions are exported
50 The xg_ functions are internal
52 We also have a couple of different extensibility mechanisms.
53 1) The idiom replacement:
54 This is used when a line is first parsed to
55 replace an instruction pattern with another instruction
56 It is currently limited to replacements of instructions
57 with constant operands.
58 2) The xtensa-relax.c mechanism that has stronger instruction
59 replacement patterns. When an instruction's immediate field
60 does not fit the next instruction sequence is attempted.
61 In addition, "narrow" opcodes are supported this way. */
64 /* Define characters with special meanings to GAS. */
65 const char comment_chars
[] = "#";
66 const char line_comment_chars
[] = "#";
67 const char line_separator_chars
[] = ";";
68 const char EXP_CHARS
[] = "eE";
69 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
72 /* Flags to indicate whether the hardware supports the density and
73 absolute literals options. */
75 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
76 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
78 static vliw_insn cur_vinsn
;
80 unsigned xtensa_num_pipe_stages
;
81 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
83 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
85 /* Some functions are only valid in the front end. This variable
86 allows us to assert that we haven't crossed over into the
88 static bfd_boolean past_xtensa_end
= FALSE
;
90 /* Flags for properties of the last instruction in a segment. */
91 #define FLAG_IS_A0_WRITER 0x1
92 #define FLAG_IS_BAD_LOOPEND 0x2
95 /* We define a special segment names ".literal" to place literals
96 into. The .fini and .init sections are special because they
97 contain code that is moved together by the linker. We give them
98 their own special .fini.literal and .init.literal sections. */
100 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
101 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
102 #define INIT_SECTION_NAME xtensa_section_rename (".init")
103 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. If lit_prefix is set, it is
108 used to determine the literal section names; otherwise, the literal
109 sections are determined based on the current text section. The
110 lit_seg and lit4_seg fields cache these literal sections, with the
111 current_text_seg field used a tag to indicate whether the cached
114 typedef struct lit_state_struct
117 segT current_text_seg
;
122 static lit_state default_lit_sections
;
125 /* We keep a list of literal segments. The seg_list type is the node
126 for this list. The literal_head pointer is the head of the list,
127 with the literal_head_h dummy node at the start. */
129 typedef struct seg_list_struct
131 struct seg_list_struct
*next
;
135 static seg_list literal_head_h
;
136 static seg_list
*literal_head
= &literal_head_h
;
139 /* Lists of symbols. We keep a list of symbols that label the current
140 instruction, so that we can adjust the symbols when inserting alignment
141 for various instructions. We also keep a list of all the symbols on
142 literals, so that we can fix up those symbols when the literals are
143 later moved into the text sections. */
145 typedef struct sym_list_struct
147 struct sym_list_struct
*next
;
151 static sym_list
*insn_labels
= NULL
;
152 static sym_list
*free_insn_labels
= NULL
;
153 static sym_list
*saved_insn_labels
= NULL
;
155 static sym_list
*literal_syms
;
158 /* Flags to determine whether to prefer const16 or l32r
159 if both options are available. */
160 int prefer_const16
= 0;
163 /* Global flag to indicate when we are emitting literals. */
164 int generating_literals
= 0;
166 /* The following PROPERTY table definitions are copied from
167 <elf/xtensa.h> and must be kept in sync with the code there. */
169 /* Flags in the property tables to specify whether blocks of memory
170 are literals, instructions, data, or unreachable. For
171 instructions, blocks that begin loop targets and branch targets are
172 designated. Blocks that do not allow density, instruction
173 reordering or transformation are also specified. Finally, for
174 branch targets, branch target alignment priority is included.
175 Alignment of the next block is specified in the current block
176 and the size of the current block does not include any fill required
177 to align to the next block. */
179 #define XTENSA_PROP_LITERAL 0x00000001
180 #define XTENSA_PROP_INSN 0x00000002
181 #define XTENSA_PROP_DATA 0x00000004
182 #define XTENSA_PROP_UNREACHABLE 0x00000008
183 /* Instruction only properties at beginning of code. */
184 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
185 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
186 /* Instruction only properties about code. */
187 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
188 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
189 /* Historically, NO_TRANSFORM was a property of instructions,
190 but it should apply to literals under certain circumstances. */
191 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
193 /* Branch target alignment information. This transmits information
194 to the linker optimization about the priority of aligning a
195 particular block for branch target alignment: None, low priority,
196 high priority, or required. These only need to be checked in
197 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
200 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
201 case XTENSA_PROP_BT_ALIGN_NONE:
202 case XTENSA_PROP_BT_ALIGN_LOW:
203 case XTENSA_PROP_BT_ALIGN_HIGH:
204 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208 /* No branch target alignment. */
209 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
210 /* Low priority branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
212 /* High priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
214 /* Required branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
218 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
219 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
220 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
221 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
224 /* Alignment is specified in the block BEFORE the one that needs
225 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
226 get the required alignment specified as a power of 2. Use
227 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
228 alignment. Be careful of side effects since the SET will evaluate
229 flags twice. Also, note that the SIZE of a block in the property
230 table does not include the alignment size, so the alignment fill
231 must be calculated to determine if two blocks are contiguous.
232 TEXT_ALIGN is not currently implemented but is a placeholder for a
233 possible future implementation. */
235 #define XTENSA_PROP_ALIGN 0x00000800
237 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
239 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
240 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
241 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
242 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
243 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
245 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
248 /* Structure for saving instruction and alignment per-fragment data
249 that will be written to the object file. This structure is
250 equivalent to the actual data that will be written out to the file
251 but is easier to use. We provide a conversion to file flags
252 in frag_flags_to_number. */
254 typedef struct frag_flags_struct frag_flags
;
256 struct frag_flags_struct
258 /* is_literal should only be used after xtensa_move_literals.
259 If you need to check if you are generating a literal fragment,
260 then use the generating_literals global. */
262 unsigned is_literal
: 1;
263 unsigned is_insn
: 1;
264 unsigned is_data
: 1;
265 unsigned is_unreachable
: 1;
267 /* is_specific_opcode implies no_transform. */
268 unsigned is_no_transform
: 1;
272 unsigned is_loop_target
: 1;
273 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
274 unsigned bt_align_priority
: 2;
276 unsigned is_no_density
: 1;
277 /* no_longcalls flag does not need to be placed in the object file. */
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 xtensa_format narrowest
;
334 /* formats is a bitfield with the Nth bit set
335 if the opcode fits in the Nth xtensa_format. */
338 /* slots[N]'s Mth bit is set if the op fits in the
339 Mth slot of the Nth xtensa_format. */
340 bitfield slots
[MAX_FORMATS
];
342 /* A count of the number of slots in a given format
343 an op can fit (i.e., the bitcount of the slot field above). */
344 char slots_in_format
[MAX_FORMATS
];
346 } op_placement_info
, *op_placement_info_table
;
348 op_placement_info_table op_placement_table
;
351 /* Extra expression types. */
353 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
354 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
355 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
356 #define O_pcrel O_md4 /* value is a PC-relative offset */
357 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
358 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
359 #define O_tlscall O_md7 /* TLS_CALL relocation */
360 #define O_tpoff O_md8 /* TPOFF relocation */
361 #define O_dtpoff O_md9 /* DTPOFF relocation */
363 struct suffix_reloc_map
367 bfd_reloc_code_real_type reloc
;
368 unsigned char operator;
371 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
373 static struct suffix_reloc_map suffix_relocs
[] =
375 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
376 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
377 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
378 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
379 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
380 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
381 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
382 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
383 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
384 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
398 directive_literal_prefix
,
400 directive_absolute_literals
,
401 directive_last_directive
407 bfd_boolean can_be_negated
;
410 const directive_infoS directive_info
[] =
413 { "literal", FALSE
},
415 { "transform", TRUE
},
416 { "freeregs", FALSE
},
417 { "longcalls", TRUE
},
418 { "literal_prefix", FALSE
},
419 { "schedule", TRUE
},
420 { "absolute-literals", TRUE
}
423 bfd_boolean directive_state
[] =
427 #if !XCHAL_HAVE_DENSITY
432 TRUE
, /* transform */
433 FALSE
, /* freeregs */
434 FALSE
, /* longcalls */
435 FALSE
, /* literal_prefix */
436 FALSE
, /* schedule */
437 #if XSHAL_USE_ABSOLUTE_LITERALS
438 TRUE
/* absolute_literals */
440 FALSE
/* absolute_literals */
445 /* Directive functions. */
447 static void xtensa_begin_directive (int);
448 static void xtensa_end_directive (int);
449 static void xtensa_literal_prefix (void);
450 static void xtensa_literal_position (int);
451 static void xtensa_literal_pseudo (int);
452 static void xtensa_frequency_pseudo (int);
453 static void xtensa_elf_cons (int);
454 static void xtensa_leb128 (int);
456 /* Parsing and Idiom Translation. */
458 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
460 /* Various Other Internal Functions. */
462 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
463 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
464 static void xtensa_mark_literal_pool_location (void);
465 static addressT
get_expanded_loop_offset (xtensa_opcode
);
466 static fragS
*get_literal_pool_location (segT
);
467 static void set_literal_pool_location (segT
, fragS
*);
468 static void xtensa_set_frag_assembly_state (fragS
*);
469 static void finish_vinsn (vliw_insn
*);
470 static bfd_boolean
emit_single_op (TInsn
*);
471 static int total_frag_text_expansion (fragS
*);
473 /* Alignment Functions. */
475 static int get_text_align_power (unsigned);
476 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
477 static int branch_align_power (segT
);
479 /* Helpers for xtensa_relax_frag(). */
481 static long relax_frag_add_nop (fragS
*);
483 /* Accessors for additional per-subsegment information. */
485 static unsigned get_last_insn_flags (segT
, subsegT
);
486 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
487 static float get_subseg_total_freq (segT
, subsegT
);
488 static float get_subseg_target_freq (segT
, subsegT
);
489 static void set_subseg_freq (segT
, subsegT
, float, float);
491 /* Segment list functions. */
493 static void xtensa_move_literals (void);
494 static void xtensa_reorder_segments (void);
495 static void xtensa_switch_to_literal_fragment (emit_state
*);
496 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
497 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
498 static void xtensa_restore_emit_state (emit_state
*);
499 static segT
cache_literal_section (bfd_boolean
);
501 /* Import from elf32-xtensa.c in BFD library. */
503 extern asection
*xtensa_make_property_section (asection
*, const char *);
505 /* op_placement_info functions. */
507 static void init_op_placement_info_table (void);
508 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
509 static int xg_get_single_size (xtensa_opcode
);
510 static xtensa_format
xg_get_single_format (xtensa_opcode
);
511 static int xg_get_single_slot (xtensa_opcode
);
513 /* TInsn and IStack functions. */
515 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
516 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
517 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
518 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
519 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
520 static void tinsn_from_chars (TInsn
*, char *, int);
521 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
522 static int get_num_stack_text_bytes (IStack
*);
523 static int get_num_stack_literal_bytes (IStack
*);
525 /* vliw_insn functions. */
527 static void xg_init_vinsn (vliw_insn
*);
528 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
529 static void xg_clear_vinsn (vliw_insn
*);
530 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
531 static void xg_free_vinsn (vliw_insn
*);
532 static bfd_boolean vinsn_to_insnbuf
533 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
534 static void vinsn_from_chars (vliw_insn
*, char *);
536 /* Expression Utilities. */
538 bfd_boolean
expr_is_const (const expressionS
*);
539 offsetT
get_expr_const (const expressionS
*);
540 void set_expr_const (expressionS
*, offsetT
);
541 bfd_boolean
expr_is_register (const expressionS
*);
542 offsetT
get_expr_register (const expressionS
*);
543 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
544 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
545 static void copy_expr (expressionS
*, const expressionS
*);
547 /* Section renaming. */
549 static void build_section_rename (const char *);
552 /* ISA imported from bfd. */
553 extern xtensa_isa xtensa_default_isa
;
555 extern int target_big_endian
;
557 static xtensa_opcode xtensa_addi_opcode
;
558 static xtensa_opcode xtensa_addmi_opcode
;
559 static xtensa_opcode xtensa_call0_opcode
;
560 static xtensa_opcode xtensa_call4_opcode
;
561 static xtensa_opcode xtensa_call8_opcode
;
562 static xtensa_opcode xtensa_call12_opcode
;
563 static xtensa_opcode xtensa_callx0_opcode
;
564 static xtensa_opcode xtensa_callx4_opcode
;
565 static xtensa_opcode xtensa_callx8_opcode
;
566 static xtensa_opcode xtensa_callx12_opcode
;
567 static xtensa_opcode xtensa_const16_opcode
;
568 static xtensa_opcode xtensa_entry_opcode
;
569 static xtensa_opcode xtensa_extui_opcode
;
570 static xtensa_opcode xtensa_movi_opcode
;
571 static xtensa_opcode xtensa_movi_n_opcode
;
572 static xtensa_opcode xtensa_isync_opcode
;
573 static xtensa_opcode xtensa_j_opcode
;
574 static xtensa_opcode xtensa_jx_opcode
;
575 static xtensa_opcode xtensa_l32r_opcode
;
576 static xtensa_opcode xtensa_loop_opcode
;
577 static xtensa_opcode xtensa_loopnez_opcode
;
578 static xtensa_opcode xtensa_loopgtz_opcode
;
579 static xtensa_opcode xtensa_nop_opcode
;
580 static xtensa_opcode xtensa_nop_n_opcode
;
581 static xtensa_opcode xtensa_or_opcode
;
582 static xtensa_opcode xtensa_ret_opcode
;
583 static xtensa_opcode xtensa_ret_n_opcode
;
584 static xtensa_opcode xtensa_retw_opcode
;
585 static xtensa_opcode xtensa_retw_n_opcode
;
586 static xtensa_opcode xtensa_rsr_lcount_opcode
;
587 static xtensa_opcode xtensa_waiti_opcode
;
588 static int config_max_slots
= 0;
591 /* Command-line Options. */
593 bfd_boolean use_literal_section
= TRUE
;
594 enum flix_level produce_flix
= FLIX_ALL
;
595 static bfd_boolean align_targets
= TRUE
;
596 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
597 static bfd_boolean has_a0_b_retw
= FALSE
;
598 static bfd_boolean workaround_a0_b_retw
= FALSE
;
599 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
600 static bfd_boolean workaround_short_loop
= FALSE
;
601 static bfd_boolean maybe_has_short_loop
= FALSE
;
602 static bfd_boolean workaround_close_loop_end
= FALSE
;
603 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
604 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
606 /* When workaround_short_loops is TRUE, all loops with early exits must
607 have at least 3 instructions. workaround_all_short_loops is a modifier
608 to the workaround_short_loop flag. In addition to the
609 workaround_short_loop actions, all straightline loopgtz and loopnez
610 must have at least 3 instructions. */
612 static bfd_boolean workaround_all_short_loops
= FALSE
;
616 xtensa_setup_hw_workarounds (int earliest
, int latest
)
618 if (earliest
> latest
)
619 as_fatal (_("illegal range of target hardware versions"));
621 /* Enable all workarounds for pre-T1050.0 hardware. */
622 if (earliest
< 105000 || latest
< 105000)
624 workaround_a0_b_retw
|= TRUE
;
625 workaround_b_j_loop_end
|= TRUE
;
626 workaround_short_loop
|= TRUE
;
627 workaround_close_loop_end
|= TRUE
;
628 workaround_all_short_loops
|= TRUE
;
629 enforce_three_byte_loop_align
= TRUE
;
636 option_density
= OPTION_MD_BASE
,
640 option_no_generate_flix
,
647 option_no_link_relax
,
655 option_text_section_literals
,
656 option_no_text_section_literals
,
658 option_absolute_literals
,
659 option_no_absolute_literals
,
661 option_align_targets
,
662 option_no_align_targets
,
664 option_warn_unaligned_targets
,
669 option_workaround_a0_b_retw
,
670 option_no_workaround_a0_b_retw
,
672 option_workaround_b_j_loop_end
,
673 option_no_workaround_b_j_loop_end
,
675 option_workaround_short_loop
,
676 option_no_workaround_short_loop
,
678 option_workaround_all_short_loops
,
679 option_no_workaround_all_short_loops
,
681 option_workaround_close_loop_end
,
682 option_no_workaround_close_loop_end
,
684 option_no_workarounds
,
686 option_rename_section_name
,
689 option_prefer_const16
,
691 option_target_hardware
694 const char *md_shortopts
= "";
696 struct option md_longopts
[] =
698 { "density", no_argument
, NULL
, option_density
},
699 { "no-density", no_argument
, NULL
, option_no_density
},
701 { "flix", no_argument
, NULL
, option_flix
},
702 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
703 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
705 /* Both "relax" and "generics" are deprecated and treated as equivalent
706 to the "transform" option. */
707 { "relax", no_argument
, NULL
, option_relax
},
708 { "no-relax", no_argument
, NULL
, option_no_relax
},
709 { "generics", no_argument
, NULL
, option_generics
},
710 { "no-generics", no_argument
, NULL
, option_no_generics
},
712 { "transform", no_argument
, NULL
, option_transform
},
713 { "no-transform", no_argument
, NULL
, option_no_transform
},
714 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
715 { "no-text-section-literals", no_argument
, NULL
,
716 option_no_text_section_literals
},
717 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
718 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
719 /* This option was changed from -align-target to -target-align
720 because it conflicted with the "-al" option. */
721 { "target-align", no_argument
, NULL
, option_align_targets
},
722 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
723 { "warn-unaligned-targets", no_argument
, NULL
,
724 option_warn_unaligned_targets
},
725 { "longcalls", no_argument
, NULL
, option_longcalls
},
726 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
728 { "no-workaround-a0-b-retw", no_argument
, NULL
,
729 option_no_workaround_a0_b_retw
},
730 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
732 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
733 option_no_workaround_b_j_loop_end
},
734 { "workaround-b-j-loop-end", no_argument
, NULL
,
735 option_workaround_b_j_loop_end
},
737 { "no-workaround-short-loops", no_argument
, NULL
,
738 option_no_workaround_short_loop
},
739 { "workaround-short-loops", no_argument
, NULL
,
740 option_workaround_short_loop
},
742 { "no-workaround-all-short-loops", no_argument
, NULL
,
743 option_no_workaround_all_short_loops
},
744 { "workaround-all-short-loop", no_argument
, NULL
,
745 option_workaround_all_short_loops
},
747 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
748 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
750 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
752 { "no-workaround-close-loop-end", no_argument
, NULL
,
753 option_no_workaround_close_loop_end
},
754 { "workaround-close-loop-end", no_argument
, NULL
,
755 option_workaround_close_loop_end
},
757 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
759 { "link-relax", no_argument
, NULL
, option_link_relax
},
760 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
762 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
764 { NULL
, no_argument
, NULL
, 0 }
767 size_t md_longopts_size
= sizeof md_longopts
;
771 md_parse_option (int c
, char *arg
)
776 as_warn (_("--density option is ignored"));
778 case option_no_density
:
779 as_warn (_("--no-density option is ignored"));
781 case option_link_relax
:
784 case option_no_link_relax
:
788 produce_flix
= FLIX_ALL
;
790 case option_no_generate_flix
:
791 produce_flix
= FLIX_NO_GENERATE
;
794 produce_flix
= FLIX_NONE
;
796 case option_generics
:
797 as_warn (_("--generics is deprecated; use --transform instead"));
798 return md_parse_option (option_transform
, arg
);
799 case option_no_generics
:
800 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
801 return md_parse_option (option_no_transform
, arg
);
803 as_warn (_("--relax is deprecated; use --transform instead"));
804 return md_parse_option (option_transform
, arg
);
805 case option_no_relax
:
806 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
807 return md_parse_option (option_no_transform
, arg
);
808 case option_longcalls
:
809 directive_state
[directive_longcalls
] = TRUE
;
811 case option_no_longcalls
:
812 directive_state
[directive_longcalls
] = FALSE
;
814 case option_text_section_literals
:
815 use_literal_section
= FALSE
;
817 case option_no_text_section_literals
:
818 use_literal_section
= TRUE
;
820 case option_absolute_literals
:
821 if (!absolute_literals_supported
)
823 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
826 directive_state
[directive_absolute_literals
] = TRUE
;
828 case option_no_absolute_literals
:
829 directive_state
[directive_absolute_literals
] = FALSE
;
832 case option_workaround_a0_b_retw
:
833 workaround_a0_b_retw
= TRUE
;
835 case option_no_workaround_a0_b_retw
:
836 workaround_a0_b_retw
= FALSE
;
838 case option_workaround_b_j_loop_end
:
839 workaround_b_j_loop_end
= TRUE
;
841 case option_no_workaround_b_j_loop_end
:
842 workaround_b_j_loop_end
= FALSE
;
845 case option_workaround_short_loop
:
846 workaround_short_loop
= TRUE
;
848 case option_no_workaround_short_loop
:
849 workaround_short_loop
= FALSE
;
852 case option_workaround_all_short_loops
:
853 workaround_all_short_loops
= TRUE
;
855 case option_no_workaround_all_short_loops
:
856 workaround_all_short_loops
= FALSE
;
859 case option_workaround_close_loop_end
:
860 workaround_close_loop_end
= TRUE
;
862 case option_no_workaround_close_loop_end
:
863 workaround_close_loop_end
= FALSE
;
866 case option_no_workarounds
:
867 workaround_a0_b_retw
= FALSE
;
868 workaround_b_j_loop_end
= FALSE
;
869 workaround_short_loop
= FALSE
;
870 workaround_all_short_loops
= FALSE
;
871 workaround_close_loop_end
= FALSE
;
874 case option_align_targets
:
875 align_targets
= TRUE
;
877 case option_no_align_targets
:
878 align_targets
= FALSE
;
881 case option_warn_unaligned_targets
:
882 warn_unaligned_branch_targets
= TRUE
;
885 case option_rename_section_name
:
886 build_section_rename (arg
);
890 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
891 should be emitted or not. FIXME: Not implemented. */
894 case option_prefer_l32r
:
896 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
900 case option_prefer_const16
:
902 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
906 case option_target_hardware
:
908 int earliest
, latest
= 0;
909 if (*arg
== 0 || *arg
== '-')
910 as_fatal (_("invalid target hardware version"));
912 earliest
= strtol (arg
, &arg
, 0);
916 else if (*arg
== '-')
919 as_fatal (_("invalid target hardware version"));
920 latest
= strtol (arg
, &arg
, 0);
923 as_fatal (_("invalid target hardware version"));
925 xtensa_setup_hw_workarounds (earliest
, latest
);
929 case option_transform
:
930 /* This option has no affect other than to use the defaults,
931 which are already set. */
934 case option_no_transform
:
935 /* This option turns off all transformations of any kind.
936 However, because we want to preserve the state of other
937 directives, we only change its own field. Thus, before
938 you perform any transformation, always check if transform
939 is available. If you use the functions we provide for this
940 purpose, you will be ok. */
941 directive_state
[directive_transform
] = FALSE
;
951 md_show_usage (FILE *stream
)
955 --[no-]text-section-literals\n\
956 [Do not] put literals in the text section\n\
957 --[no-]absolute-literals\n\
958 [Do not] default to use non-PC-relative literals\n\
959 --[no-]target-align [Do not] try to align branch targets\n\
960 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
961 --[no-]transform [Do not] transform instructions\n\
962 --flix both allow hand-written and generate flix bundles\n\
963 --no-generate-flix allow hand-written but do not generate\n\
965 --no-allow-flix neither allow hand-written nor generate\n\
967 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
971 /* Functions related to the list of current label symbols. */
974 xtensa_add_insn_label (symbolS
*sym
)
978 if (!free_insn_labels
)
979 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
982 l
= free_insn_labels
;
983 free_insn_labels
= l
->next
;
987 l
->next
= insn_labels
;
993 xtensa_clear_insn_labels (void)
997 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1005 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1009 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1011 symbolS
*lit_sym
= lit
->sym
;
1012 S_SET_VALUE (lit_sym
, new_offset
);
1013 symbol_set_frag (lit_sym
, new_frag
);
1018 /* Directive data and functions. */
1020 typedef struct state_stackS_struct
1022 directiveE directive
;
1023 bfd_boolean negated
;
1024 bfd_boolean old_state
;
1028 struct state_stackS_struct
*prev
;
1031 state_stackS
*directive_state_stack
;
1033 const pseudo_typeS md_pseudo_table
[] =
1035 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1036 { "literal_position", xtensa_literal_position
, 0 },
1037 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1038 { "long", xtensa_elf_cons
, 4 },
1039 { "word", xtensa_elf_cons
, 4 },
1040 { "4byte", xtensa_elf_cons
, 4 },
1041 { "short", xtensa_elf_cons
, 2 },
1042 { "2byte", xtensa_elf_cons
, 2 },
1043 { "sleb128", xtensa_leb128
, 1},
1044 { "uleb128", xtensa_leb128
, 0},
1045 { "begin", xtensa_begin_directive
, 0 },
1046 { "end", xtensa_end_directive
, 0 },
1047 { "literal", xtensa_literal_pseudo
, 0 },
1048 { "frequency", xtensa_frequency_pseudo
, 0 },
1054 use_transform (void)
1056 /* After md_end, you should be checking frag by frag, rather
1057 than state directives. */
1058 gas_assert (!past_xtensa_end
);
1059 return directive_state
[directive_transform
];
1064 do_align_targets (void)
1066 /* Do not use this function after md_end; just look at align_targets
1067 instead. There is no target-align directive, so alignment is either
1068 enabled for all frags or not done at all. */
1069 gas_assert (!past_xtensa_end
);
1070 return align_targets
&& use_transform ();
1075 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1079 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1081 as_where (&file
, &line
);
1083 stack
->directive
= directive
;
1084 stack
->negated
= negated
;
1085 stack
->old_state
= directive_state
[directive
];
1088 stack
->datum
= datum
;
1089 stack
->prev
= directive_state_stack
;
1090 directive_state_stack
= stack
;
1092 directive_state
[directive
] = !negated
;
1097 directive_pop (directiveE
*directive
,
1098 bfd_boolean
*negated
,
1103 state_stackS
*top
= directive_state_stack
;
1105 if (!directive_state_stack
)
1107 as_bad (_("unmatched end directive"));
1108 *directive
= directive_none
;
1112 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1113 *directive
= top
->directive
;
1114 *negated
= top
->negated
;
1117 *datum
= top
->datum
;
1118 directive_state_stack
= top
->prev
;
1124 directive_balance (void)
1126 while (directive_state_stack
)
1128 directiveE directive
;
1129 bfd_boolean negated
;
1134 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1135 as_warn_where ((char *) file
, line
,
1136 _(".begin directive with no matching .end directive"));
1142 inside_directive (directiveE dir
)
1144 state_stackS
*top
= directive_state_stack
;
1146 while (top
&& top
->directive
!= dir
)
1149 return (top
!= NULL
);
1154 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1158 char *directive_string
;
1160 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1165 input_line_pointer
+= 3;
1168 len
= strspn (input_line_pointer
,
1169 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1171 /* This code is a hack to make .begin [no-][generics|relax] exactly
1172 equivalent to .begin [no-]transform. We should remove it when
1173 we stop accepting those options. */
1175 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1177 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1178 directive_string
= "transform";
1180 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1182 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1183 directive_string
= "transform";
1186 directive_string
= input_line_pointer
;
1188 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1190 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1192 input_line_pointer
+= len
;
1193 *directive
= (directiveE
) i
;
1194 if (*negated
&& !directive_info
[i
].can_be_negated
)
1195 as_bad (_("directive %s cannot be negated"),
1196 directive_info
[i
].name
);
1201 as_bad (_("unknown directive"));
1202 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1207 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1209 directiveE directive
;
1210 bfd_boolean negated
;
1214 get_directive (&directive
, &negated
);
1215 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1217 discard_rest_of_line ();
1221 if (cur_vinsn
.inside_bundle
)
1222 as_bad (_("directives are not valid inside bundles"));
1226 case directive_literal
:
1227 if (!inside_directive (directive_literal
))
1229 /* Previous labels go with whatever follows this directive, not with
1230 the literal, so save them now. */
1231 saved_insn_labels
= insn_labels
;
1234 as_warn (_(".begin literal is deprecated; use .literal instead"));
1235 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1236 xtensa_switch_to_literal_fragment (state
);
1237 directive_push (directive_literal
, negated
, state
);
1240 case directive_literal_prefix
:
1241 /* Have to flush pending output because a movi relaxed to an l32r
1242 might produce a literal. */
1243 md_flush_pending_output ();
1244 /* Check to see if the current fragment is a literal
1245 fragment. If it is, then this operation is not allowed. */
1246 if (generating_literals
)
1248 as_bad (_("cannot set literal_prefix inside literal fragment"));
1252 /* Allocate the literal state for this section and push
1253 onto the directive stack. */
1254 ls
= xmalloc (sizeof (lit_state
));
1257 *ls
= default_lit_sections
;
1258 directive_push (directive_literal_prefix
, negated
, ls
);
1260 /* Process the new prefix. */
1261 xtensa_literal_prefix ();
1264 case directive_freeregs
:
1265 /* This information is currently unused, but we'll accept the statement
1266 and just discard the rest of the line. This won't check the syntax,
1267 but it will accept every correct freeregs directive. */
1268 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1269 directive_push (directive_freeregs
, negated
, 0);
1272 case directive_schedule
:
1273 md_flush_pending_output ();
1274 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1275 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1276 directive_push (directive_schedule
, negated
, 0);
1277 xtensa_set_frag_assembly_state (frag_now
);
1280 case directive_density
:
1281 as_warn (_(".begin [no-]density is ignored"));
1284 case directive_absolute_literals
:
1285 md_flush_pending_output ();
1286 if (!absolute_literals_supported
&& !negated
)
1288 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1291 xtensa_set_frag_assembly_state (frag_now
);
1292 directive_push (directive
, negated
, 0);
1296 md_flush_pending_output ();
1297 xtensa_set_frag_assembly_state (frag_now
);
1298 directive_push (directive
, negated
, 0);
1302 demand_empty_rest_of_line ();
1307 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1309 directiveE begin_directive
, end_directive
;
1310 bfd_boolean begin_negated
, end_negated
;
1314 emit_state
**state_ptr
;
1317 if (cur_vinsn
.inside_bundle
)
1318 as_bad (_("directives are not valid inside bundles"));
1320 get_directive (&end_directive
, &end_negated
);
1322 md_flush_pending_output ();
1324 switch (end_directive
)
1326 case (directiveE
) XTENSA_UNDEFINED
:
1327 discard_rest_of_line ();
1330 case directive_density
:
1331 as_warn (_(".end [no-]density is ignored"));
1332 demand_empty_rest_of_line ();
1335 case directive_absolute_literals
:
1336 if (!absolute_literals_supported
&& !end_negated
)
1338 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1339 demand_empty_rest_of_line ();
1348 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1349 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1350 (const void **) state_ptr
);
1352 if (begin_directive
!= directive_none
)
1354 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1356 as_bad (_("does not match begin %s%s at %s:%d"),
1357 begin_negated
? "no-" : "",
1358 directive_info
[begin_directive
].name
, file
, line
);
1362 switch (end_directive
)
1364 case directive_literal
:
1365 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1366 xtensa_restore_emit_state (state
);
1367 xtensa_set_frag_assembly_state (frag_now
);
1369 if (!inside_directive (directive_literal
))
1371 /* Restore the list of current labels. */
1372 xtensa_clear_insn_labels ();
1373 insn_labels
= saved_insn_labels
;
1377 case directive_literal_prefix
:
1378 /* Restore the default collection sections from saved state. */
1379 s
= (lit_state
*) state
;
1381 default_lit_sections
= *s
;
1383 /* Free the state storage. */
1384 free (s
->lit_prefix
);
1388 case directive_schedule
:
1389 case directive_freeregs
:
1393 xtensa_set_frag_assembly_state (frag_now
);
1399 demand_empty_rest_of_line ();
1403 /* Place an aligned literal fragment at the current location. */
1406 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1408 md_flush_pending_output ();
1410 if (inside_directive (directive_literal
))
1411 as_warn (_(".literal_position inside literal directive; ignoring"));
1412 xtensa_mark_literal_pool_location ();
1414 demand_empty_rest_of_line ();
1415 xtensa_clear_insn_labels ();
1419 /* Support .literal label, expr, ... */
1422 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1425 char *p
, *base_name
;
1429 if (inside_directive (directive_literal
))
1431 as_bad (_(".literal not allowed inside .begin literal region"));
1432 ignore_rest_of_line ();
1436 md_flush_pending_output ();
1438 /* Previous labels go with whatever follows this directive, not with
1439 the literal, so save them now. */
1440 saved_insn_labels
= insn_labels
;
1443 /* If we are using text-section literals, then this is the right value... */
1446 base_name
= input_line_pointer
;
1448 xtensa_switch_to_literal_fragment (&state
);
1450 /* ...but if we aren't using text-section-literals, then we
1451 need to put them in the section we just switched to. */
1452 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1455 /* All literals are aligned to four-byte boundaries. */
1456 frag_align (2, 0, 0);
1457 record_alignment (now_seg
, 2);
1459 c
= get_symbol_end ();
1460 /* Just after name is now '\0'. */
1461 p
= input_line_pointer
;
1465 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1467 as_bad (_("expected comma or colon after symbol name; "
1468 "rest of line ignored"));
1469 ignore_rest_of_line ();
1470 xtensa_restore_emit_state (&state
);
1478 input_line_pointer
++; /* skip ',' or ':' */
1480 xtensa_elf_cons (4);
1482 xtensa_restore_emit_state (&state
);
1484 /* Restore the list of current labels. */
1485 xtensa_clear_insn_labels ();
1486 insn_labels
= saved_insn_labels
;
1491 xtensa_literal_prefix (void)
1496 /* Parse the new prefix from the input_line_pointer. */
1498 len
= strspn (input_line_pointer
,
1499 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1500 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1502 /* Get a null-terminated copy of the name. */
1503 name
= xmalloc (len
+ 1);
1505 strncpy (name
, input_line_pointer
, len
);
1508 /* Skip the name in the input line. */
1509 input_line_pointer
+= len
;
1511 default_lit_sections
.lit_prefix
= name
;
1513 /* Clear cached literal sections, since the prefix has changed. */
1514 default_lit_sections
.lit_seg
= NULL
;
1515 default_lit_sections
.lit4_seg
= NULL
;
1519 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1522 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1524 float fall_through_f
, target_f
;
1526 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1527 if (fall_through_f
< 0)
1529 as_bad (_("fall through frequency must be greater than 0"));
1530 ignore_rest_of_line ();
1534 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1537 as_bad (_("branch target frequency must be greater than 0"));
1538 ignore_rest_of_line ();
1542 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1544 demand_empty_rest_of_line ();
1548 /* Like normal .long/.short/.word, except support @plt, etc.
1549 Clobbers input_line_pointer, checks end-of-line. */
1552 xtensa_elf_cons (int nbytes
)
1555 bfd_reloc_code_real_type reloc
;
1557 md_flush_pending_output ();
1559 if (cur_vinsn
.inside_bundle
)
1560 as_bad (_("directives are not valid inside bundles"));
1562 if (is_it_end_of_statement ())
1564 demand_empty_rest_of_line ();
1571 if (exp
.X_op
== O_symbol
1572 && *input_line_pointer
== '@'
1573 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1576 reloc_howto_type
*reloc_howto
=
1577 bfd_reloc_type_lookup (stdoutput
, reloc
);
1579 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1580 as_bad (_("unsupported relocation"));
1581 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1582 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1583 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1584 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1585 as_bad (_("opcode-specific %s relocation used outside "
1586 "an instruction"), reloc_howto
->name
);
1587 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1588 as_bad (_("%s relocations do not fit in %d bytes"),
1589 reloc_howto
->name
, nbytes
);
1590 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1591 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1592 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1593 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1596 char *p
= frag_more ((int) nbytes
);
1597 xtensa_set_frag_assembly_state (frag_now
);
1598 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1599 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1604 xtensa_set_frag_assembly_state (frag_now
);
1605 emit_expr (&exp
, (unsigned int) nbytes
);
1608 while (*input_line_pointer
++ == ',');
1610 input_line_pointer
--; /* Put terminator back into stream. */
1611 demand_empty_rest_of_line ();
1614 static bfd_boolean is_leb128_expr
;
1617 xtensa_leb128 (int sign
)
1619 is_leb128_expr
= TRUE
;
1621 is_leb128_expr
= FALSE
;
1625 /* Parsing and Idiom Translation. */
1627 /* Parse @plt, etc. and return the desired relocation. */
1628 static bfd_reloc_code_real_type
1629 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1636 struct suffix_reloc_map
*ptr
;
1639 return BFD_RELOC_NONE
;
1641 for (ch
= *str
, str2
= ident
;
1642 (str2
< ident
+ sizeof (ident
) - 1
1643 && (ISALNUM (ch
) || ch
== '@'));
1646 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1653 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1654 if (ch
== ptr
->suffix
[0]
1655 && len
== ptr
->length
1656 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1658 /* Now check for "identifier@suffix+constant". */
1659 if (*str
== '-' || *str
== '+')
1661 char *orig_line
= input_line_pointer
;
1662 expressionS new_exp
;
1664 input_line_pointer
= str
;
1665 expression (&new_exp
);
1666 if (new_exp
.X_op
== O_constant
)
1668 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1669 str
= input_line_pointer
;
1672 if (&input_line_pointer
!= str_p
)
1673 input_line_pointer
= orig_line
;
1680 return BFD_RELOC_UNUSED
;
1684 /* Find the matching operator type. */
1685 static unsigned char
1686 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1688 struct suffix_reloc_map
*sfx
;
1689 unsigned char operator = (unsigned char) -1;
1691 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1693 if (sfx
->reloc
== reloc
)
1695 operator = sfx
->operator;
1699 gas_assert (operator != (unsigned char) -1);
1704 /* Find the matching reloc type. */
1705 static bfd_reloc_code_real_type
1706 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1708 struct suffix_reloc_map
*sfx
;
1709 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1711 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1713 if (sfx
->operator == operator)
1722 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1723 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1724 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1725 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1728 if (reloc
== BFD_RELOC_UNUSED
)
1729 return BFD_RELOC_32
;
1736 expression_end (const char *name
)
1759 #define ERROR_REG_NUM ((unsigned) -1)
1762 tc_get_register (const char *prefix
)
1765 const char *next_expr
;
1766 const char *old_line_pointer
;
1769 old_line_pointer
= input_line_pointer
;
1771 if (*input_line_pointer
== '$')
1772 ++input_line_pointer
;
1774 /* Accept "sp" as a synonym for "a1". */
1775 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1776 && expression_end (input_line_pointer
+ 2))
1778 input_line_pointer
+= 2;
1779 return 1; /* AR[1] */
1782 while (*input_line_pointer
++ == *prefix
++)
1784 --input_line_pointer
;
1789 as_bad (_("bad register name: %s"), old_line_pointer
);
1790 return ERROR_REG_NUM
;
1793 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1795 as_bad (_("bad register number: %s"), input_line_pointer
);
1796 return ERROR_REG_NUM
;
1801 while (ISDIGIT ((int) *input_line_pointer
))
1802 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1804 if (!(next_expr
= expression_end (input_line_pointer
)))
1806 as_bad (_("bad register name: %s"), old_line_pointer
);
1807 return ERROR_REG_NUM
;
1810 input_line_pointer
= (char *) next_expr
;
1817 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1819 xtensa_isa isa
= xtensa_default_isa
;
1821 /* Check if this is an immediate operand. */
1822 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1824 bfd_reloc_code_real_type reloc
;
1825 segT t
= expression (tok
);
1827 if (t
== absolute_section
1828 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1830 gas_assert (tok
->X_op
== O_constant
);
1831 tok
->X_op
= O_symbol
;
1832 tok
->X_add_symbol
= &abs_symbol
;
1835 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1836 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1841 case BFD_RELOC_LO16
:
1842 if (tok
->X_op
== O_constant
)
1844 tok
->X_add_number
&= 0xffff;
1848 case BFD_RELOC_HI16
:
1849 if (tok
->X_op
== O_constant
)
1851 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1855 case BFD_RELOC_UNUSED
:
1856 as_bad (_("unsupported relocation"));
1858 case BFD_RELOC_32_PCREL
:
1859 as_bad (_("pcrel relocation not allowed in an instruction"));
1864 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1869 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1870 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1872 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1875 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1876 as_bad (_("register number out of range"));
1879 tok
->X_op
= O_register
;
1880 tok
->X_add_symbol
= 0;
1881 tok
->X_add_number
= reg
;
1886 /* Split up the arguments for an opcode or pseudo-op. */
1889 tokenize_arguments (char **args
, char *str
)
1891 char *old_input_line_pointer
;
1892 bfd_boolean saw_comma
= FALSE
;
1893 bfd_boolean saw_arg
= FALSE
;
1894 bfd_boolean saw_colon
= FALSE
;
1896 char *arg_end
, *arg
;
1899 /* Save and restore input_line_pointer around this function. */
1900 old_input_line_pointer
= input_line_pointer
;
1901 input_line_pointer
= str
;
1903 while (*input_line_pointer
)
1906 switch (*input_line_pointer
)
1913 input_line_pointer
++;
1914 if (saw_comma
|| saw_colon
|| !saw_arg
)
1920 input_line_pointer
++;
1921 if (saw_comma
|| saw_colon
|| !saw_arg
)
1927 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1930 arg_end
= input_line_pointer
+ 1;
1931 while (!expression_end (arg_end
))
1934 arg_len
= arg_end
- input_line_pointer
;
1935 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1936 args
[num_args
] = arg
;
1940 strncpy (arg
, input_line_pointer
, arg_len
);
1941 arg
[arg_len
] = '\0';
1943 input_line_pointer
= arg_end
;
1953 if (saw_comma
|| saw_colon
)
1955 input_line_pointer
= old_input_line_pointer
;
1960 as_bad (_("extra comma"));
1962 as_bad (_("extra colon"));
1964 as_bad (_("missing argument"));
1966 as_bad (_("missing comma or colon"));
1967 input_line_pointer
= old_input_line_pointer
;
1972 /* Parse the arguments to an opcode. Return TRUE on error. */
1975 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1977 expressionS
*tok
, *last_tok
;
1978 xtensa_opcode opcode
= insn
->opcode
;
1979 bfd_boolean had_error
= TRUE
;
1980 xtensa_isa isa
= xtensa_default_isa
;
1981 int n
, num_regs
= 0;
1982 int opcode_operand_count
;
1983 int opnd_cnt
, last_opnd_cnt
;
1984 unsigned int next_reg
= 0;
1985 char *old_input_line_pointer
;
1987 if (insn
->insn_type
== ITYPE_LITERAL
)
1988 opcode_operand_count
= 1;
1990 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1993 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1995 /* Save and restore input_line_pointer around this function. */
1996 old_input_line_pointer
= input_line_pointer
;
2002 /* Skip invisible operands. */
2003 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2009 for (n
= 0; n
< num_args
; n
++)
2011 input_line_pointer
= arg_strings
[n
];
2012 if (*input_line_pointer
== ':')
2014 xtensa_regfile opnd_rf
;
2015 input_line_pointer
++;
2018 gas_assert (opnd_cnt
> 0);
2020 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2022 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2023 as_warn (_("incorrect register number, ignoring"));
2028 if (opnd_cnt
>= opcode_operand_count
)
2030 as_warn (_("too many arguments"));
2033 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2035 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2036 next_reg
= tok
->X_add_number
+ 1;
2038 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2040 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2042 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2043 /* minus 1 because we are seeing one right now */
2049 last_opnd_cnt
= opnd_cnt
;
2050 demand_empty_rest_of_line ();
2057 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2061 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2064 insn
->ntok
= tok
- insn
->tok
;
2068 input_line_pointer
= old_input_line_pointer
;
2074 get_invisible_operands (TInsn
*insn
)
2076 xtensa_isa isa
= xtensa_default_isa
;
2077 static xtensa_insnbuf slotbuf
= NULL
;
2079 xtensa_opcode opc
= insn
->opcode
;
2080 int slot
, opnd
, fmt_found
;
2084 slotbuf
= xtensa_insnbuf_alloc (isa
);
2086 /* Find format/slot where this can be encoded. */
2089 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2091 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2093 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2099 if (fmt_found
) break;
2104 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2108 /* First encode all the visible operands
2109 (to deal with shared field operands). */
2110 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2112 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2113 && (insn
->tok
[opnd
].X_op
== O_register
2114 || insn
->tok
[opnd
].X_op
== O_constant
))
2116 val
= insn
->tok
[opnd
].X_add_number
;
2117 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2118 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2122 /* Then pull out the values for the invisible ones. */
2123 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2125 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2127 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2128 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2129 insn
->tok
[opnd
].X_add_number
= val
;
2130 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2131 insn
->tok
[opnd
].X_op
= O_register
;
2133 insn
->tok
[opnd
].X_op
= O_constant
;
2142 xg_reverse_shift_count (char **cnt_argp
)
2144 char *cnt_arg
, *new_arg
;
2145 cnt_arg
= *cnt_argp
;
2147 /* replace the argument with "31-(argument)" */
2148 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2149 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2152 *cnt_argp
= new_arg
;
2156 /* If "arg" is a constant expression, return non-zero with the value
2160 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2163 char *save_ptr
= input_line_pointer
;
2165 input_line_pointer
= arg
;
2167 input_line_pointer
= save_ptr
;
2169 if (exp
.X_op
== O_constant
)
2171 *valp
= exp
.X_add_number
;
2180 xg_replace_opname (char **popname
, char *newop
)
2183 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2184 strcpy (*popname
, newop
);
2189 xg_check_num_args (int *pnum_args
,
2194 int num_args
= *pnum_args
;
2196 if (num_args
< expected_num
)
2198 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2199 num_args
, opname
, expected_num
);
2203 if (num_args
> expected_num
)
2205 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2206 num_args
, opname
, expected_num
);
2207 while (num_args
-- > expected_num
)
2209 free (arg_strings
[num_args
]);
2210 arg_strings
[num_args
] = 0;
2212 *pnum_args
= expected_num
;
2220 /* If the register is not specified as part of the opcode,
2221 then get it from the operand and move it to the opcode. */
2224 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2226 xtensa_isa isa
= xtensa_default_isa
;
2228 char *opname
, *new_opname
;
2229 const char *sr_name
;
2230 int is_user
, is_write
;
2235 is_user
= (opname
[1] == 'u');
2236 is_write
= (opname
[0] == 'w');
2238 /* Opname == [rw]ur or [rwx]sr... */
2240 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2243 /* Check if the argument is a symbolic register name. */
2244 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2245 /* Handle WSR to "INTSET" as a special case. */
2246 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2247 && !strcasecmp (arg_strings
[1], "intset"))
2248 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2249 if (sr
== XTENSA_UNDEFINED
2250 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2252 /* Maybe it's a register number.... */
2254 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2256 as_bad (_("invalid register '%s' for '%s' instruction"),
2257 arg_strings
[1], opname
);
2260 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2261 if (sr
== XTENSA_UNDEFINED
)
2263 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2264 (long) val
, opname
);
2269 /* Remove the last argument, which is now part of the opcode. */
2270 free (arg_strings
[1]);
2274 /* Translate the opcode. */
2275 sr_name
= xtensa_sysreg_name (isa
, sr
);
2276 /* Another special case for "WSR.INTSET".... */
2277 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2279 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2280 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2282 *popname
= new_opname
;
2289 xtensa_translate_old_userreg_ops (char **popname
)
2291 xtensa_isa isa
= xtensa_default_isa
;
2293 char *opname
, *new_opname
;
2294 const char *sr_name
;
2295 bfd_boolean has_underbar
= FALSE
;
2298 if (opname
[0] == '_')
2300 has_underbar
= TRUE
;
2304 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2305 if (sr
!= XTENSA_UNDEFINED
)
2307 /* The new default name ("nnn") is different from the old default
2308 name ("URnnn"). The old default is handled below, and we don't
2309 want to recognize [RW]nnn, so do nothing if the name is the (new)
2311 static char namebuf
[10];
2312 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2313 if (strcmp (namebuf
, opname
+ 1) == 0)
2321 /* Only continue if the reg name is "URnnn". */
2322 if (opname
[1] != 'u' || opname
[2] != 'r')
2324 val
= strtoul (opname
+ 3, &end
, 10);
2328 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2329 if (sr
== XTENSA_UNDEFINED
)
2331 as_bad (_("invalid register number (%ld) for '%s'"),
2332 (long) val
, opname
);
2337 /* Translate the opcode. */
2338 sr_name
= xtensa_sysreg_name (isa
, sr
);
2339 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2340 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2341 opname
[0], sr_name
);
2343 *popname
= new_opname
;
2350 xtensa_translate_zero_immed (char *old_op
,
2360 gas_assert (opname
[0] != '_');
2362 if (strcmp (opname
, old_op
) != 0)
2365 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2367 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2369 xg_replace_opname (popname
, new_op
);
2370 free (arg_strings
[1]);
2371 arg_strings
[1] = arg_strings
[2];
2380 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2381 Returns non-zero if an error was found. */
2384 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2386 char *opname
= *popname
;
2387 bfd_boolean has_underbar
= FALSE
;
2391 has_underbar
= TRUE
;
2395 if (strcmp (opname
, "mov") == 0)
2397 if (use_transform () && !has_underbar
&& density_supported
)
2398 xg_replace_opname (popname
, "mov.n");
2401 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2403 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2404 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2405 strcpy (arg_strings
[2], arg_strings
[1]);
2411 if (strcmp (opname
, "bbsi.l") == 0)
2413 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2415 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2416 if (target_big_endian
)
2417 xg_reverse_shift_count (&arg_strings
[1]);
2421 if (strcmp (opname
, "bbci.l") == 0)
2423 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2425 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2426 if (target_big_endian
)
2427 xg_reverse_shift_count (&arg_strings
[1]);
2431 /* Don't do anything special with NOPs inside FLIX instructions. They
2432 are handled elsewhere. Real NOP instructions are always available
2433 in configurations with FLIX, so this should never be an issue but
2434 check for it anyway. */
2435 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2436 && strcmp (opname
, "nop") == 0)
2438 if (use_transform () && !has_underbar
&& density_supported
)
2439 xg_replace_opname (popname
, "nop.n");
2442 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2444 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2445 arg_strings
[0] = (char *) xmalloc (3);
2446 arg_strings
[1] = (char *) xmalloc (3);
2447 arg_strings
[2] = (char *) xmalloc (3);
2448 strcpy (arg_strings
[0], "a1");
2449 strcpy (arg_strings
[1], "a1");
2450 strcpy (arg_strings
[2], "a1");
2456 /* Recognize [RW]UR and [RWX]SR. */
2457 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2458 && (opname
[1] == 'u' || opname
[1] == 's'))
2459 || (opname
[0] == 'x' && opname
[1] == 's'))
2461 && opname
[3] == '\0')
2462 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2464 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2465 [RW]<name> if <name> is the non-default name of a user register. */
2466 if ((opname
[0] == 'r' || opname
[0] == 'w')
2467 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2468 return xtensa_translate_old_userreg_ops (popname
);
2470 /* Relax branches that don't allow comparisons against an immediate value
2471 of zero to the corresponding branches with implicit zero immediates. */
2472 if (!has_underbar
&& use_transform ())
2474 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2475 pnum_args
, arg_strings
))
2478 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2479 pnum_args
, arg_strings
))
2482 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2483 pnum_args
, arg_strings
))
2486 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2487 pnum_args
, arg_strings
))
2495 /* Functions for dealing with the Xtensa ISA. */
2497 /* Currently the assembler only allows us to use a single target per
2498 fragment. Because of this, only one operand for a given
2499 instruction may be symbolic. If there is a PC-relative operand,
2500 the last one is chosen. Otherwise, the result is the number of the
2501 last immediate operand, and if there are none of those, we fail and
2505 get_relaxable_immed (xtensa_opcode opcode
)
2507 int last_immed
= -1;
2510 if (opcode
== XTENSA_UNDEFINED
)
2513 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2514 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2516 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2518 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2520 if (last_immed
== -1
2521 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2528 static xtensa_opcode
2529 get_opcode_from_buf (const char *buf
, int slot
)
2531 static xtensa_insnbuf insnbuf
= NULL
;
2532 static xtensa_insnbuf slotbuf
= NULL
;
2533 xtensa_isa isa
= xtensa_default_isa
;
2538 insnbuf
= xtensa_insnbuf_alloc (isa
);
2539 slotbuf
= xtensa_insnbuf_alloc (isa
);
2542 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2543 fmt
= xtensa_format_decode (isa
, insnbuf
);
2544 if (fmt
== XTENSA_UNDEFINED
)
2545 return XTENSA_UNDEFINED
;
2547 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2548 return XTENSA_UNDEFINED
;
2550 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2551 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2555 #ifdef TENSILICA_DEBUG
2557 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2560 xtensa_print_insn_table (void)
2562 int num_opcodes
, num_operands
;
2563 xtensa_opcode opcode
;
2564 xtensa_isa isa
= xtensa_default_isa
;
2566 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2567 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2570 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2571 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2572 for (opn
= 0; opn
< num_operands
; opn
++)
2574 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2576 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2578 xtensa_regfile opnd_rf
=
2579 xtensa_operand_regfile (isa
, opcode
, opn
);
2580 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2582 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2583 fputs ("[lLr] ", stderr
);
2585 fputs ("i ", stderr
);
2587 fprintf (stderr
, "\n");
2593 print_vliw_insn (xtensa_insnbuf vbuf
)
2595 xtensa_isa isa
= xtensa_default_isa
;
2596 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2597 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2600 fprintf (stderr
, "format = %d\n", f
);
2602 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2604 xtensa_opcode opcode
;
2608 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2609 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2610 opname
= xtensa_opcode_name (isa
, opcode
);
2612 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2613 fprintf (stderr
, " operands = ");
2615 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2619 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2621 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2622 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2623 fprintf (stderr
, "%d ", val
);
2625 fprintf (stderr
, "\n");
2627 xtensa_insnbuf_free (isa
, sbuf
);
2630 #endif /* TENSILICA_DEBUG */
2634 is_direct_call_opcode (xtensa_opcode opcode
)
2636 xtensa_isa isa
= xtensa_default_isa
;
2637 int n
, num_operands
;
2639 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2642 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2643 for (n
= 0; n
< num_operands
; n
++)
2645 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2646 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2653 /* Convert from BFD relocation type code to slot and operand number.
2654 Returns non-zero on failure. */
2657 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2659 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2660 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2662 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2665 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2666 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2668 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2678 /* Convert from slot number to BFD relocation type code for the
2679 standard PC-relative relocations. Return BFD_RELOC_NONE on
2682 static bfd_reloc_code_real_type
2683 encode_reloc (int slot
)
2685 if (slot
< 0 || slot
> 14)
2686 return BFD_RELOC_NONE
;
2688 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2692 /* Convert from slot numbers to BFD relocation type code for the
2693 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2695 static bfd_reloc_code_real_type
2696 encode_alt_reloc (int slot
)
2698 if (slot
< 0 || slot
> 14)
2699 return BFD_RELOC_NONE
;
2701 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2706 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2709 xtensa_opcode opcode
,
2715 uint32 valbuf
= value
;
2717 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2719 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2721 as_bad_where ((char *) file
, line
,
2722 _("operand %d of '%s' has out of range value '%u'"),
2724 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2727 as_bad_where ((char *) file
, line
,
2728 _("operand %d of '%s' has invalid value '%u'"),
2730 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2735 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2741 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2744 xtensa_opcode opcode
,
2748 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2749 fmt
, slot
, slotbuf
, &val
);
2750 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2755 /* Checks for rules from xtensa-relax tables. */
2757 /* The routine xg_instruction_matches_option_term must return TRUE
2758 when a given option term is true. The meaning of all of the option
2759 terms is given interpretation by this function. */
2762 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2764 if (strcmp (option
->option_name
, "realnop") == 0
2765 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2767 /* These conditions were evaluated statically when building the
2768 relaxation table. There's no need to reevaluate them now. */
2771 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2772 return insn
->extra_arg
.X_op
== O_register
;
2775 as_fatal (_("internal error: unknown option name '%s'"),
2776 option
->option_name
);
2782 xg_instruction_matches_or_options (TInsn
*insn
,
2783 const ReqOrOptionList
*or_option
)
2785 const ReqOrOption
*option
;
2786 /* Must match each of the AND terms. */
2787 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2789 if (xg_instruction_matches_option_term (insn
, option
))
2797 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2799 const ReqOption
*req_options
;
2800 /* Must match each of the AND terms. */
2801 for (req_options
= options
;
2802 req_options
!= NULL
;
2803 req_options
= req_options
->next
)
2805 /* Must match one of the OR clauses. */
2806 if (!xg_instruction_matches_or_options (insn
,
2807 req_options
->or_option_terms
))
2814 /* Return the transition rule that matches or NULL if none matches. */
2817 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2819 PreconditionList
*condition_l
;
2821 if (rule
->opcode
!= insn
->opcode
)
2824 for (condition_l
= rule
->conditions
;
2825 condition_l
!= NULL
;
2826 condition_l
= condition_l
->next
)
2830 Precondition
*cond
= condition_l
->precond
;
2835 /* The expression must be the constant. */
2836 gas_assert (cond
->op_num
< insn
->ntok
);
2837 exp1
= &insn
->tok
[cond
->op_num
];
2838 if (expr_is_const (exp1
))
2843 if (get_expr_const (exp1
) != cond
->op_data
)
2847 if (get_expr_const (exp1
) == cond
->op_data
)
2854 else if (expr_is_register (exp1
))
2859 if (get_expr_register (exp1
) != cond
->op_data
)
2863 if (get_expr_register (exp1
) == cond
->op_data
)
2875 gas_assert (cond
->op_num
< insn
->ntok
);
2876 gas_assert (cond
->op_data
< insn
->ntok
);
2877 exp1
= &insn
->tok
[cond
->op_num
];
2878 exp2
= &insn
->tok
[cond
->op_data
];
2883 if (!expr_is_equal (exp1
, exp2
))
2887 if (expr_is_equal (exp1
, exp2
))
2899 if (!xg_instruction_matches_options (insn
, rule
->options
))
2907 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2909 bfd_boolean a_greater
= FALSE
;
2910 bfd_boolean b_greater
= FALSE
;
2912 ReqOptionList
*l_a
= a
->options
;
2913 ReqOptionList
*l_b
= b
->options
;
2915 /* We only care if they both are the same except for
2916 a const16 vs. an l32r. */
2918 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2920 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2921 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2922 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2924 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2926 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2928 /* This is the case we care about. */
2929 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2930 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2937 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2938 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2948 l_or_a
= l_or_a
->next
;
2949 l_or_b
= l_or_b
->next
;
2951 if (l_or_a
|| l_or_b
)
2960 /* Incomparable if the substitution was used differently in two cases. */
2961 if (a_greater
&& b_greater
)
2973 static TransitionRule
*
2974 xg_instruction_match (TInsn
*insn
)
2976 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2978 gas_assert (insn
->opcode
< table
->num_opcodes
);
2980 /* Walk through all of the possible transitions. */
2981 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2983 TransitionRule
*rule
= l
->rule
;
2984 if (xg_instruction_matches_rule (insn
, rule
))
2991 /* Various Other Internal Functions. */
2994 is_unique_insn_expansion (TransitionRule
*r
)
2996 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2998 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3004 /* Check if there is exactly one relaxation for INSN that converts it to
3005 another instruction of equal or larger size. If so, and if TARG is
3006 non-null, go ahead and generate the relaxed instruction into TARG. If
3007 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3008 instruction, i.e., ignore relaxations that convert to an instruction of
3009 equal size. In some contexts where this function is used, only
3010 a single widening is allowed and the NARROW_ONLY argument is used to
3011 exclude cases like ADDI being "widened" to an ADDMI, which may
3012 later be relaxed to an ADDMI/ADDI pair. */
3015 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3017 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3019 TransitionRule
*match
= 0;
3021 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3022 gas_assert (insn
->opcode
< table
->num_opcodes
);
3024 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3026 TransitionRule
*rule
= l
->rule
;
3028 if (xg_instruction_matches_rule (insn
, rule
)
3029 && is_unique_insn_expansion (rule
)
3030 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3031 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3042 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3047 /* Return the maximum number of bytes this opcode can expand to. */
3050 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3052 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3054 int max_size
= xg_get_single_size (opcode
);
3056 gas_assert (opcode
< table
->num_opcodes
);
3058 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3060 TransitionRule
*rule
= l
->rule
;
3061 BuildInstr
*build_list
;
3066 build_list
= rule
->to_instr
;
3067 if (is_unique_insn_expansion (rule
))
3069 gas_assert (build_list
->typ
== INSTR_INSTR
);
3070 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3073 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3075 switch (build_list
->typ
)
3078 this_size
+= xg_get_single_size (build_list
->opcode
);
3080 case INSTR_LITERAL_DEF
:
3081 case INSTR_LABEL_DEF
:
3086 if (this_size
> max_size
)
3087 max_size
= this_size
;
3093 /* Return the maximum number of literal bytes this opcode can generate. */
3096 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3098 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3102 gas_assert (opcode
< table
->num_opcodes
);
3104 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3106 TransitionRule
*rule
= l
->rule
;
3107 BuildInstr
*build_list
;
3112 build_list
= rule
->to_instr
;
3113 if (is_unique_insn_expansion (rule
))
3115 gas_assert (build_list
->typ
== INSTR_INSTR
);
3116 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3119 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3121 switch (build_list
->typ
)
3123 case INSTR_LITERAL_DEF
:
3124 /* Hard-coded 4-byte literal. */
3128 case INSTR_LABEL_DEF
:
3133 if (this_size
> max_size
)
3134 max_size
= this_size
;
3141 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3143 int steps_taken
= 0;
3144 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3147 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3148 gas_assert (insn
->opcode
< table
->num_opcodes
);
3150 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3152 TransitionRule
*rule
= l
->rule
;
3154 if (xg_instruction_matches_rule (insn
, rule
))
3156 if (steps_taken
== lateral_steps
)
3166 get_special_literal_symbol (void)
3168 static symbolS
*sym
= NULL
;
3171 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3177 get_special_label_symbol (void)
3179 static symbolS
*sym
= NULL
;
3182 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3188 xg_valid_literal_expression (const expressionS
*exp
)
3210 /* This will check to see if the value can be converted into the
3211 operand type. It will return TRUE if it does not fit. */
3214 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3216 uint32 valbuf
= value
;
3217 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3223 /* Assumes: All immeds are constants. Check that all constants fit
3224 into their immeds; return FALSE if not. */
3227 xg_immeds_fit (const TInsn
*insn
)
3229 xtensa_isa isa
= xtensa_default_isa
;
3233 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3234 for (i
= 0; i
< n
; ++i
)
3236 const expressionS
*exp
= &insn
->tok
[i
];
3238 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3245 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3250 /* The symbol should have a fixup associated with it. */
3259 /* This should only be called after we have an initial
3260 estimate of the addresses. */
3263 xg_symbolic_immeds_fit (const TInsn
*insn
,
3269 xtensa_isa isa
= xtensa_default_isa
;
3277 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3279 for (i
= 0; i
< n
; ++i
)
3281 const expressionS
*exp
= &insn
->tok
[i
];
3283 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3290 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3296 /* Check for the worst case. */
3297 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3302 /* We only allow symbols for PC-relative references.
3303 If pc_frag == 0, then we don't have frag locations yet. */
3305 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3308 /* If it is a weak symbol or a symbol in a different section,
3309 it cannot be known to fit at assembly time. */
3310 if (S_IS_WEAK (exp
->X_add_symbol
)
3311 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3313 /* For a direct call with --no-longcalls, be optimistic and
3314 assume it will be in range. If the symbol is weak and
3315 undefined, it may remain undefined at link-time, in which
3316 case it will have a zero value and almost certainly be out
3317 of range for a direct call; thus, relax for undefined weak
3318 symbols even if longcalls is not enabled. */
3319 if (is_direct_call_opcode (insn
->opcode
)
3320 && ! pc_frag
->tc_frag_data
.use_longcalls
3321 && (! S_IS_WEAK (exp
->X_add_symbol
)
3322 || S_IS_DEFINED (exp
->X_add_symbol
)))
3328 symbolP
= exp
->X_add_symbol
;
3329 sym_frag
= symbol_get_frag (symbolP
);
3330 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3331 pc
= pc_frag
->fr_address
+ pc_offset
;
3333 /* If frag has yet to be reached on this pass, assume it
3334 will move by STRETCH just as we did. If this is not so,
3335 it will be because some frag between grows, and that will
3336 force another pass. Beware zero-length frags. There
3337 should be a faster way to do this. */
3340 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3341 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3346 new_offset
= target
;
3347 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3348 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3353 /* The symbol should have a fixup associated with it. */
3362 /* Return TRUE on success. */
3365 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3371 targ
->debug_line
= insn
->debug_line
;
3372 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3377 targ
->opcode
= bi
->opcode
;
3378 targ
->insn_type
= ITYPE_INSN
;
3379 targ
->is_specific_opcode
= FALSE
;
3381 for (; op
!= NULL
; op
= op
->next
)
3383 int op_num
= op
->op_num
;
3384 int op_data
= op
->op_data
;
3386 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3388 if (targ
->ntok
<= op_num
)
3389 targ
->ntok
= op_num
+ 1;
3394 set_expr_const (&targ
->tok
[op_num
], op_data
);
3397 gas_assert (op_data
< insn
->ntok
);
3398 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3401 if (insn
->extra_arg
.X_op
!= O_register
)
3403 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3406 sym
= get_special_literal_symbol ();
3407 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3408 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3409 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3410 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3413 sym
= get_special_label_symbol ();
3414 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3416 case OP_OPERAND_HI16U
:
3417 case OP_OPERAND_LOW16U
:
3418 gas_assert (op_data
< insn
->ntok
);
3419 if (expr_is_const (&insn
->tok
[op_data
]))
3422 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3423 val
= xg_apply_userdef_op_fn (op
->typ
,
3426 targ
->tok
[op_num
].X_add_number
= val
;
3430 /* For const16 we can create relocations for these. */
3431 if (targ
->opcode
== XTENSA_UNDEFINED
3432 || (targ
->opcode
!= xtensa_const16_opcode
))
3434 gas_assert (op_data
< insn
->ntok
);
3435 /* Need to build a O_lo16 or O_hi16. */
3436 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3437 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3439 if (op
->typ
== OP_OPERAND_HI16U
)
3440 targ
->tok
[op_num
].X_op
= O_hi16
;
3441 else if (op
->typ
== OP_OPERAND_LOW16U
)
3442 targ
->tok
[op_num
].X_op
= O_lo16
;
3449 /* currently handles:
3452 OP_OPERAND_F32MINUS */
3453 if (xg_has_userdef_op_fn (op
->typ
))
3455 gas_assert (op_data
< insn
->ntok
);
3456 if (expr_is_const (&insn
->tok
[op_data
]))
3459 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3460 val
= xg_apply_userdef_op_fn (op
->typ
,
3463 targ
->tok
[op_num
].X_add_number
= val
;
3466 return FALSE
; /* We cannot use a relocation for this. */
3475 case INSTR_LITERAL_DEF
:
3477 targ
->opcode
= XTENSA_UNDEFINED
;
3478 targ
->insn_type
= ITYPE_LITERAL
;
3479 targ
->is_specific_opcode
= FALSE
;
3480 for (; op
!= NULL
; op
= op
->next
)
3482 int op_num
= op
->op_num
;
3483 int op_data
= op
->op_data
;
3484 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3486 if (targ
->ntok
<= op_num
)
3487 targ
->ntok
= op_num
+ 1;
3492 gas_assert (op_data
< insn
->ntok
);
3493 /* We can only pass resolvable literals through. */
3494 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3496 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3508 case INSTR_LABEL_DEF
:
3510 targ
->opcode
= XTENSA_UNDEFINED
;
3511 targ
->insn_type
= ITYPE_LABEL
;
3512 targ
->is_specific_opcode
= FALSE
;
3513 /* Literal with no ops is a label? */
3514 gas_assert (op
== NULL
);
3525 /* Return TRUE on success. */
3528 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3530 for (; bi
!= NULL
; bi
= bi
->next
)
3532 TInsn
*next_insn
= istack_push_space (istack
);
3534 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3541 /* Return TRUE on valid expansion. */
3544 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3546 int stack_size
= istack
->ninsn
;
3547 int steps_taken
= 0;
3548 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3551 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3552 gas_assert (insn
->opcode
< table
->num_opcodes
);
3554 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3556 TransitionRule
*rule
= l
->rule
;
3558 if (xg_instruction_matches_rule (insn
, rule
))
3560 if (lateral_steps
== steps_taken
)
3564 /* This is it. Expand the rule to the stack. */
3565 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3568 /* Check to see if it fits. */
3569 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3571 TInsn
*tinsn
= &istack
->insn
[i
];
3573 if (tinsn
->insn_type
== ITYPE_INSN
3574 && !tinsn_has_symbolic_operands (tinsn
)
3575 && !xg_immeds_fit (tinsn
))
3577 istack
->ninsn
= stack_size
;
3590 /* Relax the assembly instruction at least "min_steps".
3591 Return the number of steps taken.
3593 For relaxation to correctly terminate, every relaxation chain must
3594 terminate in one of two ways:
3596 1. If the chain from one instruction to the next consists entirely of
3597 single instructions, then the chain *must* handle all possible
3598 immediates without failing. It must not ever fail because an
3599 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3600 chain is one example. L32R loads 32 bits, and there cannot be an
3601 immediate larger than 32 bits, so it satisfies this condition.
3602 Single instruction relaxation chains are as defined by
3603 xg_is_single_relaxable_instruction.
3605 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3606 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3608 Strictly speaking, in most cases you can violate condition 1 and be OK
3609 -- in particular when the last two instructions have the same single
3610 size. But nevertheless, you should guarantee the above two conditions.
3612 We could fix this so that single-instruction expansions correctly
3613 terminate when they can't handle the range, but the error messages are
3614 worse, and it actually turns out that in every case but one (18-bit wide
3615 branches), you need a multi-instruction expansion to get the full range
3616 anyway. And because 18-bit branches are handled identically to 15-bit
3617 branches, there isn't any point in changing it. */
3620 xg_assembly_relax (IStack
*istack
,
3623 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3624 offsetT pc_offset
, /* offset in fragment */
3625 int min_steps
, /* minimum conversion steps */
3626 long stretch
) /* number of bytes stretched so far */
3628 int steps_taken
= 0;
3630 /* Some of its immeds don't fit. Try to build a relaxed version.
3631 This may go through a couple of stages of single instruction
3632 transformations before we get there. */
3634 TInsn single_target
;
3636 int lateral_steps
= 0;
3637 int istack_size
= istack
->ninsn
;
3639 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3640 && steps_taken
>= min_steps
)
3642 istack_push (istack
, insn
);
3645 current_insn
= *insn
;
3647 /* Walk through all of the single instruction expansions. */
3648 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3651 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3654 if (steps_taken
>= min_steps
)
3656 istack_push (istack
, &single_target
);
3660 current_insn
= single_target
;
3663 /* Now check for a multi-instruction expansion. */
3664 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3666 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3669 if (steps_taken
>= min_steps
)
3671 istack_push (istack
, ¤t_insn
);
3676 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3678 if (steps_taken
>= min_steps
)
3682 istack
->ninsn
= istack_size
;
3685 /* It's not going to work -- use the original. */
3686 istack_push (istack
, insn
);
3692 xg_finish_frag (char *last_insn
,
3693 enum xtensa_relax_statesE frag_state
,
3694 enum xtensa_relax_statesE slot0_state
,
3696 bfd_boolean is_insn
)
3698 /* Finish off this fragment so that it has at LEAST the desired
3699 max_growth. If it doesn't fit in this fragment, close this one
3700 and start a new one. In either case, return a pointer to the
3701 beginning of the growth area. */
3705 frag_grow (max_growth
);
3706 old_frag
= frag_now
;
3708 frag_now
->fr_opcode
= last_insn
;
3710 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3712 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3713 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3715 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3716 xtensa_set_frag_assembly_state (frag_now
);
3718 /* Just to make sure that we did not split it up. */
3719 gas_assert (old_frag
->fr_next
== frag_now
);
3723 /* Return TRUE if the target frag is one of the next non-empty frags. */
3726 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3731 for (; fragP
; fragP
= fragP
->fr_next
)
3733 if (fragP
== target
)
3735 if (fragP
->fr_fix
!= 0)
3737 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3739 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3740 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3742 if (fragP
->fr_type
== rs_space
)
3750 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3752 xtensa_isa isa
= xtensa_default_isa
;
3754 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3759 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3760 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3763 for (i
= 0; i
< num_ops
; i
++)
3765 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3771 if (target_op
== -1)
3774 if (insn
->ntok
<= target_op
)
3777 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3780 sym
= insn
->tok
[target_op
].X_add_symbol
;
3784 if (insn
->tok
[target_op
].X_add_number
!= 0)
3787 target_frag
= symbol_get_frag (sym
);
3788 if (target_frag
== NULL
)
3791 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3792 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3800 xg_add_branch_and_loop_targets (TInsn
*insn
)
3802 xtensa_isa isa
= xtensa_default_isa
;
3803 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3805 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3808 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3809 && insn
->tok
[i
].X_op
== O_symbol
)
3810 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3814 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3815 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3819 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3821 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3822 && insn
->tok
[i
].X_op
== O_symbol
)
3824 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3825 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3826 if (S_IS_DEFINED (sym
))
3827 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3834 /* Return FALSE if no error. */
3837 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3842 switch (instr_spec
->typ
)
3845 new_insn
->insn_type
= ITYPE_INSN
;
3846 new_insn
->opcode
= instr_spec
->opcode
;
3848 case INSTR_LITERAL_DEF
:
3849 new_insn
->insn_type
= ITYPE_LITERAL
;
3850 new_insn
->opcode
= XTENSA_UNDEFINED
;
3852 case INSTR_LABEL_DEF
:
3855 new_insn
->is_specific_opcode
= FALSE
;
3856 new_insn
->debug_line
= old_insn
->debug_line
;
3857 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3859 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3862 const expressionS
*src_exp
;
3868 /* The expression must be the constant. */
3869 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3870 exp
= &new_insn
->tok
[b_op
->op_num
];
3871 set_expr_const (exp
, b_op
->op_data
);
3875 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3876 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3877 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3878 exp
= &new_insn
->tok
[b_op
->op_num
];
3879 copy_expr (exp
, src_exp
);
3884 as_bad (_("can't handle generation of literal/labels yet"));
3888 as_bad (_("can't handle undefined OP TYPE"));
3893 new_insn
->ntok
= num_ops
;
3898 /* Return TRUE if it was simplified. */
3901 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3903 TransitionRule
*rule
;
3904 BuildInstr
*insn_spec
;
3906 if (old_insn
->is_specific_opcode
|| !density_supported
)
3909 rule
= xg_instruction_match (old_insn
);
3913 insn_spec
= rule
->to_instr
;
3914 /* There should only be one. */
3915 gas_assert (insn_spec
!= NULL
);
3916 gas_assert (insn_spec
->next
== NULL
);
3917 if (insn_spec
->next
!= NULL
)
3920 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3926 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3927 l32i.n. (2) Check the number of operands. (3) Place the instruction
3928 tokens into the stack or relax it and place multiple
3929 instructions/literals onto the stack. Return FALSE if no error. */
3932 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3936 bfd_boolean do_expand
;
3938 tinsn_init (&new_insn
);
3940 /* Narrow it if we can. xg_simplify_insn now does all the
3941 appropriate checking (e.g., for the density option). */
3942 if (xg_simplify_insn (orig_insn
, &new_insn
))
3943 orig_insn
= &new_insn
;
3945 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3947 if (orig_insn
->ntok
< noperands
)
3949 as_bad (_("found %d operands for '%s': Expected %d"),
3951 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3955 if (orig_insn
->ntok
> noperands
)
3956 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3958 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3961 /* If there are not enough operands, we will assert above. If there
3962 are too many, just cut out the extras here. */
3963 orig_insn
->ntok
= noperands
;
3965 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3968 /* Special case for extui opcode which has constraints not handled
3969 by the ordinary operand encoding checks. The number of operands
3970 and related syntax issues have already been checked. */
3971 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3973 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3974 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3975 if (shiftimm
+ maskimm
> 32)
3977 as_bad (_("immediate operands sum to greater than 32"));
3982 /* If the instruction will definitely need to be relaxed, it is better
3983 to expand it now for better scheduling. Decide whether to expand
3985 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3987 /* Calls should be expanded to longcalls only in the backend relaxation
3988 so that the assembly scheduler will keep the L32R/CALLX instructions
3990 if (is_direct_call_opcode (orig_insn
->opcode
))
3993 if (tinsn_has_symbolic_operands (orig_insn
))
3995 /* The values of symbolic operands are not known yet, so only expand
3996 now if an operand is "complex" (e.g., difference of symbols) and
3997 will have to be stored as a literal regardless of the value. */
3998 if (!tinsn_has_complex_operands (orig_insn
))
4001 else if (xg_immeds_fit (orig_insn
))
4005 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4007 istack_push (istack
, orig_insn
);
4013 /* Return TRUE if the section flags are marked linkonce
4014 or the name is .gnu.linkonce.*. */
4016 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4019 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4021 flagword flags
, link_once_flags
;
4023 flags
= bfd_get_section_flags (abfd
, sec
);
4024 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4026 /* Flags might not be set yet. */
4027 if (!link_once_flags
4028 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4029 link_once_flags
= SEC_LINK_ONCE
;
4031 return (link_once_flags
!= 0);
4036 xtensa_add_literal_sym (symbolS
*sym
)
4040 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4042 l
->next
= literal_syms
;
4048 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4050 static int lit_num
= 0;
4051 static char name
[256];
4054 sprintf (name
, ".L_lit_sym%d", lit_num
);
4056 /* Create a local symbol. If it is in a linkonce section, we have to
4057 be careful to make sure that if it is used in a relocation that the
4058 symbol will be in the output file. */
4059 if (get_is_linkonce_section (stdoutput
, sec
))
4061 symbolP
= symbol_new (name
, sec
, 0, frag
);
4062 S_CLEAR_EXTERNAL (symbolP
);
4063 /* symbolP->local = 1; */
4066 symbolP
= symbol_new (name
, sec
, 0, frag
);
4068 xtensa_add_literal_sym (symbolP
);
4075 /* Currently all literals that are generated here are 32-bit L32R targets. */
4078 xg_assemble_literal (/* const */ TInsn
*insn
)
4081 symbolS
*lit_sym
= NULL
;
4082 bfd_reloc_code_real_type reloc
;
4083 bfd_boolean pcrel
= FALSE
;
4086 /* size = 4 for L32R. It could easily be larger when we move to
4087 larger constants. Add a parameter later. */
4088 offsetT litsize
= 4;
4089 offsetT litalign
= 2; /* 2^2 = 4 */
4090 expressionS saved_loc
;
4091 expressionS
* emit_val
;
4093 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4095 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4096 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4098 xtensa_switch_to_literal_fragment (&state
);
4100 emit_val
= &insn
->tok
[0];
4101 if (emit_val
->X_op
== O_big
)
4103 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4106 /* This happens when someone writes a "movi a2, big_number". */
4107 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4108 _("invalid immediate"));
4109 xtensa_restore_emit_state (&state
);
4114 /* Force a 4-byte align here. Note that this opens a new frag, so all
4115 literals done with this function have a frag to themselves. That's
4116 important for the way text section literals work. */
4117 frag_align (litalign
, 0, 0);
4118 record_alignment (now_seg
, litalign
);
4120 switch (emit_val
->X_op
)
4130 p
= frag_more (litsize
);
4131 xtensa_set_frag_assembly_state (frag_now
);
4132 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4133 if (emit_val
->X_add_symbol
)
4134 emit_val
->X_op
= O_symbol
;
4136 emit_val
->X_op
= O_constant
;
4137 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4138 litsize
, emit_val
, pcrel
, reloc
);
4142 emit_expr (emit_val
, litsize
);
4146 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4147 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4148 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4149 lit_sym
= frag_now
->fr_symbol
;
4152 xtensa_restore_emit_state (&state
);
4158 xg_assemble_literal_space (/* const */ int size
, int slot
)
4161 /* We might have to do something about this alignment. It only
4162 takes effect if something is placed here. */
4163 offsetT litalign
= 2; /* 2^2 = 4 */
4164 fragS
*lit_saved_frag
;
4166 gas_assert (size
% 4 == 0);
4168 xtensa_switch_to_literal_fragment (&state
);
4170 /* Force a 4-byte align here. */
4171 frag_align (litalign
, 0, 0);
4172 record_alignment (now_seg
, litalign
);
4176 lit_saved_frag
= frag_now
;
4177 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4178 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4179 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4182 xtensa_restore_emit_state (&state
);
4183 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4187 /* Put in a fixup record based on the opcode.
4188 Return TRUE on success. */
4191 xg_add_opcode_fix (TInsn
*tinsn
,
4199 xtensa_opcode opcode
= tinsn
->opcode
;
4200 bfd_reloc_code_real_type reloc
;
4201 reloc_howto_type
*howto
;
4205 reloc
= BFD_RELOC_NONE
;
4207 /* First try the special cases for "alternate" relocs. */
4208 if (opcode
== xtensa_l32r_opcode
)
4210 if (fragP
->tc_frag_data
.use_absolute_literals
)
4211 reloc
= encode_alt_reloc (slot
);
4213 else if (opcode
== xtensa_const16_opcode
)
4215 if (exp
->X_op
== O_lo16
)
4217 reloc
= encode_reloc (slot
);
4218 exp
->X_op
= O_symbol
;
4220 else if (exp
->X_op
== O_hi16
)
4222 reloc
= encode_alt_reloc (slot
);
4223 exp
->X_op
= O_symbol
;
4227 if (opnum
!= get_relaxable_immed (opcode
))
4229 as_bad (_("invalid relocation for operand %i of '%s'"),
4230 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4234 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4235 into the symbol table where the generic portions of the assembler
4236 won't know what to do with them. */
4237 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4239 as_bad (_("invalid expression for operand %i of '%s'"),
4240 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4244 /* Next try the generic relocs. */
4245 if (reloc
== BFD_RELOC_NONE
)
4246 reloc
= encode_reloc (slot
);
4247 if (reloc
== BFD_RELOC_NONE
)
4249 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4253 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4256 as_bad (_("undefined symbol for opcode \"%s\""),
4257 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4261 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4262 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4263 howto
->pc_relative
, reloc
);
4264 the_fix
->fx_no_overflow
= 1;
4265 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4266 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4267 the_fix
->tc_fix_data
.slot
= slot
;
4274 xg_emit_insn_to_buf (TInsn
*tinsn
,
4278 bfd_boolean build_fix
)
4280 static xtensa_insnbuf insnbuf
= NULL
;
4281 bfd_boolean has_symbolic_immed
= FALSE
;
4282 bfd_boolean ok
= TRUE
;
4285 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4287 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4288 if (has_symbolic_immed
&& build_fix
)
4291 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4292 int slot
= xg_get_single_slot (tinsn
->opcode
);
4293 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4294 expressionS
*exp
= &tinsn
->tok
[opnum
];
4296 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4299 fragP
->tc_frag_data
.is_insn
= TRUE
;
4300 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4301 (unsigned char *) buf
, 0);
4307 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4309 symbolS
*sym
= get_special_literal_symbol ();
4313 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4314 for (i
= 0; i
< insn
->ntok
; i
++)
4315 if (insn
->tok
[i
].X_add_symbol
== sym
)
4316 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4322 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4324 symbolS
*sym
= get_special_label_symbol ();
4326 for (i
= 0; i
< insn
->ntok
; i
++)
4327 if (insn
->tok
[i
].X_add_symbol
== sym
)
4328 insn
->tok
[i
].X_add_symbol
= label_sym
;
4333 /* Return TRUE if the instruction can write to the specified
4334 integer register. */
4337 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4341 xtensa_isa isa
= xtensa_default_isa
;
4343 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4345 for (i
= 0; i
< num_ops
; i
++)
4348 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4349 if ((inout
== 'o' || inout
== 'm')
4350 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4352 xtensa_regfile opnd_rf
=
4353 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4354 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4356 if ((insn
->tok
[i
].X_op
== O_register
)
4357 && (insn
->tok
[i
].X_add_number
== regnum
))
4367 is_bad_loopend_opcode (const TInsn
*tinsn
)
4369 xtensa_opcode opcode
= tinsn
->opcode
;
4371 if (opcode
== XTENSA_UNDEFINED
)
4374 if (opcode
== xtensa_call0_opcode
4375 || opcode
== xtensa_callx0_opcode
4376 || opcode
== xtensa_call4_opcode
4377 || opcode
== xtensa_callx4_opcode
4378 || opcode
== xtensa_call8_opcode
4379 || opcode
== xtensa_callx8_opcode
4380 || opcode
== xtensa_call12_opcode
4381 || opcode
== xtensa_callx12_opcode
4382 || opcode
== xtensa_isync_opcode
4383 || opcode
== xtensa_ret_opcode
4384 || opcode
== xtensa_ret_n_opcode
4385 || opcode
== xtensa_retw_opcode
4386 || opcode
== xtensa_retw_n_opcode
4387 || opcode
== xtensa_waiti_opcode
4388 || opcode
== xtensa_rsr_lcount_opcode
)
4395 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4396 This allows the debugger to add unaligned labels.
4397 Also, the assembler generates stabs labels that need
4398 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4401 is_unaligned_label (symbolS
*sym
)
4403 const char *name
= S_GET_NAME (sym
);
4404 static size_t fake_size
= 0;
4408 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4411 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4413 fake_size
= strlen (FAKE_LABEL_NAME
);
4416 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4417 && (name
[fake_size
] == 'F'
4418 || name
[fake_size
] == 'L'
4419 || (name
[fake_size
] == 'e'
4420 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4428 next_non_empty_frag (const fragS
*fragP
)
4430 fragS
*next_fragP
= fragP
->fr_next
;
4432 /* Sometimes an empty will end up here due storage allocation issues.
4433 So we have to skip until we find something legit. */
4434 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4435 next_fragP
= next_fragP
->fr_next
;
4437 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4445 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4447 xtensa_opcode out_opcode
;
4448 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4450 if (next_fragP
== NULL
)
4453 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4454 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4456 *opcode
= out_opcode
;
4464 frag_format_size (const fragS
*fragP
)
4466 static xtensa_insnbuf insnbuf
= NULL
;
4467 xtensa_isa isa
= xtensa_default_isa
;
4472 insnbuf
= xtensa_insnbuf_alloc (isa
);
4475 return XTENSA_UNDEFINED
;
4477 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4478 (unsigned char *) fragP
->fr_literal
, 0);
4480 fmt
= xtensa_format_decode (isa
, insnbuf
);
4481 if (fmt
== XTENSA_UNDEFINED
)
4482 return XTENSA_UNDEFINED
;
4483 fmt_size
= xtensa_format_length (isa
, fmt
);
4485 /* If the next format won't be changing due to relaxation, just
4486 return the length of the first format. */
4487 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4490 /* If during relaxation we have to pull an instruction out of a
4491 multi-slot instruction, we will return the more conservative
4492 number. This works because alignment on bigger instructions
4493 is more restrictive than alignment on smaller instructions.
4494 This is more conservative than we would like, but it happens
4497 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4500 /* If we aren't doing one of our own relaxations or it isn't
4501 slot-based, then the insn size won't change. */
4502 if (fragP
->fr_type
!= rs_machine_dependent
)
4504 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4507 /* If an instruction is about to grow, return the longer size. */
4508 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4509 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4510 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4512 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4513 instruction in the relaxed version is of length 3. (The case
4514 where we have to pull the instruction out of a FLIX bundle
4515 is handled conservatively above.) However, frags with opcodes
4516 that are expanding to wide branches end up having formats that
4517 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4518 we can't tell directly what format the relaxer picked. This
4519 is a wart in the design of the relaxer that should someday be
4520 fixed, but would require major changes, or at least should
4521 be accompanied by major changes to make use of that data.
4523 In any event, we can tell that we are expanding from a single-slot
4524 three-byte format to a wider one with the logic below. */
4526 if (fmt_size
<= 3 && fragP
->tc_frag_data
.text_expansion
[0] != 3)
4527 return 3 + fragP
->tc_frag_data
.text_expansion
[0];
4532 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4533 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4540 next_frag_format_size (const fragS
*fragP
)
4542 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4543 return frag_format_size (next_fragP
);
4547 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4548 required two-byte instructions to be treated as three-byte instructions
4549 for loop instruction alignment. This restriction was removed beginning
4550 with Xtensa LX. Now the only requirement on loop instruction alignment
4551 is that the first instruction of the loop must appear at an address that
4552 does not cross a fetch boundary. */
4555 get_loop_align_size (int insn_size
)
4557 if (insn_size
== XTENSA_UNDEFINED
)
4558 return xtensa_fetch_width
;
4560 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4567 /* If the next legit fragment is an end-of-loop marker,
4568 switch its state so it will instantiate a NOP. */
4571 update_next_frag_state (fragS
*fragP
)
4573 fragS
*next_fragP
= fragP
->fr_next
;
4574 fragS
*new_target
= NULL
;
4578 /* We are guaranteed there will be one of these... */
4579 while (!(next_fragP
->fr_type
== rs_machine_dependent
4580 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4581 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4582 next_fragP
= next_fragP
->fr_next
;
4584 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4585 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4586 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4588 /* ...and one of these. */
4589 new_target
= next_fragP
->fr_next
;
4590 while (!(new_target
->fr_type
== rs_machine_dependent
4591 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4592 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4593 new_target
= new_target
->fr_next
;
4595 gas_assert (new_target
->fr_type
== rs_machine_dependent
4596 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4597 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4600 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4602 if (next_fragP
->fr_type
== rs_machine_dependent
4603 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4605 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4609 next_fragP
= next_fragP
->fr_next
;
4615 next_frag_is_branch_target (const fragS
*fragP
)
4617 /* Sometimes an empty will end up here due to storage allocation issues,
4618 so we have to skip until we find something legit. */
4619 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4621 if (fragP
->tc_frag_data
.is_branch_target
)
4623 if (fragP
->fr_fix
!= 0)
4631 next_frag_is_loop_target (const fragS
*fragP
)
4633 /* Sometimes an empty will end up here due storage allocation issues.
4634 So we have to skip until we find something legit. */
4635 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4637 if (fragP
->tc_frag_data
.is_loop_target
)
4639 if (fragP
->fr_fix
!= 0)
4647 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4649 const fragS
*next_fragp
= fragp
->fr_next
;
4650 xtensa_opcode next_opcode
;
4652 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4655 /* Sometimes an empty will end up here due to storage allocation issues,
4656 so we have to skip until we find something legit. */
4657 while (next_fragp
->fr_fix
== 0)
4658 next_fragp
= next_fragp
->fr_next
;
4660 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4663 /* There is some implicit knowledge encoded in here.
4664 The LOOP instructions that are NOT RELAX_IMMED have
4665 been relaxed. Note that we can assume that the LOOP
4666 instruction is in slot 0 because loops aren't bundleable. */
4667 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4668 return get_expanded_loop_offset (next_opcode
);
4674 /* Mark a location where we can later insert literal frags. Update
4675 the section's literal_pool_loc, so subsequent literals can be
4676 placed nearest to their use. */
4679 xtensa_mark_literal_pool_location (void)
4681 /* Any labels pointing to the current location need
4682 to be adjusted to after the literal pool. */
4684 fragS
*pool_location
;
4686 if (use_literal_section
)
4689 /* We stash info in these frags so we can later move the literal's
4690 fixes into this frchain's fix list. */
4691 pool_location
= frag_now
;
4692 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4693 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4694 frag_variant (rs_machine_dependent
, 0, 0,
4695 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4696 xtensa_set_frag_assembly_state (frag_now
);
4697 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4698 frag_variant (rs_machine_dependent
, 0, 0,
4699 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4700 xtensa_set_frag_assembly_state (frag_now
);
4702 /* Now put a frag into the literal pool that points to this location. */
4703 set_literal_pool_location (now_seg
, pool_location
);
4704 xtensa_switch_to_non_abs_literal_fragment (&s
);
4705 frag_align (2, 0, 0);
4706 record_alignment (now_seg
, 2);
4708 /* Close whatever frag is there. */
4709 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4710 xtensa_set_frag_assembly_state (frag_now
);
4711 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4712 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4713 xtensa_restore_emit_state (&s
);
4714 xtensa_set_frag_assembly_state (frag_now
);
4718 /* Build a nop of the correct size into tinsn. */
4721 build_nop (TInsn
*tinsn
, int size
)
4727 tinsn
->opcode
= xtensa_nop_n_opcode
;
4729 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4730 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4734 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4736 tinsn
->opcode
= xtensa_or_opcode
;
4737 set_expr_const (&tinsn
->tok
[0], 1);
4738 set_expr_const (&tinsn
->tok
[1], 1);
4739 set_expr_const (&tinsn
->tok
[2], 1);
4743 tinsn
->opcode
= xtensa_nop_opcode
;
4745 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4750 /* Assemble a NOP of the requested size in the buffer. User must have
4751 allocated "buf" with at least "size" bytes. */
4754 assemble_nop (int size
, char *buf
)
4756 static xtensa_insnbuf insnbuf
= NULL
;
4759 build_nop (&tinsn
, size
);
4762 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4764 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4765 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4766 (unsigned char *) buf
, 0);
4770 /* Return the number of bytes for the offset of the expanded loop
4771 instruction. This should be incorporated into the relaxation
4772 specification but is hard-coded here. This is used to auto-align
4773 the loop instruction. It is invalid to call this function if the
4774 configuration does not have loops or if the opcode is not a loop
4778 get_expanded_loop_offset (xtensa_opcode opcode
)
4780 /* This is the OFFSET of the loop instruction in the expanded loop.
4781 This MUST correspond directly to the specification of the loop
4782 expansion. It will be validated on fragment conversion. */
4783 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4784 if (opcode
== xtensa_loop_opcode
)
4786 if (opcode
== xtensa_loopnez_opcode
)
4788 if (opcode
== xtensa_loopgtz_opcode
)
4790 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4796 get_literal_pool_location (segT seg
)
4798 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4803 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4805 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4809 /* Set frag assembly state should be called when a new frag is
4810 opened and after a frag has been closed. */
4813 xtensa_set_frag_assembly_state (fragS
*fragP
)
4815 if (!density_supported
)
4816 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4818 /* This function is called from subsegs_finish, which is called
4819 after xtensa_end, so we can't use "use_transform" or
4820 "use_schedule" here. */
4821 if (!directive_state
[directive_transform
])
4822 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4823 if (directive_state
[directive_longcalls
])
4824 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4825 fragP
->tc_frag_data
.use_absolute_literals
=
4826 directive_state
[directive_absolute_literals
];
4827 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4832 relaxable_section (asection
*sec
)
4834 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4835 && strcmp (sec
->name
, ".eh_frame") != 0);
4840 xtensa_mark_frags_for_org (void)
4844 /* Walk over each fragment of all of the current segments. If we find
4845 a .org frag in any of the segments, mark all frags prior to it as
4846 "no transform", which will prevent linker optimizations from messing
4847 up the .org distance. This should be done after
4848 xtensa_find_unmarked_state_frags, because we don't want to worry here
4849 about that function trashing the data we save here. */
4851 for (seclist
= &stdoutput
->sections
;
4852 seclist
&& *seclist
;
4853 seclist
= &(*seclist
)->next
)
4855 segT sec
= *seclist
;
4856 segment_info_type
*seginfo
;
4859 flags
= bfd_get_section_flags (stdoutput
, sec
);
4860 if (flags
& SEC_DEBUGGING
)
4862 if (!(flags
& SEC_ALLOC
))
4865 seginfo
= seg_info (sec
);
4866 if (seginfo
&& seginfo
->frchainP
)
4868 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4869 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4870 fragP
= fragP
->fr_next
)
4872 /* cvt_frag_to_fill has changed the fr_type of org frags to
4873 rs_fill, so use the value as cached in rs_subtype here. */
4874 if (fragP
->fr_subtype
== RELAX_ORG
)
4876 while (last_fragP
!= fragP
->fr_next
)
4878 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4879 last_fragP
= last_fragP
->fr_next
;
4889 xtensa_find_unmarked_state_frags (void)
4893 /* Walk over each fragment of all of the current segments. For each
4894 unmarked fragment, mark it with the same info as the previous
4896 for (seclist
= &stdoutput
->sections
;
4897 seclist
&& *seclist
;
4898 seclist
= &(*seclist
)->next
)
4900 segT sec
= *seclist
;
4901 segment_info_type
*seginfo
;
4904 flags
= bfd_get_section_flags (stdoutput
, sec
);
4905 if (flags
& SEC_DEBUGGING
)
4907 if (!(flags
& SEC_ALLOC
))
4910 seginfo
= seg_info (sec
);
4911 if (seginfo
&& seginfo
->frchainP
)
4913 fragS
*last_fragP
= 0;
4914 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4915 fragP
= fragP
->fr_next
)
4917 if (fragP
->fr_fix
!= 0
4918 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4920 if (last_fragP
== 0)
4922 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4923 _("assembly state not set for first frag in section %s"),
4928 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4929 fragP
->tc_frag_data
.is_no_density
=
4930 last_fragP
->tc_frag_data
.is_no_density
;
4931 fragP
->tc_frag_data
.is_no_transform
=
4932 last_fragP
->tc_frag_data
.is_no_transform
;
4933 fragP
->tc_frag_data
.use_longcalls
=
4934 last_fragP
->tc_frag_data
.use_longcalls
;
4935 fragP
->tc_frag_data
.use_absolute_literals
=
4936 last_fragP
->tc_frag_data
.use_absolute_literals
;
4939 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4948 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4950 void *unused ATTRIBUTE_UNUSED
)
4952 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4953 segment_info_type
*seginfo
= seg_info (sec
);
4954 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4956 if (flags
& SEC_CODE
)
4958 xtensa_isa isa
= xtensa_default_isa
;
4959 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4960 while (frag
!= NULL
)
4962 if (frag
->tc_frag_data
.is_branch_target
)
4965 addressT branch_align
, frag_addr
;
4968 xtensa_insnbuf_from_chars
4969 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4970 fmt
= xtensa_format_decode (isa
, insnbuf
);
4971 op_size
= xtensa_format_length (isa
, fmt
);
4972 branch_align
= 1 << branch_align_power (sec
);
4973 frag_addr
= frag
->fr_address
% branch_align
;
4974 if (frag_addr
+ op_size
> branch_align
)
4975 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4976 _("unaligned branch target: %d bytes at 0x%lx"),
4977 op_size
, (long) frag
->fr_address
);
4979 frag
= frag
->fr_next
;
4981 xtensa_insnbuf_free (isa
, insnbuf
);
4987 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4989 void *unused ATTRIBUTE_UNUSED
)
4991 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4992 segment_info_type
*seginfo
= seg_info (sec
);
4993 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4994 xtensa_isa isa
= xtensa_default_isa
;
4996 if (flags
& SEC_CODE
)
4998 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4999 while (frag
!= NULL
)
5001 if (frag
->tc_frag_data
.is_first_loop_insn
)
5007 xtensa_insnbuf_from_chars
5008 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5009 fmt
= xtensa_format_decode (isa
, insnbuf
);
5010 op_size
= xtensa_format_length (isa
, fmt
);
5011 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5013 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5014 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5015 _("unaligned loop: %d bytes at 0x%lx"),
5016 op_size
, (long) frag
->fr_address
);
5018 frag
= frag
->fr_next
;
5020 xtensa_insnbuf_free (isa
, insnbuf
);
5026 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5028 xtensa_isa isa
= xtensa_default_isa
;
5029 static xtensa_insnbuf insnbuf
= NULL
;
5030 static xtensa_insnbuf slotbuf
= NULL
;
5033 bfd_boolean alt_reloc
;
5034 xtensa_opcode opcode
;
5035 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5037 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5039 as_fatal (_("unexpected fix"));
5043 insnbuf
= xtensa_insnbuf_alloc (isa
);
5044 slotbuf
= xtensa_insnbuf_alloc (isa
);
5047 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5048 fmt
= xtensa_format_decode (isa
, insnbuf
);
5049 if (fmt
== XTENSA_UNDEFINED
)
5050 as_fatal (_("undecodable fix"));
5051 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5052 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5053 if (opcode
== XTENSA_UNDEFINED
)
5054 as_fatal (_("undecodable fix"));
5056 /* CONST16 immediates are not PC-relative, despite the fact that we
5057 reuse the normal PC-relative operand relocations for the low part
5058 of a CONST16 operand. */
5059 if (opcode
== xtensa_const16_opcode
)
5062 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5063 get_relaxable_immed (opcode
), val
,
5064 fixP
->fx_file
, fixP
->fx_line
);
5066 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5067 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5073 /* External Functions and Other GAS Hooks. */
5076 xtensa_target_format (void)
5078 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5083 xtensa_file_arch_init (bfd
*abfd
)
5085 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5090 md_number_to_chars (char *buf
, valueT val
, int n
)
5092 if (target_big_endian
)
5093 number_to_chars_bigendian (buf
, val
, n
);
5095 number_to_chars_littleendian (buf
, val
, n
);
5099 /* This function is called once, at assembler startup time. It should
5100 set up all the tables, etc. that the MD part of the assembler will
5106 segT current_section
= now_seg
;
5107 int current_subsec
= now_subseg
;
5111 xtensa_default_isa
= xtensa_isa_init (0, 0);
5112 isa
= xtensa_default_isa
;
5116 /* Set up the literal sections. */
5117 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5119 subseg_set (current_section
, current_subsec
);
5121 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5122 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5123 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5124 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5125 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5126 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5127 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5128 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5129 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5130 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5131 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5132 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5133 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5134 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5135 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5136 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5137 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5138 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5139 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5140 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5141 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5142 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5143 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5144 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5145 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5146 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5147 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5148 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5149 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5150 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5151 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5153 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5155 int format_slots
= xtensa_format_num_slots (isa
, i
);
5156 if (format_slots
> config_max_slots
)
5157 config_max_slots
= format_slots
;
5160 xg_init_vinsn (&cur_vinsn
);
5162 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5164 init_op_placement_info_table ();
5166 /* Set up the assembly state. */
5167 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5168 xtensa_set_frag_assembly_state (frag_now
);
5172 /* TC_INIT_FIX_DATA hook */
5175 xtensa_init_fix_data (fixS
*x
)
5177 x
->tc_fix_data
.slot
= 0;
5178 x
->tc_fix_data
.X_add_symbol
= NULL
;
5179 x
->tc_fix_data
.X_add_number
= 0;
5183 /* tc_frob_label hook */
5186 xtensa_frob_label (symbolS
*sym
)
5190 if (cur_vinsn
.inside_bundle
)
5192 as_bad (_("labels are not valid inside bundles"));
5196 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5198 /* Since the label was already attached to a frag associated with the
5199 previous basic block, it now needs to be reset to the current frag. */
5200 symbol_set_frag (sym
, frag_now
);
5201 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5203 if (generating_literals
)
5204 xtensa_add_literal_sym (sym
);
5206 xtensa_add_insn_label (sym
);
5208 if (symbol_get_tc (sym
)->is_loop_target
)
5210 if ((get_last_insn_flags (now_seg
, now_subseg
)
5211 & FLAG_IS_BAD_LOOPEND
) != 0)
5212 as_bad (_("invalid last instruction for a zero-overhead loop"));
5214 xtensa_set_frag_assembly_state (frag_now
);
5215 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5216 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5218 xtensa_set_frag_assembly_state (frag_now
);
5219 xtensa_move_labels (frag_now
, 0);
5222 /* No target aligning in the absolute section. */
5223 if (now_seg
!= absolute_section
5224 && !is_unaligned_label (sym
)
5225 && !generating_literals
)
5227 xtensa_set_frag_assembly_state (frag_now
);
5229 if (do_align_targets ())
5230 frag_var (rs_machine_dependent
, 0, (int) freq
,
5231 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5232 frag_now
->fr_offset
, NULL
);
5234 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5235 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5236 xtensa_set_frag_assembly_state (frag_now
);
5237 xtensa_move_labels (frag_now
, 0);
5240 /* We need to mark the following properties even if we aren't aligning. */
5242 /* If the label is already known to be a branch target, i.e., a
5243 forward branch, mark the frag accordingly. Backward branches
5244 are handled by xg_add_branch_and_loop_targets. */
5245 if (symbol_get_tc (sym
)->is_branch_target
)
5246 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5248 /* Loops only go forward, so they can be identified here. */
5249 if (symbol_get_tc (sym
)->is_loop_target
)
5250 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5252 dwarf2_emit_label (sym
);
5256 /* tc_unrecognized_line hook */
5259 xtensa_unrecognized_line (int ch
)
5264 if (cur_vinsn
.inside_bundle
== 0)
5266 /* PR8110: Cannot emit line number info inside a FLIX bundle
5267 when using --gstabs. Temporarily disable debug info. */
5268 generate_lineno_debug ();
5269 if (debug_type
== DEBUG_STABS
)
5271 xt_saved_debug_type
= debug_type
;
5272 debug_type
= DEBUG_NONE
;
5275 cur_vinsn
.inside_bundle
= 1;
5279 as_bad (_("extra opening brace"));
5285 if (cur_vinsn
.inside_bundle
)
5286 finish_vinsn (&cur_vinsn
);
5289 as_bad (_("extra closing brace"));
5294 as_bad (_("syntax error"));
5301 /* md_flush_pending_output hook */
5304 xtensa_flush_pending_output (void)
5306 /* This line fixes a bug where automatically generated gstabs info
5307 separates a function label from its entry instruction, ending up
5308 with the literal position between the function label and the entry
5309 instruction and crashing code. It only happens with --gstabs and
5310 --text-section-literals, and when several other obscure relaxation
5311 conditions are met. */
5312 if (outputting_stabs_line_debug
)
5315 if (cur_vinsn
.inside_bundle
)
5316 as_bad (_("missing closing brace"));
5318 /* If there is a non-zero instruction fragment, close it. */
5319 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5321 frag_wane (frag_now
);
5323 xtensa_set_frag_assembly_state (frag_now
);
5325 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5327 xtensa_clear_insn_labels ();
5331 /* We had an error while parsing an instruction. The string might look
5332 like this: "insn arg1, arg2 }". If so, we need to see the closing
5333 brace and reset some fields. Otherwise, the vinsn never gets closed
5334 and the num_slots field will grow past the end of the array of slots,
5335 and bad things happen. */
5338 error_reset_cur_vinsn (void)
5340 if (cur_vinsn
.inside_bundle
)
5342 if (*input_line_pointer
== '}'
5343 || *(input_line_pointer
- 1) == '}'
5344 || *(input_line_pointer
- 2) == '}')
5345 xg_clear_vinsn (&cur_vinsn
);
5351 md_assemble (char *str
)
5353 xtensa_isa isa
= xtensa_default_isa
;
5356 bfd_boolean has_underbar
= FALSE
;
5357 char *arg_strings
[MAX_INSN_ARGS
];
5359 TInsn orig_insn
; /* Original instruction from the input. */
5361 tinsn_init (&orig_insn
);
5363 /* Split off the opcode. */
5364 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5365 opname
= xmalloc (opnamelen
+ 1);
5366 memcpy (opname
, str
, opnamelen
);
5367 opname
[opnamelen
] = '\0';
5369 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5372 as_bad (_("syntax error"));
5376 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5379 /* Check for an underbar prefix. */
5382 has_underbar
= TRUE
;
5386 orig_insn
.insn_type
= ITYPE_INSN
;
5388 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5389 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5391 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5392 extra argument and set the opcode to "CALLXn". */
5393 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5394 && strncasecmp (opname
, "callx", 5) == 0)
5396 unsigned long window_size
;
5399 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5400 if (suffix
!= opname
+ 5
5401 && (window_size
== 0
5404 || window_size
== 12)
5405 && strcasecmp (suffix
, ".tls") == 0)
5407 switch (window_size
)
5409 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5410 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5411 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5412 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5416 as_bad (_("wrong number of operands for '%s'"), opname
);
5419 bfd_reloc_code_real_type reloc
;
5420 char *old_input_line_pointer
;
5421 expressionS
*tok
= &orig_insn
.extra_arg
;
5424 old_input_line_pointer
= input_line_pointer
;
5425 input_line_pointer
= arg_strings
[num_args
- 1];
5427 t
= expression (tok
);
5428 if (tok
->X_op
== O_symbol
5429 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5430 == BFD_RELOC_XTENSA_TLS_CALL
))
5431 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5433 as_bad (_("bad relocation expression for '%s'"), opname
);
5435 input_line_pointer
= old_input_line_pointer
;
5441 /* Special case: Check for "j.l" psuedo op. */
5442 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5443 && strncasecmp (opname
, "j.l", 3) == 0)
5446 as_bad (_("wrong number of operands for '%s'"), opname
);
5449 char *old_input_line_pointer
;
5450 expressionS
*tok
= &orig_insn
.extra_arg
;
5452 old_input_line_pointer
= input_line_pointer
;
5453 input_line_pointer
= arg_strings
[num_args
- 1];
5455 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5456 input_line_pointer
= old_input_line_pointer
;
5459 orig_insn
.opcode
= xtensa_j_opcode
;
5463 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5465 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5466 if (fmt
== XTENSA_UNDEFINED
)
5468 as_bad (_("unknown opcode or format name '%s'"), opname
);
5469 error_reset_cur_vinsn ();
5472 if (!cur_vinsn
.inside_bundle
)
5474 as_bad (_("format names only valid inside bundles"));
5475 error_reset_cur_vinsn ();
5478 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5479 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5481 cur_vinsn
.format
= fmt
;
5482 free (has_underbar
? opname
- 1 : opname
);
5483 error_reset_cur_vinsn ();
5487 /* Parse the arguments. */
5488 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5490 as_bad (_("syntax error"));
5491 error_reset_cur_vinsn ();
5495 /* Free the opcode and argument strings, now that they've been parsed. */
5496 free (has_underbar
? opname
- 1 : opname
);
5498 while (num_args
-- > 0)
5499 free (arg_strings
[num_args
]);
5501 /* Get expressions for invisible operands. */
5502 if (get_invisible_operands (&orig_insn
))
5504 error_reset_cur_vinsn ();
5508 /* Check for the right number and type of arguments. */
5509 if (tinsn_check_arguments (&orig_insn
))
5511 error_reset_cur_vinsn ();
5515 /* Record the line number for each TInsn, because a FLIX bundle may be
5516 spread across multiple input lines and individual instructions may be
5517 moved around in some cases. */
5518 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5519 dwarf2_where (&orig_insn
.debug_line
);
5520 dwarf2_consume_line_info ();
5522 xg_add_branch_and_loop_targets (&orig_insn
);
5524 /* Check that immediate value for ENTRY is >= 16. */
5525 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5527 expressionS
*exp
= &orig_insn
.tok
[2];
5528 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5529 as_warn (_("entry instruction with stack decrement < 16"));
5533 assemble_tokens (opcode, tok, ntok);
5534 expand the tokens from the orig_insn into the
5535 stack of instructions that will not expand
5536 unless required at relaxation time. */
5538 if (!cur_vinsn
.inside_bundle
)
5539 emit_single_op (&orig_insn
);
5540 else /* We are inside a bundle. */
5542 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5543 cur_vinsn
.num_slots
++;
5544 if (*input_line_pointer
== '}'
5545 || *(input_line_pointer
- 1) == '}'
5546 || *(input_line_pointer
- 2) == '}')
5547 finish_vinsn (&cur_vinsn
);
5550 /* We've just emitted a new instruction so clear the list of labels. */
5551 xtensa_clear_insn_labels ();
5555 /* HANDLE_ALIGN hook */
5557 /* For a .align directive, we mark the previous block with the alignment
5558 information. This will be placed in the object file in the
5559 property section corresponding to this section. */
5562 xtensa_handle_align (fragS
*fragP
)
5565 && ! fragP
->tc_frag_data
.is_literal
5566 && (fragP
->fr_type
== rs_align
5567 || fragP
->fr_type
== rs_align_code
)
5568 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5569 && fragP
->fr_offset
> 0
5570 && now_seg
!= bss_section
)
5572 fragP
->tc_frag_data
.is_align
= TRUE
;
5573 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5576 if (fragP
->fr_type
== rs_align_test
)
5579 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5581 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5582 _("unaligned entry instruction"));
5585 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5586 fragP
->fr_subtype
= RELAX_ORG
;
5590 /* TC_FRAG_INIT hook */
5593 xtensa_frag_init (fragS
*frag
)
5595 xtensa_set_frag_assembly_state (frag
);
5600 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5606 /* Round up a section size to the appropriate boundary. */
5609 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5611 return size
; /* Byte alignment is fine. */
5616 md_pcrel_from (fixS
*fixP
)
5619 static xtensa_insnbuf insnbuf
= NULL
;
5620 static xtensa_insnbuf slotbuf
= NULL
;
5623 xtensa_opcode opcode
;
5626 xtensa_isa isa
= xtensa_default_isa
;
5627 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5628 bfd_boolean alt_reloc
;
5630 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5633 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5638 insnbuf
= xtensa_insnbuf_alloc (isa
);
5639 slotbuf
= xtensa_insnbuf_alloc (isa
);
5642 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5643 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5644 fmt
= xtensa_format_decode (isa
, insnbuf
);
5646 if (fmt
== XTENSA_UNDEFINED
)
5647 as_fatal (_("bad instruction format"));
5649 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5650 as_fatal (_("invalid relocation"));
5652 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5653 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5655 /* Check for "alternate" relocations (operand not specified). None
5656 of the current uses for these are really PC-relative. */
5657 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5659 if (opcode
!= xtensa_l32r_opcode
5660 && opcode
!= xtensa_const16_opcode
)
5661 as_fatal (_("invalid relocation for '%s' instruction"),
5662 xtensa_opcode_name (isa
, opcode
));
5666 opnum
= get_relaxable_immed (opcode
);
5668 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5669 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5671 as_bad_where (fixP
->fx_file
,
5673 _("invalid relocation for operand %d of '%s'"),
5674 opnum
, xtensa_opcode_name (isa
, opcode
));
5677 return 0 - opnd_value
;
5681 /* TC_FORCE_RELOCATION hook */
5684 xtensa_force_relocation (fixS
*fix
)
5686 switch (fix
->fx_r_type
)
5688 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5689 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5690 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5691 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5692 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5693 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5694 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5695 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5696 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5697 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5698 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5699 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5700 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5701 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5702 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5703 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5709 if (linkrelax
&& fix
->fx_addsy
5710 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5713 return generic_force_reloc (fix
);
5717 /* TC_VALIDATE_FIX_SUB hook */
5720 xtensa_validate_fix_sub (fixS
*fix
)
5722 segT add_symbol_segment
, sub_symbol_segment
;
5724 /* The difference of two symbols should be resolved by the assembler when
5725 linkrelax is not set. If the linker may relax the section containing
5726 the symbols, then an Xtensa DIFF relocation must be generated so that
5727 the linker knows to adjust the difference value. */
5728 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5731 /* Make sure both symbols are in the same segment, and that segment is
5732 "normal" and relaxable. If the segment is not "normal", then the
5733 fix is not valid. If the segment is not "relaxable", then the fix
5734 should have been handled earlier. */
5735 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5736 if (! SEG_NORMAL (add_symbol_segment
) ||
5737 ! relaxable_section (add_symbol_segment
))
5739 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5740 return (sub_symbol_segment
== add_symbol_segment
);
5744 /* NO_PSEUDO_DOT hook */
5746 /* This function has nothing to do with pseudo dots, but this is the
5747 nearest macro to where the check needs to take place. FIXME: This
5751 xtensa_check_inside_bundle (void)
5753 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5754 as_bad (_("directives are not valid inside bundles"));
5756 /* This function must always return FALSE because it is called via a
5757 macro that has nothing to do with bundling. */
5762 /* md_elf_section_change_hook */
5765 xtensa_elf_section_change_hook (void)
5767 /* Set up the assembly state. */
5768 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5769 xtensa_set_frag_assembly_state (frag_now
);
5773 /* tc_fix_adjustable hook */
5776 xtensa_fix_adjustable (fixS
*fixP
)
5778 /* We need the symbol name for the VTABLE entries. */
5779 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5780 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5787 /* tc_symbol_new_hook */
5789 symbolS
*expr_symbols
= NULL
;
5792 xtensa_symbol_new_hook (symbolS
*sym
)
5794 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5796 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5803 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5805 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5808 /* Subtracted symbols are only allowed for a few relocation types, and
5809 unless linkrelax is enabled, they should not make it to this point. */
5810 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5811 || fixP
->fx_r_type
== BFD_RELOC_16
5812 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5815 switch (fixP
->fx_r_type
)
5817 case BFD_RELOC_32_PCREL
:
5823 switch (fixP
->fx_r_type
)
5826 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5829 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5832 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5838 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5839 - S_GET_VALUE (fixP
->fx_subsy
));
5841 /* The difference value gets written out, and the DIFF reloc
5842 identifies the address of the subtracted symbol (i.e., the one
5843 with the lowest address). */
5845 fixP
->fx_offset
-= val
;
5846 fixP
->fx_subsy
= NULL
;
5848 else if (! fixP
->fx_addsy
)
5855 case BFD_RELOC_XTENSA_PLT
:
5856 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5857 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5860 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5861 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5862 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5863 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5864 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5865 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5866 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5869 case BFD_RELOC_XTENSA_SLOT0_OP
:
5870 case BFD_RELOC_XTENSA_SLOT1_OP
:
5871 case BFD_RELOC_XTENSA_SLOT2_OP
:
5872 case BFD_RELOC_XTENSA_SLOT3_OP
:
5873 case BFD_RELOC_XTENSA_SLOT4_OP
:
5874 case BFD_RELOC_XTENSA_SLOT5_OP
:
5875 case BFD_RELOC_XTENSA_SLOT6_OP
:
5876 case BFD_RELOC_XTENSA_SLOT7_OP
:
5877 case BFD_RELOC_XTENSA_SLOT8_OP
:
5878 case BFD_RELOC_XTENSA_SLOT9_OP
:
5879 case BFD_RELOC_XTENSA_SLOT10_OP
:
5880 case BFD_RELOC_XTENSA_SLOT11_OP
:
5881 case BFD_RELOC_XTENSA_SLOT12_OP
:
5882 case BFD_RELOC_XTENSA_SLOT13_OP
:
5883 case BFD_RELOC_XTENSA_SLOT14_OP
:
5886 /* Write the tentative value of a PC-relative relocation to a
5887 local symbol into the instruction. The value will be ignored
5888 by the linker, and it makes the object file disassembly
5889 readable when all branch targets are encoded in relocations. */
5891 gas_assert (fixP
->fx_addsy
);
5892 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5893 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5895 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5896 - md_pcrel_from (fixP
));
5897 (void) xg_apply_fix_value (fixP
, val
);
5900 else if (! fixP
->fx_addsy
)
5903 if (xg_apply_fix_value (fixP
, val
))
5908 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5909 case BFD_RELOC_XTENSA_TLS_FUNC
:
5910 case BFD_RELOC_XTENSA_TLS_ARG
:
5911 case BFD_RELOC_XTENSA_TLS_CALL
:
5912 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5913 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5914 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5915 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5916 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5917 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5918 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5919 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5920 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5921 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5922 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5923 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5924 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5925 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5926 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5927 /* These all need to be resolved at link-time. Do nothing now. */
5930 case BFD_RELOC_VTABLE_INHERIT
:
5931 case BFD_RELOC_VTABLE_ENTRY
:
5936 as_bad (_("unhandled local relocation fix %s"),
5937 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5943 md_atof (int type
, char *litP
, int *sizeP
)
5945 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5950 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5952 return total_frag_text_expansion (fragP
);
5956 /* Translate internal representation of relocation info to BFD target
5960 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5964 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5965 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5966 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5967 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5969 /* Make sure none of our internal relocations make it this far.
5970 They'd better have been fully resolved by this point. */
5971 gas_assert ((int) fixp
->fx_r_type
> 0);
5973 reloc
->addend
= fixp
->fx_offset
;
5975 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5976 if (reloc
->howto
== NULL
)
5978 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5979 _("cannot represent `%s' relocation in object file"),
5980 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5981 free (reloc
->sym_ptr_ptr
);
5986 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5987 as_fatal (_("internal error; cannot generate `%s' relocation"),
5988 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5994 /* Checks for resource conflicts between instructions. */
5996 /* The func unit stuff could be implemented as bit-vectors rather
5997 than the iterative approach here. If it ends up being too
5998 slow, we will switch it. */
6001 new_resource_table (void *data
,
6004 unit_num_copies_func uncf
,
6005 opcode_num_units_func onuf
,
6006 opcode_funcUnit_use_unit_func ouuf
,
6007 opcode_funcUnit_use_stage_func ousf
)
6010 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
6012 rt
->cycles
= cycles
;
6013 rt
->allocated_cycles
= cycles
;
6015 rt
->unit_num_copies
= uncf
;
6016 rt
->opcode_num_units
= onuf
;
6017 rt
->opcode_unit_use
= ouuf
;
6018 rt
->opcode_unit_stage
= ousf
;
6020 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6021 for (i
= 0; i
< cycles
; i
++)
6022 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6029 clear_resource_table (resource_table
*rt
)
6032 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6033 for (j
= 0; j
< rt
->num_units
; j
++)
6034 rt
->units
[i
][j
] = 0;
6038 /* We never shrink it, just fake it into thinking so. */
6041 resize_resource_table (resource_table
*rt
, int cycles
)
6045 rt
->cycles
= cycles
;
6046 if (cycles
<= rt
->allocated_cycles
)
6049 old_cycles
= rt
->allocated_cycles
;
6050 rt
->allocated_cycles
= cycles
;
6052 rt
->units
= xrealloc (rt
->units
,
6053 rt
->allocated_cycles
* sizeof (unsigned char *));
6054 for (i
= 0; i
< old_cycles
; i
++)
6055 rt
->units
[i
] = xrealloc (rt
->units
[i
],
6056 rt
->num_units
* sizeof (unsigned char));
6057 for (i
= old_cycles
; i
< cycles
; i
++)
6058 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6063 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6066 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6068 for (i
= 0; i
< uses
; i
++)
6070 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6071 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6072 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6073 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6074 if (copies_in_use
>= copies
)
6082 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6085 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6087 for (i
= 0; i
< uses
; i
++)
6089 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6090 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6091 /* Note that this allows resources to be oversubscribed. That's
6092 essential to the way the optional scheduler works.
6093 resources_available reports when a resource is over-subscribed,
6094 so it's easy to tell. */
6095 rt
->units
[stage
+ cycle
][unit
]++;
6101 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6104 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6106 for (i
= 0; i
< uses
; i
++)
6108 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6109 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6110 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6111 rt
->units
[stage
+ cycle
][unit
]--;
6116 /* Wrapper functions make parameterized resource reservation
6120 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6122 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6128 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6130 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6135 /* Note that this function does not check issue constraints, but
6136 solely whether the hardware is available to execute the given
6137 instructions together. It also doesn't check if the tinsns
6138 write the same state, or access the same tieports. That is
6139 checked by check_t1_t2_reads_and_writes. */
6142 resources_conflict (vliw_insn
*vinsn
)
6145 static resource_table
*rt
= NULL
;
6147 /* This is the most common case by far. Optimize it. */
6148 if (vinsn
->num_slots
== 1)
6153 xtensa_isa isa
= xtensa_default_isa
;
6154 rt
= new_resource_table
6155 (isa
, xtensa_num_pipe_stages
,
6156 xtensa_isa_num_funcUnits (isa
),
6157 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6158 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6159 opcode_funcUnit_use_unit
,
6160 opcode_funcUnit_use_stage
);
6163 clear_resource_table (rt
);
6165 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6167 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6169 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6176 /* finish_vinsn, emit_single_op and helper functions. */
6178 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6179 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6180 static void xg_assemble_vliw_tokens (vliw_insn
*);
6183 /* We have reached the end of a bundle; emit into the frag. */
6186 finish_vinsn (vliw_insn
*vinsn
)
6193 if (find_vinsn_conflicts (vinsn
))
6195 xg_clear_vinsn (vinsn
);
6199 /* First, find a format that works. */
6200 if (vinsn
->format
== XTENSA_UNDEFINED
)
6201 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6203 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6204 && produce_flix
== FLIX_NONE
)
6206 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6207 xg_clear_vinsn (vinsn
);
6211 if (vinsn
->format
== XTENSA_UNDEFINED
)
6213 as_where (&file_name
, &line
);
6214 as_bad_where (file_name
, line
,
6215 _("couldn't find a valid instruction format"));
6216 fprintf (stderr
, _(" ops were: "));
6217 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6218 fprintf (stderr
, _(" %s;"),
6219 xtensa_opcode_name (xtensa_default_isa
,
6220 vinsn
->slots
[i
].opcode
));
6221 fprintf (stderr
, _("\n"));
6222 xg_clear_vinsn (vinsn
);
6226 if (vinsn
->num_slots
6227 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6229 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6230 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6231 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6233 xg_clear_vinsn (vinsn
);
6237 if (resources_conflict (vinsn
))
6239 as_where (&file_name
, &line
);
6240 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6241 fprintf (stderr
, " ops were: ");
6242 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6243 fprintf (stderr
, " %s;",
6244 xtensa_opcode_name (xtensa_default_isa
,
6245 vinsn
->slots
[i
].opcode
));
6246 fprintf (stderr
, "\n");
6247 xg_clear_vinsn (vinsn
);
6251 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6253 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6255 symbolS
*lit_sym
= NULL
;
6257 bfd_boolean e
= FALSE
;
6258 bfd_boolean saved_density
= density_supported
;
6260 /* We don't want to narrow ops inside multi-slot bundles. */
6261 if (vinsn
->num_slots
> 1)
6262 density_supported
= FALSE
;
6264 istack_init (&slotstack
);
6265 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6267 vinsn
->slots
[i
].opcode
=
6268 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6270 vinsn
->slots
[i
].ntok
= 0;
6273 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6279 density_supported
= saved_density
;
6283 xg_clear_vinsn (vinsn
);
6287 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6289 TInsn
*insn
= &slotstack
.insn
[j
];
6290 if (insn
->insn_type
== ITYPE_LITERAL
)
6292 gas_assert (lit_sym
== NULL
);
6293 lit_sym
= xg_assemble_literal (insn
);
6297 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6299 xg_resolve_literals (insn
, lit_sym
);
6300 if (j
!= slotstack
.ninsn
- 1)
6301 emit_single_op (insn
);
6305 if (vinsn
->num_slots
> 1)
6307 if (opcode_fits_format_slot
6308 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6311 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6315 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6316 if (vinsn
->format
== XTENSA_UNDEFINED
)
6317 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6319 vinsn
->slots
[i
].opcode
6320 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6323 vinsn
->slots
[i
].ntok
= 0;
6328 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6329 vinsn
->format
= XTENSA_UNDEFINED
;
6334 /* Now check resource conflicts on the modified bundle. */
6335 if (resources_conflict (vinsn
))
6337 as_where (&file_name
, &line
);
6338 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6339 fprintf (stderr
, " ops were: ");
6340 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6341 fprintf (stderr
, " %s;",
6342 xtensa_opcode_name (xtensa_default_isa
,
6343 vinsn
->slots
[i
].opcode
));
6344 fprintf (stderr
, "\n");
6345 xg_clear_vinsn (vinsn
);
6349 /* First, find a format that works. */
6350 if (vinsn
->format
== XTENSA_UNDEFINED
)
6351 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6353 xg_assemble_vliw_tokens (vinsn
);
6355 xg_clear_vinsn (vinsn
);
6359 /* Given an vliw instruction, what conflicts are there in register
6360 usage and in writes to states and queues?
6362 This function does two things:
6363 1. Reports an error when a vinsn contains illegal combinations
6364 of writes to registers states or queues.
6365 2. Marks individual tinsns as not relaxable if the combination
6366 contains antidependencies.
6368 Job 2 handles things like swap semantics in instructions that need
6369 to be relaxed. For example,
6373 normally would be relaxed to
6378 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6380 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6382 then we can't relax it into
6385 { add a0, a1, a0 ; add a2, a0, a4 ; }
6387 because the value of a0 is trashed before the second add can read it. */
6389 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6392 find_vinsn_conflicts (vliw_insn
*vinsn
)
6396 xtensa_isa isa
= xtensa_default_isa
;
6398 gas_assert (!past_xtensa_end
);
6400 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6402 TInsn
*op1
= &vinsn
->slots
[i
];
6403 if (op1
->is_specific_opcode
)
6404 op1
->keep_wide
= TRUE
;
6406 op1
->keep_wide
= FALSE
;
6409 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6411 TInsn
*op1
= &vinsn
->slots
[i
];
6413 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6416 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6420 TInsn
*op2
= &vinsn
->slots
[j
];
6421 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6422 switch (conflict_type
)
6425 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6426 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6427 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6430 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6431 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6432 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6435 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6436 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6437 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6440 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6441 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6442 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6445 /* Everything is OK. */
6448 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6449 || conflict_type
== 'a');
6456 as_bad (_("multiple branches or jumps in the same bundle"));
6464 /* Check how the state used by t1 and t2 relate.
6467 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6468 case B: no relationship between what is read and written (both could
6469 read the same reg though)
6470 case C: t1 writes a register t2 writes (a register conflict within a
6472 case D: t1 writes a state that t2 also writes
6473 case E: t1 writes a tie queue that t2 also writes
6474 case F: two volatile queue accesses
6478 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6480 xtensa_isa isa
= xtensa_default_isa
;
6481 xtensa_regfile t1_regfile
, t2_regfile
;
6483 int t1_base_reg
, t1_last_reg
;
6484 int t2_base_reg
, t2_last_reg
;
6485 char t1_inout
, t2_inout
;
6487 char conflict
= 'b';
6492 bfd_boolean t1_volatile
= FALSE
;
6493 bfd_boolean t2_volatile
= FALSE
;
6495 /* Check registers. */
6496 for (j
= 0; j
< t2
->ntok
; j
++)
6498 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6501 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6502 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6503 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6505 for (i
= 0; i
< t1
->ntok
; i
++)
6507 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6510 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6512 if (t1_regfile
!= t2_regfile
)
6515 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6516 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6518 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6519 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6521 if (t1_inout
== 'm' || t1_inout
== 'o'
6522 || t2_inout
== 'm' || t2_inout
== 'o')
6529 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6530 t1_last_reg
= (t1_base_reg
6531 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6533 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6535 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6537 if (t1_reg
!= t2_reg
)
6540 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6546 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6552 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6560 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6561 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6562 for (j
= 0; j
< t2_states
; j
++)
6564 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6565 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6566 for (i
= 0; i
< t1_states
; i
++)
6568 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6569 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6570 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6573 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6579 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6585 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6590 /* Check tieports. */
6591 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6592 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6593 for (j
= 0; j
< t2_interfaces
; j
++)
6595 xtensa_interface t2_int
6596 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6597 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6599 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6600 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6603 for (i
= 0; i
< t1_interfaces
; i
++)
6605 xtensa_interface t1_int
6606 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6607 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6609 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6610 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6613 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6616 if (t1_int
!= t2_int
)
6619 if (t2_inout
== 'i' && t1_inout
== 'o')
6625 if (t1_inout
== 'i' && t2_inout
== 'o')
6631 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6640 static xtensa_format
6641 xg_find_narrowest_format (vliw_insn
*vinsn
)
6643 /* Right now we assume that the ops within the vinsn are properly
6644 ordered for the slots that the programmer wanted them in. In
6645 other words, we don't rearrange the ops in hopes of finding a
6646 better format. The scheduler handles that. */
6648 xtensa_isa isa
= xtensa_default_isa
;
6649 xtensa_format format
;
6650 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6652 if (vinsn
->num_slots
== 1)
6653 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6655 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6658 xg_copy_vinsn (&v_copy
, vinsn
);
6659 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6663 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6665 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6667 v_copy
.slots
[slot
].opcode
=
6668 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6669 v_copy
.slots
[slot
].ntok
= 0;
6672 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6675 else if (v_copy
.num_slots
> 1)
6678 /* Try the widened version. */
6679 if (!v_copy
.slots
[slot
].keep_wide
6680 && !v_copy
.slots
[slot
].is_specific_opcode
6681 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6683 && opcode_fits_format_slot (widened
.opcode
,
6686 v_copy
.slots
[slot
] = widened
;
6691 if (fit
== v_copy
.num_slots
)
6693 xg_copy_vinsn (vinsn
, &v_copy
);
6694 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6695 vinsn
->format
= format
;
6701 if (format
== xtensa_isa_num_formats (isa
))
6702 return XTENSA_UNDEFINED
;
6708 /* Return the additional space needed in a frag
6709 for possible relaxations of any ops in a VLIW insn.
6710 Also fill out the relaxations that might be required of
6711 each tinsn in the vinsn. */
6714 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6716 bfd_boolean finish_frag
= FALSE
;
6717 int extra_space
= 0;
6720 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6722 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6723 if (!tinsn_has_symbolic_operands (tinsn
))
6725 /* A narrow instruction could be widened later to help
6726 alignment issues. */
6727 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6728 && !tinsn
->is_specific_opcode
6729 && vinsn
->num_slots
== 1)
6731 /* Difference in bytes between narrow and wide insns... */
6733 tinsn
->subtype
= RELAX_NARROW
;
6738 if (workaround_b_j_loop_end
6739 && tinsn
->opcode
== xtensa_jx_opcode
6740 && use_transform ())
6742 /* Add 2 of these. */
6743 extra_space
+= 3; /* for the nop size */
6744 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6747 /* Need to assemble it with space for the relocation. */
6748 if (xg_is_relaxable_insn (tinsn
, 0)
6749 && !tinsn
->is_specific_opcode
)
6751 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6752 int max_literal_size
=
6753 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6755 tinsn
->literal_space
= max_literal_size
;
6757 tinsn
->subtype
= RELAX_IMMED
;
6758 extra_space
+= max_size
;
6762 /* A fix record will be added for this instruction prior
6763 to relaxation, so make it end the frag. */
6768 *pfinish_frag
= finish_frag
;
6774 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6776 xtensa_isa isa
= xtensa_default_isa
;
6777 int slot
, chosen_slot
;
6779 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6780 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6781 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6783 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6784 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6786 if (slot
== chosen_slot
)
6787 vinsn
->slots
[slot
] = *tinsn
;
6790 vinsn
->slots
[slot
].opcode
=
6791 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6792 vinsn
->slots
[slot
].ntok
= 0;
6793 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6800 emit_single_op (TInsn
*orig_insn
)
6803 IStack istack
; /* put instructions into here */
6804 symbolS
*lit_sym
= NULL
;
6805 symbolS
*label_sym
= NULL
;
6807 istack_init (&istack
);
6809 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6810 Because the scheduling and bundling characteristics of movi and
6811 l32r or const16 are so different, we can do much better if we relax
6812 it prior to scheduling and bundling, rather than after. */
6813 if ((orig_insn
->opcode
== xtensa_movi_opcode
6814 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6815 && !cur_vinsn
.inside_bundle
6816 && (orig_insn
->tok
[1].X_op
== O_symbol
6817 || orig_insn
->tok
[1].X_op
== O_pltrel
6818 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6819 || orig_insn
->tok
[1].X_op
== O_tlsarg
6820 || orig_insn
->tok
[1].X_op
== O_tpoff
6821 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6822 && !orig_insn
->is_specific_opcode
&& use_transform ())
6823 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6825 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6828 for (i
= 0; i
< istack
.ninsn
; i
++)
6830 TInsn
*insn
= &istack
.insn
[i
];
6831 switch (insn
->insn_type
)
6834 gas_assert (lit_sym
== NULL
);
6835 lit_sym
= xg_assemble_literal (insn
);
6839 static int relaxed_sym_idx
= 0;
6840 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6841 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6843 gas_assert (label_sym
== NULL
);
6844 label_sym
= symbol_find_or_make (label
);
6845 gas_assert (label_sym
);
6853 xg_resolve_literals (insn
, lit_sym
);
6855 xg_resolve_labels (insn
, label_sym
);
6857 bundle_tinsn (insn
, &v
);
6872 total_frag_text_expansion (fragS
*fragP
)
6875 int total_expansion
= 0;
6877 for (slot
= 0; slot
< config_max_slots
; slot
++)
6878 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6880 return total_expansion
;
6884 /* Emit a vliw instruction to the current fragment. */
6887 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6889 bfd_boolean finish_frag
;
6890 bfd_boolean is_jump
= FALSE
;
6891 bfd_boolean is_branch
= FALSE
;
6892 xtensa_isa isa
= xtensa_default_isa
;
6897 struct dwarf2_line_info debug_line
;
6898 bfd_boolean loc_directive_seen
= FALSE
;
6901 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6903 if (generating_literals
)
6905 static int reported
= 0;
6907 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6908 _("cannot assemble into a literal fragment"));
6915 if (frag_now_fix () != 0
6916 && (! frag_now
->tc_frag_data
.is_insn
6917 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6918 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6919 || (directive_state
[directive_longcalls
]
6920 != frag_now
->tc_frag_data
.use_longcalls
)
6921 || (directive_state
[directive_absolute_literals
]
6922 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6924 frag_wane (frag_now
);
6926 xtensa_set_frag_assembly_state (frag_now
);
6929 if (workaround_a0_b_retw
6930 && vinsn
->num_slots
== 1
6931 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6932 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6933 && use_transform ())
6935 has_a0_b_retw
= TRUE
;
6937 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6938 After the first assembly pass we will check all of them and
6939 add a nop if needed. */
6940 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6941 frag_var (rs_machine_dependent
, 4, 4,
6942 RELAX_ADD_NOP_IF_A0_B_RETW
,
6943 frag_now
->fr_symbol
,
6944 frag_now
->fr_offset
,
6946 xtensa_set_frag_assembly_state (frag_now
);
6947 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6948 frag_var (rs_machine_dependent
, 4, 4,
6949 RELAX_ADD_NOP_IF_A0_B_RETW
,
6950 frag_now
->fr_symbol
,
6951 frag_now
->fr_offset
,
6953 xtensa_set_frag_assembly_state (frag_now
);
6956 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6958 tinsn
= &vinsn
->slots
[slot
];
6960 /* See if the instruction implies an aligned section. */
6961 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6962 record_alignment (now_seg
, 2);
6964 /* Determine the best line number for debug info. */
6965 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6966 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6967 || tinsn
->debug_line
.line
< debug_line
.line
6968 || tinsn
->debug_line
.column
< debug_line
.column
))
6969 debug_line
= tinsn
->debug_line
;
6970 if (tinsn
->loc_directive_seen
)
6971 loc_directive_seen
= TRUE
;
6974 /* Special cases for instructions that force an alignment... */
6975 /* None of these opcodes are bundle-able. */
6976 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6980 /* Remember the symbol that marks the end of the loop in the frag
6981 that marks the start of the loop. This way we can easily find
6982 the end of the loop at the beginning, without adding special code
6983 to mark the loop instructions themselves. */
6984 symbolS
*target_sym
= NULL
;
6985 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6986 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6988 xtensa_set_frag_assembly_state (frag_now
);
6989 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6991 max_fill
= get_text_align_max_fill_size
6992 (get_text_align_power (xtensa_fetch_width
),
6993 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6995 if (use_transform ())
6996 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6997 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6999 frag_var (rs_machine_dependent
, 0, 0,
7000 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7001 xtensa_set_frag_assembly_state (frag_now
);
7004 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7005 && !vinsn
->slots
[0].is_specific_opcode
)
7007 xtensa_mark_literal_pool_location ();
7008 xtensa_move_labels (frag_now
, 0);
7009 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7012 if (vinsn
->num_slots
== 1)
7014 if (workaround_a0_b_retw
&& use_transform ())
7015 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7016 is_register_writer (&vinsn
->slots
[0], "a", 0));
7018 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7019 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7022 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7024 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7026 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7028 /* vinsn_to_insnbuf will produce the error. */
7029 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7031 f
= frag_more (insn_size
+ extra_space
);
7032 xtensa_set_frag_assembly_state (frag_now
);
7033 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7036 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7037 if (vinsn
->format
== XTENSA_UNDEFINED
)
7040 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7042 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7043 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7046 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7048 tinsn
= &vinsn
->slots
[slot
];
7049 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7050 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7051 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7052 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7053 if (tinsn
->literal_space
!= 0)
7054 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7055 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7057 if (tinsn
->subtype
== RELAX_NARROW
)
7058 gas_assert (vinsn
->num_slots
== 1);
7059 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7061 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7064 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7065 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7069 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7070 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7074 frag_variant (rs_machine_dependent
,
7075 extra_space
, extra_space
, RELAX_SLOTS
,
7076 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7077 xtensa_set_frag_assembly_state (frag_now
);
7080 /* Special cases for loops:
7081 close_loop_end should be inserted AFTER short_loop.
7082 Make sure that CLOSE loops are processed BEFORE short_loops
7083 when converting them. */
7085 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7086 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7087 && !vinsn
->slots
[0].is_specific_opcode
)
7089 if (workaround_short_loop
&& use_transform ())
7091 maybe_has_short_loop
= TRUE
;
7092 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7093 frag_var (rs_machine_dependent
, 4, 4,
7094 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7095 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7096 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7097 frag_var (rs_machine_dependent
, 4, 4,
7098 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7099 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7102 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7103 loop at least 12 bytes away from another loop's end. */
7104 if (workaround_close_loop_end
&& use_transform ())
7106 maybe_has_close_loop_end
= TRUE
;
7107 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7108 frag_var (rs_machine_dependent
, 12, 12,
7109 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7110 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7114 if (use_transform ())
7118 gas_assert (finish_frag
);
7119 frag_var (rs_machine_dependent
,
7120 xtensa_fetch_width
, xtensa_fetch_width
,
7122 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7123 xtensa_set_frag_assembly_state (frag_now
);
7125 else if (is_branch
&& do_align_targets ())
7127 gas_assert (finish_frag
);
7128 frag_var (rs_machine_dependent
,
7129 xtensa_fetch_width
, xtensa_fetch_width
,
7130 RELAX_MAYBE_UNREACHABLE
,
7131 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7132 xtensa_set_frag_assembly_state (frag_now
);
7133 frag_var (rs_machine_dependent
,
7135 RELAX_MAYBE_DESIRE_ALIGN
,
7136 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7137 xtensa_set_frag_assembly_state (frag_now
);
7141 /* Now, if the original opcode was a call... */
7142 if (do_align_targets ()
7143 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7145 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7146 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7147 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7148 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7149 xtensa_set_frag_assembly_state (frag_now
);
7152 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7154 frag_wane (frag_now
);
7156 xtensa_set_frag_assembly_state (frag_now
);
7161 /* xtensa_end and helper functions. */
7163 static void xtensa_cleanup_align_frags (void);
7164 static void xtensa_fix_target_frags (void);
7165 static void xtensa_mark_narrow_branches (void);
7166 static void xtensa_mark_zcl_first_insns (void);
7167 static void xtensa_mark_difference_of_two_symbols (void);
7168 static void xtensa_fix_a0_b_retw_frags (void);
7169 static void xtensa_fix_b_j_loop_end_frags (void);
7170 static void xtensa_fix_close_loop_end_frags (void);
7171 static void xtensa_fix_short_loop_frags (void);
7172 static void xtensa_sanity_check (void);
7173 static void xtensa_add_config_info (void);
7178 directive_balance ();
7179 xtensa_flush_pending_output ();
7181 past_xtensa_end
= TRUE
;
7183 xtensa_move_literals ();
7185 xtensa_reorder_segments ();
7186 xtensa_cleanup_align_frags ();
7187 xtensa_fix_target_frags ();
7188 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7189 xtensa_fix_a0_b_retw_frags ();
7190 if (workaround_b_j_loop_end
)
7191 xtensa_fix_b_j_loop_end_frags ();
7193 /* "close_loop_end" should be processed BEFORE "short_loop". */
7194 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7195 xtensa_fix_close_loop_end_frags ();
7197 if (workaround_short_loop
&& maybe_has_short_loop
)
7198 xtensa_fix_short_loop_frags ();
7200 xtensa_mark_narrow_branches ();
7201 xtensa_mark_zcl_first_insns ();
7203 xtensa_sanity_check ();
7205 xtensa_add_config_info ();
7210 xtensa_cleanup_align_frags (void)
7215 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7216 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7219 /* Walk over all of the fragments in a subsection. */
7220 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7222 if ((fragP
->fr_type
== rs_align
7223 || fragP
->fr_type
== rs_align_code
7224 || (fragP
->fr_type
== rs_machine_dependent
7225 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7226 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7227 && fragP
->fr_fix
== 0)
7229 fragS
*next
= fragP
->fr_next
;
7232 && next
->fr_fix
== 0
7233 && next
->fr_type
== rs_machine_dependent
7234 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7237 next
= next
->fr_next
;
7240 /* If we don't widen branch targets, then they
7241 will be easier to align. */
7242 if (fragP
->tc_frag_data
.is_branch_target
7243 && fragP
->fr_opcode
== fragP
->fr_literal
7244 && fragP
->fr_type
== rs_machine_dependent
7245 && fragP
->fr_subtype
== RELAX_SLOTS
7246 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7248 if (fragP
->fr_type
== rs_machine_dependent
7249 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7250 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7256 /* Re-process all of the fragments looking to convert all of the
7257 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7258 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7259 Otherwise, convert to a .fill 0. */
7262 xtensa_fix_target_frags (void)
7267 /* When this routine is called, all of the subsections are still intact
7268 so we walk over subsections instead of sections. */
7269 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7270 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7274 /* Walk over all of the fragments in a subsection. */
7275 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7277 if (fragP
->fr_type
== rs_machine_dependent
7278 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7280 if (next_frag_is_branch_target (fragP
))
7281 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7290 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7293 xtensa_mark_narrow_branches (void)
7298 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7299 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7302 /* Walk over all of the fragments in a subsection. */
7303 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7305 if (fragP
->fr_type
== rs_machine_dependent
7306 && fragP
->fr_subtype
== RELAX_SLOTS
7307 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7311 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7312 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7314 if (vinsn
.num_slots
== 1
7315 && xtensa_opcode_is_branch (xtensa_default_isa
,
7316 vinsn
.slots
[0].opcode
) == 1
7317 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7318 && is_narrow_branch_guaranteed_in_range (fragP
,
7321 fragP
->fr_subtype
= RELAX_SLOTS
;
7322 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7323 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7331 /* A branch is typically widened only when its target is out of
7332 range. However, we would like to widen them to align a subsequent
7333 branch target when possible.
7335 Because the branch relaxation code is so convoluted, the optimal solution
7336 (combining the two cases) is difficult to get right in all circumstances.
7337 We therefore go with an "almost as good" solution, where we only
7338 use for alignment narrow branches that definitely will not expand to a
7339 jump and a branch. These functions find and mark these cases. */
7341 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7342 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7343 We start counting beginning with the frag after the 2-byte branch, so the
7344 maximum offset is (4 - 2) + 63 = 65. */
7345 #define MAX_IMMED6 65
7347 static offsetT
unrelaxed_frag_max_size (fragS
*);
7350 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7352 const expressionS
*exp
= &tinsn
->tok
[1];
7353 symbolS
*symbolP
= exp
->X_add_symbol
;
7354 offsetT max_distance
= exp
->X_add_number
;
7357 if (exp
->X_op
!= O_symbol
)
7360 target_frag
= symbol_get_frag (symbolP
);
7362 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7363 if (is_branch_jmp_to_next (tinsn
, fragP
))
7366 /* The branch doesn't branch over it's own frag,
7367 but over the subsequent ones. */
7368 fragP
= fragP
->fr_next
;
7369 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7371 max_distance
+= unrelaxed_frag_max_size (fragP
);
7372 fragP
= fragP
->fr_next
;
7374 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7381 xtensa_mark_zcl_first_insns (void)
7386 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7387 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7390 /* Walk over all of the fragments in a subsection. */
7391 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7393 if (fragP
->fr_type
== rs_machine_dependent
7394 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7395 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7397 /* Find the loop frag. */
7398 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7399 /* Find the first insn frag. */
7400 targ_frag
= next_non_empty_frag (targ_frag
);
7402 /* Of course, sometimes (mostly for toy test cases) a
7403 zero-cost loop instruction is the last in a section. */
7406 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7407 /* Do not widen a frag that is the first instruction of a
7408 zero-cost loop. It makes that loop harder to align. */
7409 if (targ_frag
->fr_type
== rs_machine_dependent
7410 && targ_frag
->fr_subtype
== RELAX_SLOTS
7411 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7414 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7415 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7418 frag_wane (targ_frag
);
7419 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7423 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7431 /* When a difference-of-symbols expression is encoded as a uleb128 or
7432 sleb128 value, the linker is unable to adjust that value to account for
7433 link-time relaxation. Mark all the code between such symbols so that
7434 its size cannot be changed by linker relaxation. */
7437 xtensa_mark_difference_of_two_symbols (void)
7441 for (expr_sym
= expr_symbols
; expr_sym
;
7442 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7444 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7446 if (exp
->X_op
== O_subtract
)
7448 symbolS
*left
= exp
->X_add_symbol
;
7449 symbolS
*right
= exp
->X_op_symbol
;
7451 /* Difference of two symbols not in the same section
7452 are handled with relocations in the linker. */
7453 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7459 if (symbol_get_frag (left
)->fr_address
7460 <= symbol_get_frag (right
)->fr_address
)
7462 start
= symbol_get_frag (left
);
7463 end
= symbol_get_frag (right
);
7467 start
= symbol_get_frag (right
);
7468 end
= symbol_get_frag (left
);
7471 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7472 walk
= start
->tc_frag_data
.no_transform_end
;
7477 walk
->tc_frag_data
.is_no_transform
= 1;
7478 walk
= walk
->fr_next
;
7480 while (walk
&& walk
->fr_address
< end
->fr_address
);
7482 start
->tc_frag_data
.no_transform_end
= walk
;
7489 /* Re-process all of the fragments looking to convert all of the
7490 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7491 conditional branch or a retw/retw.n, convert this frag to one that
7492 will generate a NOP. In any case close it off with a .fill 0. */
7494 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7497 xtensa_fix_a0_b_retw_frags (void)
7502 /* When this routine is called, all of the subsections are still intact
7503 so we walk over subsections instead of sections. */
7504 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7505 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7509 /* Walk over all of the fragments in a subsection. */
7510 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7512 if (fragP
->fr_type
== rs_machine_dependent
7513 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7515 if (next_instrs_are_b_retw (fragP
))
7517 if (fragP
->tc_frag_data
.is_no_transform
)
7518 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7520 relax_frag_add_nop (fragP
);
7530 next_instrs_are_b_retw (fragS
*fragP
)
7532 xtensa_opcode opcode
;
7534 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7535 static xtensa_insnbuf insnbuf
= NULL
;
7536 static xtensa_insnbuf slotbuf
= NULL
;
7537 xtensa_isa isa
= xtensa_default_isa
;
7540 bfd_boolean branch_seen
= FALSE
;
7544 insnbuf
= xtensa_insnbuf_alloc (isa
);
7545 slotbuf
= xtensa_insnbuf_alloc (isa
);
7548 if (next_fragP
== NULL
)
7551 /* Check for the conditional branch. */
7552 xtensa_insnbuf_from_chars
7553 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7554 fmt
= xtensa_format_decode (isa
, insnbuf
);
7555 if (fmt
== XTENSA_UNDEFINED
)
7558 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7560 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7561 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7563 branch_seen
= (branch_seen
7564 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7570 offset
+= xtensa_format_length (isa
, fmt
);
7571 if (offset
== next_fragP
->fr_fix
)
7573 next_fragP
= next_non_empty_frag (next_fragP
);
7577 if (next_fragP
== NULL
)
7580 /* Check for the retw/retw.n. */
7581 xtensa_insnbuf_from_chars
7582 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7583 fmt
= xtensa_format_decode (isa
, insnbuf
);
7585 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7586 have no problems. */
7587 if (fmt
== XTENSA_UNDEFINED
7588 || xtensa_format_num_slots (isa
, fmt
) != 1)
7591 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7592 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7594 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7601 /* Re-process all of the fragments looking to convert all of the
7602 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7603 loop end label, convert this frag to one that will generate a NOP.
7604 In any case close it off with a .fill 0. */
7606 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7609 xtensa_fix_b_j_loop_end_frags (void)
7614 /* When this routine is called, all of the subsections are still intact
7615 so we walk over subsections instead of sections. */
7616 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7617 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7621 /* Walk over all of the fragments in a subsection. */
7622 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7624 if (fragP
->fr_type
== rs_machine_dependent
7625 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7627 if (next_instr_is_loop_end (fragP
))
7629 if (fragP
->tc_frag_data
.is_no_transform
)
7630 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7632 relax_frag_add_nop (fragP
);
7642 next_instr_is_loop_end (fragS
*fragP
)
7644 const fragS
*next_fragP
;
7646 if (next_frag_is_loop_target (fragP
))
7649 next_fragP
= next_non_empty_frag (fragP
);
7650 if (next_fragP
== NULL
)
7653 if (!next_frag_is_loop_target (next_fragP
))
7656 /* If the size is >= 3 then there is more than one instruction here.
7657 The hardware bug will not fire. */
7658 if (next_fragP
->fr_fix
> 3)
7665 /* Re-process all of the fragments looking to convert all of the
7666 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7667 not MY loop's loop end within 12 bytes, add enough nops here to
7668 make it at least 12 bytes away. In any case close it off with a
7671 static offsetT min_bytes_to_other_loop_end
7672 (fragS
*, fragS
*, offsetT
);
7675 xtensa_fix_close_loop_end_frags (void)
7680 /* When this routine is called, all of the subsections are still intact
7681 so we walk over subsections instead of sections. */
7682 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7683 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7687 fragS
*current_target
= NULL
;
7689 /* Walk over all of the fragments in a subsection. */
7690 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7692 if (fragP
->fr_type
== rs_machine_dependent
7693 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7694 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7695 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7698 && fragP
->fr_type
== rs_machine_dependent
7699 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7702 int bytes_added
= 0;
7704 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7705 /* Max out at 12. */
7706 min_bytes
= min_bytes_to_other_loop_end
7707 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7709 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7711 if (fragP
->tc_frag_data
.is_no_transform
)
7712 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7715 while (min_bytes
+ bytes_added
7716 < REQUIRED_LOOP_DIVIDING_BYTES
)
7720 if (fragP
->fr_var
< length
)
7721 as_fatal (_("fr_var %lu < length %d"),
7722 (long) fragP
->fr_var
, length
);
7725 assemble_nop (length
,
7726 fragP
->fr_literal
+ fragP
->fr_fix
);
7727 fragP
->fr_fix
+= length
;
7728 fragP
->fr_var
-= length
;
7730 bytes_added
+= length
;
7736 gas_assert (fragP
->fr_type
!= rs_machine_dependent
7737 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7743 static offsetT
unrelaxed_frag_min_size (fragS
*);
7746 min_bytes_to_other_loop_end (fragS
*fragP
,
7747 fragS
*current_target
,
7751 fragS
*current_fragP
;
7753 for (current_fragP
= fragP
;
7755 current_fragP
= current_fragP
->fr_next
)
7757 if (current_fragP
->tc_frag_data
.is_loop_target
7758 && current_fragP
!= current_target
)
7761 offset
+= unrelaxed_frag_min_size (current_fragP
);
7763 if (offset
>= max_size
)
7771 unrelaxed_frag_min_size (fragS
*fragP
)
7773 offsetT size
= fragP
->fr_fix
;
7775 /* Add fill size. */
7776 if (fragP
->fr_type
== rs_fill
)
7777 size
+= fragP
->fr_offset
;
7784 unrelaxed_frag_max_size (fragS
*fragP
)
7786 offsetT size
= fragP
->fr_fix
;
7787 switch (fragP
->fr_type
)
7790 /* Empty frags created by the obstack allocation scheme
7791 end up with type 0. */
7796 size
+= fragP
->fr_offset
;
7804 /* No further adjustments needed. */
7806 case rs_machine_dependent
:
7807 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7808 size
+= fragP
->fr_var
;
7811 /* We had darn well better know how big it is. */
7820 /* Re-process all of the fragments looking to convert all
7821 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7824 1) the instruction size count to the loop end label
7825 is too short (<= 2 instructions),
7826 2) loop has a jump or branch in it
7829 1) workaround_all_short_loops is TRUE
7830 2) The generating loop was a 'loopgtz' or 'loopnez'
7831 3) the instruction size count to the loop end label is too short
7833 then convert this frag (and maybe the next one) to generate a NOP.
7834 In any case close it off with a .fill 0. */
7836 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7837 static bfd_boolean
branch_before_loop_end (fragS
*);
7840 xtensa_fix_short_loop_frags (void)
7845 /* When this routine is called, all of the subsections are still intact
7846 so we walk over subsections instead of sections. */
7847 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7848 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7851 fragS
*current_target
= NULL
;
7852 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7854 /* Walk over all of the fragments in a subsection. */
7855 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7857 if (fragP
->fr_type
== rs_machine_dependent
7858 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7859 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7862 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7863 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7864 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7865 current_opcode
= t_insn
.opcode
;
7866 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7867 current_opcode
) == 1);
7870 if (fragP
->fr_type
== rs_machine_dependent
7871 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7873 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7874 && (branch_before_loop_end (fragP
->fr_next
)
7875 || (workaround_all_short_loops
7876 && current_opcode
!= XTENSA_UNDEFINED
7877 && current_opcode
!= xtensa_loop_opcode
)))
7879 if (fragP
->tc_frag_data
.is_no_transform
)
7880 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7882 relax_frag_add_nop (fragP
);
7891 static int unrelaxed_frag_min_insn_count (fragS
*);
7894 count_insns_to_loop_end (fragS
*base_fragP
,
7895 bfd_boolean count_relax_add
,
7898 fragS
*fragP
= NULL
;
7903 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7905 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7906 if (insn_count
>= max_count
)
7909 if (count_relax_add
)
7911 if (fragP
->fr_type
== rs_machine_dependent
7912 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7914 /* In order to add the appropriate number of
7915 NOPs, we count an instruction for downstream
7918 if (insn_count
>= max_count
)
7928 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7930 xtensa_isa isa
= xtensa_default_isa
;
7931 static xtensa_insnbuf insnbuf
= NULL
;
7935 if (!fragP
->tc_frag_data
.is_insn
)
7939 insnbuf
= xtensa_insnbuf_alloc (isa
);
7941 /* Decode the fixed instructions. */
7942 while (offset
< fragP
->fr_fix
)
7946 xtensa_insnbuf_from_chars
7947 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7948 fmt
= xtensa_format_decode (isa
, insnbuf
);
7950 if (fmt
== XTENSA_UNDEFINED
)
7952 as_fatal (_("undecodable instruction in instruction frag"));
7955 offset
+= xtensa_format_length (isa
, fmt
);
7963 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7966 branch_before_loop_end (fragS
*base_fragP
)
7970 for (fragP
= base_fragP
;
7971 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7972 fragP
= fragP
->fr_next
)
7974 if (unrelaxed_frag_has_b_j (fragP
))
7982 unrelaxed_frag_has_b_j (fragS
*fragP
)
7984 static xtensa_insnbuf insnbuf
= NULL
;
7985 xtensa_isa isa
= xtensa_default_isa
;
7988 if (!fragP
->tc_frag_data
.is_insn
)
7992 insnbuf
= xtensa_insnbuf_alloc (isa
);
7994 /* Decode the fixed instructions. */
7995 while (offset
< fragP
->fr_fix
)
8000 xtensa_insnbuf_from_chars
8001 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8002 fmt
= xtensa_format_decode (isa
, insnbuf
);
8003 if (fmt
== XTENSA_UNDEFINED
)
8006 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8008 xtensa_opcode opcode
=
8009 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8010 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8011 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8014 offset
+= xtensa_format_length (isa
, fmt
);
8020 /* Checks to be made after initial assembly but before relaxation. */
8022 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8023 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8026 xtensa_sanity_check (void)
8033 as_where (&file_name
, &line
);
8034 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8035 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8039 /* Walk over all of the fragments in a subsection. */
8040 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8042 if (fragP
->fr_type
== rs_machine_dependent
8043 && fragP
->fr_subtype
== RELAX_SLOTS
8044 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8046 static xtensa_insnbuf insnbuf
= NULL
;
8049 if (fragP
->fr_opcode
!= NULL
)
8052 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8053 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8054 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8056 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8057 t_insn
.opcode
) == 1)
8059 if (is_empty_loop (&t_insn
, fragP
))
8061 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8062 as_bad (_("invalid empty loop"));
8064 if (!is_local_forward_loop (&t_insn
, fragP
))
8066 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8067 as_bad (_("loop target does not follow "
8068 "loop instruction in section"));
8075 new_logical_line (file_name
, line
);
8079 #define LOOP_IMMED_OPN 1
8081 /* Return TRUE if the loop target is the next non-zero fragment. */
8084 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8086 const expressionS
*exp
;
8090 if (insn
->insn_type
!= ITYPE_INSN
)
8093 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8096 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8099 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8101 if (exp
->X_op
!= O_symbol
)
8104 symbolP
= exp
->X_add_symbol
;
8108 if (symbol_get_frag (symbolP
) == NULL
)
8111 if (S_GET_VALUE (symbolP
) != 0)
8114 /* Walk through the zero-size fragments from this one. If we find
8115 the target fragment, then this is a zero-size loop. */
8117 for (next_fragP
= fragP
->fr_next
;
8119 next_fragP
= next_fragP
->fr_next
)
8121 if (next_fragP
== symbol_get_frag (symbolP
))
8123 if (next_fragP
->fr_fix
!= 0)
8131 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8133 const expressionS
*exp
;
8137 if (insn
->insn_type
!= ITYPE_INSN
)
8140 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8143 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8146 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8148 if (exp
->X_op
!= O_symbol
)
8151 symbolP
= exp
->X_add_symbol
;
8155 if (symbol_get_frag (symbolP
) == NULL
)
8158 /* Walk through fragments until we find the target.
8159 If we do not find the target, then this is an invalid loop. */
8161 for (next_fragP
= fragP
->fr_next
;
8163 next_fragP
= next_fragP
->fr_next
)
8165 if (next_fragP
== symbol_get_frag (symbolP
))
8173 #define XTINFO_NAME "Xtensa_Info"
8174 #define XTINFO_NAMESZ 12
8175 #define XTINFO_TYPE 1
8178 xtensa_add_config_info (void)
8184 info_sec
= subseg_new (".xtensa.info", 0);
8185 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8187 data
= xmalloc (100);
8188 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8189 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8190 sz
= strlen (data
) + 1;
8192 /* Add enough null terminators to pad to a word boundary. */
8195 while ((sz
& 3) != 0);
8197 /* Follow the standard note section layout:
8198 First write the length of the name string. */
8200 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8202 /* Next comes the length of the "descriptor", i.e., the actual data. */
8204 md_number_to_chars (p
, (valueT
) sz
, 4);
8206 /* Write the note type. */
8208 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8210 /* Write the name field. */
8211 p
= frag_more (XTINFO_NAMESZ
);
8212 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8214 /* Finally, write the descriptor. */
8216 memcpy (p
, data
, sz
);
8222 /* Alignment Functions. */
8225 get_text_align_power (unsigned target_size
)
8227 if (target_size
<= 4)
8229 gas_assert (target_size
== 8);
8235 get_text_align_max_fill_size (int align_pow
,
8236 bfd_boolean use_nops
,
8237 bfd_boolean use_no_density
)
8240 return (1 << align_pow
);
8242 return 3 * (1 << align_pow
);
8244 return 1 + (1 << align_pow
);
8248 /* Calculate the minimum bytes of fill needed at "address" to align a
8249 target instruction of size "target_size" so that it does not cross a
8250 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8251 the fill can be an arbitrary number of bytes. Otherwise, the space must
8252 be filled by NOP instructions. */
8255 get_text_align_fill_size (addressT address
,
8258 bfd_boolean use_nops
,
8259 bfd_boolean use_no_density
)
8261 addressT alignment
, fill
, fill_limit
, fill_step
;
8262 bfd_boolean skip_one
= FALSE
;
8264 alignment
= (1 << align_pow
);
8265 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8269 fill_limit
= alignment
;
8272 else if (!use_no_density
)
8274 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8275 fill_limit
= alignment
* 2;
8281 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8282 fill_limit
= alignment
* 3;
8286 /* Try all fill sizes until finding one that works. */
8287 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8289 if (skip_one
&& fill
== 1)
8291 if ((address
+ fill
) >> align_pow
8292 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8301 branch_align_power (segT sec
)
8303 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8304 is aligned to at least an 8-byte boundary, then a branch target need
8305 only fit within an 8-byte aligned block of memory to avoid a stall.
8306 Otherwise, try to fit branch targets within 4-byte aligned blocks
8307 (which may be insufficient, e.g., if the section has no alignment, but
8308 it's good enough). */
8309 if (xtensa_fetch_width
== 8)
8311 if (get_recorded_alignment (sec
) >= 3)
8315 gas_assert (xtensa_fetch_width
== 4);
8321 /* This will assert if it is not possible. */
8324 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8330 gas_assert (fill_size
% 3 == 0);
8331 return (fill_size
/ 3);
8334 gas_assert (fill_size
!= 1); /* Bad argument. */
8336 while (fill_size
> 1)
8339 if (fill_size
== 2 || fill_size
== 4)
8341 fill_size
-= insn_size
;
8344 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8350 get_text_align_nth_nop_size (offsetT fill_size
,
8352 bfd_boolean use_no_density
)
8359 gas_assert (fill_size
!= 1); /* Bad argument. */
8361 while (fill_size
> 1)
8364 if (fill_size
== 2 || fill_size
== 4)
8366 fill_size
-= insn_size
;
8376 /* For the given fragment, find the appropriate address
8377 for it to begin at if we are using NOPs to align it. */
8380 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8382 /* The rule is: get next fragment's FIRST instruction. Find
8383 the smallest number of bytes that need to be added to
8384 ensure that the next fragment's FIRST instruction will fit
8387 E.G., 2 bytes : 0, 1, 2 mod 4
8390 If the FIRST instruction MIGHT be relaxed,
8391 assume that it will become a 3-byte instruction.
8393 Note again here that LOOP instructions are not bundleable,
8394 and this relaxation only applies to LOOP opcodes. */
8397 int first_insn_size
;
8399 addressT pre_opcode_bytes
;
8402 xtensa_opcode opcode
;
8403 bfd_boolean is_loop
;
8405 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8406 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8408 /* Find the loop frag. */
8409 first_insn
= next_non_empty_frag (fragP
);
8410 /* Now find the first insn frag. */
8411 first_insn
= next_non_empty_frag (first_insn
);
8413 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8414 gas_assert (is_loop
);
8415 loop_insn_size
= xg_get_single_size (opcode
);
8417 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8418 pre_opcode_bytes
+= loop_insn_size
;
8420 /* For loops, the alignment depends on the size of the
8421 instruction following the loop, not the LOOP instruction. */
8423 if (first_insn
== NULL
)
8424 first_insn_size
= xtensa_fetch_width
;
8426 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8428 /* If it was 8, then we'll need a larger alignment for the section. */
8429 align_power
= get_text_align_power (first_insn_size
);
8430 record_alignment (now_seg
, align_power
);
8432 fill_size
= get_text_align_fill_size
8433 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8434 fragP
->tc_frag_data
.is_no_density
);
8436 return address
+ fill_size
;
8440 /* 3 mechanisms for relaxing an alignment:
8442 Align to a power of 2.
8443 Align so the next fragment's instruction does not cross a word boundary.
8444 Align the current instruction so that if the next instruction
8445 were 3 bytes, it would not cross a word boundary.
8449 zeros - This is easy; always insert zeros.
8450 nops - 3-byte and 2-byte instructions
8454 >=5 : 3-byte instruction + fn (n-3)
8455 widening - widen previous instructions. */
8458 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8460 addressT target_address
, loop_insn_offset
;
8462 xtensa_opcode loop_opcode
;
8463 bfd_boolean is_loop
;
8466 offsetT branch_align
;
8469 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8470 switch (fragP
->fr_subtype
)
8472 case RELAX_DESIRE_ALIGN
:
8473 target_size
= next_frag_format_size (fragP
);
8474 if (target_size
== XTENSA_UNDEFINED
)
8476 align_power
= branch_align_power (now_seg
);
8477 branch_align
= 1 << align_power
;
8478 /* Don't count on the section alignment being as large as the target. */
8479 if (target_size
> branch_align
)
8480 target_size
= branch_align
;
8481 opt_diff
= get_text_align_fill_size (address
, align_power
,
8482 target_size
, FALSE
, FALSE
);
8484 *max_diff
= (opt_diff
+ branch_align
8485 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8486 gas_assert (*max_diff
>= opt_diff
);
8489 case RELAX_ALIGN_NEXT_OPCODE
:
8490 /* The next non-empty frag after this one holds the LOOP instruction
8491 that needs to be aligned. The required alignment depends on the
8492 size of the next non-empty frag after the loop frag, i.e., the
8493 first instruction in the loop. */
8494 loop_frag
= next_non_empty_frag (fragP
);
8495 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8496 loop_insn_offset
= 0;
8497 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8498 gas_assert (is_loop
);
8500 /* If the loop has been expanded then the LOOP instruction
8501 could be at an offset from this fragment. */
8502 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8503 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8505 /* In an ideal world, which is what we are shooting for here,
8506 we wouldn't need to use any NOPs immediately prior to the
8507 LOOP instruction. If this approach fails, relax_frag_loop_align
8508 will call get_noop_aligned_address. */
8510 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8511 align_power
= get_text_align_power (target_size
);
8512 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8513 target_size
, FALSE
, FALSE
);
8515 *max_diff
= xtensa_fetch_width
8516 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8517 - target_size
+ opt_diff
;
8518 gas_assert (*max_diff
>= opt_diff
);
8529 /* md_relax_frag Hook and Helper Functions. */
8531 static long relax_frag_loop_align (fragS
*, long);
8532 static long relax_frag_for_align (fragS
*, long);
8533 static long relax_frag_immed
8534 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8537 /* Return the number of bytes added to this fragment, given that the
8538 input has been stretched already by "stretch". */
8541 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8543 xtensa_isa isa
= xtensa_default_isa
;
8544 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8545 long new_stretch
= 0;
8549 static xtensa_insnbuf vbuf
= NULL
;
8550 int slot
, num_slots
;
8553 as_where (&file_name
, &line
);
8554 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8556 fragP
->tc_frag_data
.unreported_expansion
= 0;
8558 switch (fragP
->fr_subtype
)
8560 case RELAX_ALIGN_NEXT_OPCODE
:
8561 /* Always convert. */
8562 if (fragP
->tc_frag_data
.relax_seen
)
8563 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8566 case RELAX_LOOP_END
:
8570 case RELAX_LOOP_END_ADD_NOP
:
8571 /* Add a NOP and switch to .fill 0. */
8572 new_stretch
= relax_frag_add_nop (fragP
);
8576 case RELAX_DESIRE_ALIGN
:
8577 /* Do nothing. The narrowing before this frag will either align
8582 case RELAX_LITERAL_FINAL
:
8585 case RELAX_LITERAL_NR
:
8587 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8588 gas_assert (unreported
== lit_size
);
8589 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8590 fragP
->fr_var
-= lit_size
;
8591 fragP
->fr_fix
+= lit_size
;
8597 vbuf
= xtensa_insnbuf_alloc (isa
);
8599 xtensa_insnbuf_from_chars
8600 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8601 fmt
= xtensa_format_decode (isa
, vbuf
);
8602 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8604 for (slot
= 0; slot
< num_slots
; slot
++)
8606 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8609 if (fragP
->tc_frag_data
.relax_seen
)
8610 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8614 case RELAX_IMMED_STEP1
:
8615 case RELAX_IMMED_STEP2
:
8616 case RELAX_IMMED_STEP3
:
8617 /* Place the immediate. */
8618 new_stretch
+= relax_frag_immed
8619 (now_seg
, fragP
, stretch
,
8620 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8621 fmt
, slot
, stretched_p
, FALSE
);
8625 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8631 case RELAX_LITERAL_POOL_BEGIN
:
8632 case RELAX_LITERAL_POOL_END
:
8633 case RELAX_MAYBE_UNREACHABLE
:
8634 case RELAX_MAYBE_DESIRE_ALIGN
:
8635 /* No relaxation required. */
8638 case RELAX_FILL_NOP
:
8639 case RELAX_UNREACHABLE
:
8640 if (fragP
->tc_frag_data
.relax_seen
)
8641 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8645 as_bad (_("bad relaxation state"));
8648 /* Tell gas we need another relaxation pass. */
8649 if (! fragP
->tc_frag_data
.relax_seen
)
8651 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8655 new_logical_line (file_name
, line
);
8661 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8663 addressT old_address
, old_next_address
, old_size
;
8664 addressT new_address
, new_next_address
, new_size
;
8667 /* All the frags with relax_frag_for_alignment prior to this one in the
8668 section have been done, hopefully eliminating the need for a NOP here.
8669 But, this will put it in if necessary. */
8671 /* Calculate the old address of this fragment and the next fragment. */
8672 old_address
= fragP
->fr_address
- stretch
;
8673 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8674 fragP
->tc_frag_data
.text_expansion
[0]);
8675 old_size
= old_next_address
- old_address
;
8677 /* Calculate the new address of this fragment and the next fragment. */
8678 new_address
= fragP
->fr_address
;
8680 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8681 new_size
= new_next_address
- new_address
;
8683 growth
= new_size
- old_size
;
8685 /* Fix up the text_expansion field and return the new growth. */
8686 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8691 /* Add a NOP instruction. */
8694 relax_frag_add_nop (fragS
*fragP
)
8696 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8697 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8698 assemble_nop (length
, nop_buf
);
8699 fragP
->tc_frag_data
.is_insn
= TRUE
;
8701 if (fragP
->fr_var
< length
)
8703 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8707 fragP
->fr_fix
+= length
;
8708 fragP
->fr_var
-= length
;
8713 static long future_alignment_required (fragS
*, long);
8716 relax_frag_for_align (fragS
*fragP
, long stretch
)
8718 /* Overview of the relaxation procedure for alignment:
8719 We can widen with NOPs or by widening instructions or by filling
8720 bytes after jump instructions. Find the opportune places and widen
8721 them if necessary. */
8726 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8727 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8728 || (fragP
->fr_subtype
== RELAX_SLOTS
8729 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8731 stretch_me
= future_alignment_required (fragP
, stretch
);
8732 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8738 /* We expanded on a previous pass. Can we shrink now? */
8739 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8740 if (shrink
<= stretch
&& stretch
> 0)
8742 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8748 /* Below here, diff > 0. */
8749 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8755 /* Return the address of the next frag that should be aligned.
8757 By "address" we mean the address it _would_ be at if there
8758 is no action taken to align it between here and the target frag.
8759 In other words, if no narrows and no fill nops are used between
8760 here and the frag to align, _even_if_ some of the frags we use
8761 to align targets have already expanded on a previous relaxation
8764 Also, count each frag that may be used to help align the target.
8766 Return 0 if there are no frags left in the chain that need to be
8770 find_address_of_next_align_frag (fragS
**fragPP
,
8774 bfd_boolean
*paddable
)
8776 fragS
*fragP
= *fragPP
;
8777 addressT address
= fragP
->fr_address
;
8779 /* Do not reset the counts to 0. */
8783 /* Limit this to a small search. */
8784 if (*widens
>= (int) xtensa_fetch_width
)
8789 address
+= fragP
->fr_fix
;
8791 if (fragP
->fr_type
== rs_fill
)
8792 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8793 else if (fragP
->fr_type
== rs_machine_dependent
)
8795 switch (fragP
->fr_subtype
)
8797 case RELAX_UNREACHABLE
:
8801 case RELAX_FILL_NOP
:
8803 if (!fragP
->tc_frag_data
.is_no_density
)
8808 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8813 address
+= total_frag_text_expansion (fragP
);;
8817 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8820 case RELAX_ALIGN_NEXT_OPCODE
:
8821 case RELAX_DESIRE_ALIGN
:
8825 case RELAX_MAYBE_UNREACHABLE
:
8826 case RELAX_MAYBE_DESIRE_ALIGN
:
8831 /* Just punt if we don't know the type. */
8838 /* Just punt if we don't know the type. */
8842 fragP
= fragP
->fr_next
;
8850 static long bytes_to_stretch (fragS
*, int, int, int, int);
8853 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8855 fragS
*this_frag
= fragP
;
8859 int narrow_nops
= 0;
8860 bfd_boolean paddable
= FALSE
;
8861 offsetT local_opt_diff
;
8864 int stretch_amount
= 0;
8865 int local_stretch_amount
;
8866 int global_stretch_amount
;
8868 address
= find_address_of_next_align_frag
8869 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8873 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8874 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8876 frag_wane (this_frag
);
8880 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8881 opt_diff
= local_opt_diff
;
8882 gas_assert (opt_diff
>= 0);
8883 gas_assert (max_diff
>= opt_diff
);
8888 fragP
= fragP
->fr_next
;
8890 while (fragP
&& opt_diff
< max_diff
&& address
)
8892 /* We only use these to determine if we can exit early
8893 because there will be plenty of ways to align future
8895 int glob_widens
= 0;
8898 bfd_boolean glob_pad
= 0;
8899 address
= find_address_of_next_align_frag
8900 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8901 /* If there is a padable portion, then skip. */
8902 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8907 offsetT next_m_diff
;
8908 offsetT next_o_diff
;
8910 /* Downrange frags haven't had stretch added to them yet. */
8913 /* The address also includes any text expansion from this
8914 frag in a previous pass, but we don't want that. */
8915 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8917 /* Assume we are going to move at least opt_diff. In
8918 reality, we might not be able to, but assuming that
8919 we will helps catch cases where moving opt_diff pushes
8920 the next target from aligned to unaligned. */
8921 address
+= opt_diff
;
8923 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8925 /* Now cleanup for the adjustments to address. */
8926 next_o_diff
+= opt_diff
;
8927 next_m_diff
+= opt_diff
;
8928 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8929 opt_diff
= next_o_diff
;
8930 if (next_m_diff
< max_diff
)
8931 max_diff
= next_m_diff
;
8932 fragP
= fragP
->fr_next
;
8936 /* If there are enough wideners in between, do it. */
8939 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8941 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
8946 local_stretch_amount
8947 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8948 num_widens
, local_opt_diff
);
8949 global_stretch_amount
8950 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8951 num_widens
, opt_diff
);
8952 /* If the condition below is true, then the frag couldn't
8953 stretch the correct amount for the global case, so we just
8954 optimize locally. We'll rely on the subsequent frags to get
8955 the correct alignment in the global case. */
8956 if (global_stretch_amount
< local_stretch_amount
)
8957 stretch_amount
= local_stretch_amount
;
8959 stretch_amount
= global_stretch_amount
;
8961 if (this_frag
->fr_subtype
== RELAX_SLOTS
8962 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8963 gas_assert (stretch_amount
<= 1);
8964 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8966 if (this_frag
->tc_frag_data
.is_no_density
)
8967 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
8969 gas_assert (stretch_amount
<= 3);
8972 return stretch_amount
;
8976 /* The idea: widen everything you can to get a target or loop aligned,
8977 then start using NOPs.
8979 When we must have a NOP, here is a table of how we decide
8980 (so you don't have to fight through the control flow below):
8982 wide_nops = the number of wide NOPs available for aligning
8983 narrow_nops = the number of narrow NOPs available for aligning
8984 (a subset of wide_nops)
8985 widens = the number of narrow instructions that should be widened
8992 b 0 1 1 (case 3a makes this case unnecessary)
8995 c 0 1 2 (case 4a makes this case unnecessary)
8998 c 0 2 1 (case 5b makes this case unnecessary)
9001 c 0 1 4 (case 6b makes this case unnecessary)
9002 d 1 1 1 (case 6a makes this case unnecessary)
9003 e 0 2 2 (case 6a makes this case unnecessary)
9004 f 0 3 0 (case 6a makes this case unnecessary)
9007 c 1 1 2 (case 7b makes this case unnecessary)
9008 d 0 1 5 (case 7a makes this case unnecessary)
9009 e 0 2 3 (case 7b makes this case unnecessary)
9010 f 0 3 1 (case 7b makes this case unnecessary)
9011 g 1 2 1 (case 7b makes this case unnecessary)
9015 bytes_to_stretch (fragS
*this_frag
,
9021 int bytes_short
= desired_diff
- num_widens
;
9023 gas_assert (desired_diff
>= 0
9024 && desired_diff
< (signed) xtensa_fetch_width
);
9025 if (desired_diff
== 0)
9028 gas_assert (wide_nops
> 0 || num_widens
> 0);
9030 /* Always prefer widening to NOP-filling. */
9031 if (bytes_short
< 0)
9033 /* There are enough RELAX_NARROW frags after this one
9034 to align the target without widening this frag in any way. */
9038 if (bytes_short
== 0)
9040 /* Widen every narrow between here and the align target
9041 and the align target will be properly aligned. */
9042 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9048 /* From here we will need at least one NOP to get an alignment.
9049 However, we may not be able to align at all, in which case,
9051 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9053 switch (desired_diff
)
9058 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
9059 return 2; /* case 2 */
9065 return 3; /* case 3a */
9067 if (num_widens
>= 1 && wide_nops
== 1)
9068 return 3; /* case 4a */
9069 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
9070 return 2; /* case 4b */
9073 if (num_widens
>= 2 && wide_nops
== 1)
9074 return 3; /* case 5a */
9075 /* We will need two nops. Are there enough nops
9076 between here and the align target? */
9077 if (wide_nops
< 2 || narrow_nops
== 0)
9079 /* Are there other nops closer that can serve instead? */
9080 if (wide_nops
> 2 && narrow_nops
> 1)
9082 /* Take the density one first, because there might not be
9083 another density one available. */
9084 if (!this_frag
->tc_frag_data
.is_no_density
)
9085 return 2; /* case 5b narrow */
9087 return 3; /* case 5b wide */
9091 return 3; /* case 6a */
9092 else if (num_widens
>= 3 && wide_nops
== 1)
9093 return 3; /* case 6b */
9096 if (wide_nops
== 1 && num_widens
>= 4)
9097 return 3; /* case 7a */
9098 else if (wide_nops
== 2 && num_widens
>= 1)
9099 return 3; /* case 7b */
9107 /* We will need a NOP no matter what, but should we widen
9108 this instruction to help?
9110 This is a RELAX_NARROW frag. */
9111 switch (desired_diff
)
9120 if (wide_nops
>= 1 && num_widens
== 1)
9121 return 1; /* case 4a */
9124 if (wide_nops
>= 1 && num_widens
== 2)
9125 return 1; /* case 5a */
9129 return 0; /* case 6a */
9130 else if (wide_nops
>= 1 && num_widens
== 3)
9131 return 1; /* case 6b */
9134 if (wide_nops
>= 1 && num_widens
== 4)
9135 return 1; /* case 7a */
9136 else if (wide_nops
>= 2 && num_widens
== 1)
9137 return 1; /* case 7b */
9150 relax_frag_immed (segT segP
,
9157 bfd_boolean estimate_only
)
9161 bfd_boolean negatable_branch
= FALSE
;
9162 bfd_boolean branch_jmp_to_next
= FALSE
;
9163 bfd_boolean from_wide_insn
= FALSE
;
9164 xtensa_isa isa
= xtensa_default_isa
;
9166 offsetT frag_offset
;
9168 int num_text_bytes
, num_literal_bytes
;
9169 int literal_diff
, total_text_diff
, this_text_diff
;
9171 gas_assert (fragP
->fr_opcode
!= NULL
);
9173 xg_clear_vinsn (&cur_vinsn
);
9174 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9175 if (cur_vinsn
.num_slots
> 1)
9176 from_wide_insn
= TRUE
;
9178 tinsn
= cur_vinsn
.slots
[slot
];
9179 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9181 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9184 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9185 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9187 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9189 old_size
= xtensa_format_length (isa
, fmt
);
9191 /* Special case: replace a branch to the next instruction with a NOP.
9192 This is required to work around a hardware bug in T1040.0 and also
9193 serves as an optimization. */
9195 if (branch_jmp_to_next
9196 && ((old_size
== 2) || (old_size
== 3))
9197 && !next_frag_is_loop_target (fragP
))
9200 /* Here is the fun stuff: Get the immediate field from this
9201 instruction. If it fits, we are done. If not, find the next
9202 instruction sequence that fits. */
9204 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9205 istack_init (&istack
);
9206 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9207 min_steps
, stretch
);
9208 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9210 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9212 /* Figure out the number of bytes needed. */
9213 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9215 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9216 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9221 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9224 num_text_bytes
+= old_size
;
9225 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9226 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9229 /* The first instruction in the relaxed sequence will go after
9230 the current wide instruction, and thus its symbolic immediates
9233 istack_init (&istack
);
9234 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
9235 frag_offset
+ old_size
,
9236 min_steps
, stretch
+ old_size
);
9237 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9239 fragP
->tc_frag_data
.slot_subtypes
[slot
]
9240 = (int) RELAX_IMMED
+ num_steps
;
9242 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9244 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9246 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
9250 total_text_diff
= num_text_bytes
- old_size
;
9251 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9253 /* It MUST get larger. If not, we could get an infinite loop. */
9254 gas_assert (num_text_bytes
>= 0);
9255 gas_assert (literal_diff
>= 0);
9256 gas_assert (total_text_diff
>= 0);
9258 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9259 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9260 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9261 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9263 /* Find the associated expandable literal for this. */
9264 if (literal_diff
!= 0)
9266 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9269 gas_assert (literal_diff
== 4);
9270 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9272 /* We expect that the literal section state has NOT been
9274 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
9275 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9276 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9278 /* We need to mark this section for another iteration
9284 if (negatable_branch
&& istack
.ninsn
> 1)
9285 update_next_frag_state (fragP
);
9287 return this_text_diff
;
9291 /* md_convert_frag Hook and Helper Functions. */
9293 static void convert_frag_align_next_opcode (fragS
*);
9294 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9295 static void convert_frag_fill_nop (fragS
*);
9296 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9299 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9301 static xtensa_insnbuf vbuf
= NULL
;
9302 xtensa_isa isa
= xtensa_default_isa
;
9309 as_where (&file_name
, &line
);
9310 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9312 switch (fragp
->fr_subtype
)
9314 case RELAX_ALIGN_NEXT_OPCODE
:
9315 /* Always convert. */
9316 convert_frag_align_next_opcode (fragp
);
9319 case RELAX_DESIRE_ALIGN
:
9320 /* Do nothing. If not aligned already, too bad. */
9324 case RELAX_LITERAL_FINAL
:
9329 vbuf
= xtensa_insnbuf_alloc (isa
);
9331 xtensa_insnbuf_from_chars
9332 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9333 fmt
= xtensa_format_decode (isa
, vbuf
);
9334 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9336 for (slot
= 0; slot
< num_slots
; slot
++)
9338 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9341 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9345 case RELAX_IMMED_STEP1
:
9346 case RELAX_IMMED_STEP2
:
9347 case RELAX_IMMED_STEP3
:
9348 /* Place the immediate. */
9351 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9356 /* This is OK because some slots could have
9357 relaxations and others have none. */
9363 case RELAX_UNREACHABLE
:
9364 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9365 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9366 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9370 case RELAX_MAYBE_UNREACHABLE
:
9371 case RELAX_MAYBE_DESIRE_ALIGN
:
9375 case RELAX_FILL_NOP
:
9376 convert_frag_fill_nop (fragp
);
9379 case RELAX_LITERAL_NR
:
9380 if (use_literal_section
)
9382 /* This should have been handled during relaxation. When
9383 relaxing a code segment, literals sometimes need to be
9384 added to the corresponding literal segment. If that
9385 literal segment has already been relaxed, then we end up
9386 in this situation. Marking the literal segments as data
9387 would make this happen less often (since GAS always relaxes
9388 code before data), but we could still get into trouble if
9389 there are instructions in a segment that is not marked as
9390 containing code. Until we can implement a better solution,
9391 cheat and adjust the addresses of all the following frags.
9392 This could break subsequent alignments, but the linker's
9393 literal coalescing will do that anyway. */
9396 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9397 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9398 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9401 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9405 as_bad (_("invalid relaxation fragment result"));
9410 new_logical_line (file_name
, line
);
9415 convert_frag_align_next_opcode (fragS
*fragp
)
9417 char *nop_buf
; /* Location for Writing. */
9418 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9419 addressT aligned_address
;
9423 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9425 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9426 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9427 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9429 for (nop
= 0; nop
< nop_count
; nop
++)
9432 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9434 assemble_nop (nop_size
, nop_buf
);
9435 nop_buf
+= nop_size
;
9438 fragp
->fr_fix
+= fill_size
;
9439 fragp
->fr_var
-= fill_size
;
9444 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9446 TInsn tinsn
, single_target
;
9447 int size
, old_size
, diff
;
9448 offsetT frag_offset
;
9450 gas_assert (slot
== 0);
9451 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9453 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9455 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9456 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9457 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9462 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9464 /* No conversion. */
9469 gas_assert (fragP
->fr_opcode
!= NULL
);
9471 /* Frags in this relaxation state should only contain
9472 single instruction bundles. */
9473 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9475 /* Just convert it to a wide form.... */
9477 old_size
= xg_get_single_size (tinsn
.opcode
);
9479 tinsn_init (&single_target
);
9480 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9482 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9484 as_bad (_("unable to widen instruction"));
9488 size
= xg_get_single_size (single_target
.opcode
);
9489 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9492 diff
= size
- old_size
;
9493 gas_assert (diff
>= 0);
9494 gas_assert (diff
<= fragP
->fr_var
);
9495 fragP
->fr_var
-= diff
;
9496 fragP
->fr_fix
+= diff
;
9504 convert_frag_fill_nop (fragS
*fragP
)
9506 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9507 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9508 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9509 - fragP
->fr_address
- fragP
->fr_fix
));
9512 /* No conversion. */
9516 assemble_nop (size
, loc
);
9517 fragP
->tc_frag_data
.is_insn
= TRUE
;
9518 fragP
->fr_var
-= size
;
9519 fragP
->fr_fix
+= size
;
9524 static fixS
*fix_new_exp_in_seg
9525 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9526 bfd_reloc_code_real_type
);
9527 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9530 convert_frag_immed (segT segP
,
9536 char *immed_instr
= fragP
->fr_opcode
;
9538 bfd_boolean expanded
= FALSE
;
9539 bfd_boolean branch_jmp_to_next
= FALSE
;
9540 char *fr_opcode
= fragP
->fr_opcode
;
9541 xtensa_isa isa
= xtensa_default_isa
;
9542 bfd_boolean from_wide_insn
= FALSE
;
9544 bfd_boolean is_loop
;
9546 gas_assert (fr_opcode
!= NULL
);
9548 xg_clear_vinsn (&cur_vinsn
);
9550 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9551 if (cur_vinsn
.num_slots
> 1)
9552 from_wide_insn
= TRUE
;
9554 orig_tinsn
= cur_vinsn
.slots
[slot
];
9555 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9557 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9559 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9560 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9562 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9564 /* Conversion just inserts a NOP and marks the fix as completed. */
9565 bytes
= xtensa_format_length (isa
, fmt
);
9568 cur_vinsn
.slots
[slot
].opcode
=
9569 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9570 cur_vinsn
.slots
[slot
].ntok
= 0;
9574 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9575 gas_assert (bytes
== 2 || bytes
== 3);
9576 build_nop (&cur_vinsn
.slots
[0], bytes
);
9577 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9579 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9580 xtensa_insnbuf_to_chars
9581 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9586 /* Here is the fun stuff: Get the immediate field from this
9587 instruction. If it fits, we're done. If not, find the next
9588 instruction sequence that fits. */
9592 symbolS
*lit_sym
= NULL
;
9594 int target_offset
= 0;
9597 symbolS
*gen_label
= NULL
;
9598 offsetT frag_offset
;
9599 bfd_boolean first
= TRUE
;
9600 bfd_boolean last_is_jump
;
9602 /* It does not fit. Find something that does and
9603 convert immediately. */
9604 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9605 istack_init (&istack
);
9606 xg_assembly_relax (&istack
, &orig_tinsn
,
9607 segP
, fragP
, frag_offset
, min_steps
, 0);
9609 old_size
= xtensa_format_length (isa
, fmt
);
9611 /* Assemble this right inline. */
9613 /* First, create the mapping from a label name to the REAL label. */
9615 for (i
= 0; i
< istack
.ninsn
; i
++)
9617 TInsn
*tinsn
= &istack
.insn
[i
];
9620 switch (tinsn
->insn_type
)
9623 if (lit_sym
!= NULL
)
9624 as_bad (_("multiple literals in expansion"));
9625 /* First find the appropriate space in the literal pool. */
9626 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9627 if (lit_frag
== NULL
)
9628 as_bad (_("no registered fragment for literal"));
9629 if (tinsn
->ntok
!= 1)
9630 as_bad (_("number of literal tokens != 1"));
9632 /* Set the literal symbol and add a fixup. */
9633 lit_sym
= lit_frag
->fr_symbol
;
9637 if (align_targets
&& !is_loop
)
9639 fragS
*unreach
= fragP
->fr_next
;
9640 while (!(unreach
->fr_type
== rs_machine_dependent
9641 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9642 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9644 unreach
= unreach
->fr_next
;
9647 gas_assert (unreach
->fr_type
== rs_machine_dependent
9648 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9649 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9651 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9653 gas_assert (gen_label
== NULL
);
9654 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9655 fr_opcode
- fragP
->fr_literal
9656 + target_offset
, fragP
);
9660 if (first
&& from_wide_insn
)
9662 target_offset
+= xtensa_format_length (isa
, fmt
);
9664 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9665 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9668 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9675 last_is_jump
= FALSE
;
9676 for (i
= 0; i
< istack
.ninsn
; i
++)
9678 TInsn
*tinsn
= &istack
.insn
[i
];
9682 bfd_reloc_code_real_type reloc_type
;
9684 switch (tinsn
->insn_type
)
9687 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9688 /* Already checked. */
9689 gas_assert (lit_frag
!= NULL
);
9690 gas_assert (lit_sym
!= NULL
);
9691 gas_assert (tinsn
->ntok
== 1);
9693 target_seg
= S_GET_SEGMENT (lit_sym
);
9694 gas_assert (target_seg
);
9695 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
9696 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9697 &tinsn
->tok
[0], FALSE
, reloc_type
);
9704 xg_resolve_labels (tinsn
, gen_label
);
9705 xg_resolve_literals (tinsn
, lit_sym
);
9706 if (from_wide_insn
&& first
)
9709 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9711 cur_vinsn
.slots
[slot
] = *tinsn
;
9715 cur_vinsn
.slots
[slot
].opcode
=
9716 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9717 cur_vinsn
.slots
[slot
].ntok
= 0;
9719 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9720 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9721 (unsigned char *) immed_instr
, 0);
9722 fragP
->tc_frag_data
.is_insn
= TRUE
;
9723 size
= xtensa_format_length (isa
, fmt
);
9724 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9727 (tinsn
, immed_instr
+ size
, fragP
,
9728 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9729 size
+= xg_get_single_size (tinsn
->opcode
);
9734 size
= xg_get_single_size (tinsn
->opcode
);
9735 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9736 immed_instr
- fragP
->fr_literal
, TRUE
);
9738 immed_instr
+= size
;
9744 diff
= total_size
- old_size
;
9745 gas_assert (diff
>= 0);
9748 gas_assert (diff
<= fragP
->fr_var
);
9749 fragP
->fr_var
-= diff
;
9750 fragP
->fr_fix
+= diff
;
9753 /* Check for undefined immediates in LOOP instructions. */
9757 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9758 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9760 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9763 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9764 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9766 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9771 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9772 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9774 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9776 /* Add an expansion note on the expanded instruction. */
9777 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9778 &orig_tinsn
.tok
[0], TRUE
,
9779 BFD_RELOC_XTENSA_ASM_EXPAND
);
9784 /* Add a new fix expression into the desired segment. We have to
9785 switch to that segment to do this. */
9788 fix_new_exp_in_seg (segT new_seg
,
9795 bfd_reloc_code_real_type r_type
)
9799 subsegT subseg
= now_subseg
;
9801 gas_assert (new_seg
!= 0);
9802 subseg_set (new_seg
, new_subseg
);
9804 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9805 subseg_set (seg
, subseg
);
9810 /* Relax a loop instruction so that it can span loop >256 bytes.
9816 addi as, as, lo8 (label-.L1)
9817 addmi as, as, mid8 (label-.L1)
9828 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9833 unsigned long target
;
9834 static xtensa_insnbuf insnbuf
= NULL
;
9835 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9836 xtensa_isa isa
= xtensa_default_isa
;
9837 addressT loop_offset
;
9838 addressT addi_offset
= 9;
9839 addressT addmi_offset
= 12;
9844 insnbuf
= xtensa_insnbuf_alloc (isa
);
9846 /* Get the loop offset. */
9847 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9849 /* Validate that there really is a LOOP at the loop_offset. Because
9850 loops are not bundleable, we can assume that the instruction will be
9852 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9853 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9855 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9856 addi_offset
+= loop_offset
;
9857 addmi_offset
+= loop_offset
;
9859 gas_assert (tinsn
->ntok
== 2);
9860 if (tinsn
->tok
[1].X_op
== O_constant
)
9861 target
= tinsn
->tok
[1].X_add_number
;
9862 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9864 /* Find the fragment. */
9865 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9866 gas_assert (S_GET_SEGMENT (sym
) == segP
9867 || S_GET_SEGMENT (sym
) == absolute_section
);
9868 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9872 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9876 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9877 loop_length_hi
= loop_length
& ~0x0ff;
9878 loop_length_lo
= loop_length
& 0x0ff;
9879 if (loop_length_lo
>= 128)
9881 loop_length_lo
-= 256;
9882 loop_length_hi
+= 256;
9885 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9886 32512. If the loop is larger than that, then we just fail. */
9887 if (loop_length_hi
> 32512)
9888 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9889 _("loop too long for LOOP instruction"));
9891 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9892 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9894 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9895 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9897 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9898 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9900 fragP
->tc_frag_data
.is_insn
= TRUE
;
9901 xtensa_insnbuf_to_chars
9902 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9904 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9905 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9906 xtensa_insnbuf_to_chars
9907 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9909 /* Walk through all of the frags from here to the loop end
9910 and mark them as no_transform to keep them from being modified
9911 by the linker. If we ever have a relocation for the
9912 addi/addmi of the difference of two symbols we can remove this. */
9915 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9916 next_fragP
= next_fragP
->fr_next
)
9918 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9919 if (next_fragP
->tc_frag_data
.is_loop_target
)
9921 if (target_count
== 2)
9927 /* A map that keeps information on a per-subsegment basis. This is
9928 maintained during initial assembly, but is invalid once the
9929 subsegments are smashed together. I.E., it cannot be used during
9932 typedef struct subseg_map_struct
9940 float total_freq
; /* fall-through + branch target frequency */
9941 float target_freq
; /* branch target frequency alone */
9943 struct subseg_map_struct
*next
;
9947 static subseg_map
*sseg_map
= NULL
;
9950 get_subseg_info (segT seg
, subsegT subseg
)
9952 subseg_map
*subseg_e
;
9954 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9956 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9964 add_subseg_info (segT seg
, subsegT subseg
)
9966 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9967 memset (subseg_e
, 0, sizeof (subseg_map
));
9968 subseg_e
->seg
= seg
;
9969 subseg_e
->subseg
= subseg
;
9970 subseg_e
->flags
= 0;
9971 /* Start off considering every branch target very important. */
9972 subseg_e
->target_freq
= 1.0;
9973 subseg_e
->total_freq
= 1.0;
9974 subseg_e
->next
= sseg_map
;
9975 sseg_map
= subseg_e
;
9981 get_last_insn_flags (segT seg
, subsegT subseg
)
9983 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9985 return subseg_e
->flags
;
9991 set_last_insn_flags (segT seg
,
9996 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9998 subseg_e
= add_subseg_info (seg
, subseg
);
10000 subseg_e
->flags
|= fl
;
10002 subseg_e
->flags
&= ~fl
;
10007 get_subseg_total_freq (segT seg
, subsegT subseg
)
10009 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10011 return subseg_e
->total_freq
;
10017 get_subseg_target_freq (segT seg
, subsegT subseg
)
10019 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10021 return subseg_e
->target_freq
;
10027 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
10029 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10031 subseg_e
= add_subseg_info (seg
, subseg
);
10032 subseg_e
->total_freq
= total_f
;
10033 subseg_e
->target_freq
= target_f
;
10037 /* Segment Lists and emit_state Stuff. */
10040 xtensa_move_seg_list_to_beginning (seg_list
*head
)
10045 segT literal_section
= head
->seg
;
10047 /* Move the literal section to the front of the section list. */
10048 gas_assert (literal_section
);
10049 if (literal_section
!= stdoutput
->sections
)
10051 bfd_section_list_remove (stdoutput
, literal_section
);
10052 bfd_section_list_prepend (stdoutput
, literal_section
);
10059 static void mark_literal_frags (seg_list
*);
10062 xtensa_move_literals (void)
10065 frchainS
*frchain_from
, *frchain_to
;
10066 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
10067 fragS
**frag_splice
;
10070 fixS
*fix
, *next_fix
, **fix_splice
;
10073 mark_literal_frags (literal_head
->next
);
10075 if (use_literal_section
)
10078 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
10080 /* Keep the literals for .init and .fini in separate sections. */
10081 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
10082 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
10085 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10086 search_frag
= frchain_from
->frch_root
;
10087 literal_pool
= NULL
;
10089 frag_splice
= &(frchain_from
->frch_root
);
10091 while (!search_frag
->tc_frag_data
.literal_frag
)
10093 gas_assert (search_frag
->fr_fix
== 0
10094 || search_frag
->fr_type
== rs_align
);
10095 search_frag
= search_frag
->fr_next
;
10098 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10099 == RELAX_LITERAL_POOL_BEGIN
);
10100 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10102 /* Make sure that all the frags in this series are closed, and
10103 that there is at least one left over of zero-size. This
10104 prevents us from making a segment with an frchain without any
10106 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10107 xtensa_set_frag_assembly_state (frag_now
);
10108 last_frag
= frag_now
;
10109 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10110 xtensa_set_frag_assembly_state (frag_now
);
10112 while (search_frag
!= frag_now
)
10114 next_frag
= search_frag
->fr_next
;
10116 /* First, move the frag out of the literal section and
10117 to the appropriate place. */
10118 if (search_frag
->tc_frag_data
.literal_frag
)
10120 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10121 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10122 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
10123 gas_assert (frchain_to
);
10125 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
10126 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
10128 *frag_splice
= next_frag
;
10129 search_frag
->fr_next
= insert_after
->fr_next
;
10130 insert_after
->fr_next
= search_frag
;
10131 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10132 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
10134 /* Now move any fixups associated with this frag to the
10136 fix
= frchain_from
->fix_root
;
10137 fix_splice
= &(frchain_from
->fix_root
);
10140 next_fix
= fix
->fx_next
;
10141 if (fix
->fx_frag
== search_frag
)
10143 *fix_splice
= next_fix
;
10144 fix
->fx_next
= frchain_to
->fix_root
;
10145 frchain_to
->fix_root
= fix
;
10146 if (frchain_to
->fix_tail
== NULL
)
10147 frchain_to
->fix_tail
= fix
;
10150 fix_splice
= &(fix
->fx_next
);
10153 search_frag
= next_frag
;
10156 if (frchain_from
->fix_root
!= NULL
)
10158 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10159 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10161 gas_assert (frchain_from
->fix_root
== NULL
);
10163 frchain_from
->fix_tail
= NULL
;
10164 xtensa_restore_emit_state (&state
);
10167 /* Now fix up the SEGMENT value for all the literal symbols. */
10168 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10170 symbolS
*lit_sym
= lit
->sym
;
10171 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10173 S_SET_SEGMENT (lit_sym
, dseg
);
10178 /* Walk over all the frags for segments in a list and mark them as
10179 containing literals. As clunky as this is, we can't rely on frag_var
10180 and frag_variant to get called in all situations. */
10183 mark_literal_frags (seg_list
*segment
)
10185 frchainS
*frchain_from
;
10186 fragS
*search_frag
;
10190 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10191 search_frag
= frchain_from
->frch_root
;
10192 while (search_frag
)
10194 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10195 search_frag
= search_frag
->fr_next
;
10197 segment
= segment
->next
;
10203 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10205 /* Move all of the sections in the section list to come
10206 after "after" in the gnu segment list. */
10211 segT literal_section
= head
->seg
;
10213 /* Move the literal section after "after". */
10214 gas_assert (literal_section
);
10215 if (literal_section
!= after
)
10217 bfd_section_list_remove (stdoutput
, literal_section
);
10218 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10226 /* Push all the literal segments to the end of the gnu list. */
10229 xtensa_reorder_segments (void)
10236 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10242 /* Now that we have the last section, push all the literal
10243 sections to the end. */
10244 xtensa_reorder_seg_list (literal_head
, last_sec
);
10246 /* Now perform the final error check. */
10247 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10249 gas_assert (new_count
== old_count
);
10253 /* Change the emit state (seg, subseg, and frag related stuff) to the
10254 correct location. Return a emit_state which can be passed to
10255 xtensa_restore_emit_state to return to current fragment. */
10258 xtensa_switch_to_literal_fragment (emit_state
*result
)
10260 if (directive_state
[directive_absolute_literals
])
10262 segT lit4_seg
= cache_literal_section (TRUE
);
10263 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10266 xtensa_switch_to_non_abs_literal_fragment (result
);
10268 /* Do a 4-byte align here. */
10269 frag_align (2, 0, 0);
10270 record_alignment (now_seg
, 2);
10275 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10277 static bfd_boolean recursive
= FALSE
;
10278 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10280 bfd_boolean is_init
=
10281 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10282 bfd_boolean is_fini
=
10283 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10285 if (pool_location
== NULL
10286 && !use_literal_section
10288 && !is_init
&& ! is_fini
)
10290 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10292 /* When we mark a literal pool location, we want to put a frag in
10293 the literal pool that points to it. But to do that, we want to
10294 switch_to_literal_fragment. But literal sections don't have
10295 literal pools, so their location is always null, so we would
10296 recurse forever. This is kind of hacky, but it works. */
10299 xtensa_mark_literal_pool_location ();
10303 lit_seg
= cache_literal_section (FALSE
);
10304 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10306 if (!use_literal_section
10307 && !is_init
&& !is_fini
10308 && get_literal_pool_location (now_seg
) != pool_location
)
10310 /* Close whatever frag is there. */
10311 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10312 xtensa_set_frag_assembly_state (frag_now
);
10313 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10314 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10315 xtensa_set_frag_assembly_state (frag_now
);
10320 /* Call this function before emitting data into the literal section.
10321 This is a helper function for xtensa_switch_to_literal_fragment.
10322 This is similar to a .section new_now_seg subseg. */
10325 xtensa_switch_section_emit_state (emit_state
*state
,
10327 subsegT new_now_subseg
)
10329 state
->name
= now_seg
->name
;
10330 state
->now_seg
= now_seg
;
10331 state
->now_subseg
= now_subseg
;
10332 state
->generating_literals
= generating_literals
;
10333 generating_literals
++;
10334 subseg_set (new_now_seg
, new_now_subseg
);
10338 /* Use to restore the emitting into the normal place. */
10341 xtensa_restore_emit_state (emit_state
*state
)
10343 generating_literals
= state
->generating_literals
;
10344 subseg_set (state
->now_seg
, state
->now_subseg
);
10348 /* Predicate function used to look up a section in a particular group. */
10351 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10353 const char *gname
= inf
;
10354 const char *group_name
= elf_group_name (sec
);
10356 return (group_name
== gname
10357 || (group_name
!= NULL
10359 && strcmp (group_name
, gname
) == 0));
10363 /* Get the literal section to be used for the current text section.
10364 The result may be cached in the default_lit_sections structure. */
10367 cache_literal_section (bfd_boolean use_abs_literals
)
10369 const char *text_name
, *group_name
= 0;
10370 char *base_name
, *name
, *suffix
;
10372 segT seg
, current_section
;
10373 int current_subsec
;
10374 bfd_boolean linkonce
= FALSE
;
10376 /* Save the current section/subsection. */
10377 current_section
= now_seg
;
10378 current_subsec
= now_subseg
;
10380 /* Clear the cached values if they are no longer valid. */
10381 if (now_seg
!= default_lit_sections
.current_text_seg
)
10383 default_lit_sections
.current_text_seg
= now_seg
;
10384 default_lit_sections
.lit_seg
= NULL
;
10385 default_lit_sections
.lit4_seg
= NULL
;
10388 /* Check if the literal section is already cached. */
10389 if (use_abs_literals
)
10390 pcached
= &default_lit_sections
.lit4_seg
;
10392 pcached
= &default_lit_sections
.lit_seg
;
10397 text_name
= default_lit_sections
.lit_prefix
;
10398 if (! text_name
|| ! *text_name
)
10400 text_name
= segment_name (current_section
);
10401 group_name
= elf_group_name (current_section
);
10402 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10405 base_name
= use_abs_literals
? ".lit4" : ".literal";
10408 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10409 sprintf (name
, "%s.%s", base_name
, group_name
);
10411 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10413 suffix
= strchr (text_name
+ linkonce_len
, '.');
10415 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10416 + (suffix
? strlen (suffix
) : 0));
10417 strcpy (name
, ".gnu.linkonce");
10418 strcat (name
, base_name
);
10420 strcat (name
, suffix
);
10425 /* If the section name ends with ".text", then replace that suffix
10426 instead of appending an additional suffix. */
10427 size_t len
= strlen (text_name
);
10428 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10431 name
= xmalloc (len
+ strlen (base_name
) + 1);
10432 strcpy (name
, text_name
);
10433 strcpy (name
+ len
, base_name
);
10436 /* Canonicalize section names to allow renaming literal sections.
10437 The group name, if any, came from the current text section and
10438 has already been canonicalized. */
10439 name
= tc_canonicalize_symbol_name (name
);
10441 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10442 (void *) group_name
);
10447 seg
= subseg_force_new (name
, 0);
10449 if (! use_abs_literals
)
10451 /* Add the newly created literal segment to the list. */
10452 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10454 n
->next
= literal_head
->next
;
10455 literal_head
->next
= n
;
10458 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10459 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10460 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10462 elf_group_name (seg
) = group_name
;
10464 bfd_set_section_flags (stdoutput
, seg
, flags
);
10465 bfd_set_section_alignment (stdoutput
, seg
, 2);
10469 subseg_set (current_section
, current_subsec
);
10474 /* Property Tables Stuff. */
10476 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10477 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10478 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10480 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10481 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10483 static bfd_boolean
get_frag_is_literal (const fragS
*);
10484 static void xtensa_create_property_segments
10485 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10486 static void xtensa_create_xproperty_segments
10487 (frag_flags_fn
, const char *, xt_section_type
);
10488 static bfd_boolean
exclude_section_from_property_tables (segT
);
10489 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10490 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10491 static void add_xt_block_frags
10492 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10493 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10494 static void xtensa_frag_flags_init (frag_flags
*);
10495 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10496 static flagword
frag_flags_to_number (const frag_flags
*);
10497 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10499 /* Set up property tables after relaxation. */
10502 xtensa_post_relax_hook (void)
10504 xtensa_move_seg_list_to_beginning (literal_head
);
10506 xtensa_find_unmarked_state_frags ();
10507 xtensa_mark_frags_for_org ();
10508 xtensa_mark_difference_of_two_symbols ();
10510 xtensa_create_property_segments (get_frag_is_literal
,
10512 XTENSA_LIT_SEC_NAME
,
10514 xtensa_create_xproperty_segments (get_frag_property_flags
,
10515 XTENSA_PROP_SEC_NAME
,
10518 if (warn_unaligned_branch_targets
)
10519 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10520 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10524 /* This function is only meaningful after xtensa_move_literals. */
10527 get_frag_is_literal (const fragS
*fragP
)
10529 gas_assert (fragP
!= NULL
);
10530 return fragP
->tc_frag_data
.is_literal
;
10535 xtensa_create_property_segments (frag_predicate property_function
,
10536 frag_predicate end_property_function
,
10537 const char *section_name_base
,
10538 xt_section_type sec_type
)
10542 /* Walk over all of the current segments.
10543 Walk over each fragment
10544 For each non-empty fragment,
10545 Build a property record (append where possible). */
10547 for (seclist
= &stdoutput
->sections
;
10548 seclist
&& *seclist
;
10549 seclist
= &(*seclist
)->next
)
10551 segT sec
= *seclist
;
10553 if (exclude_section_from_property_tables (sec
))
10556 if (section_has_property (sec
, property_function
))
10558 segment_info_type
*xt_seg_info
;
10559 xtensa_block_info
**xt_blocks
;
10560 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10562 prop_sec
->output_section
= prop_sec
;
10563 subseg_set (prop_sec
, 0);
10564 xt_seg_info
= seg_info (prop_sec
);
10565 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10567 /* Walk over all of the frchains here and add new sections. */
10568 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10569 end_property_function
);
10573 /* Now we fill them out.... */
10575 for (seclist
= &stdoutput
->sections
;
10576 seclist
&& *seclist
;
10577 seclist
= &(*seclist
)->next
)
10579 segment_info_type
*seginfo
;
10580 xtensa_block_info
*block
;
10581 segT sec
= *seclist
;
10583 seginfo
= seg_info (sec
);
10584 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10588 xtensa_block_info
*cur_block
;
10590 bfd_size_type rec_size
;
10592 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10595 rec_size
= num_recs
* 8;
10596 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10603 subseg_set (sec
, 0);
10604 frag_data
= frag_more (rec_size
);
10606 for (i
= 0; i
< num_recs
; i
++)
10610 /* Write the fixup. */
10611 gas_assert (cur_block
);
10612 fix
= fix_new (frag_now
, i
* 8, 4,
10613 section_symbol (cur_block
->sec
),
10615 FALSE
, BFD_RELOC_32
);
10616 fix
->fx_file
= "<internal>";
10619 /* Write the length. */
10620 md_number_to_chars (&frag_data
[4 + i
* 8],
10621 cur_block
->size
, 4);
10622 cur_block
= cur_block
->next
;
10624 frag_wane (frag_now
);
10626 frag_wane (frag_now
);
10634 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10635 const char *section_name_base
,
10636 xt_section_type sec_type
)
10640 /* Walk over all of the current segments.
10641 Walk over each fragment.
10642 For each fragment that has instructions,
10643 build an instruction record (append where possible). */
10645 for (seclist
= &stdoutput
->sections
;
10646 seclist
&& *seclist
;
10647 seclist
= &(*seclist
)->next
)
10649 segT sec
= *seclist
;
10651 if (exclude_section_from_property_tables (sec
))
10654 if (section_has_xproperty (sec
, flag_fn
))
10656 segment_info_type
*xt_seg_info
;
10657 xtensa_block_info
**xt_blocks
;
10658 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10660 prop_sec
->output_section
= prop_sec
;
10661 subseg_set (prop_sec
, 0);
10662 xt_seg_info
= seg_info (prop_sec
);
10663 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10665 /* Walk over all of the frchains here and add new sections. */
10666 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10670 /* Now we fill them out.... */
10672 for (seclist
= &stdoutput
->sections
;
10673 seclist
&& *seclist
;
10674 seclist
= &(*seclist
)->next
)
10676 segment_info_type
*seginfo
;
10677 xtensa_block_info
*block
;
10678 segT sec
= *seclist
;
10680 seginfo
= seg_info (sec
);
10681 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10685 xtensa_block_info
*cur_block
;
10687 bfd_size_type rec_size
;
10689 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10692 rec_size
= num_recs
* (8 + 4);
10693 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10694 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10701 subseg_set (sec
, 0);
10702 frag_data
= frag_more (rec_size
);
10704 for (i
= 0; i
< num_recs
; i
++)
10708 /* Write the fixup. */
10709 gas_assert (cur_block
);
10710 fix
= fix_new (frag_now
, i
* 12, 4,
10711 section_symbol (cur_block
->sec
),
10713 FALSE
, BFD_RELOC_32
);
10714 fix
->fx_file
= "<internal>";
10717 /* Write the length. */
10718 md_number_to_chars (&frag_data
[4 + i
* 12],
10719 cur_block
->size
, 4);
10720 md_number_to_chars (&frag_data
[8 + i
* 12],
10721 frag_flags_to_number (&cur_block
->flags
),
10722 sizeof (flagword
));
10723 cur_block
= cur_block
->next
;
10725 frag_wane (frag_now
);
10727 frag_wane (frag_now
);
10735 exclude_section_from_property_tables (segT sec
)
10737 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
10739 /* Sections that don't contribute to the memory footprint are excluded. */
10740 if ((flags
& SEC_DEBUGGING
)
10741 || !(flags
& SEC_ALLOC
)
10742 || (flags
& SEC_MERGE
))
10745 /* Linker cie and fde optimizations mess up property entries for
10746 eh_frame sections, but there is nothing inside them relevant to
10747 property tables anyway. */
10748 if (strcmp (sec
->name
, ".eh_frame") == 0)
10756 section_has_property (segT sec
, frag_predicate property_function
)
10758 segment_info_type
*seginfo
= seg_info (sec
);
10761 if (seginfo
&& seginfo
->frchainP
)
10763 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10765 if (property_function (fragP
)
10766 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10775 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10777 segment_info_type
*seginfo
= seg_info (sec
);
10780 if (seginfo
&& seginfo
->frchainP
)
10782 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10784 frag_flags prop_flags
;
10785 property_function (fragP
, &prop_flags
);
10786 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10794 /* Two types of block sections exist right now: literal and insns. */
10797 add_xt_block_frags (segT sec
,
10798 xtensa_block_info
**xt_block
,
10799 frag_predicate property_function
,
10800 frag_predicate end_property_function
)
10804 /* Build it if needed. */
10805 while (*xt_block
!= NULL
)
10806 xt_block
= &(*xt_block
)->next
;
10807 /* We are either at NULL at the beginning or at the end. */
10809 /* Walk through the frags. */
10810 if (seg_info (sec
)->frchainP
)
10812 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10814 fragP
= fragP
->fr_next
)
10816 if (property_function (fragP
)
10817 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10819 if (*xt_block
!= NULL
)
10821 if ((*xt_block
)->offset
+ (*xt_block
)->size
10822 == fragP
->fr_address
)
10823 (*xt_block
)->size
+= fragP
->fr_fix
;
10825 xt_block
= &((*xt_block
)->next
);
10827 if (*xt_block
== NULL
)
10829 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10830 xmalloc (sizeof (xtensa_block_info
));
10831 new_block
->sec
= sec
;
10832 new_block
->offset
= fragP
->fr_address
;
10833 new_block
->size
= fragP
->fr_fix
;
10834 new_block
->next
= NULL
;
10835 xtensa_frag_flags_init (&new_block
->flags
);
10836 *xt_block
= new_block
;
10838 if (end_property_function
10839 && end_property_function (fragP
))
10841 xt_block
= &((*xt_block
)->next
);
10849 /* Break the encapsulation of add_xt_prop_frags here. */
10852 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10854 if (prop_flags
->is_literal
10855 || prop_flags
->is_insn
10856 || prop_flags
->is_data
10857 || prop_flags
->is_unreachable
)
10864 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10866 memset (prop_flags
, 0, sizeof (frag_flags
));
10871 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10873 xtensa_frag_flags_init (prop_flags
);
10874 if (fragP
->tc_frag_data
.is_literal
)
10875 prop_flags
->is_literal
= TRUE
;
10876 if (fragP
->tc_frag_data
.is_specific_opcode
10877 || fragP
->tc_frag_data
.is_no_transform
)
10879 prop_flags
->is_no_transform
= TRUE
;
10880 if (xtensa_frag_flags_is_empty (prop_flags
))
10881 prop_flags
->is_data
= TRUE
;
10883 if (fragP
->tc_frag_data
.is_unreachable
)
10884 prop_flags
->is_unreachable
= TRUE
;
10885 else if (fragP
->tc_frag_data
.is_insn
)
10887 prop_flags
->is_insn
= TRUE
;
10888 if (fragP
->tc_frag_data
.is_loop_target
)
10889 prop_flags
->insn
.is_loop_target
= TRUE
;
10890 if (fragP
->tc_frag_data
.is_branch_target
)
10891 prop_flags
->insn
.is_branch_target
= TRUE
;
10892 if (fragP
->tc_frag_data
.is_no_density
)
10893 prop_flags
->insn
.is_no_density
= TRUE
;
10894 if (fragP
->tc_frag_data
.use_absolute_literals
)
10895 prop_flags
->insn
.is_abslit
= TRUE
;
10897 if (fragP
->tc_frag_data
.is_align
)
10899 prop_flags
->is_align
= TRUE
;
10900 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10901 if (xtensa_frag_flags_is_empty (prop_flags
))
10902 prop_flags
->is_data
= TRUE
;
10908 frag_flags_to_number (const frag_flags
*prop_flags
)
10911 if (prop_flags
->is_literal
)
10912 num
|= XTENSA_PROP_LITERAL
;
10913 if (prop_flags
->is_insn
)
10914 num
|= XTENSA_PROP_INSN
;
10915 if (prop_flags
->is_data
)
10916 num
|= XTENSA_PROP_DATA
;
10917 if (prop_flags
->is_unreachable
)
10918 num
|= XTENSA_PROP_UNREACHABLE
;
10919 if (prop_flags
->insn
.is_loop_target
)
10920 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10921 if (prop_flags
->insn
.is_branch_target
)
10923 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10924 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10927 if (prop_flags
->insn
.is_no_density
)
10928 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10929 if (prop_flags
->is_no_transform
)
10930 num
|= XTENSA_PROP_NO_TRANSFORM
;
10931 if (prop_flags
->insn
.is_no_reorder
)
10932 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10933 if (prop_flags
->insn
.is_abslit
)
10934 num
|= XTENSA_PROP_INSN_ABSLIT
;
10936 if (prop_flags
->is_align
)
10938 num
|= XTENSA_PROP_ALIGN
;
10939 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10947 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10948 const frag_flags
*prop_flags_2
)
10950 /* Cannot combine with an end marker. */
10952 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10954 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10956 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10959 if (prop_flags_1
->is_insn
)
10961 /* Properties of the beginning of the frag. */
10962 if (prop_flags_2
->insn
.is_loop_target
)
10964 if (prop_flags_2
->insn
.is_branch_target
)
10966 if (prop_flags_1
->insn
.is_no_density
!=
10967 prop_flags_2
->insn
.is_no_density
)
10969 if (prop_flags_1
->is_no_transform
!=
10970 prop_flags_2
->is_no_transform
)
10972 if (prop_flags_1
->insn
.is_no_reorder
!=
10973 prop_flags_2
->insn
.is_no_reorder
)
10975 if (prop_flags_1
->insn
.is_abslit
!=
10976 prop_flags_2
->insn
.is_abslit
)
10980 if (prop_flags_1
->is_align
)
10988 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10991 unsigned align_bits
;
10993 if (!xt_block
->flags
.is_align
)
10994 return xt_block
->size
;
10996 end_addr
= xt_block
->offset
+ xt_block
->size
;
10997 align_bits
= xt_block
->flags
.alignment
;
10998 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10999 return end_addr
- xt_block
->offset
;
11004 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
11005 const xtensa_block_info
*xt_block_2
)
11007 if (xt_block
->sec
!= xt_block_2
->sec
)
11009 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
11010 != xt_block_2
->offset
)
11013 if (xt_block_2
->size
== 0
11014 && (!xt_block_2
->flags
.is_unreachable
11015 || xt_block
->flags
.is_unreachable
))
11017 if (xt_block_2
->flags
.is_align
11018 && xt_block
->flags
.is_align
)
11020 /* Nothing needed. */
11021 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11026 if (xt_block_2
->flags
.is_align
)
11028 /* Push alignment to previous entry. */
11029 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11030 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11035 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11036 &xt_block_2
->flags
))
11039 xt_block
->size
+= xt_block_2
->size
;
11041 if (xt_block_2
->flags
.is_align
)
11043 xt_block
->flags
.is_align
= TRUE
;
11044 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11052 add_xt_prop_frags (segT sec
,
11053 xtensa_block_info
**xt_block
,
11054 frag_flags_fn property_function
)
11058 /* Build it if needed. */
11059 while (*xt_block
!= NULL
)
11061 xt_block
= &(*xt_block
)->next
;
11063 /* We are either at NULL at the beginning or at the end. */
11065 /* Walk through the frags. */
11066 if (seg_info (sec
)->frchainP
)
11068 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
11069 fragP
= fragP
->fr_next
)
11071 xtensa_block_info tmp_block
;
11072 tmp_block
.sec
= sec
;
11073 tmp_block
.offset
= fragP
->fr_address
;
11074 tmp_block
.size
= fragP
->fr_fix
;
11075 tmp_block
.next
= NULL
;
11076 property_function (fragP
, &tmp_block
.flags
);
11078 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11079 /* && fragP->fr_fix != 0) */
11081 if ((*xt_block
) == NULL
11082 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11084 xtensa_block_info
*new_block
;
11085 if ((*xt_block
) != NULL
)
11086 xt_block
= &(*xt_block
)->next
;
11087 new_block
= (xtensa_block_info
*)
11088 xmalloc (sizeof (xtensa_block_info
));
11089 *new_block
= tmp_block
;
11090 *xt_block
= new_block
;
11098 /* op_placement_info_table */
11100 /* op_placement_info makes it easier to determine which
11101 ops can go in which slots. */
11104 init_op_placement_info_table (void)
11106 xtensa_isa isa
= xtensa_default_isa
;
11107 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11108 xtensa_opcode opcode
;
11111 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11113 op_placement_table
= (op_placement_info_table
)
11114 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11115 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11117 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11119 op_placement_info
*opi
= &op_placement_table
[opcode
];
11120 /* FIXME: Make tinsn allocation dynamic. */
11121 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
11122 as_fatal (_("too many operands in instruction"));
11123 opi
->narrowest
= XTENSA_UNDEFINED
;
11124 opi
->narrowest_size
= 0x7F;
11125 opi
->narrowest_slot
= 0;
11127 opi
->num_formats
= 0;
11129 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11131 opi
->slots
[fmt
] = 0;
11132 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11134 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11136 int fmt_length
= xtensa_format_length (isa
, fmt
);
11138 set_bit (fmt
, opi
->formats
);
11139 set_bit (slot
, opi
->slots
[fmt
]);
11140 if (fmt_length
< opi
->narrowest_size
11141 || (fmt_length
== opi
->narrowest_size
11142 && (xtensa_format_num_slots (isa
, fmt
)
11143 < xtensa_format_num_slots (isa
,
11146 opi
->narrowest
= fmt
;
11147 opi
->narrowest_size
= fmt_length
;
11148 opi
->narrowest_slot
= slot
;
11153 opi
->num_formats
++;
11156 xtensa_insnbuf_free (isa
, ibuf
);
11161 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11163 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11167 /* If the opcode is available in a single slot format, return its size. */
11170 xg_get_single_size (xtensa_opcode opcode
)
11172 return op_placement_table
[opcode
].narrowest_size
;
11176 static xtensa_format
11177 xg_get_single_format (xtensa_opcode opcode
)
11179 return op_placement_table
[opcode
].narrowest
;
11184 xg_get_single_slot (xtensa_opcode opcode
)
11186 return op_placement_table
[opcode
].narrowest_slot
;
11190 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11193 istack_init (IStack
*stack
)
11195 memset (stack
, 0, sizeof (IStack
));
11201 istack_empty (IStack
*stack
)
11203 return (stack
->ninsn
== 0);
11208 istack_full (IStack
*stack
)
11210 return (stack
->ninsn
== MAX_ISTACK
);
11214 /* Return a pointer to the top IStack entry.
11215 It is an error to call this if istack_empty () is TRUE. */
11218 istack_top (IStack
*stack
)
11220 int rec
= stack
->ninsn
- 1;
11221 gas_assert (!istack_empty (stack
));
11222 return &stack
->insn
[rec
];
11226 /* Add a new TInsn to an IStack.
11227 It is an error to call this if istack_full () is TRUE. */
11230 istack_push (IStack
*stack
, TInsn
*insn
)
11232 int rec
= stack
->ninsn
;
11233 gas_assert (!istack_full (stack
));
11234 stack
->insn
[rec
] = *insn
;
11239 /* Clear space for the next TInsn on the IStack and return a pointer
11240 to it. It is an error to call this if istack_full () is TRUE. */
11243 istack_push_space (IStack
*stack
)
11245 int rec
= stack
->ninsn
;
11247 gas_assert (!istack_full (stack
));
11248 insn
= &stack
->insn
[rec
];
11255 /* Remove the last pushed instruction. It is an error to call this if
11256 istack_empty () returns TRUE. */
11259 istack_pop (IStack
*stack
)
11261 int rec
= stack
->ninsn
- 1;
11262 gas_assert (!istack_empty (stack
));
11264 tinsn_init (&stack
->insn
[rec
]);
11268 /* TInsn functions. */
11271 tinsn_init (TInsn
*dst
)
11273 memset (dst
, 0, sizeof (TInsn
));
11277 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11280 tinsn_has_symbolic_operands (const TInsn
*insn
)
11283 int n
= insn
->ntok
;
11285 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11287 for (i
= 0; i
< n
; ++i
)
11289 switch (insn
->tok
[i
].X_op
)
11303 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11305 xtensa_isa isa
= xtensa_default_isa
;
11307 int n
= insn
->ntok
;
11309 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11311 for (i
= 0; i
< n
; ++i
)
11313 switch (insn
->tok
[i
].X_op
)
11321 /* Errors for these types are caught later. */
11326 /* Symbolic immediates are only allowed on the last immediate
11327 operand. At this time, CONST16 is the only opcode where we
11328 support non-PC-relative relocations. */
11329 if (i
!= get_relaxable_immed (insn
->opcode
)
11330 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11331 && insn
->opcode
!= xtensa_const16_opcode
))
11333 as_bad (_("invalid symbolic operand"));
11342 /* For assembly code with complex expressions (e.g. subtraction),
11343 we have to build them in the literal pool so that
11344 their results are calculated correctly after relaxation.
11345 The relaxation only handles expressions that
11346 boil down to SYMBOL + OFFSET. */
11349 tinsn_has_complex_operands (const TInsn
*insn
)
11352 int n
= insn
->ntok
;
11353 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11354 for (i
= 0; i
< n
; ++i
)
11356 switch (insn
->tok
[i
].X_op
)
11372 /* Encode a TInsn opcode and its constant operands into slotbuf.
11373 Return TRUE if there is a symbol in the immediate field. This
11374 function assumes that:
11375 1) The number of operands are correct.
11376 2) The insn_type is ITYPE_INSN.
11377 3) The opcode can be encoded in the specified format and slot.
11378 4) Operands are either O_constant or O_symbol, and all constants fit. */
11381 tinsn_to_slotbuf (xtensa_format fmt
,
11384 xtensa_insnbuf slotbuf
)
11386 xtensa_isa isa
= xtensa_default_isa
;
11387 xtensa_opcode opcode
= tinsn
->opcode
;
11388 bfd_boolean has_fixup
= FALSE
;
11389 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11392 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
11393 if (noperands
!= tinsn
->ntok
)
11394 as_fatal (_("operand number mismatch"));
11396 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11398 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11399 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11403 for (i
= 0; i
< noperands
; i
++)
11405 expressionS
*exp
= &tinsn
->tok
[i
];
11414 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11416 /* The register number has already been checked in
11417 expression_maybe_register, so we don't need to check here. */
11418 opnd_value
= exp
->X_add_number
;
11419 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11420 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11423 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11427 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11429 as_where (&file_name
, &line
);
11430 /* It is a constant and we called this function
11431 then we have to try to fit it. */
11432 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11433 exp
->X_add_number
, file_name
, line
);
11446 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11447 into a multi-slot instruction, fill the other slots with NOPs.
11448 Return TRUE if there is a symbol in the immediate field. See also the
11449 assumptions listed for tinsn_to_slotbuf. */
11452 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11454 static xtensa_insnbuf slotbuf
= 0;
11455 static vliw_insn vinsn
;
11456 xtensa_isa isa
= xtensa_default_isa
;
11457 bfd_boolean has_fixup
= FALSE
;
11462 slotbuf
= xtensa_insnbuf_alloc (isa
);
11463 xg_init_vinsn (&vinsn
);
11466 xg_clear_vinsn (&vinsn
);
11468 bundle_tinsn (tinsn
, &vinsn
);
11470 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11472 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11474 /* Only one slot may have a fix-up because the rest contains NOPs. */
11476 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11477 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11484 /* Check the instruction arguments. Return TRUE on failure. */
11487 tinsn_check_arguments (const TInsn
*insn
)
11489 xtensa_isa isa
= xtensa_default_isa
;
11490 xtensa_opcode opcode
= insn
->opcode
;
11491 xtensa_regfile t1_regfile
, t2_regfile
;
11492 int t1_reg
, t2_reg
;
11493 int t1_base_reg
, t1_last_reg
;
11494 int t2_base_reg
, t2_last_reg
;
11495 char t1_inout
, t2_inout
;
11498 if (opcode
== XTENSA_UNDEFINED
)
11500 as_bad (_("invalid opcode"));
11504 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11506 as_bad (_("too few operands"));
11510 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11512 as_bad (_("too many operands"));
11516 /* Check registers. */
11517 for (j
= 0; j
< insn
->ntok
; j
++)
11519 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
11522 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
11523 t2_base_reg
= insn
->tok
[j
].X_add_number
;
11525 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
11527 for (i
= 0; i
< insn
->ntok
; i
++)
11532 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
11535 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
11537 if (t1_regfile
!= t2_regfile
)
11540 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
11541 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
11543 t1_base_reg
= insn
->tok
[i
].X_add_number
;
11544 t1_last_reg
= (t1_base_reg
11545 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
11547 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
11549 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
11551 if (t1_reg
!= t2_reg
)
11554 if (t1_inout
!= 'i' && t2_inout
!= 'i')
11556 as_bad (_("multiple writes to the same register"));
11567 /* Load an instruction from its encoded form. */
11570 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11574 xg_init_vinsn (&vinsn
);
11575 vinsn_from_chars (&vinsn
, f
);
11577 *tinsn
= vinsn
.slots
[slot
];
11578 xg_free_vinsn (&vinsn
);
11583 tinsn_from_insnbuf (TInsn
*tinsn
,
11584 xtensa_insnbuf slotbuf
,
11589 xtensa_isa isa
= xtensa_default_isa
;
11591 /* Find the immed. */
11592 tinsn_init (tinsn
);
11593 tinsn
->insn_type
= ITYPE_INSN
;
11594 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11595 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11596 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11597 for (i
= 0; i
< tinsn
->ntok
; i
++)
11599 set_expr_const (&tinsn
->tok
[i
],
11600 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11601 tinsn
->opcode
, i
));
11606 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11609 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11611 xtensa_opcode opcode
= tinsn
->opcode
;
11614 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11616 opnum
= get_relaxable_immed (opcode
);
11617 gas_assert (opnum
>= 0);
11618 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11619 fragP
->tc_frag_data
.slot_symbols
[slot
],
11620 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11622 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
11627 get_num_stack_text_bytes (IStack
*istack
)
11630 int text_bytes
= 0;
11632 for (i
= 0; i
< istack
->ninsn
; i
++)
11634 TInsn
*tinsn
= &istack
->insn
[i
];
11635 if (tinsn
->insn_type
== ITYPE_INSN
)
11636 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11643 get_num_stack_literal_bytes (IStack
*istack
)
11648 for (i
= 0; i
< istack
->ninsn
; i
++)
11650 TInsn
*tinsn
= &istack
->insn
[i
];
11651 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11658 /* vliw_insn functions. */
11661 xg_init_vinsn (vliw_insn
*v
)
11664 xtensa_isa isa
= xtensa_default_isa
;
11666 xg_clear_vinsn (v
);
11668 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11669 if (v
->insnbuf
== NULL
)
11670 as_fatal (_("out of memory"));
11672 for (i
= 0; i
< config_max_slots
; i
++)
11674 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11675 if (v
->slotbuf
[i
] == NULL
)
11676 as_fatal (_("out of memory"));
11682 xg_clear_vinsn (vliw_insn
*v
)
11686 memset (v
, 0, offsetof (vliw_insn
, slots
)
11687 + sizeof(TInsn
) * config_max_slots
);
11689 v
->format
= XTENSA_UNDEFINED
;
11691 v
->inside_bundle
= FALSE
;
11693 if (xt_saved_debug_type
!= DEBUG_NONE
)
11694 debug_type
= xt_saved_debug_type
;
11696 for (i
= 0; i
< config_max_slots
; i
++)
11697 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11702 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
11705 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
11706 dst
->insnbuf
= src
->insnbuf
;
11707 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
11712 vinsn_has_specific_opcodes (vliw_insn
*v
)
11716 for (i
= 0; i
< v
->num_slots
; i
++)
11718 if (v
->slots
[i
].is_specific_opcode
)
11726 xg_free_vinsn (vliw_insn
*v
)
11729 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11730 for (i
= 0; i
< config_max_slots
; i
++)
11731 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11735 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11736 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11739 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11742 bfd_boolean record_fixup
)
11744 xtensa_isa isa
= xtensa_default_isa
;
11745 xtensa_format fmt
= vinsn
->format
;
11746 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11748 bfd_boolean has_fixup
= FALSE
;
11750 xtensa_format_encode (isa
, fmt
, insnbuf
);
11752 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11754 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11755 expressionS
*extra_arg
= &tinsn
->extra_arg
;
11756 bfd_boolean tinsn_has_fixup
=
11757 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11758 vinsn
->slotbuf
[slot
]);
11760 xtensa_format_set_slot (isa
, fmt
, slot
,
11761 insnbuf
, vinsn
->slotbuf
[slot
]);
11762 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
11764 if (vinsn
->num_slots
!= 1)
11765 as_bad (_("TLS relocation not allowed in FLIX bundle"));
11766 else if (record_fixup
)
11767 /* Instructions that generate TLS relocations should always be
11768 relaxed in the front-end. If "record_fixup" is set, then this
11769 function is being called during back-end relaxation, so flag
11770 the unexpected behavior as an error. */
11771 as_bad (_("unexpected TLS relocation"));
11773 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
11774 xtensa_format_length (isa
, fmt
),
11775 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
11776 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
11778 if (tinsn_has_fixup
)
11781 xtensa_opcode opcode
= tinsn
->opcode
;
11782 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11785 for (i
= 0; i
< noperands
; i
++)
11787 expressionS
* exp
= &tinsn
->tok
[i
];
11793 if (get_relaxable_immed (opcode
) == i
)
11795 /* Add a fix record for the instruction, except if this
11796 function is being called prior to relaxation, i.e.,
11797 if record_fixup is false, and the instruction might
11798 be relaxed later. */
11800 || tinsn
->is_specific_opcode
11801 || !xg_is_relaxable_insn (tinsn
, 0))
11803 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
11804 frag_offset
- fragP
->fr_literal
);
11808 if (exp
->X_op
!= O_symbol
)
11809 as_bad (_("invalid operand"));
11810 tinsn
->symbol
= exp
->X_add_symbol
;
11811 tinsn
->offset
= exp
->X_add_number
;
11815 as_bad (_("symbolic operand not allowed"));
11823 as_bad (_("expression too complex"));
11835 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11837 static xtensa_insnbuf insnbuf
= NULL
;
11838 static xtensa_insnbuf slotbuf
= NULL
;
11841 xtensa_isa isa
= xtensa_default_isa
;
11845 insnbuf
= xtensa_insnbuf_alloc (isa
);
11846 slotbuf
= xtensa_insnbuf_alloc (isa
);
11849 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11850 fmt
= xtensa_format_decode (isa
, insnbuf
);
11851 if (fmt
== XTENSA_UNDEFINED
)
11852 as_fatal (_("cannot decode instruction format"));
11853 vinsn
->format
= fmt
;
11854 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11856 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11858 TInsn
*tinsn
= &vinsn
->slots
[i
];
11859 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11860 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11865 /* Expression utilities. */
11867 /* Return TRUE if the expression is an integer constant. */
11870 expr_is_const (const expressionS
*s
)
11872 return (s
->X_op
== O_constant
);
11876 /* Get the expression constant.
11877 Calling this is illegal if expr_is_const () returns TRUE. */
11880 get_expr_const (const expressionS
*s
)
11882 gas_assert (expr_is_const (s
));
11883 return s
->X_add_number
;
11887 /* Set the expression to a constant value. */
11890 set_expr_const (expressionS
*s
, offsetT val
)
11892 s
->X_op
= O_constant
;
11893 s
->X_add_number
= val
;
11894 s
->X_add_symbol
= NULL
;
11895 s
->X_op_symbol
= NULL
;
11900 expr_is_register (const expressionS
*s
)
11902 return (s
->X_op
== O_register
);
11906 /* Get the expression constant.
11907 Calling this is illegal if expr_is_const () returns TRUE. */
11910 get_expr_register (const expressionS
*s
)
11912 gas_assert (expr_is_register (s
));
11913 return s
->X_add_number
;
11917 /* Set the expression to a symbol + constant offset. */
11920 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11922 s
->X_op
= O_symbol
;
11923 s
->X_add_symbol
= sym
;
11924 s
->X_op_symbol
= NULL
; /* unused */
11925 s
->X_add_number
= offset
;
11929 /* Return TRUE if the two expressions are equal. */
11932 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11934 if (s1
->X_op
!= s2
->X_op
)
11936 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11938 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11940 if (s1
->X_add_number
!= s2
->X_add_number
)
11947 copy_expr (expressionS
*dst
, const expressionS
*src
)
11949 memcpy (dst
, src
, sizeof (expressionS
));
11953 /* Support for the "--rename-section" option. */
11955 struct rename_section_struct
11959 struct rename_section_struct
*next
;
11962 static struct rename_section_struct
*section_rename
;
11965 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11966 entries to the section_rename list. Note: Specifying multiple
11967 renamings separated by colons is not documented and is retained only
11968 for backward compatibility. */
11971 build_section_rename (const char *arg
)
11973 struct rename_section_struct
*r
;
11974 char *this_arg
= NULL
;
11975 char *next_arg
= NULL
;
11977 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11979 char *old_name
, *new_name
;
11983 next_arg
= strchr (this_arg
, ':');
11991 old_name
= this_arg
;
11992 new_name
= strchr (this_arg
, '=');
11994 if (*old_name
== '\0')
11996 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11999 if (!new_name
|| new_name
[1] == '\0')
12001 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
12008 /* Check for invalid section renaming. */
12009 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12011 if (strcmp (r
->old_name
, old_name
) == 0)
12012 as_bad (_("section %s renamed multiple times"), old_name
);
12013 if (strcmp (r
->new_name
, new_name
) == 0)
12014 as_bad (_("multiple sections remapped to output section %s"),
12019 r
= (struct rename_section_struct
*)
12020 xmalloc (sizeof (struct rename_section_struct
));
12021 r
->old_name
= xstrdup (old_name
);
12022 r
->new_name
= xstrdup (new_name
);
12023 r
->next
= section_rename
;
12024 section_rename
= r
;
12030 xtensa_section_rename (char *name
)
12032 struct rename_section_struct
*r
= section_rename
;
12034 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12036 if (strcmp (r
->old_name
, name
) == 0)
12037 return r
->new_name
;