1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_num_pipe_stages
;
80 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
82 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
84 /* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
87 static bfd_boolean past_xtensa_end
= FALSE
;
89 /* Flags for properties of the last instruction in a segment. */
90 #define FLAG_IS_A0_WRITER 0x1
91 #define FLAG_IS_BAD_LOOPEND 0x2
94 /* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
99 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
100 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
105 /* This type is used for the directive_stack to keep track of the
106 state of the literal collection pools. If lit_prefix is set, it is
107 used to determine the literal section names; otherwise, the literal
108 sections are determined based on the current text section. The
109 lit_seg and lit4_seg fields cache these literal sections, with the
110 current_text_seg field used a tag to indicate whether the cached
113 typedef struct lit_state_struct
116 segT current_text_seg
;
121 static lit_state default_lit_sections
;
124 /* We keep a list of literal segments. The seg_list type is the node
125 for this list. The literal_head pointer is the head of the list,
126 with the literal_head_h dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
138 /* Lists of symbols. We keep a list of symbols that label the current
139 instruction, so that we can adjust the symbols when inserting alignment
140 for various instructions. We also keep a list of all the symbols on
141 literals, so that we can fix up those symbols when the literals are
142 later moved into the text sections. */
144 typedef struct sym_list_struct
146 struct sym_list_struct
*next
;
150 static sym_list
*insn_labels
= NULL
;
151 static sym_list
*free_insn_labels
= NULL
;
152 static sym_list
*saved_insn_labels
= NULL
;
154 static sym_list
*literal_syms
;
157 /* Flags to determine whether to prefer const16 or l32r
158 if both options are available. */
159 int prefer_const16
= 0;
162 /* Global flag to indicate when we are emitting literals. */
163 int generating_literals
= 0;
165 /* The following PROPERTY table definitions are copied from
166 <elf/xtensa.h> and must be kept in sync with the code there. */
168 /* Flags in the property tables to specify whether blocks of memory
169 are literals, instructions, data, or unreachable. For
170 instructions, blocks that begin loop targets and branch targets are
171 designated. Blocks that do not allow density, instruction
172 reordering or transformation are also specified. Finally, for
173 branch targets, branch target alignment priority is included.
174 Alignment of the next block is specified in the current block
175 and the size of the current block does not include any fill required
176 to align to the next block. */
178 #define XTENSA_PROP_LITERAL 0x00000001
179 #define XTENSA_PROP_INSN 0x00000002
180 #define XTENSA_PROP_DATA 0x00000004
181 #define XTENSA_PROP_UNREACHABLE 0x00000008
182 /* Instruction only properties at beginning of code. */
183 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
184 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
185 /* Instruction only properties about code. */
186 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
187 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
188 /* Historically, NO_TRANSFORM was a property of instructions,
189 but it should apply to literals under certain circumstances. */
190 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
266 /* is_specific_opcode implies no_transform. */
267 unsigned is_no_transform
: 1;
271 unsigned is_loop_target
: 1;
272 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
273 unsigned bt_align_priority
: 2;
275 unsigned is_no_density
: 1;
276 /* no_longcalls flag does not need to be placed in the object file. */
278 unsigned is_no_reorder
: 1;
280 /* Uses absolute literal addressing for l32r. */
281 unsigned is_abslit
: 1;
283 unsigned is_align
: 1;
284 unsigned alignment
: 5;
288 /* Structure for saving information about a block of property data
289 for frags that have the same flags. */
290 struct xtensa_block_info_struct
296 struct xtensa_block_info_struct
*next
;
300 /* Structure for saving the current state before emitting literals. */
301 typedef struct emit_state_struct
306 int generating_literals
;
310 /* Opcode placement information */
312 typedef unsigned long long bitfield
;
313 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
314 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
315 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
317 #define MAX_FORMATS 32
319 typedef struct op_placement_info_struct
322 /* A number describing how restrictive the issue is for this
323 opcode. For example, an opcode that fits lots of different
324 formats has a high freedom, as does an opcode that fits
325 only one format but many slots in that format. The most
326 restrictive is the opcode that fits only one slot in one
329 xtensa_format narrowest
;
333 /* formats is a bitfield with the Nth bit set
334 if the opcode fits in the Nth xtensa_format. */
337 /* slots[N]'s Mth bit is set if the op fits in the
338 Mth slot of the Nth xtensa_format. */
339 bitfield slots
[MAX_FORMATS
];
341 /* A count of the number of slots in a given format
342 an op can fit (i.e., the bitcount of the slot field above). */
343 char slots_in_format
[MAX_FORMATS
];
345 } op_placement_info
, *op_placement_info_table
;
347 op_placement_info_table op_placement_table
;
350 /* Extra expression types. */
352 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
353 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
354 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
355 #define O_pcrel O_md4 /* value is a PC-relative offset */
356 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
357 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
358 #define O_tlscall O_md7 /* TLS_CALL relocation */
359 #define O_tpoff O_md8 /* TPOFF relocation */
360 #define O_dtpoff O_md9 /* DTPOFF relocation */
362 struct suffix_reloc_map
366 bfd_reloc_code_real_type reloc
;
367 unsigned char operator;
370 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
372 static struct suffix_reloc_map suffix_relocs
[] =
374 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
375 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
376 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
377 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
378 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
379 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
380 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
381 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
382 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
383 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
397 directive_literal_prefix
,
399 directive_absolute_literals
,
400 directive_last_directive
406 bfd_boolean can_be_negated
;
409 const directive_infoS directive_info
[] =
412 { "literal", FALSE
},
414 { "transform", TRUE
},
415 { "freeregs", FALSE
},
416 { "longcalls", TRUE
},
417 { "literal_prefix", FALSE
},
418 { "schedule", TRUE
},
419 { "absolute-literals", TRUE
}
422 bfd_boolean directive_state
[] =
426 #if !XCHAL_HAVE_DENSITY
431 TRUE
, /* transform */
432 FALSE
, /* freeregs */
433 FALSE
, /* longcalls */
434 FALSE
, /* literal_prefix */
435 FALSE
, /* schedule */
436 #if XSHAL_USE_ABSOLUTE_LITERALS
437 TRUE
/* absolute_literals */
439 FALSE
/* absolute_literals */
444 /* Directive functions. */
446 static void xtensa_begin_directive (int);
447 static void xtensa_end_directive (int);
448 static void xtensa_literal_prefix (void);
449 static void xtensa_literal_position (int);
450 static void xtensa_literal_pseudo (int);
451 static void xtensa_frequency_pseudo (int);
452 static void xtensa_elf_cons (int);
453 static void xtensa_leb128 (int);
455 /* Parsing and Idiom Translation. */
457 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
459 /* Various Other Internal Functions. */
461 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
462 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
463 static void xtensa_mark_literal_pool_location (void);
464 static addressT
get_expanded_loop_offset (xtensa_opcode
);
465 static fragS
*get_literal_pool_location (segT
);
466 static void set_literal_pool_location (segT
, fragS
*);
467 static void xtensa_set_frag_assembly_state (fragS
*);
468 static void finish_vinsn (vliw_insn
*);
469 static bfd_boolean
emit_single_op (TInsn
*);
470 static int total_frag_text_expansion (fragS
*);
472 /* Alignment Functions. */
474 static int get_text_align_power (unsigned);
475 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
476 static int branch_align_power (segT
);
478 /* Helpers for xtensa_relax_frag(). */
480 static long relax_frag_add_nop (fragS
*);
482 /* Accessors for additional per-subsegment information. */
484 static unsigned get_last_insn_flags (segT
, subsegT
);
485 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
486 static float get_subseg_total_freq (segT
, subsegT
);
487 static float get_subseg_target_freq (segT
, subsegT
);
488 static void set_subseg_freq (segT
, subsegT
, float, float);
490 /* Segment list functions. */
492 static void xtensa_move_literals (void);
493 static void xtensa_reorder_segments (void);
494 static void xtensa_switch_to_literal_fragment (emit_state
*);
495 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
496 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
497 static void xtensa_restore_emit_state (emit_state
*);
498 static segT
cache_literal_section (bfd_boolean
);
500 /* Import from elf32-xtensa.c in BFD library. */
502 extern asection
*xtensa_make_property_section (asection
*, const char *);
504 /* op_placement_info functions. */
506 static void init_op_placement_info_table (void);
507 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
508 static int xg_get_single_size (xtensa_opcode
);
509 static xtensa_format
xg_get_single_format (xtensa_opcode
);
510 static int xg_get_single_slot (xtensa_opcode
);
512 /* TInsn and IStack functions. */
514 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
515 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
516 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
517 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
518 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
519 static void tinsn_from_chars (TInsn
*, char *, int);
520 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
521 static int get_num_stack_text_bytes (IStack
*);
522 static int get_num_stack_literal_bytes (IStack
*);
524 /* vliw_insn functions. */
526 static void xg_init_vinsn (vliw_insn
*);
527 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
528 static void xg_clear_vinsn (vliw_insn
*);
529 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
530 static void xg_free_vinsn (vliw_insn
*);
531 static bfd_boolean vinsn_to_insnbuf
532 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
533 static void vinsn_from_chars (vliw_insn
*, char *);
535 /* Expression Utilities. */
537 bfd_boolean
expr_is_const (const expressionS
*);
538 offsetT
get_expr_const (const expressionS
*);
539 void set_expr_const (expressionS
*, offsetT
);
540 bfd_boolean
expr_is_register (const expressionS
*);
541 offsetT
get_expr_register (const expressionS
*);
542 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
543 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
544 static void copy_expr (expressionS
*, const expressionS
*);
546 /* Section renaming. */
548 static void build_section_rename (const char *);
551 /* ISA imported from bfd. */
552 extern xtensa_isa xtensa_default_isa
;
554 extern int target_big_endian
;
556 static xtensa_opcode xtensa_addi_opcode
;
557 static xtensa_opcode xtensa_addmi_opcode
;
558 static xtensa_opcode xtensa_call0_opcode
;
559 static xtensa_opcode xtensa_call4_opcode
;
560 static xtensa_opcode xtensa_call8_opcode
;
561 static xtensa_opcode xtensa_call12_opcode
;
562 static xtensa_opcode xtensa_callx0_opcode
;
563 static xtensa_opcode xtensa_callx4_opcode
;
564 static xtensa_opcode xtensa_callx8_opcode
;
565 static xtensa_opcode xtensa_callx12_opcode
;
566 static xtensa_opcode xtensa_const16_opcode
;
567 static xtensa_opcode xtensa_entry_opcode
;
568 static xtensa_opcode xtensa_extui_opcode
;
569 static xtensa_opcode xtensa_movi_opcode
;
570 static xtensa_opcode xtensa_movi_n_opcode
;
571 static xtensa_opcode xtensa_isync_opcode
;
572 static xtensa_opcode xtensa_j_opcode
;
573 static xtensa_opcode xtensa_jx_opcode
;
574 static xtensa_opcode xtensa_l32r_opcode
;
575 static xtensa_opcode xtensa_loop_opcode
;
576 static xtensa_opcode xtensa_loopnez_opcode
;
577 static xtensa_opcode xtensa_loopgtz_opcode
;
578 static xtensa_opcode xtensa_nop_opcode
;
579 static xtensa_opcode xtensa_nop_n_opcode
;
580 static xtensa_opcode xtensa_or_opcode
;
581 static xtensa_opcode xtensa_ret_opcode
;
582 static xtensa_opcode xtensa_ret_n_opcode
;
583 static xtensa_opcode xtensa_retw_opcode
;
584 static xtensa_opcode xtensa_retw_n_opcode
;
585 static xtensa_opcode xtensa_rsr_lcount_opcode
;
586 static xtensa_opcode xtensa_waiti_opcode
;
587 static int config_max_slots
= 0;
590 /* Command-line Options. */
592 bfd_boolean use_literal_section
= TRUE
;
593 enum flix_level produce_flix
= FLIX_ALL
;
594 static bfd_boolean align_targets
= TRUE
;
595 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
596 static bfd_boolean has_a0_b_retw
= FALSE
;
597 static bfd_boolean workaround_a0_b_retw
= FALSE
;
598 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
599 static bfd_boolean workaround_short_loop
= FALSE
;
600 static bfd_boolean maybe_has_short_loop
= FALSE
;
601 static bfd_boolean workaround_close_loop_end
= FALSE
;
602 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
603 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
605 /* When workaround_short_loops is TRUE, all loops with early exits must
606 have at least 3 instructions. workaround_all_short_loops is a modifier
607 to the workaround_short_loop flag. In addition to the
608 workaround_short_loop actions, all straightline loopgtz and loopnez
609 must have at least 3 instructions. */
611 static bfd_boolean workaround_all_short_loops
= FALSE
;
615 xtensa_setup_hw_workarounds (int earliest
, int latest
)
617 if (earliest
> latest
)
618 as_fatal (_("illegal range of target hardware versions"));
620 /* Enable all workarounds for pre-T1050.0 hardware. */
621 if (earliest
< 105000 || latest
< 105000)
623 workaround_a0_b_retw
|= TRUE
;
624 workaround_b_j_loop_end
|= TRUE
;
625 workaround_short_loop
|= TRUE
;
626 workaround_close_loop_end
|= TRUE
;
627 workaround_all_short_loops
|= TRUE
;
628 enforce_three_byte_loop_align
= TRUE
;
635 option_density
= OPTION_MD_BASE
,
639 option_no_generate_flix
,
646 option_no_link_relax
,
654 option_text_section_literals
,
655 option_no_text_section_literals
,
657 option_absolute_literals
,
658 option_no_absolute_literals
,
660 option_align_targets
,
661 option_no_align_targets
,
663 option_warn_unaligned_targets
,
668 option_workaround_a0_b_retw
,
669 option_no_workaround_a0_b_retw
,
671 option_workaround_b_j_loop_end
,
672 option_no_workaround_b_j_loop_end
,
674 option_workaround_short_loop
,
675 option_no_workaround_short_loop
,
677 option_workaround_all_short_loops
,
678 option_no_workaround_all_short_loops
,
680 option_workaround_close_loop_end
,
681 option_no_workaround_close_loop_end
,
683 option_no_workarounds
,
685 option_rename_section_name
,
688 option_prefer_const16
,
690 option_target_hardware
693 const char *md_shortopts
= "";
695 struct option md_longopts
[] =
697 { "density", no_argument
, NULL
, option_density
},
698 { "no-density", no_argument
, NULL
, option_no_density
},
700 { "flix", no_argument
, NULL
, option_flix
},
701 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
702 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
704 /* Both "relax" and "generics" are deprecated and treated as equivalent
705 to the "transform" option. */
706 { "relax", no_argument
, NULL
, option_relax
},
707 { "no-relax", no_argument
, NULL
, option_no_relax
},
708 { "generics", no_argument
, NULL
, option_generics
},
709 { "no-generics", no_argument
, NULL
, option_no_generics
},
711 { "transform", no_argument
, NULL
, option_transform
},
712 { "no-transform", no_argument
, NULL
, option_no_transform
},
713 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
714 { "no-text-section-literals", no_argument
, NULL
,
715 option_no_text_section_literals
},
716 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
717 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
718 /* This option was changed from -align-target to -target-align
719 because it conflicted with the "-al" option. */
720 { "target-align", no_argument
, NULL
, option_align_targets
},
721 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
722 { "warn-unaligned-targets", no_argument
, NULL
,
723 option_warn_unaligned_targets
},
724 { "longcalls", no_argument
, NULL
, option_longcalls
},
725 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
727 { "no-workaround-a0-b-retw", no_argument
, NULL
,
728 option_no_workaround_a0_b_retw
},
729 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
731 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
732 option_no_workaround_b_j_loop_end
},
733 { "workaround-b-j-loop-end", no_argument
, NULL
,
734 option_workaround_b_j_loop_end
},
736 { "no-workaround-short-loops", no_argument
, NULL
,
737 option_no_workaround_short_loop
},
738 { "workaround-short-loops", no_argument
, NULL
,
739 option_workaround_short_loop
},
741 { "no-workaround-all-short-loops", no_argument
, NULL
,
742 option_no_workaround_all_short_loops
},
743 { "workaround-all-short-loop", no_argument
, NULL
,
744 option_workaround_all_short_loops
},
746 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
747 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
749 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
751 { "no-workaround-close-loop-end", no_argument
, NULL
,
752 option_no_workaround_close_loop_end
},
753 { "workaround-close-loop-end", no_argument
, NULL
,
754 option_workaround_close_loop_end
},
756 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
758 { "link-relax", no_argument
, NULL
, option_link_relax
},
759 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
761 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
763 { NULL
, no_argument
, NULL
, 0 }
766 size_t md_longopts_size
= sizeof md_longopts
;
770 md_parse_option (int c
, char *arg
)
775 as_warn (_("--density option is ignored"));
777 case option_no_density
:
778 as_warn (_("--no-density option is ignored"));
780 case option_link_relax
:
783 case option_no_link_relax
:
787 produce_flix
= FLIX_ALL
;
789 case option_no_generate_flix
:
790 produce_flix
= FLIX_NO_GENERATE
;
793 produce_flix
= FLIX_NONE
;
795 case option_generics
:
796 as_warn (_("--generics is deprecated; use --transform instead"));
797 return md_parse_option (option_transform
, arg
);
798 case option_no_generics
:
799 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
800 return md_parse_option (option_no_transform
, arg
);
802 as_warn (_("--relax is deprecated; use --transform instead"));
803 return md_parse_option (option_transform
, arg
);
804 case option_no_relax
:
805 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
806 return md_parse_option (option_no_transform
, arg
);
807 case option_longcalls
:
808 directive_state
[directive_longcalls
] = TRUE
;
810 case option_no_longcalls
:
811 directive_state
[directive_longcalls
] = FALSE
;
813 case option_text_section_literals
:
814 use_literal_section
= FALSE
;
816 case option_no_text_section_literals
:
817 use_literal_section
= TRUE
;
819 case option_absolute_literals
:
820 if (!absolute_literals_supported
)
822 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
825 directive_state
[directive_absolute_literals
] = TRUE
;
827 case option_no_absolute_literals
:
828 directive_state
[directive_absolute_literals
] = FALSE
;
831 case option_workaround_a0_b_retw
:
832 workaround_a0_b_retw
= TRUE
;
834 case option_no_workaround_a0_b_retw
:
835 workaround_a0_b_retw
= FALSE
;
837 case option_workaround_b_j_loop_end
:
838 workaround_b_j_loop_end
= TRUE
;
840 case option_no_workaround_b_j_loop_end
:
841 workaround_b_j_loop_end
= FALSE
;
844 case option_workaround_short_loop
:
845 workaround_short_loop
= TRUE
;
847 case option_no_workaround_short_loop
:
848 workaround_short_loop
= FALSE
;
851 case option_workaround_all_short_loops
:
852 workaround_all_short_loops
= TRUE
;
854 case option_no_workaround_all_short_loops
:
855 workaround_all_short_loops
= FALSE
;
858 case option_workaround_close_loop_end
:
859 workaround_close_loop_end
= TRUE
;
861 case option_no_workaround_close_loop_end
:
862 workaround_close_loop_end
= FALSE
;
865 case option_no_workarounds
:
866 workaround_a0_b_retw
= FALSE
;
867 workaround_b_j_loop_end
= FALSE
;
868 workaround_short_loop
= FALSE
;
869 workaround_all_short_loops
= FALSE
;
870 workaround_close_loop_end
= FALSE
;
873 case option_align_targets
:
874 align_targets
= TRUE
;
876 case option_no_align_targets
:
877 align_targets
= FALSE
;
880 case option_warn_unaligned_targets
:
881 warn_unaligned_branch_targets
= TRUE
;
884 case option_rename_section_name
:
885 build_section_rename (arg
);
889 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
890 should be emitted or not. FIXME: Not implemented. */
893 case option_prefer_l32r
:
895 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
899 case option_prefer_const16
:
901 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
905 case option_target_hardware
:
907 int earliest
, latest
= 0;
908 if (*arg
== 0 || *arg
== '-')
909 as_fatal (_("invalid target hardware version"));
911 earliest
= strtol (arg
, &arg
, 0);
915 else if (*arg
== '-')
918 as_fatal (_("invalid target hardware version"));
919 latest
= strtol (arg
, &arg
, 0);
922 as_fatal (_("invalid target hardware version"));
924 xtensa_setup_hw_workarounds (earliest
, latest
);
928 case option_transform
:
929 /* This option has no affect other than to use the defaults,
930 which are already set. */
933 case option_no_transform
:
934 /* This option turns off all transformations of any kind.
935 However, because we want to preserve the state of other
936 directives, we only change its own field. Thus, before
937 you perform any transformation, always check if transform
938 is available. If you use the functions we provide for this
939 purpose, you will be ok. */
940 directive_state
[directive_transform
] = FALSE
;
950 md_show_usage (FILE *stream
)
954 --[no-]text-section-literals\n\
955 [Do not] put literals in the text section\n\
956 --[no-]absolute-literals\n\
957 [Do not] default to use non-PC-relative literals\n\
958 --[no-]target-align [Do not] try to align branch targets\n\
959 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
960 --[no-]transform [Do not] transform instructions\n\
961 --flix both allow hand-written and generate flix bundles\n\
962 --no-generate-flix allow hand-written but do not generate\n\
964 --no-allow-flix neither allow hand-written nor generate\n\
966 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
970 /* Functions related to the list of current label symbols. */
973 xtensa_add_insn_label (symbolS
*sym
)
977 if (!free_insn_labels
)
978 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
981 l
= free_insn_labels
;
982 free_insn_labels
= l
->next
;
986 l
->next
= insn_labels
;
992 xtensa_clear_insn_labels (void)
996 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1004 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1008 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1010 symbolS
*lit_sym
= lit
->sym
;
1011 S_SET_VALUE (lit_sym
, new_offset
);
1012 symbol_set_frag (lit_sym
, new_frag
);
1017 /* Directive data and functions. */
1019 typedef struct state_stackS_struct
1021 directiveE directive
;
1022 bfd_boolean negated
;
1023 bfd_boolean old_state
;
1027 struct state_stackS_struct
*prev
;
1030 state_stackS
*directive_state_stack
;
1032 const pseudo_typeS md_pseudo_table
[] =
1034 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1035 { "literal_position", xtensa_literal_position
, 0 },
1036 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1037 { "long", xtensa_elf_cons
, 4 },
1038 { "word", xtensa_elf_cons
, 4 },
1039 { "4byte", xtensa_elf_cons
, 4 },
1040 { "short", xtensa_elf_cons
, 2 },
1041 { "2byte", xtensa_elf_cons
, 2 },
1042 { "sleb128", xtensa_leb128
, 1},
1043 { "uleb128", xtensa_leb128
, 0},
1044 { "begin", xtensa_begin_directive
, 0 },
1045 { "end", xtensa_end_directive
, 0 },
1046 { "literal", xtensa_literal_pseudo
, 0 },
1047 { "frequency", xtensa_frequency_pseudo
, 0 },
1053 use_transform (void)
1055 /* After md_end, you should be checking frag by frag, rather
1056 than state directives. */
1057 gas_assert (!past_xtensa_end
);
1058 return directive_state
[directive_transform
];
1063 do_align_targets (void)
1065 /* Do not use this function after md_end; just look at align_targets
1066 instead. There is no target-align directive, so alignment is either
1067 enabled for all frags or not done at all. */
1068 gas_assert (!past_xtensa_end
);
1069 return align_targets
&& use_transform ();
1074 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1078 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1080 as_where (&file
, &line
);
1082 stack
->directive
= directive
;
1083 stack
->negated
= negated
;
1084 stack
->old_state
= directive_state
[directive
];
1087 stack
->datum
= datum
;
1088 stack
->prev
= directive_state_stack
;
1089 directive_state_stack
= stack
;
1091 directive_state
[directive
] = !negated
;
1096 directive_pop (directiveE
*directive
,
1097 bfd_boolean
*negated
,
1102 state_stackS
*top
= directive_state_stack
;
1104 if (!directive_state_stack
)
1106 as_bad (_("unmatched end directive"));
1107 *directive
= directive_none
;
1111 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1112 *directive
= top
->directive
;
1113 *negated
= top
->negated
;
1116 *datum
= top
->datum
;
1117 directive_state_stack
= top
->prev
;
1123 directive_balance (void)
1125 while (directive_state_stack
)
1127 directiveE directive
;
1128 bfd_boolean negated
;
1133 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1134 as_warn_where ((char *) file
, line
,
1135 _(".begin directive with no matching .end directive"));
1141 inside_directive (directiveE dir
)
1143 state_stackS
*top
= directive_state_stack
;
1145 while (top
&& top
->directive
!= dir
)
1148 return (top
!= NULL
);
1153 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1157 char *directive_string
;
1159 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1164 input_line_pointer
+= 3;
1167 len
= strspn (input_line_pointer
,
1168 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1170 /* This code is a hack to make .begin [no-][generics|relax] exactly
1171 equivalent to .begin [no-]transform. We should remove it when
1172 we stop accepting those options. */
1174 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1176 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1177 directive_string
= "transform";
1179 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1181 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1182 directive_string
= "transform";
1185 directive_string
= input_line_pointer
;
1187 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1189 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1191 input_line_pointer
+= len
;
1192 *directive
= (directiveE
) i
;
1193 if (*negated
&& !directive_info
[i
].can_be_negated
)
1194 as_bad (_("directive %s cannot be negated"),
1195 directive_info
[i
].name
);
1200 as_bad (_("unknown directive"));
1201 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1206 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1208 directiveE directive
;
1209 bfd_boolean negated
;
1213 get_directive (&directive
, &negated
);
1214 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1216 discard_rest_of_line ();
1220 if (cur_vinsn
.inside_bundle
)
1221 as_bad (_("directives are not valid inside bundles"));
1225 case directive_literal
:
1226 if (!inside_directive (directive_literal
))
1228 /* Previous labels go with whatever follows this directive, not with
1229 the literal, so save them now. */
1230 saved_insn_labels
= insn_labels
;
1233 as_warn (_(".begin literal is deprecated; use .literal instead"));
1234 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1235 xtensa_switch_to_literal_fragment (state
);
1236 directive_push (directive_literal
, negated
, state
);
1239 case directive_literal_prefix
:
1240 /* Have to flush pending output because a movi relaxed to an l32r
1241 might produce a literal. */
1242 md_flush_pending_output ();
1243 /* Check to see if the current fragment is a literal
1244 fragment. If it is, then this operation is not allowed. */
1245 if (generating_literals
)
1247 as_bad (_("cannot set literal_prefix inside literal fragment"));
1251 /* Allocate the literal state for this section and push
1252 onto the directive stack. */
1253 ls
= xmalloc (sizeof (lit_state
));
1256 *ls
= default_lit_sections
;
1257 directive_push (directive_literal_prefix
, negated
, ls
);
1259 /* Process the new prefix. */
1260 xtensa_literal_prefix ();
1263 case directive_freeregs
:
1264 /* This information is currently unused, but we'll accept the statement
1265 and just discard the rest of the line. This won't check the syntax,
1266 but it will accept every correct freeregs directive. */
1267 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1268 directive_push (directive_freeregs
, negated
, 0);
1271 case directive_schedule
:
1272 md_flush_pending_output ();
1273 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1274 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1275 directive_push (directive_schedule
, negated
, 0);
1276 xtensa_set_frag_assembly_state (frag_now
);
1279 case directive_density
:
1280 as_warn (_(".begin [no-]density is ignored"));
1283 case directive_absolute_literals
:
1284 md_flush_pending_output ();
1285 if (!absolute_literals_supported
&& !negated
)
1287 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1290 xtensa_set_frag_assembly_state (frag_now
);
1291 directive_push (directive
, negated
, 0);
1295 md_flush_pending_output ();
1296 xtensa_set_frag_assembly_state (frag_now
);
1297 directive_push (directive
, negated
, 0);
1301 demand_empty_rest_of_line ();
1306 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1308 directiveE begin_directive
, end_directive
;
1309 bfd_boolean begin_negated
, end_negated
;
1313 emit_state
**state_ptr
;
1316 if (cur_vinsn
.inside_bundle
)
1317 as_bad (_("directives are not valid inside bundles"));
1319 get_directive (&end_directive
, &end_negated
);
1321 md_flush_pending_output ();
1323 switch ((int) end_directive
)
1325 case XTENSA_UNDEFINED
:
1326 discard_rest_of_line ();
1329 case (int) directive_density
:
1330 as_warn (_(".end [no-]density is ignored"));
1331 demand_empty_rest_of_line ();
1334 case (int) directive_absolute_literals
:
1335 if (!absolute_literals_supported
&& !end_negated
)
1337 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1338 demand_empty_rest_of_line ();
1347 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1348 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1349 (const void **) state_ptr
);
1351 if (begin_directive
!= directive_none
)
1353 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1355 as_bad (_("does not match begin %s%s at %s:%d"),
1356 begin_negated
? "no-" : "",
1357 directive_info
[begin_directive
].name
, file
, line
);
1361 switch (end_directive
)
1363 case directive_literal
:
1364 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1365 xtensa_restore_emit_state (state
);
1366 xtensa_set_frag_assembly_state (frag_now
);
1368 if (!inside_directive (directive_literal
))
1370 /* Restore the list of current labels. */
1371 xtensa_clear_insn_labels ();
1372 insn_labels
= saved_insn_labels
;
1376 case directive_literal_prefix
:
1377 /* Restore the default collection sections from saved state. */
1378 s
= (lit_state
*) state
;
1380 default_lit_sections
= *s
;
1382 /* Free the state storage. */
1383 free (s
->lit_prefix
);
1387 case directive_schedule
:
1388 case directive_freeregs
:
1392 xtensa_set_frag_assembly_state (frag_now
);
1398 demand_empty_rest_of_line ();
1402 /* Place an aligned literal fragment at the current location. */
1405 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1407 md_flush_pending_output ();
1409 if (inside_directive (directive_literal
))
1410 as_warn (_(".literal_position inside literal directive; ignoring"));
1411 xtensa_mark_literal_pool_location ();
1413 demand_empty_rest_of_line ();
1414 xtensa_clear_insn_labels ();
1418 /* Support .literal label, expr, ... */
1421 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1424 char *p
, *base_name
;
1428 if (inside_directive (directive_literal
))
1430 as_bad (_(".literal not allowed inside .begin literal region"));
1431 ignore_rest_of_line ();
1435 md_flush_pending_output ();
1437 /* Previous labels go with whatever follows this directive, not with
1438 the literal, so save them now. */
1439 saved_insn_labels
= insn_labels
;
1442 /* If we are using text-section literals, then this is the right value... */
1445 base_name
= input_line_pointer
;
1447 xtensa_switch_to_literal_fragment (&state
);
1449 /* ...but if we aren't using text-section-literals, then we
1450 need to put them in the section we just switched to. */
1451 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1454 /* FIXME, despite the previous comments, dest_seg is unused... */
1457 /* All literals are aligned to four-byte boundaries. */
1458 frag_align (2, 0, 0);
1459 record_alignment (now_seg
, 2);
1461 c
= get_symbol_end ();
1462 /* Just after name is now '\0'. */
1463 p
= input_line_pointer
;
1467 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1469 as_bad (_("expected comma or colon after symbol name; "
1470 "rest of line ignored"));
1471 ignore_rest_of_line ();
1472 xtensa_restore_emit_state (&state
);
1480 input_line_pointer
++; /* skip ',' or ':' */
1482 xtensa_elf_cons (4);
1484 xtensa_restore_emit_state (&state
);
1486 /* Restore the list of current labels. */
1487 xtensa_clear_insn_labels ();
1488 insn_labels
= saved_insn_labels
;
1493 xtensa_literal_prefix (void)
1498 /* Parse the new prefix from the input_line_pointer. */
1500 len
= strspn (input_line_pointer
,
1501 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1502 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1504 /* Get a null-terminated copy of the name. */
1505 name
= xmalloc (len
+ 1);
1507 strncpy (name
, input_line_pointer
, len
);
1510 /* Skip the name in the input line. */
1511 input_line_pointer
+= len
;
1513 default_lit_sections
.lit_prefix
= name
;
1515 /* Clear cached literal sections, since the prefix has changed. */
1516 default_lit_sections
.lit_seg
= NULL
;
1517 default_lit_sections
.lit4_seg
= NULL
;
1521 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1524 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1526 float fall_through_f
, target_f
;
1528 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1529 if (fall_through_f
< 0)
1531 as_bad (_("fall through frequency must be greater than 0"));
1532 ignore_rest_of_line ();
1536 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1539 as_bad (_("branch target frequency must be greater than 0"));
1540 ignore_rest_of_line ();
1544 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1546 demand_empty_rest_of_line ();
1550 /* Like normal .long/.short/.word, except support @plt, etc.
1551 Clobbers input_line_pointer, checks end-of-line. */
1554 xtensa_elf_cons (int nbytes
)
1557 bfd_reloc_code_real_type reloc
;
1559 md_flush_pending_output ();
1561 if (cur_vinsn
.inside_bundle
)
1562 as_bad (_("directives are not valid inside bundles"));
1564 if (is_it_end_of_statement ())
1566 demand_empty_rest_of_line ();
1573 if (exp
.X_op
== O_symbol
1574 && *input_line_pointer
== '@'
1575 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1578 reloc_howto_type
*reloc_howto
=
1579 bfd_reloc_type_lookup (stdoutput
, reloc
);
1581 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1582 as_bad (_("unsupported relocation"));
1583 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1584 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1585 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1586 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1587 as_bad (_("opcode-specific %s relocation used outside "
1588 "an instruction"), reloc_howto
->name
);
1589 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1590 as_bad (_("%s relocations do not fit in %d bytes"),
1591 reloc_howto
->name
, nbytes
);
1592 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1593 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1594 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1595 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1598 char *p
= frag_more ((int) nbytes
);
1599 xtensa_set_frag_assembly_state (frag_now
);
1600 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1601 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1606 xtensa_set_frag_assembly_state (frag_now
);
1607 emit_expr (&exp
, (unsigned int) nbytes
);
1610 while (*input_line_pointer
++ == ',');
1612 input_line_pointer
--; /* Put terminator back into stream. */
1613 demand_empty_rest_of_line ();
1616 static bfd_boolean is_leb128_expr
;
1619 xtensa_leb128 (int sign
)
1621 is_leb128_expr
= TRUE
;
1623 is_leb128_expr
= FALSE
;
1627 /* Parsing and Idiom Translation. */
1629 /* Parse @plt, etc. and return the desired relocation. */
1630 static bfd_reloc_code_real_type
1631 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1638 struct suffix_reloc_map
*ptr
;
1641 return BFD_RELOC_NONE
;
1643 for (ch
= *str
, str2
= ident
;
1644 (str2
< ident
+ sizeof (ident
) - 1
1645 && (ISALNUM (ch
) || ch
== '@'));
1648 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1655 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1656 if (ch
== ptr
->suffix
[0]
1657 && len
== ptr
->length
1658 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1660 /* Now check for "identifier@suffix+constant". */
1661 if (*str
== '-' || *str
== '+')
1663 char *orig_line
= input_line_pointer
;
1664 expressionS new_exp
;
1666 input_line_pointer
= str
;
1667 expression (&new_exp
);
1668 if (new_exp
.X_op
== O_constant
)
1670 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1671 str
= input_line_pointer
;
1674 if (&input_line_pointer
!= str_p
)
1675 input_line_pointer
= orig_line
;
1682 return BFD_RELOC_UNUSED
;
1686 /* Find the matching operator type. */
1687 static unsigned char
1688 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1690 struct suffix_reloc_map
*sfx
;
1691 unsigned char operator = (unsigned char) -1;
1693 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1695 if (sfx
->reloc
== reloc
)
1697 operator = sfx
->operator;
1701 gas_assert (operator != (unsigned char) -1);
1706 /* Find the matching reloc type. */
1707 static bfd_reloc_code_real_type
1708 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1710 struct suffix_reloc_map
*sfx
;
1711 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1713 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1715 if (sfx
->operator == operator)
1724 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1725 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1726 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1727 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1730 if (reloc
== BFD_RELOC_UNUSED
)
1731 return BFD_RELOC_32
;
1738 expression_end (const char *name
)
1761 #define ERROR_REG_NUM ((unsigned) -1)
1764 tc_get_register (const char *prefix
)
1767 const char *next_expr
;
1768 const char *old_line_pointer
;
1771 old_line_pointer
= input_line_pointer
;
1773 if (*input_line_pointer
== '$')
1774 ++input_line_pointer
;
1776 /* Accept "sp" as a synonym for "a1". */
1777 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1778 && expression_end (input_line_pointer
+ 2))
1780 input_line_pointer
+= 2;
1781 return 1; /* AR[1] */
1784 while (*input_line_pointer
++ == *prefix
++)
1786 --input_line_pointer
;
1791 as_bad (_("bad register name: %s"), old_line_pointer
);
1792 return ERROR_REG_NUM
;
1795 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1797 as_bad (_("bad register number: %s"), input_line_pointer
);
1798 return ERROR_REG_NUM
;
1803 while (ISDIGIT ((int) *input_line_pointer
))
1804 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1806 if (!(next_expr
= expression_end (input_line_pointer
)))
1808 as_bad (_("bad register name: %s"), old_line_pointer
);
1809 return ERROR_REG_NUM
;
1812 input_line_pointer
= (char *) next_expr
;
1819 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1821 xtensa_isa isa
= xtensa_default_isa
;
1823 /* Check if this is an immediate operand. */
1824 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1826 bfd_reloc_code_real_type reloc
;
1827 segT t
= expression (tok
);
1829 if (t
== absolute_section
1830 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1832 gas_assert (tok
->X_op
== O_constant
);
1833 tok
->X_op
= O_symbol
;
1834 tok
->X_add_symbol
= &abs_symbol
;
1837 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1838 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1843 case BFD_RELOC_LO16
:
1844 if (tok
->X_op
== O_constant
)
1846 tok
->X_add_number
&= 0xffff;
1850 case BFD_RELOC_HI16
:
1851 if (tok
->X_op
== O_constant
)
1853 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1857 case BFD_RELOC_UNUSED
:
1858 as_bad (_("unsupported relocation"));
1860 case BFD_RELOC_32_PCREL
:
1861 as_bad (_("pcrel relocation not allowed in an instruction"));
1866 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1871 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1872 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1874 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1877 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1878 as_bad (_("register number out of range"));
1881 tok
->X_op
= O_register
;
1882 tok
->X_add_symbol
= 0;
1883 tok
->X_add_number
= reg
;
1888 /* Split up the arguments for an opcode or pseudo-op. */
1891 tokenize_arguments (char **args
, char *str
)
1893 char *old_input_line_pointer
;
1894 bfd_boolean saw_comma
= FALSE
;
1895 bfd_boolean saw_arg
= FALSE
;
1896 bfd_boolean saw_colon
= FALSE
;
1898 char *arg_end
, *arg
;
1901 /* Save and restore input_line_pointer around this function. */
1902 old_input_line_pointer
= input_line_pointer
;
1903 input_line_pointer
= str
;
1905 while (*input_line_pointer
)
1908 switch (*input_line_pointer
)
1915 input_line_pointer
++;
1916 if (saw_comma
|| saw_colon
|| !saw_arg
)
1922 input_line_pointer
++;
1923 if (saw_comma
|| saw_colon
|| !saw_arg
)
1929 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1932 arg_end
= input_line_pointer
+ 1;
1933 while (!expression_end (arg_end
))
1936 arg_len
= arg_end
- input_line_pointer
;
1937 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1938 args
[num_args
] = arg
;
1942 strncpy (arg
, input_line_pointer
, arg_len
);
1943 arg
[arg_len
] = '\0';
1945 input_line_pointer
= arg_end
;
1955 if (saw_comma
|| saw_colon
)
1957 input_line_pointer
= old_input_line_pointer
;
1962 as_bad (_("extra comma"));
1964 as_bad (_("extra colon"));
1966 as_bad (_("missing argument"));
1968 as_bad (_("missing comma or colon"));
1969 input_line_pointer
= old_input_line_pointer
;
1974 /* Parse the arguments to an opcode. Return TRUE on error. */
1977 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1979 expressionS
*tok
, *last_tok
;
1980 xtensa_opcode opcode
= insn
->opcode
;
1981 bfd_boolean had_error
= TRUE
;
1982 xtensa_isa isa
= xtensa_default_isa
;
1983 int n
, num_regs
= 0;
1984 int opcode_operand_count
;
1985 int opnd_cnt
, last_opnd_cnt
;
1986 unsigned int next_reg
= 0;
1987 char *old_input_line_pointer
;
1989 if (insn
->insn_type
== ITYPE_LITERAL
)
1990 opcode_operand_count
= 1;
1992 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1995 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1997 /* Save and restore input_line_pointer around this function. */
1998 old_input_line_pointer
= input_line_pointer
;
2004 /* Skip invisible operands. */
2005 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2011 for (n
= 0; n
< num_args
; n
++)
2013 input_line_pointer
= arg_strings
[n
];
2014 if (*input_line_pointer
== ':')
2016 xtensa_regfile opnd_rf
;
2017 input_line_pointer
++;
2020 gas_assert (opnd_cnt
> 0);
2022 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2024 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2025 as_warn (_("incorrect register number, ignoring"));
2030 if (opnd_cnt
>= opcode_operand_count
)
2032 as_warn (_("too many arguments"));
2035 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2037 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2038 next_reg
= tok
->X_add_number
+ 1;
2040 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2042 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2044 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2045 /* minus 1 because we are seeing one right now */
2051 last_opnd_cnt
= opnd_cnt
;
2052 demand_empty_rest_of_line ();
2059 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2063 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2066 insn
->ntok
= tok
- insn
->tok
;
2070 input_line_pointer
= old_input_line_pointer
;
2076 get_invisible_operands (TInsn
*insn
)
2078 xtensa_isa isa
= xtensa_default_isa
;
2079 static xtensa_insnbuf slotbuf
= NULL
;
2081 xtensa_opcode opc
= insn
->opcode
;
2082 int slot
, opnd
, fmt_found
;
2086 slotbuf
= xtensa_insnbuf_alloc (isa
);
2088 /* Find format/slot where this can be encoded. */
2091 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2093 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2095 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2101 if (fmt_found
) break;
2106 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2110 /* First encode all the visible operands
2111 (to deal with shared field operands). */
2112 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2114 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2115 && (insn
->tok
[opnd
].X_op
== O_register
2116 || insn
->tok
[opnd
].X_op
== O_constant
))
2118 val
= insn
->tok
[opnd
].X_add_number
;
2119 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2120 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2124 /* Then pull out the values for the invisible ones. */
2125 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2127 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2129 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2130 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2131 insn
->tok
[opnd
].X_add_number
= val
;
2132 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2133 insn
->tok
[opnd
].X_op
= O_register
;
2135 insn
->tok
[opnd
].X_op
= O_constant
;
2144 xg_reverse_shift_count (char **cnt_argp
)
2146 char *cnt_arg
, *new_arg
;
2147 cnt_arg
= *cnt_argp
;
2149 /* replace the argument with "31-(argument)" */
2150 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2151 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2154 *cnt_argp
= new_arg
;
2158 /* If "arg" is a constant expression, return non-zero with the value
2162 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2165 char *save_ptr
= input_line_pointer
;
2167 input_line_pointer
= arg
;
2169 input_line_pointer
= save_ptr
;
2171 if (exp
.X_op
== O_constant
)
2173 *valp
= exp
.X_add_number
;
2182 xg_replace_opname (char **popname
, char *newop
)
2185 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2186 strcpy (*popname
, newop
);
2191 xg_check_num_args (int *pnum_args
,
2196 int num_args
= *pnum_args
;
2198 if (num_args
< expected_num
)
2200 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2201 num_args
, opname
, expected_num
);
2205 if (num_args
> expected_num
)
2207 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2208 num_args
, opname
, expected_num
);
2209 while (num_args
-- > expected_num
)
2211 free (arg_strings
[num_args
]);
2212 arg_strings
[num_args
] = 0;
2214 *pnum_args
= expected_num
;
2222 /* If the register is not specified as part of the opcode,
2223 then get it from the operand and move it to the opcode. */
2226 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2228 xtensa_isa isa
= xtensa_default_isa
;
2230 char *opname
, *new_opname
;
2231 const char *sr_name
;
2232 int is_user
, is_write
;
2237 is_user
= (opname
[1] == 'u');
2238 is_write
= (opname
[0] == 'w');
2240 /* Opname == [rw]ur or [rwx]sr... */
2242 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2245 /* Check if the argument is a symbolic register name. */
2246 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2247 /* Handle WSR to "INTSET" as a special case. */
2248 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2249 && !strcasecmp (arg_strings
[1], "intset"))
2250 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2251 if (sr
== XTENSA_UNDEFINED
2252 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2254 /* Maybe it's a register number.... */
2256 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2258 as_bad (_("invalid register '%s' for '%s' instruction"),
2259 arg_strings
[1], opname
);
2262 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2263 if (sr
== XTENSA_UNDEFINED
)
2265 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2266 (long) val
, opname
);
2271 /* Remove the last argument, which is now part of the opcode. */
2272 free (arg_strings
[1]);
2276 /* Translate the opcode. */
2277 sr_name
= xtensa_sysreg_name (isa
, sr
);
2278 /* Another special case for "WSR.INTSET".... */
2279 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2281 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2282 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2284 *popname
= new_opname
;
2291 xtensa_translate_old_userreg_ops (char **popname
)
2293 xtensa_isa isa
= xtensa_default_isa
;
2295 char *opname
, *new_opname
;
2296 const char *sr_name
;
2297 bfd_boolean has_underbar
= FALSE
;
2300 if (opname
[0] == '_')
2302 has_underbar
= TRUE
;
2306 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2307 if (sr
!= XTENSA_UNDEFINED
)
2309 /* The new default name ("nnn") is different from the old default
2310 name ("URnnn"). The old default is handled below, and we don't
2311 want to recognize [RW]nnn, so do nothing if the name is the (new)
2313 static char namebuf
[10];
2314 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2315 if (strcmp (namebuf
, opname
+ 1) == 0)
2323 /* Only continue if the reg name is "URnnn". */
2324 if (opname
[1] != 'u' || opname
[2] != 'r')
2326 val
= strtoul (opname
+ 3, &end
, 10);
2330 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2331 if (sr
== XTENSA_UNDEFINED
)
2333 as_bad (_("invalid register number (%ld) for '%s'"),
2334 (long) val
, opname
);
2339 /* Translate the opcode. */
2340 sr_name
= xtensa_sysreg_name (isa
, sr
);
2341 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2342 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2343 opname
[0], sr_name
);
2345 *popname
= new_opname
;
2352 xtensa_translate_zero_immed (char *old_op
,
2362 gas_assert (opname
[0] != '_');
2364 if (strcmp (opname
, old_op
) != 0)
2367 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2369 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2371 xg_replace_opname (popname
, new_op
);
2372 free (arg_strings
[1]);
2373 arg_strings
[1] = arg_strings
[2];
2382 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2383 Returns non-zero if an error was found. */
2386 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2388 char *opname
= *popname
;
2389 bfd_boolean has_underbar
= FALSE
;
2393 has_underbar
= TRUE
;
2397 if (strcmp (opname
, "mov") == 0)
2399 if (use_transform () && !has_underbar
&& density_supported
)
2400 xg_replace_opname (popname
, "mov.n");
2403 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2405 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2406 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2407 strcpy (arg_strings
[2], arg_strings
[1]);
2413 if (strcmp (opname
, "bbsi.l") == 0)
2415 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2417 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2418 if (target_big_endian
)
2419 xg_reverse_shift_count (&arg_strings
[1]);
2423 if (strcmp (opname
, "bbci.l") == 0)
2425 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2427 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2428 if (target_big_endian
)
2429 xg_reverse_shift_count (&arg_strings
[1]);
2433 /* Don't do anything special with NOPs inside FLIX instructions. They
2434 are handled elsewhere. Real NOP instructions are always available
2435 in configurations with FLIX, so this should never be an issue but
2436 check for it anyway. */
2437 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2438 && strcmp (opname
, "nop") == 0)
2440 if (use_transform () && !has_underbar
&& density_supported
)
2441 xg_replace_opname (popname
, "nop.n");
2444 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2446 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2447 arg_strings
[0] = (char *) xmalloc (3);
2448 arg_strings
[1] = (char *) xmalloc (3);
2449 arg_strings
[2] = (char *) xmalloc (3);
2450 strcpy (arg_strings
[0], "a1");
2451 strcpy (arg_strings
[1], "a1");
2452 strcpy (arg_strings
[2], "a1");
2458 /* Recognize [RW]UR and [RWX]SR. */
2459 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2460 && (opname
[1] == 'u' || opname
[1] == 's'))
2461 || (opname
[0] == 'x' && opname
[1] == 's'))
2463 && opname
[3] == '\0')
2464 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2466 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2467 [RW]<name> if <name> is the non-default name of a user register. */
2468 if ((opname
[0] == 'r' || opname
[0] == 'w')
2469 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2470 return xtensa_translate_old_userreg_ops (popname
);
2472 /* Relax branches that don't allow comparisons against an immediate value
2473 of zero to the corresponding branches with implicit zero immediates. */
2474 if (!has_underbar
&& use_transform ())
2476 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2477 pnum_args
, arg_strings
))
2480 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2481 pnum_args
, arg_strings
))
2484 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2485 pnum_args
, arg_strings
))
2488 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2489 pnum_args
, arg_strings
))
2497 /* Functions for dealing with the Xtensa ISA. */
2499 /* Currently the assembler only allows us to use a single target per
2500 fragment. Because of this, only one operand for a given
2501 instruction may be symbolic. If there is a PC-relative operand,
2502 the last one is chosen. Otherwise, the result is the number of the
2503 last immediate operand, and if there are none of those, we fail and
2507 get_relaxable_immed (xtensa_opcode opcode
)
2509 int last_immed
= -1;
2512 if (opcode
== XTENSA_UNDEFINED
)
2515 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2516 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2518 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2520 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2522 if (last_immed
== -1
2523 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2530 static xtensa_opcode
2531 get_opcode_from_buf (const char *buf
, int slot
)
2533 static xtensa_insnbuf insnbuf
= NULL
;
2534 static xtensa_insnbuf slotbuf
= NULL
;
2535 xtensa_isa isa
= xtensa_default_isa
;
2540 insnbuf
= xtensa_insnbuf_alloc (isa
);
2541 slotbuf
= xtensa_insnbuf_alloc (isa
);
2544 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2545 fmt
= xtensa_format_decode (isa
, insnbuf
);
2546 if (fmt
== XTENSA_UNDEFINED
)
2547 return XTENSA_UNDEFINED
;
2549 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2550 return XTENSA_UNDEFINED
;
2552 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2553 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2557 #ifdef TENSILICA_DEBUG
2559 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2562 xtensa_print_insn_table (void)
2564 int num_opcodes
, num_operands
;
2565 xtensa_opcode opcode
;
2566 xtensa_isa isa
= xtensa_default_isa
;
2568 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2569 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2572 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2573 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2574 for (opn
= 0; opn
< num_operands
; opn
++)
2576 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2578 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2580 xtensa_regfile opnd_rf
=
2581 xtensa_operand_regfile (isa
, opcode
, opn
);
2582 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2584 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2585 fputs ("[lLr] ", stderr
);
2587 fputs ("i ", stderr
);
2589 fprintf (stderr
, "\n");
2595 print_vliw_insn (xtensa_insnbuf vbuf
)
2597 xtensa_isa isa
= xtensa_default_isa
;
2598 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2599 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2602 fprintf (stderr
, "format = %d\n", f
);
2604 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2606 xtensa_opcode opcode
;
2610 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2611 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2612 opname
= xtensa_opcode_name (isa
, opcode
);
2614 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2615 fprintf (stderr
, " operands = ");
2617 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2621 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2623 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2624 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2625 fprintf (stderr
, "%d ", val
);
2627 fprintf (stderr
, "\n");
2629 xtensa_insnbuf_free (isa
, sbuf
);
2632 #endif /* TENSILICA_DEBUG */
2636 is_direct_call_opcode (xtensa_opcode opcode
)
2638 xtensa_isa isa
= xtensa_default_isa
;
2639 int n
, num_operands
;
2641 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2644 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2645 for (n
= 0; n
< num_operands
; n
++)
2647 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2648 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2655 /* Convert from BFD relocation type code to slot and operand number.
2656 Returns non-zero on failure. */
2659 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2661 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2662 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2664 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2667 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2668 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2670 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2680 /* Convert from slot number to BFD relocation type code for the
2681 standard PC-relative relocations. Return BFD_RELOC_NONE on
2684 static bfd_reloc_code_real_type
2685 encode_reloc (int slot
)
2687 if (slot
< 0 || slot
> 14)
2688 return BFD_RELOC_NONE
;
2690 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2694 /* Convert from slot numbers to BFD relocation type code for the
2695 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2697 static bfd_reloc_code_real_type
2698 encode_alt_reloc (int slot
)
2700 if (slot
< 0 || slot
> 14)
2701 return BFD_RELOC_NONE
;
2703 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2708 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2711 xtensa_opcode opcode
,
2717 uint32 valbuf
= value
;
2719 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2721 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2723 as_bad_where ((char *) file
, line
,
2724 _("operand %d of '%s' has out of range value '%u'"),
2726 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2729 as_bad_where ((char *) file
, line
,
2730 _("operand %d of '%s' has invalid value '%u'"),
2732 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2737 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2743 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2746 xtensa_opcode opcode
,
2750 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2751 fmt
, slot
, slotbuf
, &val
);
2752 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2757 /* Checks for rules from xtensa-relax tables. */
2759 /* The routine xg_instruction_matches_option_term must return TRUE
2760 when a given option term is true. The meaning of all of the option
2761 terms is given interpretation by this function. */
2764 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2766 if (strcmp (option
->option_name
, "realnop") == 0
2767 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2769 /* These conditions were evaluated statically when building the
2770 relaxation table. There's no need to reevaluate them now. */
2773 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2774 return insn
->extra_arg
.X_op
== O_register
;
2777 as_fatal (_("internal error: unknown option name '%s'"),
2778 option
->option_name
);
2784 xg_instruction_matches_or_options (TInsn
*insn
,
2785 const ReqOrOptionList
*or_option
)
2787 const ReqOrOption
*option
;
2788 /* Must match each of the AND terms. */
2789 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2791 if (xg_instruction_matches_option_term (insn
, option
))
2799 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2801 const ReqOption
*req_options
;
2802 /* Must match each of the AND terms. */
2803 for (req_options
= options
;
2804 req_options
!= NULL
;
2805 req_options
= req_options
->next
)
2807 /* Must match one of the OR clauses. */
2808 if (!xg_instruction_matches_or_options (insn
,
2809 req_options
->or_option_terms
))
2816 /* Return the transition rule that matches or NULL if none matches. */
2819 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2821 PreconditionList
*condition_l
;
2823 if (rule
->opcode
!= insn
->opcode
)
2826 for (condition_l
= rule
->conditions
;
2827 condition_l
!= NULL
;
2828 condition_l
= condition_l
->next
)
2832 Precondition
*cond
= condition_l
->precond
;
2837 /* The expression must be the constant. */
2838 gas_assert (cond
->op_num
< insn
->ntok
);
2839 exp1
= &insn
->tok
[cond
->op_num
];
2840 if (expr_is_const (exp1
))
2845 if (get_expr_const (exp1
) != cond
->op_data
)
2849 if (get_expr_const (exp1
) == cond
->op_data
)
2856 else if (expr_is_register (exp1
))
2861 if (get_expr_register (exp1
) != cond
->op_data
)
2865 if (get_expr_register (exp1
) == cond
->op_data
)
2877 gas_assert (cond
->op_num
< insn
->ntok
);
2878 gas_assert (cond
->op_data
< insn
->ntok
);
2879 exp1
= &insn
->tok
[cond
->op_num
];
2880 exp2
= &insn
->tok
[cond
->op_data
];
2885 if (!expr_is_equal (exp1
, exp2
))
2889 if (expr_is_equal (exp1
, exp2
))
2901 if (!xg_instruction_matches_options (insn
, rule
->options
))
2909 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2911 bfd_boolean a_greater
= FALSE
;
2912 bfd_boolean b_greater
= FALSE
;
2914 ReqOptionList
*l_a
= a
->options
;
2915 ReqOptionList
*l_b
= b
->options
;
2917 /* We only care if they both are the same except for
2918 a const16 vs. an l32r. */
2920 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2922 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2923 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2924 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2926 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2928 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2930 /* This is the case we care about. */
2931 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2932 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2939 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2940 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2950 l_or_a
= l_or_a
->next
;
2951 l_or_b
= l_or_b
->next
;
2953 if (l_or_a
|| l_or_b
)
2962 /* Incomparable if the substitution was used differently in two cases. */
2963 if (a_greater
&& b_greater
)
2975 static TransitionRule
*
2976 xg_instruction_match (TInsn
*insn
)
2978 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2980 gas_assert (insn
->opcode
< table
->num_opcodes
);
2982 /* Walk through all of the possible transitions. */
2983 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2985 TransitionRule
*rule
= l
->rule
;
2986 if (xg_instruction_matches_rule (insn
, rule
))
2993 /* Various Other Internal Functions. */
2996 is_unique_insn_expansion (TransitionRule
*r
)
2998 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3000 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3006 /* Check if there is exactly one relaxation for INSN that converts it to
3007 another instruction of equal or larger size. If so, and if TARG is
3008 non-null, go ahead and generate the relaxed instruction into TARG. If
3009 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3010 instruction, i.e., ignore relaxations that convert to an instruction of
3011 equal size. In some contexts where this function is used, only
3012 a single widening is allowed and the NARROW_ONLY argument is used to
3013 exclude cases like ADDI being "widened" to an ADDMI, which may
3014 later be relaxed to an ADDMI/ADDI pair. */
3017 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3019 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3021 TransitionRule
*match
= 0;
3023 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3024 gas_assert (insn
->opcode
< table
->num_opcodes
);
3026 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3028 TransitionRule
*rule
= l
->rule
;
3030 if (xg_instruction_matches_rule (insn
, rule
)
3031 && is_unique_insn_expansion (rule
)
3032 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3033 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3044 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3049 /* Return the maximum number of bytes this opcode can expand to. */
3052 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3054 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3056 int max_size
= xg_get_single_size (opcode
);
3058 gas_assert (opcode
< table
->num_opcodes
);
3060 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3062 TransitionRule
*rule
= l
->rule
;
3063 BuildInstr
*build_list
;
3068 build_list
= rule
->to_instr
;
3069 if (is_unique_insn_expansion (rule
))
3071 gas_assert (build_list
->typ
== INSTR_INSTR
);
3072 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3075 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3077 switch (build_list
->typ
)
3080 this_size
+= xg_get_single_size (build_list
->opcode
);
3082 case INSTR_LITERAL_DEF
:
3083 case INSTR_LABEL_DEF
:
3088 if (this_size
> max_size
)
3089 max_size
= this_size
;
3095 /* Return the maximum number of literal bytes this opcode can generate. */
3098 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3100 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3104 gas_assert (opcode
< table
->num_opcodes
);
3106 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3108 TransitionRule
*rule
= l
->rule
;
3109 BuildInstr
*build_list
;
3114 build_list
= rule
->to_instr
;
3115 if (is_unique_insn_expansion (rule
))
3117 gas_assert (build_list
->typ
== INSTR_INSTR
);
3118 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3121 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3123 switch (build_list
->typ
)
3125 case INSTR_LITERAL_DEF
:
3126 /* Hard-coded 4-byte literal. */
3130 case INSTR_LABEL_DEF
:
3135 if (this_size
> max_size
)
3136 max_size
= this_size
;
3143 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3145 int steps_taken
= 0;
3146 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3149 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3150 gas_assert (insn
->opcode
< table
->num_opcodes
);
3152 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3154 TransitionRule
*rule
= l
->rule
;
3156 if (xg_instruction_matches_rule (insn
, rule
))
3158 if (steps_taken
== lateral_steps
)
3168 get_special_literal_symbol (void)
3170 static symbolS
*sym
= NULL
;
3173 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3179 get_special_label_symbol (void)
3181 static symbolS
*sym
= NULL
;
3184 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3190 xg_valid_literal_expression (const expressionS
*exp
)
3212 /* This will check to see if the value can be converted into the
3213 operand type. It will return TRUE if it does not fit. */
3216 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3218 uint32 valbuf
= value
;
3219 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3225 /* Assumes: All immeds are constants. Check that all constants fit
3226 into their immeds; return FALSE if not. */
3229 xg_immeds_fit (const TInsn
*insn
)
3231 xtensa_isa isa
= xtensa_default_isa
;
3235 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3236 for (i
= 0; i
< n
; ++i
)
3238 const expressionS
*exp
= &insn
->tok
[i
];
3240 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3247 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3252 /* The symbol should have a fixup associated with it. */
3261 /* This should only be called after we have an initial
3262 estimate of the addresses. */
3265 xg_symbolic_immeds_fit (const TInsn
*insn
,
3271 xtensa_isa isa
= xtensa_default_isa
;
3279 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3281 for (i
= 0; i
< n
; ++i
)
3283 const expressionS
*exp
= &insn
->tok
[i
];
3285 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3292 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3298 /* Check for the worst case. */
3299 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3304 /* We only allow symbols for PC-relative references.
3305 If pc_frag == 0, then we don't have frag locations yet. */
3307 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3310 /* If it is a weak symbol or a symbol in a different section,
3311 it cannot be known to fit at assembly time. */
3312 if (S_IS_WEAK (exp
->X_add_symbol
)
3313 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3315 /* For a direct call with --no-longcalls, be optimistic and
3316 assume it will be in range. If the symbol is weak and
3317 undefined, it may remain undefined at link-time, in which
3318 case it will have a zero value and almost certainly be out
3319 of range for a direct call; thus, relax for undefined weak
3320 symbols even if longcalls is not enabled. */
3321 if (is_direct_call_opcode (insn
->opcode
)
3322 && ! pc_frag
->tc_frag_data
.use_longcalls
3323 && (! S_IS_WEAK (exp
->X_add_symbol
)
3324 || S_IS_DEFINED (exp
->X_add_symbol
)))
3330 symbolP
= exp
->X_add_symbol
;
3331 sym_frag
= symbol_get_frag (symbolP
);
3332 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3333 pc
= pc_frag
->fr_address
+ pc_offset
;
3335 /* If frag has yet to be reached on this pass, assume it
3336 will move by STRETCH just as we did. If this is not so,
3337 it will be because some frag between grows, and that will
3338 force another pass. Beware zero-length frags. There
3339 should be a faster way to do this. */
3342 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3343 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3348 new_offset
= target
;
3349 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3350 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3355 /* The symbol should have a fixup associated with it. */
3364 /* Return TRUE on success. */
3367 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3373 targ
->debug_line
= insn
->debug_line
;
3374 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3379 targ
->opcode
= bi
->opcode
;
3380 targ
->insn_type
= ITYPE_INSN
;
3381 targ
->is_specific_opcode
= FALSE
;
3383 for (; op
!= NULL
; op
= op
->next
)
3385 int op_num
= op
->op_num
;
3386 int op_data
= op
->op_data
;
3388 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3390 if (targ
->ntok
<= op_num
)
3391 targ
->ntok
= op_num
+ 1;
3396 set_expr_const (&targ
->tok
[op_num
], op_data
);
3399 gas_assert (op_data
< insn
->ntok
);
3400 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3403 if (insn
->extra_arg
.X_op
!= O_register
)
3405 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3408 sym
= get_special_literal_symbol ();
3409 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3410 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3411 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3412 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3415 sym
= get_special_label_symbol ();
3416 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3418 case OP_OPERAND_HI16U
:
3419 case OP_OPERAND_LOW16U
:
3420 gas_assert (op_data
< insn
->ntok
);
3421 if (expr_is_const (&insn
->tok
[op_data
]))
3424 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3425 val
= xg_apply_userdef_op_fn (op
->typ
,
3428 targ
->tok
[op_num
].X_add_number
= val
;
3432 /* For const16 we can create relocations for these. */
3433 if (targ
->opcode
== XTENSA_UNDEFINED
3434 || (targ
->opcode
!= xtensa_const16_opcode
))
3436 gas_assert (op_data
< insn
->ntok
);
3437 /* Need to build a O_lo16 or O_hi16. */
3438 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3439 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3441 if (op
->typ
== OP_OPERAND_HI16U
)
3442 targ
->tok
[op_num
].X_op
= O_hi16
;
3443 else if (op
->typ
== OP_OPERAND_LOW16U
)
3444 targ
->tok
[op_num
].X_op
= O_lo16
;
3451 /* currently handles:
3454 OP_OPERAND_F32MINUS */
3455 if (xg_has_userdef_op_fn (op
->typ
))
3457 gas_assert (op_data
< insn
->ntok
);
3458 if (expr_is_const (&insn
->tok
[op_data
]))
3461 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3462 val
= xg_apply_userdef_op_fn (op
->typ
,
3465 targ
->tok
[op_num
].X_add_number
= val
;
3468 return FALSE
; /* We cannot use a relocation for this. */
3477 case INSTR_LITERAL_DEF
:
3479 targ
->opcode
= XTENSA_UNDEFINED
;
3480 targ
->insn_type
= ITYPE_LITERAL
;
3481 targ
->is_specific_opcode
= FALSE
;
3482 for (; op
!= NULL
; op
= op
->next
)
3484 int op_num
= op
->op_num
;
3485 int op_data
= op
->op_data
;
3486 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3488 if (targ
->ntok
<= op_num
)
3489 targ
->ntok
= op_num
+ 1;
3494 gas_assert (op_data
< insn
->ntok
);
3495 /* We can only pass resolvable literals through. */
3496 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3498 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3510 case INSTR_LABEL_DEF
:
3512 targ
->opcode
= XTENSA_UNDEFINED
;
3513 targ
->insn_type
= ITYPE_LABEL
;
3514 targ
->is_specific_opcode
= FALSE
;
3515 /* Literal with no ops is a label? */
3516 gas_assert (op
== NULL
);
3527 /* Return TRUE on success. */
3530 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3532 for (; bi
!= NULL
; bi
= bi
->next
)
3534 TInsn
*next_insn
= istack_push_space (istack
);
3536 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3543 /* Return TRUE on valid expansion. */
3546 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3548 int stack_size
= istack
->ninsn
;
3549 int steps_taken
= 0;
3550 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3553 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3554 gas_assert (insn
->opcode
< table
->num_opcodes
);
3556 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3558 TransitionRule
*rule
= l
->rule
;
3560 if (xg_instruction_matches_rule (insn
, rule
))
3562 if (lateral_steps
== steps_taken
)
3566 /* This is it. Expand the rule to the stack. */
3567 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3570 /* Check to see if it fits. */
3571 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3573 TInsn
*tinsn
= &istack
->insn
[i
];
3575 if (tinsn
->insn_type
== ITYPE_INSN
3576 && !tinsn_has_symbolic_operands (tinsn
)
3577 && !xg_immeds_fit (tinsn
))
3579 istack
->ninsn
= stack_size
;
3592 /* Relax the assembly instruction at least "min_steps".
3593 Return the number of steps taken.
3595 For relaxation to correctly terminate, every relaxation chain must
3596 terminate in one of two ways:
3598 1. If the chain from one instruction to the next consists entirely of
3599 single instructions, then the chain *must* handle all possible
3600 immediates without failing. It must not ever fail because an
3601 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3602 chain is one example. L32R loads 32 bits, and there cannot be an
3603 immediate larger than 32 bits, so it satisfies this condition.
3604 Single instruction relaxation chains are as defined by
3605 xg_is_single_relaxable_instruction.
3607 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3608 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3610 Strictly speaking, in most cases you can violate condition 1 and be OK
3611 -- in particular when the last two instructions have the same single
3612 size. But nevertheless, you should guarantee the above two conditions.
3614 We could fix this so that single-instruction expansions correctly
3615 terminate when they can't handle the range, but the error messages are
3616 worse, and it actually turns out that in every case but one (18-bit wide
3617 branches), you need a multi-instruction expansion to get the full range
3618 anyway. And because 18-bit branches are handled identically to 15-bit
3619 branches, there isn't any point in changing it. */
3622 xg_assembly_relax (IStack
*istack
,
3625 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3626 offsetT pc_offset
, /* offset in fragment */
3627 int min_steps
, /* minimum conversion steps */
3628 long stretch
) /* number of bytes stretched so far */
3630 int steps_taken
= 0;
3632 /* Some of its immeds don't fit. Try to build a relaxed version.
3633 This may go through a couple of stages of single instruction
3634 transformations before we get there. */
3636 TInsn single_target
;
3638 int lateral_steps
= 0;
3639 int istack_size
= istack
->ninsn
;
3641 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3642 && steps_taken
>= min_steps
)
3644 istack_push (istack
, insn
);
3647 current_insn
= *insn
;
3649 /* Walk through all of the single instruction expansions. */
3650 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3653 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3656 if (steps_taken
>= min_steps
)
3658 istack_push (istack
, &single_target
);
3662 current_insn
= single_target
;
3665 /* Now check for a multi-instruction expansion. */
3666 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3668 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3671 if (steps_taken
>= min_steps
)
3673 istack_push (istack
, ¤t_insn
);
3678 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3680 if (steps_taken
>= min_steps
)
3684 istack
->ninsn
= istack_size
;
3687 /* It's not going to work -- use the original. */
3688 istack_push (istack
, insn
);
3694 xg_finish_frag (char *last_insn
,
3695 enum xtensa_relax_statesE frag_state
,
3696 enum xtensa_relax_statesE slot0_state
,
3698 bfd_boolean is_insn
)
3700 /* Finish off this fragment so that it has at LEAST the desired
3701 max_growth. If it doesn't fit in this fragment, close this one
3702 and start a new one. In either case, return a pointer to the
3703 beginning of the growth area. */
3707 frag_grow (max_growth
);
3708 old_frag
= frag_now
;
3710 frag_now
->fr_opcode
= last_insn
;
3712 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3714 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3715 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3717 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3718 xtensa_set_frag_assembly_state (frag_now
);
3720 /* Just to make sure that we did not split it up. */
3721 gas_assert (old_frag
->fr_next
== frag_now
);
3725 /* Return TRUE if the target frag is one of the next non-empty frags. */
3728 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3733 for (; fragP
; fragP
= fragP
->fr_next
)
3735 if (fragP
== target
)
3737 if (fragP
->fr_fix
!= 0)
3739 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3741 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3742 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3744 if (fragP
->fr_type
== rs_space
)
3752 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3754 xtensa_isa isa
= xtensa_default_isa
;
3756 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3761 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3762 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3765 for (i
= 0; i
< num_ops
; i
++)
3767 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3773 if (target_op
== -1)
3776 if (insn
->ntok
<= target_op
)
3779 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3782 sym
= insn
->tok
[target_op
].X_add_symbol
;
3786 if (insn
->tok
[target_op
].X_add_number
!= 0)
3789 target_frag
= symbol_get_frag (sym
);
3790 if (target_frag
== NULL
)
3793 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3794 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3802 xg_add_branch_and_loop_targets (TInsn
*insn
)
3804 xtensa_isa isa
= xtensa_default_isa
;
3805 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3807 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3810 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3811 && insn
->tok
[i
].X_op
== O_symbol
)
3812 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3816 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3817 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3821 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3823 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3824 && insn
->tok
[i
].X_op
== O_symbol
)
3826 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3827 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3828 if (S_IS_DEFINED (sym
))
3829 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3836 /* Return FALSE if no error. */
3839 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3844 switch (instr_spec
->typ
)
3847 new_insn
->insn_type
= ITYPE_INSN
;
3848 new_insn
->opcode
= instr_spec
->opcode
;
3850 case INSTR_LITERAL_DEF
:
3851 new_insn
->insn_type
= ITYPE_LITERAL
;
3852 new_insn
->opcode
= XTENSA_UNDEFINED
;
3854 case INSTR_LABEL_DEF
:
3857 new_insn
->is_specific_opcode
= FALSE
;
3858 new_insn
->debug_line
= old_insn
->debug_line
;
3859 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3861 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3864 const expressionS
*src_exp
;
3870 /* The expression must be the constant. */
3871 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3872 exp
= &new_insn
->tok
[b_op
->op_num
];
3873 set_expr_const (exp
, b_op
->op_data
);
3877 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3878 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3879 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3880 exp
= &new_insn
->tok
[b_op
->op_num
];
3881 copy_expr (exp
, src_exp
);
3886 as_bad (_("can't handle generation of literal/labels yet"));
3890 as_bad (_("can't handle undefined OP TYPE"));
3895 new_insn
->ntok
= num_ops
;
3900 /* Return TRUE if it was simplified. */
3903 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3905 TransitionRule
*rule
;
3906 BuildInstr
*insn_spec
;
3908 if (old_insn
->is_specific_opcode
|| !density_supported
)
3911 rule
= xg_instruction_match (old_insn
);
3915 insn_spec
= rule
->to_instr
;
3916 /* There should only be one. */
3917 gas_assert (insn_spec
!= NULL
);
3918 gas_assert (insn_spec
->next
== NULL
);
3919 if (insn_spec
->next
!= NULL
)
3922 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3928 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3929 l32i.n. (2) Check the number of operands. (3) Place the instruction
3930 tokens into the stack or relax it and place multiple
3931 instructions/literals onto the stack. Return FALSE if no error. */
3934 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3938 bfd_boolean do_expand
;
3940 tinsn_init (&new_insn
);
3942 /* Narrow it if we can. xg_simplify_insn now does all the
3943 appropriate checking (e.g., for the density option). */
3944 if (xg_simplify_insn (orig_insn
, &new_insn
))
3945 orig_insn
= &new_insn
;
3947 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3949 if (orig_insn
->ntok
< noperands
)
3951 as_bad (_("found %d operands for '%s': Expected %d"),
3953 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3957 if (orig_insn
->ntok
> noperands
)
3958 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3960 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3963 /* If there are not enough operands, we will assert above. If there
3964 are too many, just cut out the extras here. */
3965 orig_insn
->ntok
= noperands
;
3967 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3970 /* Special case for extui opcode which has constraints not handled
3971 by the ordinary operand encoding checks. The number of operands
3972 and related syntax issues have already been checked. */
3973 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3975 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3976 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3977 if (shiftimm
+ maskimm
> 32)
3979 as_bad (_("immediate operands sum to greater than 32"));
3984 /* If the instruction will definitely need to be relaxed, it is better
3985 to expand it now for better scheduling. Decide whether to expand
3987 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3989 /* Calls should be expanded to longcalls only in the backend relaxation
3990 so that the assembly scheduler will keep the L32R/CALLX instructions
3992 if (is_direct_call_opcode (orig_insn
->opcode
))
3995 if (tinsn_has_symbolic_operands (orig_insn
))
3997 /* The values of symbolic operands are not known yet, so only expand
3998 now if an operand is "complex" (e.g., difference of symbols) and
3999 will have to be stored as a literal regardless of the value. */
4000 if (!tinsn_has_complex_operands (orig_insn
))
4003 else if (xg_immeds_fit (orig_insn
))
4007 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4009 istack_push (istack
, orig_insn
);
4015 /* Return TRUE if the section flags are marked linkonce
4016 or the name is .gnu.linkonce.*. */
4018 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4021 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4023 flagword flags
, link_once_flags
;
4025 flags
= bfd_get_section_flags (abfd
, sec
);
4026 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4028 /* Flags might not be set yet. */
4029 if (!link_once_flags
4030 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4031 link_once_flags
= SEC_LINK_ONCE
;
4033 return (link_once_flags
!= 0);
4038 xtensa_add_literal_sym (symbolS
*sym
)
4042 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4044 l
->next
= literal_syms
;
4050 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4052 static int lit_num
= 0;
4053 static char name
[256];
4056 sprintf (name
, ".L_lit_sym%d", lit_num
);
4058 /* Create a local symbol. If it is in a linkonce section, we have to
4059 be careful to make sure that if it is used in a relocation that the
4060 symbol will be in the output file. */
4061 if (get_is_linkonce_section (stdoutput
, sec
))
4063 symbolP
= symbol_new (name
, sec
, 0, frag
);
4064 S_CLEAR_EXTERNAL (symbolP
);
4065 /* symbolP->local = 1; */
4068 symbolP
= symbol_new (name
, sec
, 0, frag
);
4070 xtensa_add_literal_sym (symbolP
);
4077 /* Currently all literals that are generated here are 32-bit L32R targets. */
4080 xg_assemble_literal (/* const */ TInsn
*insn
)
4083 symbolS
*lit_sym
= NULL
;
4084 bfd_reloc_code_real_type reloc
;
4085 bfd_boolean pcrel
= FALSE
;
4088 /* size = 4 for L32R. It could easily be larger when we move to
4089 larger constants. Add a parameter later. */
4090 offsetT litsize
= 4;
4091 offsetT litalign
= 2; /* 2^2 = 4 */
4092 expressionS saved_loc
;
4093 expressionS
* emit_val
;
4095 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4097 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4098 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4100 xtensa_switch_to_literal_fragment (&state
);
4102 emit_val
= &insn
->tok
[0];
4103 if (emit_val
->X_op
== O_big
)
4105 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4108 /* This happens when someone writes a "movi a2, big_number". */
4109 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4110 _("invalid immediate"));
4111 xtensa_restore_emit_state (&state
);
4116 /* Force a 4-byte align here. Note that this opens a new frag, so all
4117 literals done with this function have a frag to themselves. That's
4118 important for the way text section literals work. */
4119 frag_align (litalign
, 0, 0);
4120 record_alignment (now_seg
, litalign
);
4122 switch (emit_val
->X_op
)
4132 p
= frag_more (litsize
);
4133 xtensa_set_frag_assembly_state (frag_now
);
4134 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4135 if (emit_val
->X_add_symbol
)
4136 emit_val
->X_op
= O_symbol
;
4138 emit_val
->X_op
= O_constant
;
4139 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4140 litsize
, emit_val
, pcrel
, reloc
);
4144 emit_expr (emit_val
, litsize
);
4148 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4149 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4150 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4151 lit_sym
= frag_now
->fr_symbol
;
4154 xtensa_restore_emit_state (&state
);
4160 xg_assemble_literal_space (/* const */ int size
, int slot
)
4163 /* We might have to do something about this alignment. It only
4164 takes effect if something is placed here. */
4165 offsetT litalign
= 2; /* 2^2 = 4 */
4166 fragS
*lit_saved_frag
;
4168 gas_assert (size
% 4 == 0);
4170 xtensa_switch_to_literal_fragment (&state
);
4172 /* Force a 4-byte align here. */
4173 frag_align (litalign
, 0, 0);
4174 record_alignment (now_seg
, litalign
);
4178 lit_saved_frag
= frag_now
;
4179 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4180 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4181 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4184 xtensa_restore_emit_state (&state
);
4185 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4189 /* Put in a fixup record based on the opcode.
4190 Return TRUE on success. */
4193 xg_add_opcode_fix (TInsn
*tinsn
,
4201 xtensa_opcode opcode
= tinsn
->opcode
;
4202 bfd_reloc_code_real_type reloc
;
4203 reloc_howto_type
*howto
;
4207 reloc
= BFD_RELOC_NONE
;
4209 /* First try the special cases for "alternate" relocs. */
4210 if (opcode
== xtensa_l32r_opcode
)
4212 if (fragP
->tc_frag_data
.use_absolute_literals
)
4213 reloc
= encode_alt_reloc (slot
);
4215 else if (opcode
== xtensa_const16_opcode
)
4217 if (exp
->X_op
== O_lo16
)
4219 reloc
= encode_reloc (slot
);
4220 exp
->X_op
= O_symbol
;
4222 else if (exp
->X_op
== O_hi16
)
4224 reloc
= encode_alt_reloc (slot
);
4225 exp
->X_op
= O_symbol
;
4229 if (opnum
!= get_relaxable_immed (opcode
))
4231 as_bad (_("invalid relocation for operand %i of '%s'"),
4232 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4236 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4237 into the symbol table where the generic portions of the assembler
4238 won't know what to do with them. */
4239 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4241 as_bad (_("invalid expression for operand %i of '%s'"),
4242 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4246 /* Next try the generic relocs. */
4247 if (reloc
== BFD_RELOC_NONE
)
4248 reloc
= encode_reloc (slot
);
4249 if (reloc
== BFD_RELOC_NONE
)
4251 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4255 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4258 as_bad (_("undefined symbol for opcode \"%s\""),
4259 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4263 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4264 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4265 howto
->pc_relative
, reloc
);
4266 the_fix
->fx_no_overflow
= 1;
4267 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4268 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4269 the_fix
->tc_fix_data
.slot
= slot
;
4276 xg_emit_insn_to_buf (TInsn
*tinsn
,
4280 bfd_boolean build_fix
)
4282 static xtensa_insnbuf insnbuf
= NULL
;
4283 bfd_boolean has_symbolic_immed
= FALSE
;
4284 bfd_boolean ok
= TRUE
;
4287 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4289 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4290 if (has_symbolic_immed
&& build_fix
)
4293 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4294 int slot
= xg_get_single_slot (tinsn
->opcode
);
4295 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4296 expressionS
*exp
= &tinsn
->tok
[opnum
];
4298 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4301 fragP
->tc_frag_data
.is_insn
= TRUE
;
4302 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4303 (unsigned char *) buf
, 0);
4309 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4311 symbolS
*sym
= get_special_literal_symbol ();
4315 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4316 for (i
= 0; i
< insn
->ntok
; i
++)
4317 if (insn
->tok
[i
].X_add_symbol
== sym
)
4318 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4324 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4326 symbolS
*sym
= get_special_label_symbol ();
4328 for (i
= 0; i
< insn
->ntok
; i
++)
4329 if (insn
->tok
[i
].X_add_symbol
== sym
)
4330 insn
->tok
[i
].X_add_symbol
= label_sym
;
4335 /* Return TRUE if the instruction can write to the specified
4336 integer register. */
4339 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4343 xtensa_isa isa
= xtensa_default_isa
;
4345 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4347 for (i
= 0; i
< num_ops
; i
++)
4350 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4351 if ((inout
== 'o' || inout
== 'm')
4352 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4354 xtensa_regfile opnd_rf
=
4355 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4356 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4358 if ((insn
->tok
[i
].X_op
== O_register
)
4359 && (insn
->tok
[i
].X_add_number
== regnum
))
4369 is_bad_loopend_opcode (const TInsn
*tinsn
)
4371 xtensa_opcode opcode
= tinsn
->opcode
;
4373 if (opcode
== XTENSA_UNDEFINED
)
4376 if (opcode
== xtensa_call0_opcode
4377 || opcode
== xtensa_callx0_opcode
4378 || opcode
== xtensa_call4_opcode
4379 || opcode
== xtensa_callx4_opcode
4380 || opcode
== xtensa_call8_opcode
4381 || opcode
== xtensa_callx8_opcode
4382 || opcode
== xtensa_call12_opcode
4383 || opcode
== xtensa_callx12_opcode
4384 || opcode
== xtensa_isync_opcode
4385 || opcode
== xtensa_ret_opcode
4386 || opcode
== xtensa_ret_n_opcode
4387 || opcode
== xtensa_retw_opcode
4388 || opcode
== xtensa_retw_n_opcode
4389 || opcode
== xtensa_waiti_opcode
4390 || opcode
== xtensa_rsr_lcount_opcode
)
4397 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4398 This allows the debugger to add unaligned labels.
4399 Also, the assembler generates stabs labels that need
4400 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4403 is_unaligned_label (symbolS
*sym
)
4405 const char *name
= S_GET_NAME (sym
);
4406 static size_t fake_size
= 0;
4410 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4413 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4415 fake_size
= strlen (FAKE_LABEL_NAME
);
4418 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4419 && (name
[fake_size
] == 'F'
4420 || name
[fake_size
] == 'L'
4421 || (name
[fake_size
] == 'e'
4422 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4430 next_non_empty_frag (const fragS
*fragP
)
4432 fragS
*next_fragP
= fragP
->fr_next
;
4434 /* Sometimes an empty will end up here due storage allocation issues.
4435 So we have to skip until we find something legit. */
4436 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4437 next_fragP
= next_fragP
->fr_next
;
4439 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4447 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4449 xtensa_opcode out_opcode
;
4450 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4452 if (next_fragP
== NULL
)
4455 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4456 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4458 *opcode
= out_opcode
;
4466 frag_format_size (const fragS
*fragP
)
4468 static xtensa_insnbuf insnbuf
= NULL
;
4469 xtensa_isa isa
= xtensa_default_isa
;
4474 insnbuf
= xtensa_insnbuf_alloc (isa
);
4477 return XTENSA_UNDEFINED
;
4479 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4480 (unsigned char *) fragP
->fr_literal
, 0);
4482 fmt
= xtensa_format_decode (isa
, insnbuf
);
4483 if (fmt
== XTENSA_UNDEFINED
)
4484 return XTENSA_UNDEFINED
;
4485 fmt_size
= xtensa_format_length (isa
, fmt
);
4487 /* If the next format won't be changing due to relaxation, just
4488 return the length of the first format. */
4489 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4492 /* If during relaxation we have to pull an instruction out of a
4493 multi-slot instruction, we will return the more conservative
4494 number. This works because alignment on bigger instructions
4495 is more restrictive than alignment on smaller instructions.
4496 This is more conservative than we would like, but it happens
4499 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4502 /* If we aren't doing one of our own relaxations or it isn't
4503 slot-based, then the insn size won't change. */
4504 if (fragP
->fr_type
!= rs_machine_dependent
)
4506 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4509 /* If an instruction is about to grow, return the longer size. */
4510 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4511 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4512 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4514 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4515 instruction in the relaxed version is of length 3. (The case
4516 where we have to pull the instruction out of a FLIX bundle
4517 is handled conservatively above.) However, frags with opcodes
4518 that are expanding to wide branches end up having formats that
4519 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4520 we can't tell directly what format the relaxer picked. This
4521 is a wart in the design of the relaxer that should someday be
4522 fixed, but would require major changes, or at least should
4523 be accompanied by major changes to make use of that data.
4525 In any event, we can tell that we are expanding from a single-slot
4526 format to a wider one with the logic below. */
4529 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4531 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4533 if (relaxed_size
== xtensa_format_length (isa
, i
))
4534 return relaxed_size
;
4540 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4541 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4548 next_frag_format_size (const fragS
*fragP
)
4550 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4551 return frag_format_size (next_fragP
);
4555 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4556 required two-byte instructions to be treated as three-byte instructions
4557 for loop instruction alignment. This restriction was removed beginning
4558 with Xtensa LX. Now the only requirement on loop instruction alignment
4559 is that the first instruction of the loop must appear at an address that
4560 does not cross a fetch boundary. */
4563 get_loop_align_size (int insn_size
)
4565 if (insn_size
== XTENSA_UNDEFINED
)
4566 return xtensa_fetch_width
;
4568 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4575 /* If the next legit fragment is an end-of-loop marker,
4576 switch its state so it will instantiate a NOP. */
4579 update_next_frag_state (fragS
*fragP
)
4581 fragS
*next_fragP
= fragP
->fr_next
;
4582 fragS
*new_target
= NULL
;
4586 /* We are guaranteed there will be one of these... */
4587 while (!(next_fragP
->fr_type
== rs_machine_dependent
4588 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4589 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4590 next_fragP
= next_fragP
->fr_next
;
4592 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4593 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4594 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4596 /* ...and one of these. */
4597 new_target
= next_fragP
->fr_next
;
4598 while (!(new_target
->fr_type
== rs_machine_dependent
4599 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4600 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4601 new_target
= new_target
->fr_next
;
4603 gas_assert (new_target
->fr_type
== rs_machine_dependent
4604 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4605 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4608 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4610 if (next_fragP
->fr_type
== rs_machine_dependent
4611 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4613 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4617 next_fragP
= next_fragP
->fr_next
;
4623 next_frag_is_branch_target (const fragS
*fragP
)
4625 /* Sometimes an empty will end up here due to storage allocation issues,
4626 so we have to skip until we find something legit. */
4627 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4629 if (fragP
->tc_frag_data
.is_branch_target
)
4631 if (fragP
->fr_fix
!= 0)
4639 next_frag_is_loop_target (const fragS
*fragP
)
4641 /* Sometimes an empty will end up here due storage allocation issues.
4642 So we have to skip until we find something legit. */
4643 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4645 if (fragP
->tc_frag_data
.is_loop_target
)
4647 if (fragP
->fr_fix
!= 0)
4654 /* As specified in the relaxation table, when a loop instruction is
4655 relaxed, there are 24 bytes between the loop instruction itself and
4656 the first instruction in the loop. */
4658 #define RELAXED_LOOP_INSN_BYTES 24
4661 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4663 const fragS
*next_fragp
= fragp
->fr_next
;
4664 xtensa_opcode next_opcode
;
4666 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4669 /* Sometimes an empty will end up here due to storage allocation issues,
4670 so we have to skip until we find something legit. */
4671 while (next_fragp
->fr_fix
== 0)
4672 next_fragp
= next_fragp
->fr_next
;
4674 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4677 /* There is some implicit knowledge encoded in here.
4678 The LOOP instructions that are NOT RELAX_IMMED have
4679 been relaxed. Note that we can assume that the LOOP
4680 instruction is in slot 0 because loops aren't bundleable. */
4681 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4682 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4688 /* Mark a location where we can later insert literal frags. Update
4689 the section's literal_pool_loc, so subsequent literals can be
4690 placed nearest to their use. */
4693 xtensa_mark_literal_pool_location (void)
4695 /* Any labels pointing to the current location need
4696 to be adjusted to after the literal pool. */
4698 fragS
*pool_location
;
4700 if (use_literal_section
)
4703 /* We stash info in these frags so we can later move the literal's
4704 fixes into this frchain's fix list. */
4705 pool_location
= frag_now
;
4706 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4707 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4708 frag_variant (rs_machine_dependent
, 0, 0,
4709 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4710 xtensa_set_frag_assembly_state (frag_now
);
4711 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4712 frag_variant (rs_machine_dependent
, 0, 0,
4713 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4714 xtensa_set_frag_assembly_state (frag_now
);
4716 /* Now put a frag into the literal pool that points to this location. */
4717 set_literal_pool_location (now_seg
, pool_location
);
4718 xtensa_switch_to_non_abs_literal_fragment (&s
);
4719 frag_align (2, 0, 0);
4720 record_alignment (now_seg
, 2);
4722 /* Close whatever frag is there. */
4723 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4724 xtensa_set_frag_assembly_state (frag_now
);
4725 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4726 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4727 xtensa_restore_emit_state (&s
);
4728 xtensa_set_frag_assembly_state (frag_now
);
4732 /* Build a nop of the correct size into tinsn. */
4735 build_nop (TInsn
*tinsn
, int size
)
4741 tinsn
->opcode
= xtensa_nop_n_opcode
;
4743 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4744 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4748 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4750 tinsn
->opcode
= xtensa_or_opcode
;
4751 set_expr_const (&tinsn
->tok
[0], 1);
4752 set_expr_const (&tinsn
->tok
[1], 1);
4753 set_expr_const (&tinsn
->tok
[2], 1);
4757 tinsn
->opcode
= xtensa_nop_opcode
;
4759 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4764 /* Assemble a NOP of the requested size in the buffer. User must have
4765 allocated "buf" with at least "size" bytes. */
4768 assemble_nop (int size
, char *buf
)
4770 static xtensa_insnbuf insnbuf
= NULL
;
4773 build_nop (&tinsn
, size
);
4776 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4778 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4779 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4780 (unsigned char *) buf
, 0);
4784 /* Return the number of bytes for the offset of the expanded loop
4785 instruction. This should be incorporated into the relaxation
4786 specification but is hard-coded here. This is used to auto-align
4787 the loop instruction. It is invalid to call this function if the
4788 configuration does not have loops or if the opcode is not a loop
4792 get_expanded_loop_offset (xtensa_opcode opcode
)
4794 /* This is the OFFSET of the loop instruction in the expanded loop.
4795 This MUST correspond directly to the specification of the loop
4796 expansion. It will be validated on fragment conversion. */
4797 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4798 if (opcode
== xtensa_loop_opcode
)
4800 if (opcode
== xtensa_loopnez_opcode
)
4802 if (opcode
== xtensa_loopgtz_opcode
)
4804 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4810 get_literal_pool_location (segT seg
)
4812 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4817 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4819 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4823 /* Set frag assembly state should be called when a new frag is
4824 opened and after a frag has been closed. */
4827 xtensa_set_frag_assembly_state (fragS
*fragP
)
4829 if (!density_supported
)
4830 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4832 /* This function is called from subsegs_finish, which is called
4833 after xtensa_end, so we can't use "use_transform" or
4834 "use_schedule" here. */
4835 if (!directive_state
[directive_transform
])
4836 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4837 if (directive_state
[directive_longcalls
])
4838 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4839 fragP
->tc_frag_data
.use_absolute_literals
=
4840 directive_state
[directive_absolute_literals
];
4841 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4846 relaxable_section (asection
*sec
)
4848 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4849 && strcmp (sec
->name
, ".eh_frame") != 0);
4854 xtensa_mark_frags_for_org (void)
4858 /* Walk over each fragment of all of the current segments. If we find
4859 a .org frag in any of the segments, mark all frags prior to it as
4860 "no transform", which will prevent linker optimizations from messing
4861 up the .org distance. This should be done after
4862 xtensa_find_unmarked_state_frags, because we don't want to worry here
4863 about that function trashing the data we save here. */
4865 for (seclist
= &stdoutput
->sections
;
4866 seclist
&& *seclist
;
4867 seclist
= &(*seclist
)->next
)
4869 segT sec
= *seclist
;
4870 segment_info_type
*seginfo
;
4873 flags
= bfd_get_section_flags (stdoutput
, sec
);
4874 if (flags
& SEC_DEBUGGING
)
4876 if (!(flags
& SEC_ALLOC
))
4879 seginfo
= seg_info (sec
);
4880 if (seginfo
&& seginfo
->frchainP
)
4882 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4883 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4884 fragP
= fragP
->fr_next
)
4886 /* cvt_frag_to_fill has changed the fr_type of org frags to
4887 rs_fill, so use the value as cached in rs_subtype here. */
4888 if (fragP
->fr_subtype
== RELAX_ORG
)
4890 while (last_fragP
!= fragP
->fr_next
)
4892 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4893 last_fragP
= last_fragP
->fr_next
;
4903 xtensa_find_unmarked_state_frags (void)
4907 /* Walk over each fragment of all of the current segments. For each
4908 unmarked fragment, mark it with the same info as the previous
4910 for (seclist
= &stdoutput
->sections
;
4911 seclist
&& *seclist
;
4912 seclist
= &(*seclist
)->next
)
4914 segT sec
= *seclist
;
4915 segment_info_type
*seginfo
;
4918 flags
= bfd_get_section_flags (stdoutput
, sec
);
4919 if (flags
& SEC_DEBUGGING
)
4921 if (!(flags
& SEC_ALLOC
))
4924 seginfo
= seg_info (sec
);
4925 if (seginfo
&& seginfo
->frchainP
)
4927 fragS
*last_fragP
= 0;
4928 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4929 fragP
= fragP
->fr_next
)
4931 if (fragP
->fr_fix
!= 0
4932 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4934 if (last_fragP
== 0)
4936 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4937 _("assembly state not set for first frag in section %s"),
4942 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4943 fragP
->tc_frag_data
.is_no_density
=
4944 last_fragP
->tc_frag_data
.is_no_density
;
4945 fragP
->tc_frag_data
.is_no_transform
=
4946 last_fragP
->tc_frag_data
.is_no_transform
;
4947 fragP
->tc_frag_data
.use_longcalls
=
4948 last_fragP
->tc_frag_data
.use_longcalls
;
4949 fragP
->tc_frag_data
.use_absolute_literals
=
4950 last_fragP
->tc_frag_data
.use_absolute_literals
;
4953 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4962 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4964 void *unused ATTRIBUTE_UNUSED
)
4966 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4967 segment_info_type
*seginfo
= seg_info (sec
);
4968 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4970 if (flags
& SEC_CODE
)
4972 xtensa_isa isa
= xtensa_default_isa
;
4973 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4974 while (frag
!= NULL
)
4976 if (frag
->tc_frag_data
.is_branch_target
)
4979 addressT branch_align
, frag_addr
;
4982 xtensa_insnbuf_from_chars
4983 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4984 fmt
= xtensa_format_decode (isa
, insnbuf
);
4985 op_size
= xtensa_format_length (isa
, fmt
);
4986 branch_align
= 1 << branch_align_power (sec
);
4987 frag_addr
= frag
->fr_address
% branch_align
;
4988 if (frag_addr
+ op_size
> branch_align
)
4989 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4990 _("unaligned branch target: %d bytes at 0x%lx"),
4991 op_size
, (long) frag
->fr_address
);
4993 frag
= frag
->fr_next
;
4995 xtensa_insnbuf_free (isa
, insnbuf
);
5001 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5003 void *unused ATTRIBUTE_UNUSED
)
5005 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5006 segment_info_type
*seginfo
= seg_info (sec
);
5007 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5008 xtensa_isa isa
= xtensa_default_isa
;
5010 if (flags
& SEC_CODE
)
5012 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5013 while (frag
!= NULL
)
5015 if (frag
->tc_frag_data
.is_first_loop_insn
)
5021 if (frag
->fr_fix
== 0)
5022 frag
= next_non_empty_frag (frag
);
5026 xtensa_insnbuf_from_chars
5027 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5028 fmt
= xtensa_format_decode (isa
, insnbuf
);
5029 op_size
= xtensa_format_length (isa
, fmt
);
5030 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5032 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5033 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5034 _("unaligned loop: %d bytes at 0x%lx"),
5035 op_size
, (long) frag
->fr_address
);
5038 frag
= frag
->fr_next
;
5040 xtensa_insnbuf_free (isa
, insnbuf
);
5046 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5048 xtensa_isa isa
= xtensa_default_isa
;
5049 static xtensa_insnbuf insnbuf
= NULL
;
5050 static xtensa_insnbuf slotbuf
= NULL
;
5053 bfd_boolean alt_reloc
;
5054 xtensa_opcode opcode
;
5055 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5057 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5059 as_fatal (_("unexpected fix"));
5063 insnbuf
= xtensa_insnbuf_alloc (isa
);
5064 slotbuf
= xtensa_insnbuf_alloc (isa
);
5067 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5068 fmt
= xtensa_format_decode (isa
, insnbuf
);
5069 if (fmt
== XTENSA_UNDEFINED
)
5070 as_fatal (_("undecodable fix"));
5071 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5072 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5073 if (opcode
== XTENSA_UNDEFINED
)
5074 as_fatal (_("undecodable fix"));
5076 /* CONST16 immediates are not PC-relative, despite the fact that we
5077 reuse the normal PC-relative operand relocations for the low part
5078 of a CONST16 operand. */
5079 if (opcode
== xtensa_const16_opcode
)
5082 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5083 get_relaxable_immed (opcode
), val
,
5084 fixP
->fx_file
, fixP
->fx_line
);
5086 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5087 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5093 /* External Functions and Other GAS Hooks. */
5096 xtensa_target_format (void)
5098 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5103 xtensa_file_arch_init (bfd
*abfd
)
5105 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5110 md_number_to_chars (char *buf
, valueT val
, int n
)
5112 if (target_big_endian
)
5113 number_to_chars_bigendian (buf
, val
, n
);
5115 number_to_chars_littleendian (buf
, val
, n
);
5119 /* This function is called once, at assembler startup time. It should
5120 set up all the tables, etc. that the MD part of the assembler will
5126 segT current_section
= now_seg
;
5127 int current_subsec
= now_subseg
;
5131 xtensa_default_isa
= xtensa_isa_init (0, 0);
5132 isa
= xtensa_default_isa
;
5136 /* Set up the literal sections. */
5137 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5139 subseg_set (current_section
, current_subsec
);
5141 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5142 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5143 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5144 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5145 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5146 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5147 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5148 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5149 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5150 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5151 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5152 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5153 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5154 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5155 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5156 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5157 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5158 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5159 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5160 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5161 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5162 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5163 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5164 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5165 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5166 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5167 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5168 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5169 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5170 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5171 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5173 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5175 int format_slots
= xtensa_format_num_slots (isa
, i
);
5176 if (format_slots
> config_max_slots
)
5177 config_max_slots
= format_slots
;
5180 xg_init_vinsn (&cur_vinsn
);
5182 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5184 init_op_placement_info_table ();
5186 /* Set up the assembly state. */
5187 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5188 xtensa_set_frag_assembly_state (frag_now
);
5192 /* TC_INIT_FIX_DATA hook */
5195 xtensa_init_fix_data (fixS
*x
)
5197 x
->tc_fix_data
.slot
= 0;
5198 x
->tc_fix_data
.X_add_symbol
= NULL
;
5199 x
->tc_fix_data
.X_add_number
= 0;
5203 /* tc_frob_label hook */
5206 xtensa_frob_label (symbolS
*sym
)
5210 if (cur_vinsn
.inside_bundle
)
5212 as_bad (_("labels are not valid inside bundles"));
5216 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5218 /* Since the label was already attached to a frag associated with the
5219 previous basic block, it now needs to be reset to the current frag. */
5220 symbol_set_frag (sym
, frag_now
);
5221 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5223 if (generating_literals
)
5224 xtensa_add_literal_sym (sym
);
5226 xtensa_add_insn_label (sym
);
5228 if (symbol_get_tc (sym
)->is_loop_target
)
5230 if ((get_last_insn_flags (now_seg
, now_subseg
)
5231 & FLAG_IS_BAD_LOOPEND
) != 0)
5232 as_bad (_("invalid last instruction for a zero-overhead loop"));
5234 xtensa_set_frag_assembly_state (frag_now
);
5235 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5236 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5238 xtensa_set_frag_assembly_state (frag_now
);
5239 xtensa_move_labels (frag_now
, 0);
5242 /* No target aligning in the absolute section. */
5243 if (now_seg
!= absolute_section
5244 && !is_unaligned_label (sym
)
5245 && !generating_literals
)
5247 xtensa_set_frag_assembly_state (frag_now
);
5249 if (do_align_targets ())
5250 frag_var (rs_machine_dependent
, 0, (int) freq
,
5251 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5252 frag_now
->fr_offset
, NULL
);
5254 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5255 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5256 xtensa_set_frag_assembly_state (frag_now
);
5257 xtensa_move_labels (frag_now
, 0);
5260 /* We need to mark the following properties even if we aren't aligning. */
5262 /* If the label is already known to be a branch target, i.e., a
5263 forward branch, mark the frag accordingly. Backward branches
5264 are handled by xg_add_branch_and_loop_targets. */
5265 if (symbol_get_tc (sym
)->is_branch_target
)
5266 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5268 /* Loops only go forward, so they can be identified here. */
5269 if (symbol_get_tc (sym
)->is_loop_target
)
5270 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5272 dwarf2_emit_label (sym
);
5276 /* tc_unrecognized_line hook */
5279 xtensa_unrecognized_line (int ch
)
5284 if (cur_vinsn
.inside_bundle
== 0)
5286 /* PR8110: Cannot emit line number info inside a FLIX bundle
5287 when using --gstabs. Temporarily disable debug info. */
5288 generate_lineno_debug ();
5289 if (debug_type
== DEBUG_STABS
)
5291 xt_saved_debug_type
= debug_type
;
5292 debug_type
= DEBUG_NONE
;
5295 cur_vinsn
.inside_bundle
= 1;
5299 as_bad (_("extra opening brace"));
5305 if (cur_vinsn
.inside_bundle
)
5306 finish_vinsn (&cur_vinsn
);
5309 as_bad (_("extra closing brace"));
5314 as_bad (_("syntax error"));
5321 /* md_flush_pending_output hook */
5324 xtensa_flush_pending_output (void)
5326 /* This line fixes a bug where automatically generated gstabs info
5327 separates a function label from its entry instruction, ending up
5328 with the literal position between the function label and the entry
5329 instruction and crashing code. It only happens with --gstabs and
5330 --text-section-literals, and when several other obscure relaxation
5331 conditions are met. */
5332 if (outputting_stabs_line_debug
)
5335 if (cur_vinsn
.inside_bundle
)
5336 as_bad (_("missing closing brace"));
5338 /* If there is a non-zero instruction fragment, close it. */
5339 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5341 frag_wane (frag_now
);
5343 xtensa_set_frag_assembly_state (frag_now
);
5345 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5347 xtensa_clear_insn_labels ();
5351 /* We had an error while parsing an instruction. The string might look
5352 like this: "insn arg1, arg2 }". If so, we need to see the closing
5353 brace and reset some fields. Otherwise, the vinsn never gets closed
5354 and the num_slots field will grow past the end of the array of slots,
5355 and bad things happen. */
5358 error_reset_cur_vinsn (void)
5360 if (cur_vinsn
.inside_bundle
)
5362 if (*input_line_pointer
== '}'
5363 || *(input_line_pointer
- 1) == '}'
5364 || *(input_line_pointer
- 2) == '}')
5365 xg_clear_vinsn (&cur_vinsn
);
5371 md_assemble (char *str
)
5373 xtensa_isa isa
= xtensa_default_isa
;
5376 bfd_boolean has_underbar
= FALSE
;
5377 char *arg_strings
[MAX_INSN_ARGS
];
5379 TInsn orig_insn
; /* Original instruction from the input. */
5381 tinsn_init (&orig_insn
);
5383 /* Split off the opcode. */
5384 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5385 opname
= xmalloc (opnamelen
+ 1);
5386 memcpy (opname
, str
, opnamelen
);
5387 opname
[opnamelen
] = '\0';
5389 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5392 as_bad (_("syntax error"));
5396 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5399 /* Check for an underbar prefix. */
5402 has_underbar
= TRUE
;
5406 orig_insn
.insn_type
= ITYPE_INSN
;
5408 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5409 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5411 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5412 extra argument and set the opcode to "CALLXn". */
5413 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5414 && strncasecmp (opname
, "callx", 5) == 0)
5416 unsigned long window_size
;
5419 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5420 if (suffix
!= opname
+ 5
5421 && (window_size
== 0
5424 || window_size
== 12)
5425 && strcasecmp (suffix
, ".tls") == 0)
5427 switch (window_size
)
5429 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5430 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5431 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5432 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5436 as_bad (_("wrong number of operands for '%s'"), opname
);
5439 bfd_reloc_code_real_type reloc
;
5440 char *old_input_line_pointer
;
5441 expressionS
*tok
= &orig_insn
.extra_arg
;
5443 old_input_line_pointer
= input_line_pointer
;
5444 input_line_pointer
= arg_strings
[num_args
- 1];
5447 if (tok
->X_op
== O_symbol
5448 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5449 == BFD_RELOC_XTENSA_TLS_CALL
))
5450 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5452 as_bad (_("bad relocation expression for '%s'"), opname
);
5454 input_line_pointer
= old_input_line_pointer
;
5460 /* Special case: Check for "j.l" psuedo op. */
5461 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5462 && strncasecmp (opname
, "j.l", 3) == 0)
5465 as_bad (_("wrong number of operands for '%s'"), opname
);
5468 char *old_input_line_pointer
;
5469 expressionS
*tok
= &orig_insn
.extra_arg
;
5471 old_input_line_pointer
= input_line_pointer
;
5472 input_line_pointer
= arg_strings
[num_args
- 1];
5474 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5475 input_line_pointer
= old_input_line_pointer
;
5478 orig_insn
.opcode
= xtensa_j_opcode
;
5482 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5484 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5485 if (fmt
== XTENSA_UNDEFINED
)
5487 as_bad (_("unknown opcode or format name '%s'"), opname
);
5488 error_reset_cur_vinsn ();
5491 if (!cur_vinsn
.inside_bundle
)
5493 as_bad (_("format names only valid inside bundles"));
5494 error_reset_cur_vinsn ();
5497 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5498 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5500 cur_vinsn
.format
= fmt
;
5501 free (has_underbar
? opname
- 1 : opname
);
5502 error_reset_cur_vinsn ();
5506 /* Parse the arguments. */
5507 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5509 as_bad (_("syntax error"));
5510 error_reset_cur_vinsn ();
5514 /* Free the opcode and argument strings, now that they've been parsed. */
5515 free (has_underbar
? opname
- 1 : opname
);
5517 while (num_args
-- > 0)
5518 free (arg_strings
[num_args
]);
5520 /* Get expressions for invisible operands. */
5521 if (get_invisible_operands (&orig_insn
))
5523 error_reset_cur_vinsn ();
5527 /* Check for the right number and type of arguments. */
5528 if (tinsn_check_arguments (&orig_insn
))
5530 error_reset_cur_vinsn ();
5534 /* Record the line number for each TInsn, because a FLIX bundle may be
5535 spread across multiple input lines and individual instructions may be
5536 moved around in some cases. */
5537 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5538 dwarf2_where (&orig_insn
.debug_line
);
5539 dwarf2_consume_line_info ();
5541 xg_add_branch_and_loop_targets (&orig_insn
);
5543 /* Check that immediate value for ENTRY is >= 16. */
5544 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5546 expressionS
*exp
= &orig_insn
.tok
[2];
5547 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5548 as_warn (_("entry instruction with stack decrement < 16"));
5552 assemble_tokens (opcode, tok, ntok);
5553 expand the tokens from the orig_insn into the
5554 stack of instructions that will not expand
5555 unless required at relaxation time. */
5557 if (!cur_vinsn
.inside_bundle
)
5558 emit_single_op (&orig_insn
);
5559 else /* We are inside a bundle. */
5561 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5562 cur_vinsn
.num_slots
++;
5563 if (*input_line_pointer
== '}'
5564 || *(input_line_pointer
- 1) == '}'
5565 || *(input_line_pointer
- 2) == '}')
5566 finish_vinsn (&cur_vinsn
);
5569 /* We've just emitted a new instruction so clear the list of labels. */
5570 xtensa_clear_insn_labels ();
5574 /* HANDLE_ALIGN hook */
5576 /* For a .align directive, we mark the previous block with the alignment
5577 information. This will be placed in the object file in the
5578 property section corresponding to this section. */
5581 xtensa_handle_align (fragS
*fragP
)
5584 && ! fragP
->tc_frag_data
.is_literal
5585 && (fragP
->fr_type
== rs_align
5586 || fragP
->fr_type
== rs_align_code
)
5587 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5588 && fragP
->fr_offset
> 0
5589 && now_seg
!= bss_section
)
5591 fragP
->tc_frag_data
.is_align
= TRUE
;
5592 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5595 if (fragP
->fr_type
== rs_align_test
)
5598 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5600 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5601 _("unaligned entry instruction"));
5604 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5605 fragP
->fr_subtype
= RELAX_ORG
;
5609 /* TC_FRAG_INIT hook */
5612 xtensa_frag_init (fragS
*frag
)
5614 xtensa_set_frag_assembly_state (frag
);
5619 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5625 /* Round up a section size to the appropriate boundary. */
5628 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5630 return size
; /* Byte alignment is fine. */
5635 md_pcrel_from (fixS
*fixP
)
5638 static xtensa_insnbuf insnbuf
= NULL
;
5639 static xtensa_insnbuf slotbuf
= NULL
;
5642 xtensa_opcode opcode
;
5645 xtensa_isa isa
= xtensa_default_isa
;
5646 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5647 bfd_boolean alt_reloc
;
5649 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5652 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5657 insnbuf
= xtensa_insnbuf_alloc (isa
);
5658 slotbuf
= xtensa_insnbuf_alloc (isa
);
5661 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5662 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5663 fmt
= xtensa_format_decode (isa
, insnbuf
);
5665 if (fmt
== XTENSA_UNDEFINED
)
5666 as_fatal (_("bad instruction format"));
5668 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5669 as_fatal (_("invalid relocation"));
5671 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5672 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5674 /* Check for "alternate" relocations (operand not specified). None
5675 of the current uses for these are really PC-relative. */
5676 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5678 if (opcode
!= xtensa_l32r_opcode
5679 && opcode
!= xtensa_const16_opcode
)
5680 as_fatal (_("invalid relocation for '%s' instruction"),
5681 xtensa_opcode_name (isa
, opcode
));
5685 opnum
= get_relaxable_immed (opcode
);
5687 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5688 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5690 as_bad_where (fixP
->fx_file
,
5692 _("invalid relocation for operand %d of '%s'"),
5693 opnum
, xtensa_opcode_name (isa
, opcode
));
5696 return 0 - opnd_value
;
5700 /* TC_FORCE_RELOCATION hook */
5703 xtensa_force_relocation (fixS
*fix
)
5705 switch (fix
->fx_r_type
)
5707 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5708 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5709 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5710 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5711 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5712 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5713 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5714 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5715 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5716 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5717 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5718 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5719 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5720 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5721 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5722 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5728 if (linkrelax
&& fix
->fx_addsy
5729 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5732 return generic_force_reloc (fix
);
5736 /* TC_VALIDATE_FIX_SUB hook */
5739 xtensa_validate_fix_sub (fixS
*fix
)
5741 segT add_symbol_segment
, sub_symbol_segment
;
5743 /* The difference of two symbols should be resolved by the assembler when
5744 linkrelax is not set. If the linker may relax the section containing
5745 the symbols, then an Xtensa DIFF relocation must be generated so that
5746 the linker knows to adjust the difference value. */
5747 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5750 /* Make sure both symbols are in the same segment, and that segment is
5751 "normal" and relaxable. If the segment is not "normal", then the
5752 fix is not valid. If the segment is not "relaxable", then the fix
5753 should have been handled earlier. */
5754 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5755 if (! SEG_NORMAL (add_symbol_segment
) ||
5756 ! relaxable_section (add_symbol_segment
))
5758 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5759 return (sub_symbol_segment
== add_symbol_segment
);
5763 /* NO_PSEUDO_DOT hook */
5765 /* This function has nothing to do with pseudo dots, but this is the
5766 nearest macro to where the check needs to take place. FIXME: This
5770 xtensa_check_inside_bundle (void)
5772 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5773 as_bad (_("directives are not valid inside bundles"));
5775 /* This function must always return FALSE because it is called via a
5776 macro that has nothing to do with bundling. */
5781 /* md_elf_section_change_hook */
5784 xtensa_elf_section_change_hook (void)
5786 /* Set up the assembly state. */
5787 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5788 xtensa_set_frag_assembly_state (frag_now
);
5792 /* tc_fix_adjustable hook */
5795 xtensa_fix_adjustable (fixS
*fixP
)
5797 /* We need the symbol name for the VTABLE entries. */
5798 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5799 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5806 /* tc_symbol_new_hook */
5808 symbolS
*expr_symbols
= NULL
;
5811 xtensa_symbol_new_hook (symbolS
*sym
)
5813 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5815 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5822 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5824 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5827 /* Subtracted symbols are only allowed for a few relocation types, and
5828 unless linkrelax is enabled, they should not make it to this point. */
5829 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5830 || fixP
->fx_r_type
== BFD_RELOC_16
5831 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5834 switch (fixP
->fx_r_type
)
5836 case BFD_RELOC_32_PCREL
:
5842 switch (fixP
->fx_r_type
)
5845 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5848 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5851 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5857 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5858 - S_GET_VALUE (fixP
->fx_subsy
));
5860 /* The difference value gets written out, and the DIFF reloc
5861 identifies the address of the subtracted symbol (i.e., the one
5862 with the lowest address). */
5864 fixP
->fx_offset
-= val
;
5865 fixP
->fx_subsy
= NULL
;
5867 else if (! fixP
->fx_addsy
)
5874 case BFD_RELOC_XTENSA_PLT
:
5875 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5876 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5879 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5880 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5881 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5882 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5883 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5884 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5885 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5888 case BFD_RELOC_XTENSA_SLOT0_OP
:
5889 case BFD_RELOC_XTENSA_SLOT1_OP
:
5890 case BFD_RELOC_XTENSA_SLOT2_OP
:
5891 case BFD_RELOC_XTENSA_SLOT3_OP
:
5892 case BFD_RELOC_XTENSA_SLOT4_OP
:
5893 case BFD_RELOC_XTENSA_SLOT5_OP
:
5894 case BFD_RELOC_XTENSA_SLOT6_OP
:
5895 case BFD_RELOC_XTENSA_SLOT7_OP
:
5896 case BFD_RELOC_XTENSA_SLOT8_OP
:
5897 case BFD_RELOC_XTENSA_SLOT9_OP
:
5898 case BFD_RELOC_XTENSA_SLOT10_OP
:
5899 case BFD_RELOC_XTENSA_SLOT11_OP
:
5900 case BFD_RELOC_XTENSA_SLOT12_OP
:
5901 case BFD_RELOC_XTENSA_SLOT13_OP
:
5902 case BFD_RELOC_XTENSA_SLOT14_OP
:
5905 /* Write the tentative value of a PC-relative relocation to a
5906 local symbol into the instruction. The value will be ignored
5907 by the linker, and it makes the object file disassembly
5908 readable when all branch targets are encoded in relocations. */
5910 gas_assert (fixP
->fx_addsy
);
5911 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5912 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5914 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5915 - md_pcrel_from (fixP
));
5916 (void) xg_apply_fix_value (fixP
, val
);
5919 else if (! fixP
->fx_addsy
)
5922 if (xg_apply_fix_value (fixP
, val
))
5927 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5928 case BFD_RELOC_XTENSA_TLS_FUNC
:
5929 case BFD_RELOC_XTENSA_TLS_ARG
:
5930 case BFD_RELOC_XTENSA_TLS_CALL
:
5931 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5932 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5933 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5934 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5935 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5936 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5937 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5938 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5939 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5940 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5941 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5942 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5943 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5944 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5945 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5946 /* These all need to be resolved at link-time. Do nothing now. */
5949 case BFD_RELOC_VTABLE_INHERIT
:
5950 case BFD_RELOC_VTABLE_ENTRY
:
5955 as_bad (_("unhandled local relocation fix %s"),
5956 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5962 md_atof (int type
, char *litP
, int *sizeP
)
5964 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5969 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5971 return total_frag_text_expansion (fragP
);
5975 /* Translate internal representation of relocation info to BFD target
5979 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5983 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5984 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5985 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5986 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5988 /* Make sure none of our internal relocations make it this far.
5989 They'd better have been fully resolved by this point. */
5990 gas_assert ((int) fixp
->fx_r_type
> 0);
5992 reloc
->addend
= fixp
->fx_offset
;
5994 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5995 if (reloc
->howto
== NULL
)
5997 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5998 _("cannot represent `%s' relocation in object file"),
5999 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6000 free (reloc
->sym_ptr_ptr
);
6005 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6006 as_fatal (_("internal error; cannot generate `%s' relocation"),
6007 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6013 /* Checks for resource conflicts between instructions. */
6015 /* The func unit stuff could be implemented as bit-vectors rather
6016 than the iterative approach here. If it ends up being too
6017 slow, we will switch it. */
6020 new_resource_table (void *data
,
6023 unit_num_copies_func uncf
,
6024 opcode_num_units_func onuf
,
6025 opcode_funcUnit_use_unit_func ouuf
,
6026 opcode_funcUnit_use_stage_func ousf
)
6029 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
6031 rt
->cycles
= cycles
;
6032 rt
->allocated_cycles
= cycles
;
6034 rt
->unit_num_copies
= uncf
;
6035 rt
->opcode_num_units
= onuf
;
6036 rt
->opcode_unit_use
= ouuf
;
6037 rt
->opcode_unit_stage
= ousf
;
6039 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6040 for (i
= 0; i
< cycles
; i
++)
6041 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6048 clear_resource_table (resource_table
*rt
)
6051 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6052 for (j
= 0; j
< rt
->num_units
; j
++)
6053 rt
->units
[i
][j
] = 0;
6057 /* We never shrink it, just fake it into thinking so. */
6060 resize_resource_table (resource_table
*rt
, int cycles
)
6064 rt
->cycles
= cycles
;
6065 if (cycles
<= rt
->allocated_cycles
)
6068 old_cycles
= rt
->allocated_cycles
;
6069 rt
->allocated_cycles
= cycles
;
6071 rt
->units
= xrealloc (rt
->units
,
6072 rt
->allocated_cycles
* sizeof (unsigned char *));
6073 for (i
= 0; i
< old_cycles
; i
++)
6074 rt
->units
[i
] = xrealloc (rt
->units
[i
],
6075 rt
->num_units
* sizeof (unsigned char));
6076 for (i
= old_cycles
; i
< cycles
; i
++)
6077 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6082 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6085 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6087 for (i
= 0; i
< uses
; i
++)
6089 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6090 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6091 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6092 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6093 if (copies_in_use
>= copies
)
6101 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6104 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6106 for (i
= 0; i
< uses
; i
++)
6108 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6109 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6110 /* Note that this allows resources to be oversubscribed. That's
6111 essential to the way the optional scheduler works.
6112 resources_available reports when a resource is over-subscribed,
6113 so it's easy to tell. */
6114 rt
->units
[stage
+ cycle
][unit
]++;
6120 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6123 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6125 for (i
= 0; i
< uses
; i
++)
6127 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6128 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6129 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6130 rt
->units
[stage
+ cycle
][unit
]--;
6135 /* Wrapper functions make parameterized resource reservation
6139 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6141 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6147 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6149 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6154 /* Note that this function does not check issue constraints, but
6155 solely whether the hardware is available to execute the given
6156 instructions together. It also doesn't check if the tinsns
6157 write the same state, or access the same tieports. That is
6158 checked by check_t1_t2_reads_and_writes. */
6161 resources_conflict (vliw_insn
*vinsn
)
6164 static resource_table
*rt
= NULL
;
6166 /* This is the most common case by far. Optimize it. */
6167 if (vinsn
->num_slots
== 1)
6172 xtensa_isa isa
= xtensa_default_isa
;
6173 rt
= new_resource_table
6174 (isa
, xtensa_num_pipe_stages
,
6175 xtensa_isa_num_funcUnits (isa
),
6176 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6177 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6178 opcode_funcUnit_use_unit
,
6179 opcode_funcUnit_use_stage
);
6182 clear_resource_table (rt
);
6184 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6186 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6188 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6195 /* finish_vinsn, emit_single_op and helper functions. */
6197 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6198 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6199 static void xg_assemble_vliw_tokens (vliw_insn
*);
6202 /* We have reached the end of a bundle; emit into the frag. */
6205 finish_vinsn (vliw_insn
*vinsn
)
6212 if (find_vinsn_conflicts (vinsn
))
6214 xg_clear_vinsn (vinsn
);
6218 /* First, find a format that works. */
6219 if (vinsn
->format
== XTENSA_UNDEFINED
)
6220 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6222 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6223 && produce_flix
== FLIX_NONE
)
6225 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6226 xg_clear_vinsn (vinsn
);
6230 if (vinsn
->format
== XTENSA_UNDEFINED
)
6232 as_where (&file_name
, &line
);
6233 as_bad_where (file_name
, line
,
6234 _("couldn't find a valid instruction format"));
6235 fprintf (stderr
, _(" ops were: "));
6236 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6237 fprintf (stderr
, _(" %s;"),
6238 xtensa_opcode_name (xtensa_default_isa
,
6239 vinsn
->slots
[i
].opcode
));
6240 fprintf (stderr
, _("\n"));
6241 xg_clear_vinsn (vinsn
);
6245 if (vinsn
->num_slots
6246 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6248 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6249 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6250 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6252 xg_clear_vinsn (vinsn
);
6256 if (resources_conflict (vinsn
))
6258 as_where (&file_name
, &line
);
6259 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6260 fprintf (stderr
, " ops were: ");
6261 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6262 fprintf (stderr
, " %s;",
6263 xtensa_opcode_name (xtensa_default_isa
,
6264 vinsn
->slots
[i
].opcode
));
6265 fprintf (stderr
, "\n");
6266 xg_clear_vinsn (vinsn
);
6270 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6272 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6274 symbolS
*lit_sym
= NULL
;
6276 bfd_boolean e
= FALSE
;
6277 bfd_boolean saved_density
= density_supported
;
6279 /* We don't want to narrow ops inside multi-slot bundles. */
6280 if (vinsn
->num_slots
> 1)
6281 density_supported
= FALSE
;
6283 istack_init (&slotstack
);
6284 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6286 vinsn
->slots
[i
].opcode
=
6287 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6289 vinsn
->slots
[i
].ntok
= 0;
6292 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6298 density_supported
= saved_density
;
6302 xg_clear_vinsn (vinsn
);
6306 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6308 TInsn
*insn
= &slotstack
.insn
[j
];
6309 if (insn
->insn_type
== ITYPE_LITERAL
)
6311 gas_assert (lit_sym
== NULL
);
6312 lit_sym
= xg_assemble_literal (insn
);
6316 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6318 xg_resolve_literals (insn
, lit_sym
);
6319 if (j
!= slotstack
.ninsn
- 1)
6320 emit_single_op (insn
);
6324 if (vinsn
->num_slots
> 1)
6326 if (opcode_fits_format_slot
6327 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6330 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6334 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6335 if (vinsn
->format
== XTENSA_UNDEFINED
)
6336 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6338 vinsn
->slots
[i
].opcode
6339 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6342 vinsn
->slots
[i
].ntok
= 0;
6347 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6348 vinsn
->format
= XTENSA_UNDEFINED
;
6353 /* Now check resource conflicts on the modified bundle. */
6354 if (resources_conflict (vinsn
))
6356 as_where (&file_name
, &line
);
6357 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6358 fprintf (stderr
, " ops were: ");
6359 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6360 fprintf (stderr
, " %s;",
6361 xtensa_opcode_name (xtensa_default_isa
,
6362 vinsn
->slots
[i
].opcode
));
6363 fprintf (stderr
, "\n");
6364 xg_clear_vinsn (vinsn
);
6368 /* First, find a format that works. */
6369 if (vinsn
->format
== XTENSA_UNDEFINED
)
6370 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6372 xg_assemble_vliw_tokens (vinsn
);
6374 xg_clear_vinsn (vinsn
);
6378 /* Given an vliw instruction, what conflicts are there in register
6379 usage and in writes to states and queues?
6381 This function does two things:
6382 1. Reports an error when a vinsn contains illegal combinations
6383 of writes to registers states or queues.
6384 2. Marks individual tinsns as not relaxable if the combination
6385 contains antidependencies.
6387 Job 2 handles things like swap semantics in instructions that need
6388 to be relaxed. For example,
6392 normally would be relaxed to
6397 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6399 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6401 then we can't relax it into
6404 { add a0, a1, a0 ; add a2, a0, a4 ; }
6406 because the value of a0 is trashed before the second add can read it. */
6408 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6411 find_vinsn_conflicts (vliw_insn
*vinsn
)
6415 xtensa_isa isa
= xtensa_default_isa
;
6417 gas_assert (!past_xtensa_end
);
6419 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6421 TInsn
*op1
= &vinsn
->slots
[i
];
6422 if (op1
->is_specific_opcode
)
6423 op1
->keep_wide
= TRUE
;
6425 op1
->keep_wide
= FALSE
;
6428 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6430 TInsn
*op1
= &vinsn
->slots
[i
];
6432 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6435 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6439 TInsn
*op2
= &vinsn
->slots
[j
];
6440 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6441 switch (conflict_type
)
6444 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6445 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6446 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6449 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6450 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6451 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6454 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6455 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6456 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6459 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6460 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6461 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6464 /* Everything is OK. */
6467 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6468 || conflict_type
== 'a');
6475 as_bad (_("multiple branches or jumps in the same bundle"));
6483 /* Check how the state used by t1 and t2 relate.
6486 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6487 case B: no relationship between what is read and written (both could
6488 read the same reg though)
6489 case C: t1 writes a register t2 writes (a register conflict within a
6491 case D: t1 writes a state that t2 also writes
6492 case E: t1 writes a tie queue that t2 also writes
6493 case F: two volatile queue accesses
6497 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6499 xtensa_isa isa
= xtensa_default_isa
;
6500 xtensa_regfile t1_regfile
, t2_regfile
;
6502 int t1_base_reg
, t1_last_reg
;
6503 int t2_base_reg
, t2_last_reg
;
6504 char t1_inout
, t2_inout
;
6506 char conflict
= 'b';
6511 bfd_boolean t1_volatile
= FALSE
;
6512 bfd_boolean t2_volatile
= FALSE
;
6514 /* Check registers. */
6515 for (j
= 0; j
< t2
->ntok
; j
++)
6517 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6520 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6521 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6522 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6524 for (i
= 0; i
< t1
->ntok
; i
++)
6526 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6529 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6531 if (t1_regfile
!= t2_regfile
)
6534 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6535 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6537 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6538 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6540 if (t1_inout
== 'm' || t1_inout
== 'o'
6541 || t2_inout
== 'm' || t2_inout
== 'o')
6548 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6549 t1_last_reg
= (t1_base_reg
6550 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6552 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6554 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6556 if (t1_reg
!= t2_reg
)
6559 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6565 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6571 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6579 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6580 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6581 for (j
= 0; j
< t2_states
; j
++)
6583 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6584 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6585 for (i
= 0; i
< t1_states
; i
++)
6587 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6588 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6589 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6592 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6598 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6604 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6609 /* Check tieports. */
6610 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6611 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6612 for (j
= 0; j
< t2_interfaces
; j
++)
6614 xtensa_interface t2_int
6615 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6616 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6618 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6619 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6622 for (i
= 0; i
< t1_interfaces
; i
++)
6624 xtensa_interface t1_int
6625 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6626 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6628 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6629 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6632 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6635 if (t1_int
!= t2_int
)
6638 if (t2_inout
== 'i' && t1_inout
== 'o')
6644 if (t1_inout
== 'i' && t2_inout
== 'o')
6650 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6659 static xtensa_format
6660 xg_find_narrowest_format (vliw_insn
*vinsn
)
6662 /* Right now we assume that the ops within the vinsn are properly
6663 ordered for the slots that the programmer wanted them in. In
6664 other words, we don't rearrange the ops in hopes of finding a
6665 better format. The scheduler handles that. */
6667 xtensa_isa isa
= xtensa_default_isa
;
6668 xtensa_format format
;
6669 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6671 if (vinsn
->num_slots
== 1)
6672 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6674 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6677 xg_copy_vinsn (&v_copy
, vinsn
);
6678 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6682 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6684 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6686 v_copy
.slots
[slot
].opcode
=
6687 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6688 v_copy
.slots
[slot
].ntok
= 0;
6691 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6694 else if (v_copy
.num_slots
> 1)
6697 /* Try the widened version. */
6698 if (!v_copy
.slots
[slot
].keep_wide
6699 && !v_copy
.slots
[slot
].is_specific_opcode
6700 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6702 && opcode_fits_format_slot (widened
.opcode
,
6705 v_copy
.slots
[slot
] = widened
;
6710 if (fit
== v_copy
.num_slots
)
6712 xg_copy_vinsn (vinsn
, &v_copy
);
6713 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6714 vinsn
->format
= format
;
6720 if (format
== xtensa_isa_num_formats (isa
))
6721 return XTENSA_UNDEFINED
;
6727 /* Return the additional space needed in a frag
6728 for possible relaxations of any ops in a VLIW insn.
6729 Also fill out the relaxations that might be required of
6730 each tinsn in the vinsn. */
6733 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6735 bfd_boolean finish_frag
= FALSE
;
6736 int extra_space
= 0;
6739 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6741 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6742 if (!tinsn_has_symbolic_operands (tinsn
))
6744 /* A narrow instruction could be widened later to help
6745 alignment issues. */
6746 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6747 && !tinsn
->is_specific_opcode
6748 && vinsn
->num_slots
== 1)
6750 /* Difference in bytes between narrow and wide insns... */
6752 tinsn
->subtype
= RELAX_NARROW
;
6757 if (workaround_b_j_loop_end
6758 && tinsn
->opcode
== xtensa_jx_opcode
6759 && use_transform ())
6761 /* Add 2 of these. */
6762 extra_space
+= 3; /* for the nop size */
6763 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6766 /* Need to assemble it with space for the relocation. */
6767 if (xg_is_relaxable_insn (tinsn
, 0)
6768 && !tinsn
->is_specific_opcode
)
6770 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6771 int max_literal_size
=
6772 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6774 tinsn
->literal_space
= max_literal_size
;
6776 tinsn
->subtype
= RELAX_IMMED
;
6777 extra_space
+= max_size
;
6781 /* A fix record will be added for this instruction prior
6782 to relaxation, so make it end the frag. */
6787 *pfinish_frag
= finish_frag
;
6793 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6795 xtensa_isa isa
= xtensa_default_isa
;
6796 int slot
, chosen_slot
;
6798 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6799 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6800 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6802 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6803 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6805 if (slot
== chosen_slot
)
6806 vinsn
->slots
[slot
] = *tinsn
;
6809 vinsn
->slots
[slot
].opcode
=
6810 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6811 vinsn
->slots
[slot
].ntok
= 0;
6812 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6819 emit_single_op (TInsn
*orig_insn
)
6822 IStack istack
; /* put instructions into here */
6823 symbolS
*lit_sym
= NULL
;
6824 symbolS
*label_sym
= NULL
;
6826 istack_init (&istack
);
6828 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6829 Because the scheduling and bundling characteristics of movi and
6830 l32r or const16 are so different, we can do much better if we relax
6831 it prior to scheduling and bundling, rather than after. */
6832 if ((orig_insn
->opcode
== xtensa_movi_opcode
6833 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6834 && !cur_vinsn
.inside_bundle
6835 && (orig_insn
->tok
[1].X_op
== O_symbol
6836 || orig_insn
->tok
[1].X_op
== O_pltrel
6837 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6838 || orig_insn
->tok
[1].X_op
== O_tlsarg
6839 || orig_insn
->tok
[1].X_op
== O_tpoff
6840 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6841 && !orig_insn
->is_specific_opcode
&& use_transform ())
6842 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6844 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6847 for (i
= 0; i
< istack
.ninsn
; i
++)
6849 TInsn
*insn
= &istack
.insn
[i
];
6850 switch (insn
->insn_type
)
6853 gas_assert (lit_sym
== NULL
);
6854 lit_sym
= xg_assemble_literal (insn
);
6858 static int relaxed_sym_idx
= 0;
6859 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6860 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6862 gas_assert (label_sym
== NULL
);
6863 label_sym
= symbol_find_or_make (label
);
6864 gas_assert (label_sym
);
6872 xg_resolve_literals (insn
, lit_sym
);
6874 xg_resolve_labels (insn
, label_sym
);
6876 bundle_tinsn (insn
, &v
);
6891 total_frag_text_expansion (fragS
*fragP
)
6894 int total_expansion
= 0;
6896 for (slot
= 0; slot
< config_max_slots
; slot
++)
6897 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6899 return total_expansion
;
6903 /* Emit a vliw instruction to the current fragment. */
6906 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6908 bfd_boolean finish_frag
;
6909 bfd_boolean is_jump
= FALSE
;
6910 bfd_boolean is_branch
= FALSE
;
6911 xtensa_isa isa
= xtensa_default_isa
;
6916 struct dwarf2_line_info debug_line
;
6917 bfd_boolean loc_directive_seen
= FALSE
;
6920 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6922 if (generating_literals
)
6924 static int reported
= 0;
6926 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6927 _("cannot assemble into a literal fragment"));
6934 if (frag_now_fix () != 0
6935 && (! frag_now
->tc_frag_data
.is_insn
6936 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6937 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6938 || (directive_state
[directive_longcalls
]
6939 != frag_now
->tc_frag_data
.use_longcalls
)
6940 || (directive_state
[directive_absolute_literals
]
6941 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6943 frag_wane (frag_now
);
6945 xtensa_set_frag_assembly_state (frag_now
);
6948 if (workaround_a0_b_retw
6949 && vinsn
->num_slots
== 1
6950 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6951 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6952 && use_transform ())
6954 has_a0_b_retw
= TRUE
;
6956 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6957 After the first assembly pass we will check all of them and
6958 add a nop if needed. */
6959 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6960 frag_var (rs_machine_dependent
, 4, 4,
6961 RELAX_ADD_NOP_IF_A0_B_RETW
,
6962 frag_now
->fr_symbol
,
6963 frag_now
->fr_offset
,
6965 xtensa_set_frag_assembly_state (frag_now
);
6966 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6967 frag_var (rs_machine_dependent
, 4, 4,
6968 RELAX_ADD_NOP_IF_A0_B_RETW
,
6969 frag_now
->fr_symbol
,
6970 frag_now
->fr_offset
,
6972 xtensa_set_frag_assembly_state (frag_now
);
6975 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6977 tinsn
= &vinsn
->slots
[slot
];
6979 /* See if the instruction implies an aligned section. */
6980 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6981 record_alignment (now_seg
, 2);
6983 /* Determine the best line number for debug info. */
6984 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6985 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6986 || tinsn
->debug_line
.line
< debug_line
.line
6987 || tinsn
->debug_line
.column
< debug_line
.column
))
6988 debug_line
= tinsn
->debug_line
;
6989 if (tinsn
->loc_directive_seen
)
6990 loc_directive_seen
= TRUE
;
6993 /* Special cases for instructions that force an alignment... */
6994 /* None of these opcodes are bundle-able. */
6995 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6999 /* Remember the symbol that marks the end of the loop in the frag
7000 that marks the start of the loop. This way we can easily find
7001 the end of the loop at the beginning, without adding special code
7002 to mark the loop instructions themselves. */
7003 symbolS
*target_sym
= NULL
;
7004 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7005 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7007 xtensa_set_frag_assembly_state (frag_now
);
7008 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7010 max_fill
= get_text_align_max_fill_size
7011 (get_text_align_power (xtensa_fetch_width
),
7012 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7014 if (use_transform ())
7015 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7016 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7018 frag_var (rs_machine_dependent
, 0, 0,
7019 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7020 xtensa_set_frag_assembly_state (frag_now
);
7023 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7024 && !vinsn
->slots
[0].is_specific_opcode
)
7026 xtensa_mark_literal_pool_location ();
7027 xtensa_move_labels (frag_now
, 0);
7028 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7031 if (vinsn
->num_slots
== 1)
7033 if (workaround_a0_b_retw
&& use_transform ())
7034 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7035 is_register_writer (&vinsn
->slots
[0], "a", 0));
7037 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7038 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7041 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7043 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7045 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7047 /* vinsn_to_insnbuf will produce the error. */
7048 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7050 f
= frag_more (insn_size
+ extra_space
);
7051 xtensa_set_frag_assembly_state (frag_now
);
7052 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7055 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7056 if (vinsn
->format
== XTENSA_UNDEFINED
)
7059 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7061 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7062 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7065 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7067 tinsn
= &vinsn
->slots
[slot
];
7068 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7069 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7070 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7071 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7072 if (tinsn
->literal_space
!= 0)
7073 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7074 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7076 if (tinsn
->subtype
== RELAX_NARROW
)
7077 gas_assert (vinsn
->num_slots
== 1);
7078 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7080 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7083 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7084 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7088 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7089 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7093 frag_variant (rs_machine_dependent
,
7094 extra_space
, extra_space
, RELAX_SLOTS
,
7095 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7096 xtensa_set_frag_assembly_state (frag_now
);
7099 /* Special cases for loops:
7100 close_loop_end should be inserted AFTER short_loop.
7101 Make sure that CLOSE loops are processed BEFORE short_loops
7102 when converting them. */
7104 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7105 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7106 && !vinsn
->slots
[0].is_specific_opcode
)
7108 if (workaround_short_loop
&& use_transform ())
7110 maybe_has_short_loop
= TRUE
;
7111 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7112 frag_var (rs_machine_dependent
, 4, 4,
7113 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7114 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7115 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7116 frag_var (rs_machine_dependent
, 4, 4,
7117 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7118 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7121 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7122 loop at least 12 bytes away from another loop's end. */
7123 if (workaround_close_loop_end
&& use_transform ())
7125 maybe_has_close_loop_end
= TRUE
;
7126 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7127 frag_var (rs_machine_dependent
, 12, 12,
7128 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7129 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7133 if (use_transform ())
7137 gas_assert (finish_frag
);
7138 frag_var (rs_machine_dependent
,
7139 xtensa_fetch_width
, xtensa_fetch_width
,
7141 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7142 xtensa_set_frag_assembly_state (frag_now
);
7144 else if (is_branch
&& do_align_targets ())
7146 gas_assert (finish_frag
);
7147 frag_var (rs_machine_dependent
,
7148 xtensa_fetch_width
, xtensa_fetch_width
,
7149 RELAX_MAYBE_UNREACHABLE
,
7150 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7151 xtensa_set_frag_assembly_state (frag_now
);
7152 frag_var (rs_machine_dependent
,
7154 RELAX_MAYBE_DESIRE_ALIGN
,
7155 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7156 xtensa_set_frag_assembly_state (frag_now
);
7160 /* Now, if the original opcode was a call... */
7161 if (do_align_targets ()
7162 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7164 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7165 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7166 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7167 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7168 xtensa_set_frag_assembly_state (frag_now
);
7171 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7173 frag_wane (frag_now
);
7175 xtensa_set_frag_assembly_state (frag_now
);
7180 /* xtensa_end and helper functions. */
7182 static void xtensa_cleanup_align_frags (void);
7183 static void xtensa_fix_target_frags (void);
7184 static void xtensa_mark_narrow_branches (void);
7185 static void xtensa_mark_zcl_first_insns (void);
7186 static void xtensa_mark_difference_of_two_symbols (void);
7187 static void xtensa_fix_a0_b_retw_frags (void);
7188 static void xtensa_fix_b_j_loop_end_frags (void);
7189 static void xtensa_fix_close_loop_end_frags (void);
7190 static void xtensa_fix_short_loop_frags (void);
7191 static void xtensa_sanity_check (void);
7192 static void xtensa_add_config_info (void);
7197 directive_balance ();
7198 xtensa_flush_pending_output ();
7200 past_xtensa_end
= TRUE
;
7202 xtensa_move_literals ();
7204 xtensa_reorder_segments ();
7205 xtensa_cleanup_align_frags ();
7206 xtensa_fix_target_frags ();
7207 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7208 xtensa_fix_a0_b_retw_frags ();
7209 if (workaround_b_j_loop_end
)
7210 xtensa_fix_b_j_loop_end_frags ();
7212 /* "close_loop_end" should be processed BEFORE "short_loop". */
7213 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7214 xtensa_fix_close_loop_end_frags ();
7216 if (workaround_short_loop
&& maybe_has_short_loop
)
7217 xtensa_fix_short_loop_frags ();
7219 xtensa_mark_narrow_branches ();
7220 xtensa_mark_zcl_first_insns ();
7222 xtensa_sanity_check ();
7224 xtensa_add_config_info ();
7229 xtensa_cleanup_align_frags (void)
7234 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7235 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7238 /* Walk over all of the fragments in a subsection. */
7239 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7241 if ((fragP
->fr_type
== rs_align
7242 || fragP
->fr_type
== rs_align_code
7243 || (fragP
->fr_type
== rs_machine_dependent
7244 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7245 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7246 && fragP
->fr_fix
== 0)
7248 fragS
*next
= fragP
->fr_next
;
7251 && next
->fr_fix
== 0
7252 && next
->fr_type
== rs_machine_dependent
7253 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7256 next
= next
->fr_next
;
7259 /* If we don't widen branch targets, then they
7260 will be easier to align. */
7261 if (fragP
->tc_frag_data
.is_branch_target
7262 && fragP
->fr_opcode
== fragP
->fr_literal
7263 && fragP
->fr_type
== rs_machine_dependent
7264 && fragP
->fr_subtype
== RELAX_SLOTS
7265 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7267 if (fragP
->fr_type
== rs_machine_dependent
7268 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7269 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7275 /* Re-process all of the fragments looking to convert all of the
7276 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7277 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7278 Otherwise, convert to a .fill 0. */
7281 xtensa_fix_target_frags (void)
7286 /* When this routine is called, all of the subsections are still intact
7287 so we walk over subsections instead of sections. */
7288 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7289 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7293 /* Walk over all of the fragments in a subsection. */
7294 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7296 if (fragP
->fr_type
== rs_machine_dependent
7297 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7299 if (next_frag_is_branch_target (fragP
))
7300 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7309 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7312 xtensa_mark_narrow_branches (void)
7317 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7318 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7321 /* Walk over all of the fragments in a subsection. */
7322 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7324 if (fragP
->fr_type
== rs_machine_dependent
7325 && fragP
->fr_subtype
== RELAX_SLOTS
7326 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7330 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7331 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7333 if (vinsn
.num_slots
== 1
7334 && xtensa_opcode_is_branch (xtensa_default_isa
,
7335 vinsn
.slots
[0].opcode
) == 1
7336 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7337 && is_narrow_branch_guaranteed_in_range (fragP
,
7340 fragP
->fr_subtype
= RELAX_SLOTS
;
7341 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7342 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7350 /* A branch is typically widened only when its target is out of
7351 range. However, we would like to widen them to align a subsequent
7352 branch target when possible.
7354 Because the branch relaxation code is so convoluted, the optimal solution
7355 (combining the two cases) is difficult to get right in all circumstances.
7356 We therefore go with an "almost as good" solution, where we only
7357 use for alignment narrow branches that definitely will not expand to a
7358 jump and a branch. These functions find and mark these cases. */
7360 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7361 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7362 We start counting beginning with the frag after the 2-byte branch, so the
7363 maximum offset is (4 - 2) + 63 = 65. */
7364 #define MAX_IMMED6 65
7366 static offsetT
unrelaxed_frag_max_size (fragS
*);
7369 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7371 const expressionS
*exp
= &tinsn
->tok
[1];
7372 symbolS
*symbolP
= exp
->X_add_symbol
;
7373 offsetT max_distance
= exp
->X_add_number
;
7376 if (exp
->X_op
!= O_symbol
)
7379 target_frag
= symbol_get_frag (symbolP
);
7381 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7382 if (is_branch_jmp_to_next (tinsn
, fragP
))
7385 /* The branch doesn't branch over it's own frag,
7386 but over the subsequent ones. */
7387 fragP
= fragP
->fr_next
;
7388 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7390 max_distance
+= unrelaxed_frag_max_size (fragP
);
7391 fragP
= fragP
->fr_next
;
7393 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7400 xtensa_mark_zcl_first_insns (void)
7405 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7406 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7409 /* Walk over all of the fragments in a subsection. */
7410 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7412 if (fragP
->fr_type
== rs_machine_dependent
7413 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7414 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7416 /* Find the loop frag. */
7417 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7418 /* Find the first insn frag. */
7419 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
7421 /* Handle a corner case that comes up in hardware
7422 diagnostics. The original assembly looks like this:
7425 <empty_frag>--not found by next_non_empty_frag
7428 Depending on the start address, the assembler may or
7429 may not change it to look something like this:
7432 nop--frag isn't empty anymore
7435 So set up to check the alignment of the nop if it
7437 while (loop_frag
!= targ_frag
)
7439 if (loop_frag
->fr_type
== rs_machine_dependent
7440 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7441 || loop_frag
->fr_subtype
7442 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7443 targ_frag
= loop_frag
;
7445 loop_frag
= loop_frag
->fr_next
;
7448 /* Of course, sometimes (mostly for toy test cases) a
7449 zero-cost loop instruction is the last in a section. */
7452 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7453 /* Do not widen a frag that is the first instruction of a
7454 zero-cost loop. It makes that loop harder to align. */
7455 if (targ_frag
->fr_type
== rs_machine_dependent
7456 && targ_frag
->fr_subtype
== RELAX_SLOTS
7457 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7460 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7461 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7464 frag_wane (targ_frag
);
7465 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7469 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7477 /* When a difference-of-symbols expression is encoded as a uleb128 or
7478 sleb128 value, the linker is unable to adjust that value to account for
7479 link-time relaxation. Mark all the code between such symbols so that
7480 its size cannot be changed by linker relaxation. */
7483 xtensa_mark_difference_of_two_symbols (void)
7487 for (expr_sym
= expr_symbols
; expr_sym
;
7488 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7490 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7492 if (exp
->X_op
== O_subtract
)
7494 symbolS
*left
= exp
->X_add_symbol
;
7495 symbolS
*right
= exp
->X_op_symbol
;
7497 /* Difference of two symbols not in the same section
7498 are handled with relocations in the linker. */
7499 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7505 if (symbol_get_frag (left
)->fr_address
7506 <= symbol_get_frag (right
)->fr_address
)
7508 start
= symbol_get_frag (left
);
7509 end
= symbol_get_frag (right
);
7513 start
= symbol_get_frag (right
);
7514 end
= symbol_get_frag (left
);
7517 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7518 walk
= start
->tc_frag_data
.no_transform_end
;
7523 walk
->tc_frag_data
.is_no_transform
= 1;
7524 walk
= walk
->fr_next
;
7526 while (walk
&& walk
->fr_address
< end
->fr_address
);
7528 start
->tc_frag_data
.no_transform_end
= walk
;
7535 /* Re-process all of the fragments looking to convert all of the
7536 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7537 conditional branch or a retw/retw.n, convert this frag to one that
7538 will generate a NOP. In any case close it off with a .fill 0. */
7540 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7543 xtensa_fix_a0_b_retw_frags (void)
7548 /* When this routine is called, all of the subsections are still intact
7549 so we walk over subsections instead of sections. */
7550 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7551 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7555 /* Walk over all of the fragments in a subsection. */
7556 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7558 if (fragP
->fr_type
== rs_machine_dependent
7559 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7561 if (next_instrs_are_b_retw (fragP
))
7563 if (fragP
->tc_frag_data
.is_no_transform
)
7564 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7566 relax_frag_add_nop (fragP
);
7576 next_instrs_are_b_retw (fragS
*fragP
)
7578 xtensa_opcode opcode
;
7580 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7581 static xtensa_insnbuf insnbuf
= NULL
;
7582 static xtensa_insnbuf slotbuf
= NULL
;
7583 xtensa_isa isa
= xtensa_default_isa
;
7586 bfd_boolean branch_seen
= FALSE
;
7590 insnbuf
= xtensa_insnbuf_alloc (isa
);
7591 slotbuf
= xtensa_insnbuf_alloc (isa
);
7594 if (next_fragP
== NULL
)
7597 /* Check for the conditional branch. */
7598 xtensa_insnbuf_from_chars
7599 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7600 fmt
= xtensa_format_decode (isa
, insnbuf
);
7601 if (fmt
== XTENSA_UNDEFINED
)
7604 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7606 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7607 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7609 branch_seen
= (branch_seen
7610 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7616 offset
+= xtensa_format_length (isa
, fmt
);
7617 if (offset
== next_fragP
->fr_fix
)
7619 next_fragP
= next_non_empty_frag (next_fragP
);
7623 if (next_fragP
== NULL
)
7626 /* Check for the retw/retw.n. */
7627 xtensa_insnbuf_from_chars
7628 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7629 fmt
= xtensa_format_decode (isa
, insnbuf
);
7631 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7632 have no problems. */
7633 if (fmt
== XTENSA_UNDEFINED
7634 || xtensa_format_num_slots (isa
, fmt
) != 1)
7637 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7638 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7640 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7647 /* Re-process all of the fragments looking to convert all of the
7648 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7649 loop end label, convert this frag to one that will generate a NOP.
7650 In any case close it off with a .fill 0. */
7652 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7655 xtensa_fix_b_j_loop_end_frags (void)
7660 /* When this routine is called, all of the subsections are still intact
7661 so we walk over subsections instead of sections. */
7662 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7663 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7667 /* Walk over all of the fragments in a subsection. */
7668 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7670 if (fragP
->fr_type
== rs_machine_dependent
7671 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7673 if (next_instr_is_loop_end (fragP
))
7675 if (fragP
->tc_frag_data
.is_no_transform
)
7676 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7678 relax_frag_add_nop (fragP
);
7688 next_instr_is_loop_end (fragS
*fragP
)
7690 const fragS
*next_fragP
;
7692 if (next_frag_is_loop_target (fragP
))
7695 next_fragP
= next_non_empty_frag (fragP
);
7696 if (next_fragP
== NULL
)
7699 if (!next_frag_is_loop_target (next_fragP
))
7702 /* If the size is >= 3 then there is more than one instruction here.
7703 The hardware bug will not fire. */
7704 if (next_fragP
->fr_fix
> 3)
7711 /* Re-process all of the fragments looking to convert all of the
7712 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7713 not MY loop's loop end within 12 bytes, add enough nops here to
7714 make it at least 12 bytes away. In any case close it off with a
7717 static offsetT min_bytes_to_other_loop_end
7718 (fragS
*, fragS
*, offsetT
);
7721 xtensa_fix_close_loop_end_frags (void)
7726 /* When this routine is called, all of the subsections are still intact
7727 so we walk over subsections instead of sections. */
7728 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7729 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7733 fragS
*current_target
= NULL
;
7735 /* Walk over all of the fragments in a subsection. */
7736 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7738 if (fragP
->fr_type
== rs_machine_dependent
7739 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7740 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7741 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7744 && fragP
->fr_type
== rs_machine_dependent
7745 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7748 int bytes_added
= 0;
7750 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7751 /* Max out at 12. */
7752 min_bytes
= min_bytes_to_other_loop_end
7753 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7755 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7757 if (fragP
->tc_frag_data
.is_no_transform
)
7758 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7761 while (min_bytes
+ bytes_added
7762 < REQUIRED_LOOP_DIVIDING_BYTES
)
7766 if (fragP
->fr_var
< length
)
7767 as_fatal (_("fr_var %lu < length %d"),
7768 (long) fragP
->fr_var
, length
);
7771 assemble_nop (length
,
7772 fragP
->fr_literal
+ fragP
->fr_fix
);
7773 fragP
->fr_fix
+= length
;
7774 fragP
->fr_var
-= length
;
7776 bytes_added
+= length
;
7782 gas_assert (fragP
->fr_type
!= rs_machine_dependent
7783 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7789 static offsetT
unrelaxed_frag_min_size (fragS
*);
7792 min_bytes_to_other_loop_end (fragS
*fragP
,
7793 fragS
*current_target
,
7797 fragS
*current_fragP
;
7799 for (current_fragP
= fragP
;
7801 current_fragP
= current_fragP
->fr_next
)
7803 if (current_fragP
->tc_frag_data
.is_loop_target
7804 && current_fragP
!= current_target
)
7807 offset
+= unrelaxed_frag_min_size (current_fragP
);
7809 if (offset
>= max_size
)
7817 unrelaxed_frag_min_size (fragS
*fragP
)
7819 offsetT size
= fragP
->fr_fix
;
7821 /* Add fill size. */
7822 if (fragP
->fr_type
== rs_fill
)
7823 size
+= fragP
->fr_offset
;
7830 unrelaxed_frag_max_size (fragS
*fragP
)
7832 offsetT size
= fragP
->fr_fix
;
7833 switch (fragP
->fr_type
)
7836 /* Empty frags created by the obstack allocation scheme
7837 end up with type 0. */
7842 size
+= fragP
->fr_offset
;
7850 /* No further adjustments needed. */
7852 case rs_machine_dependent
:
7853 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7854 size
+= fragP
->fr_var
;
7857 /* We had darn well better know how big it is. */
7866 /* Re-process all of the fragments looking to convert all
7867 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7870 1) the instruction size count to the loop end label
7871 is too short (<= 2 instructions),
7872 2) loop has a jump or branch in it
7875 1) workaround_all_short_loops is TRUE
7876 2) The generating loop was a 'loopgtz' or 'loopnez'
7877 3) the instruction size count to the loop end label is too short
7879 then convert this frag (and maybe the next one) to generate a NOP.
7880 In any case close it off with a .fill 0. */
7882 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7883 static bfd_boolean
branch_before_loop_end (fragS
*);
7886 xtensa_fix_short_loop_frags (void)
7891 /* When this routine is called, all of the subsections are still intact
7892 so we walk over subsections instead of sections. */
7893 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7894 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7897 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7899 /* Walk over all of the fragments in a subsection. */
7900 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7902 if (fragP
->fr_type
== rs_machine_dependent
7903 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7904 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7907 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7908 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7909 current_opcode
= t_insn
.opcode
;
7910 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7911 current_opcode
) == 1);
7914 if (fragP
->fr_type
== rs_machine_dependent
7915 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7917 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7918 && (branch_before_loop_end (fragP
->fr_next
)
7919 || (workaround_all_short_loops
7920 && current_opcode
!= XTENSA_UNDEFINED
7921 && current_opcode
!= xtensa_loop_opcode
)))
7923 if (fragP
->tc_frag_data
.is_no_transform
)
7924 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7926 relax_frag_add_nop (fragP
);
7935 static int unrelaxed_frag_min_insn_count (fragS
*);
7938 count_insns_to_loop_end (fragS
*base_fragP
,
7939 bfd_boolean count_relax_add
,
7942 fragS
*fragP
= NULL
;
7947 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7949 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7950 if (insn_count
>= max_count
)
7953 if (count_relax_add
)
7955 if (fragP
->fr_type
== rs_machine_dependent
7956 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7958 /* In order to add the appropriate number of
7959 NOPs, we count an instruction for downstream
7962 if (insn_count
>= max_count
)
7972 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7974 xtensa_isa isa
= xtensa_default_isa
;
7975 static xtensa_insnbuf insnbuf
= NULL
;
7979 if (!fragP
->tc_frag_data
.is_insn
)
7983 insnbuf
= xtensa_insnbuf_alloc (isa
);
7985 /* Decode the fixed instructions. */
7986 while (offset
< fragP
->fr_fix
)
7990 xtensa_insnbuf_from_chars
7991 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7992 fmt
= xtensa_format_decode (isa
, insnbuf
);
7994 if (fmt
== XTENSA_UNDEFINED
)
7996 as_fatal (_("undecodable instruction in instruction frag"));
7999 offset
+= xtensa_format_length (isa
, fmt
);
8007 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8010 branch_before_loop_end (fragS
*base_fragP
)
8014 for (fragP
= base_fragP
;
8015 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8016 fragP
= fragP
->fr_next
)
8018 if (unrelaxed_frag_has_b_j (fragP
))
8026 unrelaxed_frag_has_b_j (fragS
*fragP
)
8028 static xtensa_insnbuf insnbuf
= NULL
;
8029 xtensa_isa isa
= xtensa_default_isa
;
8032 if (!fragP
->tc_frag_data
.is_insn
)
8036 insnbuf
= xtensa_insnbuf_alloc (isa
);
8038 /* Decode the fixed instructions. */
8039 while (offset
< fragP
->fr_fix
)
8044 xtensa_insnbuf_from_chars
8045 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8046 fmt
= xtensa_format_decode (isa
, insnbuf
);
8047 if (fmt
== XTENSA_UNDEFINED
)
8050 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8052 xtensa_opcode opcode
=
8053 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8054 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8055 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8058 offset
+= xtensa_format_length (isa
, fmt
);
8064 /* Checks to be made after initial assembly but before relaxation. */
8066 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8067 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8070 xtensa_sanity_check (void)
8077 as_where (&file_name
, &line
);
8078 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8079 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8083 /* Walk over all of the fragments in a subsection. */
8084 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8086 if (fragP
->fr_type
== rs_machine_dependent
8087 && fragP
->fr_subtype
== RELAX_SLOTS
8088 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8090 static xtensa_insnbuf insnbuf
= NULL
;
8093 if (fragP
->fr_opcode
!= NULL
)
8096 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8097 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8098 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8100 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8101 t_insn
.opcode
) == 1)
8103 if (is_empty_loop (&t_insn
, fragP
))
8105 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8106 as_bad (_("invalid empty loop"));
8108 if (!is_local_forward_loop (&t_insn
, fragP
))
8110 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8111 as_bad (_("loop target does not follow "
8112 "loop instruction in section"));
8119 new_logical_line (file_name
, line
);
8123 #define LOOP_IMMED_OPN 1
8125 /* Return TRUE if the loop target is the next non-zero fragment. */
8128 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8130 const expressionS
*exp
;
8134 if (insn
->insn_type
!= ITYPE_INSN
)
8137 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8140 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8143 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8145 if (exp
->X_op
!= O_symbol
)
8148 symbolP
= exp
->X_add_symbol
;
8152 if (symbol_get_frag (symbolP
) == NULL
)
8155 if (S_GET_VALUE (symbolP
) != 0)
8158 /* Walk through the zero-size fragments from this one. If we find
8159 the target fragment, then this is a zero-size loop. */
8161 for (next_fragP
= fragP
->fr_next
;
8163 next_fragP
= next_fragP
->fr_next
)
8165 if (next_fragP
== symbol_get_frag (symbolP
))
8167 if (next_fragP
->fr_fix
!= 0)
8175 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8177 const expressionS
*exp
;
8181 if (insn
->insn_type
!= ITYPE_INSN
)
8184 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8187 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8190 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8192 if (exp
->X_op
!= O_symbol
)
8195 symbolP
= exp
->X_add_symbol
;
8199 if (symbol_get_frag (symbolP
) == NULL
)
8202 /* Walk through fragments until we find the target.
8203 If we do not find the target, then this is an invalid loop. */
8205 for (next_fragP
= fragP
->fr_next
;
8207 next_fragP
= next_fragP
->fr_next
)
8209 if (next_fragP
== symbol_get_frag (symbolP
))
8217 #define XTINFO_NAME "Xtensa_Info"
8218 #define XTINFO_NAMESZ 12
8219 #define XTINFO_TYPE 1
8222 xtensa_add_config_info (void)
8228 info_sec
= subseg_new (".xtensa.info", 0);
8229 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8231 data
= xmalloc (100);
8232 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8233 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8234 sz
= strlen (data
) + 1;
8236 /* Add enough null terminators to pad to a word boundary. */
8239 while ((sz
& 3) != 0);
8241 /* Follow the standard note section layout:
8242 First write the length of the name string. */
8244 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8246 /* Next comes the length of the "descriptor", i.e., the actual data. */
8248 md_number_to_chars (p
, (valueT
) sz
, 4);
8250 /* Write the note type. */
8252 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8254 /* Write the name field. */
8255 p
= frag_more (XTINFO_NAMESZ
);
8256 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8258 /* Finally, write the descriptor. */
8260 memcpy (p
, data
, sz
);
8266 /* Alignment Functions. */
8269 get_text_align_power (unsigned target_size
)
8271 if (target_size
<= 4)
8274 if (target_size
<= 8)
8277 if (target_size
<= 16)
8280 if (target_size
<= 32)
8283 if (target_size
<= 64)
8286 if (target_size
<= 128)
8289 if (target_size
<= 256)
8292 if (target_size
<= 512)
8295 if (target_size
<= 1024)
8304 get_text_align_max_fill_size (int align_pow
,
8305 bfd_boolean use_nops
,
8306 bfd_boolean use_no_density
)
8309 return (1 << align_pow
);
8311 return 3 * (1 << align_pow
);
8313 return 1 + (1 << align_pow
);
8317 /* Calculate the minimum bytes of fill needed at "address" to align a
8318 target instruction of size "target_size" so that it does not cross a
8319 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8320 the fill can be an arbitrary number of bytes. Otherwise, the space must
8321 be filled by NOP instructions. */
8324 get_text_align_fill_size (addressT address
,
8327 bfd_boolean use_nops
,
8328 bfd_boolean use_no_density
)
8330 addressT alignment
, fill
, fill_limit
, fill_step
;
8331 bfd_boolean skip_one
= FALSE
;
8333 alignment
= (1 << align_pow
);
8334 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8338 fill_limit
= alignment
;
8341 else if (!use_no_density
)
8343 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8344 fill_limit
= alignment
* 2;
8350 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8351 fill_limit
= alignment
* 3;
8355 /* Try all fill sizes until finding one that works. */
8356 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8358 if (skip_one
&& fill
== 1)
8360 if ((address
+ fill
) >> align_pow
8361 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8370 branch_align_power (segT sec
)
8372 /* If the Xtensa processor has a fetch width of X, and
8373 the section is aligned to at least that boundary, then a branch
8374 target need only fit within that aligned block of memory to avoid
8375 a stall. Otherwise, try to fit branch targets within 4-byte
8376 aligned blocks (which may be insufficient, e.g., if the section
8377 has no alignment, but it's good enough). */
8378 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8379 int sec_align
= get_recorded_alignment (sec
);
8381 if (sec_align
>= fetch_align
)
8388 /* This will assert if it is not possible. */
8391 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8397 gas_assert (fill_size
% 3 == 0);
8398 return (fill_size
/ 3);
8401 gas_assert (fill_size
!= 1); /* Bad argument. */
8403 while (fill_size
> 1)
8406 if (fill_size
== 2 || fill_size
== 4)
8408 fill_size
-= insn_size
;
8411 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8417 get_text_align_nth_nop_size (offsetT fill_size
,
8419 bfd_boolean use_no_density
)
8426 gas_assert (fill_size
!= 1); /* Bad argument. */
8428 while (fill_size
> 1)
8431 if (fill_size
== 2 || fill_size
== 4)
8433 fill_size
-= insn_size
;
8443 /* For the given fragment, find the appropriate address
8444 for it to begin at if we are using NOPs to align it. */
8447 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8449 /* The rule is: get next fragment's FIRST instruction. Find
8450 the smallest number of bytes that need to be added to
8451 ensure that the next fragment's FIRST instruction will fit
8454 E.G., 2 bytes : 0, 1, 2 mod 4
8457 If the FIRST instruction MIGHT be relaxed,
8458 assume that it will become a 3-byte instruction.
8460 Note again here that LOOP instructions are not bundleable,
8461 and this relaxation only applies to LOOP opcodes. */
8464 int first_insn_size
;
8466 addressT pre_opcode_bytes
;
8469 xtensa_opcode opcode
;
8470 bfd_boolean is_loop
;
8472 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8473 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8475 /* Find the loop frag. */
8476 first_insn
= next_non_empty_frag (fragP
);
8477 /* Now find the first insn frag. */
8478 first_insn
= next_non_empty_frag (first_insn
);
8480 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8481 gas_assert (is_loop
);
8482 loop_insn_size
= xg_get_single_size (opcode
);
8484 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8485 pre_opcode_bytes
+= loop_insn_size
;
8487 /* For loops, the alignment depends on the size of the
8488 instruction following the loop, not the LOOP instruction. */
8490 if (first_insn
== NULL
)
8491 first_insn_size
= xtensa_fetch_width
;
8493 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8495 /* If it was 8, then we'll need a larger alignment for the section. */
8496 align_power
= get_text_align_power (first_insn_size
);
8497 record_alignment (now_seg
, align_power
);
8499 fill_size
= get_text_align_fill_size
8500 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8501 fragP
->tc_frag_data
.is_no_density
);
8503 return address
+ fill_size
;
8507 /* 3 mechanisms for relaxing an alignment:
8509 Align to a power of 2.
8510 Align so the next fragment's instruction does not cross a word boundary.
8511 Align the current instruction so that if the next instruction
8512 were 3 bytes, it would not cross a word boundary.
8516 zeros - This is easy; always insert zeros.
8517 nops - 3-byte and 2-byte instructions
8521 >=5 : 3-byte instruction + fn (n-3)
8522 widening - widen previous instructions. */
8525 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8527 addressT target_address
, loop_insn_offset
;
8529 xtensa_opcode loop_opcode
;
8530 bfd_boolean is_loop
;
8533 offsetT branch_align
;
8536 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8537 switch (fragP
->fr_subtype
)
8539 case RELAX_DESIRE_ALIGN
:
8540 target_size
= next_frag_format_size (fragP
);
8541 if (target_size
== XTENSA_UNDEFINED
)
8543 align_power
= branch_align_power (now_seg
);
8544 branch_align
= 1 << align_power
;
8545 /* Don't count on the section alignment being as large as the target. */
8546 if (target_size
> branch_align
)
8547 target_size
= branch_align
;
8548 opt_diff
= get_text_align_fill_size (address
, align_power
,
8549 target_size
, FALSE
, FALSE
);
8551 *max_diff
= (opt_diff
+ branch_align
8552 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8553 gas_assert (*max_diff
>= opt_diff
);
8556 case RELAX_ALIGN_NEXT_OPCODE
:
8557 /* The next non-empty frag after this one holds the LOOP instruction
8558 that needs to be aligned. The required alignment depends on the
8559 size of the next non-empty frag after the loop frag, i.e., the
8560 first instruction in the loop. */
8561 loop_frag
= next_non_empty_frag (fragP
);
8562 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8563 loop_insn_offset
= 0;
8564 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8565 gas_assert (is_loop
);
8567 /* If the loop has been expanded then the LOOP instruction
8568 could be at an offset from this fragment. */
8569 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8570 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8572 /* In an ideal world, which is what we are shooting for here,
8573 we wouldn't need to use any NOPs immediately prior to the
8574 LOOP instruction. If this approach fails, relax_frag_loop_align
8575 will call get_noop_aligned_address. */
8577 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8578 align_power
= get_text_align_power (target_size
);
8579 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8580 target_size
, FALSE
, FALSE
);
8582 *max_diff
= xtensa_fetch_width
8583 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8584 - target_size
+ opt_diff
;
8585 gas_assert (*max_diff
>= opt_diff
);
8596 /* md_relax_frag Hook and Helper Functions. */
8598 static long relax_frag_loop_align (fragS
*, long);
8599 static long relax_frag_for_align (fragS
*, long);
8600 static long relax_frag_immed
8601 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8604 /* Return the number of bytes added to this fragment, given that the
8605 input has been stretched already by "stretch". */
8608 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8610 xtensa_isa isa
= xtensa_default_isa
;
8611 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8612 long new_stretch
= 0;
8616 static xtensa_insnbuf vbuf
= NULL
;
8617 int slot
, num_slots
;
8620 as_where (&file_name
, &line
);
8621 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8623 fragP
->tc_frag_data
.unreported_expansion
= 0;
8625 switch (fragP
->fr_subtype
)
8627 case RELAX_ALIGN_NEXT_OPCODE
:
8628 /* Always convert. */
8629 if (fragP
->tc_frag_data
.relax_seen
)
8630 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8633 case RELAX_LOOP_END
:
8637 case RELAX_LOOP_END_ADD_NOP
:
8638 /* Add a NOP and switch to .fill 0. */
8639 new_stretch
= relax_frag_add_nop (fragP
);
8643 case RELAX_DESIRE_ALIGN
:
8644 /* Do nothing. The narrowing before this frag will either align
8649 case RELAX_LITERAL_FINAL
:
8652 case RELAX_LITERAL_NR
:
8654 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8655 gas_assert (unreported
== lit_size
);
8656 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8657 fragP
->fr_var
-= lit_size
;
8658 fragP
->fr_fix
+= lit_size
;
8664 vbuf
= xtensa_insnbuf_alloc (isa
);
8666 xtensa_insnbuf_from_chars
8667 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8668 fmt
= xtensa_format_decode (isa
, vbuf
);
8669 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8671 for (slot
= 0; slot
< num_slots
; slot
++)
8673 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8676 if (fragP
->tc_frag_data
.relax_seen
)
8677 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8681 case RELAX_IMMED_STEP1
:
8682 case RELAX_IMMED_STEP2
:
8683 case RELAX_IMMED_STEP3
:
8684 /* Place the immediate. */
8685 new_stretch
+= relax_frag_immed
8686 (now_seg
, fragP
, stretch
,
8687 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8688 fmt
, slot
, stretched_p
, FALSE
);
8692 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8698 case RELAX_LITERAL_POOL_BEGIN
:
8699 case RELAX_LITERAL_POOL_END
:
8700 case RELAX_MAYBE_UNREACHABLE
:
8701 case RELAX_MAYBE_DESIRE_ALIGN
:
8702 /* No relaxation required. */
8705 case RELAX_FILL_NOP
:
8706 case RELAX_UNREACHABLE
:
8707 if (fragP
->tc_frag_data
.relax_seen
)
8708 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8712 as_bad (_("bad relaxation state"));
8715 /* Tell gas we need another relaxation pass. */
8716 if (! fragP
->tc_frag_data
.relax_seen
)
8718 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8722 new_logical_line (file_name
, line
);
8728 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8730 addressT old_address
, old_next_address
, old_size
;
8731 addressT new_address
, new_next_address
, new_size
;
8734 /* All the frags with relax_frag_for_alignment prior to this one in the
8735 section have been done, hopefully eliminating the need for a NOP here.
8736 But, this will put it in if necessary. */
8738 /* Calculate the old address of this fragment and the next fragment. */
8739 old_address
= fragP
->fr_address
- stretch
;
8740 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8741 fragP
->tc_frag_data
.text_expansion
[0]);
8742 old_size
= old_next_address
- old_address
;
8744 /* Calculate the new address of this fragment and the next fragment. */
8745 new_address
= fragP
->fr_address
;
8747 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8748 new_size
= new_next_address
- new_address
;
8750 growth
= new_size
- old_size
;
8752 /* Fix up the text_expansion field and return the new growth. */
8753 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8758 /* Add a NOP instruction. */
8761 relax_frag_add_nop (fragS
*fragP
)
8763 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8764 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8765 assemble_nop (length
, nop_buf
);
8766 fragP
->tc_frag_data
.is_insn
= TRUE
;
8768 if (fragP
->fr_var
< length
)
8770 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8774 fragP
->fr_fix
+= length
;
8775 fragP
->fr_var
-= length
;
8780 static long future_alignment_required (fragS
*, long);
8783 relax_frag_for_align (fragS
*fragP
, long stretch
)
8785 /* Overview of the relaxation procedure for alignment:
8786 We can widen with NOPs or by widening instructions or by filling
8787 bytes after jump instructions. Find the opportune places and widen
8788 them if necessary. */
8793 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8794 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8795 || (fragP
->fr_subtype
== RELAX_SLOTS
8796 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8798 stretch_me
= future_alignment_required (fragP
, stretch
);
8799 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8805 /* We expanded on a previous pass. Can we shrink now? */
8806 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8807 if (shrink
<= stretch
&& stretch
> 0)
8809 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8815 /* Below here, diff > 0. */
8816 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8822 /* Return the address of the next frag that should be aligned.
8824 By "address" we mean the address it _would_ be at if there
8825 is no action taken to align it between here and the target frag.
8826 In other words, if no narrows and no fill nops are used between
8827 here and the frag to align, _even_if_ some of the frags we use
8828 to align targets have already expanded on a previous relaxation
8831 Also, count each frag that may be used to help align the target.
8833 Return 0 if there are no frags left in the chain that need to be
8837 find_address_of_next_align_frag (fragS
**fragPP
,
8841 bfd_boolean
*paddable
)
8843 fragS
*fragP
= *fragPP
;
8844 addressT address
= fragP
->fr_address
;
8846 /* Do not reset the counts to 0. */
8850 /* Limit this to a small search. */
8851 if (*widens
>= (int) xtensa_fetch_width
)
8856 address
+= fragP
->fr_fix
;
8858 if (fragP
->fr_type
== rs_fill
)
8859 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8860 else if (fragP
->fr_type
== rs_machine_dependent
)
8862 switch (fragP
->fr_subtype
)
8864 case RELAX_UNREACHABLE
:
8868 case RELAX_FILL_NOP
:
8870 if (!fragP
->tc_frag_data
.is_no_density
)
8875 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8880 address
+= total_frag_text_expansion (fragP
);
8884 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8887 case RELAX_ALIGN_NEXT_OPCODE
:
8888 case RELAX_DESIRE_ALIGN
:
8892 case RELAX_MAYBE_UNREACHABLE
:
8893 case RELAX_MAYBE_DESIRE_ALIGN
:
8898 /* Just punt if we don't know the type. */
8905 /* Just punt if we don't know the type. */
8909 fragP
= fragP
->fr_next
;
8917 static long bytes_to_stretch (fragS
*, int, int, int, int);
8920 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8922 fragS
*this_frag
= fragP
;
8926 int narrow_nops
= 0;
8927 bfd_boolean paddable
= FALSE
;
8928 offsetT local_opt_diff
;
8931 int stretch_amount
= 0;
8932 int local_stretch_amount
;
8933 int global_stretch_amount
;
8935 address
= find_address_of_next_align_frag
8936 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8940 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8941 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8943 frag_wane (this_frag
);
8947 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8948 opt_diff
= local_opt_diff
;
8949 gas_assert (opt_diff
>= 0);
8950 gas_assert (max_diff
>= opt_diff
);
8955 fragP
= fragP
->fr_next
;
8957 while (fragP
&& opt_diff
< max_diff
&& address
)
8959 /* We only use these to determine if we can exit early
8960 because there will be plenty of ways to align future
8962 int glob_widens
= 0;
8965 bfd_boolean glob_pad
= 0;
8966 address
= find_address_of_next_align_frag
8967 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8968 /* If there is a padable portion, then skip. */
8969 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8974 offsetT next_m_diff
;
8975 offsetT next_o_diff
;
8977 /* Downrange frags haven't had stretch added to them yet. */
8980 /* The address also includes any text expansion from this
8981 frag in a previous pass, but we don't want that. */
8982 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8984 /* Assume we are going to move at least opt_diff. In
8985 reality, we might not be able to, but assuming that
8986 we will helps catch cases where moving opt_diff pushes
8987 the next target from aligned to unaligned. */
8988 address
+= opt_diff
;
8990 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8992 /* Now cleanup for the adjustments to address. */
8993 next_o_diff
+= opt_diff
;
8994 next_m_diff
+= opt_diff
;
8995 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8996 opt_diff
= next_o_diff
;
8997 if (next_m_diff
< max_diff
)
8998 max_diff
= next_m_diff
;
8999 fragP
= fragP
->fr_next
;
9003 /* If there are enough wideners in between, do it. */
9006 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9008 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9013 local_stretch_amount
9014 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9015 num_widens
, local_opt_diff
);
9016 global_stretch_amount
9017 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9018 num_widens
, opt_diff
);
9019 /* If the condition below is true, then the frag couldn't
9020 stretch the correct amount for the global case, so we just
9021 optimize locally. We'll rely on the subsequent frags to get
9022 the correct alignment in the global case. */
9023 if (global_stretch_amount
< local_stretch_amount
)
9024 stretch_amount
= local_stretch_amount
;
9026 stretch_amount
= global_stretch_amount
;
9028 if (this_frag
->fr_subtype
== RELAX_SLOTS
9029 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9030 gas_assert (stretch_amount
<= 1);
9031 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9033 if (this_frag
->tc_frag_data
.is_no_density
)
9034 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9036 gas_assert (stretch_amount
<= 3);
9039 return stretch_amount
;
9043 /* The idea: widen everything you can to get a target or loop aligned,
9044 then start using NOPs.
9046 wide_nops = the number of wide NOPs available for aligning
9047 narrow_nops = the number of narrow NOPs available for aligning
9048 (a subset of wide_nops)
9049 widens = the number of narrow instructions that should be widened
9054 bytes_to_stretch (fragS
*this_frag
,
9063 int bytes_short
= desired_diff
- num_widens
;
9065 gas_assert (desired_diff
>= 0
9066 && desired_diff
< (signed) xtensa_fetch_width
);
9067 if (desired_diff
== 0)
9070 gas_assert (wide_nops
> 0 || num_widens
> 0);
9072 /* Always prefer widening to NOP-filling. */
9073 if (bytes_short
< 0)
9075 /* There are enough RELAX_NARROW frags after this one
9076 to align the target without widening this frag in any way. */
9080 if (bytes_short
== 0)
9082 /* Widen every narrow between here and the align target
9083 and the align target will be properly aligned. */
9084 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9090 /* From here we will need at least one NOP to get an alignment.
9091 However, we may not be able to align at all, in which case,
9093 nops_needed
= desired_diff
/ 3;
9095 /* If there aren't enough nops, don't widen. */
9096 if (nops_needed
> wide_nops
)
9099 /* First try it with all wide nops. */
9100 nop_bytes
= nops_needed
* 3;
9101 extra_bytes
= desired_diff
- nop_bytes
;
9103 if (nop_bytes
+ num_widens
>= desired_diff
)
9105 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9107 else if (num_widens
== extra_bytes
)
9112 /* Add a narrow nop. */
9116 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9119 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9121 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9122 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9123 else if (num_widens
== extra_bytes
)
9128 /* Replace a wide nop with a narrow nop--we can get here if
9129 extra_bytes was negative in the previous conditional. */
9130 if (narrow_nops
== 1)
9134 if (nop_bytes
+ num_widens
>= desired_diff
)
9136 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9137 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9138 else if (num_widens
== extra_bytes
)
9143 /* If we can't satisfy any of the above cases, then we can't align
9144 using padding or fill nops. */
9150 relax_frag_immed (segT segP
,
9157 bfd_boolean estimate_only
)
9161 bfd_boolean negatable_branch
= FALSE
;
9162 bfd_boolean branch_jmp_to_next
= FALSE
;
9163 bfd_boolean from_wide_insn
= FALSE
;
9164 xtensa_isa isa
= xtensa_default_isa
;
9166 offsetT frag_offset
;
9168 int num_text_bytes
, num_literal_bytes
;
9169 int literal_diff
, total_text_diff
, this_text_diff
;
9171 gas_assert (fragP
->fr_opcode
!= NULL
);
9173 xg_clear_vinsn (&cur_vinsn
);
9174 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9175 if (cur_vinsn
.num_slots
> 1)
9176 from_wide_insn
= TRUE
;
9178 tinsn
= cur_vinsn
.slots
[slot
];
9179 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9181 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9184 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9185 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9187 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9189 old_size
= xtensa_format_length (isa
, fmt
);
9191 /* Special case: replace a branch to the next instruction with a NOP.
9192 This is required to work around a hardware bug in T1040.0 and also
9193 serves as an optimization. */
9195 if (branch_jmp_to_next
9196 && ((old_size
== 2) || (old_size
== 3))
9197 && !next_frag_is_loop_target (fragP
))
9200 /* Here is the fun stuff: Get the immediate field from this
9201 instruction. If it fits, we are done. If not, find the next
9202 instruction sequence that fits. */
9204 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9205 istack_init (&istack
);
9206 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9207 min_steps
, stretch
);
9208 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9210 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9212 /* Figure out the number of bytes needed. */
9213 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9215 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9216 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9221 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9224 num_text_bytes
+= old_size
;
9225 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9226 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9229 /* The first instruction in the relaxed sequence will go after
9230 the current wide instruction, and thus its symbolic immediates
9233 istack_init (&istack
);
9234 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
9235 frag_offset
+ old_size
,
9236 min_steps
, stretch
+ old_size
);
9237 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9239 fragP
->tc_frag_data
.slot_subtypes
[slot
]
9240 = (int) RELAX_IMMED
+ num_steps
;
9242 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9244 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9246 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
9250 total_text_diff
= num_text_bytes
- old_size
;
9251 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9253 /* It MUST get larger. If not, we could get an infinite loop. */
9254 gas_assert (num_text_bytes
>= 0);
9255 gas_assert (literal_diff
>= 0);
9256 gas_assert (total_text_diff
>= 0);
9258 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9259 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9260 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9261 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9263 /* Find the associated expandable literal for this. */
9264 if (literal_diff
!= 0)
9266 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9269 gas_assert (literal_diff
== 4);
9270 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9272 /* We expect that the literal section state has NOT been
9274 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
9275 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9276 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9278 /* We need to mark this section for another iteration
9284 if (negatable_branch
&& istack
.ninsn
> 1)
9285 update_next_frag_state (fragP
);
9287 return this_text_diff
;
9291 /* md_convert_frag Hook and Helper Functions. */
9293 static void convert_frag_align_next_opcode (fragS
*);
9294 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9295 static void convert_frag_fill_nop (fragS
*);
9296 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9299 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9301 static xtensa_insnbuf vbuf
= NULL
;
9302 xtensa_isa isa
= xtensa_default_isa
;
9309 as_where (&file_name
, &line
);
9310 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9312 switch (fragp
->fr_subtype
)
9314 case RELAX_ALIGN_NEXT_OPCODE
:
9315 /* Always convert. */
9316 convert_frag_align_next_opcode (fragp
);
9319 case RELAX_DESIRE_ALIGN
:
9320 /* Do nothing. If not aligned already, too bad. */
9324 case RELAX_LITERAL_FINAL
:
9329 vbuf
= xtensa_insnbuf_alloc (isa
);
9331 xtensa_insnbuf_from_chars
9332 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9333 fmt
= xtensa_format_decode (isa
, vbuf
);
9334 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9336 for (slot
= 0; slot
< num_slots
; slot
++)
9338 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9341 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9345 case RELAX_IMMED_STEP1
:
9346 case RELAX_IMMED_STEP2
:
9347 case RELAX_IMMED_STEP3
:
9348 /* Place the immediate. */
9351 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9356 /* This is OK because some slots could have
9357 relaxations and others have none. */
9363 case RELAX_UNREACHABLE
:
9364 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9365 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9366 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9370 case RELAX_MAYBE_UNREACHABLE
:
9371 case RELAX_MAYBE_DESIRE_ALIGN
:
9375 case RELAX_FILL_NOP
:
9376 convert_frag_fill_nop (fragp
);
9379 case RELAX_LITERAL_NR
:
9380 if (use_literal_section
)
9382 /* This should have been handled during relaxation. When
9383 relaxing a code segment, literals sometimes need to be
9384 added to the corresponding literal segment. If that
9385 literal segment has already been relaxed, then we end up
9386 in this situation. Marking the literal segments as data
9387 would make this happen less often (since GAS always relaxes
9388 code before data), but we could still get into trouble if
9389 there are instructions in a segment that is not marked as
9390 containing code. Until we can implement a better solution,
9391 cheat and adjust the addresses of all the following frags.
9392 This could break subsequent alignments, but the linker's
9393 literal coalescing will do that anyway. */
9396 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9397 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9398 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9401 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9405 as_bad (_("invalid relaxation fragment result"));
9410 new_logical_line (file_name
, line
);
9415 convert_frag_align_next_opcode (fragS
*fragp
)
9417 char *nop_buf
; /* Location for Writing. */
9418 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9419 addressT aligned_address
;
9423 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9425 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9426 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9427 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9429 for (nop
= 0; nop
< nop_count
; nop
++)
9432 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9434 assemble_nop (nop_size
, nop_buf
);
9435 nop_buf
+= nop_size
;
9438 fragp
->fr_fix
+= fill_size
;
9439 fragp
->fr_var
-= fill_size
;
9444 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9446 TInsn tinsn
, single_target
;
9447 int size
, old_size
, diff
;
9448 offsetT frag_offset
;
9450 gas_assert (slot
== 0);
9451 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9453 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9455 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9456 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9457 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9462 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9464 /* No conversion. */
9469 gas_assert (fragP
->fr_opcode
!= NULL
);
9471 /* Frags in this relaxation state should only contain
9472 single instruction bundles. */
9473 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9475 /* Just convert it to a wide form.... */
9477 old_size
= xg_get_single_size (tinsn
.opcode
);
9479 tinsn_init (&single_target
);
9480 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9482 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9484 as_bad (_("unable to widen instruction"));
9488 size
= xg_get_single_size (single_target
.opcode
);
9489 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9492 diff
= size
- old_size
;
9493 gas_assert (diff
>= 0);
9494 gas_assert (diff
<= fragP
->fr_var
);
9495 fragP
->fr_var
-= diff
;
9496 fragP
->fr_fix
+= diff
;
9504 convert_frag_fill_nop (fragS
*fragP
)
9506 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9507 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9508 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9509 - fragP
->fr_address
- fragP
->fr_fix
));
9512 /* No conversion. */
9516 assemble_nop (size
, loc
);
9517 fragP
->tc_frag_data
.is_insn
= TRUE
;
9518 fragP
->fr_var
-= size
;
9519 fragP
->fr_fix
+= size
;
9524 static fixS
*fix_new_exp_in_seg
9525 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9526 bfd_reloc_code_real_type
);
9527 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9530 convert_frag_immed (segT segP
,
9536 char *immed_instr
= fragP
->fr_opcode
;
9538 bfd_boolean expanded
= FALSE
;
9539 bfd_boolean branch_jmp_to_next
= FALSE
;
9540 char *fr_opcode
= fragP
->fr_opcode
;
9541 xtensa_isa isa
= xtensa_default_isa
;
9542 bfd_boolean from_wide_insn
= FALSE
;
9544 bfd_boolean is_loop
;
9546 gas_assert (fr_opcode
!= NULL
);
9548 xg_clear_vinsn (&cur_vinsn
);
9550 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9551 if (cur_vinsn
.num_slots
> 1)
9552 from_wide_insn
= TRUE
;
9554 orig_tinsn
= cur_vinsn
.slots
[slot
];
9555 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9557 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9559 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9560 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9562 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9564 /* Conversion just inserts a NOP and marks the fix as completed. */
9565 bytes
= xtensa_format_length (isa
, fmt
);
9568 cur_vinsn
.slots
[slot
].opcode
=
9569 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9570 cur_vinsn
.slots
[slot
].ntok
= 0;
9574 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9575 gas_assert (bytes
== 2 || bytes
== 3);
9576 build_nop (&cur_vinsn
.slots
[0], bytes
);
9577 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9579 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9580 xtensa_insnbuf_to_chars
9581 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9586 /* Here is the fun stuff: Get the immediate field from this
9587 instruction. If it fits, we're done. If not, find the next
9588 instruction sequence that fits. */
9592 symbolS
*lit_sym
= NULL
;
9594 int target_offset
= 0;
9597 symbolS
*gen_label
= NULL
;
9598 offsetT frag_offset
;
9599 bfd_boolean first
= TRUE
;
9601 /* It does not fit. Find something that does and
9602 convert immediately. */
9603 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9604 istack_init (&istack
);
9605 xg_assembly_relax (&istack
, &orig_tinsn
,
9606 segP
, fragP
, frag_offset
, min_steps
, 0);
9608 old_size
= xtensa_format_length (isa
, fmt
);
9610 /* Assemble this right inline. */
9612 /* First, create the mapping from a label name to the REAL label. */
9614 for (i
= 0; i
< istack
.ninsn
; i
++)
9616 TInsn
*tinsn
= &istack
.insn
[i
];
9619 switch (tinsn
->insn_type
)
9622 if (lit_sym
!= NULL
)
9623 as_bad (_("multiple literals in expansion"));
9624 /* First find the appropriate space in the literal pool. */
9625 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9626 if (lit_frag
== NULL
)
9627 as_bad (_("no registered fragment for literal"));
9628 if (tinsn
->ntok
!= 1)
9629 as_bad (_("number of literal tokens != 1"));
9631 /* Set the literal symbol and add a fixup. */
9632 lit_sym
= lit_frag
->fr_symbol
;
9636 if (align_targets
&& !is_loop
)
9638 fragS
*unreach
= fragP
->fr_next
;
9639 while (!(unreach
->fr_type
== rs_machine_dependent
9640 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9641 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9643 unreach
= unreach
->fr_next
;
9646 gas_assert (unreach
->fr_type
== rs_machine_dependent
9647 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9648 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9650 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9652 gas_assert (gen_label
== NULL
);
9653 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9654 fr_opcode
- fragP
->fr_literal
9655 + target_offset
, fragP
);
9659 if (first
&& from_wide_insn
)
9661 target_offset
+= xtensa_format_length (isa
, fmt
);
9663 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9664 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9667 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9674 for (i
= 0; i
< istack
.ninsn
; i
++)
9676 TInsn
*tinsn
= &istack
.insn
[i
];
9680 bfd_reloc_code_real_type reloc_type
;
9682 switch (tinsn
->insn_type
)
9685 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9686 /* Already checked. */
9687 gas_assert (lit_frag
!= NULL
);
9688 gas_assert (lit_sym
!= NULL
);
9689 gas_assert (tinsn
->ntok
== 1);
9691 target_seg
= S_GET_SEGMENT (lit_sym
);
9692 gas_assert (target_seg
);
9693 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
9694 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9695 &tinsn
->tok
[0], FALSE
, reloc_type
);
9702 xg_resolve_labels (tinsn
, gen_label
);
9703 xg_resolve_literals (tinsn
, lit_sym
);
9704 if (from_wide_insn
&& first
)
9707 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9709 cur_vinsn
.slots
[slot
] = *tinsn
;
9713 cur_vinsn
.slots
[slot
].opcode
=
9714 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9715 cur_vinsn
.slots
[slot
].ntok
= 0;
9717 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9718 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9719 (unsigned char *) immed_instr
, 0);
9720 fragP
->tc_frag_data
.is_insn
= TRUE
;
9721 size
= xtensa_format_length (isa
, fmt
);
9722 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9725 (tinsn
, immed_instr
+ size
, fragP
,
9726 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9727 size
+= xg_get_single_size (tinsn
->opcode
);
9732 size
= xg_get_single_size (tinsn
->opcode
);
9733 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9734 immed_instr
- fragP
->fr_literal
, TRUE
);
9736 immed_instr
+= size
;
9742 diff
= total_size
- old_size
;
9743 gas_assert (diff
>= 0);
9746 gas_assert (diff
<= fragP
->fr_var
);
9747 fragP
->fr_var
-= diff
;
9748 fragP
->fr_fix
+= diff
;
9751 /* Check for undefined immediates in LOOP instructions. */
9755 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9756 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9758 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9761 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9762 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9764 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9769 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9770 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9772 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9774 /* Add an expansion note on the expanded instruction. */
9775 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9776 &orig_tinsn
.tok
[0], TRUE
,
9777 BFD_RELOC_XTENSA_ASM_EXPAND
);
9782 /* Add a new fix expression into the desired segment. We have to
9783 switch to that segment to do this. */
9786 fix_new_exp_in_seg (segT new_seg
,
9793 bfd_reloc_code_real_type r_type
)
9797 subsegT subseg
= now_subseg
;
9799 gas_assert (new_seg
!= 0);
9800 subseg_set (new_seg
, new_subseg
);
9802 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9803 subseg_set (seg
, subseg
);
9808 /* Relax a loop instruction so that it can span loop >256 bytes.
9814 addi as, as, lo8 (label-.L1)
9815 addmi as, as, mid8 (label-.L1)
9826 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9831 unsigned long target
;
9832 static xtensa_insnbuf insnbuf
= NULL
;
9833 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9834 xtensa_isa isa
= xtensa_default_isa
;
9835 addressT loop_offset
;
9836 addressT addi_offset
= 9;
9837 addressT addmi_offset
= 12;
9842 insnbuf
= xtensa_insnbuf_alloc (isa
);
9844 /* Get the loop offset. */
9845 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9847 /* Validate that there really is a LOOP at the loop_offset. Because
9848 loops are not bundleable, we can assume that the instruction will be
9850 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9851 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9853 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9854 addi_offset
+= loop_offset
;
9855 addmi_offset
+= loop_offset
;
9857 gas_assert (tinsn
->ntok
== 2);
9858 if (tinsn
->tok
[1].X_op
== O_constant
)
9859 target
= tinsn
->tok
[1].X_add_number
;
9860 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9862 /* Find the fragment. */
9863 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9864 gas_assert (S_GET_SEGMENT (sym
) == segP
9865 || S_GET_SEGMENT (sym
) == absolute_section
);
9866 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9870 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9874 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9875 loop_length_hi
= loop_length
& ~0x0ff;
9876 loop_length_lo
= loop_length
& 0x0ff;
9877 if (loop_length_lo
>= 128)
9879 loop_length_lo
-= 256;
9880 loop_length_hi
+= 256;
9883 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9884 32512. If the loop is larger than that, then we just fail. */
9885 if (loop_length_hi
> 32512)
9886 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9887 _("loop too long for LOOP instruction"));
9889 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9890 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9892 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9893 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9895 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9896 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9898 fragP
->tc_frag_data
.is_insn
= TRUE
;
9899 xtensa_insnbuf_to_chars
9900 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9902 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9903 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9904 xtensa_insnbuf_to_chars
9905 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9907 /* Walk through all of the frags from here to the loop end
9908 and mark them as no_transform to keep them from being modified
9909 by the linker. If we ever have a relocation for the
9910 addi/addmi of the difference of two symbols we can remove this. */
9913 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9914 next_fragP
= next_fragP
->fr_next
)
9916 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9917 if (next_fragP
->tc_frag_data
.is_loop_target
)
9919 if (target_count
== 2)
9925 /* A map that keeps information on a per-subsegment basis. This is
9926 maintained during initial assembly, but is invalid once the
9927 subsegments are smashed together. I.E., it cannot be used during
9930 typedef struct subseg_map_struct
9938 float total_freq
; /* fall-through + branch target frequency */
9939 float target_freq
; /* branch target frequency alone */
9941 struct subseg_map_struct
*next
;
9945 static subseg_map
*sseg_map
= NULL
;
9948 get_subseg_info (segT seg
, subsegT subseg
)
9950 subseg_map
*subseg_e
;
9952 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9954 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9962 add_subseg_info (segT seg
, subsegT subseg
)
9964 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9965 memset (subseg_e
, 0, sizeof (subseg_map
));
9966 subseg_e
->seg
= seg
;
9967 subseg_e
->subseg
= subseg
;
9968 subseg_e
->flags
= 0;
9969 /* Start off considering every branch target very important. */
9970 subseg_e
->target_freq
= 1.0;
9971 subseg_e
->total_freq
= 1.0;
9972 subseg_e
->next
= sseg_map
;
9973 sseg_map
= subseg_e
;
9979 get_last_insn_flags (segT seg
, subsegT subseg
)
9981 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9983 return subseg_e
->flags
;
9989 set_last_insn_flags (segT seg
,
9994 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9996 subseg_e
= add_subseg_info (seg
, subseg
);
9998 subseg_e
->flags
|= fl
;
10000 subseg_e
->flags
&= ~fl
;
10005 get_subseg_total_freq (segT seg
, subsegT subseg
)
10007 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10009 return subseg_e
->total_freq
;
10015 get_subseg_target_freq (segT seg
, subsegT subseg
)
10017 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10019 return subseg_e
->target_freq
;
10025 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
10027 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10029 subseg_e
= add_subseg_info (seg
, subseg
);
10030 subseg_e
->total_freq
= total_f
;
10031 subseg_e
->target_freq
= target_f
;
10035 /* Segment Lists and emit_state Stuff. */
10038 xtensa_move_seg_list_to_beginning (seg_list
*head
)
10043 segT literal_section
= head
->seg
;
10045 /* Move the literal section to the front of the section list. */
10046 gas_assert (literal_section
);
10047 if (literal_section
!= stdoutput
->sections
)
10049 bfd_section_list_remove (stdoutput
, literal_section
);
10050 bfd_section_list_prepend (stdoutput
, literal_section
);
10057 static void mark_literal_frags (seg_list
*);
10060 xtensa_move_literals (void)
10063 frchainS
*frchain_from
, *frchain_to
;
10064 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
10065 fragS
**frag_splice
;
10068 fixS
*fix
, *next_fix
, **fix_splice
;
10071 mark_literal_frags (literal_head
->next
);
10073 if (use_literal_section
)
10076 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
10078 /* Keep the literals for .init and .fini in separate sections. */
10079 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
10080 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
10083 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10084 search_frag
= frchain_from
->frch_root
;
10085 literal_pool
= NULL
;
10087 frag_splice
= &(frchain_from
->frch_root
);
10089 while (!search_frag
->tc_frag_data
.literal_frag
)
10091 gas_assert (search_frag
->fr_fix
== 0
10092 || search_frag
->fr_type
== rs_align
);
10093 search_frag
= search_frag
->fr_next
;
10096 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10097 == RELAX_LITERAL_POOL_BEGIN
);
10098 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10100 /* Make sure that all the frags in this series are closed, and
10101 that there is at least one left over of zero-size. This
10102 prevents us from making a segment with an frchain without any
10104 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10105 xtensa_set_frag_assembly_state (frag_now
);
10106 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10107 xtensa_set_frag_assembly_state (frag_now
);
10109 while (search_frag
!= frag_now
)
10111 next_frag
= search_frag
->fr_next
;
10113 /* First, move the frag out of the literal section and
10114 to the appropriate place. */
10115 if (search_frag
->tc_frag_data
.literal_frag
)
10117 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10118 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10119 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
10120 gas_assert (frchain_to
);
10122 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
10123 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
10125 *frag_splice
= next_frag
;
10126 search_frag
->fr_next
= insert_after
->fr_next
;
10127 insert_after
->fr_next
= search_frag
;
10128 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10129 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
10131 /* Now move any fixups associated with this frag to the
10133 fix
= frchain_from
->fix_root
;
10134 fix_splice
= &(frchain_from
->fix_root
);
10137 next_fix
= fix
->fx_next
;
10138 if (fix
->fx_frag
== search_frag
)
10140 *fix_splice
= next_fix
;
10141 fix
->fx_next
= frchain_to
->fix_root
;
10142 frchain_to
->fix_root
= fix
;
10143 if (frchain_to
->fix_tail
== NULL
)
10144 frchain_to
->fix_tail
= fix
;
10147 fix_splice
= &(fix
->fx_next
);
10150 search_frag
= next_frag
;
10153 if (frchain_from
->fix_root
!= NULL
)
10155 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10156 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10158 gas_assert (frchain_from
->fix_root
== NULL
);
10160 frchain_from
->fix_tail
= NULL
;
10161 xtensa_restore_emit_state (&state
);
10164 /* Now fix up the SEGMENT value for all the literal symbols. */
10165 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10167 symbolS
*lit_sym
= lit
->sym
;
10168 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10170 S_SET_SEGMENT (lit_sym
, dseg
);
10175 /* Walk over all the frags for segments in a list and mark them as
10176 containing literals. As clunky as this is, we can't rely on frag_var
10177 and frag_variant to get called in all situations. */
10180 mark_literal_frags (seg_list
*segment
)
10182 frchainS
*frchain_from
;
10183 fragS
*search_frag
;
10187 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10188 search_frag
= frchain_from
->frch_root
;
10189 while (search_frag
)
10191 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10192 search_frag
= search_frag
->fr_next
;
10194 segment
= segment
->next
;
10200 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10202 /* Move all of the sections in the section list to come
10203 after "after" in the gnu segment list. */
10208 segT literal_section
= head
->seg
;
10210 /* Move the literal section after "after". */
10211 gas_assert (literal_section
);
10212 if (literal_section
!= after
)
10214 bfd_section_list_remove (stdoutput
, literal_section
);
10215 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10223 /* Push all the literal segments to the end of the gnu list. */
10226 xtensa_reorder_segments (void)
10233 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10239 /* Now that we have the last section, push all the literal
10240 sections to the end. */
10241 xtensa_reorder_seg_list (literal_head
, last_sec
);
10243 /* Now perform the final error check. */
10244 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10246 gas_assert (new_count
== old_count
);
10250 /* Change the emit state (seg, subseg, and frag related stuff) to the
10251 correct location. Return a emit_state which can be passed to
10252 xtensa_restore_emit_state to return to current fragment. */
10255 xtensa_switch_to_literal_fragment (emit_state
*result
)
10257 if (directive_state
[directive_absolute_literals
])
10259 segT lit4_seg
= cache_literal_section (TRUE
);
10260 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10263 xtensa_switch_to_non_abs_literal_fragment (result
);
10265 /* Do a 4-byte align here. */
10266 frag_align (2, 0, 0);
10267 record_alignment (now_seg
, 2);
10272 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10274 static bfd_boolean recursive
= FALSE
;
10275 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10277 bfd_boolean is_init
=
10278 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10279 bfd_boolean is_fini
=
10280 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10282 if (pool_location
== NULL
10283 && !use_literal_section
10285 && !is_init
&& ! is_fini
)
10287 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10289 /* When we mark a literal pool location, we want to put a frag in
10290 the literal pool that points to it. But to do that, we want to
10291 switch_to_literal_fragment. But literal sections don't have
10292 literal pools, so their location is always null, so we would
10293 recurse forever. This is kind of hacky, but it works. */
10296 xtensa_mark_literal_pool_location ();
10300 lit_seg
= cache_literal_section (FALSE
);
10301 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10303 if (!use_literal_section
10304 && !is_init
&& !is_fini
10305 && get_literal_pool_location (now_seg
) != pool_location
)
10307 /* Close whatever frag is there. */
10308 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10309 xtensa_set_frag_assembly_state (frag_now
);
10310 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10311 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10312 xtensa_set_frag_assembly_state (frag_now
);
10317 /* Call this function before emitting data into the literal section.
10318 This is a helper function for xtensa_switch_to_literal_fragment.
10319 This is similar to a .section new_now_seg subseg. */
10322 xtensa_switch_section_emit_state (emit_state
*state
,
10324 subsegT new_now_subseg
)
10326 state
->name
= now_seg
->name
;
10327 state
->now_seg
= now_seg
;
10328 state
->now_subseg
= now_subseg
;
10329 state
->generating_literals
= generating_literals
;
10330 generating_literals
++;
10331 subseg_set (new_now_seg
, new_now_subseg
);
10335 /* Use to restore the emitting into the normal place. */
10338 xtensa_restore_emit_state (emit_state
*state
)
10340 generating_literals
= state
->generating_literals
;
10341 subseg_set (state
->now_seg
, state
->now_subseg
);
10345 /* Predicate function used to look up a section in a particular group. */
10348 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10350 const char *gname
= inf
;
10351 const char *group_name
= elf_group_name (sec
);
10353 return (group_name
== gname
10354 || (group_name
!= NULL
10356 && strcmp (group_name
, gname
) == 0));
10360 /* Get the literal section to be used for the current text section.
10361 The result may be cached in the default_lit_sections structure. */
10364 cache_literal_section (bfd_boolean use_abs_literals
)
10366 const char *text_name
, *group_name
= 0;
10367 char *base_name
, *name
, *suffix
;
10369 segT seg
, current_section
;
10370 int current_subsec
;
10371 bfd_boolean linkonce
= FALSE
;
10373 /* Save the current section/subsection. */
10374 current_section
= now_seg
;
10375 current_subsec
= now_subseg
;
10377 /* Clear the cached values if they are no longer valid. */
10378 if (now_seg
!= default_lit_sections
.current_text_seg
)
10380 default_lit_sections
.current_text_seg
= now_seg
;
10381 default_lit_sections
.lit_seg
= NULL
;
10382 default_lit_sections
.lit4_seg
= NULL
;
10385 /* Check if the literal section is already cached. */
10386 if (use_abs_literals
)
10387 pcached
= &default_lit_sections
.lit4_seg
;
10389 pcached
= &default_lit_sections
.lit_seg
;
10394 text_name
= default_lit_sections
.lit_prefix
;
10395 if (! text_name
|| ! *text_name
)
10397 text_name
= segment_name (current_section
);
10398 group_name
= elf_group_name (current_section
);
10399 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10402 base_name
= use_abs_literals
? ".lit4" : ".literal";
10405 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10406 sprintf (name
, "%s.%s", base_name
, group_name
);
10408 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10410 suffix
= strchr (text_name
+ linkonce_len
, '.');
10412 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10413 + (suffix
? strlen (suffix
) : 0));
10414 strcpy (name
, ".gnu.linkonce");
10415 strcat (name
, base_name
);
10417 strcat (name
, suffix
);
10422 /* If the section name begins or ends with ".text", then replace
10423 that portion instead of appending an additional suffix. */
10424 size_t len
= strlen (text_name
);
10426 && (strcmp (text_name
+ len
- 5, ".text") == 0
10427 || strncmp (text_name
, ".text", 5) == 0))
10430 name
= xmalloc (len
+ strlen (base_name
) + 1);
10431 if (strncmp (text_name
, ".text", 5) == 0)
10433 strcpy (name
, base_name
);
10434 strcat (name
, text_name
+ 5);
10438 strcpy (name
, text_name
);
10439 strcpy (name
+ len
, base_name
);
10443 /* Canonicalize section names to allow renaming literal sections.
10444 The group name, if any, came from the current text section and
10445 has already been canonicalized. */
10446 name
= tc_canonicalize_symbol_name (name
);
10448 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10449 (void *) group_name
);
10454 seg
= subseg_force_new (name
, 0);
10456 if (! use_abs_literals
)
10458 /* Add the newly created literal segment to the list. */
10459 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10461 n
->next
= literal_head
->next
;
10462 literal_head
->next
= n
;
10465 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10466 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10467 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10469 elf_group_name (seg
) = group_name
;
10471 bfd_set_section_flags (stdoutput
, seg
, flags
);
10472 bfd_set_section_alignment (stdoutput
, seg
, 2);
10476 subseg_set (current_section
, current_subsec
);
10481 /* Property Tables Stuff. */
10483 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10484 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10485 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10487 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10488 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10490 static bfd_boolean
get_frag_is_literal (const fragS
*);
10491 static void xtensa_create_property_segments
10492 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10493 static void xtensa_create_xproperty_segments
10494 (frag_flags_fn
, const char *, xt_section_type
);
10495 static bfd_boolean
exclude_section_from_property_tables (segT
);
10496 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10497 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10498 static void add_xt_block_frags
10499 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10500 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10501 static void xtensa_frag_flags_init (frag_flags
*);
10502 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10503 static flagword
frag_flags_to_number (const frag_flags
*);
10504 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10506 /* Set up property tables after relaxation. */
10509 xtensa_post_relax_hook (void)
10511 xtensa_move_seg_list_to_beginning (literal_head
);
10513 xtensa_find_unmarked_state_frags ();
10514 xtensa_mark_frags_for_org ();
10515 xtensa_mark_difference_of_two_symbols ();
10517 xtensa_create_property_segments (get_frag_is_literal
,
10519 XTENSA_LIT_SEC_NAME
,
10521 xtensa_create_xproperty_segments (get_frag_property_flags
,
10522 XTENSA_PROP_SEC_NAME
,
10525 if (warn_unaligned_branch_targets
)
10526 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10527 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10531 /* This function is only meaningful after xtensa_move_literals. */
10534 get_frag_is_literal (const fragS
*fragP
)
10536 gas_assert (fragP
!= NULL
);
10537 return fragP
->tc_frag_data
.is_literal
;
10542 xtensa_create_property_segments (frag_predicate property_function
,
10543 frag_predicate end_property_function
,
10544 const char *section_name_base
,
10545 xt_section_type sec_type
)
10549 /* Walk over all of the current segments.
10550 Walk over each fragment
10551 For each non-empty fragment,
10552 Build a property record (append where possible). */
10554 for (seclist
= &stdoutput
->sections
;
10555 seclist
&& *seclist
;
10556 seclist
= &(*seclist
)->next
)
10558 segT sec
= *seclist
;
10560 if (exclude_section_from_property_tables (sec
))
10563 if (section_has_property (sec
, property_function
))
10565 segment_info_type
*xt_seg_info
;
10566 xtensa_block_info
**xt_blocks
;
10567 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10569 prop_sec
->output_section
= prop_sec
;
10570 subseg_set (prop_sec
, 0);
10571 xt_seg_info
= seg_info (prop_sec
);
10572 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10574 /* Walk over all of the frchains here and add new sections. */
10575 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10576 end_property_function
);
10580 /* Now we fill them out.... */
10582 for (seclist
= &stdoutput
->sections
;
10583 seclist
&& *seclist
;
10584 seclist
= &(*seclist
)->next
)
10586 segment_info_type
*seginfo
;
10587 xtensa_block_info
*block
;
10588 segT sec
= *seclist
;
10590 seginfo
= seg_info (sec
);
10591 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10595 xtensa_block_info
*cur_block
;
10597 bfd_size_type rec_size
;
10599 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10602 rec_size
= num_recs
* 8;
10603 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10610 subseg_set (sec
, 0);
10611 frag_data
= frag_more (rec_size
);
10613 for (i
= 0; i
< num_recs
; i
++)
10617 /* Write the fixup. */
10618 gas_assert (cur_block
);
10619 fix
= fix_new (frag_now
, i
* 8, 4,
10620 section_symbol (cur_block
->sec
),
10622 FALSE
, BFD_RELOC_32
);
10623 fix
->fx_file
= "<internal>";
10626 /* Write the length. */
10627 md_number_to_chars (&frag_data
[4 + i
* 8],
10628 cur_block
->size
, 4);
10629 cur_block
= cur_block
->next
;
10631 frag_wane (frag_now
);
10633 frag_wane (frag_now
);
10641 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10642 const char *section_name_base
,
10643 xt_section_type sec_type
)
10647 /* Walk over all of the current segments.
10648 Walk over each fragment.
10649 For each fragment that has instructions,
10650 build an instruction record (append where possible). */
10652 for (seclist
= &stdoutput
->sections
;
10653 seclist
&& *seclist
;
10654 seclist
= &(*seclist
)->next
)
10656 segT sec
= *seclist
;
10658 if (exclude_section_from_property_tables (sec
))
10661 if (section_has_xproperty (sec
, flag_fn
))
10663 segment_info_type
*xt_seg_info
;
10664 xtensa_block_info
**xt_blocks
;
10665 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10667 prop_sec
->output_section
= prop_sec
;
10668 subseg_set (prop_sec
, 0);
10669 xt_seg_info
= seg_info (prop_sec
);
10670 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10672 /* Walk over all of the frchains here and add new sections. */
10673 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10677 /* Now we fill them out.... */
10679 for (seclist
= &stdoutput
->sections
;
10680 seclist
&& *seclist
;
10681 seclist
= &(*seclist
)->next
)
10683 segment_info_type
*seginfo
;
10684 xtensa_block_info
*block
;
10685 segT sec
= *seclist
;
10687 seginfo
= seg_info (sec
);
10688 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10692 xtensa_block_info
*cur_block
;
10694 bfd_size_type rec_size
;
10696 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10699 rec_size
= num_recs
* (8 + 4);
10700 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10701 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10708 subseg_set (sec
, 0);
10709 frag_data
= frag_more (rec_size
);
10711 for (i
= 0; i
< num_recs
; i
++)
10715 /* Write the fixup. */
10716 gas_assert (cur_block
);
10717 fix
= fix_new (frag_now
, i
* 12, 4,
10718 section_symbol (cur_block
->sec
),
10720 FALSE
, BFD_RELOC_32
);
10721 fix
->fx_file
= "<internal>";
10724 /* Write the length. */
10725 md_number_to_chars (&frag_data
[4 + i
* 12],
10726 cur_block
->size
, 4);
10727 md_number_to_chars (&frag_data
[8 + i
* 12],
10728 frag_flags_to_number (&cur_block
->flags
),
10729 sizeof (flagword
));
10730 cur_block
= cur_block
->next
;
10732 frag_wane (frag_now
);
10734 frag_wane (frag_now
);
10742 exclude_section_from_property_tables (segT sec
)
10744 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
10746 /* Sections that don't contribute to the memory footprint are excluded. */
10747 if ((flags
& SEC_DEBUGGING
)
10748 || !(flags
& SEC_ALLOC
)
10749 || (flags
& SEC_MERGE
))
10752 /* Linker cie and fde optimizations mess up property entries for
10753 eh_frame sections, but there is nothing inside them relevant to
10754 property tables anyway. */
10755 if (strcmp (sec
->name
, ".eh_frame") == 0)
10763 section_has_property (segT sec
, frag_predicate property_function
)
10765 segment_info_type
*seginfo
= seg_info (sec
);
10768 if (seginfo
&& seginfo
->frchainP
)
10770 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10772 if (property_function (fragP
)
10773 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10782 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10784 segment_info_type
*seginfo
= seg_info (sec
);
10787 if (seginfo
&& seginfo
->frchainP
)
10789 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10791 frag_flags prop_flags
;
10792 property_function (fragP
, &prop_flags
);
10793 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10801 /* Two types of block sections exist right now: literal and insns. */
10804 add_xt_block_frags (segT sec
,
10805 xtensa_block_info
**xt_block
,
10806 frag_predicate property_function
,
10807 frag_predicate end_property_function
)
10811 /* Build it if needed. */
10812 while (*xt_block
!= NULL
)
10813 xt_block
= &(*xt_block
)->next
;
10814 /* We are either at NULL at the beginning or at the end. */
10816 /* Walk through the frags. */
10817 if (seg_info (sec
)->frchainP
)
10819 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10821 fragP
= fragP
->fr_next
)
10823 if (property_function (fragP
)
10824 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10826 if (*xt_block
!= NULL
)
10828 if ((*xt_block
)->offset
+ (*xt_block
)->size
10829 == fragP
->fr_address
)
10830 (*xt_block
)->size
+= fragP
->fr_fix
;
10832 xt_block
= &((*xt_block
)->next
);
10834 if (*xt_block
== NULL
)
10836 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10837 xmalloc (sizeof (xtensa_block_info
));
10838 new_block
->sec
= sec
;
10839 new_block
->offset
= fragP
->fr_address
;
10840 new_block
->size
= fragP
->fr_fix
;
10841 new_block
->next
= NULL
;
10842 xtensa_frag_flags_init (&new_block
->flags
);
10843 *xt_block
= new_block
;
10845 if (end_property_function
10846 && end_property_function (fragP
))
10848 xt_block
= &((*xt_block
)->next
);
10856 /* Break the encapsulation of add_xt_prop_frags here. */
10859 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10861 if (prop_flags
->is_literal
10862 || prop_flags
->is_insn
10863 || prop_flags
->is_data
10864 || prop_flags
->is_unreachable
)
10871 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10873 memset (prop_flags
, 0, sizeof (frag_flags
));
10878 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10880 xtensa_frag_flags_init (prop_flags
);
10881 if (fragP
->tc_frag_data
.is_literal
)
10882 prop_flags
->is_literal
= TRUE
;
10883 if (fragP
->tc_frag_data
.is_specific_opcode
10884 || fragP
->tc_frag_data
.is_no_transform
)
10886 prop_flags
->is_no_transform
= TRUE
;
10887 if (xtensa_frag_flags_is_empty (prop_flags
))
10888 prop_flags
->is_data
= TRUE
;
10890 if (fragP
->tc_frag_data
.is_unreachable
)
10891 prop_flags
->is_unreachable
= TRUE
;
10892 else if (fragP
->tc_frag_data
.is_insn
)
10894 prop_flags
->is_insn
= TRUE
;
10895 if (fragP
->tc_frag_data
.is_loop_target
)
10896 prop_flags
->insn
.is_loop_target
= TRUE
;
10897 if (fragP
->tc_frag_data
.is_branch_target
)
10898 prop_flags
->insn
.is_branch_target
= TRUE
;
10899 if (fragP
->tc_frag_data
.is_no_density
)
10900 prop_flags
->insn
.is_no_density
= TRUE
;
10901 if (fragP
->tc_frag_data
.use_absolute_literals
)
10902 prop_flags
->insn
.is_abslit
= TRUE
;
10904 if (fragP
->tc_frag_data
.is_align
)
10906 prop_flags
->is_align
= TRUE
;
10907 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10908 if (xtensa_frag_flags_is_empty (prop_flags
))
10909 prop_flags
->is_data
= TRUE
;
10915 frag_flags_to_number (const frag_flags
*prop_flags
)
10918 if (prop_flags
->is_literal
)
10919 num
|= XTENSA_PROP_LITERAL
;
10920 if (prop_flags
->is_insn
)
10921 num
|= XTENSA_PROP_INSN
;
10922 if (prop_flags
->is_data
)
10923 num
|= XTENSA_PROP_DATA
;
10924 if (prop_flags
->is_unreachable
)
10925 num
|= XTENSA_PROP_UNREACHABLE
;
10926 if (prop_flags
->insn
.is_loop_target
)
10927 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10928 if (prop_flags
->insn
.is_branch_target
)
10930 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10931 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10934 if (prop_flags
->insn
.is_no_density
)
10935 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10936 if (prop_flags
->is_no_transform
)
10937 num
|= XTENSA_PROP_NO_TRANSFORM
;
10938 if (prop_flags
->insn
.is_no_reorder
)
10939 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10940 if (prop_flags
->insn
.is_abslit
)
10941 num
|= XTENSA_PROP_INSN_ABSLIT
;
10943 if (prop_flags
->is_align
)
10945 num
|= XTENSA_PROP_ALIGN
;
10946 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10954 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10955 const frag_flags
*prop_flags_2
)
10957 /* Cannot combine with an end marker. */
10959 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10961 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10963 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10966 if (prop_flags_1
->is_insn
)
10968 /* Properties of the beginning of the frag. */
10969 if (prop_flags_2
->insn
.is_loop_target
)
10971 if (prop_flags_2
->insn
.is_branch_target
)
10973 if (prop_flags_1
->insn
.is_no_density
!=
10974 prop_flags_2
->insn
.is_no_density
)
10976 if (prop_flags_1
->is_no_transform
!=
10977 prop_flags_2
->is_no_transform
)
10979 if (prop_flags_1
->insn
.is_no_reorder
!=
10980 prop_flags_2
->insn
.is_no_reorder
)
10982 if (prop_flags_1
->insn
.is_abslit
!=
10983 prop_flags_2
->insn
.is_abslit
)
10987 if (prop_flags_1
->is_align
)
10995 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10998 unsigned align_bits
;
11000 if (!xt_block
->flags
.is_align
)
11001 return xt_block
->size
;
11003 end_addr
= xt_block
->offset
+ xt_block
->size
;
11004 align_bits
= xt_block
->flags
.alignment
;
11005 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
11006 return end_addr
- xt_block
->offset
;
11011 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
11012 const xtensa_block_info
*xt_block_2
)
11014 if (xt_block
->sec
!= xt_block_2
->sec
)
11016 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
11017 != xt_block_2
->offset
)
11020 if (xt_block_2
->size
== 0
11021 && (!xt_block_2
->flags
.is_unreachable
11022 || xt_block
->flags
.is_unreachable
))
11024 if (xt_block_2
->flags
.is_align
11025 && xt_block
->flags
.is_align
)
11027 /* Nothing needed. */
11028 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11033 if (xt_block_2
->flags
.is_align
)
11035 /* Push alignment to previous entry. */
11036 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11037 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11042 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11043 &xt_block_2
->flags
))
11046 xt_block
->size
+= xt_block_2
->size
;
11048 if (xt_block_2
->flags
.is_align
)
11050 xt_block
->flags
.is_align
= TRUE
;
11051 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11059 add_xt_prop_frags (segT sec
,
11060 xtensa_block_info
**xt_block
,
11061 frag_flags_fn property_function
)
11065 /* Build it if needed. */
11066 while (*xt_block
!= NULL
)
11068 xt_block
= &(*xt_block
)->next
;
11070 /* We are either at NULL at the beginning or at the end. */
11072 /* Walk through the frags. */
11073 if (seg_info (sec
)->frchainP
)
11075 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
11076 fragP
= fragP
->fr_next
)
11078 xtensa_block_info tmp_block
;
11079 tmp_block
.sec
= sec
;
11080 tmp_block
.offset
= fragP
->fr_address
;
11081 tmp_block
.size
= fragP
->fr_fix
;
11082 tmp_block
.next
= NULL
;
11083 property_function (fragP
, &tmp_block
.flags
);
11085 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11086 /* && fragP->fr_fix != 0) */
11088 if ((*xt_block
) == NULL
11089 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11091 xtensa_block_info
*new_block
;
11092 if ((*xt_block
) != NULL
)
11093 xt_block
= &(*xt_block
)->next
;
11094 new_block
= (xtensa_block_info
*)
11095 xmalloc (sizeof (xtensa_block_info
));
11096 *new_block
= tmp_block
;
11097 *xt_block
= new_block
;
11105 /* op_placement_info_table */
11107 /* op_placement_info makes it easier to determine which
11108 ops can go in which slots. */
11111 init_op_placement_info_table (void)
11113 xtensa_isa isa
= xtensa_default_isa
;
11114 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11115 xtensa_opcode opcode
;
11118 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11120 op_placement_table
= (op_placement_info_table
)
11121 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11122 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11124 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11126 op_placement_info
*opi
= &op_placement_table
[opcode
];
11127 /* FIXME: Make tinsn allocation dynamic. */
11128 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
11129 as_fatal (_("too many operands in instruction"));
11130 opi
->narrowest
= XTENSA_UNDEFINED
;
11131 opi
->narrowest_size
= 0x7F;
11132 opi
->narrowest_slot
= 0;
11134 opi
->num_formats
= 0;
11136 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11138 opi
->slots
[fmt
] = 0;
11139 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11141 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11143 int fmt_length
= xtensa_format_length (isa
, fmt
);
11145 set_bit (fmt
, opi
->formats
);
11146 set_bit (slot
, opi
->slots
[fmt
]);
11147 if (fmt_length
< opi
->narrowest_size
11148 || (fmt_length
== opi
->narrowest_size
11149 && (xtensa_format_num_slots (isa
, fmt
)
11150 < xtensa_format_num_slots (isa
,
11153 opi
->narrowest
= fmt
;
11154 opi
->narrowest_size
= fmt_length
;
11155 opi
->narrowest_slot
= slot
;
11160 opi
->num_formats
++;
11163 xtensa_insnbuf_free (isa
, ibuf
);
11168 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11170 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11174 /* If the opcode is available in a single slot format, return its size. */
11177 xg_get_single_size (xtensa_opcode opcode
)
11179 return op_placement_table
[opcode
].narrowest_size
;
11183 static xtensa_format
11184 xg_get_single_format (xtensa_opcode opcode
)
11186 return op_placement_table
[opcode
].narrowest
;
11191 xg_get_single_slot (xtensa_opcode opcode
)
11193 return op_placement_table
[opcode
].narrowest_slot
;
11197 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11200 istack_init (IStack
*stack
)
11207 istack_empty (IStack
*stack
)
11209 return (stack
->ninsn
== 0);
11214 istack_full (IStack
*stack
)
11216 return (stack
->ninsn
== MAX_ISTACK
);
11220 /* Return a pointer to the top IStack entry.
11221 It is an error to call this if istack_empty () is TRUE. */
11224 istack_top (IStack
*stack
)
11226 int rec
= stack
->ninsn
- 1;
11227 gas_assert (!istack_empty (stack
));
11228 return &stack
->insn
[rec
];
11232 /* Add a new TInsn to an IStack.
11233 It is an error to call this if istack_full () is TRUE. */
11236 istack_push (IStack
*stack
, TInsn
*insn
)
11238 int rec
= stack
->ninsn
;
11239 gas_assert (!istack_full (stack
));
11240 stack
->insn
[rec
] = *insn
;
11245 /* Clear space for the next TInsn on the IStack and return a pointer
11246 to it. It is an error to call this if istack_full () is TRUE. */
11249 istack_push_space (IStack
*stack
)
11251 int rec
= stack
->ninsn
;
11253 gas_assert (!istack_full (stack
));
11254 insn
= &stack
->insn
[rec
];
11261 /* Remove the last pushed instruction. It is an error to call this if
11262 istack_empty () returns TRUE. */
11265 istack_pop (IStack
*stack
)
11267 int rec
= stack
->ninsn
- 1;
11268 gas_assert (!istack_empty (stack
));
11270 tinsn_init (&stack
->insn
[rec
]);
11274 /* TInsn functions. */
11277 tinsn_init (TInsn
*dst
)
11279 memset (dst
, 0, sizeof (TInsn
));
11283 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11286 tinsn_has_symbolic_operands (const TInsn
*insn
)
11289 int n
= insn
->ntok
;
11291 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11293 for (i
= 0; i
< n
; ++i
)
11295 switch (insn
->tok
[i
].X_op
)
11309 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11311 xtensa_isa isa
= xtensa_default_isa
;
11313 int n
= insn
->ntok
;
11315 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11317 for (i
= 0; i
< n
; ++i
)
11319 switch (insn
->tok
[i
].X_op
)
11327 /* Errors for these types are caught later. */
11332 /* Symbolic immediates are only allowed on the last immediate
11333 operand. At this time, CONST16 is the only opcode where we
11334 support non-PC-relative relocations. */
11335 if (i
!= get_relaxable_immed (insn
->opcode
)
11336 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11337 && insn
->opcode
!= xtensa_const16_opcode
))
11339 as_bad (_("invalid symbolic operand"));
11348 /* For assembly code with complex expressions (e.g. subtraction),
11349 we have to build them in the literal pool so that
11350 their results are calculated correctly after relaxation.
11351 The relaxation only handles expressions that
11352 boil down to SYMBOL + OFFSET. */
11355 tinsn_has_complex_operands (const TInsn
*insn
)
11358 int n
= insn
->ntok
;
11359 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11360 for (i
= 0; i
< n
; ++i
)
11362 switch (insn
->tok
[i
].X_op
)
11378 /* Encode a TInsn opcode and its constant operands into slotbuf.
11379 Return TRUE if there is a symbol in the immediate field. This
11380 function assumes that:
11381 1) The number of operands are correct.
11382 2) The insn_type is ITYPE_INSN.
11383 3) The opcode can be encoded in the specified format and slot.
11384 4) Operands are either O_constant or O_symbol, and all constants fit. */
11387 tinsn_to_slotbuf (xtensa_format fmt
,
11390 xtensa_insnbuf slotbuf
)
11392 xtensa_isa isa
= xtensa_default_isa
;
11393 xtensa_opcode opcode
= tinsn
->opcode
;
11394 bfd_boolean has_fixup
= FALSE
;
11395 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11398 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
11399 if (noperands
!= tinsn
->ntok
)
11400 as_fatal (_("operand number mismatch"));
11402 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11404 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11405 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11409 for (i
= 0; i
< noperands
; i
++)
11411 expressionS
*exp
= &tinsn
->tok
[i
];
11420 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11422 /* The register number has already been checked in
11423 expression_maybe_register, so we don't need to check here. */
11424 opnd_value
= exp
->X_add_number
;
11425 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11426 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11429 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11433 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11435 as_where (&file_name
, &line
);
11436 /* It is a constant and we called this function
11437 then we have to try to fit it. */
11438 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11439 exp
->X_add_number
, file_name
, line
);
11452 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11453 into a multi-slot instruction, fill the other slots with NOPs.
11454 Return TRUE if there is a symbol in the immediate field. See also the
11455 assumptions listed for tinsn_to_slotbuf. */
11458 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11460 static xtensa_insnbuf slotbuf
= 0;
11461 static vliw_insn vinsn
;
11462 xtensa_isa isa
= xtensa_default_isa
;
11463 bfd_boolean has_fixup
= FALSE
;
11468 slotbuf
= xtensa_insnbuf_alloc (isa
);
11469 xg_init_vinsn (&vinsn
);
11472 xg_clear_vinsn (&vinsn
);
11474 bundle_tinsn (tinsn
, &vinsn
);
11476 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11478 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11480 /* Only one slot may have a fix-up because the rest contains NOPs. */
11482 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11483 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11490 /* Check the instruction arguments. Return TRUE on failure. */
11493 tinsn_check_arguments (const TInsn
*insn
)
11495 xtensa_isa isa
= xtensa_default_isa
;
11496 xtensa_opcode opcode
= insn
->opcode
;
11497 xtensa_regfile t1_regfile
, t2_regfile
;
11498 int t1_reg
, t2_reg
;
11499 int t1_base_reg
, t1_last_reg
;
11500 int t2_base_reg
, t2_last_reg
;
11501 char t1_inout
, t2_inout
;
11504 if (opcode
== XTENSA_UNDEFINED
)
11506 as_bad (_("invalid opcode"));
11510 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11512 as_bad (_("too few operands"));
11516 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11518 as_bad (_("too many operands"));
11522 /* Check registers. */
11523 for (j
= 0; j
< insn
->ntok
; j
++)
11525 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
11528 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
11529 t2_base_reg
= insn
->tok
[j
].X_add_number
;
11531 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
11533 for (i
= 0; i
< insn
->ntok
; i
++)
11538 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
11541 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
11543 if (t1_regfile
!= t2_regfile
)
11546 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
11547 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
11549 t1_base_reg
= insn
->tok
[i
].X_add_number
;
11550 t1_last_reg
= (t1_base_reg
11551 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
11553 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
11555 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
11557 if (t1_reg
!= t2_reg
)
11560 if (t1_inout
!= 'i' && t2_inout
!= 'i')
11562 as_bad (_("multiple writes to the same register"));
11573 /* Load an instruction from its encoded form. */
11576 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11580 xg_init_vinsn (&vinsn
);
11581 vinsn_from_chars (&vinsn
, f
);
11583 *tinsn
= vinsn
.slots
[slot
];
11584 xg_free_vinsn (&vinsn
);
11589 tinsn_from_insnbuf (TInsn
*tinsn
,
11590 xtensa_insnbuf slotbuf
,
11595 xtensa_isa isa
= xtensa_default_isa
;
11597 /* Find the immed. */
11598 tinsn_init (tinsn
);
11599 tinsn
->insn_type
= ITYPE_INSN
;
11600 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11601 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11602 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11603 for (i
= 0; i
< tinsn
->ntok
; i
++)
11605 set_expr_const (&tinsn
->tok
[i
],
11606 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11607 tinsn
->opcode
, i
));
11612 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11615 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11617 xtensa_opcode opcode
= tinsn
->opcode
;
11620 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11622 opnum
= get_relaxable_immed (opcode
);
11623 gas_assert (opnum
>= 0);
11624 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11625 fragP
->tc_frag_data
.slot_symbols
[slot
],
11626 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11628 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
11633 get_num_stack_text_bytes (IStack
*istack
)
11636 int text_bytes
= 0;
11638 for (i
= 0; i
< istack
->ninsn
; i
++)
11640 TInsn
*tinsn
= &istack
->insn
[i
];
11641 if (tinsn
->insn_type
== ITYPE_INSN
)
11642 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11649 get_num_stack_literal_bytes (IStack
*istack
)
11654 for (i
= 0; i
< istack
->ninsn
; i
++)
11656 TInsn
*tinsn
= &istack
->insn
[i
];
11657 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11664 /* vliw_insn functions. */
11667 xg_init_vinsn (vliw_insn
*v
)
11670 xtensa_isa isa
= xtensa_default_isa
;
11672 xg_clear_vinsn (v
);
11674 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11675 if (v
->insnbuf
== NULL
)
11676 as_fatal (_("out of memory"));
11678 for (i
= 0; i
< config_max_slots
; i
++)
11680 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11681 if (v
->slotbuf
[i
] == NULL
)
11682 as_fatal (_("out of memory"));
11688 xg_clear_vinsn (vliw_insn
*v
)
11692 memset (v
, 0, offsetof (vliw_insn
, slots
)
11693 + sizeof(TInsn
) * config_max_slots
);
11695 v
->format
= XTENSA_UNDEFINED
;
11697 v
->inside_bundle
= FALSE
;
11699 if (xt_saved_debug_type
!= DEBUG_NONE
)
11700 debug_type
= xt_saved_debug_type
;
11702 for (i
= 0; i
< config_max_slots
; i
++)
11703 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11708 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
11711 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
11712 dst
->insnbuf
= src
->insnbuf
;
11713 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
11718 vinsn_has_specific_opcodes (vliw_insn
*v
)
11722 for (i
= 0; i
< v
->num_slots
; i
++)
11724 if (v
->slots
[i
].is_specific_opcode
)
11732 xg_free_vinsn (vliw_insn
*v
)
11735 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11736 for (i
= 0; i
< config_max_slots
; i
++)
11737 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11741 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11742 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11745 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11748 bfd_boolean record_fixup
)
11750 xtensa_isa isa
= xtensa_default_isa
;
11751 xtensa_format fmt
= vinsn
->format
;
11752 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11754 bfd_boolean has_fixup
= FALSE
;
11756 xtensa_format_encode (isa
, fmt
, insnbuf
);
11758 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11760 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11761 expressionS
*extra_arg
= &tinsn
->extra_arg
;
11762 bfd_boolean tinsn_has_fixup
=
11763 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11764 vinsn
->slotbuf
[slot
]);
11766 xtensa_format_set_slot (isa
, fmt
, slot
,
11767 insnbuf
, vinsn
->slotbuf
[slot
]);
11768 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
11770 if (vinsn
->num_slots
!= 1)
11771 as_bad (_("TLS relocation not allowed in FLIX bundle"));
11772 else if (record_fixup
)
11773 /* Instructions that generate TLS relocations should always be
11774 relaxed in the front-end. If "record_fixup" is set, then this
11775 function is being called during back-end relaxation, so flag
11776 the unexpected behavior as an error. */
11777 as_bad (_("unexpected TLS relocation"));
11779 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
11780 xtensa_format_length (isa
, fmt
),
11781 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
11782 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
11784 if (tinsn_has_fixup
)
11787 xtensa_opcode opcode
= tinsn
->opcode
;
11788 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11791 for (i
= 0; i
< noperands
; i
++)
11793 expressionS
* exp
= &tinsn
->tok
[i
];
11799 if (get_relaxable_immed (opcode
) == i
)
11801 /* Add a fix record for the instruction, except if this
11802 function is being called prior to relaxation, i.e.,
11803 if record_fixup is false, and the instruction might
11804 be relaxed later. */
11806 || tinsn
->is_specific_opcode
11807 || !xg_is_relaxable_insn (tinsn
, 0))
11809 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
11810 frag_offset
- fragP
->fr_literal
);
11814 if (exp
->X_op
!= O_symbol
)
11815 as_bad (_("invalid operand"));
11816 tinsn
->symbol
= exp
->X_add_symbol
;
11817 tinsn
->offset
= exp
->X_add_number
;
11821 as_bad (_("symbolic operand not allowed"));
11829 as_bad (_("expression too complex"));
11841 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11843 static xtensa_insnbuf insnbuf
= NULL
;
11844 static xtensa_insnbuf slotbuf
= NULL
;
11847 xtensa_isa isa
= xtensa_default_isa
;
11851 insnbuf
= xtensa_insnbuf_alloc (isa
);
11852 slotbuf
= xtensa_insnbuf_alloc (isa
);
11855 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11856 fmt
= xtensa_format_decode (isa
, insnbuf
);
11857 if (fmt
== XTENSA_UNDEFINED
)
11858 as_fatal (_("cannot decode instruction format"));
11859 vinsn
->format
= fmt
;
11860 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11862 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11864 TInsn
*tinsn
= &vinsn
->slots
[i
];
11865 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11866 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11871 /* Expression utilities. */
11873 /* Return TRUE if the expression is an integer constant. */
11876 expr_is_const (const expressionS
*s
)
11878 return (s
->X_op
== O_constant
);
11882 /* Get the expression constant.
11883 Calling this is illegal if expr_is_const () returns TRUE. */
11886 get_expr_const (const expressionS
*s
)
11888 gas_assert (expr_is_const (s
));
11889 return s
->X_add_number
;
11893 /* Set the expression to a constant value. */
11896 set_expr_const (expressionS
*s
, offsetT val
)
11898 s
->X_op
= O_constant
;
11899 s
->X_add_number
= val
;
11900 s
->X_add_symbol
= NULL
;
11901 s
->X_op_symbol
= NULL
;
11906 expr_is_register (const expressionS
*s
)
11908 return (s
->X_op
== O_register
);
11912 /* Get the expression constant.
11913 Calling this is illegal if expr_is_const () returns TRUE. */
11916 get_expr_register (const expressionS
*s
)
11918 gas_assert (expr_is_register (s
));
11919 return s
->X_add_number
;
11923 /* Set the expression to a symbol + constant offset. */
11926 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11928 s
->X_op
= O_symbol
;
11929 s
->X_add_symbol
= sym
;
11930 s
->X_op_symbol
= NULL
; /* unused */
11931 s
->X_add_number
= offset
;
11935 /* Return TRUE if the two expressions are equal. */
11938 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11940 if (s1
->X_op
!= s2
->X_op
)
11942 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11944 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11946 if (s1
->X_add_number
!= s2
->X_add_number
)
11953 copy_expr (expressionS
*dst
, const expressionS
*src
)
11955 memcpy (dst
, src
, sizeof (expressionS
));
11959 /* Support for the "--rename-section" option. */
11961 struct rename_section_struct
11965 struct rename_section_struct
*next
;
11968 static struct rename_section_struct
*section_rename
;
11971 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11972 entries to the section_rename list. Note: Specifying multiple
11973 renamings separated by colons is not documented and is retained only
11974 for backward compatibility. */
11977 build_section_rename (const char *arg
)
11979 struct rename_section_struct
*r
;
11980 char *this_arg
= NULL
;
11981 char *next_arg
= NULL
;
11983 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11985 char *old_name
, *new_name
;
11989 next_arg
= strchr (this_arg
, ':');
11997 old_name
= this_arg
;
11998 new_name
= strchr (this_arg
, '=');
12000 if (*old_name
== '\0')
12002 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12005 if (!new_name
|| new_name
[1] == '\0')
12007 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
12014 /* Check for invalid section renaming. */
12015 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12017 if (strcmp (r
->old_name
, old_name
) == 0)
12018 as_bad (_("section %s renamed multiple times"), old_name
);
12019 if (strcmp (r
->new_name
, new_name
) == 0)
12020 as_bad (_("multiple sections remapped to output section %s"),
12025 r
= (struct rename_section_struct
*)
12026 xmalloc (sizeof (struct rename_section_struct
));
12027 r
->old_name
= xstrdup (old_name
);
12028 r
->new_name
= xstrdup (new_name
);
12029 r
->next
= section_rename
;
12030 section_rename
= r
;
12036 xtensa_section_rename (char *name
)
12038 struct rename_section_struct
*r
= section_rename
;
12040 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12042 if (strcmp (r
->old_name
, name
) == 0)
12043 return r
->new_name
;