1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 /* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
358 struct suffix_reloc_map
362 bfd_reloc_code_real_type reloc
;
363 unsigned char operator;
366 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
368 static struct suffix_reloc_map suffix_relocs
[] =
370 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
371 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
372 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
373 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
387 directive_literal_prefix
,
389 directive_absolute_literals
,
390 directive_last_directive
396 bfd_boolean can_be_negated
;
399 const directive_infoS directive_info
[] =
402 { "literal", FALSE
},
404 { "transform", TRUE
},
405 { "freeregs", FALSE
},
406 { "longcalls", TRUE
},
407 { "literal_prefix", FALSE
},
408 { "schedule", TRUE
},
409 { "absolute-literals", TRUE
}
412 bfd_boolean directive_state
[] =
416 #if !XCHAL_HAVE_DENSITY
421 TRUE
, /* transform */
422 FALSE
, /* freeregs */
423 FALSE
, /* longcalls */
424 FALSE
, /* literal_prefix */
425 FALSE
, /* schedule */
426 #if XSHAL_USE_ABSOLUTE_LITERALS
427 TRUE
/* absolute_literals */
429 FALSE
/* absolute_literals */
434 /* Directive functions. */
436 static void xtensa_begin_directive (int);
437 static void xtensa_end_directive (int);
438 static void xtensa_literal_prefix (void);
439 static void xtensa_literal_position (int);
440 static void xtensa_literal_pseudo (int);
441 static void xtensa_frequency_pseudo (int);
442 static void xtensa_elf_cons (int);
444 /* Parsing and Idiom Translation. */
446 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
448 /* Various Other Internal Functions. */
450 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
451 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
452 static void xtensa_mark_literal_pool_location (void);
453 static addressT
get_expanded_loop_offset (xtensa_opcode
);
454 static fragS
*get_literal_pool_location (segT
);
455 static void set_literal_pool_location (segT
, fragS
*);
456 static void xtensa_set_frag_assembly_state (fragS
*);
457 static void finish_vinsn (vliw_insn
*);
458 static bfd_boolean
emit_single_op (TInsn
*);
459 static int total_frag_text_expansion (fragS
*);
461 /* Alignment Functions. */
463 static int get_text_align_power (unsigned);
464 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
465 static int branch_align_power (segT
);
467 /* Helpers for xtensa_relax_frag(). */
469 static long relax_frag_add_nop (fragS
*);
471 /* Accessors for additional per-subsegment information. */
473 static unsigned get_last_insn_flags (segT
, subsegT
);
474 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
475 static float get_subseg_total_freq (segT
, subsegT
);
476 static float get_subseg_target_freq (segT
, subsegT
);
477 static void set_subseg_freq (segT
, subsegT
, float, float);
479 /* Segment list functions. */
481 static void xtensa_move_literals (void);
482 static void xtensa_reorder_segments (void);
483 static void xtensa_switch_to_literal_fragment (emit_state
*);
484 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
485 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
486 static void xtensa_restore_emit_state (emit_state
*);
487 static segT
cache_literal_section (bfd_boolean
);
489 /* Import from elf32-xtensa.c in BFD library. */
491 extern asection
*xtensa_get_property_section (asection
*, const char *);
493 /* op_placement_info functions. */
495 static void init_op_placement_info_table (void);
496 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
497 static int xg_get_single_size (xtensa_opcode
);
498 static xtensa_format
xg_get_single_format (xtensa_opcode
);
499 static int xg_get_single_slot (xtensa_opcode
);
501 /* TInsn and IStack functions. */
503 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
504 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
505 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
506 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
507 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
508 static void tinsn_from_chars (TInsn
*, char *, int);
509 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
510 static int get_num_stack_text_bytes (IStack
*);
511 static int get_num_stack_literal_bytes (IStack
*);
513 /* vliw_insn functions. */
515 static void xg_init_vinsn (vliw_insn
*);
516 static void xg_clear_vinsn (vliw_insn
*);
517 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
518 static void xg_free_vinsn (vliw_insn
*);
519 static bfd_boolean vinsn_to_insnbuf
520 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
521 static void vinsn_from_chars (vliw_insn
*, char *);
523 /* Expression Utilities. */
525 bfd_boolean
expr_is_const (const expressionS
*);
526 offsetT
get_expr_const (const expressionS
*);
527 void set_expr_const (expressionS
*, offsetT
);
528 bfd_boolean
expr_is_register (const expressionS
*);
529 offsetT
get_expr_register (const expressionS
*);
530 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
531 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
532 static void copy_expr (expressionS
*, const expressionS
*);
534 /* Section renaming. */
536 static void build_section_rename (const char *);
539 /* ISA imported from bfd. */
540 extern xtensa_isa xtensa_default_isa
;
542 extern int target_big_endian
;
544 static xtensa_opcode xtensa_addi_opcode
;
545 static xtensa_opcode xtensa_addmi_opcode
;
546 static xtensa_opcode xtensa_call0_opcode
;
547 static xtensa_opcode xtensa_call4_opcode
;
548 static xtensa_opcode xtensa_call8_opcode
;
549 static xtensa_opcode xtensa_call12_opcode
;
550 static xtensa_opcode xtensa_callx0_opcode
;
551 static xtensa_opcode xtensa_callx4_opcode
;
552 static xtensa_opcode xtensa_callx8_opcode
;
553 static xtensa_opcode xtensa_callx12_opcode
;
554 static xtensa_opcode xtensa_const16_opcode
;
555 static xtensa_opcode xtensa_entry_opcode
;
556 static xtensa_opcode xtensa_extui_opcode
;
557 static xtensa_opcode xtensa_movi_opcode
;
558 static xtensa_opcode xtensa_movi_n_opcode
;
559 static xtensa_opcode xtensa_isync_opcode
;
560 static xtensa_opcode xtensa_jx_opcode
;
561 static xtensa_opcode xtensa_l32r_opcode
;
562 static xtensa_opcode xtensa_loop_opcode
;
563 static xtensa_opcode xtensa_loopnez_opcode
;
564 static xtensa_opcode xtensa_loopgtz_opcode
;
565 static xtensa_opcode xtensa_nop_opcode
;
566 static xtensa_opcode xtensa_nop_n_opcode
;
567 static xtensa_opcode xtensa_or_opcode
;
568 static xtensa_opcode xtensa_ret_opcode
;
569 static xtensa_opcode xtensa_ret_n_opcode
;
570 static xtensa_opcode xtensa_retw_opcode
;
571 static xtensa_opcode xtensa_retw_n_opcode
;
572 static xtensa_opcode xtensa_rsr_lcount_opcode
;
573 static xtensa_opcode xtensa_waiti_opcode
;
576 /* Command-line Options. */
578 bfd_boolean use_literal_section
= TRUE
;
579 static bfd_boolean align_targets
= TRUE
;
580 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
581 static bfd_boolean has_a0_b_retw
= FALSE
;
582 static bfd_boolean workaround_a0_b_retw
= FALSE
;
583 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
584 static bfd_boolean workaround_short_loop
= FALSE
;
585 static bfd_boolean maybe_has_short_loop
= FALSE
;
586 static bfd_boolean workaround_close_loop_end
= FALSE
;
587 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
588 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
590 /* When workaround_short_loops is TRUE, all loops with early exits must
591 have at least 3 instructions. workaround_all_short_loops is a modifier
592 to the workaround_short_loop flag. In addition to the
593 workaround_short_loop actions, all straightline loopgtz and loopnez
594 must have at least 3 instructions. */
596 static bfd_boolean workaround_all_short_loops
= FALSE
;
600 xtensa_setup_hw_workarounds (int earliest
, int latest
)
602 if (earliest
> latest
)
603 as_fatal (_("illegal range of target hardware versions"));
605 /* Enable all workarounds for pre-T1050.0 hardware. */
606 if (earliest
< 105000 || latest
< 105000)
608 workaround_a0_b_retw
|= TRUE
;
609 workaround_b_j_loop_end
|= TRUE
;
610 workaround_short_loop
|= TRUE
;
611 workaround_close_loop_end
|= TRUE
;
612 workaround_all_short_loops
|= TRUE
;
613 enforce_three_byte_loop_align
= TRUE
;
620 option_density
= OPTION_MD_BASE
,
627 option_no_link_relax
,
635 option_text_section_literals
,
636 option_no_text_section_literals
,
638 option_absolute_literals
,
639 option_no_absolute_literals
,
641 option_align_targets
,
642 option_no_align_targets
,
644 option_warn_unaligned_targets
,
649 option_workaround_a0_b_retw
,
650 option_no_workaround_a0_b_retw
,
652 option_workaround_b_j_loop_end
,
653 option_no_workaround_b_j_loop_end
,
655 option_workaround_short_loop
,
656 option_no_workaround_short_loop
,
658 option_workaround_all_short_loops
,
659 option_no_workaround_all_short_loops
,
661 option_workaround_close_loop_end
,
662 option_no_workaround_close_loop_end
,
664 option_no_workarounds
,
666 option_rename_section_name
,
669 option_prefer_const16
,
671 option_target_hardware
674 const char *md_shortopts
= "";
676 struct option md_longopts
[] =
678 { "density", no_argument
, NULL
, option_density
},
679 { "no-density", no_argument
, NULL
, option_no_density
},
681 /* Both "relax" and "generics" are deprecated and treated as equivalent
682 to the "transform" option. */
683 { "relax", no_argument
, NULL
, option_relax
},
684 { "no-relax", no_argument
, NULL
, option_no_relax
},
685 { "generics", no_argument
, NULL
, option_generics
},
686 { "no-generics", no_argument
, NULL
, option_no_generics
},
688 { "transform", no_argument
, NULL
, option_transform
},
689 { "no-transform", no_argument
, NULL
, option_no_transform
},
690 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
691 { "no-text-section-literals", no_argument
, NULL
,
692 option_no_text_section_literals
},
693 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
694 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
695 /* This option was changed from -align-target to -target-align
696 because it conflicted with the "-al" option. */
697 { "target-align", no_argument
, NULL
, option_align_targets
},
698 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
699 { "warn-unaligned-targets", no_argument
, NULL
,
700 option_warn_unaligned_targets
},
701 { "longcalls", no_argument
, NULL
, option_longcalls
},
702 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
704 { "no-workaround-a0-b-retw", no_argument
, NULL
,
705 option_no_workaround_a0_b_retw
},
706 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
708 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
709 option_no_workaround_b_j_loop_end
},
710 { "workaround-b-j-loop-end", no_argument
, NULL
,
711 option_workaround_b_j_loop_end
},
713 { "no-workaround-short-loops", no_argument
, NULL
,
714 option_no_workaround_short_loop
},
715 { "workaround-short-loops", no_argument
, NULL
,
716 option_workaround_short_loop
},
718 { "no-workaround-all-short-loops", no_argument
, NULL
,
719 option_no_workaround_all_short_loops
},
720 { "workaround-all-short-loop", no_argument
, NULL
,
721 option_workaround_all_short_loops
},
723 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
724 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
726 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
728 { "no-workaround-close-loop-end", no_argument
, NULL
,
729 option_no_workaround_close_loop_end
},
730 { "workaround-close-loop-end", no_argument
, NULL
,
731 option_workaround_close_loop_end
},
733 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
735 { "link-relax", no_argument
, NULL
, option_link_relax
},
736 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
738 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
740 { NULL
, no_argument
, NULL
, 0 }
743 size_t md_longopts_size
= sizeof md_longopts
;
747 md_parse_option (int c
, char *arg
)
752 as_warn (_("--density option is ignored"));
754 case option_no_density
:
755 as_warn (_("--no-density option is ignored"));
757 case option_link_relax
:
760 case option_no_link_relax
:
763 case option_generics
:
764 as_warn (_("--generics is deprecated; use --transform instead"));
765 return md_parse_option (option_transform
, arg
);
766 case option_no_generics
:
767 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
768 return md_parse_option (option_no_transform
, arg
);
770 as_warn (_("--relax is deprecated; use --transform instead"));
771 return md_parse_option (option_transform
, arg
);
772 case option_no_relax
:
773 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
774 return md_parse_option (option_no_transform
, arg
);
775 case option_longcalls
:
776 directive_state
[directive_longcalls
] = TRUE
;
778 case option_no_longcalls
:
779 directive_state
[directive_longcalls
] = FALSE
;
781 case option_text_section_literals
:
782 use_literal_section
= FALSE
;
784 case option_no_text_section_literals
:
785 use_literal_section
= TRUE
;
787 case option_absolute_literals
:
788 if (!absolute_literals_supported
)
790 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
793 directive_state
[directive_absolute_literals
] = TRUE
;
795 case option_no_absolute_literals
:
796 directive_state
[directive_absolute_literals
] = FALSE
;
799 case option_workaround_a0_b_retw
:
800 workaround_a0_b_retw
= TRUE
;
802 case option_no_workaround_a0_b_retw
:
803 workaround_a0_b_retw
= FALSE
;
805 case option_workaround_b_j_loop_end
:
806 workaround_b_j_loop_end
= TRUE
;
808 case option_no_workaround_b_j_loop_end
:
809 workaround_b_j_loop_end
= FALSE
;
812 case option_workaround_short_loop
:
813 workaround_short_loop
= TRUE
;
815 case option_no_workaround_short_loop
:
816 workaround_short_loop
= FALSE
;
819 case option_workaround_all_short_loops
:
820 workaround_all_short_loops
= TRUE
;
822 case option_no_workaround_all_short_loops
:
823 workaround_all_short_loops
= FALSE
;
826 case option_workaround_close_loop_end
:
827 workaround_close_loop_end
= TRUE
;
829 case option_no_workaround_close_loop_end
:
830 workaround_close_loop_end
= FALSE
;
833 case option_no_workarounds
:
834 workaround_a0_b_retw
= FALSE
;
835 workaround_b_j_loop_end
= FALSE
;
836 workaround_short_loop
= FALSE
;
837 workaround_all_short_loops
= FALSE
;
838 workaround_close_loop_end
= FALSE
;
841 case option_align_targets
:
842 align_targets
= TRUE
;
844 case option_no_align_targets
:
845 align_targets
= FALSE
;
848 case option_warn_unaligned_targets
:
849 warn_unaligned_branch_targets
= TRUE
;
852 case option_rename_section_name
:
853 build_section_rename (arg
);
857 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
858 should be emitted or not. FIXME: Not implemented. */
861 case option_prefer_l32r
:
863 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
867 case option_prefer_const16
:
869 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
873 case option_target_hardware
:
875 int earliest
, latest
= 0;
876 if (*arg
== 0 || *arg
== '-')
877 as_fatal (_("invalid target hardware version"));
879 earliest
= strtol (arg
, &arg
, 0);
883 else if (*arg
== '-')
886 as_fatal (_("invalid target hardware version"));
887 latest
= strtol (arg
, &arg
, 0);
890 as_fatal (_("invalid target hardware version"));
892 xtensa_setup_hw_workarounds (earliest
, latest
);
896 case option_transform
:
897 /* This option has no affect other than to use the defaults,
898 which are already set. */
901 case option_no_transform
:
902 /* This option turns off all transformations of any kind.
903 However, because we want to preserve the state of other
904 directives, we only change its own field. Thus, before
905 you perform any transformation, always check if transform
906 is available. If you use the functions we provide for this
907 purpose, you will be ok. */
908 directive_state
[directive_transform
] = FALSE
;
918 md_show_usage (FILE *stream
)
922 --[no-]text-section-literals\n\
923 [Do not] put literals in the text section\n\
924 --[no-]absolute-literals\n\
925 [Do not] default to use non-PC-relative literals\n\
926 --[no-]target-align [Do not] try to align branch targets\n\
927 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
928 --[no-]transform [Do not] transform instructions\n\
929 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
933 /* Functions related to the list of current label symbols. */
936 xtensa_add_insn_label (symbolS
*sym
)
940 if (!free_insn_labels
)
941 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
944 l
= free_insn_labels
;
945 free_insn_labels
= l
->next
;
949 l
->next
= insn_labels
;
955 xtensa_clear_insn_labels (void)
959 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
967 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
971 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
973 symbolS
*lit_sym
= lit
->sym
;
974 S_SET_VALUE (lit_sym
, new_offset
);
975 symbol_set_frag (lit_sym
, new_frag
);
980 /* Directive data and functions. */
982 typedef struct state_stackS_struct
984 directiveE directive
;
986 bfd_boolean old_state
;
990 struct state_stackS_struct
*prev
;
993 state_stackS
*directive_state_stack
;
995 const pseudo_typeS md_pseudo_table
[] =
997 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
998 { "literal_position", xtensa_literal_position
, 0 },
999 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1000 { "long", xtensa_elf_cons
, 4 },
1001 { "word", xtensa_elf_cons
, 4 },
1002 { "short", xtensa_elf_cons
, 2 },
1003 { "begin", xtensa_begin_directive
, 0 },
1004 { "end", xtensa_end_directive
, 0 },
1005 { "literal", xtensa_literal_pseudo
, 0 },
1006 { "frequency", xtensa_frequency_pseudo
, 0 },
1012 use_transform (void)
1014 /* After md_end, you should be checking frag by frag, rather
1015 than state directives. */
1016 assert (!past_xtensa_end
);
1017 return directive_state
[directive_transform
];
1022 do_align_targets (void)
1024 /* Do not use this function after md_end; just look at align_targets
1025 instead. There is no target-align directive, so alignment is either
1026 enabled for all frags or not done at all. */
1027 assert (!past_xtensa_end
);
1028 return align_targets
&& use_transform ();
1033 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1037 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1039 as_where (&file
, &line
);
1041 stack
->directive
= directive
;
1042 stack
->negated
= negated
;
1043 stack
->old_state
= directive_state
[directive
];
1046 stack
->datum
= datum
;
1047 stack
->prev
= directive_state_stack
;
1048 directive_state_stack
= stack
;
1050 directive_state
[directive
] = !negated
;
1055 directive_pop (directiveE
*directive
,
1056 bfd_boolean
*negated
,
1061 state_stackS
*top
= directive_state_stack
;
1063 if (!directive_state_stack
)
1065 as_bad (_("unmatched end directive"));
1066 *directive
= directive_none
;
1070 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1071 *directive
= top
->directive
;
1072 *negated
= top
->negated
;
1075 *datum
= top
->datum
;
1076 directive_state_stack
= top
->prev
;
1082 directive_balance (void)
1084 while (directive_state_stack
)
1086 directiveE directive
;
1087 bfd_boolean negated
;
1092 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1093 as_warn_where ((char *) file
, line
,
1094 _(".begin directive with no matching .end directive"));
1100 inside_directive (directiveE dir
)
1102 state_stackS
*top
= directive_state_stack
;
1104 while (top
&& top
->directive
!= dir
)
1107 return (top
!= NULL
);
1112 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1116 char *directive_string
;
1118 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1123 input_line_pointer
+= 3;
1126 len
= strspn (input_line_pointer
,
1127 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1129 /* This code is a hack to make .begin [no-][generics|relax] exactly
1130 equivalent to .begin [no-]transform. We should remove it when
1131 we stop accepting those options. */
1133 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1135 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1136 directive_string
= "transform";
1138 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1140 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1141 directive_string
= "transform";
1144 directive_string
= input_line_pointer
;
1146 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1148 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1150 input_line_pointer
+= len
;
1151 *directive
= (directiveE
) i
;
1152 if (*negated
&& !directive_info
[i
].can_be_negated
)
1153 as_bad (_("directive %s cannot be negated"),
1154 directive_info
[i
].name
);
1159 as_bad (_("unknown directive"));
1160 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1165 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1167 directiveE directive
;
1168 bfd_boolean negated
;
1172 get_directive (&directive
, &negated
);
1173 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1175 discard_rest_of_line ();
1179 if (cur_vinsn
.inside_bundle
)
1180 as_bad (_("directives are not valid inside bundles"));
1184 case directive_literal
:
1185 if (!inside_directive (directive_literal
))
1187 /* Previous labels go with whatever follows this directive, not with
1188 the literal, so save them now. */
1189 saved_insn_labels
= insn_labels
;
1192 as_warn (_(".begin literal is deprecated; use .literal instead"));
1193 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1194 xtensa_switch_to_literal_fragment (state
);
1195 directive_push (directive_literal
, negated
, state
);
1198 case directive_literal_prefix
:
1199 /* Have to flush pending output because a movi relaxed to an l32r
1200 might produce a literal. */
1201 md_flush_pending_output ();
1202 /* Check to see if the current fragment is a literal
1203 fragment. If it is, then this operation is not allowed. */
1204 if (generating_literals
)
1206 as_bad (_("cannot set literal_prefix inside literal fragment"));
1210 /* Allocate the literal state for this section and push
1211 onto the directive stack. */
1212 ls
= xmalloc (sizeof (lit_state
));
1215 *ls
= default_lit_sections
;
1216 directive_push (directive_literal_prefix
, negated
, ls
);
1218 /* Process the new prefix. */
1219 xtensa_literal_prefix ();
1222 case directive_freeregs
:
1223 /* This information is currently unused, but we'll accept the statement
1224 and just discard the rest of the line. This won't check the syntax,
1225 but it will accept every correct freeregs directive. */
1226 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1227 directive_push (directive_freeregs
, negated
, 0);
1230 case directive_schedule
:
1231 md_flush_pending_output ();
1232 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1233 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1234 directive_push (directive_schedule
, negated
, 0);
1235 xtensa_set_frag_assembly_state (frag_now
);
1238 case directive_density
:
1239 as_warn (_(".begin [no-]density is ignored"));
1242 case directive_absolute_literals
:
1243 md_flush_pending_output ();
1244 if (!absolute_literals_supported
&& !negated
)
1246 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1249 xtensa_set_frag_assembly_state (frag_now
);
1250 directive_push (directive
, negated
, 0);
1254 md_flush_pending_output ();
1255 xtensa_set_frag_assembly_state (frag_now
);
1256 directive_push (directive
, negated
, 0);
1260 demand_empty_rest_of_line ();
1265 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1267 directiveE begin_directive
, end_directive
;
1268 bfd_boolean begin_negated
, end_negated
;
1272 emit_state
**state_ptr
;
1275 if (cur_vinsn
.inside_bundle
)
1276 as_bad (_("directives are not valid inside bundles"));
1278 get_directive (&end_directive
, &end_negated
);
1280 md_flush_pending_output ();
1282 switch (end_directive
)
1284 case (directiveE
) XTENSA_UNDEFINED
:
1285 discard_rest_of_line ();
1288 case directive_density
:
1289 as_warn (_(".end [no-]density is ignored"));
1290 demand_empty_rest_of_line ();
1293 case directive_absolute_literals
:
1294 if (!absolute_literals_supported
&& !end_negated
)
1296 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1297 demand_empty_rest_of_line ();
1306 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1307 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1308 (const void **) state_ptr
);
1310 if (begin_directive
!= directive_none
)
1312 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1314 as_bad (_("does not match begin %s%s at %s:%d"),
1315 begin_negated
? "no-" : "",
1316 directive_info
[begin_directive
].name
, file
, line
);
1320 switch (end_directive
)
1322 case directive_literal
:
1323 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1324 xtensa_restore_emit_state (state
);
1325 xtensa_set_frag_assembly_state (frag_now
);
1327 if (!inside_directive (directive_literal
))
1329 /* Restore the list of current labels. */
1330 xtensa_clear_insn_labels ();
1331 insn_labels
= saved_insn_labels
;
1335 case directive_literal_prefix
:
1336 /* Restore the default collection sections from saved state. */
1337 s
= (lit_state
*) state
;
1339 default_lit_sections
= *s
;
1341 /* Free the state storage. */
1342 free (s
->lit_prefix
);
1346 case directive_schedule
:
1347 case directive_freeregs
:
1351 xtensa_set_frag_assembly_state (frag_now
);
1357 demand_empty_rest_of_line ();
1361 /* Place an aligned literal fragment at the current location. */
1364 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1366 md_flush_pending_output ();
1368 if (inside_directive (directive_literal
))
1369 as_warn (_(".literal_position inside literal directive; ignoring"));
1370 xtensa_mark_literal_pool_location ();
1372 demand_empty_rest_of_line ();
1373 xtensa_clear_insn_labels ();
1377 /* Support .literal label, expr, ... */
1380 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1383 char *p
, *base_name
;
1387 if (inside_directive (directive_literal
))
1389 as_bad (_(".literal not allowed inside .begin literal region"));
1390 ignore_rest_of_line ();
1394 md_flush_pending_output ();
1396 /* Previous labels go with whatever follows this directive, not with
1397 the literal, so save them now. */
1398 saved_insn_labels
= insn_labels
;
1401 /* If we are using text-section literals, then this is the right value... */
1404 base_name
= input_line_pointer
;
1406 xtensa_switch_to_literal_fragment (&state
);
1408 /* ...but if we aren't using text-section-literals, then we
1409 need to put them in the section we just switched to. */
1410 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1413 /* All literals are aligned to four-byte boundaries. */
1414 frag_align (2, 0, 0);
1415 record_alignment (now_seg
, 2);
1417 c
= get_symbol_end ();
1418 /* Just after name is now '\0'. */
1419 p
= input_line_pointer
;
1423 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1425 as_bad (_("expected comma or colon after symbol name; "
1426 "rest of line ignored"));
1427 ignore_rest_of_line ();
1428 xtensa_restore_emit_state (&state
);
1436 input_line_pointer
++; /* skip ',' or ':' */
1438 xtensa_elf_cons (4);
1440 xtensa_restore_emit_state (&state
);
1442 /* Restore the list of current labels. */
1443 xtensa_clear_insn_labels ();
1444 insn_labels
= saved_insn_labels
;
1449 xtensa_literal_prefix (void)
1454 /* Parse the new prefix from the input_line_pointer. */
1456 len
= strspn (input_line_pointer
,
1457 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1458 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1460 /* Get a null-terminated copy of the name. */
1461 name
= xmalloc (len
+ 1);
1463 strncpy (name
, input_line_pointer
, len
);
1466 /* Skip the name in the input line. */
1467 input_line_pointer
+= len
;
1469 default_lit_sections
.lit_prefix
= name
;
1471 /* Clear cached literal sections, since the prefix has changed. */
1472 default_lit_sections
.lit_seg
= NULL
;
1473 default_lit_sections
.lit4_seg
= NULL
;
1477 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1480 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1482 float fall_through_f
, target_f
;
1484 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1485 if (fall_through_f
< 0)
1487 as_bad (_("fall through frequency must be greater than 0"));
1488 ignore_rest_of_line ();
1492 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1495 as_bad (_("branch target frequency must be greater than 0"));
1496 ignore_rest_of_line ();
1500 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1502 demand_empty_rest_of_line ();
1506 /* Like normal .long/.short/.word, except support @plt, etc.
1507 Clobbers input_line_pointer, checks end-of-line. */
1510 xtensa_elf_cons (int nbytes
)
1513 bfd_reloc_code_real_type reloc
;
1515 md_flush_pending_output ();
1517 if (cur_vinsn
.inside_bundle
)
1518 as_bad (_("directives are not valid inside bundles"));
1520 if (is_it_end_of_statement ())
1522 demand_empty_rest_of_line ();
1529 if (exp
.X_op
== O_symbol
1530 && *input_line_pointer
== '@'
1531 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1534 reloc_howto_type
*reloc_howto
=
1535 bfd_reloc_type_lookup (stdoutput
, reloc
);
1537 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1538 as_bad (_("unsupported relocation"));
1539 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1540 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1541 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1542 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1543 as_bad (_("opcode-specific %s relocation used outside "
1544 "an instruction"), reloc_howto
->name
);
1545 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1546 as_bad (_("%s relocations do not fit in %d bytes"),
1547 reloc_howto
->name
, nbytes
);
1550 char *p
= frag_more ((int) nbytes
);
1551 xtensa_set_frag_assembly_state (frag_now
);
1552 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1553 nbytes
, &exp
, 0, reloc
);
1557 emit_expr (&exp
, (unsigned int) nbytes
);
1559 while (*input_line_pointer
++ == ',');
1561 input_line_pointer
--; /* Put terminator back into stream. */
1562 demand_empty_rest_of_line ();
1566 /* Parsing and Idiom Translation. */
1568 /* Parse @plt, etc. and return the desired relocation. */
1569 static bfd_reloc_code_real_type
1570 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1577 struct suffix_reloc_map
*ptr
;
1580 return BFD_RELOC_NONE
;
1582 for (ch
= *str
, str2
= ident
;
1583 (str2
< ident
+ sizeof (ident
) - 1
1584 && (ISALNUM (ch
) || ch
== '@'));
1587 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1594 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1595 if (ch
== ptr
->suffix
[0]
1596 && len
== ptr
->length
1597 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1599 /* Now check for "identifier@suffix+constant". */
1600 if (*str
== '-' || *str
== '+')
1602 char *orig_line
= input_line_pointer
;
1603 expressionS new_exp
;
1605 input_line_pointer
= str
;
1606 expression (&new_exp
);
1607 if (new_exp
.X_op
== O_constant
)
1609 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1610 str
= input_line_pointer
;
1613 if (&input_line_pointer
!= str_p
)
1614 input_line_pointer
= orig_line
;
1621 return BFD_RELOC_UNUSED
;
1625 /* Find the matching operator type. */
1626 static unsigned char
1627 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1629 struct suffix_reloc_map
*sfx
;
1630 unsigned char operator = (unsigned char) -1;
1632 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1634 if (sfx
->reloc
== reloc
)
1636 operator = sfx
->operator;
1640 assert (operator != (unsigned char) -1);
1645 /* Find the matching reloc type. */
1646 static bfd_reloc_code_real_type
1647 map_operator_to_reloc (unsigned char operator)
1649 struct suffix_reloc_map
*sfx
;
1650 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1652 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1654 if (sfx
->operator == operator)
1661 if (reloc
== BFD_RELOC_UNUSED
)
1662 return BFD_RELOC_32
;
1669 expression_end (const char *name
)
1692 #define ERROR_REG_NUM ((unsigned) -1)
1695 tc_get_register (const char *prefix
)
1698 const char *next_expr
;
1699 const char *old_line_pointer
;
1702 old_line_pointer
= input_line_pointer
;
1704 if (*input_line_pointer
== '$')
1705 ++input_line_pointer
;
1707 /* Accept "sp" as a synonym for "a1". */
1708 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1709 && expression_end (input_line_pointer
+ 2))
1711 input_line_pointer
+= 2;
1712 return 1; /* AR[1] */
1715 while (*input_line_pointer
++ == *prefix
++)
1717 --input_line_pointer
;
1722 as_bad (_("bad register name: %s"), old_line_pointer
);
1723 return ERROR_REG_NUM
;
1726 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1728 as_bad (_("bad register number: %s"), input_line_pointer
);
1729 return ERROR_REG_NUM
;
1734 while (ISDIGIT ((int) *input_line_pointer
))
1735 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1737 if (!(next_expr
= expression_end (input_line_pointer
)))
1739 as_bad (_("bad register name: %s"), old_line_pointer
);
1740 return ERROR_REG_NUM
;
1743 input_line_pointer
= (char *) next_expr
;
1750 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1752 xtensa_isa isa
= xtensa_default_isa
;
1754 /* Check if this is an immediate operand. */
1755 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1757 bfd_reloc_code_real_type reloc
;
1758 segT t
= expression (tok
);
1759 if (t
== absolute_section
1760 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1762 assert (tok
->X_op
== O_constant
);
1763 tok
->X_op
= O_symbol
;
1764 tok
->X_add_symbol
= &abs_symbol
;
1767 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1768 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1771 if (reloc
== BFD_RELOC_UNUSED
)
1773 as_bad (_("unsupported relocation"));
1777 if (tok
->X_op
== O_constant
)
1781 case BFD_RELOC_LO16
:
1782 tok
->X_add_number
&= 0xffff;
1785 case BFD_RELOC_HI16
:
1786 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1793 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1798 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1799 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1801 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1804 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1805 as_bad (_("register number out of range"));
1808 tok
->X_op
= O_register
;
1809 tok
->X_add_symbol
= 0;
1810 tok
->X_add_number
= reg
;
1815 /* Split up the arguments for an opcode or pseudo-op. */
1818 tokenize_arguments (char **args
, char *str
)
1820 char *old_input_line_pointer
;
1821 bfd_boolean saw_comma
= FALSE
;
1822 bfd_boolean saw_arg
= FALSE
;
1823 bfd_boolean saw_colon
= FALSE
;
1825 char *arg_end
, *arg
;
1828 /* Save and restore input_line_pointer around this function. */
1829 old_input_line_pointer
= input_line_pointer
;
1830 input_line_pointer
= str
;
1832 while (*input_line_pointer
)
1835 switch (*input_line_pointer
)
1842 input_line_pointer
++;
1843 if (saw_comma
|| saw_colon
|| !saw_arg
)
1849 input_line_pointer
++;
1850 if (saw_comma
|| saw_colon
|| !saw_arg
)
1856 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1859 arg_end
= input_line_pointer
+ 1;
1860 while (!expression_end (arg_end
))
1863 arg_len
= arg_end
- input_line_pointer
;
1864 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1865 args
[num_args
] = arg
;
1869 strncpy (arg
, input_line_pointer
, arg_len
);
1870 arg
[arg_len
] = '\0';
1872 input_line_pointer
= arg_end
;
1882 if (saw_comma
|| saw_colon
)
1884 input_line_pointer
= old_input_line_pointer
;
1889 as_bad (_("extra comma"));
1891 as_bad (_("extra colon"));
1893 as_bad (_("missing argument"));
1895 as_bad (_("missing comma or colon"));
1896 input_line_pointer
= old_input_line_pointer
;
1901 /* Parse the arguments to an opcode. Return TRUE on error. */
1904 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1906 expressionS
*tok
, *last_tok
;
1907 xtensa_opcode opcode
= insn
->opcode
;
1908 bfd_boolean had_error
= TRUE
;
1909 xtensa_isa isa
= xtensa_default_isa
;
1910 int n
, num_regs
= 0;
1911 int opcode_operand_count
;
1912 int opnd_cnt
, last_opnd_cnt
;
1913 unsigned int next_reg
= 0;
1914 char *old_input_line_pointer
;
1916 if (insn
->insn_type
== ITYPE_LITERAL
)
1917 opcode_operand_count
= 1;
1919 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1922 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1924 /* Save and restore input_line_pointer around this function. */
1925 old_input_line_pointer
= input_line_pointer
;
1931 /* Skip invisible operands. */
1932 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1938 for (n
= 0; n
< num_args
; n
++)
1940 input_line_pointer
= arg_strings
[n
];
1941 if (*input_line_pointer
== ':')
1943 xtensa_regfile opnd_rf
;
1944 input_line_pointer
++;
1947 assert (opnd_cnt
> 0);
1949 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1951 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1952 as_warn (_("incorrect register number, ignoring"));
1957 if (opnd_cnt
>= opcode_operand_count
)
1959 as_warn (_("too many arguments"));
1962 assert (opnd_cnt
< MAX_INSN_ARGS
);
1964 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1965 next_reg
= tok
->X_add_number
+ 1;
1967 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1969 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1971 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1972 /* minus 1 because we are seeing one right now */
1978 last_opnd_cnt
= opnd_cnt
;
1985 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1989 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1992 insn
->ntok
= tok
- insn
->tok
;
1996 input_line_pointer
= old_input_line_pointer
;
2002 get_invisible_operands (TInsn
*insn
)
2004 xtensa_isa isa
= xtensa_default_isa
;
2005 static xtensa_insnbuf slotbuf
= NULL
;
2007 xtensa_opcode opc
= insn
->opcode
;
2008 int slot
, opnd
, fmt_found
;
2012 slotbuf
= xtensa_insnbuf_alloc (isa
);
2014 /* Find format/slot where this can be encoded. */
2017 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2019 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2021 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2027 if (fmt_found
) break;
2032 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2036 /* First encode all the visible operands
2037 (to deal with shared field operands). */
2038 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2040 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2041 && (insn
->tok
[opnd
].X_op
== O_register
2042 || insn
->tok
[opnd
].X_op
== O_constant
))
2044 val
= insn
->tok
[opnd
].X_add_number
;
2045 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2046 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2050 /* Then pull out the values for the invisible ones. */
2051 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2053 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2055 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2056 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2057 insn
->tok
[opnd
].X_add_number
= val
;
2058 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2059 insn
->tok
[opnd
].X_op
= O_register
;
2061 insn
->tok
[opnd
].X_op
= O_constant
;
2070 xg_reverse_shift_count (char **cnt_argp
)
2072 char *cnt_arg
, *new_arg
;
2073 cnt_arg
= *cnt_argp
;
2075 /* replace the argument with "31-(argument)" */
2076 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2077 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2080 *cnt_argp
= new_arg
;
2084 /* If "arg" is a constant expression, return non-zero with the value
2088 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2091 char *save_ptr
= input_line_pointer
;
2093 input_line_pointer
= arg
;
2095 input_line_pointer
= save_ptr
;
2097 if (exp
.X_op
== O_constant
)
2099 *valp
= exp
.X_add_number
;
2108 xg_replace_opname (char **popname
, char *newop
)
2111 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2112 strcpy (*popname
, newop
);
2117 xg_check_num_args (int *pnum_args
,
2122 int num_args
= *pnum_args
;
2124 if (num_args
< expected_num
)
2126 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2127 num_args
, opname
, expected_num
);
2131 if (num_args
> expected_num
)
2133 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2134 num_args
, opname
, expected_num
);
2135 while (num_args
-- > expected_num
)
2137 free (arg_strings
[num_args
]);
2138 arg_strings
[num_args
] = 0;
2140 *pnum_args
= expected_num
;
2148 /* If the register is not specified as part of the opcode,
2149 then get it from the operand and move it to the opcode. */
2152 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2154 xtensa_isa isa
= xtensa_default_isa
;
2156 char *opname
, *new_opname
;
2157 const char *sr_name
;
2158 int is_user
, is_write
;
2163 is_user
= (opname
[1] == 'u');
2164 is_write
= (opname
[0] == 'w');
2166 /* Opname == [rw]ur or [rwx]sr... */
2168 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2171 /* Check if the argument is a symbolic register name. */
2172 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2173 /* Handle WSR to "INTSET" as a special case. */
2174 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2175 && !strcasecmp (arg_strings
[1], "intset"))
2176 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2177 if (sr
== XTENSA_UNDEFINED
2178 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2180 /* Maybe it's a register number.... */
2182 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2184 as_bad (_("invalid register '%s' for '%s' instruction"),
2185 arg_strings
[1], opname
);
2188 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2189 if (sr
== XTENSA_UNDEFINED
)
2191 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2192 (long) val
, opname
);
2197 /* Remove the last argument, which is now part of the opcode. */
2198 free (arg_strings
[1]);
2202 /* Translate the opcode. */
2203 sr_name
= xtensa_sysreg_name (isa
, sr
);
2204 /* Another special case for "WSR.INTSET".... */
2205 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2207 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2208 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2210 *popname
= new_opname
;
2217 xtensa_translate_old_userreg_ops (char **popname
)
2219 xtensa_isa isa
= xtensa_default_isa
;
2221 char *opname
, *new_opname
;
2222 const char *sr_name
;
2223 bfd_boolean has_underbar
= FALSE
;
2226 if (opname
[0] == '_')
2228 has_underbar
= TRUE
;
2232 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2233 if (sr
!= XTENSA_UNDEFINED
)
2235 /* The new default name ("nnn") is different from the old default
2236 name ("URnnn"). The old default is handled below, and we don't
2237 want to recognize [RW]nnn, so do nothing if the name is the (new)
2239 static char namebuf
[10];
2240 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2241 if (strcmp (namebuf
, opname
+ 1) == 0)
2249 /* Only continue if the reg name is "URnnn". */
2250 if (opname
[1] != 'u' || opname
[2] != 'r')
2252 val
= strtoul (opname
+ 3, &end
, 10);
2256 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2257 if (sr
== XTENSA_UNDEFINED
)
2259 as_bad (_("invalid register number (%ld) for '%s'"),
2260 (long) val
, opname
);
2265 /* Translate the opcode. */
2266 sr_name
= xtensa_sysreg_name (isa
, sr
);
2267 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2268 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2269 opname
[0], sr_name
);
2271 *popname
= new_opname
;
2278 xtensa_translate_zero_immed (char *old_op
,
2288 assert (opname
[0] != '_');
2290 if (strcmp (opname
, old_op
) != 0)
2293 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2295 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2297 xg_replace_opname (popname
, new_op
);
2298 free (arg_strings
[1]);
2299 arg_strings
[1] = arg_strings
[2];
2308 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2309 Returns non-zero if an error was found. */
2312 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2314 char *opname
= *popname
;
2315 bfd_boolean has_underbar
= FALSE
;
2319 has_underbar
= TRUE
;
2323 if (strcmp (opname
, "mov") == 0)
2325 if (use_transform () && !has_underbar
&& density_supported
)
2326 xg_replace_opname (popname
, "mov.n");
2329 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2331 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2332 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2333 strcpy (arg_strings
[2], arg_strings
[1]);
2339 if (strcmp (opname
, "bbsi.l") == 0)
2341 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2343 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2344 if (target_big_endian
)
2345 xg_reverse_shift_count (&arg_strings
[1]);
2349 if (strcmp (opname
, "bbci.l") == 0)
2351 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2353 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2354 if (target_big_endian
)
2355 xg_reverse_shift_count (&arg_strings
[1]);
2359 /* Don't do anything special with NOPs inside FLIX instructions. They
2360 are handled elsewhere. Real NOP instructions are always available
2361 in configurations with FLIX, so this should never be an issue but
2362 check for it anyway. */
2363 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2364 && strcmp (opname
, "nop") == 0)
2366 if (use_transform () && !has_underbar
&& density_supported
)
2367 xg_replace_opname (popname
, "nop.n");
2370 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2372 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2373 arg_strings
[0] = (char *) xmalloc (3);
2374 arg_strings
[1] = (char *) xmalloc (3);
2375 arg_strings
[2] = (char *) xmalloc (3);
2376 strcpy (arg_strings
[0], "a1");
2377 strcpy (arg_strings
[1], "a1");
2378 strcpy (arg_strings
[2], "a1");
2384 /* Recognize [RW]UR and [RWX]SR. */
2385 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2386 && (opname
[1] == 'u' || opname
[1] == 's'))
2387 || (opname
[0] == 'x' && opname
[1] == 's'))
2389 && opname
[3] == '\0')
2390 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2392 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2393 [RW]<name> if <name> is the non-default name of a user register. */
2394 if ((opname
[0] == 'r' || opname
[0] == 'w')
2395 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2396 return xtensa_translate_old_userreg_ops (popname
);
2398 /* Relax branches that don't allow comparisons against an immediate value
2399 of zero to the corresponding branches with implicit zero immediates. */
2400 if (!has_underbar
&& use_transform ())
2402 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2403 pnum_args
, arg_strings
))
2406 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2407 pnum_args
, arg_strings
))
2410 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2411 pnum_args
, arg_strings
))
2414 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2415 pnum_args
, arg_strings
))
2423 /* Functions for dealing with the Xtensa ISA. */
2425 /* Currently the assembler only allows us to use a single target per
2426 fragment. Because of this, only one operand for a given
2427 instruction may be symbolic. If there is a PC-relative operand,
2428 the last one is chosen. Otherwise, the result is the number of the
2429 last immediate operand, and if there are none of those, we fail and
2433 get_relaxable_immed (xtensa_opcode opcode
)
2435 int last_immed
= -1;
2438 if (opcode
== XTENSA_UNDEFINED
)
2441 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2442 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2444 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2446 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2448 if (last_immed
== -1
2449 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2456 static xtensa_opcode
2457 get_opcode_from_buf (const char *buf
, int slot
)
2459 static xtensa_insnbuf insnbuf
= NULL
;
2460 static xtensa_insnbuf slotbuf
= NULL
;
2461 xtensa_isa isa
= xtensa_default_isa
;
2466 insnbuf
= xtensa_insnbuf_alloc (isa
);
2467 slotbuf
= xtensa_insnbuf_alloc (isa
);
2470 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2471 fmt
= xtensa_format_decode (isa
, insnbuf
);
2472 if (fmt
== XTENSA_UNDEFINED
)
2473 return XTENSA_UNDEFINED
;
2475 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2476 return XTENSA_UNDEFINED
;
2478 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2479 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2483 #ifdef TENSILICA_DEBUG
2485 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2488 xtensa_print_insn_table (void)
2490 int num_opcodes
, num_operands
;
2491 xtensa_opcode opcode
;
2492 xtensa_isa isa
= xtensa_default_isa
;
2494 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2495 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2498 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2499 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2500 for (opn
= 0; opn
< num_operands
; opn
++)
2502 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2504 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2506 xtensa_regfile opnd_rf
=
2507 xtensa_operand_regfile (isa
, opcode
, opn
);
2508 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2510 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2511 fputs ("[lLr] ", stderr
);
2513 fputs ("i ", stderr
);
2515 fprintf (stderr
, "\n");
2521 print_vliw_insn (xtensa_insnbuf vbuf
)
2523 xtensa_isa isa
= xtensa_default_isa
;
2524 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2525 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2528 fprintf (stderr
, "format = %d\n", f
);
2530 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2532 xtensa_opcode opcode
;
2536 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2537 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2538 opname
= xtensa_opcode_name (isa
, opcode
);
2540 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2541 fprintf (stderr
, " operands = ");
2543 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2547 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2549 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2550 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2551 fprintf (stderr
, "%d ", val
);
2553 fprintf (stderr
, "\n");
2555 xtensa_insnbuf_free (isa
, sbuf
);
2558 #endif /* TENSILICA_DEBUG */
2562 is_direct_call_opcode (xtensa_opcode opcode
)
2564 xtensa_isa isa
= xtensa_default_isa
;
2565 int n
, num_operands
;
2567 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2570 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2571 for (n
= 0; n
< num_operands
; n
++)
2573 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2574 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2581 /* Convert from BFD relocation type code to slot and operand number.
2582 Returns non-zero on failure. */
2585 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2587 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2588 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2590 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2593 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2594 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2596 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2606 /* Convert from slot number to BFD relocation type code for the
2607 standard PC-relative relocations. Return BFD_RELOC_NONE on
2610 static bfd_reloc_code_real_type
2611 encode_reloc (int slot
)
2613 if (slot
< 0 || slot
> 14)
2614 return BFD_RELOC_NONE
;
2616 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2620 /* Convert from slot numbers to BFD relocation type code for the
2621 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2623 static bfd_reloc_code_real_type
2624 encode_alt_reloc (int slot
)
2626 if (slot
< 0 || slot
> 14)
2627 return BFD_RELOC_NONE
;
2629 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2634 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2637 xtensa_opcode opcode
,
2643 uint32 valbuf
= value
;
2645 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2647 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2649 as_bad_where ((char *) file
, line
,
2650 _("operand %d of '%s' has out of range value '%u'"),
2652 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2655 as_bad_where ((char *) file
, line
,
2656 _("operand %d of '%s' has invalid value '%u'"),
2658 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2663 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2669 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2672 xtensa_opcode opcode
,
2676 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2677 fmt
, slot
, slotbuf
, &val
);
2678 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2683 /* Checks for rules from xtensa-relax tables. */
2685 /* The routine xg_instruction_matches_option_term must return TRUE
2686 when a given option term is true. The meaning of all of the option
2687 terms is given interpretation by this function. This is needed when
2688 an option depends on the state of a directive, but there are no such
2689 options in use right now. */
2692 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2693 const ReqOrOption
*option
)
2695 if (strcmp (option
->option_name
, "realnop") == 0
2696 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2698 /* These conditions were evaluated statically when building the
2699 relaxation table. There's no need to reevaluate them now. */
2704 as_fatal (_("internal error: unknown option name '%s'"),
2705 option
->option_name
);
2711 xg_instruction_matches_or_options (TInsn
*insn
,
2712 const ReqOrOptionList
*or_option
)
2714 const ReqOrOption
*option
;
2715 /* Must match each of the AND terms. */
2716 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2718 if (xg_instruction_matches_option_term (insn
, option
))
2726 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2728 const ReqOption
*req_options
;
2729 /* Must match each of the AND terms. */
2730 for (req_options
= options
;
2731 req_options
!= NULL
;
2732 req_options
= req_options
->next
)
2734 /* Must match one of the OR clauses. */
2735 if (!xg_instruction_matches_or_options (insn
,
2736 req_options
->or_option_terms
))
2743 /* Return the transition rule that matches or NULL if none matches. */
2746 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2748 PreconditionList
*condition_l
;
2750 if (rule
->opcode
!= insn
->opcode
)
2753 for (condition_l
= rule
->conditions
;
2754 condition_l
!= NULL
;
2755 condition_l
= condition_l
->next
)
2759 Precondition
*cond
= condition_l
->precond
;
2764 /* The expression must be the constant. */
2765 assert (cond
->op_num
< insn
->ntok
);
2766 exp1
= &insn
->tok
[cond
->op_num
];
2767 if (expr_is_const (exp1
))
2772 if (get_expr_const (exp1
) != cond
->op_data
)
2776 if (get_expr_const (exp1
) == cond
->op_data
)
2783 else if (expr_is_register (exp1
))
2788 if (get_expr_register (exp1
) != cond
->op_data
)
2792 if (get_expr_register (exp1
) == cond
->op_data
)
2804 assert (cond
->op_num
< insn
->ntok
);
2805 assert (cond
->op_data
< insn
->ntok
);
2806 exp1
= &insn
->tok
[cond
->op_num
];
2807 exp2
= &insn
->tok
[cond
->op_data
];
2812 if (!expr_is_equal (exp1
, exp2
))
2816 if (expr_is_equal (exp1
, exp2
))
2828 if (!xg_instruction_matches_options (insn
, rule
->options
))
2836 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2838 bfd_boolean a_greater
= FALSE
;
2839 bfd_boolean b_greater
= FALSE
;
2841 ReqOptionList
*l_a
= a
->options
;
2842 ReqOptionList
*l_b
= b
->options
;
2844 /* We only care if they both are the same except for
2845 a const16 vs. an l32r. */
2847 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2849 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2850 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2851 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2853 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2855 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2857 /* This is the case we care about. */
2858 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2859 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2866 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2867 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2877 l_or_a
= l_or_a
->next
;
2878 l_or_b
= l_or_b
->next
;
2880 if (l_or_a
|| l_or_b
)
2889 /* Incomparable if the substitution was used differently in two cases. */
2890 if (a_greater
&& b_greater
)
2902 static TransitionRule
*
2903 xg_instruction_match (TInsn
*insn
)
2905 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2907 assert (insn
->opcode
< table
->num_opcodes
);
2909 /* Walk through all of the possible transitions. */
2910 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2912 TransitionRule
*rule
= l
->rule
;
2913 if (xg_instruction_matches_rule (insn
, rule
))
2920 /* Various Other Internal Functions. */
2923 is_unique_insn_expansion (TransitionRule
*r
)
2925 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2927 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2933 /* Check if there is exactly one relaxation for INSN that converts it to
2934 another instruction of equal or larger size. If so, and if TARG is
2935 non-null, go ahead and generate the relaxed instruction into TARG. If
2936 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2937 instruction, i.e., ignore relaxations that convert to an instruction of
2938 equal size. In some contexts where this function is used, only
2939 a single widening is allowed and the NARROW_ONLY argument is used to
2940 exclude cases like ADDI being "widened" to an ADDMI, which may
2941 later be relaxed to an ADDMI/ADDI pair. */
2944 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2946 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2948 TransitionRule
*match
= 0;
2950 assert (insn
->insn_type
== ITYPE_INSN
);
2951 assert (insn
->opcode
< table
->num_opcodes
);
2953 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2955 TransitionRule
*rule
= l
->rule
;
2957 if (xg_instruction_matches_rule (insn
, rule
)
2958 && is_unique_insn_expansion (rule
)
2959 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2960 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2971 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2976 /* Return the maximum number of bytes this opcode can expand to. */
2979 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2981 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2983 int max_size
= xg_get_single_size (opcode
);
2985 assert (opcode
< table
->num_opcodes
);
2987 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2989 TransitionRule
*rule
= l
->rule
;
2990 BuildInstr
*build_list
;
2995 build_list
= rule
->to_instr
;
2996 if (is_unique_insn_expansion (rule
))
2998 assert (build_list
->typ
== INSTR_INSTR
);
2999 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3002 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3004 switch (build_list
->typ
)
3007 this_size
+= xg_get_single_size (build_list
->opcode
);
3009 case INSTR_LITERAL_DEF
:
3010 case INSTR_LABEL_DEF
:
3015 if (this_size
> max_size
)
3016 max_size
= this_size
;
3022 /* Return the maximum number of literal bytes this opcode can generate. */
3025 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3027 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3031 assert (opcode
< table
->num_opcodes
);
3033 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3035 TransitionRule
*rule
= l
->rule
;
3036 BuildInstr
*build_list
;
3041 build_list
= rule
->to_instr
;
3042 if (is_unique_insn_expansion (rule
))
3044 assert (build_list
->typ
== INSTR_INSTR
);
3045 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3048 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3050 switch (build_list
->typ
)
3052 case INSTR_LITERAL_DEF
:
3053 /* Hard-coded 4-byte literal. */
3057 case INSTR_LABEL_DEF
:
3062 if (this_size
> max_size
)
3063 max_size
= this_size
;
3070 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3072 int steps_taken
= 0;
3073 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3076 assert (insn
->insn_type
== ITYPE_INSN
);
3077 assert (insn
->opcode
< table
->num_opcodes
);
3079 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3081 TransitionRule
*rule
= l
->rule
;
3083 if (xg_instruction_matches_rule (insn
, rule
))
3085 if (steps_taken
== lateral_steps
)
3095 get_special_literal_symbol (void)
3097 static symbolS
*sym
= NULL
;
3100 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3106 get_special_label_symbol (void)
3108 static symbolS
*sym
= NULL
;
3111 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3117 xg_valid_literal_expression (const expressionS
*exp
)
3134 /* This will check to see if the value can be converted into the
3135 operand type. It will return TRUE if it does not fit. */
3138 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3140 uint32 valbuf
= value
;
3141 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3147 /* Assumes: All immeds are constants. Check that all constants fit
3148 into their immeds; return FALSE if not. */
3151 xg_immeds_fit (const TInsn
*insn
)
3153 xtensa_isa isa
= xtensa_default_isa
;
3157 assert (insn
->insn_type
== ITYPE_INSN
);
3158 for (i
= 0; i
< n
; ++i
)
3160 const expressionS
*expr
= &insn
->tok
[i
];
3161 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3168 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3173 /* The symbol should have a fixup associated with it. */
3182 /* This should only be called after we have an initial
3183 estimate of the addresses. */
3186 xg_symbolic_immeds_fit (const TInsn
*insn
,
3192 xtensa_isa isa
= xtensa_default_isa
;
3200 assert (insn
->insn_type
== ITYPE_INSN
);
3202 for (i
= 0; i
< n
; ++i
)
3204 const expressionS
*expr
= &insn
->tok
[i
];
3205 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3212 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3218 /* Check for the worst case. */
3219 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3224 /* We only allow symbols for PC-relative references.
3225 If pc_frag == 0, then we don't have frag locations yet. */
3227 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3230 /* If it is a weak symbol, then assume it won't reach. */
3231 if (S_IS_WEAK (expr
->X_add_symbol
))
3234 if (is_direct_call_opcode (insn
->opcode
)
3235 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3237 /* If callee is undefined or in a different segment, be
3238 optimistic and assume it will be in range. */
3239 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3243 /* Only references within a segment can be known to fit in the
3244 operands at assembly time. */
3245 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3248 symbolP
= expr
->X_add_symbol
;
3249 sym_frag
= symbol_get_frag (symbolP
);
3250 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3251 pc
= pc_frag
->fr_address
+ pc_offset
;
3253 /* If frag has yet to be reached on this pass, assume it
3254 will move by STRETCH just as we did. If this is not so,
3255 it will be because some frag between grows, and that will
3256 force another pass. Beware zero-length frags. There
3257 should be a faster way to do this. */
3260 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3261 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3266 new_offset
= target
;
3267 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3268 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3273 /* The symbol should have a fixup associated with it. */
3282 /* Return TRUE on success. */
3285 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3291 targ
->debug_line
= insn
->debug_line
;
3292 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3297 targ
->opcode
= bi
->opcode
;
3298 targ
->insn_type
= ITYPE_INSN
;
3299 targ
->is_specific_opcode
= FALSE
;
3301 for (; op
!= NULL
; op
= op
->next
)
3303 int op_num
= op
->op_num
;
3304 int op_data
= op
->op_data
;
3306 assert (op
->op_num
< MAX_INSN_ARGS
);
3308 if (targ
->ntok
<= op_num
)
3309 targ
->ntok
= op_num
+ 1;
3314 set_expr_const (&targ
->tok
[op_num
], op_data
);
3317 assert (op_data
< insn
->ntok
);
3318 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3321 sym
= get_special_literal_symbol ();
3322 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3325 sym
= get_special_label_symbol ();
3326 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3328 case OP_OPERAND_HI16U
:
3329 case OP_OPERAND_LOW16U
:
3330 assert (op_data
< insn
->ntok
);
3331 if (expr_is_const (&insn
->tok
[op_data
]))
3334 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3335 val
= xg_apply_userdef_op_fn (op
->typ
,
3338 targ
->tok
[op_num
].X_add_number
= val
;
3342 /* For const16 we can create relocations for these. */
3343 if (targ
->opcode
== XTENSA_UNDEFINED
3344 || (targ
->opcode
!= xtensa_const16_opcode
))
3346 assert (op_data
< insn
->ntok
);
3347 /* Need to build a O_lo16 or O_hi16. */
3348 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3349 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3351 if (op
->typ
== OP_OPERAND_HI16U
)
3352 targ
->tok
[op_num
].X_op
= O_hi16
;
3353 else if (op
->typ
== OP_OPERAND_LOW16U
)
3354 targ
->tok
[op_num
].X_op
= O_lo16
;
3361 /* currently handles:
3364 OP_OPERAND_F32MINUS */
3365 if (xg_has_userdef_op_fn (op
->typ
))
3367 assert (op_data
< insn
->ntok
);
3368 if (expr_is_const (&insn
->tok
[op_data
]))
3371 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3372 val
= xg_apply_userdef_op_fn (op
->typ
,
3375 targ
->tok
[op_num
].X_add_number
= val
;
3378 return FALSE
; /* We cannot use a relocation for this. */
3387 case INSTR_LITERAL_DEF
:
3389 targ
->opcode
= XTENSA_UNDEFINED
;
3390 targ
->insn_type
= ITYPE_LITERAL
;
3391 targ
->is_specific_opcode
= FALSE
;
3392 for (; op
!= NULL
; op
= op
->next
)
3394 int op_num
= op
->op_num
;
3395 int op_data
= op
->op_data
;
3396 assert (op
->op_num
< MAX_INSN_ARGS
);
3398 if (targ
->ntok
<= op_num
)
3399 targ
->ntok
= op_num
+ 1;
3404 assert (op_data
< insn
->ntok
);
3405 /* We can only pass resolvable literals through. */
3406 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3408 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3420 case INSTR_LABEL_DEF
:
3422 targ
->opcode
= XTENSA_UNDEFINED
;
3423 targ
->insn_type
= ITYPE_LABEL
;
3424 targ
->is_specific_opcode
= FALSE
;
3425 /* Literal with no ops is a label? */
3426 assert (op
== NULL
);
3437 /* Return TRUE on success. */
3440 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3442 for (; bi
!= NULL
; bi
= bi
->next
)
3444 TInsn
*next_insn
= istack_push_space (istack
);
3446 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3453 /* Return TRUE on valid expansion. */
3456 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3458 int stack_size
= istack
->ninsn
;
3459 int steps_taken
= 0;
3460 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3463 assert (insn
->insn_type
== ITYPE_INSN
);
3464 assert (insn
->opcode
< table
->num_opcodes
);
3466 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3468 TransitionRule
*rule
= l
->rule
;
3470 if (xg_instruction_matches_rule (insn
, rule
))
3472 if (lateral_steps
== steps_taken
)
3476 /* This is it. Expand the rule to the stack. */
3477 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3480 /* Check to see if it fits. */
3481 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3483 TInsn
*insn
= &istack
->insn
[i
];
3485 if (insn
->insn_type
== ITYPE_INSN
3486 && !tinsn_has_symbolic_operands (insn
)
3487 && !xg_immeds_fit (insn
))
3489 istack
->ninsn
= stack_size
;
3502 /* Relax the assembly instruction at least "min_steps".
3503 Return the number of steps taken.
3505 For relaxation to correctly terminate, every relaxation chain must
3506 terminate in one of two ways:
3508 1. If the chain from one instruction to the next consists entirely of
3509 single instructions, then the chain *must* handle all possible
3510 immediates without failing. It must not ever fail because an
3511 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3512 chain is one example. L32R loads 32 bits, and there cannot be an
3513 immediate larger than 32 bits, so it satisfies this condition.
3514 Single instruction relaxation chains are as defined by
3515 xg_is_single_relaxable_instruction.
3517 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3518 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3520 Strictly speaking, in most cases you can violate condition 1 and be OK
3521 -- in particular when the last two instructions have the same single
3522 size. But nevertheless, you should guarantee the above two conditions.
3524 We could fix this so that single-instruction expansions correctly
3525 terminate when they can't handle the range, but the error messages are
3526 worse, and it actually turns out that in every case but one (18-bit wide
3527 branches), you need a multi-instruction expansion to get the full range
3528 anyway. And because 18-bit branches are handled identically to 15-bit
3529 branches, there isn't any point in changing it. */
3532 xg_assembly_relax (IStack
*istack
,
3535 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3536 offsetT pc_offset
, /* offset in fragment */
3537 int min_steps
, /* minimum conversion steps */
3538 long stretch
) /* number of bytes stretched so far */
3540 int steps_taken
= 0;
3542 /* Some of its immeds don't fit. Try to build a relaxed version.
3543 This may go through a couple of stages of single instruction
3544 transformations before we get there. */
3546 TInsn single_target
;
3548 int lateral_steps
= 0;
3549 int istack_size
= istack
->ninsn
;
3551 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3552 && steps_taken
>= min_steps
)
3554 istack_push (istack
, insn
);
3557 current_insn
= *insn
;
3559 /* Walk through all of the single instruction expansions. */
3560 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3563 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3566 if (steps_taken
>= min_steps
)
3568 istack_push (istack
, &single_target
);
3572 current_insn
= single_target
;
3575 /* Now check for a multi-instruction expansion. */
3576 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3578 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3581 if (steps_taken
>= min_steps
)
3583 istack_push (istack
, ¤t_insn
);
3588 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3590 if (steps_taken
>= min_steps
)
3594 istack
->ninsn
= istack_size
;
3597 /* It's not going to work -- use the original. */
3598 istack_push (istack
, insn
);
3604 xg_finish_frag (char *last_insn
,
3605 enum xtensa_relax_statesE frag_state
,
3606 enum xtensa_relax_statesE slot0_state
,
3608 bfd_boolean is_insn
)
3610 /* Finish off this fragment so that it has at LEAST the desired
3611 max_growth. If it doesn't fit in this fragment, close this one
3612 and start a new one. In either case, return a pointer to the
3613 beginning of the growth area. */
3617 frag_grow (max_growth
);
3618 old_frag
= frag_now
;
3620 frag_now
->fr_opcode
= last_insn
;
3622 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3624 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3625 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3627 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3628 xtensa_set_frag_assembly_state (frag_now
);
3630 /* Just to make sure that we did not split it up. */
3631 assert (old_frag
->fr_next
== frag_now
);
3635 /* Return TRUE if the target frag is one of the next non-empty frags. */
3638 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3643 for (; fragP
; fragP
= fragP
->fr_next
)
3645 if (fragP
== target
)
3647 if (fragP
->fr_fix
!= 0)
3649 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3651 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3652 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3654 if (fragP
->fr_type
== rs_space
)
3662 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3664 xtensa_isa isa
= xtensa_default_isa
;
3666 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3671 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3672 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3675 for (i
= 0; i
< num_ops
; i
++)
3677 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3683 if (target_op
== -1)
3686 if (insn
->ntok
<= target_op
)
3689 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3692 sym
= insn
->tok
[target_op
].X_add_symbol
;
3696 if (insn
->tok
[target_op
].X_add_number
!= 0)
3699 target_frag
= symbol_get_frag (sym
);
3700 if (target_frag
== NULL
)
3703 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3704 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3712 xg_add_branch_and_loop_targets (TInsn
*insn
)
3714 xtensa_isa isa
= xtensa_default_isa
;
3715 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3717 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3720 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3721 && insn
->tok
[i
].X_op
== O_symbol
)
3722 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3726 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3727 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3731 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3733 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3734 && insn
->tok
[i
].X_op
== O_symbol
)
3736 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3737 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3738 if (S_IS_DEFINED (sym
))
3739 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3746 /* Return FALSE if no error. */
3749 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3754 switch (instr_spec
->typ
)
3757 new_insn
->insn_type
= ITYPE_INSN
;
3758 new_insn
->opcode
= instr_spec
->opcode
;
3760 case INSTR_LITERAL_DEF
:
3761 new_insn
->insn_type
= ITYPE_LITERAL
;
3762 new_insn
->opcode
= XTENSA_UNDEFINED
;
3764 case INSTR_LABEL_DEF
:
3767 new_insn
->is_specific_opcode
= FALSE
;
3768 new_insn
->debug_line
= old_insn
->debug_line
;
3769 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3771 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3774 const expressionS
*src_exp
;
3780 /* The expression must be the constant. */
3781 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3782 exp
= &new_insn
->tok
[b_op
->op_num
];
3783 set_expr_const (exp
, b_op
->op_data
);
3787 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3788 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3789 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3790 exp
= &new_insn
->tok
[b_op
->op_num
];
3791 copy_expr (exp
, src_exp
);
3796 as_bad (_("can't handle generation of literal/labels yet"));
3800 as_bad (_("can't handle undefined OP TYPE"));
3805 new_insn
->ntok
= num_ops
;
3810 /* Return TRUE if it was simplified. */
3813 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3815 TransitionRule
*rule
;
3816 BuildInstr
*insn_spec
;
3818 if (old_insn
->is_specific_opcode
|| !density_supported
)
3821 rule
= xg_instruction_match (old_insn
);
3825 insn_spec
= rule
->to_instr
;
3826 /* There should only be one. */
3827 assert (insn_spec
!= NULL
);
3828 assert (insn_spec
->next
== NULL
);
3829 if (insn_spec
->next
!= NULL
)
3832 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3838 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3839 l32i.n. (2) Check the number of operands. (3) Place the instruction
3840 tokens into the stack or relax it and place multiple
3841 instructions/literals onto the stack. Return FALSE if no error. */
3844 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3848 bfd_boolean do_expand
;
3850 tinsn_init (&new_insn
);
3852 /* Narrow it if we can. xg_simplify_insn now does all the
3853 appropriate checking (e.g., for the density option). */
3854 if (xg_simplify_insn (orig_insn
, &new_insn
))
3855 orig_insn
= &new_insn
;
3857 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3859 if (orig_insn
->ntok
< noperands
)
3861 as_bad (_("found %d operands for '%s': Expected %d"),
3863 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3867 if (orig_insn
->ntok
> noperands
)
3868 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3870 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3873 /* If there are not enough operands, we will assert above. If there
3874 are too many, just cut out the extras here. */
3875 orig_insn
->ntok
= noperands
;
3877 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3880 /* Special case for extui opcode which has constraints not handled
3881 by the ordinary operand encoding checks. The number of operands
3882 and related syntax issues have already been checked. */
3883 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3885 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3886 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3887 if (shiftimm
+ maskimm
> 32)
3889 as_bad (_("immediate operands sum to greater than 32"));
3894 /* If the instruction will definitely need to be relaxed, it is better
3895 to expand it now for better scheduling. Decide whether to expand
3897 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3899 /* Calls should be expanded to longcalls only in the backend relaxation
3900 so that the assembly scheduler will keep the L32R/CALLX instructions
3902 if (is_direct_call_opcode (orig_insn
->opcode
))
3905 if (tinsn_has_symbolic_operands (orig_insn
))
3907 /* The values of symbolic operands are not known yet, so only expand
3908 now if an operand is "complex" (e.g., difference of symbols) and
3909 will have to be stored as a literal regardless of the value. */
3910 if (!tinsn_has_complex_operands (orig_insn
))
3913 else if (xg_immeds_fit (orig_insn
))
3917 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3919 istack_push (istack
, orig_insn
);
3925 /* Return TRUE if the section flags are marked linkonce
3926 or the name is .gnu.linkonce.*. */
3928 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3931 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3933 flagword flags
, link_once_flags
;
3935 flags
= bfd_get_section_flags (abfd
, sec
);
3936 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3938 /* Flags might not be set yet. */
3939 if (!link_once_flags
3940 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3941 link_once_flags
= SEC_LINK_ONCE
;
3943 return (link_once_flags
!= 0);
3948 xtensa_add_literal_sym (symbolS
*sym
)
3952 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3954 l
->next
= literal_syms
;
3960 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3962 static int lit_num
= 0;
3963 static char name
[256];
3966 sprintf (name
, ".L_lit_sym%d", lit_num
);
3968 /* Create a local symbol. If it is in a linkonce section, we have to
3969 be careful to make sure that if it is used in a relocation that the
3970 symbol will be in the output file. */
3971 if (get_is_linkonce_section (stdoutput
, sec
))
3973 symbolP
= symbol_new (name
, sec
, 0, frag
);
3974 S_CLEAR_EXTERNAL (symbolP
);
3975 /* symbolP->local = 1; */
3978 symbolP
= symbol_new (name
, sec
, 0, frag
);
3980 xtensa_add_literal_sym (symbolP
);
3987 /* Currently all literals that are generated here are 32-bit L32R targets. */
3990 xg_assemble_literal (/* const */ TInsn
*insn
)
3993 symbolS
*lit_sym
= NULL
;
3994 bfd_reloc_code_real_type reloc
;
3997 /* size = 4 for L32R. It could easily be larger when we move to
3998 larger constants. Add a parameter later. */
3999 offsetT litsize
= 4;
4000 offsetT litalign
= 2; /* 2^2 = 4 */
4001 expressionS saved_loc
;
4002 expressionS
* emit_val
;
4004 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4006 assert (insn
->insn_type
== ITYPE_LITERAL
);
4007 assert (insn
->ntok
== 1); /* must be only one token here */
4009 xtensa_switch_to_literal_fragment (&state
);
4011 emit_val
= &insn
->tok
[0];
4012 if (emit_val
->X_op
== O_big
)
4014 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4017 /* This happens when someone writes a "movi a2, big_number". */
4018 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4019 _("invalid immediate"));
4020 xtensa_restore_emit_state (&state
);
4025 /* Force a 4-byte align here. Note that this opens a new frag, so all
4026 literals done with this function have a frag to themselves. That's
4027 important for the way text section literals work. */
4028 frag_align (litalign
, 0, 0);
4029 record_alignment (now_seg
, litalign
);
4031 switch (emit_val
->X_op
)
4034 p
= frag_more (litsize
);
4035 xtensa_set_frag_assembly_state (frag_now
);
4036 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4037 if (emit_val
->X_add_symbol
)
4038 emit_val
->X_op
= O_symbol
;
4040 emit_val
->X_op
= O_constant
;
4041 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4042 litsize
, emit_val
, 0, reloc
);
4046 emit_expr (emit_val
, litsize
);
4050 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4051 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4052 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4053 lit_sym
= frag_now
->fr_symbol
;
4056 xtensa_restore_emit_state (&state
);
4062 xg_assemble_literal_space (/* const */ int size
, int slot
)
4065 /* We might have to do something about this alignment. It only
4066 takes effect if something is placed here. */
4067 offsetT litalign
= 2; /* 2^2 = 4 */
4068 fragS
*lit_saved_frag
;
4070 assert (size
% 4 == 0);
4072 xtensa_switch_to_literal_fragment (&state
);
4074 /* Force a 4-byte align here. */
4075 frag_align (litalign
, 0, 0);
4076 record_alignment (now_seg
, litalign
);
4080 lit_saved_frag
= frag_now
;
4081 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4082 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4083 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4086 xtensa_restore_emit_state (&state
);
4087 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4091 /* Put in a fixup record based on the opcode.
4092 Return TRUE on success. */
4095 xg_add_opcode_fix (TInsn
*tinsn
,
4103 xtensa_opcode opcode
= tinsn
->opcode
;
4104 bfd_reloc_code_real_type reloc
;
4105 reloc_howto_type
*howto
;
4109 reloc
= BFD_RELOC_NONE
;
4111 /* First try the special cases for "alternate" relocs. */
4112 if (opcode
== xtensa_l32r_opcode
)
4114 if (fragP
->tc_frag_data
.use_absolute_literals
)
4115 reloc
= encode_alt_reloc (slot
);
4117 else if (opcode
== xtensa_const16_opcode
)
4119 if (expr
->X_op
== O_lo16
)
4121 reloc
= encode_reloc (slot
);
4122 expr
->X_op
= O_symbol
;
4124 else if (expr
->X_op
== O_hi16
)
4126 reloc
= encode_alt_reloc (slot
);
4127 expr
->X_op
= O_symbol
;
4131 if (opnum
!= get_relaxable_immed (opcode
))
4133 as_bad (_("invalid relocation for operand %i of '%s'"),
4134 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4138 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4139 into the symbol table where the generic portions of the assembler
4140 won't know what to do with them. */
4141 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4143 as_bad (_("invalid expression for operand %i of '%s'"),
4144 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4148 /* Next try the generic relocs. */
4149 if (reloc
== BFD_RELOC_NONE
)
4150 reloc
= encode_reloc (slot
);
4151 if (reloc
== BFD_RELOC_NONE
)
4153 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4157 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4160 as_bad (_("undefined symbol for opcode \"%s\""),
4161 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4165 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4166 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4167 howto
->pc_relative
, reloc
);
4168 the_fix
->fx_no_overflow
= 1;
4169 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4170 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4171 the_fix
->tc_fix_data
.slot
= slot
;
4178 xg_emit_insn_to_buf (TInsn
*tinsn
,
4182 bfd_boolean build_fix
)
4184 static xtensa_insnbuf insnbuf
= NULL
;
4185 bfd_boolean has_symbolic_immed
= FALSE
;
4186 bfd_boolean ok
= TRUE
;
4189 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4191 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4192 if (has_symbolic_immed
&& build_fix
)
4195 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4196 int slot
= xg_get_single_slot (tinsn
->opcode
);
4197 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4198 expressionS
*exp
= &tinsn
->tok
[opnum
];
4200 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4203 fragP
->tc_frag_data
.is_insn
= TRUE
;
4204 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4205 (unsigned char *) buf
, 0);
4211 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4213 symbolS
*sym
= get_special_literal_symbol ();
4217 assert (insn
->insn_type
== ITYPE_INSN
);
4218 for (i
= 0; i
< insn
->ntok
; i
++)
4219 if (insn
->tok
[i
].X_add_symbol
== sym
)
4220 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4226 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4228 symbolS
*sym
= get_special_label_symbol ();
4230 for (i
= 0; i
< insn
->ntok
; i
++)
4231 if (insn
->tok
[i
].X_add_symbol
== sym
)
4232 insn
->tok
[i
].X_add_symbol
= label_sym
;
4237 /* Return TRUE if the instruction can write to the specified
4238 integer register. */
4241 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4245 xtensa_isa isa
= xtensa_default_isa
;
4247 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4249 for (i
= 0; i
< num_ops
; i
++)
4252 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4253 if ((inout
== 'o' || inout
== 'm')
4254 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4256 xtensa_regfile opnd_rf
=
4257 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4258 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4260 if ((insn
->tok
[i
].X_op
== O_register
)
4261 && (insn
->tok
[i
].X_add_number
== regnum
))
4271 is_bad_loopend_opcode (const TInsn
*tinsn
)
4273 xtensa_opcode opcode
= tinsn
->opcode
;
4275 if (opcode
== XTENSA_UNDEFINED
)
4278 if (opcode
== xtensa_call0_opcode
4279 || opcode
== xtensa_callx0_opcode
4280 || opcode
== xtensa_call4_opcode
4281 || opcode
== xtensa_callx4_opcode
4282 || opcode
== xtensa_call8_opcode
4283 || opcode
== xtensa_callx8_opcode
4284 || opcode
== xtensa_call12_opcode
4285 || opcode
== xtensa_callx12_opcode
4286 || opcode
== xtensa_isync_opcode
4287 || opcode
== xtensa_ret_opcode
4288 || opcode
== xtensa_ret_n_opcode
4289 || opcode
== xtensa_retw_opcode
4290 || opcode
== xtensa_retw_n_opcode
4291 || opcode
== xtensa_waiti_opcode
4292 || opcode
== xtensa_rsr_lcount_opcode
)
4299 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4300 This allows the debugger to add unaligned labels.
4301 Also, the assembler generates stabs labels that need
4302 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4305 is_unaligned_label (symbolS
*sym
)
4307 const char *name
= S_GET_NAME (sym
);
4308 static size_t fake_size
= 0;
4312 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4315 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4317 fake_size
= strlen (FAKE_LABEL_NAME
);
4320 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4321 && (name
[fake_size
] == 'F'
4322 || name
[fake_size
] == 'L'
4323 || (name
[fake_size
] == 'e'
4324 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4332 next_non_empty_frag (const fragS
*fragP
)
4334 fragS
*next_fragP
= fragP
->fr_next
;
4336 /* Sometimes an empty will end up here due storage allocation issues.
4337 So we have to skip until we find something legit. */
4338 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4339 next_fragP
= next_fragP
->fr_next
;
4341 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4349 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4351 xtensa_opcode out_opcode
;
4352 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4354 if (next_fragP
== NULL
)
4357 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4358 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4360 *opcode
= out_opcode
;
4368 frag_format_size (const fragS
*fragP
)
4370 static xtensa_insnbuf insnbuf
= NULL
;
4371 xtensa_isa isa
= xtensa_default_isa
;
4376 insnbuf
= xtensa_insnbuf_alloc (isa
);
4379 return XTENSA_UNDEFINED
;
4381 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4382 (unsigned char *) fragP
->fr_literal
, 0);
4384 fmt
= xtensa_format_decode (isa
, insnbuf
);
4385 if (fmt
== XTENSA_UNDEFINED
)
4386 return XTENSA_UNDEFINED
;
4387 fmt_size
= xtensa_format_length (isa
, fmt
);
4389 /* If the next format won't be changing due to relaxation, just
4390 return the length of the first format. */
4391 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4394 /* If during relaxation we have to pull an instruction out of a
4395 multi-slot instruction, we will return the more conservative
4396 number. This works because alignment on bigger instructions
4397 is more restrictive than alignment on smaller instructions.
4398 This is more conservative than we would like, but it happens
4401 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4404 /* If we aren't doing one of our own relaxations or it isn't
4405 slot-based, then the insn size won't change. */
4406 if (fragP
->fr_type
!= rs_machine_dependent
)
4408 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4411 /* If an instruction is about to grow, return the longer size. */
4412 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4413 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4414 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4417 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4418 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4425 next_frag_format_size (const fragS
*fragP
)
4427 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4428 return frag_format_size (next_fragP
);
4432 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4433 required two-byte instructions to be treated as three-byte instructions
4434 for loop instruction alignment. This restriction was removed beginning
4435 with Xtensa LX. Now the only requirement on loop instruction alignment
4436 is that the first instruction of the loop must appear at an address that
4437 does not cross a fetch boundary. */
4440 get_loop_align_size (int insn_size
)
4442 if (insn_size
== XTENSA_UNDEFINED
)
4443 return xtensa_fetch_width
;
4445 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4452 /* If the next legit fragment is an end-of-loop marker,
4453 switch its state so it will instantiate a NOP. */
4456 update_next_frag_state (fragS
*fragP
)
4458 fragS
*next_fragP
= fragP
->fr_next
;
4459 fragS
*new_target
= NULL
;
4463 /* We are guaranteed there will be one of these... */
4464 while (!(next_fragP
->fr_type
== rs_machine_dependent
4465 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4466 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4467 next_fragP
= next_fragP
->fr_next
;
4469 assert (next_fragP
->fr_type
== rs_machine_dependent
4470 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4471 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4473 /* ...and one of these. */
4474 new_target
= next_fragP
->fr_next
;
4475 while (!(new_target
->fr_type
== rs_machine_dependent
4476 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4477 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4478 new_target
= new_target
->fr_next
;
4480 assert (new_target
->fr_type
== rs_machine_dependent
4481 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4482 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4485 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4487 if (next_fragP
->fr_type
== rs_machine_dependent
4488 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4490 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4494 next_fragP
= next_fragP
->fr_next
;
4500 next_frag_is_branch_target (const fragS
*fragP
)
4502 /* Sometimes an empty will end up here due to storage allocation issues,
4503 so we have to skip until we find something legit. */
4504 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4506 if (fragP
->tc_frag_data
.is_branch_target
)
4508 if (fragP
->fr_fix
!= 0)
4516 next_frag_is_loop_target (const fragS
*fragP
)
4518 /* Sometimes an empty will end up here due storage allocation issues.
4519 So we have to skip until we find something legit. */
4520 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4522 if (fragP
->tc_frag_data
.is_loop_target
)
4524 if (fragP
->fr_fix
!= 0)
4532 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4534 const fragS
*next_fragp
= fragp
->fr_next
;
4535 xtensa_opcode next_opcode
;
4537 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4540 /* Sometimes an empty will end up here due to storage allocation issues,
4541 so we have to skip until we find something legit. */
4542 while (next_fragp
->fr_fix
== 0)
4543 next_fragp
= next_fragp
->fr_next
;
4545 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4548 /* There is some implicit knowledge encoded in here.
4549 The LOOP instructions that are NOT RELAX_IMMED have
4550 been relaxed. Note that we can assume that the LOOP
4551 instruction is in slot 0 because loops aren't bundleable. */
4552 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4553 return get_expanded_loop_offset (next_opcode
);
4559 /* Mark a location where we can later insert literal frags. Update
4560 the section's literal_pool_loc, so subsequent literals can be
4561 placed nearest to their use. */
4564 xtensa_mark_literal_pool_location (void)
4566 /* Any labels pointing to the current location need
4567 to be adjusted to after the literal pool. */
4569 fragS
*pool_location
;
4571 if (use_literal_section
)
4574 /* We stash info in these frags so we can later move the literal's
4575 fixes into this frchain's fix list. */
4576 pool_location
= frag_now
;
4577 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4578 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4579 frag_variant (rs_machine_dependent
, 0, 0,
4580 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4581 xtensa_set_frag_assembly_state (frag_now
);
4582 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4583 frag_variant (rs_machine_dependent
, 0, 0,
4584 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4585 xtensa_set_frag_assembly_state (frag_now
);
4587 /* Now put a frag into the literal pool that points to this location. */
4588 set_literal_pool_location (now_seg
, pool_location
);
4589 xtensa_switch_to_non_abs_literal_fragment (&s
);
4590 frag_align (2, 0, 0);
4591 record_alignment (now_seg
, 2);
4593 /* Close whatever frag is there. */
4594 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4595 xtensa_set_frag_assembly_state (frag_now
);
4596 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4597 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4598 xtensa_restore_emit_state (&s
);
4599 xtensa_set_frag_assembly_state (frag_now
);
4603 /* Build a nop of the correct size into tinsn. */
4606 build_nop (TInsn
*tinsn
, int size
)
4612 tinsn
->opcode
= xtensa_nop_n_opcode
;
4614 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4615 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4619 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4621 tinsn
->opcode
= xtensa_or_opcode
;
4622 set_expr_const (&tinsn
->tok
[0], 1);
4623 set_expr_const (&tinsn
->tok
[1], 1);
4624 set_expr_const (&tinsn
->tok
[2], 1);
4628 tinsn
->opcode
= xtensa_nop_opcode
;
4630 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4635 /* Assemble a NOP of the requested size in the buffer. User must have
4636 allocated "buf" with at least "size" bytes. */
4639 assemble_nop (int size
, char *buf
)
4641 static xtensa_insnbuf insnbuf
= NULL
;
4644 build_nop (&tinsn
, size
);
4647 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4649 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4650 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4651 (unsigned char *) buf
, 0);
4655 /* Return the number of bytes for the offset of the expanded loop
4656 instruction. This should be incorporated into the relaxation
4657 specification but is hard-coded here. This is used to auto-align
4658 the loop instruction. It is invalid to call this function if the
4659 configuration does not have loops or if the opcode is not a loop
4663 get_expanded_loop_offset (xtensa_opcode opcode
)
4665 /* This is the OFFSET of the loop instruction in the expanded loop.
4666 This MUST correspond directly to the specification of the loop
4667 expansion. It will be validated on fragment conversion. */
4668 assert (opcode
!= XTENSA_UNDEFINED
);
4669 if (opcode
== xtensa_loop_opcode
)
4671 if (opcode
== xtensa_loopnez_opcode
)
4673 if (opcode
== xtensa_loopgtz_opcode
)
4675 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4681 get_literal_pool_location (segT seg
)
4683 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4688 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4690 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4694 /* Set frag assembly state should be called when a new frag is
4695 opened and after a frag has been closed. */
4698 xtensa_set_frag_assembly_state (fragS
*fragP
)
4700 if (!density_supported
)
4701 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4703 /* This function is called from subsegs_finish, which is called
4704 after xtensa_end, so we can't use "use_transform" or
4705 "use_schedule" here. */
4706 if (!directive_state
[directive_transform
])
4707 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4708 if (directive_state
[directive_longcalls
])
4709 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4710 fragP
->tc_frag_data
.use_absolute_literals
=
4711 directive_state
[directive_absolute_literals
];
4712 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4717 relaxable_section (asection
*sec
)
4719 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4720 && strcmp (sec
->name
, ".eh_frame") != 0);
4725 xtensa_mark_frags_for_org (void)
4729 /* Walk over each fragment of all of the current segments. If we find
4730 a .org frag in any of the segments, mark all frags prior to it as
4731 "no transform", which will prevent linker optimizations from messing
4732 up the .org distance. This should be done after
4733 xtensa_find_unmarked_state_frags, because we don't want to worry here
4734 about that function trashing the data we save here. */
4736 for (seclist
= &stdoutput
->sections
;
4737 seclist
&& *seclist
;
4738 seclist
= &(*seclist
)->next
)
4740 segT sec
= *seclist
;
4741 segment_info_type
*seginfo
;
4744 flags
= bfd_get_section_flags (stdoutput
, sec
);
4745 if (flags
& SEC_DEBUGGING
)
4747 if (!(flags
& SEC_ALLOC
))
4750 seginfo
= seg_info (sec
);
4751 if (seginfo
&& seginfo
->frchainP
)
4753 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4754 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4755 fragP
= fragP
->fr_next
)
4757 /* cvt_frag_to_fill has changed the fr_type of org frags to
4758 rs_fill, so use the value as cached in rs_subtype here. */
4759 if (fragP
->fr_subtype
== RELAX_ORG
)
4761 while (last_fragP
!= fragP
->fr_next
)
4763 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4764 last_fragP
= last_fragP
->fr_next
;
4774 xtensa_find_unmarked_state_frags (void)
4778 /* Walk over each fragment of all of the current segments. For each
4779 unmarked fragment, mark it with the same info as the previous
4781 for (seclist
= &stdoutput
->sections
;
4782 seclist
&& *seclist
;
4783 seclist
= &(*seclist
)->next
)
4785 segT sec
= *seclist
;
4786 segment_info_type
*seginfo
;
4789 flags
= bfd_get_section_flags (stdoutput
, sec
);
4790 if (flags
& SEC_DEBUGGING
)
4792 if (!(flags
& SEC_ALLOC
))
4795 seginfo
= seg_info (sec
);
4796 if (seginfo
&& seginfo
->frchainP
)
4798 fragS
*last_fragP
= 0;
4799 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4800 fragP
= fragP
->fr_next
)
4802 if (fragP
->fr_fix
!= 0
4803 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4805 if (last_fragP
== 0)
4807 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4808 _("assembly state not set for first frag in section %s"),
4813 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4814 fragP
->tc_frag_data
.is_no_density
=
4815 last_fragP
->tc_frag_data
.is_no_density
;
4816 fragP
->tc_frag_data
.is_no_transform
=
4817 last_fragP
->tc_frag_data
.is_no_transform
;
4818 fragP
->tc_frag_data
.use_longcalls
=
4819 last_fragP
->tc_frag_data
.use_longcalls
;
4820 fragP
->tc_frag_data
.use_absolute_literals
=
4821 last_fragP
->tc_frag_data
.use_absolute_literals
;
4824 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4833 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4835 void *unused ATTRIBUTE_UNUSED
)
4837 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4838 segment_info_type
*seginfo
= seg_info (sec
);
4839 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4841 if (flags
& SEC_CODE
)
4843 xtensa_isa isa
= xtensa_default_isa
;
4844 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4845 while (frag
!= NULL
)
4847 if (frag
->tc_frag_data
.is_branch_target
)
4850 addressT branch_align
, frag_addr
;
4853 xtensa_insnbuf_from_chars
4854 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4855 fmt
= xtensa_format_decode (isa
, insnbuf
);
4856 op_size
= xtensa_format_length (isa
, fmt
);
4857 branch_align
= 1 << branch_align_power (sec
);
4858 frag_addr
= frag
->fr_address
% branch_align
;
4859 if (frag_addr
+ op_size
> branch_align
)
4860 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4861 _("unaligned branch target: %d bytes at 0x%lx"),
4862 op_size
, (long) frag
->fr_address
);
4864 frag
= frag
->fr_next
;
4866 xtensa_insnbuf_free (isa
, insnbuf
);
4872 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4874 void *unused ATTRIBUTE_UNUSED
)
4876 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4877 segment_info_type
*seginfo
= seg_info (sec
);
4878 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4879 xtensa_isa isa
= xtensa_default_isa
;
4881 if (flags
& SEC_CODE
)
4883 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4884 while (frag
!= NULL
)
4886 if (frag
->tc_frag_data
.is_first_loop_insn
)
4892 xtensa_insnbuf_from_chars
4893 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4894 fmt
= xtensa_format_decode (isa
, insnbuf
);
4895 op_size
= xtensa_format_length (isa
, fmt
);
4896 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4898 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4899 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4900 _("unaligned loop: %d bytes at 0x%lx"),
4901 op_size
, (long) frag
->fr_address
);
4903 frag
= frag
->fr_next
;
4905 xtensa_insnbuf_free (isa
, insnbuf
);
4911 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4913 xtensa_isa isa
= xtensa_default_isa
;
4914 static xtensa_insnbuf insnbuf
= NULL
;
4915 static xtensa_insnbuf slotbuf
= NULL
;
4918 bfd_boolean alt_reloc
;
4919 xtensa_opcode opcode
;
4920 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4922 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4924 as_fatal (_("unexpected fix"));
4928 insnbuf
= xtensa_insnbuf_alloc (isa
);
4929 slotbuf
= xtensa_insnbuf_alloc (isa
);
4932 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4933 fmt
= xtensa_format_decode (isa
, insnbuf
);
4934 if (fmt
== XTENSA_UNDEFINED
)
4935 as_fatal (_("undecodable fix"));
4936 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4937 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4938 if (opcode
== XTENSA_UNDEFINED
)
4939 as_fatal (_("undecodable fix"));
4941 /* CONST16 immediates are not PC-relative, despite the fact that we
4942 reuse the normal PC-relative operand relocations for the low part
4943 of a CONST16 operand. */
4944 if (opcode
== xtensa_const16_opcode
)
4947 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4948 get_relaxable_immed (opcode
), val
,
4949 fixP
->fx_file
, fixP
->fx_line
);
4951 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4952 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4958 /* External Functions and Other GAS Hooks. */
4961 xtensa_target_format (void)
4963 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4968 xtensa_file_arch_init (bfd
*abfd
)
4970 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4975 md_number_to_chars (char *buf
, valueT val
, int n
)
4977 if (target_big_endian
)
4978 number_to_chars_bigendian (buf
, val
, n
);
4980 number_to_chars_littleendian (buf
, val
, n
);
4984 /* This function is called once, at assembler startup time. It should
4985 set up all the tables, etc. that the MD part of the assembler will
4991 segT current_section
= now_seg
;
4992 int current_subsec
= now_subseg
;
4995 xtensa_default_isa
= xtensa_isa_init (0, 0);
4996 isa
= xtensa_default_isa
;
5000 /* Set up the literal sections. */
5001 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5003 subseg_set (current_section
, current_subsec
);
5005 xg_init_vinsn (&cur_vinsn
);
5007 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5008 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5009 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5010 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5011 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5012 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5013 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5014 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5015 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5016 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5017 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5018 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5019 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5020 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5021 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5022 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5023 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5024 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5025 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5026 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5027 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5028 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5029 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5030 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5031 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5032 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5033 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5034 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5035 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5036 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5038 init_op_placement_info_table ();
5040 /* Set up the assembly state. */
5041 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5042 xtensa_set_frag_assembly_state (frag_now
);
5046 /* TC_INIT_FIX_DATA hook */
5049 xtensa_init_fix_data (fixS
*x
)
5051 x
->tc_fix_data
.slot
= 0;
5052 x
->tc_fix_data
.X_add_symbol
= NULL
;
5053 x
->tc_fix_data
.X_add_number
= 0;
5057 /* tc_frob_label hook */
5060 xtensa_frob_label (symbolS
*sym
)
5064 if (cur_vinsn
.inside_bundle
)
5066 as_bad (_("labels are not valid inside bundles"));
5070 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5072 /* Since the label was already attached to a frag associated with the
5073 previous basic block, it now needs to be reset to the current frag. */
5074 symbol_set_frag (sym
, frag_now
);
5075 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5077 if (generating_literals
)
5078 xtensa_add_literal_sym (sym
);
5080 xtensa_add_insn_label (sym
);
5082 if (symbol_get_tc (sym
)->is_loop_target
)
5084 if ((get_last_insn_flags (now_seg
, now_subseg
)
5085 & FLAG_IS_BAD_LOOPEND
) != 0)
5086 as_bad (_("invalid last instruction for a zero-overhead loop"));
5088 xtensa_set_frag_assembly_state (frag_now
);
5089 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5090 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5092 xtensa_set_frag_assembly_state (frag_now
);
5093 xtensa_move_labels (frag_now
, 0);
5096 /* No target aligning in the absolute section. */
5097 if (now_seg
!= absolute_section
5098 && do_align_targets ()
5099 && !is_unaligned_label (sym
)
5100 && !generating_literals
)
5102 xtensa_set_frag_assembly_state (frag_now
);
5104 frag_var (rs_machine_dependent
,
5106 RELAX_DESIRE_ALIGN_IF_TARGET
,
5107 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5108 xtensa_set_frag_assembly_state (frag_now
);
5109 xtensa_move_labels (frag_now
, 0);
5112 /* We need to mark the following properties even if we aren't aligning. */
5114 /* If the label is already known to be a branch target, i.e., a
5115 forward branch, mark the frag accordingly. Backward branches
5116 are handled by xg_add_branch_and_loop_targets. */
5117 if (symbol_get_tc (sym
)->is_branch_target
)
5118 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5120 /* Loops only go forward, so they can be identified here. */
5121 if (symbol_get_tc (sym
)->is_loop_target
)
5122 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5124 dwarf2_emit_label (sym
);
5128 /* tc_unrecognized_line hook */
5131 xtensa_unrecognized_line (int ch
)
5136 if (cur_vinsn
.inside_bundle
== 0)
5138 /* PR8110: Cannot emit line number info inside a FLIX bundle
5139 when using --gstabs. Temporarily disable debug info. */
5140 generate_lineno_debug ();
5141 if (debug_type
== DEBUG_STABS
)
5143 xt_saved_debug_type
= debug_type
;
5144 debug_type
= DEBUG_NONE
;
5147 cur_vinsn
.inside_bundle
= 1;
5151 as_bad (_("extra opening brace"));
5157 if (cur_vinsn
.inside_bundle
)
5158 finish_vinsn (&cur_vinsn
);
5161 as_bad (_("extra closing brace"));
5166 as_bad (_("syntax error"));
5173 /* md_flush_pending_output hook */
5176 xtensa_flush_pending_output (void)
5178 /* This line fixes a bug where automatically generated gstabs info
5179 separates a function label from its entry instruction, ending up
5180 with the literal position between the function label and the entry
5181 instruction and crashing code. It only happens with --gstabs and
5182 --text-section-literals, and when several other obscure relaxation
5183 conditions are met. */
5184 if (outputting_stabs_line_debug
)
5187 if (cur_vinsn
.inside_bundle
)
5188 as_bad (_("missing closing brace"));
5190 /* If there is a non-zero instruction fragment, close it. */
5191 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5193 frag_wane (frag_now
);
5195 xtensa_set_frag_assembly_state (frag_now
);
5197 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5199 xtensa_clear_insn_labels ();
5203 /* We had an error while parsing an instruction. The string might look
5204 like this: "insn arg1, arg2 }". If so, we need to see the closing
5205 brace and reset some fields. Otherwise, the vinsn never gets closed
5206 and the num_slots field will grow past the end of the array of slots,
5207 and bad things happen. */
5210 error_reset_cur_vinsn (void)
5212 if (cur_vinsn
.inside_bundle
)
5214 if (*input_line_pointer
== '}'
5215 || *(input_line_pointer
- 1) == '}'
5216 || *(input_line_pointer
- 2) == '}')
5217 xg_clear_vinsn (&cur_vinsn
);
5223 md_assemble (char *str
)
5225 xtensa_isa isa
= xtensa_default_isa
;
5228 bfd_boolean has_underbar
= FALSE
;
5229 char *arg_strings
[MAX_INSN_ARGS
];
5231 TInsn orig_insn
; /* Original instruction from the input. */
5233 tinsn_init (&orig_insn
);
5235 /* Split off the opcode. */
5236 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5237 opname
= xmalloc (opnamelen
+ 1);
5238 memcpy (opname
, str
, opnamelen
);
5239 opname
[opnamelen
] = '\0';
5241 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5244 as_bad (_("syntax error"));
5248 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5251 /* Check for an underbar prefix. */
5254 has_underbar
= TRUE
;
5258 orig_insn
.insn_type
= ITYPE_INSN
;
5260 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5262 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5263 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5265 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5266 if (fmt
== XTENSA_UNDEFINED
)
5268 as_bad (_("unknown opcode or format name '%s'"), opname
);
5269 error_reset_cur_vinsn ();
5272 if (!cur_vinsn
.inside_bundle
)
5274 as_bad (_("format names only valid inside bundles"));
5275 error_reset_cur_vinsn ();
5278 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5279 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5281 cur_vinsn
.format
= fmt
;
5282 free (has_underbar
? opname
- 1 : opname
);
5283 error_reset_cur_vinsn ();
5287 /* Parse the arguments. */
5288 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5290 as_bad (_("syntax error"));
5291 error_reset_cur_vinsn ();
5295 /* Free the opcode and argument strings, now that they've been parsed. */
5296 free (has_underbar
? opname
- 1 : opname
);
5298 while (num_args
-- > 0)
5299 free (arg_strings
[num_args
]);
5301 /* Get expressions for invisible operands. */
5302 if (get_invisible_operands (&orig_insn
))
5304 error_reset_cur_vinsn ();
5308 /* Check for the right number and type of arguments. */
5309 if (tinsn_check_arguments (&orig_insn
))
5311 error_reset_cur_vinsn ();
5315 /* Record the line number for each TInsn, because a FLIX bundle may be
5316 spread across multiple input lines and individual instructions may be
5317 moved around in some cases. */
5318 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5319 dwarf2_where (&orig_insn
.debug_line
);
5320 dwarf2_consume_line_info ();
5322 xg_add_branch_and_loop_targets (&orig_insn
);
5324 /* Check that immediate value for ENTRY is >= 16. */
5325 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5327 expressionS
*exp
= &orig_insn
.tok
[2];
5328 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5329 as_warn (_("entry instruction with stack decrement < 16"));
5333 assemble_tokens (opcode, tok, ntok);
5334 expand the tokens from the orig_insn into the
5335 stack of instructions that will not expand
5336 unless required at relaxation time. */
5338 if (!cur_vinsn
.inside_bundle
)
5339 emit_single_op (&orig_insn
);
5340 else /* We are inside a bundle. */
5342 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5343 cur_vinsn
.num_slots
++;
5344 if (*input_line_pointer
== '}'
5345 || *(input_line_pointer
- 1) == '}'
5346 || *(input_line_pointer
- 2) == '}')
5347 finish_vinsn (&cur_vinsn
);
5350 /* We've just emitted a new instruction so clear the list of labels. */
5351 xtensa_clear_insn_labels ();
5355 /* HANDLE_ALIGN hook */
5357 /* For a .align directive, we mark the previous block with the alignment
5358 information. This will be placed in the object file in the
5359 property section corresponding to this section. */
5362 xtensa_handle_align (fragS
*fragP
)
5365 && ! fragP
->tc_frag_data
.is_literal
5366 && (fragP
->fr_type
== rs_align
5367 || fragP
->fr_type
== rs_align_code
)
5368 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5369 && fragP
->fr_offset
> 0
5370 && now_seg
!= bss_section
)
5372 fragP
->tc_frag_data
.is_align
= TRUE
;
5373 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5376 if (fragP
->fr_type
== rs_align_test
)
5379 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5381 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5382 _("unaligned entry instruction"));
5385 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5386 fragP
->fr_subtype
= RELAX_ORG
;
5390 /* TC_FRAG_INIT hook */
5393 xtensa_frag_init (fragS
*frag
)
5395 xtensa_set_frag_assembly_state (frag
);
5400 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5406 /* Round up a section size to the appropriate boundary. */
5409 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5411 return size
; /* Byte alignment is fine. */
5416 md_pcrel_from (fixS
*fixP
)
5419 static xtensa_insnbuf insnbuf
= NULL
;
5420 static xtensa_insnbuf slotbuf
= NULL
;
5423 xtensa_opcode opcode
;
5426 xtensa_isa isa
= xtensa_default_isa
;
5427 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5428 bfd_boolean alt_reloc
;
5430 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5435 insnbuf
= xtensa_insnbuf_alloc (isa
);
5436 slotbuf
= xtensa_insnbuf_alloc (isa
);
5439 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5440 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5441 fmt
= xtensa_format_decode (isa
, insnbuf
);
5443 if (fmt
== XTENSA_UNDEFINED
)
5444 as_fatal (_("bad instruction format"));
5446 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5447 as_fatal (_("invalid relocation"));
5449 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5450 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5452 /* Check for "alternate" relocations (operand not specified). None
5453 of the current uses for these are really PC-relative. */
5454 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5456 if (opcode
!= xtensa_l32r_opcode
5457 && opcode
!= xtensa_const16_opcode
)
5458 as_fatal (_("invalid relocation for '%s' instruction"),
5459 xtensa_opcode_name (isa
, opcode
));
5463 opnum
= get_relaxable_immed (opcode
);
5465 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5466 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5468 as_bad_where (fixP
->fx_file
,
5470 _("invalid relocation for operand %d of '%s'"),
5471 opnum
, xtensa_opcode_name (isa
, opcode
));
5474 return 0 - opnd_value
;
5478 /* TC_FORCE_RELOCATION hook */
5481 xtensa_force_relocation (fixS
*fix
)
5483 switch (fix
->fx_r_type
)
5485 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5486 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5487 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5488 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5489 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5490 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5491 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5492 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5493 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5494 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5495 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5496 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5497 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5498 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5499 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5500 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5506 if (linkrelax
&& fix
->fx_addsy
5507 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5510 return generic_force_reloc (fix
);
5514 /* TC_VALIDATE_FIX_SUB hook */
5517 xtensa_validate_fix_sub (fixS
*fix
)
5519 segT add_symbol_segment
, sub_symbol_segment
;
5521 /* The difference of two symbols should be resolved by the assembler when
5522 linkrelax is not set. If the linker may relax the section containing
5523 the symbols, then an Xtensa DIFF relocation must be generated so that
5524 the linker knows to adjust the difference value. */
5525 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5528 /* Make sure both symbols are in the same segment, and that segment is
5529 "normal" and relaxable. If the segment is not "normal", then the
5530 fix is not valid. If the segment is not "relaxable", then the fix
5531 should have been handled earlier. */
5532 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5533 if (! SEG_NORMAL (add_symbol_segment
) ||
5534 ! relaxable_section (add_symbol_segment
))
5536 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5537 return (sub_symbol_segment
== add_symbol_segment
);
5541 /* NO_PSEUDO_DOT hook */
5543 /* This function has nothing to do with pseudo dots, but this is the
5544 nearest macro to where the check needs to take place. FIXME: This
5548 xtensa_check_inside_bundle (void)
5550 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5551 as_bad (_("directives are not valid inside bundles"));
5553 /* This function must always return FALSE because it is called via a
5554 macro that has nothing to do with bundling. */
5559 /* md_elf_section_change_hook */
5562 xtensa_elf_section_change_hook (void)
5564 /* Set up the assembly state. */
5565 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5566 xtensa_set_frag_assembly_state (frag_now
);
5570 /* tc_fix_adjustable hook */
5573 xtensa_fix_adjustable (fixS
*fixP
)
5575 /* An offset is not allowed in combination with the difference of two
5576 symbols, but that cannot be easily detected after a local symbol
5577 has been adjusted to a (section+offset) form. Return 0 so that such
5578 an fix will not be adjusted. */
5579 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5580 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5583 /* We need the symbol name for the VTABLE entries. */
5584 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5585 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5592 /* tc_symbol_new_hook */
5594 symbolS
*expr_symbols
= NULL
;
5597 xtensa_symbol_new_hook (symbolS
*sym
)
5599 if (S_GET_SEGMENT (sym
) == expr_section
)
5601 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5609 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5611 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5614 /* Subtracted symbols are only allowed for a few relocation types, and
5615 unless linkrelax is enabled, they should not make it to this point. */
5616 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5617 || fixP
->fx_r_type
== BFD_RELOC_16
5618 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5621 switch (fixP
->fx_r_type
)
5628 switch (fixP
->fx_r_type
)
5631 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5634 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5637 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5643 /* An offset is only allowed when it results from adjusting a
5644 local symbol into a section-relative offset. If the offset
5645 came from the original expression, tc_fix_adjustable will have
5646 prevented the fix from being converted to a section-relative
5647 form so that we can flag the error here. */
5648 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5649 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5650 _("cannot represent subtraction with an offset"));
5652 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5653 - S_GET_VALUE (fixP
->fx_subsy
));
5655 /* The difference value gets written out, and the DIFF reloc
5656 identifies the address of the subtracted symbol (i.e., the one
5657 with the lowest address). */
5659 fixP
->fx_offset
-= val
;
5660 fixP
->fx_subsy
= NULL
;
5662 else if (! fixP
->fx_addsy
)
5669 case BFD_RELOC_XTENSA_PLT
:
5670 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5671 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5674 case BFD_RELOC_XTENSA_SLOT0_OP
:
5675 case BFD_RELOC_XTENSA_SLOT1_OP
:
5676 case BFD_RELOC_XTENSA_SLOT2_OP
:
5677 case BFD_RELOC_XTENSA_SLOT3_OP
:
5678 case BFD_RELOC_XTENSA_SLOT4_OP
:
5679 case BFD_RELOC_XTENSA_SLOT5_OP
:
5680 case BFD_RELOC_XTENSA_SLOT6_OP
:
5681 case BFD_RELOC_XTENSA_SLOT7_OP
:
5682 case BFD_RELOC_XTENSA_SLOT8_OP
:
5683 case BFD_RELOC_XTENSA_SLOT9_OP
:
5684 case BFD_RELOC_XTENSA_SLOT10_OP
:
5685 case BFD_RELOC_XTENSA_SLOT11_OP
:
5686 case BFD_RELOC_XTENSA_SLOT12_OP
:
5687 case BFD_RELOC_XTENSA_SLOT13_OP
:
5688 case BFD_RELOC_XTENSA_SLOT14_OP
:
5691 /* Write the tentative value of a PC-relative relocation to a
5692 local symbol into the instruction. The value will be ignored
5693 by the linker, and it makes the object file disassembly
5694 readable when all branch targets are encoded in relocations. */
5696 assert (fixP
->fx_addsy
);
5697 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5698 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5700 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5701 - md_pcrel_from (fixP
));
5702 (void) xg_apply_fix_value (fixP
, val
);
5705 else if (! fixP
->fx_addsy
)
5708 if (xg_apply_fix_value (fixP
, val
))
5713 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5714 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5715 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5716 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5717 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5718 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5719 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5720 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5721 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5722 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5723 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5724 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5725 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5726 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5727 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5728 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5729 /* These all need to be resolved at link-time. Do nothing now. */
5732 case BFD_RELOC_VTABLE_INHERIT
:
5733 case BFD_RELOC_VTABLE_ENTRY
:
5738 as_bad (_("unhandled local relocation fix %s"),
5739 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5745 md_atof (int type
, char *litP
, int *sizeP
)
5747 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5752 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5754 return total_frag_text_expansion (fragP
);
5758 /* Translate internal representation of relocation info to BFD target
5762 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5766 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5767 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5768 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5769 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5771 /* Make sure none of our internal relocations make it this far.
5772 They'd better have been fully resolved by this point. */
5773 assert ((int) fixp
->fx_r_type
> 0);
5775 reloc
->addend
= fixp
->fx_offset
;
5777 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5778 if (reloc
->howto
== NULL
)
5780 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5781 _("cannot represent `%s' relocation in object file"),
5782 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5783 free (reloc
->sym_ptr_ptr
);
5788 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5789 as_fatal (_("internal error? cannot generate `%s' relocation"),
5790 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5796 /* Checks for resource conflicts between instructions. */
5798 /* The func unit stuff could be implemented as bit-vectors rather
5799 than the iterative approach here. If it ends up being too
5800 slow, we will switch it. */
5803 new_resource_table (void *data
,
5806 unit_num_copies_func uncf
,
5807 opcode_num_units_func onuf
,
5808 opcode_funcUnit_use_unit_func ouuf
,
5809 opcode_funcUnit_use_stage_func ousf
)
5812 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5814 rt
->cycles
= cycles
;
5815 rt
->allocated_cycles
= cycles
;
5817 rt
->unit_num_copies
= uncf
;
5818 rt
->opcode_num_units
= onuf
;
5819 rt
->opcode_unit_use
= ouuf
;
5820 rt
->opcode_unit_stage
= ousf
;
5822 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5823 for (i
= 0; i
< cycles
; i
++)
5824 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5831 clear_resource_table (resource_table
*rt
)
5834 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5835 for (j
= 0; j
< rt
->num_units
; j
++)
5836 rt
->units
[i
][j
] = 0;
5840 /* We never shrink it, just fake it into thinking so. */
5843 resize_resource_table (resource_table
*rt
, int cycles
)
5847 rt
->cycles
= cycles
;
5848 if (cycles
<= rt
->allocated_cycles
)
5851 old_cycles
= rt
->allocated_cycles
;
5852 rt
->allocated_cycles
= cycles
;
5854 rt
->units
= xrealloc (rt
->units
,
5855 rt
->allocated_cycles
* sizeof (unsigned char *));
5856 for (i
= 0; i
< old_cycles
; i
++)
5857 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5858 rt
->num_units
* sizeof (unsigned char));
5859 for (i
= old_cycles
; i
< cycles
; i
++)
5860 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5865 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5868 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5870 for (i
= 0; i
< uses
; i
++)
5872 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5873 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5874 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5875 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5876 if (copies_in_use
>= copies
)
5884 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5887 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5889 for (i
= 0; i
< uses
; i
++)
5891 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5892 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5893 /* Note that this allows resources to be oversubscribed. That's
5894 essential to the way the optional scheduler works.
5895 resources_available reports when a resource is over-subscribed,
5896 so it's easy to tell. */
5897 rt
->units
[stage
+ cycle
][unit
]++;
5903 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5906 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5908 for (i
= 0; i
< uses
; i
++)
5910 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5911 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5912 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5913 rt
->units
[stage
+ cycle
][unit
]--;
5918 /* Wrapper functions make parameterized resource reservation
5922 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5924 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5930 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5932 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5937 /* Note that this function does not check issue constraints, but
5938 solely whether the hardware is available to execute the given
5939 instructions together. It also doesn't check if the tinsns
5940 write the same state, or access the same tieports. That is
5941 checked by check_t1_t2_reads_and_writes. */
5944 resources_conflict (vliw_insn
*vinsn
)
5947 static resource_table
*rt
= NULL
;
5949 /* This is the most common case by far. Optimize it. */
5950 if (vinsn
->num_slots
== 1)
5955 xtensa_isa isa
= xtensa_default_isa
;
5956 rt
= new_resource_table
5957 (isa
, xtensa_isa_num_pipe_stages (isa
),
5958 xtensa_isa_num_funcUnits (isa
),
5959 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5960 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5961 opcode_funcUnit_use_unit
,
5962 opcode_funcUnit_use_stage
);
5965 clear_resource_table (rt
);
5967 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5969 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5971 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5978 /* finish_vinsn, emit_single_op and helper functions. */
5980 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5981 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5982 static void xg_assemble_vliw_tokens (vliw_insn
*);
5985 /* We have reached the end of a bundle; emit into the frag. */
5988 finish_vinsn (vliw_insn
*vinsn
)
5995 if (find_vinsn_conflicts (vinsn
))
5997 xg_clear_vinsn (vinsn
);
6001 /* First, find a format that works. */
6002 if (vinsn
->format
== XTENSA_UNDEFINED
)
6003 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6005 if (vinsn
->format
== XTENSA_UNDEFINED
)
6007 as_where (&file_name
, &line
);
6008 as_bad_where (file_name
, line
,
6009 _("couldn't find a valid instruction format"));
6010 fprintf (stderr
, _(" ops were: "));
6011 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6012 fprintf (stderr
, _(" %s;"),
6013 xtensa_opcode_name (xtensa_default_isa
,
6014 vinsn
->slots
[i
].opcode
));
6015 fprintf (stderr
, _("\n"));
6016 xg_clear_vinsn (vinsn
);
6020 if (vinsn
->num_slots
6021 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6023 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6024 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6025 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6027 xg_clear_vinsn (vinsn
);
6031 if (resources_conflict (vinsn
))
6033 as_where (&file_name
, &line
);
6034 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6035 fprintf (stderr
, " ops were: ");
6036 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6037 fprintf (stderr
, " %s;",
6038 xtensa_opcode_name (xtensa_default_isa
,
6039 vinsn
->slots
[i
].opcode
));
6040 fprintf (stderr
, "\n");
6041 xg_clear_vinsn (vinsn
);
6045 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6047 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6049 symbolS
*lit_sym
= NULL
;
6051 bfd_boolean e
= FALSE
;
6052 bfd_boolean saved_density
= density_supported
;
6054 /* We don't want to narrow ops inside multi-slot bundles. */
6055 if (vinsn
->num_slots
> 1)
6056 density_supported
= FALSE
;
6058 istack_init (&slotstack
);
6059 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6061 vinsn
->slots
[i
].opcode
=
6062 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6064 vinsn
->slots
[i
].ntok
= 0;
6067 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6073 density_supported
= saved_density
;
6077 xg_clear_vinsn (vinsn
);
6081 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6083 TInsn
*insn
= &slotstack
.insn
[j
];
6084 if (insn
->insn_type
== ITYPE_LITERAL
)
6086 assert (lit_sym
== NULL
);
6087 lit_sym
= xg_assemble_literal (insn
);
6091 assert (insn
->insn_type
== ITYPE_INSN
);
6093 xg_resolve_literals (insn
, lit_sym
);
6094 if (j
!= slotstack
.ninsn
- 1)
6095 emit_single_op (insn
);
6099 if (vinsn
->num_slots
> 1)
6101 if (opcode_fits_format_slot
6102 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6105 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6109 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6110 if (vinsn
->format
== XTENSA_UNDEFINED
)
6111 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6113 vinsn
->slots
[i
].opcode
6114 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6117 vinsn
->slots
[i
].ntok
= 0;
6122 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6123 vinsn
->format
= XTENSA_UNDEFINED
;
6128 /* Now check resource conflicts on the modified bundle. */
6129 if (resources_conflict (vinsn
))
6131 as_where (&file_name
, &line
);
6132 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6133 fprintf (stderr
, " ops were: ");
6134 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6135 fprintf (stderr
, " %s;",
6136 xtensa_opcode_name (xtensa_default_isa
,
6137 vinsn
->slots
[i
].opcode
));
6138 fprintf (stderr
, "\n");
6139 xg_clear_vinsn (vinsn
);
6143 /* First, find a format that works. */
6144 if (vinsn
->format
== XTENSA_UNDEFINED
)
6145 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6147 xg_assemble_vliw_tokens (vinsn
);
6149 xg_clear_vinsn (vinsn
);
6153 /* Given an vliw instruction, what conflicts are there in register
6154 usage and in writes to states and queues?
6156 This function does two things:
6157 1. Reports an error when a vinsn contains illegal combinations
6158 of writes to registers states or queues.
6159 2. Marks individual tinsns as not relaxable if the combination
6160 contains antidependencies.
6162 Job 2 handles things like swap semantics in instructions that need
6163 to be relaxed. For example,
6167 normally would be relaxed to
6172 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6174 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6176 then we can't relax it into
6179 { add a0, a1, a0 ; add a2, a0, a4 ; }
6181 because the value of a0 is trashed before the second add can read it. */
6183 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6186 find_vinsn_conflicts (vliw_insn
*vinsn
)
6190 xtensa_isa isa
= xtensa_default_isa
;
6192 assert (!past_xtensa_end
);
6194 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6196 TInsn
*op1
= &vinsn
->slots
[i
];
6197 if (op1
->is_specific_opcode
)
6198 op1
->keep_wide
= TRUE
;
6200 op1
->keep_wide
= FALSE
;
6203 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6205 TInsn
*op1
= &vinsn
->slots
[i
];
6207 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6210 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6214 TInsn
*op2
= &vinsn
->slots
[j
];
6215 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6216 switch (conflict_type
)
6219 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6220 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6221 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6224 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6225 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6226 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6229 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6230 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6231 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6234 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6235 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6236 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6239 /* Everything is OK. */
6242 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6243 || conflict_type
== 'a');
6250 as_bad (_("multiple branches or jumps in the same bundle"));
6258 /* Check how the state used by t1 and t2 relate.
6261 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6262 case B: no relationship between what is read and written (both could
6263 read the same reg though)
6264 case C: t1 writes a register t2 writes (a register conflict within a
6266 case D: t1 writes a state that t2 also writes
6267 case E: t1 writes a tie queue that t2 also writes
6268 case F: two volatile queue accesses
6272 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6274 xtensa_isa isa
= xtensa_default_isa
;
6275 xtensa_regfile t1_regfile
, t2_regfile
;
6277 int t1_base_reg
, t1_last_reg
;
6278 int t2_base_reg
, t2_last_reg
;
6279 char t1_inout
, t2_inout
;
6281 char conflict
= 'b';
6286 bfd_boolean t1_volatile
= FALSE
;
6287 bfd_boolean t2_volatile
= FALSE
;
6289 /* Check registers. */
6290 for (j
= 0; j
< t2
->ntok
; j
++)
6292 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6295 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6296 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6297 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6299 for (i
= 0; i
< t1
->ntok
; i
++)
6301 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6304 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6306 if (t1_regfile
!= t2_regfile
)
6309 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6310 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6312 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6313 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6315 if (t1_inout
== 'm' || t1_inout
== 'o'
6316 || t2_inout
== 'm' || t2_inout
== 'o')
6323 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6324 t1_last_reg
= (t1_base_reg
6325 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6327 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6329 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6331 if (t1_reg
!= t2_reg
)
6334 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6340 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6346 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6354 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6355 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6356 for (j
= 0; j
< t2_states
; j
++)
6358 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6359 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6360 for (i
= 0; i
< t1_states
; i
++)
6362 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6363 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6367 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6373 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6379 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6384 /* Check tieports. */
6385 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6386 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6387 for (j
= 0; j
< t2_interfaces
; j
++)
6389 xtensa_interface t2_int
6390 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6391 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6393 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6394 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6397 for (i
= 0; i
< t1_interfaces
; i
++)
6399 xtensa_interface t1_int
6400 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6401 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6403 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6404 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6407 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6410 if (t1_int
!= t2_int
)
6413 if (t2_inout
== 'i' && t1_inout
== 'o')
6419 if (t1_inout
== 'i' && t2_inout
== 'o')
6425 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6434 static xtensa_format
6435 xg_find_narrowest_format (vliw_insn
*vinsn
)
6437 /* Right now we assume that the ops within the vinsn are properly
6438 ordered for the slots that the programmer wanted them in. In
6439 other words, we don't rearrange the ops in hopes of finding a
6440 better format. The scheduler handles that. */
6442 xtensa_isa isa
= xtensa_default_isa
;
6443 xtensa_format format
;
6444 vliw_insn v_copy
= *vinsn
;
6445 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6447 if (vinsn
->num_slots
== 1)
6448 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6450 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6453 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6457 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6459 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6461 v_copy
.slots
[slot
].opcode
=
6462 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6463 v_copy
.slots
[slot
].ntok
= 0;
6466 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6469 else if (v_copy
.num_slots
> 1)
6472 /* Try the widened version. */
6473 if (!v_copy
.slots
[slot
].keep_wide
6474 && !v_copy
.slots
[slot
].is_specific_opcode
6475 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6477 && opcode_fits_format_slot (widened
.opcode
,
6480 v_copy
.slots
[slot
] = widened
;
6485 if (fit
== v_copy
.num_slots
)
6488 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6489 vinsn
->format
= format
;
6495 if (format
== xtensa_isa_num_formats (isa
))
6496 return XTENSA_UNDEFINED
;
6502 /* Return the additional space needed in a frag
6503 for possible relaxations of any ops in a VLIW insn.
6504 Also fill out the relaxations that might be required of
6505 each tinsn in the vinsn. */
6508 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6510 bfd_boolean finish_frag
= FALSE
;
6511 int extra_space
= 0;
6514 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6516 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6517 if (!tinsn_has_symbolic_operands (tinsn
))
6519 /* A narrow instruction could be widened later to help
6520 alignment issues. */
6521 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6522 && !tinsn
->is_specific_opcode
6523 && vinsn
->num_slots
== 1)
6525 /* Difference in bytes between narrow and wide insns... */
6527 tinsn
->subtype
= RELAX_NARROW
;
6532 if (workaround_b_j_loop_end
6533 && tinsn
->opcode
== xtensa_jx_opcode
6534 && use_transform ())
6536 /* Add 2 of these. */
6537 extra_space
+= 3; /* for the nop size */
6538 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6541 /* Need to assemble it with space for the relocation. */
6542 if (xg_is_relaxable_insn (tinsn
, 0)
6543 && !tinsn
->is_specific_opcode
)
6545 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6546 int max_literal_size
=
6547 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6549 tinsn
->literal_space
= max_literal_size
;
6551 tinsn
->subtype
= RELAX_IMMED
;
6552 extra_space
+= max_size
;
6556 /* A fix record will be added for this instruction prior
6557 to relaxation, so make it end the frag. */
6562 *pfinish_frag
= finish_frag
;
6568 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6570 xtensa_isa isa
= xtensa_default_isa
;
6571 int slot
, chosen_slot
;
6573 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6574 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6575 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6577 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6578 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6580 if (slot
== chosen_slot
)
6581 vinsn
->slots
[slot
] = *tinsn
;
6584 vinsn
->slots
[slot
].opcode
=
6585 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6586 vinsn
->slots
[slot
].ntok
= 0;
6587 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6594 emit_single_op (TInsn
*orig_insn
)
6597 IStack istack
; /* put instructions into here */
6598 symbolS
*lit_sym
= NULL
;
6599 symbolS
*label_sym
= NULL
;
6601 istack_init (&istack
);
6603 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6604 Because the scheduling and bundling characteristics of movi and
6605 l32r or const16 are so different, we can do much better if we relax
6606 it prior to scheduling and bundling, rather than after. */
6607 if ((orig_insn
->opcode
== xtensa_movi_opcode
6608 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6609 && !cur_vinsn
.inside_bundle
6610 && (orig_insn
->tok
[1].X_op
== O_symbol
6611 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6612 && !orig_insn
->is_specific_opcode
&& use_transform ())
6613 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6615 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6618 for (i
= 0; i
< istack
.ninsn
; i
++)
6620 TInsn
*insn
= &istack
.insn
[i
];
6621 switch (insn
->insn_type
)
6624 assert (lit_sym
== NULL
);
6625 lit_sym
= xg_assemble_literal (insn
);
6629 static int relaxed_sym_idx
= 0;
6630 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6631 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6633 assert (label_sym
== NULL
);
6634 label_sym
= symbol_find_or_make (label
);
6643 xg_resolve_literals (insn
, lit_sym
);
6645 xg_resolve_labels (insn
, label_sym
);
6647 bundle_tinsn (insn
, &v
);
6662 total_frag_text_expansion (fragS
*fragP
)
6665 int total_expansion
= 0;
6667 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6668 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6670 return total_expansion
;
6674 /* Emit a vliw instruction to the current fragment. */
6677 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6679 bfd_boolean finish_frag
;
6680 bfd_boolean is_jump
= FALSE
;
6681 bfd_boolean is_branch
= FALSE
;
6682 xtensa_isa isa
= xtensa_default_isa
;
6687 struct dwarf2_line_info debug_line
;
6688 bfd_boolean loc_directive_seen
= FALSE
;
6691 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6693 if (generating_literals
)
6695 static int reported
= 0;
6697 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6698 _("cannot assemble into a literal fragment"));
6705 if (frag_now_fix () != 0
6706 && (! frag_now
->tc_frag_data
.is_insn
6707 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6708 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6709 || (directive_state
[directive_longcalls
]
6710 != frag_now
->tc_frag_data
.use_longcalls
)
6711 || (directive_state
[directive_absolute_literals
]
6712 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6714 frag_wane (frag_now
);
6716 xtensa_set_frag_assembly_state (frag_now
);
6719 if (workaround_a0_b_retw
6720 && vinsn
->num_slots
== 1
6721 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6722 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6723 && use_transform ())
6725 has_a0_b_retw
= TRUE
;
6727 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6728 After the first assembly pass we will check all of them and
6729 add a nop if needed. */
6730 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6731 frag_var (rs_machine_dependent
, 4, 4,
6732 RELAX_ADD_NOP_IF_A0_B_RETW
,
6733 frag_now
->fr_symbol
,
6734 frag_now
->fr_offset
,
6736 xtensa_set_frag_assembly_state (frag_now
);
6737 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6738 frag_var (rs_machine_dependent
, 4, 4,
6739 RELAX_ADD_NOP_IF_A0_B_RETW
,
6740 frag_now
->fr_symbol
,
6741 frag_now
->fr_offset
,
6743 xtensa_set_frag_assembly_state (frag_now
);
6746 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6748 tinsn
= &vinsn
->slots
[slot
];
6750 /* See if the instruction implies an aligned section. */
6751 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6752 record_alignment (now_seg
, 2);
6754 /* Determine the best line number for debug info. */
6755 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6756 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6757 || tinsn
->debug_line
.line
< debug_line
.line
6758 || tinsn
->debug_line
.column
< debug_line
.column
))
6759 debug_line
= tinsn
->debug_line
;
6760 if (tinsn
->loc_directive_seen
)
6761 loc_directive_seen
= TRUE
;
6764 /* Special cases for instructions that force an alignment... */
6765 /* None of these opcodes are bundle-able. */
6766 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6770 /* Remember the symbol that marks the end of the loop in the frag
6771 that marks the start of the loop. This way we can easily find
6772 the end of the loop at the beginning, without adding special code
6773 to mark the loop instructions themselves. */
6774 symbolS
*target_sym
= NULL
;
6775 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6776 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6778 xtensa_set_frag_assembly_state (frag_now
);
6779 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6781 max_fill
= get_text_align_max_fill_size
6782 (get_text_align_power (xtensa_fetch_width
),
6783 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6785 if (use_transform ())
6786 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6787 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6789 frag_var (rs_machine_dependent
, 0, 0,
6790 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6791 xtensa_set_frag_assembly_state (frag_now
);
6794 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6795 && !vinsn
->slots
[0].is_specific_opcode
)
6797 xtensa_mark_literal_pool_location ();
6798 xtensa_move_labels (frag_now
, 0);
6799 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6802 if (vinsn
->num_slots
== 1)
6804 if (workaround_a0_b_retw
&& use_transform ())
6805 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6806 is_register_writer (&vinsn
->slots
[0], "a", 0));
6808 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6809 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6812 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6814 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6816 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6818 /* vinsn_to_insnbuf will produce the error. */
6819 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6821 f
= frag_more (insn_size
+ extra_space
);
6822 xtensa_set_frag_assembly_state (frag_now
);
6823 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6826 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6827 if (vinsn
->format
== XTENSA_UNDEFINED
)
6830 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6832 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
6833 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
6836 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6838 tinsn
= &vinsn
->slots
[slot
];
6839 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6840 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6841 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6842 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6843 if (tinsn
->literal_space
!= 0)
6844 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6846 if (tinsn
->subtype
== RELAX_NARROW
)
6847 assert (vinsn
->num_slots
== 1);
6848 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6850 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6853 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6854 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6858 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6859 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6863 frag_variant (rs_machine_dependent
,
6864 extra_space
, extra_space
, RELAX_SLOTS
,
6865 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6866 xtensa_set_frag_assembly_state (frag_now
);
6869 /* Special cases for loops:
6870 close_loop_end should be inserted AFTER short_loop.
6871 Make sure that CLOSE loops are processed BEFORE short_loops
6872 when converting them. */
6874 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6875 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6876 && !vinsn
->slots
[0].is_specific_opcode
)
6878 if (workaround_short_loop
&& use_transform ())
6880 maybe_has_short_loop
= TRUE
;
6881 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6882 frag_var (rs_machine_dependent
, 4, 4,
6883 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6884 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6885 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6886 frag_var (rs_machine_dependent
, 4, 4,
6887 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6888 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6891 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6892 loop at least 12 bytes away from another loop's end. */
6893 if (workaround_close_loop_end
&& use_transform ())
6895 maybe_has_close_loop_end
= TRUE
;
6896 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6897 frag_var (rs_machine_dependent
, 12, 12,
6898 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6899 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6903 if (use_transform ())
6907 assert (finish_frag
);
6908 frag_var (rs_machine_dependent
,
6909 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6911 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6912 xtensa_set_frag_assembly_state (frag_now
);
6914 else if (is_branch
&& do_align_targets ())
6916 assert (finish_frag
);
6917 frag_var (rs_machine_dependent
,
6918 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6919 RELAX_MAYBE_UNREACHABLE
,
6920 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6921 xtensa_set_frag_assembly_state (frag_now
);
6922 frag_var (rs_machine_dependent
,
6924 RELAX_MAYBE_DESIRE_ALIGN
,
6925 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6926 xtensa_set_frag_assembly_state (frag_now
);
6930 /* Now, if the original opcode was a call... */
6931 if (do_align_targets ()
6932 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6934 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6935 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6936 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6937 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6938 xtensa_set_frag_assembly_state (frag_now
);
6941 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6943 frag_wane (frag_now
);
6945 xtensa_set_frag_assembly_state (frag_now
);
6950 /* xtensa_end and helper functions. */
6952 static void xtensa_cleanup_align_frags (void);
6953 static void xtensa_fix_target_frags (void);
6954 static void xtensa_mark_narrow_branches (void);
6955 static void xtensa_mark_zcl_first_insns (void);
6956 static void xtensa_mark_difference_of_two_symbols (void);
6957 static void xtensa_fix_a0_b_retw_frags (void);
6958 static void xtensa_fix_b_j_loop_end_frags (void);
6959 static void xtensa_fix_close_loop_end_frags (void);
6960 static void xtensa_fix_short_loop_frags (void);
6961 static void xtensa_sanity_check (void);
6962 static void xtensa_add_config_info (void);
6967 directive_balance ();
6968 xtensa_flush_pending_output ();
6970 past_xtensa_end
= TRUE
;
6972 xtensa_move_literals ();
6974 xtensa_reorder_segments ();
6975 xtensa_cleanup_align_frags ();
6976 xtensa_fix_target_frags ();
6977 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6978 xtensa_fix_a0_b_retw_frags ();
6979 if (workaround_b_j_loop_end
)
6980 xtensa_fix_b_j_loop_end_frags ();
6982 /* "close_loop_end" should be processed BEFORE "short_loop". */
6983 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6984 xtensa_fix_close_loop_end_frags ();
6986 if (workaround_short_loop
&& maybe_has_short_loop
)
6987 xtensa_fix_short_loop_frags ();
6989 xtensa_mark_narrow_branches ();
6990 xtensa_mark_zcl_first_insns ();
6992 xtensa_sanity_check ();
6994 xtensa_add_config_info ();
6999 xtensa_cleanup_align_frags (void)
7004 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7005 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7008 /* Walk over all of the fragments in a subsection. */
7009 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7011 if ((fragP
->fr_type
== rs_align
7012 || fragP
->fr_type
== rs_align_code
7013 || (fragP
->fr_type
== rs_machine_dependent
7014 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7015 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7016 && fragP
->fr_fix
== 0)
7018 fragS
*next
= fragP
->fr_next
;
7021 && next
->fr_fix
== 0
7022 && next
->fr_type
== rs_machine_dependent
7023 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7026 next
= next
->fr_next
;
7029 /* If we don't widen branch targets, then they
7030 will be easier to align. */
7031 if (fragP
->tc_frag_data
.is_branch_target
7032 && fragP
->fr_opcode
== fragP
->fr_literal
7033 && fragP
->fr_type
== rs_machine_dependent
7034 && fragP
->fr_subtype
== RELAX_SLOTS
7035 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7037 if (fragP
->fr_type
== rs_machine_dependent
7038 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7039 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7045 /* Re-process all of the fragments looking to convert all of the
7046 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7047 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7048 Otherwise, convert to a .fill 0. */
7051 xtensa_fix_target_frags (void)
7056 /* When this routine is called, all of the subsections are still intact
7057 so we walk over subsections instead of sections. */
7058 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7059 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7063 /* Walk over all of the fragments in a subsection. */
7064 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7066 if (fragP
->fr_type
== rs_machine_dependent
7067 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7069 if (next_frag_is_branch_target (fragP
))
7070 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7079 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7082 xtensa_mark_narrow_branches (void)
7087 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7088 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7091 /* Walk over all of the fragments in a subsection. */
7092 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7094 if (fragP
->fr_type
== rs_machine_dependent
7095 && fragP
->fr_subtype
== RELAX_SLOTS
7096 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7100 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7101 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7103 if (vinsn
.num_slots
== 1
7104 && xtensa_opcode_is_branch (xtensa_default_isa
,
7105 vinsn
.slots
[0].opcode
) == 1
7106 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7107 && is_narrow_branch_guaranteed_in_range (fragP
,
7110 fragP
->fr_subtype
= RELAX_SLOTS
;
7111 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7112 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7120 /* A branch is typically widened only when its target is out of
7121 range. However, we would like to widen them to align a subsequent
7122 branch target when possible.
7124 Because the branch relaxation code is so convoluted, the optimal solution
7125 (combining the two cases) is difficult to get right in all circumstances.
7126 We therefore go with an "almost as good" solution, where we only
7127 use for alignment narrow branches that definitely will not expand to a
7128 jump and a branch. These functions find and mark these cases. */
7130 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7131 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7132 We start counting beginning with the frag after the 2-byte branch, so the
7133 maximum offset is (4 - 2) + 63 = 65. */
7134 #define MAX_IMMED6 65
7136 static offsetT
unrelaxed_frag_max_size (fragS
*);
7139 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7141 const expressionS
*expr
= &tinsn
->tok
[1];
7142 symbolS
*symbolP
= expr
->X_add_symbol
;
7143 offsetT max_distance
= expr
->X_add_number
;
7146 if (expr
->X_op
!= O_symbol
)
7149 target_frag
= symbol_get_frag (symbolP
);
7151 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7152 if (is_branch_jmp_to_next (tinsn
, fragP
))
7155 /* The branch doesn't branch over it's own frag,
7156 but over the subsequent ones. */
7157 fragP
= fragP
->fr_next
;
7158 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7160 max_distance
+= unrelaxed_frag_max_size (fragP
);
7161 fragP
= fragP
->fr_next
;
7163 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7170 xtensa_mark_zcl_first_insns (void)
7175 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7176 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7179 /* Walk over all of the fragments in a subsection. */
7180 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7182 if (fragP
->fr_type
== rs_machine_dependent
7183 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7184 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7186 /* Find the loop frag. */
7187 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7188 /* Find the first insn frag. */
7189 targ_frag
= next_non_empty_frag (targ_frag
);
7191 /* Of course, sometimes (mostly for toy test cases) a
7192 zero-cost loop instruction is the last in a section. */
7195 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7196 /* Do not widen a frag that is the first instruction of a
7197 zero-cost loop. It makes that loop harder to align. */
7198 if (targ_frag
->fr_type
== rs_machine_dependent
7199 && targ_frag
->fr_subtype
== RELAX_SLOTS
7200 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7203 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7204 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7207 frag_wane (targ_frag
);
7208 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7212 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7220 /* Some difference-of-symbols expressions make it out to the linker. Some
7221 don't. If one does, then the linker can optimize between the two labels.
7222 If it doesn't, then the linker shouldn't. */
7225 xtensa_mark_difference_of_two_symbols (void)
7229 for (expr_sym
= expr_symbols
; expr_sym
;
7230 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7232 expressionS
*expr
= symbol_get_value_expression (expr_sym
);
7234 if (expr
->X_op
== O_subtract
)
7236 symbolS
*left
= expr
->X_add_symbol
;
7237 symbolS
*right
= expr
->X_op_symbol
;
7239 /* Difference of two symbols not in the same section
7240 are handled with relocations in the linker. */
7241 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7246 if (symbol_get_frag (left
)->fr_address
7247 <= symbol_get_frag (right
)->fr_address
)
7249 start
= symbol_get_frag (left
);
7250 end
= symbol_get_frag (right
);
7254 start
= symbol_get_frag (right
);
7255 end
= symbol_get_frag (left
);
7259 start
->tc_frag_data
.is_no_transform
= 1;
7260 start
= start
->fr_next
;
7262 while (start
&& start
->fr_address
< end
->fr_address
);
7269 /* Re-process all of the fragments looking to convert all of the
7270 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7271 conditional branch or a retw/retw.n, convert this frag to one that
7272 will generate a NOP. In any case close it off with a .fill 0. */
7274 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7277 xtensa_fix_a0_b_retw_frags (void)
7282 /* When this routine is called, all of the subsections are still intact
7283 so we walk over subsections instead of sections. */
7284 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7285 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7289 /* Walk over all of the fragments in a subsection. */
7290 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7292 if (fragP
->fr_type
== rs_machine_dependent
7293 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7295 if (next_instrs_are_b_retw (fragP
))
7297 if (fragP
->tc_frag_data
.is_no_transform
)
7298 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7300 relax_frag_add_nop (fragP
);
7310 next_instrs_are_b_retw (fragS
*fragP
)
7312 xtensa_opcode opcode
;
7314 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7315 static xtensa_insnbuf insnbuf
= NULL
;
7316 static xtensa_insnbuf slotbuf
= NULL
;
7317 xtensa_isa isa
= xtensa_default_isa
;
7320 bfd_boolean branch_seen
= FALSE
;
7324 insnbuf
= xtensa_insnbuf_alloc (isa
);
7325 slotbuf
= xtensa_insnbuf_alloc (isa
);
7328 if (next_fragP
== NULL
)
7331 /* Check for the conditional branch. */
7332 xtensa_insnbuf_from_chars
7333 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7334 fmt
= xtensa_format_decode (isa
, insnbuf
);
7335 if (fmt
== XTENSA_UNDEFINED
)
7338 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7340 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7341 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7343 branch_seen
= (branch_seen
7344 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7350 offset
+= xtensa_format_length (isa
, fmt
);
7351 if (offset
== next_fragP
->fr_fix
)
7353 next_fragP
= next_non_empty_frag (next_fragP
);
7357 if (next_fragP
== NULL
)
7360 /* Check for the retw/retw.n. */
7361 xtensa_insnbuf_from_chars
7362 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7363 fmt
= xtensa_format_decode (isa
, insnbuf
);
7365 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7366 have no problems. */
7367 if (fmt
== XTENSA_UNDEFINED
7368 || xtensa_format_num_slots (isa
, fmt
) != 1)
7371 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7372 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7374 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7381 /* Re-process all of the fragments looking to convert all of the
7382 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7383 loop end label, convert this frag to one that will generate a NOP.
7384 In any case close it off with a .fill 0. */
7386 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7389 xtensa_fix_b_j_loop_end_frags (void)
7394 /* When this routine is called, all of the subsections are still intact
7395 so we walk over subsections instead of sections. */
7396 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7397 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7401 /* Walk over all of the fragments in a subsection. */
7402 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7404 if (fragP
->fr_type
== rs_machine_dependent
7405 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7407 if (next_instr_is_loop_end (fragP
))
7409 if (fragP
->tc_frag_data
.is_no_transform
)
7410 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7412 relax_frag_add_nop (fragP
);
7422 next_instr_is_loop_end (fragS
*fragP
)
7424 const fragS
*next_fragP
;
7426 if (next_frag_is_loop_target (fragP
))
7429 next_fragP
= next_non_empty_frag (fragP
);
7430 if (next_fragP
== NULL
)
7433 if (!next_frag_is_loop_target (next_fragP
))
7436 /* If the size is >= 3 then there is more than one instruction here.
7437 The hardware bug will not fire. */
7438 if (next_fragP
->fr_fix
> 3)
7445 /* Re-process all of the fragments looking to convert all of the
7446 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7447 not MY loop's loop end within 12 bytes, add enough nops here to
7448 make it at least 12 bytes away. In any case close it off with a
7451 static offsetT min_bytes_to_other_loop_end
7452 (fragS
*, fragS
*, offsetT
);
7455 xtensa_fix_close_loop_end_frags (void)
7460 /* When this routine is called, all of the subsections are still intact
7461 so we walk over subsections instead of sections. */
7462 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7463 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7467 fragS
*current_target
= NULL
;
7469 /* Walk over all of the fragments in a subsection. */
7470 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7472 if (fragP
->fr_type
== rs_machine_dependent
7473 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7474 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7475 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7478 && fragP
->fr_type
== rs_machine_dependent
7479 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7482 int bytes_added
= 0;
7484 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7485 /* Max out at 12. */
7486 min_bytes
= min_bytes_to_other_loop_end
7487 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7489 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7491 if (fragP
->tc_frag_data
.is_no_transform
)
7492 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7495 while (min_bytes
+ bytes_added
7496 < REQUIRED_LOOP_DIVIDING_BYTES
)
7500 if (fragP
->fr_var
< length
)
7501 as_fatal (_("fr_var %lu < length %d"),
7502 (long) fragP
->fr_var
, length
);
7505 assemble_nop (length
,
7506 fragP
->fr_literal
+ fragP
->fr_fix
);
7507 fragP
->fr_fix
+= length
;
7508 fragP
->fr_var
-= length
;
7510 bytes_added
+= length
;
7516 assert (fragP
->fr_type
!= rs_machine_dependent
7517 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7523 static offsetT
unrelaxed_frag_min_size (fragS
*);
7526 min_bytes_to_other_loop_end (fragS
*fragP
,
7527 fragS
*current_target
,
7531 fragS
*current_fragP
;
7533 for (current_fragP
= fragP
;
7535 current_fragP
= current_fragP
->fr_next
)
7537 if (current_fragP
->tc_frag_data
.is_loop_target
7538 && current_fragP
!= current_target
)
7541 offset
+= unrelaxed_frag_min_size (current_fragP
);
7543 if (offset
>= max_size
)
7551 unrelaxed_frag_min_size (fragS
*fragP
)
7553 offsetT size
= fragP
->fr_fix
;
7555 /* Add fill size. */
7556 if (fragP
->fr_type
== rs_fill
)
7557 size
+= fragP
->fr_offset
;
7564 unrelaxed_frag_max_size (fragS
*fragP
)
7566 offsetT size
= fragP
->fr_fix
;
7567 switch (fragP
->fr_type
)
7570 /* Empty frags created by the obstack allocation scheme
7571 end up with type 0. */
7576 size
+= fragP
->fr_offset
;
7584 /* No further adjustments needed. */
7586 case rs_machine_dependent
:
7587 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7588 size
+= fragP
->fr_var
;
7591 /* We had darn well better know how big it is. */
7600 /* Re-process all of the fragments looking to convert all
7601 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7604 1) the instruction size count to the loop end label
7605 is too short (<= 2 instructions),
7606 2) loop has a jump or branch in it
7609 1) workaround_all_short_loops is TRUE
7610 2) The generating loop was a 'loopgtz' or 'loopnez'
7611 3) the instruction size count to the loop end label is too short
7613 then convert this frag (and maybe the next one) to generate a NOP.
7614 In any case close it off with a .fill 0. */
7616 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7617 static bfd_boolean
branch_before_loop_end (fragS
*);
7620 xtensa_fix_short_loop_frags (void)
7625 /* When this routine is called, all of the subsections are still intact
7626 so we walk over subsections instead of sections. */
7627 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7628 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7631 fragS
*current_target
= NULL
;
7632 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7634 /* Walk over all of the fragments in a subsection. */
7635 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7637 if (fragP
->fr_type
== rs_machine_dependent
7638 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7639 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7642 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7643 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7644 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7645 current_opcode
= t_insn
.opcode
;
7646 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7647 current_opcode
) == 1);
7650 if (fragP
->fr_type
== rs_machine_dependent
7651 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7653 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7654 && (branch_before_loop_end (fragP
->fr_next
)
7655 || (workaround_all_short_loops
7656 && current_opcode
!= XTENSA_UNDEFINED
7657 && current_opcode
!= xtensa_loop_opcode
)))
7659 if (fragP
->tc_frag_data
.is_no_transform
)
7660 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7662 relax_frag_add_nop (fragP
);
7671 static int unrelaxed_frag_min_insn_count (fragS
*);
7674 count_insns_to_loop_end (fragS
*base_fragP
,
7675 bfd_boolean count_relax_add
,
7678 fragS
*fragP
= NULL
;
7683 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7685 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7686 if (insn_count
>= max_count
)
7689 if (count_relax_add
)
7691 if (fragP
->fr_type
== rs_machine_dependent
7692 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7694 /* In order to add the appropriate number of
7695 NOPs, we count an instruction for downstream
7698 if (insn_count
>= max_count
)
7708 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7710 xtensa_isa isa
= xtensa_default_isa
;
7711 static xtensa_insnbuf insnbuf
= NULL
;
7715 if (!fragP
->tc_frag_data
.is_insn
)
7719 insnbuf
= xtensa_insnbuf_alloc (isa
);
7721 /* Decode the fixed instructions. */
7722 while (offset
< fragP
->fr_fix
)
7726 xtensa_insnbuf_from_chars
7727 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7728 fmt
= xtensa_format_decode (isa
, insnbuf
);
7730 if (fmt
== XTENSA_UNDEFINED
)
7732 as_fatal (_("undecodable instruction in instruction frag"));
7735 offset
+= xtensa_format_length (isa
, fmt
);
7743 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7746 branch_before_loop_end (fragS
*base_fragP
)
7750 for (fragP
= base_fragP
;
7751 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7752 fragP
= fragP
->fr_next
)
7754 if (unrelaxed_frag_has_b_j (fragP
))
7762 unrelaxed_frag_has_b_j (fragS
*fragP
)
7764 static xtensa_insnbuf insnbuf
= NULL
;
7765 xtensa_isa isa
= xtensa_default_isa
;
7768 if (!fragP
->tc_frag_data
.is_insn
)
7772 insnbuf
= xtensa_insnbuf_alloc (isa
);
7774 /* Decode the fixed instructions. */
7775 while (offset
< fragP
->fr_fix
)
7780 xtensa_insnbuf_from_chars
7781 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7782 fmt
= xtensa_format_decode (isa
, insnbuf
);
7783 if (fmt
== XTENSA_UNDEFINED
)
7786 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7788 xtensa_opcode opcode
=
7789 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7790 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7791 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7794 offset
+= xtensa_format_length (isa
, fmt
);
7800 /* Checks to be made after initial assembly but before relaxation. */
7802 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7803 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7806 xtensa_sanity_check (void)
7813 as_where (&file_name
, &line
);
7814 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7815 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7819 /* Walk over all of the fragments in a subsection. */
7820 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7822 if (fragP
->fr_type
== rs_machine_dependent
7823 && fragP
->fr_subtype
== RELAX_SLOTS
7824 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7826 static xtensa_insnbuf insnbuf
= NULL
;
7829 if (fragP
->fr_opcode
!= NULL
)
7832 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7833 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7834 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7836 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7837 t_insn
.opcode
) == 1)
7839 if (is_empty_loop (&t_insn
, fragP
))
7841 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7842 as_bad (_("invalid empty loop"));
7844 if (!is_local_forward_loop (&t_insn
, fragP
))
7846 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7847 as_bad (_("loop target does not follow "
7848 "loop instruction in section"));
7855 new_logical_line (file_name
, line
);
7859 #define LOOP_IMMED_OPN 1
7861 /* Return TRUE if the loop target is the next non-zero fragment. */
7864 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7866 const expressionS
*expr
;
7870 if (insn
->insn_type
!= ITYPE_INSN
)
7873 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7876 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7879 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7881 if (expr
->X_op
!= O_symbol
)
7884 symbolP
= expr
->X_add_symbol
;
7888 if (symbol_get_frag (symbolP
) == NULL
)
7891 if (S_GET_VALUE (symbolP
) != 0)
7894 /* Walk through the zero-size fragments from this one. If we find
7895 the target fragment, then this is a zero-size loop. */
7897 for (next_fragP
= fragP
->fr_next
;
7899 next_fragP
= next_fragP
->fr_next
)
7901 if (next_fragP
== symbol_get_frag (symbolP
))
7903 if (next_fragP
->fr_fix
!= 0)
7911 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7913 const expressionS
*expr
;
7917 if (insn
->insn_type
!= ITYPE_INSN
)
7920 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7923 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7926 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7928 if (expr
->X_op
!= O_symbol
)
7931 symbolP
= expr
->X_add_symbol
;
7935 if (symbol_get_frag (symbolP
) == NULL
)
7938 /* Walk through fragments until we find the target.
7939 If we do not find the target, then this is an invalid loop. */
7941 for (next_fragP
= fragP
->fr_next
;
7943 next_fragP
= next_fragP
->fr_next
)
7945 if (next_fragP
== symbol_get_frag (symbolP
))
7953 #define XTINFO_NAME "Xtensa_Info"
7954 #define XTINFO_NAMESZ 12
7955 #define XTINFO_TYPE 1
7958 xtensa_add_config_info (void)
7964 info_sec
= subseg_new (".xtensa.info", 0);
7965 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7967 data
= xmalloc (100);
7968 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7969 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
7970 sz
= strlen (data
) + 1;
7972 /* Add enough null terminators to pad to a word boundary. */
7975 while ((sz
& 3) != 0);
7977 /* Follow the standard note section layout:
7978 First write the length of the name string. */
7980 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
7982 /* Next comes the length of the "descriptor", i.e., the actual data. */
7984 md_number_to_chars (p
, (valueT
) sz
, 4);
7986 /* Write the note type. */
7988 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
7990 /* Write the name field. */
7991 p
= frag_more (XTINFO_NAMESZ
);
7992 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
7994 /* Finally, write the descriptor. */
7996 memcpy (p
, data
, sz
);
8002 /* Alignment Functions. */
8005 get_text_align_power (unsigned target_size
)
8007 if (target_size
<= 4)
8009 assert (target_size
== 8);
8015 get_text_align_max_fill_size (int align_pow
,
8016 bfd_boolean use_nops
,
8017 bfd_boolean use_no_density
)
8020 return (1 << align_pow
);
8022 return 3 * (1 << align_pow
);
8024 return 1 + (1 << align_pow
);
8028 /* Calculate the minimum bytes of fill needed at "address" to align a
8029 target instruction of size "target_size" so that it does not cross a
8030 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8031 the fill can be an arbitrary number of bytes. Otherwise, the space must
8032 be filled by NOP instructions. */
8035 get_text_align_fill_size (addressT address
,
8038 bfd_boolean use_nops
,
8039 bfd_boolean use_no_density
)
8041 addressT alignment
, fill
, fill_limit
, fill_step
;
8042 bfd_boolean skip_one
= FALSE
;
8044 alignment
= (1 << align_pow
);
8045 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8049 fill_limit
= alignment
;
8052 else if (!use_no_density
)
8054 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8055 fill_limit
= alignment
* 2;
8061 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8062 fill_limit
= alignment
* 3;
8066 /* Try all fill sizes until finding one that works. */
8067 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8069 if (skip_one
&& fill
== 1)
8071 if ((address
+ fill
) >> align_pow
8072 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8081 branch_align_power (segT sec
)
8083 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8084 is aligned to at least an 8-byte boundary, then a branch target need
8085 only fit within an 8-byte aligned block of memory to avoid a stall.
8086 Otherwise, try to fit branch targets within 4-byte aligned blocks
8087 (which may be insufficient, e.g., if the section has no alignment, but
8088 it's good enough). */
8089 if (xtensa_fetch_width
== 8)
8091 if (get_recorded_alignment (sec
) >= 3)
8095 assert (xtensa_fetch_width
== 4);
8101 /* This will assert if it is not possible. */
8104 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8110 assert (fill_size
% 3 == 0);
8111 return (fill_size
/ 3);
8114 assert (fill_size
!= 1); /* Bad argument. */
8116 while (fill_size
> 1)
8119 if (fill_size
== 2 || fill_size
== 4)
8121 fill_size
-= insn_size
;
8124 assert (fill_size
!= 1); /* Bad algorithm. */
8130 get_text_align_nth_nop_size (offsetT fill_size
,
8132 bfd_boolean use_no_density
)
8139 assert (fill_size
!= 1); /* Bad argument. */
8141 while (fill_size
> 1)
8144 if (fill_size
== 2 || fill_size
== 4)
8146 fill_size
-= insn_size
;
8156 /* For the given fragment, find the appropriate address
8157 for it to begin at if we are using NOPs to align it. */
8160 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8162 /* The rule is: get next fragment's FIRST instruction. Find
8163 the smallest number of bytes that need to be added to
8164 ensure that the next fragment's FIRST instruction will fit
8167 E.G., 2 bytes : 0, 1, 2 mod 4
8170 If the FIRST instruction MIGHT be relaxed,
8171 assume that it will become a 3-byte instruction.
8173 Note again here that LOOP instructions are not bundleable,
8174 and this relaxation only applies to LOOP opcodes. */
8177 int first_insn_size
;
8179 addressT pre_opcode_bytes
;
8182 xtensa_opcode opcode
;
8183 bfd_boolean is_loop
;
8185 assert (fragP
->fr_type
== rs_machine_dependent
);
8186 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8188 /* Find the loop frag. */
8189 first_insn
= next_non_empty_frag (fragP
);
8190 /* Now find the first insn frag. */
8191 first_insn
= next_non_empty_frag (first_insn
);
8193 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8195 loop_insn_size
= xg_get_single_size (opcode
);
8197 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8198 pre_opcode_bytes
+= loop_insn_size
;
8200 /* For loops, the alignment depends on the size of the
8201 instruction following the loop, not the LOOP instruction. */
8203 if (first_insn
== NULL
)
8204 first_insn_size
= xtensa_fetch_width
;
8206 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8208 /* If it was 8, then we'll need a larger alignment for the section. */
8209 align_power
= get_text_align_power (first_insn_size
);
8210 record_alignment (now_seg
, align_power
);
8212 fill_size
= get_text_align_fill_size
8213 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8214 fragP
->tc_frag_data
.is_no_density
);
8216 return address
+ fill_size
;
8220 /* 3 mechanisms for relaxing an alignment:
8222 Align to a power of 2.
8223 Align so the next fragment's instruction does not cross a word boundary.
8224 Align the current instruction so that if the next instruction
8225 were 3 bytes, it would not cross a word boundary.
8229 zeros - This is easy; always insert zeros.
8230 nops - 3-byte and 2-byte instructions
8234 >=5 : 3-byte instruction + fn (n-3)
8235 widening - widen previous instructions. */
8238 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8240 addressT target_address
, loop_insn_offset
;
8242 xtensa_opcode loop_opcode
;
8243 bfd_boolean is_loop
;
8246 offsetT branch_align
;
8248 assert (fragP
->fr_type
== rs_machine_dependent
);
8249 switch (fragP
->fr_subtype
)
8251 case RELAX_DESIRE_ALIGN
:
8252 target_size
= next_frag_format_size (fragP
);
8253 if (target_size
== XTENSA_UNDEFINED
)
8255 align_power
= branch_align_power (now_seg
);
8256 branch_align
= 1 << align_power
;
8257 /* Don't count on the section alignment being as large as the target. */
8258 if (target_size
> branch_align
)
8259 target_size
= branch_align
;
8260 opt_diff
= get_text_align_fill_size (address
, align_power
,
8261 target_size
, FALSE
, FALSE
);
8263 *max_diff
= (opt_diff
+ branch_align
8264 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8265 assert (*max_diff
>= opt_diff
);
8268 case RELAX_ALIGN_NEXT_OPCODE
:
8269 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8270 loop_insn_offset
= 0;
8271 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8274 /* If the loop has been expanded then the LOOP instruction
8275 could be at an offset from this fragment. */
8276 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8278 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8280 /* In an ideal world, which is what we are shooting for here,
8281 we wouldn't need to use any NOPs immediately prior to the
8282 LOOP instruction. If this approach fails, relax_frag_loop_align
8283 will call get_noop_aligned_address. */
8285 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8286 align_power
= get_text_align_power (target_size
),
8287 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8288 target_size
, FALSE
, FALSE
);
8290 *max_diff
= xtensa_fetch_width
8291 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8292 - target_size
+ opt_diff
;
8293 assert (*max_diff
>= opt_diff
);
8304 /* md_relax_frag Hook and Helper Functions. */
8306 static long relax_frag_loop_align (fragS
*, long);
8307 static long relax_frag_for_align (fragS
*, long);
8308 static long relax_frag_immed
8309 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8312 /* Return the number of bytes added to this fragment, given that the
8313 input has been stretched already by "stretch". */
8316 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8318 xtensa_isa isa
= xtensa_default_isa
;
8319 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8320 long new_stretch
= 0;
8324 static xtensa_insnbuf vbuf
= NULL
;
8325 int slot
, num_slots
;
8328 as_where (&file_name
, &line
);
8329 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8331 fragP
->tc_frag_data
.unreported_expansion
= 0;
8333 switch (fragP
->fr_subtype
)
8335 case RELAX_ALIGN_NEXT_OPCODE
:
8336 /* Always convert. */
8337 if (fragP
->tc_frag_data
.relax_seen
)
8338 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8341 case RELAX_LOOP_END
:
8345 case RELAX_LOOP_END_ADD_NOP
:
8346 /* Add a NOP and switch to .fill 0. */
8347 new_stretch
= relax_frag_add_nop (fragP
);
8351 case RELAX_DESIRE_ALIGN
:
8352 /* Do nothing. The narrowing before this frag will either align
8357 case RELAX_LITERAL_FINAL
:
8360 case RELAX_LITERAL_NR
:
8362 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8363 assert (unreported
== lit_size
);
8364 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8365 fragP
->fr_var
-= lit_size
;
8366 fragP
->fr_fix
+= lit_size
;
8372 vbuf
= xtensa_insnbuf_alloc (isa
);
8374 xtensa_insnbuf_from_chars
8375 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8376 fmt
= xtensa_format_decode (isa
, vbuf
);
8377 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8379 for (slot
= 0; slot
< num_slots
; slot
++)
8381 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8384 if (fragP
->tc_frag_data
.relax_seen
)
8385 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8389 case RELAX_IMMED_STEP1
:
8390 case RELAX_IMMED_STEP2
:
8391 case RELAX_IMMED_STEP3
:
8392 /* Place the immediate. */
8393 new_stretch
+= relax_frag_immed
8394 (now_seg
, fragP
, stretch
,
8395 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8396 fmt
, slot
, stretched_p
, FALSE
);
8400 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8406 case RELAX_LITERAL_POOL_BEGIN
:
8407 case RELAX_LITERAL_POOL_END
:
8408 case RELAX_MAYBE_UNREACHABLE
:
8409 case RELAX_MAYBE_DESIRE_ALIGN
:
8410 /* No relaxation required. */
8413 case RELAX_FILL_NOP
:
8414 case RELAX_UNREACHABLE
:
8415 if (fragP
->tc_frag_data
.relax_seen
)
8416 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8420 as_bad (_("bad relaxation state"));
8423 /* Tell gas we need another relaxation pass. */
8424 if (! fragP
->tc_frag_data
.relax_seen
)
8426 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8430 new_logical_line (file_name
, line
);
8436 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8438 addressT old_address
, old_next_address
, old_size
;
8439 addressT new_address
, new_next_address
, new_size
;
8442 /* All the frags with relax_frag_for_alignment prior to this one in the
8443 section have been done, hopefully eliminating the need for a NOP here.
8444 But, this will put it in if necessary. */
8446 /* Calculate the old address of this fragment and the next fragment. */
8447 old_address
= fragP
->fr_address
- stretch
;
8448 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8449 fragP
->tc_frag_data
.text_expansion
[0]);
8450 old_size
= old_next_address
- old_address
;
8452 /* Calculate the new address of this fragment and the next fragment. */
8453 new_address
= fragP
->fr_address
;
8455 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8456 new_size
= new_next_address
- new_address
;
8458 growth
= new_size
- old_size
;
8460 /* Fix up the text_expansion field and return the new growth. */
8461 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8466 /* Add a NOP instruction. */
8469 relax_frag_add_nop (fragS
*fragP
)
8471 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8472 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8473 assemble_nop (length
, nop_buf
);
8474 fragP
->tc_frag_data
.is_insn
= TRUE
;
8476 if (fragP
->fr_var
< length
)
8478 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8482 fragP
->fr_fix
+= length
;
8483 fragP
->fr_var
-= length
;
8488 static long future_alignment_required (fragS
*, long);
8491 relax_frag_for_align (fragS
*fragP
, long stretch
)
8493 /* Overview of the relaxation procedure for alignment:
8494 We can widen with NOPs or by widening instructions or by filling
8495 bytes after jump instructions. Find the opportune places and widen
8496 them if necessary. */
8501 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8502 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8503 || (fragP
->fr_subtype
== RELAX_SLOTS
8504 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8506 stretch_me
= future_alignment_required (fragP
, stretch
);
8507 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8513 /* We expanded on a previous pass. Can we shrink now? */
8514 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8515 if (shrink
<= stretch
&& stretch
> 0)
8517 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8523 /* Below here, diff > 0. */
8524 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8530 /* Return the address of the next frag that should be aligned.
8532 By "address" we mean the address it _would_ be at if there
8533 is no action taken to align it between here and the target frag.
8534 In other words, if no narrows and no fill nops are used between
8535 here and the frag to align, _even_if_ some of the frags we use
8536 to align targets have already expanded on a previous relaxation
8539 Also, count each frag that may be used to help align the target.
8541 Return 0 if there are no frags left in the chain that need to be
8545 find_address_of_next_align_frag (fragS
**fragPP
,
8549 bfd_boolean
*paddable
)
8551 fragS
*fragP
= *fragPP
;
8552 addressT address
= fragP
->fr_address
;
8554 /* Do not reset the counts to 0. */
8558 /* Limit this to a small search. */
8559 if (*widens
>= (int) xtensa_fetch_width
)
8564 address
+= fragP
->fr_fix
;
8566 if (fragP
->fr_type
== rs_fill
)
8567 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8568 else if (fragP
->fr_type
== rs_machine_dependent
)
8570 switch (fragP
->fr_subtype
)
8572 case RELAX_UNREACHABLE
:
8576 case RELAX_FILL_NOP
:
8578 if (!fragP
->tc_frag_data
.is_no_density
)
8583 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8588 address
+= total_frag_text_expansion (fragP
);;
8592 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8595 case RELAX_ALIGN_NEXT_OPCODE
:
8596 case RELAX_DESIRE_ALIGN
:
8600 case RELAX_MAYBE_UNREACHABLE
:
8601 case RELAX_MAYBE_DESIRE_ALIGN
:
8606 /* Just punt if we don't know the type. */
8613 /* Just punt if we don't know the type. */
8617 fragP
= fragP
->fr_next
;
8625 static long bytes_to_stretch (fragS
*, int, int, int, int);
8628 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8630 fragS
*this_frag
= fragP
;
8634 int narrow_nops
= 0;
8635 bfd_boolean paddable
= FALSE
;
8636 offsetT local_opt_diff
;
8639 int stretch_amount
= 0;
8640 int local_stretch_amount
;
8641 int global_stretch_amount
;
8643 address
= find_address_of_next_align_frag
8644 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8648 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8649 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8651 frag_wane (this_frag
);
8655 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8656 opt_diff
= local_opt_diff
;
8657 assert (opt_diff
>= 0);
8658 assert (max_diff
>= opt_diff
);
8663 fragP
= fragP
->fr_next
;
8665 while (fragP
&& opt_diff
< max_diff
&& address
)
8667 /* We only use these to determine if we can exit early
8668 because there will be plenty of ways to align future
8670 int glob_widens
= 0;
8673 bfd_boolean glob_pad
= 0;
8674 address
= find_address_of_next_align_frag
8675 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8676 /* If there is a padable portion, then skip. */
8677 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8682 offsetT next_m_diff
;
8683 offsetT next_o_diff
;
8685 /* Downrange frags haven't had stretch added to them yet. */
8688 /* The address also includes any text expansion from this
8689 frag in a previous pass, but we don't want that. */
8690 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8692 /* Assume we are going to move at least opt_diff. In
8693 reality, we might not be able to, but assuming that
8694 we will helps catch cases where moving opt_diff pushes
8695 the next target from aligned to unaligned. */
8696 address
+= opt_diff
;
8698 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8700 /* Now cleanup for the adjustments to address. */
8701 next_o_diff
+= opt_diff
;
8702 next_m_diff
+= opt_diff
;
8703 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8704 opt_diff
= next_o_diff
;
8705 if (next_m_diff
< max_diff
)
8706 max_diff
= next_m_diff
;
8707 fragP
= fragP
->fr_next
;
8711 /* If there are enough wideners in between, do it. */
8714 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8716 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8721 local_stretch_amount
8722 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8723 num_widens
, local_opt_diff
);
8724 global_stretch_amount
8725 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8726 num_widens
, opt_diff
);
8727 /* If the condition below is true, then the frag couldn't
8728 stretch the correct amount for the global case, so we just
8729 optimize locally. We'll rely on the subsequent frags to get
8730 the correct alignment in the global case. */
8731 if (global_stretch_amount
< local_stretch_amount
)
8732 stretch_amount
= local_stretch_amount
;
8734 stretch_amount
= global_stretch_amount
;
8736 if (this_frag
->fr_subtype
== RELAX_SLOTS
8737 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8738 assert (stretch_amount
<= 1);
8739 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8741 if (this_frag
->tc_frag_data
.is_no_density
)
8742 assert (stretch_amount
== 3 || stretch_amount
== 0);
8744 assert (stretch_amount
<= 3);
8747 return stretch_amount
;
8751 /* The idea: widen everything you can to get a target or loop aligned,
8752 then start using NOPs.
8754 When we must have a NOP, here is a table of how we decide
8755 (so you don't have to fight through the control flow below):
8757 wide_nops = the number of wide NOPs available for aligning
8758 narrow_nops = the number of narrow NOPs available for aligning
8759 (a subset of wide_nops)
8760 widens = the number of narrow instructions that should be widened
8767 b 0 1 1 (case 3a makes this case unnecessary)
8770 c 0 1 2 (case 4a makes this case unnecessary)
8773 c 0 2 1 (case 5b makes this case unnecessary)
8776 c 0 1 4 (case 6b makes this case unnecessary)
8777 d 1 1 1 (case 6a makes this case unnecessary)
8778 e 0 2 2 (case 6a makes this case unnecessary)
8779 f 0 3 0 (case 6a makes this case unnecessary)
8782 c 1 1 2 (case 7b makes this case unnecessary)
8783 d 0 1 5 (case 7a makes this case unnecessary)
8784 e 0 2 3 (case 7b makes this case unnecessary)
8785 f 0 3 1 (case 7b makes this case unnecessary)
8786 g 1 2 1 (case 7b makes this case unnecessary)
8790 bytes_to_stretch (fragS
*this_frag
,
8796 int bytes_short
= desired_diff
- num_widens
;
8798 assert (desired_diff
>= 0 && desired_diff
< 8);
8799 if (desired_diff
== 0)
8802 assert (wide_nops
> 0 || num_widens
> 0);
8804 /* Always prefer widening to NOP-filling. */
8805 if (bytes_short
< 0)
8807 /* There are enough RELAX_NARROW frags after this one
8808 to align the target without widening this frag in any way. */
8812 if (bytes_short
== 0)
8814 /* Widen every narrow between here and the align target
8815 and the align target will be properly aligned. */
8816 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8822 /* From here we will need at least one NOP to get an alignment.
8823 However, we may not be able to align at all, in which case,
8825 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8827 switch (desired_diff
)
8832 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8833 return 2; /* case 2 */
8839 return 3; /* case 3a */
8841 if (num_widens
>= 1 && wide_nops
== 1)
8842 return 3; /* case 4a */
8843 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8844 return 2; /* case 4b */
8847 if (num_widens
>= 2 && wide_nops
== 1)
8848 return 3; /* case 5a */
8849 /* We will need two nops. Are there enough nops
8850 between here and the align target? */
8851 if (wide_nops
< 2 || narrow_nops
== 0)
8853 /* Are there other nops closer that can serve instead? */
8854 if (wide_nops
> 2 && narrow_nops
> 1)
8856 /* Take the density one first, because there might not be
8857 another density one available. */
8858 if (!this_frag
->tc_frag_data
.is_no_density
)
8859 return 2; /* case 5b narrow */
8861 return 3; /* case 5b wide */
8865 return 3; /* case 6a */
8866 else if (num_widens
>= 3 && wide_nops
== 1)
8867 return 3; /* case 6b */
8870 if (wide_nops
== 1 && num_widens
>= 4)
8871 return 3; /* case 7a */
8872 else if (wide_nops
== 2 && num_widens
>= 1)
8873 return 3; /* case 7b */
8881 /* We will need a NOP no matter what, but should we widen
8882 this instruction to help?
8884 This is a RELAX_NARROW frag. */
8885 switch (desired_diff
)
8894 if (wide_nops
>= 1 && num_widens
== 1)
8895 return 1; /* case 4a */
8898 if (wide_nops
>= 1 && num_widens
== 2)
8899 return 1; /* case 5a */
8903 return 0; /* case 6a */
8904 else if (wide_nops
>= 1 && num_widens
== 3)
8905 return 1; /* case 6b */
8908 if (wide_nops
>= 1 && num_widens
== 4)
8909 return 1; /* case 7a */
8910 else if (wide_nops
>= 2 && num_widens
== 1)
8911 return 1; /* case 7b */
8924 relax_frag_immed (segT segP
,
8931 bfd_boolean estimate_only
)
8935 bfd_boolean negatable_branch
= FALSE
;
8936 bfd_boolean branch_jmp_to_next
= FALSE
;
8937 bfd_boolean wide_insn
= FALSE
;
8938 xtensa_isa isa
= xtensa_default_isa
;
8940 offsetT frag_offset
;
8943 int num_text_bytes
, num_literal_bytes
;
8944 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8946 assert (fragP
->fr_opcode
!= NULL
);
8948 xg_clear_vinsn (&cur_vinsn
);
8949 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8950 if (cur_vinsn
.num_slots
> 1)
8953 tinsn
= cur_vinsn
.slots
[slot
];
8954 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8956 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8959 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8960 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8962 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8964 old_size
= xtensa_format_length (isa
, fmt
);
8966 /* Special case: replace a branch to the next instruction with a NOP.
8967 This is required to work around a hardware bug in T1040.0 and also
8968 serves as an optimization. */
8970 if (branch_jmp_to_next
8971 && ((old_size
== 2) || (old_size
== 3))
8972 && !next_frag_is_loop_target (fragP
))
8975 /* Here is the fun stuff: Get the immediate field from this
8976 instruction. If it fits, we are done. If not, find the next
8977 instruction sequence that fits. */
8979 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8980 istack_init (&istack
);
8981 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8982 min_steps
, stretch
);
8983 if (num_steps
< min_steps
)
8985 as_fatal (_("internal error: relaxation failed"));
8989 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8991 as_fatal (_("internal error: relaxation requires too many steps"));
8995 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8997 /* Figure out the number of bytes needed. */
8999 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9001 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9003 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9005 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9008 num_text_bytes
+= old_size
;
9009 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9010 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9012 total_text_diff
= num_text_bytes
- old_size
;
9013 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9015 /* It MUST get larger. If not, we could get an infinite loop. */
9016 assert (num_text_bytes
>= 0);
9017 assert (literal_diff
>= 0);
9018 assert (total_text_diff
>= 0);
9020 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9021 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9022 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9023 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9025 /* Find the associated expandable literal for this. */
9026 if (literal_diff
!= 0)
9028 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9031 assert (literal_diff
== 4);
9032 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9034 /* We expect that the literal section state has NOT been
9036 assert (lit_fragP
->fr_type
== rs_machine_dependent
9037 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9038 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9040 /* We need to mark this section for another iteration
9046 if (negatable_branch
&& istack
.ninsn
> 1)
9047 update_next_frag_state (fragP
);
9049 return this_text_diff
;
9053 /* md_convert_frag Hook and Helper Functions. */
9055 static void convert_frag_align_next_opcode (fragS
*);
9056 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9057 static void convert_frag_fill_nop (fragS
*);
9058 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9061 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9063 static xtensa_insnbuf vbuf
= NULL
;
9064 xtensa_isa isa
= xtensa_default_isa
;
9071 as_where (&file_name
, &line
);
9072 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9074 switch (fragp
->fr_subtype
)
9076 case RELAX_ALIGN_NEXT_OPCODE
:
9077 /* Always convert. */
9078 convert_frag_align_next_opcode (fragp
);
9081 case RELAX_DESIRE_ALIGN
:
9082 /* Do nothing. If not aligned already, too bad. */
9086 case RELAX_LITERAL_FINAL
:
9091 vbuf
= xtensa_insnbuf_alloc (isa
);
9093 xtensa_insnbuf_from_chars
9094 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9095 fmt
= xtensa_format_decode (isa
, vbuf
);
9096 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9098 for (slot
= 0; slot
< num_slots
; slot
++)
9100 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9103 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9107 case RELAX_IMMED_STEP1
:
9108 case RELAX_IMMED_STEP2
:
9109 case RELAX_IMMED_STEP3
:
9110 /* Place the immediate. */
9113 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9118 /* This is OK because some slots could have
9119 relaxations and others have none. */
9125 case RELAX_UNREACHABLE
:
9126 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9127 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9128 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9132 case RELAX_MAYBE_UNREACHABLE
:
9133 case RELAX_MAYBE_DESIRE_ALIGN
:
9137 case RELAX_FILL_NOP
:
9138 convert_frag_fill_nop (fragp
);
9141 case RELAX_LITERAL_NR
:
9142 if (use_literal_section
)
9144 /* This should have been handled during relaxation. When
9145 relaxing a code segment, literals sometimes need to be
9146 added to the corresponding literal segment. If that
9147 literal segment has already been relaxed, then we end up
9148 in this situation. Marking the literal segments as data
9149 would make this happen less often (since GAS always relaxes
9150 code before data), but we could still get into trouble if
9151 there are instructions in a segment that is not marked as
9152 containing code. Until we can implement a better solution,
9153 cheat and adjust the addresses of all the following frags.
9154 This could break subsequent alignments, but the linker's
9155 literal coalescing will do that anyway. */
9158 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9159 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9160 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9163 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9167 as_bad (_("invalid relaxation fragment result"));
9172 new_logical_line (file_name
, line
);
9177 convert_frag_align_next_opcode (fragS
*fragp
)
9179 char *nop_buf
; /* Location for Writing. */
9180 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9181 addressT aligned_address
;
9185 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9187 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9188 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9189 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9191 for (nop
= 0; nop
< nop_count
; nop
++)
9194 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9196 assemble_nop (nop_size
, nop_buf
);
9197 nop_buf
+= nop_size
;
9200 fragp
->fr_fix
+= fill_size
;
9201 fragp
->fr_var
-= fill_size
;
9206 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9208 TInsn tinsn
, single_target
;
9209 int size
, old_size
, diff
;
9210 offsetT frag_offset
;
9213 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9215 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9217 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9218 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9219 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9224 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9226 /* No conversion. */
9231 assert (fragP
->fr_opcode
!= NULL
);
9233 /* Frags in this relaxation state should only contain
9234 single instruction bundles. */
9235 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9237 /* Just convert it to a wide form.... */
9239 old_size
= xg_get_single_size (tinsn
.opcode
);
9241 tinsn_init (&single_target
);
9242 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9244 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9246 as_bad (_("unable to widen instruction"));
9250 size
= xg_get_single_size (single_target
.opcode
);
9251 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9254 diff
= size
- old_size
;
9256 assert (diff
<= fragP
->fr_var
);
9257 fragP
->fr_var
-= diff
;
9258 fragP
->fr_fix
+= diff
;
9266 convert_frag_fill_nop (fragS
*fragP
)
9268 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9269 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9270 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9271 - fragP
->fr_address
- fragP
->fr_fix
));
9274 /* No conversion. */
9278 assemble_nop (size
, loc
);
9279 fragP
->tc_frag_data
.is_insn
= TRUE
;
9280 fragP
->fr_var
-= size
;
9281 fragP
->fr_fix
+= size
;
9286 static fixS
*fix_new_exp_in_seg
9287 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9288 bfd_reloc_code_real_type
);
9289 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9292 convert_frag_immed (segT segP
,
9298 char *immed_instr
= fragP
->fr_opcode
;
9300 bfd_boolean expanded
= FALSE
;
9301 bfd_boolean branch_jmp_to_next
= FALSE
;
9302 char *fr_opcode
= fragP
->fr_opcode
;
9303 xtensa_isa isa
= xtensa_default_isa
;
9304 bfd_boolean wide_insn
= FALSE
;
9306 bfd_boolean is_loop
;
9308 assert (fr_opcode
!= NULL
);
9310 xg_clear_vinsn (&cur_vinsn
);
9312 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9313 if (cur_vinsn
.num_slots
> 1)
9316 orig_tinsn
= cur_vinsn
.slots
[slot
];
9317 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9319 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9321 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9322 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9324 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9326 /* Conversion just inserts a NOP and marks the fix as completed. */
9327 bytes
= xtensa_format_length (isa
, fmt
);
9330 cur_vinsn
.slots
[slot
].opcode
=
9331 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9332 cur_vinsn
.slots
[slot
].ntok
= 0;
9336 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9337 assert (bytes
== 2 || bytes
== 3);
9338 build_nop (&cur_vinsn
.slots
[0], bytes
);
9339 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9341 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9342 xtensa_insnbuf_to_chars
9343 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9348 /* Here is the fun stuff: Get the immediate field from this
9349 instruction. If it fits, we're done. If not, find the next
9350 instruction sequence that fits. */
9354 symbolS
*lit_sym
= NULL
;
9356 int target_offset
= 0;
9359 symbolS
*gen_label
= NULL
;
9360 offsetT frag_offset
;
9361 bfd_boolean first
= TRUE
;
9362 bfd_boolean last_is_jump
;
9364 /* It does not fit. Find something that does and
9365 convert immediately. */
9366 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9367 istack_init (&istack
);
9368 xg_assembly_relax (&istack
, &orig_tinsn
,
9369 segP
, fragP
, frag_offset
, min_steps
, 0);
9371 old_size
= xtensa_format_length (isa
, fmt
);
9373 /* Assemble this right inline. */
9375 /* First, create the mapping from a label name to the REAL label. */
9377 for (i
= 0; i
< istack
.ninsn
; i
++)
9379 TInsn
*tinsn
= &istack
.insn
[i
];
9382 switch (tinsn
->insn_type
)
9385 if (lit_sym
!= NULL
)
9386 as_bad (_("multiple literals in expansion"));
9387 /* First find the appropriate space in the literal pool. */
9388 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9389 if (lit_frag
== NULL
)
9390 as_bad (_("no registered fragment for literal"));
9391 if (tinsn
->ntok
!= 1)
9392 as_bad (_("number of literal tokens != 1"));
9394 /* Set the literal symbol and add a fixup. */
9395 lit_sym
= lit_frag
->fr_symbol
;
9399 if (align_targets
&& !is_loop
)
9401 fragS
*unreach
= fragP
->fr_next
;
9402 while (!(unreach
->fr_type
== rs_machine_dependent
9403 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9404 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9406 unreach
= unreach
->fr_next
;
9409 assert (unreach
->fr_type
== rs_machine_dependent
9410 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9411 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9413 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9415 assert (gen_label
== NULL
);
9416 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9417 fr_opcode
- fragP
->fr_literal
9418 + target_offset
, fragP
);
9422 if (first
&& wide_insn
)
9424 target_offset
+= xtensa_format_length (isa
, fmt
);
9426 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9427 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9430 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9437 last_is_jump
= FALSE
;
9438 for (i
= 0; i
< istack
.ninsn
; i
++)
9440 TInsn
*tinsn
= &istack
.insn
[i
];
9444 bfd_reloc_code_real_type reloc_type
;
9446 switch (tinsn
->insn_type
)
9449 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9450 /* Already checked. */
9451 assert (lit_frag
!= NULL
);
9452 assert (lit_sym
!= NULL
);
9453 assert (tinsn
->ntok
== 1);
9455 target_seg
= S_GET_SEGMENT (lit_sym
);
9456 assert (target_seg
);
9457 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9458 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9459 &tinsn
->tok
[0], FALSE
, reloc_type
);
9466 xg_resolve_labels (tinsn
, gen_label
);
9467 xg_resolve_literals (tinsn
, lit_sym
);
9468 if (wide_insn
&& first
)
9471 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9473 cur_vinsn
.slots
[slot
] = *tinsn
;
9477 cur_vinsn
.slots
[slot
].opcode
=
9478 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9479 cur_vinsn
.slots
[slot
].ntok
= 0;
9481 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9482 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9483 (unsigned char *) immed_instr
, 0);
9484 fragP
->tc_frag_data
.is_insn
= TRUE
;
9485 size
= xtensa_format_length (isa
, fmt
);
9486 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9489 (tinsn
, immed_instr
+ size
, fragP
,
9490 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9491 size
+= xg_get_single_size (tinsn
->opcode
);
9496 size
= xg_get_single_size (tinsn
->opcode
);
9497 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9498 immed_instr
- fragP
->fr_literal
, TRUE
);
9500 immed_instr
+= size
;
9506 diff
= total_size
- old_size
;
9510 assert (diff
<= fragP
->fr_var
);
9511 fragP
->fr_var
-= diff
;
9512 fragP
->fr_fix
+= diff
;
9515 /* Check for undefined immediates in LOOP instructions. */
9519 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9520 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9522 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9525 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9526 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9528 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9533 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9534 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9536 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9538 /* Add an expansion note on the expanded instruction. */
9539 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9540 &orig_tinsn
.tok
[0], TRUE
,
9541 BFD_RELOC_XTENSA_ASM_EXPAND
);
9546 /* Add a new fix expression into the desired segment. We have to
9547 switch to that segment to do this. */
9550 fix_new_exp_in_seg (segT new_seg
,
9557 bfd_reloc_code_real_type r_type
)
9561 subsegT subseg
= now_subseg
;
9563 assert (new_seg
!= 0);
9564 subseg_set (new_seg
, new_subseg
);
9566 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9567 subseg_set (seg
, subseg
);
9572 /* Relax a loop instruction so that it can span loop >256 bytes.
9578 addi as, as, lo8 (label-.L1)
9579 addmi as, as, mid8 (label-.L1)
9590 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9595 unsigned long target
;
9596 static xtensa_insnbuf insnbuf
= NULL
;
9597 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9598 xtensa_isa isa
= xtensa_default_isa
;
9599 addressT loop_offset
;
9600 addressT addi_offset
= 9;
9601 addressT addmi_offset
= 12;
9606 insnbuf
= xtensa_insnbuf_alloc (isa
);
9608 /* Get the loop offset. */
9609 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9611 /* Validate that there really is a LOOP at the loop_offset. Because
9612 loops are not bundleable, we can assume that the instruction will be
9614 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9615 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9617 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9618 addi_offset
+= loop_offset
;
9619 addmi_offset
+= loop_offset
;
9621 assert (tinsn
->ntok
== 2);
9622 if (tinsn
->tok
[1].X_op
== O_constant
)
9623 target
= tinsn
->tok
[1].X_add_number
;
9624 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9626 /* Find the fragment. */
9627 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9628 assert (S_GET_SEGMENT (sym
) == segP
9629 || S_GET_SEGMENT (sym
) == absolute_section
);
9630 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9634 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9638 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9639 loop_length_hi
= loop_length
& ~0x0ff;
9640 loop_length_lo
= loop_length
& 0x0ff;
9641 if (loop_length_lo
>= 128)
9643 loop_length_lo
-= 256;
9644 loop_length_hi
+= 256;
9647 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9648 32512. If the loop is larger than that, then we just fail. */
9649 if (loop_length_hi
> 32512)
9650 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9651 _("loop too long for LOOP instruction"));
9653 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9654 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9656 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9657 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9659 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9660 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9662 fragP
->tc_frag_data
.is_insn
= TRUE
;
9663 xtensa_insnbuf_to_chars
9664 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9666 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9667 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9668 xtensa_insnbuf_to_chars
9669 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9671 /* Walk through all of the frags from here to the loop end
9672 and mark them as no_transform to keep them from being modified
9673 by the linker. If we ever have a relocation for the
9674 addi/addmi of the difference of two symbols we can remove this. */
9677 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9678 next_fragP
= next_fragP
->fr_next
)
9680 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9681 if (next_fragP
->tc_frag_data
.is_loop_target
)
9683 if (target_count
== 2)
9689 /* A map that keeps information on a per-subsegment basis. This is
9690 maintained during initial assembly, but is invalid once the
9691 subsegments are smashed together. I.E., it cannot be used during
9694 typedef struct subseg_map_struct
9702 float total_freq
; /* fall-through + branch target frequency */
9703 float target_freq
; /* branch target frequency alone */
9705 struct subseg_map_struct
*next
;
9709 static subseg_map
*sseg_map
= NULL
;
9712 get_subseg_info (segT seg
, subsegT subseg
)
9714 subseg_map
*subseg_e
;
9716 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9718 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9726 add_subseg_info (segT seg
, subsegT subseg
)
9728 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9729 memset (subseg_e
, 0, sizeof (subseg_map
));
9730 subseg_e
->seg
= seg
;
9731 subseg_e
->subseg
= subseg
;
9732 subseg_e
->flags
= 0;
9733 /* Start off considering every branch target very important. */
9734 subseg_e
->target_freq
= 1.0;
9735 subseg_e
->total_freq
= 1.0;
9736 subseg_e
->next
= sseg_map
;
9737 sseg_map
= subseg_e
;
9743 get_last_insn_flags (segT seg
, subsegT subseg
)
9745 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9747 return subseg_e
->flags
;
9753 set_last_insn_flags (segT seg
,
9758 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9760 subseg_e
= add_subseg_info (seg
, subseg
);
9762 subseg_e
->flags
|= fl
;
9764 subseg_e
->flags
&= ~fl
;
9769 get_subseg_total_freq (segT seg
, subsegT subseg
)
9771 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9773 return subseg_e
->total_freq
;
9779 get_subseg_target_freq (segT seg
, subsegT subseg
)
9781 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9783 return subseg_e
->target_freq
;
9789 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9791 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9793 subseg_e
= add_subseg_info (seg
, subseg
);
9794 subseg_e
->total_freq
= total_f
;
9795 subseg_e
->target_freq
= target_f
;
9799 /* Segment Lists and emit_state Stuff. */
9802 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9807 segT literal_section
= head
->seg
;
9809 /* Move the literal section to the front of the section list. */
9810 assert (literal_section
);
9811 if (literal_section
!= stdoutput
->sections
)
9813 bfd_section_list_remove (stdoutput
, literal_section
);
9814 bfd_section_list_prepend (stdoutput
, literal_section
);
9821 static void mark_literal_frags (seg_list
*);
9824 xtensa_move_literals (void)
9827 frchainS
*frchain_from
, *frchain_to
;
9828 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9829 fragS
**frag_splice
;
9832 fixS
*fix
, *next_fix
, **fix_splice
;
9835 mark_literal_frags (literal_head
->next
);
9837 if (use_literal_section
)
9840 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9842 /* Keep the literals for .init and .fini in separate sections. */
9843 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9844 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9847 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9848 search_frag
= frchain_from
->frch_root
;
9849 literal_pool
= NULL
;
9851 frag_splice
= &(frchain_from
->frch_root
);
9853 while (!search_frag
->tc_frag_data
.literal_frag
)
9855 assert (search_frag
->fr_fix
== 0
9856 || search_frag
->fr_type
== rs_align
);
9857 search_frag
= search_frag
->fr_next
;
9860 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9861 == RELAX_LITERAL_POOL_BEGIN
);
9862 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9864 /* Make sure that all the frags in this series are closed, and
9865 that there is at least one left over of zero-size. This
9866 prevents us from making a segment with an frchain without any
9868 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9869 xtensa_set_frag_assembly_state (frag_now
);
9870 last_frag
= frag_now
;
9871 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9872 xtensa_set_frag_assembly_state (frag_now
);
9874 while (search_frag
!= frag_now
)
9876 next_frag
= search_frag
->fr_next
;
9878 /* First, move the frag out of the literal section and
9879 to the appropriate place. */
9880 if (search_frag
->tc_frag_data
.literal_frag
)
9882 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9883 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9884 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9885 assert (frchain_to
);
9887 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
9888 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9890 *frag_splice
= next_frag
;
9891 search_frag
->fr_next
= insert_after
->fr_next
;
9892 insert_after
->fr_next
= search_frag
;
9893 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9894 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
9896 /* Now move any fixups associated with this frag to the
9898 fix
= frchain_from
->fix_root
;
9899 fix_splice
= &(frchain_from
->fix_root
);
9902 next_fix
= fix
->fx_next
;
9903 if (fix
->fx_frag
== search_frag
)
9905 *fix_splice
= next_fix
;
9906 fix
->fx_next
= frchain_to
->fix_root
;
9907 frchain_to
->fix_root
= fix
;
9908 if (frchain_to
->fix_tail
== NULL
)
9909 frchain_to
->fix_tail
= fix
;
9912 fix_splice
= &(fix
->fx_next
);
9915 search_frag
= next_frag
;
9918 if (frchain_from
->fix_root
!= NULL
)
9920 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9921 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9923 assert (frchain_from
->fix_root
== NULL
);
9925 frchain_from
->fix_tail
= NULL
;
9926 xtensa_restore_emit_state (&state
);
9929 /* Now fix up the SEGMENT value for all the literal symbols. */
9930 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9932 symbolS
*lit_sym
= lit
->sym
;
9933 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9935 S_SET_SEGMENT (lit_sym
, dest_seg
);
9940 /* Walk over all the frags for segments in a list and mark them as
9941 containing literals. As clunky as this is, we can't rely on frag_var
9942 and frag_variant to get called in all situations. */
9945 mark_literal_frags (seg_list
*segment
)
9947 frchainS
*frchain_from
;
9952 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9953 search_frag
= frchain_from
->frch_root
;
9956 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9957 search_frag
= search_frag
->fr_next
;
9959 segment
= segment
->next
;
9965 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9967 /* Move all of the sections in the section list to come
9968 after "after" in the gnu segment list. */
9973 segT literal_section
= head
->seg
;
9975 /* Move the literal section after "after". */
9976 assert (literal_section
);
9977 if (literal_section
!= after
)
9979 bfd_section_list_remove (stdoutput
, literal_section
);
9980 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9988 /* Push all the literal segments to the end of the gnu list. */
9991 xtensa_reorder_segments (void)
9998 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10004 /* Now that we have the last section, push all the literal
10005 sections to the end. */
10006 xtensa_reorder_seg_list (literal_head
, last_sec
);
10008 /* Now perform the final error check. */
10009 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10011 assert (new_count
== old_count
);
10015 /* Change the emit state (seg, subseg, and frag related stuff) to the
10016 correct location. Return a emit_state which can be passed to
10017 xtensa_restore_emit_state to return to current fragment. */
10020 xtensa_switch_to_literal_fragment (emit_state
*result
)
10022 if (directive_state
[directive_absolute_literals
])
10024 segT lit4_seg
= cache_literal_section (TRUE
);
10025 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10028 xtensa_switch_to_non_abs_literal_fragment (result
);
10030 /* Do a 4-byte align here. */
10031 frag_align (2, 0, 0);
10032 record_alignment (now_seg
, 2);
10037 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10039 static bfd_boolean recursive
= FALSE
;
10040 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10042 bfd_boolean is_init
=
10043 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10044 bfd_boolean is_fini
=
10045 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10047 if (pool_location
== NULL
10048 && !use_literal_section
10050 && !is_init
&& ! is_fini
)
10052 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10054 /* When we mark a literal pool location, we want to put a frag in
10055 the literal pool that points to it. But to do that, we want to
10056 switch_to_literal_fragment. But literal sections don't have
10057 literal pools, so their location is always null, so we would
10058 recurse forever. This is kind of hacky, but it works. */
10061 xtensa_mark_literal_pool_location ();
10065 lit_seg
= cache_literal_section (FALSE
);
10066 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10068 if (!use_literal_section
10069 && !is_init
&& !is_fini
10070 && get_literal_pool_location (now_seg
) != pool_location
)
10072 /* Close whatever frag is there. */
10073 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10074 xtensa_set_frag_assembly_state (frag_now
);
10075 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10076 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10077 xtensa_set_frag_assembly_state (frag_now
);
10082 /* Call this function before emitting data into the literal section.
10083 This is a helper function for xtensa_switch_to_literal_fragment.
10084 This is similar to a .section new_now_seg subseg. */
10087 xtensa_switch_section_emit_state (emit_state
*state
,
10089 subsegT new_now_subseg
)
10091 state
->name
= now_seg
->name
;
10092 state
->now_seg
= now_seg
;
10093 state
->now_subseg
= now_subseg
;
10094 state
->generating_literals
= generating_literals
;
10095 generating_literals
++;
10096 subseg_set (new_now_seg
, new_now_subseg
);
10100 /* Use to restore the emitting into the normal place. */
10103 xtensa_restore_emit_state (emit_state
*state
)
10105 generating_literals
= state
->generating_literals
;
10106 subseg_set (state
->now_seg
, state
->now_subseg
);
10110 /* Predicate function used to look up a section in a particular group. */
10113 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10115 const char *gname
= inf
;
10116 const char *group_name
= elf_group_name (sec
);
10118 return (group_name
== gname
10119 || (group_name
!= NULL
10121 && strcmp (group_name
, gname
) == 0));
10125 /* Get the literal section to be used for the current text section.
10126 The result may be cached in the default_lit_sections structure. */
10129 cache_literal_section (bfd_boolean use_abs_literals
)
10131 const char *text_name
, *group_name
= 0;
10132 char *base_name
, *name
, *suffix
;
10134 segT seg
, current_section
;
10135 int current_subsec
;
10136 bfd_boolean linkonce
= FALSE
;
10138 /* Save the current section/subsection. */
10139 current_section
= now_seg
;
10140 current_subsec
= now_subseg
;
10142 /* Clear the cached values if they are no longer valid. */
10143 if (now_seg
!= default_lit_sections
.current_text_seg
)
10145 default_lit_sections
.current_text_seg
= now_seg
;
10146 default_lit_sections
.lit_seg
= NULL
;
10147 default_lit_sections
.lit4_seg
= NULL
;
10150 /* Check if the literal section is already cached. */
10151 if (use_abs_literals
)
10152 pcached
= &default_lit_sections
.lit4_seg
;
10154 pcached
= &default_lit_sections
.lit_seg
;
10159 text_name
= default_lit_sections
.lit_prefix
;
10160 if (! text_name
|| ! *text_name
)
10162 text_name
= segment_name (current_section
);
10163 group_name
= elf_group_name (current_section
);
10164 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10167 base_name
= use_abs_literals
? ".lit4" : ".literal";
10170 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10171 sprintf (name
, "%s.%s", base_name
, group_name
);
10173 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10175 suffix
= strchr (text_name
+ linkonce_len
, '.');
10177 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10178 + (suffix
? strlen (suffix
) : 0));
10179 strcpy (name
, ".gnu.linkonce");
10180 strcat (name
, base_name
);
10182 strcat (name
, suffix
);
10187 /* If the section name ends with ".text", then replace that suffix
10188 instead of appending an additional suffix. */
10189 size_t len
= strlen (text_name
);
10190 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10193 name
= xmalloc (len
+ strlen (base_name
) + 1);
10194 strcpy (name
, text_name
);
10195 strcpy (name
+ len
, base_name
);
10198 /* Canonicalize section names to allow renaming literal sections.
10199 The group name, if any, came from the current text section and
10200 has already been canonicalized. */
10201 name
= tc_canonicalize_symbol_name (name
);
10203 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10204 (void *) group_name
);
10209 seg
= subseg_force_new (name
, 0);
10211 if (! use_abs_literals
)
10213 /* Add the newly created literal segment to the list. */
10214 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10216 n
->next
= literal_head
->next
;
10217 literal_head
->next
= n
;
10220 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10221 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10222 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10224 elf_group_name (seg
) = group_name
;
10226 bfd_set_section_flags (stdoutput
, seg
, flags
);
10227 bfd_set_section_alignment (stdoutput
, seg
, 2);
10231 subseg_set (current_section
, current_subsec
);
10236 /* Property Tables Stuff. */
10238 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10239 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10240 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10242 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10243 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10245 static bfd_boolean
get_frag_is_literal (const fragS
*);
10246 static void xtensa_create_property_segments
10247 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10248 static void xtensa_create_xproperty_segments
10249 (frag_flags_fn
, const char *, xt_section_type
);
10250 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10251 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10252 static void add_xt_block_frags
10253 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10254 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10255 static void xtensa_frag_flags_init (frag_flags
*);
10256 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10257 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10258 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10260 /* Set up property tables after relaxation. */
10263 xtensa_post_relax_hook (void)
10265 xtensa_move_seg_list_to_beginning (literal_head
);
10267 xtensa_find_unmarked_state_frags ();
10268 xtensa_mark_frags_for_org ();
10269 xtensa_mark_difference_of_two_symbols ();
10271 xtensa_create_property_segments (get_frag_is_literal
,
10273 XTENSA_LIT_SEC_NAME
,
10275 xtensa_create_xproperty_segments (get_frag_property_flags
,
10276 XTENSA_PROP_SEC_NAME
,
10279 if (warn_unaligned_branch_targets
)
10280 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10281 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10285 /* This function is only meaningful after xtensa_move_literals. */
10288 get_frag_is_literal (const fragS
*fragP
)
10290 assert (fragP
!= NULL
);
10291 return fragP
->tc_frag_data
.is_literal
;
10296 xtensa_create_property_segments (frag_predicate property_function
,
10297 frag_predicate end_property_function
,
10298 const char *section_name_base
,
10299 xt_section_type sec_type
)
10303 /* Walk over all of the current segments.
10304 Walk over each fragment
10305 For each non-empty fragment,
10306 Build a property record (append where possible). */
10308 for (seclist
= &stdoutput
->sections
;
10309 seclist
&& *seclist
;
10310 seclist
= &(*seclist
)->next
)
10312 segT sec
= *seclist
;
10315 flags
= bfd_get_section_flags (stdoutput
, sec
);
10316 if (flags
& SEC_DEBUGGING
)
10318 if (!(flags
& SEC_ALLOC
))
10321 if (section_has_property (sec
, property_function
))
10323 segment_info_type
*xt_seg_info
;
10324 xtensa_block_info
**xt_blocks
;
10325 segT prop_sec
= xtensa_get_property_section (sec
, section_name_base
);
10327 prop_sec
->output_section
= prop_sec
;
10328 subseg_set (prop_sec
, 0);
10329 xt_seg_info
= seg_info (prop_sec
);
10330 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10332 /* Walk over all of the frchains here and add new sections. */
10333 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10334 end_property_function
);
10338 /* Now we fill them out.... */
10340 for (seclist
= &stdoutput
->sections
;
10341 seclist
&& *seclist
;
10342 seclist
= &(*seclist
)->next
)
10344 segment_info_type
*seginfo
;
10345 xtensa_block_info
*block
;
10346 segT sec
= *seclist
;
10348 seginfo
= seg_info (sec
);
10349 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10353 xtensa_block_info
*cur_block
;
10355 bfd_size_type rec_size
;
10357 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10360 rec_size
= num_recs
* 8;
10361 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10368 subseg_set (sec
, 0);
10369 frag_data
= frag_more (rec_size
);
10371 for (i
= 0; i
< num_recs
; i
++)
10375 /* Write the fixup. */
10376 assert (cur_block
);
10377 fix
= fix_new (frag_now
, i
* 8, 4,
10378 section_symbol (cur_block
->sec
),
10380 FALSE
, BFD_RELOC_32
);
10381 fix
->fx_file
= "<internal>";
10384 /* Write the length. */
10385 md_number_to_chars (&frag_data
[4 + i
* 8],
10386 cur_block
->size
, 4);
10387 cur_block
= cur_block
->next
;
10389 frag_wane (frag_now
);
10391 frag_wane (frag_now
);
10399 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10400 const char *section_name_base
,
10401 xt_section_type sec_type
)
10405 /* Walk over all of the current segments.
10406 Walk over each fragment.
10407 For each fragment that has instructions,
10408 build an instruction record (append where possible). */
10410 for (seclist
= &stdoutput
->sections
;
10411 seclist
&& *seclist
;
10412 seclist
= &(*seclist
)->next
)
10414 segT sec
= *seclist
;
10417 flags
= bfd_get_section_flags (stdoutput
, sec
);
10418 if ((flags
& SEC_DEBUGGING
)
10419 || !(flags
& SEC_ALLOC
)
10420 || (flags
& SEC_MERGE
))
10423 if (section_has_xproperty (sec
, flag_fn
))
10425 segment_info_type
*xt_seg_info
;
10426 xtensa_block_info
**xt_blocks
;
10427 segT prop_sec
= xtensa_get_property_section (sec
, section_name_base
);
10429 prop_sec
->output_section
= prop_sec
;
10430 subseg_set (prop_sec
, 0);
10431 xt_seg_info
= seg_info (prop_sec
);
10432 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10434 /* Walk over all of the frchains here and add new sections. */
10435 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10439 /* Now we fill them out.... */
10441 for (seclist
= &stdoutput
->sections
;
10442 seclist
&& *seclist
;
10443 seclist
= &(*seclist
)->next
)
10445 segment_info_type
*seginfo
;
10446 xtensa_block_info
*block
;
10447 segT sec
= *seclist
;
10449 seginfo
= seg_info (sec
);
10450 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10454 xtensa_block_info
*cur_block
;
10456 bfd_size_type rec_size
;
10458 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10461 rec_size
= num_recs
* (8 + 4);
10462 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10463 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10470 subseg_set (sec
, 0);
10471 frag_data
= frag_more (rec_size
);
10473 for (i
= 0; i
< num_recs
; i
++)
10477 /* Write the fixup. */
10478 assert (cur_block
);
10479 fix
= fix_new (frag_now
, i
* 12, 4,
10480 section_symbol (cur_block
->sec
),
10482 FALSE
, BFD_RELOC_32
);
10483 fix
->fx_file
= "<internal>";
10486 /* Write the length. */
10487 md_number_to_chars (&frag_data
[4 + i
* 12],
10488 cur_block
->size
, 4);
10489 md_number_to_chars (&frag_data
[8 + i
* 12],
10490 frag_flags_to_number (&cur_block
->flags
),
10492 cur_block
= cur_block
->next
;
10494 frag_wane (frag_now
);
10496 frag_wane (frag_now
);
10504 section_has_property (segT sec
, frag_predicate property_function
)
10506 segment_info_type
*seginfo
= seg_info (sec
);
10509 if (seginfo
&& seginfo
->frchainP
)
10511 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10513 if (property_function (fragP
)
10514 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10523 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10525 segment_info_type
*seginfo
= seg_info (sec
);
10528 if (seginfo
&& seginfo
->frchainP
)
10530 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10532 frag_flags prop_flags
;
10533 property_function (fragP
, &prop_flags
);
10534 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10542 /* Two types of block sections exist right now: literal and insns. */
10545 add_xt_block_frags (segT sec
,
10546 xtensa_block_info
**xt_block
,
10547 frag_predicate property_function
,
10548 frag_predicate end_property_function
)
10550 bfd_vma seg_offset
;
10553 /* Build it if needed. */
10554 while (*xt_block
!= NULL
)
10555 xt_block
= &(*xt_block
)->next
;
10556 /* We are either at NULL at the beginning or at the end. */
10558 /* Walk through the frags. */
10561 if (seg_info (sec
)->frchainP
)
10563 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10565 fragP
= fragP
->fr_next
)
10567 if (property_function (fragP
)
10568 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10570 if (*xt_block
!= NULL
)
10572 if ((*xt_block
)->offset
+ (*xt_block
)->size
10573 == fragP
->fr_address
)
10574 (*xt_block
)->size
+= fragP
->fr_fix
;
10576 xt_block
= &((*xt_block
)->next
);
10578 if (*xt_block
== NULL
)
10580 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10581 xmalloc (sizeof (xtensa_block_info
));
10582 new_block
->sec
= sec
;
10583 new_block
->offset
= fragP
->fr_address
;
10584 new_block
->size
= fragP
->fr_fix
;
10585 new_block
->next
= NULL
;
10586 xtensa_frag_flags_init (&new_block
->flags
);
10587 *xt_block
= new_block
;
10589 if (end_property_function
10590 && end_property_function (fragP
))
10592 xt_block
= &((*xt_block
)->next
);
10600 /* Break the encapsulation of add_xt_prop_frags here. */
10603 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10605 if (prop_flags
->is_literal
10606 || prop_flags
->is_insn
10607 || prop_flags
->is_data
10608 || prop_flags
->is_unreachable
)
10615 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10617 memset (prop_flags
, 0, sizeof (frag_flags
));
10622 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10624 xtensa_frag_flags_init (prop_flags
);
10625 if (fragP
->tc_frag_data
.is_literal
)
10626 prop_flags
->is_literal
= TRUE
;
10627 if (fragP
->tc_frag_data
.is_specific_opcode
10628 || fragP
->tc_frag_data
.is_no_transform
)
10629 prop_flags
->is_no_transform
= TRUE
;
10630 if (fragP
->tc_frag_data
.is_unreachable
)
10631 prop_flags
->is_unreachable
= TRUE
;
10632 else if (fragP
->tc_frag_data
.is_insn
)
10634 prop_flags
->is_insn
= TRUE
;
10635 if (fragP
->tc_frag_data
.is_loop_target
)
10636 prop_flags
->insn
.is_loop_target
= TRUE
;
10637 if (fragP
->tc_frag_data
.is_branch_target
)
10638 prop_flags
->insn
.is_branch_target
= TRUE
;
10639 if (fragP
->tc_frag_data
.is_no_density
)
10640 prop_flags
->insn
.is_no_density
= TRUE
;
10641 if (fragP
->tc_frag_data
.use_absolute_literals
)
10642 prop_flags
->insn
.is_abslit
= TRUE
;
10644 if (fragP
->tc_frag_data
.is_align
)
10646 prop_flags
->is_align
= TRUE
;
10647 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10648 if (xtensa_frag_flags_is_empty (prop_flags
))
10649 prop_flags
->is_data
= TRUE
;
10655 frag_flags_to_number (const frag_flags
*prop_flags
)
10658 if (prop_flags
->is_literal
)
10659 num
|= XTENSA_PROP_LITERAL
;
10660 if (prop_flags
->is_insn
)
10661 num
|= XTENSA_PROP_INSN
;
10662 if (prop_flags
->is_data
)
10663 num
|= XTENSA_PROP_DATA
;
10664 if (prop_flags
->is_unreachable
)
10665 num
|= XTENSA_PROP_UNREACHABLE
;
10666 if (prop_flags
->insn
.is_loop_target
)
10667 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10668 if (prop_flags
->insn
.is_branch_target
)
10670 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10671 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10674 if (prop_flags
->insn
.is_no_density
)
10675 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10676 if (prop_flags
->is_no_transform
)
10677 num
|= XTENSA_PROP_NO_TRANSFORM
;
10678 if (prop_flags
->insn
.is_no_reorder
)
10679 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10680 if (prop_flags
->insn
.is_abslit
)
10681 num
|= XTENSA_PROP_INSN_ABSLIT
;
10683 if (prop_flags
->is_align
)
10685 num
|= XTENSA_PROP_ALIGN
;
10686 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10694 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10695 const frag_flags
*prop_flags_2
)
10697 /* Cannot combine with an end marker. */
10699 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10701 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10703 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10706 if (prop_flags_1
->is_insn
)
10708 /* Properties of the beginning of the frag. */
10709 if (prop_flags_2
->insn
.is_loop_target
)
10711 if (prop_flags_2
->insn
.is_branch_target
)
10713 if (prop_flags_1
->insn
.is_no_density
!=
10714 prop_flags_2
->insn
.is_no_density
)
10716 if (prop_flags_1
->is_no_transform
!=
10717 prop_flags_2
->is_no_transform
)
10719 if (prop_flags_1
->insn
.is_no_reorder
!=
10720 prop_flags_2
->insn
.is_no_reorder
)
10722 if (prop_flags_1
->insn
.is_abslit
!=
10723 prop_flags_2
->insn
.is_abslit
)
10727 if (prop_flags_1
->is_align
)
10735 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10738 unsigned align_bits
;
10740 if (!xt_block
->flags
.is_align
)
10741 return xt_block
->size
;
10743 end_addr
= xt_block
->offset
+ xt_block
->size
;
10744 align_bits
= xt_block
->flags
.alignment
;
10745 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10746 return end_addr
- xt_block
->offset
;
10751 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10752 const xtensa_block_info
*xt_block_2
)
10754 if (xt_block
->sec
!= xt_block_2
->sec
)
10756 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10757 != xt_block_2
->offset
)
10760 if (xt_block_2
->size
== 0
10761 && (!xt_block_2
->flags
.is_unreachable
10762 || xt_block
->flags
.is_unreachable
))
10764 if (xt_block_2
->flags
.is_align
10765 && xt_block
->flags
.is_align
)
10767 /* Nothing needed. */
10768 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10773 if (xt_block_2
->flags
.is_align
)
10775 /* Push alignment to previous entry. */
10776 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10777 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10782 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10783 &xt_block_2
->flags
))
10786 xt_block
->size
+= xt_block_2
->size
;
10788 if (xt_block_2
->flags
.is_align
)
10790 xt_block
->flags
.is_align
= TRUE
;
10791 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10799 add_xt_prop_frags (segT sec
,
10800 xtensa_block_info
**xt_block
,
10801 frag_flags_fn property_function
)
10803 bfd_vma seg_offset
;
10806 /* Build it if needed. */
10807 while (*xt_block
!= NULL
)
10809 xt_block
= &(*xt_block
)->next
;
10811 /* We are either at NULL at the beginning or at the end. */
10813 /* Walk through the frags. */
10816 if (seg_info (sec
)->frchainP
)
10818 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
10819 fragP
= fragP
->fr_next
)
10821 xtensa_block_info tmp_block
;
10822 tmp_block
.sec
= sec
;
10823 tmp_block
.offset
= fragP
->fr_address
;
10824 tmp_block
.size
= fragP
->fr_fix
;
10825 tmp_block
.next
= NULL
;
10826 property_function (fragP
, &tmp_block
.flags
);
10828 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10829 /* && fragP->fr_fix != 0) */
10831 if ((*xt_block
) == NULL
10832 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10834 xtensa_block_info
*new_block
;
10835 if ((*xt_block
) != NULL
)
10836 xt_block
= &(*xt_block
)->next
;
10837 new_block
= (xtensa_block_info
*)
10838 xmalloc (sizeof (xtensa_block_info
));
10839 *new_block
= tmp_block
;
10840 *xt_block
= new_block
;
10848 /* op_placement_info_table */
10850 /* op_placement_info makes it easier to determine which
10851 ops can go in which slots. */
10854 init_op_placement_info_table (void)
10856 xtensa_isa isa
= xtensa_default_isa
;
10857 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10858 xtensa_opcode opcode
;
10861 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10863 op_placement_table
= (op_placement_info_table
)
10864 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10865 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10867 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10869 op_placement_info
*opi
= &op_placement_table
[opcode
];
10870 /* FIXME: Make tinsn allocation dynamic. */
10871 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10872 as_fatal (_("too many operands in instruction"));
10873 opi
->narrowest
= XTENSA_UNDEFINED
;
10874 opi
->narrowest_size
= 0x7F;
10875 opi
->narrowest_slot
= 0;
10877 opi
->num_formats
= 0;
10879 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10881 opi
->slots
[fmt
] = 0;
10882 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10884 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10886 int fmt_length
= xtensa_format_length (isa
, fmt
);
10888 set_bit (fmt
, opi
->formats
);
10889 set_bit (slot
, opi
->slots
[fmt
]);
10890 if (fmt_length
< opi
->narrowest_size
10891 || (fmt_length
== opi
->narrowest_size
10892 && (xtensa_format_num_slots (isa
, fmt
)
10893 < xtensa_format_num_slots (isa
,
10896 opi
->narrowest
= fmt
;
10897 opi
->narrowest_size
= fmt_length
;
10898 opi
->narrowest_slot
= slot
;
10903 opi
->num_formats
++;
10906 xtensa_insnbuf_free (isa
, ibuf
);
10911 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10913 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10917 /* If the opcode is available in a single slot format, return its size. */
10920 xg_get_single_size (xtensa_opcode opcode
)
10922 return op_placement_table
[opcode
].narrowest_size
;
10926 static xtensa_format
10927 xg_get_single_format (xtensa_opcode opcode
)
10929 return op_placement_table
[opcode
].narrowest
;
10934 xg_get_single_slot (xtensa_opcode opcode
)
10936 return op_placement_table
[opcode
].narrowest_slot
;
10940 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10943 istack_init (IStack
*stack
)
10945 memset (stack
, 0, sizeof (IStack
));
10951 istack_empty (IStack
*stack
)
10953 return (stack
->ninsn
== 0);
10958 istack_full (IStack
*stack
)
10960 return (stack
->ninsn
== MAX_ISTACK
);
10964 /* Return a pointer to the top IStack entry.
10965 It is an error to call this if istack_empty () is TRUE. */
10968 istack_top (IStack
*stack
)
10970 int rec
= stack
->ninsn
- 1;
10971 assert (!istack_empty (stack
));
10972 return &stack
->insn
[rec
];
10976 /* Add a new TInsn to an IStack.
10977 It is an error to call this if istack_full () is TRUE. */
10980 istack_push (IStack
*stack
, TInsn
*insn
)
10982 int rec
= stack
->ninsn
;
10983 assert (!istack_full (stack
));
10984 stack
->insn
[rec
] = *insn
;
10989 /* Clear space for the next TInsn on the IStack and return a pointer
10990 to it. It is an error to call this if istack_full () is TRUE. */
10993 istack_push_space (IStack
*stack
)
10995 int rec
= stack
->ninsn
;
10997 assert (!istack_full (stack
));
10998 insn
= &stack
->insn
[rec
];
11005 /* Remove the last pushed instruction. It is an error to call this if
11006 istack_empty () returns TRUE. */
11009 istack_pop (IStack
*stack
)
11011 int rec
= stack
->ninsn
- 1;
11012 assert (!istack_empty (stack
));
11014 tinsn_init (&stack
->insn
[rec
]);
11018 /* TInsn functions. */
11021 tinsn_init (TInsn
*dst
)
11023 memset (dst
, 0, sizeof (TInsn
));
11027 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11030 tinsn_has_symbolic_operands (const TInsn
*insn
)
11033 int n
= insn
->ntok
;
11035 assert (insn
->insn_type
== ITYPE_INSN
);
11037 for (i
= 0; i
< n
; ++i
)
11039 switch (insn
->tok
[i
].X_op
)
11053 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11055 xtensa_isa isa
= xtensa_default_isa
;
11057 int n
= insn
->ntok
;
11059 assert (insn
->insn_type
== ITYPE_INSN
);
11061 for (i
= 0; i
< n
; ++i
)
11063 switch (insn
->tok
[i
].X_op
)
11071 /* Errors for these types are caught later. */
11076 /* Symbolic immediates are only allowed on the last immediate
11077 operand. At this time, CONST16 is the only opcode where we
11078 support non-PC-relative relocations. */
11079 if (i
!= get_relaxable_immed (insn
->opcode
)
11080 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11081 && insn
->opcode
!= xtensa_const16_opcode
))
11083 as_bad (_("invalid symbolic operand"));
11092 /* For assembly code with complex expressions (e.g. subtraction),
11093 we have to build them in the literal pool so that
11094 their results are calculated correctly after relaxation.
11095 The relaxation only handles expressions that
11096 boil down to SYMBOL + OFFSET. */
11099 tinsn_has_complex_operands (const TInsn
*insn
)
11102 int n
= insn
->ntok
;
11103 assert (insn
->insn_type
== ITYPE_INSN
);
11104 for (i
= 0; i
< n
; ++i
)
11106 switch (insn
->tok
[i
].X_op
)
11122 /* Encode a TInsn opcode and its constant operands into slotbuf.
11123 Return TRUE if there is a symbol in the immediate field. This
11124 function assumes that:
11125 1) The number of operands are correct.
11126 2) The insn_type is ITYPE_INSN.
11127 3) The opcode can be encoded in the specified format and slot.
11128 4) Operands are either O_constant or O_symbol, and all constants fit. */
11131 tinsn_to_slotbuf (xtensa_format fmt
,
11134 xtensa_insnbuf slotbuf
)
11136 xtensa_isa isa
= xtensa_default_isa
;
11137 xtensa_opcode opcode
= tinsn
->opcode
;
11138 bfd_boolean has_fixup
= FALSE
;
11139 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11142 assert (tinsn
->insn_type
== ITYPE_INSN
);
11143 if (noperands
!= tinsn
->ntok
)
11144 as_fatal (_("operand number mismatch"));
11146 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11148 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11149 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11153 for (i
= 0; i
< noperands
; i
++)
11155 expressionS
*expr
= &tinsn
->tok
[i
];
11161 switch (expr
->X_op
)
11164 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11166 /* The register number has already been checked in
11167 expression_maybe_register, so we don't need to check here. */
11168 opnd_value
= expr
->X_add_number
;
11169 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11170 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11173 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11177 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11179 as_where (&file_name
, &line
);
11180 /* It is a constant and we called this function
11181 then we have to try to fit it. */
11182 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11183 expr
->X_add_number
, file_name
, line
);
11196 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11197 into a multi-slot instruction, fill the other slots with NOPs.
11198 Return TRUE if there is a symbol in the immediate field. See also the
11199 assumptions listed for tinsn_to_slotbuf. */
11202 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11204 static xtensa_insnbuf slotbuf
= 0;
11205 static vliw_insn vinsn
;
11206 xtensa_isa isa
= xtensa_default_isa
;
11207 bfd_boolean has_fixup
= FALSE
;
11212 slotbuf
= xtensa_insnbuf_alloc (isa
);
11213 xg_init_vinsn (&vinsn
);
11216 xg_clear_vinsn (&vinsn
);
11218 bundle_tinsn (tinsn
, &vinsn
);
11220 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11222 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11224 /* Only one slot may have a fix-up because the rest contains NOPs. */
11226 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11227 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11234 /* Check the instruction arguments. Return TRUE on failure. */
11237 tinsn_check_arguments (const TInsn
*insn
)
11239 xtensa_isa isa
= xtensa_default_isa
;
11240 xtensa_opcode opcode
= insn
->opcode
;
11242 if (opcode
== XTENSA_UNDEFINED
)
11244 as_bad (_("invalid opcode"));
11248 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11250 as_bad (_("too few operands"));
11254 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11256 as_bad (_("too many operands"));
11263 /* Load an instruction from its encoded form. */
11266 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11270 xg_init_vinsn (&vinsn
);
11271 vinsn_from_chars (&vinsn
, f
);
11273 *tinsn
= vinsn
.slots
[slot
];
11274 xg_free_vinsn (&vinsn
);
11279 tinsn_from_insnbuf (TInsn
*tinsn
,
11280 xtensa_insnbuf slotbuf
,
11285 xtensa_isa isa
= xtensa_default_isa
;
11287 /* Find the immed. */
11288 tinsn_init (tinsn
);
11289 tinsn
->insn_type
= ITYPE_INSN
;
11290 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11291 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11292 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11293 for (i
= 0; i
< tinsn
->ntok
; i
++)
11295 set_expr_const (&tinsn
->tok
[i
],
11296 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11297 tinsn
->opcode
, i
));
11302 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11305 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11307 xtensa_opcode opcode
= tinsn
->opcode
;
11310 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11312 opnum
= get_relaxable_immed (opcode
);
11313 assert (opnum
>= 0);
11314 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11315 fragP
->tc_frag_data
.slot_symbols
[slot
],
11316 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11322 get_num_stack_text_bytes (IStack
*istack
)
11325 int text_bytes
= 0;
11327 for (i
= 0; i
< istack
->ninsn
; i
++)
11329 TInsn
*tinsn
= &istack
->insn
[i
];
11330 if (tinsn
->insn_type
== ITYPE_INSN
)
11331 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11338 get_num_stack_literal_bytes (IStack
*istack
)
11343 for (i
= 0; i
< istack
->ninsn
; i
++)
11345 TInsn
*tinsn
= &istack
->insn
[i
];
11346 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11353 /* vliw_insn functions. */
11356 xg_init_vinsn (vliw_insn
*v
)
11359 xtensa_isa isa
= xtensa_default_isa
;
11361 xg_clear_vinsn (v
);
11363 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11364 if (v
->insnbuf
== NULL
)
11365 as_fatal (_("out of memory"));
11367 for (i
= 0; i
< MAX_SLOTS
; i
++)
11369 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11370 if (v
->slotbuf
[i
] == NULL
)
11371 as_fatal (_("out of memory"));
11377 xg_clear_vinsn (vliw_insn
*v
)
11381 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11383 v
->format
= XTENSA_UNDEFINED
;
11385 v
->inside_bundle
= FALSE
;
11387 if (xt_saved_debug_type
!= DEBUG_NONE
)
11388 debug_type
= xt_saved_debug_type
;
11390 for (i
= 0; i
< MAX_SLOTS
; i
++)
11391 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11396 vinsn_has_specific_opcodes (vliw_insn
*v
)
11400 for (i
= 0; i
< v
->num_slots
; i
++)
11402 if (v
->slots
[i
].is_specific_opcode
)
11410 xg_free_vinsn (vliw_insn
*v
)
11413 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11414 for (i
= 0; i
< MAX_SLOTS
; i
++)
11415 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11419 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11420 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11423 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11426 bfd_boolean record_fixup
)
11428 xtensa_isa isa
= xtensa_default_isa
;
11429 xtensa_format fmt
= vinsn
->format
;
11430 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11432 bfd_boolean has_fixup
= FALSE
;
11434 xtensa_format_encode (isa
, fmt
, insnbuf
);
11436 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11438 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11439 bfd_boolean tinsn_has_fixup
=
11440 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11441 vinsn
->slotbuf
[slot
]);
11443 xtensa_format_set_slot (isa
, fmt
, slot
,
11444 insnbuf
, vinsn
->slotbuf
[slot
]);
11445 if (tinsn_has_fixup
)
11448 xtensa_opcode opcode
= tinsn
->opcode
;
11449 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11452 for (i
= 0; i
< noperands
; i
++)
11454 expressionS
* expr
= &tinsn
->tok
[i
];
11455 switch (expr
->X_op
)
11460 if (get_relaxable_immed (opcode
) == i
)
11462 /* Add a fix record for the instruction, except if this
11463 function is being called prior to relaxation, i.e.,
11464 if record_fixup is false, and the instruction might
11465 be relaxed later. */
11467 || tinsn
->is_specific_opcode
11468 || !xg_is_relaxable_insn (tinsn
, 0))
11470 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11471 frag_offset
- fragP
->fr_literal
);
11475 if (expr
->X_op
!= O_symbol
)
11476 as_bad (_("invalid operand"));
11477 tinsn
->symbol
= expr
->X_add_symbol
;
11478 tinsn
->offset
= expr
->X_add_number
;
11482 as_bad (_("symbolic operand not allowed"));
11490 as_bad (_("expression too complex"));
11502 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11504 static xtensa_insnbuf insnbuf
= NULL
;
11505 static xtensa_insnbuf slotbuf
= NULL
;
11508 xtensa_isa isa
= xtensa_default_isa
;
11512 insnbuf
= xtensa_insnbuf_alloc (isa
);
11513 slotbuf
= xtensa_insnbuf_alloc (isa
);
11516 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11517 fmt
= xtensa_format_decode (isa
, insnbuf
);
11518 if (fmt
== XTENSA_UNDEFINED
)
11519 as_fatal (_("cannot decode instruction format"));
11520 vinsn
->format
= fmt
;
11521 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11523 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11525 TInsn
*tinsn
= &vinsn
->slots
[i
];
11526 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11527 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11532 /* Expression utilities. */
11534 /* Return TRUE if the expression is an integer constant. */
11537 expr_is_const (const expressionS
*s
)
11539 return (s
->X_op
== O_constant
);
11543 /* Get the expression constant.
11544 Calling this is illegal if expr_is_const () returns TRUE. */
11547 get_expr_const (const expressionS
*s
)
11549 assert (expr_is_const (s
));
11550 return s
->X_add_number
;
11554 /* Set the expression to a constant value. */
11557 set_expr_const (expressionS
*s
, offsetT val
)
11559 s
->X_op
= O_constant
;
11560 s
->X_add_number
= val
;
11561 s
->X_add_symbol
= NULL
;
11562 s
->X_op_symbol
= NULL
;
11567 expr_is_register (const expressionS
*s
)
11569 return (s
->X_op
== O_register
);
11573 /* Get the expression constant.
11574 Calling this is illegal if expr_is_const () returns TRUE. */
11577 get_expr_register (const expressionS
*s
)
11579 assert (expr_is_register (s
));
11580 return s
->X_add_number
;
11584 /* Set the expression to a symbol + constant offset. */
11587 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11589 s
->X_op
= O_symbol
;
11590 s
->X_add_symbol
= sym
;
11591 s
->X_op_symbol
= NULL
; /* unused */
11592 s
->X_add_number
= offset
;
11596 /* Return TRUE if the two expressions are equal. */
11599 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11601 if (s1
->X_op
!= s2
->X_op
)
11603 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11605 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11607 if (s1
->X_add_number
!= s2
->X_add_number
)
11614 copy_expr (expressionS
*dst
, const expressionS
*src
)
11616 memcpy (dst
, src
, sizeof (expressionS
));
11620 /* Support for the "--rename-section" option. */
11622 struct rename_section_struct
11626 struct rename_section_struct
*next
;
11629 static struct rename_section_struct
*section_rename
;
11632 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11633 entries to the section_rename list. Note: Specifying multiple
11634 renamings separated by colons is not documented and is retained only
11635 for backward compatibility. */
11638 build_section_rename (const char *arg
)
11640 struct rename_section_struct
*r
;
11641 char *this_arg
= NULL
;
11642 char *next_arg
= NULL
;
11644 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11646 char *old_name
, *new_name
;
11650 next_arg
= strchr (this_arg
, ':');
11658 old_name
= this_arg
;
11659 new_name
= strchr (this_arg
, '=');
11661 if (*old_name
== '\0')
11663 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11666 if (!new_name
|| new_name
[1] == '\0')
11668 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11675 /* Check for invalid section renaming. */
11676 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11678 if (strcmp (r
->old_name
, old_name
) == 0)
11679 as_bad (_("section %s renamed multiple times"), old_name
);
11680 if (strcmp (r
->new_name
, new_name
) == 0)
11681 as_bad (_("multiple sections remapped to output section %s"),
11686 r
= (struct rename_section_struct
*)
11687 xmalloc (sizeof (struct rename_section_struct
));
11688 r
->old_name
= xstrdup (old_name
);
11689 r
->new_name
= xstrdup (new_name
);
11690 r
->next
= section_rename
;
11691 section_rename
= r
;
11697 xtensa_section_rename (char *name
)
11699 struct rename_section_struct
*r
= section_rename
;
11701 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11703 if (strcmp (r
->old_name
, name
) == 0)
11704 return r
->new_name
;