1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 xtensa_format narrowest
;
334 /* formats is a bitfield with the Nth bit set
335 if the opcode fits in the Nth xtensa_format. */
338 /* slots[N]'s Mth bit is set if the op fits in the
339 Mth slot of the Nth xtensa_format. */
340 bitfield slots
[MAX_FORMATS
];
342 /* A count of the number of slots in a given format
343 an op can fit (i.e., the bitcount of the slot field above). */
344 char slots_in_format
[MAX_FORMATS
];
346 } op_placement_info
, *op_placement_info_table
;
348 op_placement_info_table op_placement_table
;
351 /* Extra expression types. */
353 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
354 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
355 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
368 directive_literal_prefix
,
370 directive_absolute_literals
,
371 directive_last_directive
377 bfd_boolean can_be_negated
;
380 const directive_infoS directive_info
[] =
383 { "literal", FALSE
},
385 { "transform", TRUE
},
386 { "freeregs", FALSE
},
387 { "longcalls", TRUE
},
388 { "literal_prefix", FALSE
},
389 { "schedule", TRUE
},
390 { "absolute-literals", TRUE
}
393 bfd_boolean directive_state
[] =
397 #if !XCHAL_HAVE_DENSITY
402 TRUE
, /* transform */
403 FALSE
, /* freeregs */
404 FALSE
, /* longcalls */
405 FALSE
, /* literal_prefix */
407 #if XSHAL_USE_ABSOLUTE_LITERALS
408 TRUE
/* absolute_literals */
410 FALSE
/* absolute_literals */
415 /* Directive functions. */
417 static void xtensa_begin_directive (int);
418 static void xtensa_end_directive (int);
419 static void xtensa_literal_prefix (char const *, int);
420 static void xtensa_literal_position (int);
421 static void xtensa_literal_pseudo (int);
422 static void xtensa_frequency_pseudo (int);
423 static void xtensa_elf_cons (int);
425 /* Parsing and Idiom Translation. */
427 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
429 /* Various Other Internal Functions. */
431 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
432 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
433 static void xtensa_mark_literal_pool_location (void);
434 static addressT
get_expanded_loop_offset (xtensa_opcode
);
435 static fragS
*get_literal_pool_location (segT
);
436 static void set_literal_pool_location (segT
, fragS
*);
437 static void xtensa_set_frag_assembly_state (fragS
*);
438 static void finish_vinsn (vliw_insn
*);
439 static bfd_boolean
emit_single_op (TInsn
*);
440 static int total_frag_text_expansion (fragS
*);
442 /* Alignment Functions. */
444 static int get_text_align_power (unsigned);
445 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
446 static int branch_align_power (segT
);
448 /* Helpers for xtensa_relax_frag(). */
450 static long relax_frag_add_nop (fragS
*);
452 /* Accessors for additional per-subsegment information. */
454 static unsigned get_last_insn_flags (segT
, subsegT
);
455 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
456 static float get_subseg_total_freq (segT
, subsegT
);
457 static float get_subseg_target_freq (segT
, subsegT
);
458 static void set_subseg_freq (segT
, subsegT
, float, float);
460 /* Segment list functions. */
462 static void xtensa_move_literals (void);
463 static void xtensa_reorder_segments (void);
464 static void xtensa_switch_to_literal_fragment (emit_state
*);
465 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
466 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
467 static void xtensa_restore_emit_state (emit_state
*);
468 static void cache_literal_section
469 (seg_list
*, const char *, segT
*, bfd_boolean
);
471 /* Import from elf32-xtensa.c in BFD library. */
473 extern char *xtensa_get_property_section_name (asection
*, const char *);
475 /* op_placement_info functions. */
477 static void init_op_placement_info_table (void);
478 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
479 static int xg_get_single_size (xtensa_opcode
);
480 static xtensa_format
xg_get_single_format (xtensa_opcode
);
481 static int xg_get_single_slot (xtensa_opcode
);
483 /* TInsn and IStack functions. */
485 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
486 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
487 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
488 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
489 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
490 static void tinsn_from_chars (TInsn
*, char *, int);
491 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
492 static int get_num_stack_text_bytes (IStack
*);
493 static int get_num_stack_literal_bytes (IStack
*);
495 /* vliw_insn functions. */
497 static void xg_init_vinsn (vliw_insn
*);
498 static void xg_clear_vinsn (vliw_insn
*);
499 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
500 static void xg_free_vinsn (vliw_insn
*);
501 static bfd_boolean vinsn_to_insnbuf
502 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
503 static void vinsn_from_chars (vliw_insn
*, char *);
505 /* Expression Utilities. */
507 bfd_boolean
expr_is_const (const expressionS
*);
508 offsetT
get_expr_const (const expressionS
*);
509 void set_expr_const (expressionS
*, offsetT
);
510 bfd_boolean
expr_is_register (const expressionS
*);
511 offsetT
get_expr_register (const expressionS
*);
512 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
513 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
514 static void copy_expr (expressionS
*, const expressionS
*);
516 /* Section renaming. */
518 static void build_section_rename (const char *);
521 /* ISA imported from bfd. */
522 extern xtensa_isa xtensa_default_isa
;
524 extern int target_big_endian
;
526 static xtensa_opcode xtensa_addi_opcode
;
527 static xtensa_opcode xtensa_addmi_opcode
;
528 static xtensa_opcode xtensa_call0_opcode
;
529 static xtensa_opcode xtensa_call4_opcode
;
530 static xtensa_opcode xtensa_call8_opcode
;
531 static xtensa_opcode xtensa_call12_opcode
;
532 static xtensa_opcode xtensa_callx0_opcode
;
533 static xtensa_opcode xtensa_callx4_opcode
;
534 static xtensa_opcode xtensa_callx8_opcode
;
535 static xtensa_opcode xtensa_callx12_opcode
;
536 static xtensa_opcode xtensa_const16_opcode
;
537 static xtensa_opcode xtensa_entry_opcode
;
538 static xtensa_opcode xtensa_movi_opcode
;
539 static xtensa_opcode xtensa_movi_n_opcode
;
540 static xtensa_opcode xtensa_isync_opcode
;
541 static xtensa_opcode xtensa_jx_opcode
;
542 static xtensa_opcode xtensa_l32r_opcode
;
543 static xtensa_opcode xtensa_loop_opcode
;
544 static xtensa_opcode xtensa_loopnez_opcode
;
545 static xtensa_opcode xtensa_loopgtz_opcode
;
546 static xtensa_opcode xtensa_nop_opcode
;
547 static xtensa_opcode xtensa_nop_n_opcode
;
548 static xtensa_opcode xtensa_or_opcode
;
549 static xtensa_opcode xtensa_ret_opcode
;
550 static xtensa_opcode xtensa_ret_n_opcode
;
551 static xtensa_opcode xtensa_retw_opcode
;
552 static xtensa_opcode xtensa_retw_n_opcode
;
553 static xtensa_opcode xtensa_rsr_lcount_opcode
;
554 static xtensa_opcode xtensa_waiti_opcode
;
557 /* Command-line Options. */
559 bfd_boolean use_literal_section
= TRUE
;
560 static bfd_boolean align_targets
= TRUE
;
561 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
562 static bfd_boolean has_a0_b_retw
= FALSE
;
563 static bfd_boolean workaround_a0_b_retw
= FALSE
;
564 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
565 static bfd_boolean workaround_short_loop
= FALSE
;
566 static bfd_boolean maybe_has_short_loop
= FALSE
;
567 static bfd_boolean workaround_close_loop_end
= FALSE
;
568 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
570 /* When workaround_short_loops is TRUE, all loops with early exits must
571 have at least 3 instructions. workaround_all_short_loops is a modifier
572 to the workaround_short_loop flag. In addition to the
573 workaround_short_loop actions, all straightline loopgtz and loopnez
574 must have at least 3 instructions. */
576 static bfd_boolean workaround_all_short_loops
= FALSE
;
580 xtensa_setup_hw_workarounds (int earliest
, int latest
)
582 if (earliest
> latest
)
583 as_fatal (_("illegal range of target hardware versions"));
585 /* Enable all workarounds for pre-T1050.0 hardware. */
586 if (earliest
< 105000 || latest
< 105000)
588 workaround_a0_b_retw
|= TRUE
;
589 workaround_b_j_loop_end
|= TRUE
;
590 workaround_short_loop
|= TRUE
;
591 workaround_close_loop_end
|= TRUE
;
592 workaround_all_short_loops
|= TRUE
;
599 option_density
= OPTION_MD_BASE
,
606 option_no_link_relax
,
614 option_text_section_literals
,
615 option_no_text_section_literals
,
617 option_absolute_literals
,
618 option_no_absolute_literals
,
620 option_align_targets
,
621 option_no_align_targets
,
623 option_warn_unaligned_targets
,
628 option_workaround_a0_b_retw
,
629 option_no_workaround_a0_b_retw
,
631 option_workaround_b_j_loop_end
,
632 option_no_workaround_b_j_loop_end
,
634 option_workaround_short_loop
,
635 option_no_workaround_short_loop
,
637 option_workaround_all_short_loops
,
638 option_no_workaround_all_short_loops
,
640 option_workaround_close_loop_end
,
641 option_no_workaround_close_loop_end
,
643 option_no_workarounds
,
645 option_rename_section_name
,
648 option_prefer_const16
,
650 option_target_hardware
653 const char *md_shortopts
= "";
655 struct option md_longopts
[] =
657 { "density", no_argument
, NULL
, option_density
},
658 { "no-density", no_argument
, NULL
, option_no_density
},
660 /* Both "relax" and "generics" are deprecated and treated as equivalent
661 to the "transform" option. */
662 { "relax", no_argument
, NULL
, option_relax
},
663 { "no-relax", no_argument
, NULL
, option_no_relax
},
664 { "generics", no_argument
, NULL
, option_generics
},
665 { "no-generics", no_argument
, NULL
, option_no_generics
},
667 { "transform", no_argument
, NULL
, option_transform
},
668 { "no-transform", no_argument
, NULL
, option_no_transform
},
669 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
670 { "no-text-section-literals", no_argument
, NULL
,
671 option_no_text_section_literals
},
672 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
673 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
674 /* This option was changed from -align-target to -target-align
675 because it conflicted with the "-al" option. */
676 { "target-align", no_argument
, NULL
, option_align_targets
},
677 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
678 { "warn-unaligned-targets", no_argument
, NULL
,
679 option_warn_unaligned_targets
},
680 { "longcalls", no_argument
, NULL
, option_longcalls
},
681 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
683 { "no-workaround-a0-b-retw", no_argument
, NULL
,
684 option_no_workaround_a0_b_retw
},
685 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
687 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
688 option_no_workaround_b_j_loop_end
},
689 { "workaround-b-j-loop-end", no_argument
, NULL
,
690 option_workaround_b_j_loop_end
},
692 { "no-workaround-short-loops", no_argument
, NULL
,
693 option_no_workaround_short_loop
},
694 { "workaround-short-loops", no_argument
, NULL
,
695 option_workaround_short_loop
},
697 { "no-workaround-all-short-loops", no_argument
, NULL
,
698 option_no_workaround_all_short_loops
},
699 { "workaround-all-short-loop", no_argument
, NULL
,
700 option_workaround_all_short_loops
},
702 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
703 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
705 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
707 { "no-workaround-close-loop-end", no_argument
, NULL
,
708 option_no_workaround_close_loop_end
},
709 { "workaround-close-loop-end", no_argument
, NULL
,
710 option_workaround_close_loop_end
},
712 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
714 { "link-relax", no_argument
, NULL
, option_link_relax
},
715 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
717 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
719 { NULL
, no_argument
, NULL
, 0 }
722 size_t md_longopts_size
= sizeof md_longopts
;
726 md_parse_option (int c
, char *arg
)
731 as_warn (_("--density option is ignored"));
733 case option_no_density
:
734 as_warn (_("--no-density option is ignored"));
736 case option_link_relax
:
739 case option_no_link_relax
:
742 case option_generics
:
743 as_warn (_("--generics is deprecated; use --transform instead"));
744 return md_parse_option (option_transform
, arg
);
745 case option_no_generics
:
746 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
747 return md_parse_option (option_no_transform
, arg
);
749 as_warn (_("--relax is deprecated; use --transform instead"));
750 return md_parse_option (option_transform
, arg
);
751 case option_no_relax
:
752 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
753 return md_parse_option (option_no_transform
, arg
);
754 case option_longcalls
:
755 directive_state
[directive_longcalls
] = TRUE
;
757 case option_no_longcalls
:
758 directive_state
[directive_longcalls
] = FALSE
;
760 case option_text_section_literals
:
761 use_literal_section
= FALSE
;
763 case option_no_text_section_literals
:
764 use_literal_section
= TRUE
;
766 case option_absolute_literals
:
767 if (!absolute_literals_supported
)
769 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
772 directive_state
[directive_absolute_literals
] = TRUE
;
774 case option_no_absolute_literals
:
775 directive_state
[directive_absolute_literals
] = FALSE
;
778 case option_workaround_a0_b_retw
:
779 workaround_a0_b_retw
= TRUE
;
781 case option_no_workaround_a0_b_retw
:
782 workaround_a0_b_retw
= FALSE
;
784 case option_workaround_b_j_loop_end
:
785 workaround_b_j_loop_end
= TRUE
;
787 case option_no_workaround_b_j_loop_end
:
788 workaround_b_j_loop_end
= FALSE
;
791 case option_workaround_short_loop
:
792 workaround_short_loop
= TRUE
;
794 case option_no_workaround_short_loop
:
795 workaround_short_loop
= FALSE
;
798 case option_workaround_all_short_loops
:
799 workaround_all_short_loops
= TRUE
;
801 case option_no_workaround_all_short_loops
:
802 workaround_all_short_loops
= FALSE
;
805 case option_workaround_close_loop_end
:
806 workaround_close_loop_end
= TRUE
;
808 case option_no_workaround_close_loop_end
:
809 workaround_close_loop_end
= FALSE
;
812 case option_no_workarounds
:
813 workaround_a0_b_retw
= FALSE
;
814 workaround_b_j_loop_end
= FALSE
;
815 workaround_short_loop
= FALSE
;
816 workaround_all_short_loops
= FALSE
;
817 workaround_close_loop_end
= FALSE
;
820 case option_align_targets
:
821 align_targets
= TRUE
;
823 case option_no_align_targets
:
824 align_targets
= FALSE
;
827 case option_warn_unaligned_targets
:
828 warn_unaligned_branch_targets
= TRUE
;
831 case option_rename_section_name
:
832 build_section_rename (arg
);
836 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
837 should be emitted or not. FIXME: Not implemented. */
840 case option_prefer_l32r
:
842 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
846 case option_prefer_const16
:
848 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
852 case option_target_hardware
:
854 int earliest
, latest
= 0;
855 if (*arg
== 0 || *arg
== '-')
856 as_fatal (_("invalid target hardware version"));
858 earliest
= strtol (arg
, &arg
, 0);
862 else if (*arg
== '-')
865 as_fatal (_("invalid target hardware version"));
866 latest
= strtol (arg
, &arg
, 0);
869 as_fatal (_("invalid target hardware version"));
871 xtensa_setup_hw_workarounds (earliest
, latest
);
875 case option_transform
:
876 /* This option has no affect other than to use the defaults,
877 which are already set. */
880 case option_no_transform
:
881 /* This option turns off all transformations of any kind.
882 However, because we want to preserve the state of other
883 directives, we only change its own field. Thus, before
884 you perform any transformation, always check if transform
885 is available. If you use the functions we provide for this
886 purpose, you will be ok. */
887 directive_state
[directive_transform
] = FALSE
;
897 md_show_usage (FILE *stream
)
901 --[no-]text-section-literals\n\
902 [Do not] put literals in the text section\n\
903 --[no-]absolute-literals\n\
904 [Do not] default to use non-PC-relative literals\n\
905 --[no-]target-align [Do not] try to align branch targets\n\
906 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
907 --[no-]transform [Do not] transform instructions\n\
908 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
912 /* Functions related to the list of current label symbols. */
915 xtensa_add_insn_label (symbolS
*sym
)
919 if (!free_insn_labels
)
920 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
923 l
= free_insn_labels
;
924 free_insn_labels
= l
->next
;
928 l
->next
= insn_labels
;
934 xtensa_clear_insn_labels (void)
938 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
945 /* The "loops_ok" argument is provided to allow ignoring labels that
946 define loop ends. This fixes a bug where the NOPs to align a
947 loop opcode were included in a previous zero-cost loop:
966 This argument is used to prevent moving the NOP to before the
967 loop-end label, which is what you want in this special case. */
970 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
974 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
976 symbolS
*lit_sym
= lit
->sym
;
977 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
979 S_SET_VALUE (lit_sym
, new_offset
);
980 symbol_set_frag (lit_sym
, new_frag
);
986 /* Directive data and functions. */
988 typedef struct state_stackS_struct
990 directiveE directive
;
992 bfd_boolean old_state
;
996 struct state_stackS_struct
*prev
;
999 state_stackS
*directive_state_stack
;
1001 const pseudo_typeS md_pseudo_table
[] =
1003 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1004 { "literal_position", xtensa_literal_position
, 0 },
1005 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1006 { "long", xtensa_elf_cons
, 4 },
1007 { "word", xtensa_elf_cons
, 4 },
1008 { "short", xtensa_elf_cons
, 2 },
1009 { "begin", xtensa_begin_directive
, 0 },
1010 { "end", xtensa_end_directive
, 0 },
1011 { "literal", xtensa_literal_pseudo
, 0 },
1012 { "frequency", xtensa_frequency_pseudo
, 0 },
1018 use_transform (void)
1020 /* After md_end, you should be checking frag by frag, rather
1021 than state directives. */
1022 assert (!past_xtensa_end
);
1023 return directive_state
[directive_transform
];
1028 do_align_targets (void)
1030 /* Do not use this function after md_end; just look at align_targets
1031 instead. There is no target-align directive, so alignment is either
1032 enabled for all frags or not done at all. */
1033 assert (!past_xtensa_end
);
1034 return align_targets
&& use_transform ();
1039 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1043 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1045 as_where (&file
, &line
);
1047 stack
->directive
= directive
;
1048 stack
->negated
= negated
;
1049 stack
->old_state
= directive_state
[directive
];
1052 stack
->datum
= datum
;
1053 stack
->prev
= directive_state_stack
;
1054 directive_state_stack
= stack
;
1056 directive_state
[directive
] = !negated
;
1061 directive_pop (directiveE
*directive
,
1062 bfd_boolean
*negated
,
1067 state_stackS
*top
= directive_state_stack
;
1069 if (!directive_state_stack
)
1071 as_bad (_("unmatched end directive"));
1072 *directive
= directive_none
;
1076 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1077 *directive
= top
->directive
;
1078 *negated
= top
->negated
;
1081 *datum
= top
->datum
;
1082 directive_state_stack
= top
->prev
;
1088 directive_balance (void)
1090 while (directive_state_stack
)
1092 directiveE directive
;
1093 bfd_boolean negated
;
1098 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1099 as_warn_where ((char *) file
, line
,
1100 _(".begin directive with no matching .end directive"));
1106 inside_directive (directiveE dir
)
1108 state_stackS
*top
= directive_state_stack
;
1110 while (top
&& top
->directive
!= dir
)
1113 return (top
!= NULL
);
1118 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1122 char *directive_string
;
1124 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1129 input_line_pointer
+= 3;
1132 len
= strspn (input_line_pointer
,
1133 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1135 /* This code is a hack to make .begin [no-][generics|relax] exactly
1136 equivalent to .begin [no-]transform. We should remove it when
1137 we stop accepting those options. */
1139 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1141 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1142 directive_string
= "transform";
1144 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1146 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1147 directive_string
= "transform";
1150 directive_string
= input_line_pointer
;
1152 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1154 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1156 input_line_pointer
+= len
;
1157 *directive
= (directiveE
) i
;
1158 if (*negated
&& !directive_info
[i
].can_be_negated
)
1159 as_bad (_("directive %s cannot be negated"),
1160 directive_info
[i
].name
);
1165 as_bad (_("unknown directive"));
1166 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1171 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1173 directiveE directive
;
1174 bfd_boolean negated
;
1179 get_directive (&directive
, &negated
);
1180 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1182 discard_rest_of_line ();
1186 if (cur_vinsn
.inside_bundle
)
1187 as_bad (_("directives are not valid inside bundles"));
1191 case directive_literal
:
1192 if (!inside_directive (directive_literal
))
1194 /* Previous labels go with whatever follows this directive, not with
1195 the literal, so save them now. */
1196 saved_insn_labels
= insn_labels
;
1199 as_warn (_(".begin literal is deprecated; use .literal instead"));
1200 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1201 xtensa_switch_to_literal_fragment (state
);
1202 directive_push (directive_literal
, negated
, state
);
1205 case directive_literal_prefix
:
1206 /* Have to flush pending output because a movi relaxed to an l32r
1207 might produce a literal. */
1208 md_flush_pending_output ();
1209 /* Check to see if the current fragment is a literal
1210 fragment. If it is, then this operation is not allowed. */
1211 if (generating_literals
)
1213 as_bad (_("cannot set literal_prefix inside literal fragment"));
1217 /* Allocate the literal state for this section and push
1218 onto the directive stack. */
1219 ls
= xmalloc (sizeof (lit_state
));
1222 *ls
= default_lit_sections
;
1224 directive_push (directive_literal_prefix
, negated
, ls
);
1226 /* Parse the new prefix from the input_line_pointer. */
1228 len
= strspn (input_line_pointer
,
1229 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1230 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1232 /* Process the new prefix. */
1233 xtensa_literal_prefix (input_line_pointer
, len
);
1235 /* Skip the name in the input line. */
1236 input_line_pointer
+= len
;
1239 case directive_freeregs
:
1240 /* This information is currently unused, but we'll accept the statement
1241 and just discard the rest of the line. This won't check the syntax,
1242 but it will accept every correct freeregs directive. */
1243 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1244 directive_push (directive_freeregs
, negated
, 0);
1247 case directive_schedule
:
1248 md_flush_pending_output ();
1249 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1250 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1251 directive_push (directive_schedule
, negated
, 0);
1252 xtensa_set_frag_assembly_state (frag_now
);
1255 case directive_density
:
1256 as_warn (_(".begin [no-]density is ignored"));
1259 case directive_absolute_literals
:
1260 md_flush_pending_output ();
1261 if (!absolute_literals_supported
&& !negated
)
1263 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1266 xtensa_set_frag_assembly_state (frag_now
);
1267 directive_push (directive
, negated
, 0);
1271 md_flush_pending_output ();
1272 xtensa_set_frag_assembly_state (frag_now
);
1273 directive_push (directive
, negated
, 0);
1277 demand_empty_rest_of_line ();
1282 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1284 directiveE begin_directive
, end_directive
;
1285 bfd_boolean begin_negated
, end_negated
;
1289 emit_state
**state_ptr
;
1292 if (cur_vinsn
.inside_bundle
)
1293 as_bad (_("directives are not valid inside bundles"));
1295 get_directive (&end_directive
, &end_negated
);
1297 md_flush_pending_output ();
1299 switch (end_directive
)
1301 case (directiveE
) XTENSA_UNDEFINED
:
1302 discard_rest_of_line ();
1305 case directive_density
:
1306 as_warn (_(".end [no-]density is ignored"));
1307 demand_empty_rest_of_line ();
1310 case directive_absolute_literals
:
1311 if (!absolute_literals_supported
&& !end_negated
)
1313 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1314 demand_empty_rest_of_line ();
1323 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1324 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1325 (const void **) state_ptr
);
1327 if (begin_directive
!= directive_none
)
1329 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1331 as_bad (_("does not match begin %s%s at %s:%d"),
1332 begin_negated
? "no-" : "",
1333 directive_info
[begin_directive
].name
, file
, line
);
1337 switch (end_directive
)
1339 case directive_literal
:
1340 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1341 xtensa_restore_emit_state (state
);
1342 xtensa_set_frag_assembly_state (frag_now
);
1344 if (!inside_directive (directive_literal
))
1346 /* Restore the list of current labels. */
1347 xtensa_clear_insn_labels ();
1348 insn_labels
= saved_insn_labels
;
1352 case directive_literal_prefix
:
1353 /* Restore the default collection sections from saved state. */
1354 s
= (lit_state
*) state
;
1357 default_lit_sections
= *s
;
1359 /* free the state storage */
1363 case directive_schedule
:
1364 case directive_freeregs
:
1368 xtensa_set_frag_assembly_state (frag_now
);
1374 demand_empty_rest_of_line ();
1378 /* Place an aligned literal fragment at the current location. */
1381 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1383 md_flush_pending_output ();
1385 if (inside_directive (directive_literal
))
1386 as_warn (_(".literal_position inside literal directive; ignoring"));
1387 xtensa_mark_literal_pool_location ();
1389 demand_empty_rest_of_line ();
1390 xtensa_clear_insn_labels ();
1394 /* Support .literal label, expr, ... */
1397 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1400 char *p
, *base_name
;
1404 if (inside_directive (directive_literal
))
1406 as_bad (_(".literal not allowed inside .begin literal region"));
1407 ignore_rest_of_line ();
1411 md_flush_pending_output ();
1413 /* Previous labels go with whatever follows this directive, not with
1414 the literal, so save them now. */
1415 saved_insn_labels
= insn_labels
;
1418 /* If we are using text-section literals, then this is the right value... */
1421 base_name
= input_line_pointer
;
1423 xtensa_switch_to_literal_fragment (&state
);
1425 /* ...but if we aren't using text-section-literals, then we
1426 need to put them in the section we just switched to. */
1427 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1430 /* All literals are aligned to four-byte boundaries. */
1431 frag_align (2, 0, 0);
1432 record_alignment (now_seg
, 2);
1434 c
= get_symbol_end ();
1435 /* Just after name is now '\0'. */
1436 p
= input_line_pointer
;
1440 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1442 as_bad (_("expected comma or colon after symbol name; "
1443 "rest of line ignored"));
1444 ignore_rest_of_line ();
1445 xtensa_restore_emit_state (&state
);
1453 input_line_pointer
++; /* skip ',' or ':' */
1455 xtensa_elf_cons (4);
1457 xtensa_restore_emit_state (&state
);
1459 /* Restore the list of current labels. */
1460 xtensa_clear_insn_labels ();
1461 insn_labels
= saved_insn_labels
;
1466 xtensa_literal_prefix (char const *start
, int len
)
1468 char *name
, *linkonce_suffix
;
1469 char *newname
, *newname4
;
1470 size_t linkonce_len
;
1472 /* Get a null-terminated copy of the name. */
1473 name
= xmalloc (len
+ 1);
1476 strncpy (name
, start
, len
);
1479 /* Allocate the sections (interesting note: the memory pointing to
1480 the name is actually used for the name by the new section). */
1482 newname
= xmalloc (len
+ strlen (".literal") + 1);
1483 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1485 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1486 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1487 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1489 strcpy (newname
, ".gnu.linkonce.literal");
1490 strcpy (newname4
, ".gnu.linkonce.lit4");
1492 strcat (newname
, linkonce_suffix
);
1493 strcat (newname4
, linkonce_suffix
);
1497 int suffix_pos
= len
;
1499 /* If the section name ends with ".text", then replace that suffix
1500 instead of appending an additional suffix. */
1501 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1504 strcpy (newname
, name
);
1505 strcpy (newname4
, name
);
1507 strcpy (newname
+ suffix_pos
, ".literal");
1508 strcpy (newname4
+ suffix_pos
, ".lit4");
1511 /* Note that cache_literal_section does not create a segment if
1512 it already exists. */
1513 default_lit_sections
.lit_seg
= NULL
;
1514 default_lit_sections
.lit4_seg
= NULL
;
1516 /* Canonicalizing section names allows renaming literal
1517 sections to occur correctly. */
1518 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1519 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1525 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1528 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1530 float fall_through_f
, target_f
;
1532 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1533 if (fall_through_f
< 0)
1535 as_bad (_("fall through frequency must be greater than 0"));
1536 ignore_rest_of_line ();
1540 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1543 as_bad (_("branch target frequency must be greater than 0"));
1544 ignore_rest_of_line ();
1548 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1550 demand_empty_rest_of_line ();
1554 /* Like normal .long/.short/.word, except support @plt, etc.
1555 Clobbers input_line_pointer, checks end-of-line. */
1558 xtensa_elf_cons (int nbytes
)
1561 bfd_reloc_code_real_type reloc
;
1563 md_flush_pending_output ();
1565 if (cur_vinsn
.inside_bundle
)
1566 as_bad (_("directives are not valid inside bundles"));
1568 if (is_it_end_of_statement ())
1570 demand_empty_rest_of_line ();
1577 if (exp
.X_op
== O_symbol
1578 && *input_line_pointer
== '@'
1579 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1582 reloc_howto_type
*reloc_howto
=
1583 bfd_reloc_type_lookup (stdoutput
, reloc
);
1585 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1586 as_bad (_("unsupported relocation"));
1587 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1588 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1589 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1590 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1591 as_bad (_("opcode-specific %s relocation used outside "
1592 "an instruction"), reloc_howto
->name
);
1593 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1594 as_bad (_("%s relocations do not fit in %d bytes"),
1595 reloc_howto
->name
, nbytes
);
1598 char *p
= frag_more ((int) nbytes
);
1599 xtensa_set_frag_assembly_state (frag_now
);
1600 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1601 nbytes
, &exp
, 0, reloc
);
1605 emit_expr (&exp
, (unsigned int) nbytes
);
1607 while (*input_line_pointer
++ == ',');
1609 input_line_pointer
--; /* Put terminator back into stream. */
1610 demand_empty_rest_of_line ();
1614 /* Parsing and Idiom Translation. */
1616 /* Parse @plt, etc. and return the desired relocation. */
1617 static bfd_reloc_code_real_type
1618 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1624 bfd_reloc_code_real_type reloc
;
1632 struct map_bfd
*ptr
;
1634 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1636 static struct map_bfd mapping
[] =
1638 MAP ("l", BFD_RELOC_LO16
),
1639 MAP ("h", BFD_RELOC_HI16
),
1640 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1641 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1645 return BFD_RELOC_NONE
;
1647 for (ch
= *str
, str2
= ident
;
1648 (str2
< ident
+ sizeof (ident
) - 1
1649 && (ISALNUM (ch
) || ch
== '@'));
1652 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1659 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1660 if (ch
== ptr
->string
[0]
1661 && len
== ptr
->length
1662 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1664 /* Now check for "identifier@suffix+constant". */
1665 if (*str
== '-' || *str
== '+')
1667 char *orig_line
= input_line_pointer
;
1668 expressionS new_exp
;
1670 input_line_pointer
= str
;
1671 expression (&new_exp
);
1672 if (new_exp
.X_op
== O_constant
)
1674 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1675 str
= input_line_pointer
;
1678 if (&input_line_pointer
!= str_p
)
1679 input_line_pointer
= orig_line
;
1686 return BFD_RELOC_UNUSED
;
1691 expression_end (const char *name
)
1714 #define ERROR_REG_NUM ((unsigned) -1)
1717 tc_get_register (const char *prefix
)
1720 const char *next_expr
;
1721 const char *old_line_pointer
;
1724 old_line_pointer
= input_line_pointer
;
1726 if (*input_line_pointer
== '$')
1727 ++input_line_pointer
;
1729 /* Accept "sp" as a synonym for "a1". */
1730 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1731 && expression_end (input_line_pointer
+ 2))
1733 input_line_pointer
+= 2;
1734 return 1; /* AR[1] */
1737 while (*input_line_pointer
++ == *prefix
++)
1739 --input_line_pointer
;
1744 as_bad (_("bad register name: %s"), old_line_pointer
);
1745 return ERROR_REG_NUM
;
1748 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1750 as_bad (_("bad register number: %s"), input_line_pointer
);
1751 return ERROR_REG_NUM
;
1756 while (ISDIGIT ((int) *input_line_pointer
))
1757 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1759 if (!(next_expr
= expression_end (input_line_pointer
)))
1761 as_bad (_("bad register name: %s"), old_line_pointer
);
1762 return ERROR_REG_NUM
;
1765 input_line_pointer
= (char *) next_expr
;
1772 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1774 xtensa_isa isa
= xtensa_default_isa
;
1776 /* Check if this is an immediate operand. */
1777 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1779 bfd_reloc_code_real_type reloc
;
1780 segT t
= expression (tok
);
1781 if (t
== absolute_section
1782 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1784 assert (tok
->X_op
== O_constant
);
1785 tok
->X_op
= O_symbol
;
1786 tok
->X_add_symbol
= &abs_symbol
;
1789 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1790 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1791 && (reloc
!= BFD_RELOC_NONE
))
1796 case BFD_RELOC_UNUSED
:
1797 as_bad (_("unsupported relocation"));
1800 case BFD_RELOC_XTENSA_PLT
:
1801 tok
->X_op
= O_pltrel
;
1804 case BFD_RELOC_LO16
:
1805 if (tok
->X_op
== O_constant
)
1806 tok
->X_add_number
&= 0xffff;
1811 case BFD_RELOC_HI16
:
1812 if (tok
->X_op
== O_constant
)
1813 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1822 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1823 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1825 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1828 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1829 as_bad (_("register number out of range"));
1832 tok
->X_op
= O_register
;
1833 tok
->X_add_symbol
= 0;
1834 tok
->X_add_number
= reg
;
1839 /* Split up the arguments for an opcode or pseudo-op. */
1842 tokenize_arguments (char **args
, char *str
)
1844 char *old_input_line_pointer
;
1845 bfd_boolean saw_comma
= FALSE
;
1846 bfd_boolean saw_arg
= FALSE
;
1847 bfd_boolean saw_colon
= FALSE
;
1849 char *arg_end
, *arg
;
1852 /* Save and restore input_line_pointer around this function. */
1853 old_input_line_pointer
= input_line_pointer
;
1854 input_line_pointer
= str
;
1856 while (*input_line_pointer
)
1859 switch (*input_line_pointer
)
1866 input_line_pointer
++;
1867 if (saw_comma
|| saw_colon
|| !saw_arg
)
1873 input_line_pointer
++;
1874 if (saw_comma
|| saw_colon
|| !saw_arg
)
1880 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1883 arg_end
= input_line_pointer
+ 1;
1884 while (!expression_end (arg_end
))
1887 arg_len
= arg_end
- input_line_pointer
;
1888 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1889 args
[num_args
] = arg
;
1893 strncpy (arg
, input_line_pointer
, arg_len
);
1894 arg
[arg_len
] = '\0';
1896 input_line_pointer
= arg_end
;
1906 if (saw_comma
|| saw_colon
)
1908 input_line_pointer
= old_input_line_pointer
;
1913 as_bad (_("extra comma"));
1915 as_bad (_("extra colon"));
1917 as_bad (_("missing argument"));
1919 as_bad (_("missing comma or colon"));
1920 input_line_pointer
= old_input_line_pointer
;
1925 /* Parse the arguments to an opcode. Return TRUE on error. */
1928 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1930 expressionS
*tok
, *last_tok
;
1931 xtensa_opcode opcode
= insn
->opcode
;
1932 bfd_boolean had_error
= TRUE
;
1933 xtensa_isa isa
= xtensa_default_isa
;
1934 int n
, num_regs
= 0;
1935 int opcode_operand_count
;
1936 int opnd_cnt
, last_opnd_cnt
;
1937 unsigned int next_reg
= 0;
1938 char *old_input_line_pointer
;
1940 if (insn
->insn_type
== ITYPE_LITERAL
)
1941 opcode_operand_count
= 1;
1943 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1946 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1948 /* Save and restore input_line_pointer around this function. */
1949 old_input_line_pointer
= input_line_pointer
;
1955 /* Skip invisible operands. */
1956 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1962 for (n
= 0; n
< num_args
; n
++)
1964 input_line_pointer
= arg_strings
[n
];
1965 if (*input_line_pointer
== ':')
1967 xtensa_regfile opnd_rf
;
1968 input_line_pointer
++;
1971 assert (opnd_cnt
> 0);
1973 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1975 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1976 as_warn (_("incorrect register number, ignoring"));
1981 if (opnd_cnt
>= opcode_operand_count
)
1983 as_warn (_("too many arguments"));
1986 assert (opnd_cnt
< MAX_INSN_ARGS
);
1988 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1989 next_reg
= tok
->X_add_number
+ 1;
1991 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1993 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1995 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1996 /* minus 1 because we are seeing one right now */
2002 last_opnd_cnt
= opnd_cnt
;
2009 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2013 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2016 insn
->ntok
= tok
- insn
->tok
;
2020 input_line_pointer
= old_input_line_pointer
;
2026 get_invisible_operands (TInsn
*insn
)
2028 xtensa_isa isa
= xtensa_default_isa
;
2029 static xtensa_insnbuf slotbuf
= NULL
;
2031 xtensa_opcode opc
= insn
->opcode
;
2032 int slot
, opnd
, fmt_found
;
2036 slotbuf
= xtensa_insnbuf_alloc (isa
);
2038 /* Find format/slot where this can be encoded. */
2041 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2043 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2045 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2051 if (fmt_found
) break;
2056 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2060 /* First encode all the visible operands
2061 (to deal with shared field operands). */
2062 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2064 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2065 && (insn
->tok
[opnd
].X_op
== O_register
2066 || insn
->tok
[opnd
].X_op
== O_constant
))
2068 val
= insn
->tok
[opnd
].X_add_number
;
2069 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2070 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2074 /* Then pull out the values for the invisible ones. */
2075 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2077 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2079 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2080 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2081 insn
->tok
[opnd
].X_add_number
= val
;
2082 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2083 insn
->tok
[opnd
].X_op
= O_register
;
2085 insn
->tok
[opnd
].X_op
= O_constant
;
2094 xg_reverse_shift_count (char **cnt_argp
)
2096 char *cnt_arg
, *new_arg
;
2097 cnt_arg
= *cnt_argp
;
2099 /* replace the argument with "31-(argument)" */
2100 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2101 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2104 *cnt_argp
= new_arg
;
2108 /* If "arg" is a constant expression, return non-zero with the value
2112 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2115 char *save_ptr
= input_line_pointer
;
2117 input_line_pointer
= arg
;
2119 input_line_pointer
= save_ptr
;
2121 if (exp
.X_op
== O_constant
)
2123 *valp
= exp
.X_add_number
;
2132 xg_replace_opname (char **popname
, char *newop
)
2135 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2136 strcpy (*popname
, newop
);
2141 xg_check_num_args (int *pnum_args
,
2146 int num_args
= *pnum_args
;
2148 if (num_args
< expected_num
)
2150 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2151 num_args
, opname
, expected_num
);
2155 if (num_args
> expected_num
)
2157 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2158 num_args
, opname
, expected_num
);
2159 while (num_args
-- > expected_num
)
2161 free (arg_strings
[num_args
]);
2162 arg_strings
[num_args
] = 0;
2164 *pnum_args
= expected_num
;
2172 /* If the register is not specified as part of the opcode,
2173 then get it from the operand and move it to the opcode. */
2176 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2178 xtensa_isa isa
= xtensa_default_isa
;
2180 char *opname
, *new_opname
;
2181 const char *sr_name
;
2182 int is_user
, is_write
;
2183 bfd_boolean has_underbar
= FALSE
;
2188 has_underbar
= TRUE
;
2191 is_user
= (opname
[1] == 'u');
2192 is_write
= (opname
[0] == 'w');
2194 /* Opname == [rw]ur or [rwx]sr... */
2196 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2199 /* Check if the argument is a symbolic register name. */
2200 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2201 /* Handle WSR to "INTSET" as a special case. */
2202 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2203 && !strcasecmp (arg_strings
[1], "intset"))
2204 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2205 if (sr
== XTENSA_UNDEFINED
2206 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2208 /* Maybe it's a register number.... */
2210 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2212 as_bad (_("invalid register '%s' for '%s' instruction"),
2213 arg_strings
[1], opname
);
2216 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2217 if (sr
== XTENSA_UNDEFINED
)
2219 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2220 (long) val
, opname
);
2225 /* Remove the last argument, which is now part of the opcode. */
2226 free (arg_strings
[1]);
2230 /* Translate the opcode. */
2231 sr_name
= xtensa_sysreg_name (isa
, sr
);
2232 /* Another special case for "WSR.INTSET".... */
2233 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2235 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2236 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2239 *popname
= new_opname
;
2246 xtensa_translate_old_userreg_ops (char **popname
)
2248 xtensa_isa isa
= xtensa_default_isa
;
2250 char *opname
, *new_opname
;
2251 const char *sr_name
;
2252 bfd_boolean has_underbar
= FALSE
;
2255 if (opname
[0] == '_')
2257 has_underbar
= TRUE
;
2261 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2262 if (sr
!= XTENSA_UNDEFINED
)
2264 /* The new default name ("nnn") is different from the old default
2265 name ("URnnn"). The old default is handled below, and we don't
2266 want to recognize [RW]nnn, so do nothing if the name is the (new)
2268 static char namebuf
[10];
2269 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2270 if (strcmp (namebuf
, opname
+ 1) == 0)
2278 /* Only continue if the reg name is "URnnn". */
2279 if (opname
[1] != 'u' || opname
[2] != 'r')
2281 val
= strtoul (opname
+ 3, &end
, 10);
2285 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2286 if (sr
== XTENSA_UNDEFINED
)
2288 as_bad (_("invalid register number (%ld) for '%s'"),
2289 (long) val
, opname
);
2294 /* Translate the opcode. */
2295 sr_name
= xtensa_sysreg_name (isa
, sr
);
2296 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2297 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2298 opname
[0], sr_name
);
2300 *popname
= new_opname
;
2307 xtensa_translate_zero_immed (char *old_op
,
2317 assert (opname
[0] != '_');
2319 if (strcmp (opname
, old_op
) != 0)
2322 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2324 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2326 xg_replace_opname (popname
, new_op
);
2327 free (arg_strings
[1]);
2328 arg_strings
[1] = arg_strings
[2];
2337 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2338 Returns non-zero if an error was found. */
2341 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2343 char *opname
= *popname
;
2344 bfd_boolean has_underbar
= FALSE
;
2346 if (cur_vinsn
.inside_bundle
)
2351 has_underbar
= TRUE
;
2355 if (strcmp (opname
, "mov") == 0)
2357 if (use_transform () && !has_underbar
&& density_supported
)
2358 xg_replace_opname (popname
, "mov.n");
2361 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2363 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2364 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2365 strcpy (arg_strings
[2], arg_strings
[1]);
2371 if (strcmp (opname
, "bbsi.l") == 0)
2373 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2375 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2376 if (target_big_endian
)
2377 xg_reverse_shift_count (&arg_strings
[1]);
2381 if (strcmp (opname
, "bbci.l") == 0)
2383 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2385 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2386 if (target_big_endian
)
2387 xg_reverse_shift_count (&arg_strings
[1]);
2391 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2392 && strcmp (opname
, "nop") == 0)
2394 if (use_transform () && !has_underbar
&& density_supported
)
2395 xg_replace_opname (popname
, "nop.n");
2398 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2400 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2401 arg_strings
[0] = (char *) xmalloc (3);
2402 arg_strings
[1] = (char *) xmalloc (3);
2403 arg_strings
[2] = (char *) xmalloc (3);
2404 strcpy (arg_strings
[0], "a1");
2405 strcpy (arg_strings
[1], "a1");
2406 strcpy (arg_strings
[2], "a1");
2412 /* Recognize [RW]UR and [RWX]SR. */
2413 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2414 && (opname
[1] == 'u' || opname
[1] == 's'))
2415 || (opname
[0] == 'x' && opname
[1] == 's'))
2417 && opname
[3] == '\0')
2418 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2420 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2421 [RW]<name> if <name> is the non-default name of a user register. */
2422 if ((opname
[0] == 'r' || opname
[0] == 'w')
2423 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2424 return xtensa_translate_old_userreg_ops (popname
);
2426 /* Relax branches that don't allow comparisons against an immediate value
2427 of zero to the corresponding branches with implicit zero immediates. */
2428 if (!has_underbar
&& use_transform ())
2430 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2431 pnum_args
, arg_strings
))
2434 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2435 pnum_args
, arg_strings
))
2438 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2439 pnum_args
, arg_strings
))
2442 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2443 pnum_args
, arg_strings
))
2451 /* Functions for dealing with the Xtensa ISA. */
2453 /* Currently the assembler only allows us to use a single target per
2454 fragment. Because of this, only one operand for a given
2455 instruction may be symbolic. If there is a PC-relative operand,
2456 the last one is chosen. Otherwise, the result is the number of the
2457 last immediate operand, and if there are none of those, we fail and
2461 get_relaxable_immed (xtensa_opcode opcode
)
2463 int last_immed
= -1;
2466 if (opcode
== XTENSA_UNDEFINED
)
2469 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2470 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2472 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2474 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2476 if (last_immed
== -1
2477 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2484 static xtensa_opcode
2485 get_opcode_from_buf (const char *buf
, int slot
)
2487 static xtensa_insnbuf insnbuf
= NULL
;
2488 static xtensa_insnbuf slotbuf
= NULL
;
2489 xtensa_isa isa
= xtensa_default_isa
;
2494 insnbuf
= xtensa_insnbuf_alloc (isa
);
2495 slotbuf
= xtensa_insnbuf_alloc (isa
);
2498 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2499 fmt
= xtensa_format_decode (isa
, insnbuf
);
2500 if (fmt
== XTENSA_UNDEFINED
)
2501 return XTENSA_UNDEFINED
;
2503 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2504 return XTENSA_UNDEFINED
;
2506 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2507 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2511 #ifdef TENSILICA_DEBUG
2513 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2516 xtensa_print_insn_table (void)
2518 int num_opcodes
, num_operands
;
2519 xtensa_opcode opcode
;
2520 xtensa_isa isa
= xtensa_default_isa
;
2522 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2523 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2526 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2527 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2528 for (opn
= 0; opn
< num_operands
; opn
++)
2530 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2532 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2534 xtensa_regfile opnd_rf
=
2535 xtensa_operand_regfile (isa
, opcode
, opn
);
2536 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2538 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2539 fputs ("[lLr] ", stderr
);
2541 fputs ("i ", stderr
);
2543 fprintf (stderr
, "\n");
2549 print_vliw_insn (xtensa_insnbuf vbuf
)
2551 xtensa_isa isa
= xtensa_default_isa
;
2552 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2553 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2556 fprintf (stderr
, "format = %d\n", f
);
2558 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2560 xtensa_opcode opcode
;
2564 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2565 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2566 opname
= xtensa_opcode_name (isa
, opcode
);
2568 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2569 fprintf (stderr
, " operands = ");
2571 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2575 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2577 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2578 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2579 fprintf (stderr
, "%d ", val
);
2581 fprintf (stderr
, "\n");
2583 xtensa_insnbuf_free (isa
, sbuf
);
2586 #endif /* TENSILICA_DEBUG */
2590 is_direct_call_opcode (xtensa_opcode opcode
)
2592 xtensa_isa isa
= xtensa_default_isa
;
2593 int n
, num_operands
;
2595 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2598 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2599 for (n
= 0; n
< num_operands
; n
++)
2601 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2602 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2609 /* Convert from BFD relocation type code to slot and operand number.
2610 Returns non-zero on failure. */
2613 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2615 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2616 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2618 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2621 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2622 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2624 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2634 /* Convert from slot number to BFD relocation type code for the
2635 standard PC-relative relocations. Return BFD_RELOC_NONE on
2638 static bfd_reloc_code_real_type
2639 encode_reloc (int slot
)
2641 if (slot
< 0 || slot
> 14)
2642 return BFD_RELOC_NONE
;
2644 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2648 /* Convert from slot numbers to BFD relocation type code for the
2649 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2651 static bfd_reloc_code_real_type
2652 encode_alt_reloc (int slot
)
2654 if (slot
< 0 || slot
> 14)
2655 return BFD_RELOC_NONE
;
2657 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2662 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2665 xtensa_opcode opcode
,
2671 uint32 valbuf
= value
;
2673 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2675 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2677 as_bad_where ((char *) file
, line
,
2678 _("operand %d of '%s' has out of range value '%u'"),
2680 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2683 as_bad_where ((char *) file
, line
,
2684 _("operand %d of '%s' has invalid value '%u'"),
2686 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2691 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2697 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2700 xtensa_opcode opcode
,
2704 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2705 fmt
, slot
, slotbuf
, &val
);
2706 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2711 /* Checks for rules from xtensa-relax tables. */
2713 /* The routine xg_instruction_matches_option_term must return TRUE
2714 when a given option term is true. The meaning of all of the option
2715 terms is given interpretation by this function. This is needed when
2716 an option depends on the state of a directive, but there are no such
2717 options in use right now. */
2720 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2721 const ReqOrOption
*option
)
2723 if (strcmp (option
->option_name
, "realnop") == 0
2724 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2726 /* These conditions were evaluated statically when building the
2727 relaxation table. There's no need to reevaluate them now. */
2732 as_fatal (_("internal error: unknown option name '%s'"),
2733 option
->option_name
);
2739 xg_instruction_matches_or_options (TInsn
*insn
,
2740 const ReqOrOptionList
*or_option
)
2742 const ReqOrOption
*option
;
2743 /* Must match each of the AND terms. */
2744 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2746 if (xg_instruction_matches_option_term (insn
, option
))
2754 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2756 const ReqOption
*req_options
;
2757 /* Must match each of the AND terms. */
2758 for (req_options
= options
;
2759 req_options
!= NULL
;
2760 req_options
= req_options
->next
)
2762 /* Must match one of the OR clauses. */
2763 if (!xg_instruction_matches_or_options (insn
,
2764 req_options
->or_option_terms
))
2771 /* Return the transition rule that matches or NULL if none matches. */
2774 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2776 PreconditionList
*condition_l
;
2778 if (rule
->opcode
!= insn
->opcode
)
2781 for (condition_l
= rule
->conditions
;
2782 condition_l
!= NULL
;
2783 condition_l
= condition_l
->next
)
2787 Precondition
*cond
= condition_l
->precond
;
2792 /* The expression must be the constant. */
2793 assert (cond
->op_num
< insn
->ntok
);
2794 exp1
= &insn
->tok
[cond
->op_num
];
2795 if (expr_is_const (exp1
))
2800 if (get_expr_const (exp1
) != cond
->op_data
)
2804 if (get_expr_const (exp1
) == cond
->op_data
)
2811 else if (expr_is_register (exp1
))
2816 if (get_expr_register (exp1
) != cond
->op_data
)
2820 if (get_expr_register (exp1
) == cond
->op_data
)
2832 assert (cond
->op_num
< insn
->ntok
);
2833 assert (cond
->op_data
< insn
->ntok
);
2834 exp1
= &insn
->tok
[cond
->op_num
];
2835 exp2
= &insn
->tok
[cond
->op_data
];
2840 if (!expr_is_equal (exp1
, exp2
))
2844 if (expr_is_equal (exp1
, exp2
))
2856 if (!xg_instruction_matches_options (insn
, rule
->options
))
2864 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2866 bfd_boolean a_greater
= FALSE
;
2867 bfd_boolean b_greater
= FALSE
;
2869 ReqOptionList
*l_a
= a
->options
;
2870 ReqOptionList
*l_b
= b
->options
;
2872 /* We only care if they both are the same except for
2873 a const16 vs. an l32r. */
2875 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2877 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2878 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2879 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2881 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2883 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2885 /* This is the case we care about. */
2886 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2887 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2894 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2895 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2905 l_or_a
= l_or_a
->next
;
2906 l_or_b
= l_or_b
->next
;
2908 if (l_or_a
|| l_or_b
)
2917 /* Incomparable if the substitution was used differently in two cases. */
2918 if (a_greater
&& b_greater
)
2930 static TransitionRule
*
2931 xg_instruction_match (TInsn
*insn
)
2933 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2935 assert (insn
->opcode
< table
->num_opcodes
);
2937 /* Walk through all of the possible transitions. */
2938 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2940 TransitionRule
*rule
= l
->rule
;
2941 if (xg_instruction_matches_rule (insn
, rule
))
2948 /* Various Other Internal Functions. */
2951 is_unique_insn_expansion (TransitionRule
*r
)
2953 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2955 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2961 /* Check if there is exactly one relaxation for INSN that converts it to
2962 another instruction of equal or larger size. If so, and if TARG is
2963 non-null, go ahead and generate the relaxed instruction into TARG. If
2964 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2965 instruction, i.e., ignore relaxations that convert to an instruction of
2966 equal size. In some contexts where this function is used, only
2967 a single widening is allowed and the NARROW_ONLY argument is used to
2968 exclude cases like ADDI being "widened" to an ADDMI, which may
2969 later be relaxed to an ADDMI/ADDI pair. */
2972 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2974 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2976 TransitionRule
*match
= 0;
2978 assert (insn
->insn_type
== ITYPE_INSN
);
2979 assert (insn
->opcode
< table
->num_opcodes
);
2981 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2983 TransitionRule
*rule
= l
->rule
;
2985 if (xg_instruction_matches_rule (insn
, rule
)
2986 && is_unique_insn_expansion (rule
)
2987 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2988 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2999 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3004 /* Return the maximum number of bytes this opcode can expand to. */
3007 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3009 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3011 int max_size
= xg_get_single_size (opcode
);
3013 assert (opcode
< table
->num_opcodes
);
3015 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3017 TransitionRule
*rule
= l
->rule
;
3018 BuildInstr
*build_list
;
3023 build_list
= rule
->to_instr
;
3024 if (is_unique_insn_expansion (rule
))
3026 assert (build_list
->typ
== INSTR_INSTR
);
3027 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3030 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3032 switch (build_list
->typ
)
3035 this_size
+= xg_get_single_size (build_list
->opcode
);
3037 case INSTR_LITERAL_DEF
:
3038 case INSTR_LABEL_DEF
:
3043 if (this_size
> max_size
)
3044 max_size
= this_size
;
3050 /* Return the maximum number of literal bytes this opcode can generate. */
3053 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3055 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3059 assert (opcode
< table
->num_opcodes
);
3061 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3063 TransitionRule
*rule
= l
->rule
;
3064 BuildInstr
*build_list
;
3069 build_list
= rule
->to_instr
;
3070 if (is_unique_insn_expansion (rule
))
3072 assert (build_list
->typ
== INSTR_INSTR
);
3073 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3076 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3078 switch (build_list
->typ
)
3080 case INSTR_LITERAL_DEF
:
3081 /* Hard-coded 4-byte literal. */
3085 case INSTR_LABEL_DEF
:
3090 if (this_size
> max_size
)
3091 max_size
= this_size
;
3098 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3100 int steps_taken
= 0;
3101 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3104 assert (insn
->insn_type
== ITYPE_INSN
);
3105 assert (insn
->opcode
< table
->num_opcodes
);
3107 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3109 TransitionRule
*rule
= l
->rule
;
3111 if (xg_instruction_matches_rule (insn
, rule
))
3113 if (steps_taken
== lateral_steps
)
3123 get_special_literal_symbol (void)
3125 static symbolS
*sym
= NULL
;
3128 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3134 get_special_label_symbol (void)
3136 static symbolS
*sym
= NULL
;
3139 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3145 xg_valid_literal_expression (const expressionS
*exp
)
3162 /* This will check to see if the value can be converted into the
3163 operand type. It will return TRUE if it does not fit. */
3166 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3168 uint32 valbuf
= value
;
3169 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3175 /* Assumes: All immeds are constants. Check that all constants fit
3176 into their immeds; return FALSE if not. */
3179 xg_immeds_fit (const TInsn
*insn
)
3181 xtensa_isa isa
= xtensa_default_isa
;
3185 assert (insn
->insn_type
== ITYPE_INSN
);
3186 for (i
= 0; i
< n
; ++i
)
3188 const expressionS
*expr
= &insn
->tok
[i
];
3189 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3196 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3201 /* The symbol should have a fixup associated with it. */
3210 /* This should only be called after we have an initial
3211 estimate of the addresses. */
3214 xg_symbolic_immeds_fit (const TInsn
*insn
,
3220 xtensa_isa isa
= xtensa_default_isa
;
3228 assert (insn
->insn_type
== ITYPE_INSN
);
3230 for (i
= 0; i
< n
; ++i
)
3232 const expressionS
*expr
= &insn
->tok
[i
];
3233 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3240 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3246 /* Check for the worst case. */
3247 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3252 /* We only allow symbols for PC-relative references.
3253 If pc_frag == 0, then we don't have frag locations yet. */
3255 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3258 /* If it is a weak symbol, then assume it won't reach. */
3259 if (S_IS_WEAK (expr
->X_add_symbol
))
3262 if (is_direct_call_opcode (insn
->opcode
)
3263 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3265 /* If callee is undefined or in a different segment, be
3266 optimistic and assume it will be in range. */
3267 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3271 /* Only references within a segment can be known to fit in the
3272 operands at assembly time. */
3273 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3276 symbolP
= expr
->X_add_symbol
;
3277 sym_frag
= symbol_get_frag (symbolP
);
3278 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3279 pc
= pc_frag
->fr_address
+ pc_offset
;
3281 /* If frag has yet to be reached on this pass, assume it
3282 will move by STRETCH just as we did. If this is not so,
3283 it will be because some frag between grows, and that will
3284 force another pass. Beware zero-length frags. There
3285 should be a faster way to do this. */
3288 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3289 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3294 new_offset
= target
;
3295 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3296 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3301 /* The symbol should have a fixup associated with it. */
3310 /* Return TRUE on success. */
3313 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3318 memset (targ
, 0, sizeof (TInsn
));
3319 targ
->linenum
= insn
->linenum
;
3324 targ
->opcode
= bi
->opcode
;
3325 targ
->insn_type
= ITYPE_INSN
;
3326 targ
->is_specific_opcode
= FALSE
;
3328 for (; op
!= NULL
; op
= op
->next
)
3330 int op_num
= op
->op_num
;
3331 int op_data
= op
->op_data
;
3333 assert (op
->op_num
< MAX_INSN_ARGS
);
3335 if (targ
->ntok
<= op_num
)
3336 targ
->ntok
= op_num
+ 1;
3341 set_expr_const (&targ
->tok
[op_num
], op_data
);
3344 assert (op_data
< insn
->ntok
);
3345 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3348 sym
= get_special_literal_symbol ();
3349 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3352 sym
= get_special_label_symbol ();
3353 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3355 case OP_OPERAND_HI16U
:
3356 case OP_OPERAND_LOW16U
:
3357 assert (op_data
< insn
->ntok
);
3358 if (expr_is_const (&insn
->tok
[op_data
]))
3361 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3362 val
= xg_apply_userdef_op_fn (op
->typ
,
3365 targ
->tok
[op_num
].X_add_number
= val
;
3369 /* For const16 we can create relocations for these. */
3370 if (targ
->opcode
== XTENSA_UNDEFINED
3371 || (targ
->opcode
!= xtensa_const16_opcode
))
3373 assert (op_data
< insn
->ntok
);
3374 /* Need to build a O_lo16 or O_hi16. */
3375 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3376 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3378 if (op
->typ
== OP_OPERAND_HI16U
)
3379 targ
->tok
[op_num
].X_op
= O_hi16
;
3380 else if (op
->typ
== OP_OPERAND_LOW16U
)
3381 targ
->tok
[op_num
].X_op
= O_lo16
;
3388 /* currently handles:
3391 OP_OPERAND_F32MINUS */
3392 if (xg_has_userdef_op_fn (op
->typ
))
3394 assert (op_data
< insn
->ntok
);
3395 if (expr_is_const (&insn
->tok
[op_data
]))
3398 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3399 val
= xg_apply_userdef_op_fn (op
->typ
,
3402 targ
->tok
[op_num
].X_add_number
= val
;
3405 return FALSE
; /* We cannot use a relocation for this. */
3414 case INSTR_LITERAL_DEF
:
3416 targ
->opcode
= XTENSA_UNDEFINED
;
3417 targ
->insn_type
= ITYPE_LITERAL
;
3418 targ
->is_specific_opcode
= FALSE
;
3419 for (; op
!= NULL
; op
= op
->next
)
3421 int op_num
= op
->op_num
;
3422 int op_data
= op
->op_data
;
3423 assert (op
->op_num
< MAX_INSN_ARGS
);
3425 if (targ
->ntok
<= op_num
)
3426 targ
->ntok
= op_num
+ 1;
3431 assert (op_data
< insn
->ntok
);
3432 /* We can only pass resolvable literals through. */
3433 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3435 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3447 case INSTR_LABEL_DEF
:
3449 targ
->opcode
= XTENSA_UNDEFINED
;
3450 targ
->insn_type
= ITYPE_LABEL
;
3451 targ
->is_specific_opcode
= FALSE
;
3452 /* Literal with no ops is a label? */
3453 assert (op
== NULL
);
3464 /* Return TRUE on success. */
3467 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3469 for (; bi
!= NULL
; bi
= bi
->next
)
3471 TInsn
*next_insn
= istack_push_space (istack
);
3473 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3480 /* Return TRUE on valid expansion. */
3483 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3485 int stack_size
= istack
->ninsn
;
3486 int steps_taken
= 0;
3487 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3490 assert (insn
->insn_type
== ITYPE_INSN
);
3491 assert (insn
->opcode
< table
->num_opcodes
);
3493 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3495 TransitionRule
*rule
= l
->rule
;
3497 if (xg_instruction_matches_rule (insn
, rule
))
3499 if (lateral_steps
== steps_taken
)
3503 /* This is it. Expand the rule to the stack. */
3504 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3507 /* Check to see if it fits. */
3508 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3510 TInsn
*insn
= &istack
->insn
[i
];
3512 if (insn
->insn_type
== ITYPE_INSN
3513 && !tinsn_has_symbolic_operands (insn
)
3514 && !xg_immeds_fit (insn
))
3516 istack
->ninsn
= stack_size
;
3529 /* Relax the assembly instruction at least "min_steps".
3530 Return the number of steps taken. */
3533 xg_assembly_relax (IStack
*istack
,
3536 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3537 offsetT pc_offset
, /* offset in fragment */
3538 int min_steps
, /* minimum conversion steps */
3539 long stretch
) /* number of bytes stretched so far */
3541 int steps_taken
= 0;
3543 /* assert (has no symbolic operands)
3544 Some of its immeds don't fit.
3545 Try to build a relaxed version.
3546 This may go through a couple of stages
3547 of single instruction transformations before
3550 TInsn single_target
;
3552 int lateral_steps
= 0;
3553 int istack_size
= istack
->ninsn
;
3555 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3556 && steps_taken
>= min_steps
)
3558 istack_push (istack
, insn
);
3561 current_insn
= *insn
;
3563 /* Walk through all of the single instruction expansions. */
3564 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3567 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3570 if (steps_taken
>= min_steps
)
3572 istack_push (istack
, &single_target
);
3576 current_insn
= single_target
;
3579 /* Now check for a multi-instruction expansion. */
3580 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3582 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3585 if (steps_taken
>= min_steps
)
3587 istack_push (istack
, ¤t_insn
);
3592 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3594 if (steps_taken
>= min_steps
)
3598 istack
->ninsn
= istack_size
;
3601 /* It's not going to work -- use the original. */
3602 istack_push (istack
, insn
);
3608 xg_force_frag_space (int size
)
3610 /* This may have the side effect of creating a new fragment for the
3611 space to go into. I just do not like the name of the "frag"
3618 xg_finish_frag (char *last_insn
,
3619 enum xtensa_relax_statesE frag_state
,
3620 enum xtensa_relax_statesE slot0_state
,
3622 bfd_boolean is_insn
)
3624 /* Finish off this fragment so that it has at LEAST the desired
3625 max_growth. If it doesn't fit in this fragment, close this one
3626 and start a new one. In either case, return a pointer to the
3627 beginning of the growth area. */
3631 xg_force_frag_space (max_growth
);
3633 old_frag
= frag_now
;
3635 frag_now
->fr_opcode
= last_insn
;
3637 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3639 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3640 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3642 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3643 xtensa_set_frag_assembly_state (frag_now
);
3645 /* Just to make sure that we did not split it up. */
3646 assert (old_frag
->fr_next
== frag_now
);
3650 /* Return TRUE if the target frag is one of the next non-empty frags. */
3653 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3658 for (; fragP
; fragP
= fragP
->fr_next
)
3660 if (fragP
== target
)
3662 if (fragP
->fr_fix
!= 0)
3664 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3666 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3667 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3669 if (fragP
->fr_type
== rs_space
)
3677 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3679 xtensa_isa isa
= xtensa_default_isa
;
3681 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3686 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3687 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3690 for (i
= 0; i
< num_ops
; i
++)
3692 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3698 if (target_op
== -1)
3701 if (insn
->ntok
<= target_op
)
3704 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3707 sym
= insn
->tok
[target_op
].X_add_symbol
;
3711 if (insn
->tok
[target_op
].X_add_number
!= 0)
3714 target_frag
= symbol_get_frag (sym
);
3715 if (target_frag
== NULL
)
3718 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3719 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3727 xg_add_branch_and_loop_targets (TInsn
*insn
)
3729 xtensa_isa isa
= xtensa_default_isa
;
3730 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3732 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3735 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3736 && insn
->tok
[i
].X_op
== O_symbol
)
3737 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3741 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3742 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3746 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3748 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3749 && insn
->tok
[i
].X_op
== O_symbol
)
3751 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3752 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3753 if (S_IS_DEFINED (sym
))
3754 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3761 /* Return FALSE if no error. */
3764 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3769 switch (instr_spec
->typ
)
3772 new_insn
->insn_type
= ITYPE_INSN
;
3773 new_insn
->opcode
= instr_spec
->opcode
;
3774 new_insn
->is_specific_opcode
= FALSE
;
3775 new_insn
->linenum
= old_insn
->linenum
;
3777 case INSTR_LITERAL_DEF
:
3778 new_insn
->insn_type
= ITYPE_LITERAL
;
3779 new_insn
->opcode
= XTENSA_UNDEFINED
;
3780 new_insn
->is_specific_opcode
= FALSE
;
3781 new_insn
->linenum
= old_insn
->linenum
;
3783 case INSTR_LABEL_DEF
:
3784 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3788 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3791 const expressionS
*src_exp
;
3797 /* The expression must be the constant. */
3798 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3799 exp
= &new_insn
->tok
[b_op
->op_num
];
3800 set_expr_const (exp
, b_op
->op_data
);
3804 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3805 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3806 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3807 exp
= &new_insn
->tok
[b_op
->op_num
];
3808 copy_expr (exp
, src_exp
);
3813 as_bad (_("can't handle generation of literal/labels yet"));
3817 as_bad (_("can't handle undefined OP TYPE"));
3822 new_insn
->ntok
= num_ops
;
3827 /* Return TRUE if it was simplified. */
3830 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3832 TransitionRule
*rule
;
3833 BuildInstr
*insn_spec
;
3835 if (old_insn
->is_specific_opcode
|| !density_supported
)
3838 rule
= xg_instruction_match (old_insn
);
3842 insn_spec
= rule
->to_instr
;
3843 /* There should only be one. */
3844 assert (insn_spec
!= NULL
);
3845 assert (insn_spec
->next
== NULL
);
3846 if (insn_spec
->next
!= NULL
)
3849 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3855 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3856 l32i.n. (2) Check the number of operands. (3) Place the instruction
3857 tokens into the stack or relax it and place multiple
3858 instructions/literals onto the stack. Return FALSE if no error. */
3861 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3865 bfd_boolean do_expand
;
3867 memset (&new_insn
, 0, sizeof (TInsn
));
3869 /* Narrow it if we can. xg_simplify_insn now does all the
3870 appropriate checking (e.g., for the density option). */
3871 if (xg_simplify_insn (orig_insn
, &new_insn
))
3872 orig_insn
= &new_insn
;
3874 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3876 if (orig_insn
->ntok
< noperands
)
3878 as_bad (_("found %d operands for '%s': Expected %d"),
3880 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3884 if (orig_insn
->ntok
> noperands
)
3885 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3887 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3890 /* If there are not enough operands, we will assert above. If there
3891 are too many, just cut out the extras here. */
3892 orig_insn
->ntok
= noperands
;
3894 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3897 /* If the instruction will definitely need to be relaxed, it is better
3898 to expand it now for better scheduling. Decide whether to expand
3900 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3902 /* Calls should be expanded to longcalls only in the backend relaxation
3903 so that the assembly scheduler will keep the L32R/CALLX instructions
3905 if (is_direct_call_opcode (orig_insn
->opcode
))
3908 if (tinsn_has_symbolic_operands (orig_insn
))
3910 /* The values of symbolic operands are not known yet, so only expand
3911 now if an operand is "complex" (e.g., difference of symbols) and
3912 will have to be stored as a literal regardless of the value. */
3913 if (!tinsn_has_complex_operands (orig_insn
))
3916 else if (xg_immeds_fit (orig_insn
))
3920 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3922 istack_push (istack
, orig_insn
);
3928 /* Return TRUE if the section flags are marked linkonce
3929 or the name is .gnu.linkonce*. */
3932 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3934 flagword flags
, link_once_flags
;
3936 flags
= bfd_get_section_flags (abfd
, sec
);
3937 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3939 /* Flags might not be set yet. */
3940 if (!link_once_flags
)
3942 static size_t len
= sizeof ".gnu.linkonce.t.";
3944 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
3945 link_once_flags
= SEC_LINK_ONCE
;
3947 return (link_once_flags
!= 0);
3952 xtensa_add_literal_sym (symbolS
*sym
)
3956 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3958 l
->next
= literal_syms
;
3964 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3966 static int lit_num
= 0;
3967 static char name
[256];
3970 sprintf (name
, ".L_lit_sym%d", lit_num
);
3972 /* Create a local symbol. If it is in a linkonce section, we have to
3973 be careful to make sure that if it is used in a relocation that the
3974 symbol will be in the output file. */
3975 if (get_is_linkonce_section (stdoutput
, sec
))
3977 symbolP
= symbol_new (name
, sec
, 0, frag
);
3978 S_CLEAR_EXTERNAL (symbolP
);
3979 /* symbolP->local = 1; */
3982 symbolP
= symbol_new (name
, sec
, 0, frag
);
3984 xtensa_add_literal_sym (symbolP
);
3986 frag
->tc_frag_data
.is_literal
= TRUE
;
3992 /* Currently all literals that are generated here are 32-bit L32R targets. */
3995 xg_assemble_literal (/* const */ TInsn
*insn
)
3998 symbolS
*lit_sym
= NULL
;
4000 /* size = 4 for L32R. It could easily be larger when we move to
4001 larger constants. Add a parameter later. */
4002 offsetT litsize
= 4;
4003 offsetT litalign
= 2; /* 2^2 = 4 */
4004 expressionS saved_loc
;
4005 expressionS
* emit_val
;
4007 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4009 assert (insn
->insn_type
== ITYPE_LITERAL
);
4010 assert (insn
->ntok
== 1); /* must be only one token here */
4012 xtensa_switch_to_literal_fragment (&state
);
4014 emit_val
= &insn
->tok
[0];
4015 if (emit_val
->X_op
== O_big
)
4017 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4020 /* This happens when someone writes a "movi a2, big_number". */
4021 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4022 _("invalid immediate"));
4023 xtensa_restore_emit_state (&state
);
4028 /* Force a 4-byte align here. Note that this opens a new frag, so all
4029 literals done with this function have a frag to themselves. That's
4030 important for the way text section literals work. */
4031 frag_align (litalign
, 0, 0);
4032 record_alignment (now_seg
, litalign
);
4034 if (emit_val
->X_op
== O_pltrel
)
4036 char *p
= frag_more (litsize
);
4037 xtensa_set_frag_assembly_state (frag_now
);
4038 if (emit_val
->X_add_symbol
)
4039 emit_val
->X_op
= O_symbol
;
4041 emit_val
->X_op
= O_constant
;
4042 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4043 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4046 emit_expr (emit_val
, litsize
);
4048 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4049 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4050 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4051 lit_sym
= frag_now
->fr_symbol
;
4052 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4055 xtensa_restore_emit_state (&state
);
4061 xg_assemble_literal_space (/* const */ int size
, int slot
)
4064 /* We might have to do something about this alignment. It only
4065 takes effect if something is placed here. */
4066 offsetT litalign
= 2; /* 2^2 = 4 */
4067 fragS
*lit_saved_frag
;
4069 assert (size
% 4 == 0);
4071 xtensa_switch_to_literal_fragment (&state
);
4073 /* Force a 4-byte align here. */
4074 frag_align (litalign
, 0, 0);
4075 record_alignment (now_seg
, litalign
);
4077 xg_force_frag_space (size
);
4079 lit_saved_frag
= frag_now
;
4080 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4081 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4082 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4083 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4086 xtensa_restore_emit_state (&state
);
4087 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4091 /* Put in a fixup record based on the opcode.
4092 Return TRUE on success. */
4095 xg_add_opcode_fix (TInsn
*tinsn
,
4103 xtensa_opcode opcode
= tinsn
->opcode
;
4104 bfd_reloc_code_real_type reloc
;
4105 reloc_howto_type
*howto
;
4109 reloc
= BFD_RELOC_NONE
;
4111 /* First try the special cases for "alternate" relocs. */
4112 if (opcode
== xtensa_l32r_opcode
)
4114 if (fragP
->tc_frag_data
.use_absolute_literals
)
4115 reloc
= encode_alt_reloc (slot
);
4117 else if (opcode
== xtensa_const16_opcode
)
4119 if (expr
->X_op
== O_lo16
)
4121 reloc
= encode_reloc (slot
);
4122 expr
->X_op
= O_symbol
;
4124 else if (expr
->X_op
== O_hi16
)
4126 reloc
= encode_alt_reloc (slot
);
4127 expr
->X_op
= O_symbol
;
4131 if (opnum
!= get_relaxable_immed (opcode
))
4133 as_bad (_("invalid relocation for operand %i of '%s'"),
4134 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4138 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4139 into the symbol table where the generic portions of the assembler
4140 won't know what to do with them. */
4141 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4143 as_bad (_("invalid expression for operand %i of '%s'"),
4144 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4148 /* Next try the generic relocs. */
4149 if (reloc
== BFD_RELOC_NONE
)
4150 reloc
= encode_reloc (slot
);
4151 if (reloc
== BFD_RELOC_NONE
)
4153 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4157 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4160 as_bad (_("undefined symbol for opcode \"%s\""),
4161 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4165 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4166 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4167 howto
->pc_relative
, reloc
);
4168 the_fix
->fx_no_overflow
= 1;
4170 if (expr
->X_add_symbol
4171 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4172 || S_IS_WEAK (expr
->X_add_symbol
)))
4173 the_fix
->fx_plt
= TRUE
;
4175 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4176 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4177 the_fix
->tc_fix_data
.slot
= slot
;
4184 xg_emit_insn_to_buf (TInsn
*tinsn
,
4188 bfd_boolean build_fix
)
4190 static xtensa_insnbuf insnbuf
= NULL
;
4191 bfd_boolean has_symbolic_immed
= FALSE
;
4192 bfd_boolean ok
= TRUE
;
4195 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4197 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4198 if (has_symbolic_immed
&& build_fix
)
4201 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4202 int slot
= xg_get_single_slot (tinsn
->opcode
);
4203 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4204 expressionS
*exp
= &tinsn
->tok
[opnum
];
4206 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4209 fragP
->tc_frag_data
.is_insn
= TRUE
;
4210 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4211 (unsigned char *) buf
, 0);
4217 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4219 symbolS
*sym
= get_special_literal_symbol ();
4223 assert (insn
->insn_type
== ITYPE_INSN
);
4224 for (i
= 0; i
< insn
->ntok
; i
++)
4225 if (insn
->tok
[i
].X_add_symbol
== sym
)
4226 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4232 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4234 symbolS
*sym
= get_special_label_symbol ();
4236 /* assert (!insn->is_literal); */
4237 for (i
= 0; i
< insn
->ntok
; i
++)
4238 if (insn
->tok
[i
].X_add_symbol
== sym
)
4239 insn
->tok
[i
].X_add_symbol
= label_sym
;
4244 /* Return TRUE if the instruction can write to the specified
4245 integer register. */
4248 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4252 xtensa_isa isa
= xtensa_default_isa
;
4254 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4256 for (i
= 0; i
< num_ops
; i
++)
4259 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4260 if ((inout
== 'o' || inout
== 'm')
4261 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4263 xtensa_regfile opnd_rf
=
4264 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4265 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4267 if ((insn
->tok
[i
].X_op
== O_register
)
4268 && (insn
->tok
[i
].X_add_number
== regnum
))
4278 is_bad_loopend_opcode (const TInsn
*tinsn
)
4280 xtensa_opcode opcode
= tinsn
->opcode
;
4282 if (opcode
== XTENSA_UNDEFINED
)
4285 if (opcode
== xtensa_call0_opcode
4286 || opcode
== xtensa_callx0_opcode
4287 || opcode
== xtensa_call4_opcode
4288 || opcode
== xtensa_callx4_opcode
4289 || opcode
== xtensa_call8_opcode
4290 || opcode
== xtensa_callx8_opcode
4291 || opcode
== xtensa_call12_opcode
4292 || opcode
== xtensa_callx12_opcode
4293 || opcode
== xtensa_isync_opcode
4294 || opcode
== xtensa_ret_opcode
4295 || opcode
== xtensa_ret_n_opcode
4296 || opcode
== xtensa_retw_opcode
4297 || opcode
== xtensa_retw_n_opcode
4298 || opcode
== xtensa_waiti_opcode
4299 || opcode
== xtensa_rsr_lcount_opcode
)
4306 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4307 This allows the debugger to add unaligned labels.
4308 Also, the assembler generates stabs labels that need
4309 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4312 is_unaligned_label (symbolS
*sym
)
4314 const char *name
= S_GET_NAME (sym
);
4315 static size_t fake_size
= 0;
4319 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4322 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4324 fake_size
= strlen (FAKE_LABEL_NAME
);
4327 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4328 && (name
[fake_size
] == 'F'
4329 || name
[fake_size
] == 'L'
4330 || (name
[fake_size
] == 'e'
4331 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4339 next_non_empty_frag (const fragS
*fragP
)
4341 fragS
*next_fragP
= fragP
->fr_next
;
4343 /* Sometimes an empty will end up here due storage allocation issues.
4344 So we have to skip until we find something legit. */
4345 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4346 next_fragP
= next_fragP
->fr_next
;
4348 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4356 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4358 xtensa_opcode out_opcode
;
4359 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4361 if (next_fragP
== NULL
)
4364 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4365 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4367 *opcode
= out_opcode
;
4375 frag_format_size (const fragS
*fragP
)
4377 static xtensa_insnbuf insnbuf
= NULL
;
4378 xtensa_isa isa
= xtensa_default_isa
;
4383 insnbuf
= xtensa_insnbuf_alloc (isa
);
4386 return XTENSA_UNDEFINED
;
4388 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4389 (unsigned char *) fragP
->fr_literal
, 0);
4391 fmt
= xtensa_format_decode (isa
, insnbuf
);
4392 if (fmt
== XTENSA_UNDEFINED
)
4393 return XTENSA_UNDEFINED
;
4394 fmt_size
= xtensa_format_length (isa
, fmt
);
4396 /* If the next format won't be changing due to relaxation, just
4397 return the length of the first format. */
4398 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4401 /* If during relaxation we have to pull an instruction out of a
4402 multi-slot instruction, we will return the more conservative
4403 number. This works because alignment on bigger instructions
4404 is more restrictive than alignment on smaller instructions.
4405 This is more conservative than we would like, but it happens
4408 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4411 /* If we aren't doing one of our own relaxations or it isn't
4412 slot-based, then the insn size won't change. */
4413 if (fragP
->fr_type
!= rs_machine_dependent
)
4415 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4418 /* If an instruction is about to grow, return the longer size. */
4419 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4420 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4423 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4424 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4431 next_frag_format_size (const fragS
*fragP
)
4433 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4434 return frag_format_size (next_fragP
);
4438 /* If the next legit fragment is an end-of-loop marker,
4439 switch its state so it will instantiate a NOP. */
4442 update_next_frag_state (fragS
*fragP
)
4444 fragS
*next_fragP
= fragP
->fr_next
;
4445 fragS
*new_target
= NULL
;
4449 /* We are guaranteed there will be one of these... */
4450 while (!(next_fragP
->fr_type
== rs_machine_dependent
4451 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4452 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4453 next_fragP
= next_fragP
->fr_next
;
4455 assert (next_fragP
->fr_type
== rs_machine_dependent
4456 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4457 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4459 /* ...and one of these. */
4460 new_target
= next_fragP
->fr_next
;
4461 while (!(new_target
->fr_type
== rs_machine_dependent
4462 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4463 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4464 new_target
= new_target
->fr_next
;
4466 assert (new_target
->fr_type
== rs_machine_dependent
4467 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4468 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4471 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4473 if (next_fragP
->fr_type
== rs_machine_dependent
4474 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4476 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4480 next_fragP
= next_fragP
->fr_next
;
4486 next_frag_is_branch_target (const fragS
*fragP
)
4488 /* Sometimes an empty will end up here due to storage allocation issues,
4489 so we have to skip until we find something legit. */
4490 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4492 if (fragP
->tc_frag_data
.is_branch_target
)
4494 if (fragP
->fr_fix
!= 0)
4502 next_frag_is_loop_target (const fragS
*fragP
)
4504 /* Sometimes an empty will end up here due storage allocation issues.
4505 So we have to skip until we find something legit. */
4506 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4508 if (fragP
->tc_frag_data
.is_loop_target
)
4510 if (fragP
->fr_fix
!= 0)
4518 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4520 const fragS
*next_fragp
= fragp
->fr_next
;
4521 xtensa_opcode next_opcode
;
4523 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4526 /* Sometimes an empty will end up here due to storage allocation issues,
4527 so we have to skip until we find something legit. */
4528 while (next_fragp
->fr_fix
== 0)
4529 next_fragp
= next_fragp
->fr_next
;
4531 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4534 /* There is some implicit knowledge encoded in here.
4535 The LOOP instructions that are NOT RELAX_IMMED have
4536 been relaxed. Note that we can assume that the LOOP
4537 instruction is in slot 0 because loops aren't bundleable. */
4538 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4539 return get_expanded_loop_offset (next_opcode
);
4545 /* Mark a location where we can later insert literal frags. Update
4546 the section's literal_pool_loc, so subsequent literals can be
4547 placed nearest to their use. */
4550 xtensa_mark_literal_pool_location (void)
4552 /* Any labels pointing to the current location need
4553 to be adjusted to after the literal pool. */
4555 fragS
*pool_location
;
4557 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4560 frag_align (2, 0, 0);
4561 record_alignment (now_seg
, 2);
4563 /* We stash info in these frags so we can later move the literal's
4564 fixes into this frchain's fix list. */
4565 pool_location
= frag_now
;
4566 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4567 frag_variant (rs_machine_dependent
, 0, 0,
4568 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4569 xtensa_set_frag_assembly_state (frag_now
);
4570 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4571 frag_variant (rs_machine_dependent
, 0, 0,
4572 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4573 xtensa_set_frag_assembly_state (frag_now
);
4575 /* Now put a frag into the literal pool that points to this location. */
4576 set_literal_pool_location (now_seg
, pool_location
);
4577 xtensa_switch_to_non_abs_literal_fragment (&s
);
4578 frag_align (2, 0, 0);
4579 record_alignment (now_seg
, 2);
4581 /* Close whatever frag is there. */
4582 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4583 xtensa_set_frag_assembly_state (frag_now
);
4584 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4585 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4586 xtensa_restore_emit_state (&s
);
4587 xtensa_set_frag_assembly_state (frag_now
);
4591 /* Build a nop of the correct size into tinsn. */
4594 build_nop (TInsn
*tinsn
, int size
)
4600 tinsn
->opcode
= xtensa_nop_n_opcode
;
4602 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4603 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4607 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4609 tinsn
->opcode
= xtensa_or_opcode
;
4610 set_expr_const (&tinsn
->tok
[0], 1);
4611 set_expr_const (&tinsn
->tok
[1], 1);
4612 set_expr_const (&tinsn
->tok
[2], 1);
4616 tinsn
->opcode
= xtensa_nop_opcode
;
4618 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4623 /* Assemble a NOP of the requested size in the buffer. User must have
4624 allocated "buf" with at least "size" bytes. */
4627 assemble_nop (int size
, char *buf
)
4629 static xtensa_insnbuf insnbuf
= NULL
;
4632 build_nop (&tinsn
, size
);
4635 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4637 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4638 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4639 (unsigned char *) buf
, 0);
4643 /* Return the number of bytes for the offset of the expanded loop
4644 instruction. This should be incorporated into the relaxation
4645 specification but is hard-coded here. This is used to auto-align
4646 the loop instruction. It is invalid to call this function if the
4647 configuration does not have loops or if the opcode is not a loop
4651 get_expanded_loop_offset (xtensa_opcode opcode
)
4653 /* This is the OFFSET of the loop instruction in the expanded loop.
4654 This MUST correspond directly to the specification of the loop
4655 expansion. It will be validated on fragment conversion. */
4656 assert (opcode
!= XTENSA_UNDEFINED
);
4657 if (opcode
== xtensa_loop_opcode
)
4659 if (opcode
== xtensa_loopnez_opcode
)
4661 if (opcode
== xtensa_loopgtz_opcode
)
4663 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4669 get_literal_pool_location (segT seg
)
4671 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4676 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4678 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4682 /* Set frag assembly state should be called when a new frag is
4683 opened and after a frag has been closed. */
4686 xtensa_set_frag_assembly_state (fragS
*fragP
)
4688 if (!density_supported
)
4689 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4691 /* This function is called from subsegs_finish, which is called
4692 after xtensa_end, so we can't use "use_transform" or
4693 "use_schedule" here. */
4694 if (!directive_state
[directive_transform
])
4695 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4696 if (directive_state
[directive_longcalls
])
4697 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4698 fragP
->tc_frag_data
.use_absolute_literals
=
4699 directive_state
[directive_absolute_literals
];
4700 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4705 relaxable_section (asection
*sec
)
4707 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4712 xtensa_find_unmarked_state_frags (void)
4716 /* Walk over each fragment of all of the current segments. For each
4717 unmarked fragment, mark it with the same info as the previous
4719 for (seclist
= &stdoutput
->sections
;
4720 seclist
&& *seclist
;
4721 seclist
= &(*seclist
)->next
)
4723 segT sec
= *seclist
;
4724 segment_info_type
*seginfo
;
4727 flags
= bfd_get_section_flags (stdoutput
, sec
);
4728 if (flags
& SEC_DEBUGGING
)
4730 if (!(flags
& SEC_ALLOC
))
4733 seginfo
= seg_info (sec
);
4734 if (seginfo
&& seginfo
->frchainP
)
4736 fragS
*last_fragP
= 0;
4737 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4738 fragP
= fragP
->fr_next
)
4740 if (fragP
->fr_fix
!= 0
4741 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4743 if (last_fragP
== 0)
4745 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4746 _("assembly state not set for first frag in section %s"),
4751 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4752 fragP
->tc_frag_data
.is_no_density
=
4753 last_fragP
->tc_frag_data
.is_no_density
;
4754 fragP
->tc_frag_data
.is_no_transform
=
4755 last_fragP
->tc_frag_data
.is_no_transform
;
4756 fragP
->tc_frag_data
.use_longcalls
=
4757 last_fragP
->tc_frag_data
.use_longcalls
;
4758 fragP
->tc_frag_data
.use_absolute_literals
=
4759 last_fragP
->tc_frag_data
.use_absolute_literals
;
4762 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4771 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4773 void *unused ATTRIBUTE_UNUSED
)
4775 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4776 segment_info_type
*seginfo
= seg_info (sec
);
4777 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4779 if (flags
& SEC_CODE
)
4781 xtensa_isa isa
= xtensa_default_isa
;
4782 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4783 while (frag
!= NULL
)
4785 if (frag
->tc_frag_data
.is_branch_target
)
4788 addressT branch_align
, frag_addr
;
4791 xtensa_insnbuf_from_chars
4792 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4793 fmt
= xtensa_format_decode (isa
, insnbuf
);
4794 op_size
= xtensa_format_length (isa
, fmt
);
4795 branch_align
= 1 << branch_align_power (sec
);
4796 frag_addr
= frag
->fr_address
% branch_align
;
4797 if (frag_addr
+ op_size
> branch_align
)
4798 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4799 _("unaligned branch target: %d bytes at 0x%lx"),
4800 op_size
, (long) frag
->fr_address
);
4802 frag
= frag
->fr_next
;
4804 xtensa_insnbuf_free (isa
, insnbuf
);
4810 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4812 void *unused ATTRIBUTE_UNUSED
)
4814 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4815 segment_info_type
*seginfo
= seg_info (sec
);
4816 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4817 xtensa_isa isa
= xtensa_default_isa
;
4819 if (flags
& SEC_CODE
)
4821 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4822 while (frag
!= NULL
)
4824 if (frag
->tc_frag_data
.is_first_loop_insn
)
4830 xtensa_insnbuf_from_chars
4831 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4832 fmt
= xtensa_format_decode (isa
, insnbuf
);
4833 op_size
= xtensa_format_length (isa
, fmt
);
4834 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4836 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4837 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4838 _("unaligned loop: %d bytes at 0x%lx"),
4839 op_size
, (long) frag
->fr_address
);
4841 frag
= frag
->fr_next
;
4843 xtensa_insnbuf_free (isa
, insnbuf
);
4849 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4851 xtensa_isa isa
= xtensa_default_isa
;
4852 static xtensa_insnbuf insnbuf
= NULL
;
4853 static xtensa_insnbuf slotbuf
= NULL
;
4856 bfd_boolean alt_reloc
;
4857 xtensa_opcode opcode
;
4858 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4860 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4862 as_fatal (_("unexpected fix"));
4866 insnbuf
= xtensa_insnbuf_alloc (isa
);
4867 slotbuf
= xtensa_insnbuf_alloc (isa
);
4870 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4871 fmt
= xtensa_format_decode (isa
, insnbuf
);
4872 if (fmt
== XTENSA_UNDEFINED
)
4873 as_fatal (_("undecodable fix"));
4874 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4875 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4876 if (opcode
== XTENSA_UNDEFINED
)
4877 as_fatal (_("undecodable fix"));
4879 /* CONST16 immediates are not PC-relative, despite the fact that we
4880 reuse the normal PC-relative operand relocations for the low part
4881 of a CONST16 operand. */
4882 if (opcode
== xtensa_const16_opcode
)
4885 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4886 get_relaxable_immed (opcode
), val
,
4887 fixP
->fx_file
, fixP
->fx_line
);
4889 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4890 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4896 /* External Functions and Other GAS Hooks. */
4899 xtensa_target_format (void)
4901 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4906 xtensa_file_arch_init (bfd
*abfd
)
4908 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4913 md_number_to_chars (char *buf
, valueT val
, int n
)
4915 if (target_big_endian
)
4916 number_to_chars_bigendian (buf
, val
, n
);
4918 number_to_chars_littleendian (buf
, val
, n
);
4922 /* This function is called once, at assembler startup time. It should
4923 set up all the tables, etc. that the MD part of the assembler will
4929 segT current_section
= now_seg
;
4930 int current_subsec
= now_subseg
;
4933 xtensa_default_isa
= xtensa_isa_init (0, 0);
4934 isa
= xtensa_default_isa
;
4938 /* Set up the .literal, .fini.literal and .init.literal sections. */
4939 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4940 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
4941 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
4942 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
4943 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
4945 subseg_set (current_section
, current_subsec
);
4947 xg_init_vinsn (&cur_vinsn
);
4949 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4950 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4951 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4952 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4953 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4954 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4955 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4956 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4957 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4958 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4959 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4960 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4961 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4962 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4963 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4964 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4965 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4966 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4967 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4968 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4969 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4970 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4971 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4972 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4973 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4974 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4975 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4976 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4977 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4979 init_op_placement_info_table ();
4981 /* Set up the assembly state. */
4982 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4983 xtensa_set_frag_assembly_state (frag_now
);
4987 /* TC_INIT_FIX_DATA hook */
4990 xtensa_init_fix_data (fixS
*x
)
4992 x
->tc_fix_data
.slot
= 0;
4993 x
->tc_fix_data
.X_add_symbol
= NULL
;
4994 x
->tc_fix_data
.X_add_number
= 0;
4998 /* tc_frob_label hook */
5001 xtensa_frob_label (symbolS
*sym
)
5005 if (cur_vinsn
.inside_bundle
)
5007 as_bad (_("labels are not valid inside bundles"));
5011 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5013 /* Since the label was already attached to a frag associated with the
5014 previous basic block, it now needs to be reset to the current frag. */
5015 symbol_set_frag (sym
, frag_now
);
5016 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5018 if (generating_literals
)
5019 xtensa_add_literal_sym (sym
);
5021 xtensa_add_insn_label (sym
);
5023 if (symbol_get_tc (sym
)->is_loop_target
)
5025 if ((get_last_insn_flags (now_seg
, now_subseg
)
5026 & FLAG_IS_BAD_LOOPEND
) != 0)
5027 as_bad (_("invalid last instruction for a zero-overhead loop"));
5029 xtensa_set_frag_assembly_state (frag_now
);
5030 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5031 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5033 xtensa_set_frag_assembly_state (frag_now
);
5034 xtensa_move_labels (frag_now
, 0, TRUE
);
5037 /* No target aligning in the absolute section. */
5038 if (now_seg
!= absolute_section
5039 && do_align_targets ()
5040 && !is_unaligned_label (sym
)
5041 && !generating_literals
)
5043 xtensa_set_frag_assembly_state (frag_now
);
5045 frag_var (rs_machine_dependent
,
5047 RELAX_DESIRE_ALIGN_IF_TARGET
,
5048 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5049 xtensa_set_frag_assembly_state (frag_now
);
5050 xtensa_move_labels (frag_now
, 0, TRUE
);
5053 /* We need to mark the following properties even if we aren't aligning. */
5055 /* If the label is already known to be a branch target, i.e., a
5056 forward branch, mark the frag accordingly. Backward branches
5057 are handled by xg_add_branch_and_loop_targets. */
5058 if (symbol_get_tc (sym
)->is_branch_target
)
5059 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5061 /* Loops only go forward, so they can be identified here. */
5062 if (symbol_get_tc (sym
)->is_loop_target
)
5063 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5065 dwarf2_emit_label (sym
);
5069 /* tc_unrecognized_line hook */
5072 xtensa_unrecognized_line (int ch
)
5077 if (cur_vinsn
.inside_bundle
== 0)
5079 /* PR8110: Cannot emit line number info inside a FLIX bundle
5080 when using --gstabs. Temporarily disable debug info. */
5081 generate_lineno_debug ();
5082 if (debug_type
== DEBUG_STABS
)
5084 xt_saved_debug_type
= debug_type
;
5085 debug_type
= DEBUG_NONE
;
5088 cur_vinsn
.inside_bundle
= 1;
5092 as_bad (_("extra opening brace"));
5098 if (cur_vinsn
.inside_bundle
)
5099 finish_vinsn (&cur_vinsn
);
5102 as_bad (_("extra closing brace"));
5107 as_bad (_("syntax error"));
5114 /* md_flush_pending_output hook */
5117 xtensa_flush_pending_output (void)
5119 if (cur_vinsn
.inside_bundle
)
5120 as_bad (_("missing closing brace"));
5122 /* If there is a non-zero instruction fragment, close it. */
5123 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5125 frag_wane (frag_now
);
5127 xtensa_set_frag_assembly_state (frag_now
);
5129 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5131 xtensa_clear_insn_labels ();
5135 /* We had an error while parsing an instruction. The string might look
5136 like this: "insn arg1, arg2 }". If so, we need to see the closing
5137 brace and reset some fields. Otherwise, the vinsn never gets closed
5138 and the num_slots field will grow past the end of the array of slots,
5139 and bad things happen. */
5142 error_reset_cur_vinsn (void)
5144 if (cur_vinsn
.inside_bundle
)
5146 if (*input_line_pointer
== '}'
5147 || *(input_line_pointer
- 1) == '}'
5148 || *(input_line_pointer
- 2) == '}')
5149 xg_clear_vinsn (&cur_vinsn
);
5155 md_assemble (char *str
)
5157 xtensa_isa isa
= xtensa_default_isa
;
5158 char *opname
, *file_name
;
5160 bfd_boolean has_underbar
= FALSE
;
5161 char *arg_strings
[MAX_INSN_ARGS
];
5163 TInsn orig_insn
; /* Original instruction from the input. */
5165 tinsn_init (&orig_insn
);
5167 /* Split off the opcode. */
5168 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5169 opname
= xmalloc (opnamelen
+ 1);
5170 memcpy (opname
, str
, opnamelen
);
5171 opname
[opnamelen
] = '\0';
5173 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5176 as_bad (_("syntax error"));
5180 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5183 /* Check for an underbar prefix. */
5186 has_underbar
= TRUE
;
5190 orig_insn
.insn_type
= ITYPE_INSN
;
5192 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5194 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5195 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5197 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5198 if (fmt
== XTENSA_UNDEFINED
)
5200 as_bad (_("unknown opcode or format name '%s'"), opname
);
5201 error_reset_cur_vinsn ();
5204 if (!cur_vinsn
.inside_bundle
)
5206 as_bad (_("format names only valid inside bundles"));
5207 error_reset_cur_vinsn ();
5210 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5211 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5213 cur_vinsn
.format
= fmt
;
5214 free (has_underbar
? opname
- 1 : opname
);
5215 error_reset_cur_vinsn ();
5219 /* Parse the arguments. */
5220 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5222 as_bad (_("syntax error"));
5223 error_reset_cur_vinsn ();
5227 /* Free the opcode and argument strings, now that they've been parsed. */
5228 free (has_underbar
? opname
- 1 : opname
);
5230 while (num_args
-- > 0)
5231 free (arg_strings
[num_args
]);
5233 /* Get expressions for invisible operands. */
5234 if (get_invisible_operands (&orig_insn
))
5236 error_reset_cur_vinsn ();
5240 /* Check for the right number and type of arguments. */
5241 if (tinsn_check_arguments (&orig_insn
))
5243 error_reset_cur_vinsn ();
5247 /* A FLIX bundle may be spread across multiple input lines. We want to
5248 report the first such line in the debug information. Record the line
5249 number for each TInsn (assume the file name doesn't change), so the
5250 first line can be found later. */
5251 as_where (&file_name
, &orig_insn
.linenum
);
5253 xg_add_branch_and_loop_targets (&orig_insn
);
5255 /* Check that immediate value for ENTRY is >= 16. */
5256 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5258 expressionS
*exp
= &orig_insn
.tok
[2];
5259 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5260 as_warn (_("entry instruction with stack decrement < 16"));
5264 assemble_tokens (opcode, tok, ntok);
5265 expand the tokens from the orig_insn into the
5266 stack of instructions that will not expand
5267 unless required at relaxation time. */
5269 if (!cur_vinsn
.inside_bundle
)
5270 emit_single_op (&orig_insn
);
5271 else /* We are inside a bundle. */
5273 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5274 cur_vinsn
.num_slots
++;
5275 if (*input_line_pointer
== '}'
5276 || *(input_line_pointer
- 1) == '}'
5277 || *(input_line_pointer
- 2) == '}')
5278 finish_vinsn (&cur_vinsn
);
5281 /* We've just emitted a new instruction so clear the list of labels. */
5282 xtensa_clear_insn_labels ();
5286 /* HANDLE_ALIGN hook */
5288 /* For a .align directive, we mark the previous block with the alignment
5289 information. This will be placed in the object file in the
5290 property section corresponding to this section. */
5293 xtensa_handle_align (fragS
*fragP
)
5296 && ! fragP
->tc_frag_data
.is_literal
5297 && (fragP
->fr_type
== rs_align
5298 || fragP
->fr_type
== rs_align_code
)
5299 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5300 && fragP
->fr_offset
> 0
5301 && now_seg
!= bss_section
)
5303 fragP
->tc_frag_data
.is_align
= TRUE
;
5304 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5307 if (fragP
->fr_type
== rs_align_test
)
5310 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5312 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5313 _("unaligned entry instruction"));
5318 /* TC_FRAG_INIT hook */
5321 xtensa_frag_init (fragS
*frag
)
5323 xtensa_set_frag_assembly_state (frag
);
5328 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5334 /* Round up a section size to the appropriate boundary. */
5337 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5339 return size
; /* Byte alignment is fine. */
5344 md_pcrel_from (fixS
*fixP
)
5347 static xtensa_insnbuf insnbuf
= NULL
;
5348 static xtensa_insnbuf slotbuf
= NULL
;
5351 xtensa_opcode opcode
;
5354 xtensa_isa isa
= xtensa_default_isa
;
5355 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5356 bfd_boolean alt_reloc
;
5358 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5363 insnbuf
= xtensa_insnbuf_alloc (isa
);
5364 slotbuf
= xtensa_insnbuf_alloc (isa
);
5367 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5368 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5369 fmt
= xtensa_format_decode (isa
, insnbuf
);
5371 if (fmt
== XTENSA_UNDEFINED
)
5372 as_fatal (_("bad instruction format"));
5374 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5375 as_fatal (_("invalid relocation"));
5377 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5378 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5380 /* Check for "alternate" relocations (operand not specified). None
5381 of the current uses for these are really PC-relative. */
5382 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5384 if (opcode
!= xtensa_l32r_opcode
5385 && opcode
!= xtensa_const16_opcode
)
5386 as_fatal (_("invalid relocation for '%s' instruction"),
5387 xtensa_opcode_name (isa
, opcode
));
5391 opnum
= get_relaxable_immed (opcode
);
5393 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5394 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5396 as_bad_where (fixP
->fx_file
,
5398 _("invalid relocation for operand %d of '%s'"),
5399 opnum
, xtensa_opcode_name (isa
, opcode
));
5402 return 0 - opnd_value
;
5406 /* TC_FORCE_RELOCATION hook */
5409 xtensa_force_relocation (fixS
*fix
)
5411 switch (fix
->fx_r_type
)
5413 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5414 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5415 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5416 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5417 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5418 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5419 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5420 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5421 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5422 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5423 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5424 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5425 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5426 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5427 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5428 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5434 if (linkrelax
&& fix
->fx_addsy
5435 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5438 return generic_force_reloc (fix
);
5442 /* TC_VALIDATE_FIX_SUB hook */
5445 xtensa_validate_fix_sub (fixS
*fix
)
5447 segT add_symbol_segment
, sub_symbol_segment
;
5449 /* The difference of two symbols should be resolved by the assembler when
5450 linkrelax is not set. If the linker may relax the section containing
5451 the symbols, then an Xtensa DIFF relocation must be generated so that
5452 the linker knows to adjust the difference value. */
5453 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5456 /* Make sure both symbols are in the same segment, and that segment is
5457 "normal" and relaxable. If the segment is not "normal", then the
5458 fix is not valid. If the segment is not "relaxable", then the fix
5459 should have been handled earlier. */
5460 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5461 if (! SEG_NORMAL (add_symbol_segment
) ||
5462 ! relaxable_section (add_symbol_segment
))
5464 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5465 return (sub_symbol_segment
== add_symbol_segment
);
5469 /* NO_PSEUDO_DOT hook */
5471 /* This function has nothing to do with pseudo dots, but this is the
5472 nearest macro to where the check needs to take place. FIXME: This
5476 xtensa_check_inside_bundle (void)
5478 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5479 as_bad (_("directives are not valid inside bundles"));
5481 /* This function must always return FALSE because it is called via a
5482 macro that has nothing to do with bundling. */
5487 /* md_elf_section_change_hook */
5490 xtensa_elf_section_change_hook (void)
5492 /* Set up the assembly state. */
5493 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5494 xtensa_set_frag_assembly_state (frag_now
);
5498 /* tc_fix_adjustable hook */
5501 xtensa_fix_adjustable (fixS
*fixP
)
5503 /* An offset is not allowed in combination with the difference of two
5504 symbols, but that cannot be easily detected after a local symbol
5505 has been adjusted to a (section+offset) form. Return 0 so that such
5506 an fix will not be adjusted. */
5507 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5508 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5511 /* We need the symbol name for the VTABLE entries. */
5512 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5513 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5521 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5523 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5526 /* Subtracted symbols are only allowed for a few relocation types, and
5527 unless linkrelax is enabled, they should not make it to this point. */
5528 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5529 || fixP
->fx_r_type
== BFD_RELOC_16
5530 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5533 switch (fixP
->fx_r_type
)
5540 switch (fixP
->fx_r_type
)
5543 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5546 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5549 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5555 /* An offset is only allowed when it results from adjusting a
5556 local symbol into a section-relative offset. If the offset
5557 came from the original expression, tc_fix_adjustable will have
5558 prevented the fix from being converted to a section-relative
5559 form so that we can flag the error here. */
5560 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5561 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5562 _("cannot represent subtraction with an offset"));
5564 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5565 - S_GET_VALUE (fixP
->fx_subsy
));
5567 /* The difference value gets written out, and the DIFF reloc
5568 identifies the address of the subtracted symbol (i.e., the one
5569 with the lowest address). */
5571 fixP
->fx_offset
-= val
;
5572 fixP
->fx_subsy
= NULL
;
5574 else if (! fixP
->fx_addsy
)
5581 case BFD_RELOC_XTENSA_PLT
:
5582 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5583 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5586 case BFD_RELOC_XTENSA_SLOT0_OP
:
5587 case BFD_RELOC_XTENSA_SLOT1_OP
:
5588 case BFD_RELOC_XTENSA_SLOT2_OP
:
5589 case BFD_RELOC_XTENSA_SLOT3_OP
:
5590 case BFD_RELOC_XTENSA_SLOT4_OP
:
5591 case BFD_RELOC_XTENSA_SLOT5_OP
:
5592 case BFD_RELOC_XTENSA_SLOT6_OP
:
5593 case BFD_RELOC_XTENSA_SLOT7_OP
:
5594 case BFD_RELOC_XTENSA_SLOT8_OP
:
5595 case BFD_RELOC_XTENSA_SLOT9_OP
:
5596 case BFD_RELOC_XTENSA_SLOT10_OP
:
5597 case BFD_RELOC_XTENSA_SLOT11_OP
:
5598 case BFD_RELOC_XTENSA_SLOT12_OP
:
5599 case BFD_RELOC_XTENSA_SLOT13_OP
:
5600 case BFD_RELOC_XTENSA_SLOT14_OP
:
5603 /* Write the tentative value of a PC-relative relocation to a
5604 local symbol into the instruction. The value will be ignored
5605 by the linker, and it makes the object file disassembly
5606 readable when all branch targets are encoded in relocations. */
5608 assert (fixP
->fx_addsy
);
5609 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5610 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5612 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5613 - md_pcrel_from (fixP
));
5614 (void) xg_apply_fix_value (fixP
, val
);
5617 else if (! fixP
->fx_addsy
)
5620 if (xg_apply_fix_value (fixP
, val
))
5625 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5626 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5627 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5628 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5629 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5630 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5631 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5632 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5633 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5634 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5635 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5636 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5637 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5638 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5639 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5640 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5641 /* These all need to be resolved at link-time. Do nothing now. */
5644 case BFD_RELOC_VTABLE_INHERIT
:
5645 case BFD_RELOC_VTABLE_ENTRY
:
5650 as_bad (_("unhandled local relocation fix %s"),
5651 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5657 md_atof (int type
, char *litP
, int *sizeP
)
5660 LITTLENUM_TYPE words
[4];
5676 return "bad call to md_atof";
5679 t
= atof_ieee (input_line_pointer
, type
, words
);
5681 input_line_pointer
= t
;
5685 for (i
= prec
- 1; i
>= 0; i
--)
5688 if (target_big_endian
)
5689 idx
= (prec
- 1 - i
);
5691 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5700 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5702 return total_frag_text_expansion (fragP
);
5706 /* Translate internal representation of relocation info to BFD target
5710 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5714 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5715 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5716 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5717 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5719 /* Make sure none of our internal relocations make it this far.
5720 They'd better have been fully resolved by this point. */
5721 assert ((int) fixp
->fx_r_type
> 0);
5723 reloc
->addend
= fixp
->fx_offset
;
5725 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5726 if (reloc
->howto
== NULL
)
5728 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5729 _("cannot represent `%s' relocation in object file"),
5730 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5731 free (reloc
->sym_ptr_ptr
);
5736 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5737 as_fatal (_("internal error? cannot generate `%s' relocation"),
5738 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5744 /* Checks for resource conflicts between instructions. */
5746 /* The func unit stuff could be implemented as bit-vectors rather
5747 than the iterative approach here. If it ends up being too
5748 slow, we will switch it. */
5751 new_resource_table (void *data
,
5754 unit_num_copies_func uncf
,
5755 opcode_num_units_func onuf
,
5756 opcode_funcUnit_use_unit_func ouuf
,
5757 opcode_funcUnit_use_stage_func ousf
)
5760 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5762 rt
->cycles
= cycles
;
5763 rt
->allocated_cycles
= cycles
;
5765 rt
->unit_num_copies
= uncf
;
5766 rt
->opcode_num_units
= onuf
;
5767 rt
->opcode_unit_use
= ouuf
;
5768 rt
->opcode_unit_stage
= ousf
;
5770 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5771 for (i
= 0; i
< cycles
; i
++)
5772 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5779 clear_resource_table (resource_table
*rt
)
5782 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5783 for (j
= 0; j
< rt
->num_units
; j
++)
5784 rt
->units
[i
][j
] = 0;
5788 /* We never shrink it, just fake it into thinking so. */
5791 resize_resource_table (resource_table
*rt
, int cycles
)
5795 rt
->cycles
= cycles
;
5796 if (cycles
<= rt
->allocated_cycles
)
5799 old_cycles
= rt
->allocated_cycles
;
5800 rt
->allocated_cycles
= cycles
;
5802 rt
->units
= xrealloc (rt
->units
,
5803 rt
->allocated_cycles
* sizeof (unsigned char *));
5804 for (i
= 0; i
< old_cycles
; i
++)
5805 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5806 rt
->num_units
* sizeof (unsigned char));
5807 for (i
= old_cycles
; i
< cycles
; i
++)
5808 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5813 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5816 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5818 for (i
= 0; i
< uses
; i
++)
5820 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5821 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5822 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5823 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5824 if (copies_in_use
>= copies
)
5832 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5835 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5837 for (i
= 0; i
< uses
; i
++)
5839 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5840 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5841 /* Note that this allows resources to be oversubscribed. That's
5842 essential to the way the optional scheduler works.
5843 resources_available reports when a resource is over-subscribed,
5844 so it's easy to tell. */
5845 rt
->units
[stage
+ cycle
][unit
]++;
5851 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5854 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5856 for (i
= 0; i
< uses
; i
++)
5858 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5859 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5860 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5861 rt
->units
[stage
+ cycle
][unit
]--;
5866 /* Wrapper functions make parameterized resource reservation
5870 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5872 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5878 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5880 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5885 /* Note that this function does not check issue constraints, but
5886 solely whether the hardware is available to execute the given
5887 instructions together. It also doesn't check if the tinsns
5888 write the same state, or access the same tieports. That is
5889 checked by check_t1_t2_reads_and_writes. */
5892 resources_conflict (vliw_insn
*vinsn
)
5895 static resource_table
*rt
= NULL
;
5897 /* This is the most common case by far. Optimize it. */
5898 if (vinsn
->num_slots
== 1)
5903 xtensa_isa isa
= xtensa_default_isa
;
5904 rt
= new_resource_table
5905 (isa
, xtensa_isa_num_pipe_stages (isa
),
5906 xtensa_isa_num_funcUnits (isa
),
5907 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5908 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5909 opcode_funcUnit_use_unit
,
5910 opcode_funcUnit_use_stage
);
5913 clear_resource_table (rt
);
5915 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5917 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5919 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5926 /* finish_vinsn, emit_single_op and helper functions. */
5928 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5929 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5930 static void xg_assemble_vliw_tokens (vliw_insn
*);
5933 /* We have reached the end of a bundle; emit into the frag. */
5936 finish_vinsn (vliw_insn
*vinsn
)
5943 if (find_vinsn_conflicts (vinsn
))
5945 xg_clear_vinsn (vinsn
);
5949 /* First, find a format that works. */
5950 if (vinsn
->format
== XTENSA_UNDEFINED
)
5951 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5953 if (vinsn
->format
== XTENSA_UNDEFINED
)
5955 as_where (&file_name
, &line
);
5956 as_bad_where (file_name
, line
,
5957 _("couldn't find a valid instruction format"));
5958 fprintf (stderr
, _(" ops were: "));
5959 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5960 fprintf (stderr
, _(" %s;"),
5961 xtensa_opcode_name (xtensa_default_isa
,
5962 vinsn
->slots
[i
].opcode
));
5963 fprintf (stderr
, _("\n"));
5964 xg_clear_vinsn (vinsn
);
5968 if (vinsn
->num_slots
5969 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5971 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5972 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5973 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5975 xg_clear_vinsn (vinsn
);
5979 if (resources_conflict (vinsn
))
5981 as_where (&file_name
, &line
);
5982 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5983 fprintf (stderr
, " ops were: ");
5984 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5985 fprintf (stderr
, " %s;",
5986 xtensa_opcode_name (xtensa_default_isa
,
5987 vinsn
->slots
[i
].opcode
));
5988 fprintf (stderr
, "\n");
5989 xg_clear_vinsn (vinsn
);
5993 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5995 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
5997 symbolS
*lit_sym
= NULL
;
5999 bfd_boolean e
= FALSE
;
6000 bfd_boolean saved_density
= density_supported
;
6002 /* We don't want to narrow ops inside multi-slot bundles. */
6003 if (vinsn
->num_slots
> 1)
6004 density_supported
= FALSE
;
6006 istack_init (&slotstack
);
6007 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6009 vinsn
->slots
[i
].opcode
=
6010 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6012 vinsn
->slots
[i
].ntok
= 0;
6015 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6021 density_supported
= saved_density
;
6025 xg_clear_vinsn (vinsn
);
6029 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6031 TInsn
*insn
= &slotstack
.insn
[j
];
6032 if (insn
->insn_type
== ITYPE_LITERAL
)
6034 assert (lit_sym
== NULL
);
6035 lit_sym
= xg_assemble_literal (insn
);
6039 assert (insn
->insn_type
== ITYPE_INSN
);
6041 xg_resolve_literals (insn
, lit_sym
);
6042 if (j
!= slotstack
.ninsn
- 1)
6043 emit_single_op (insn
);
6047 if (vinsn
->num_slots
> 1)
6049 if (opcode_fits_format_slot
6050 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6053 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6057 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6058 if (vinsn
->format
== XTENSA_UNDEFINED
)
6059 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6061 vinsn
->slots
[i
].opcode
6062 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6065 vinsn
->slots
[i
].ntok
= 0;
6070 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6071 vinsn
->format
= XTENSA_UNDEFINED
;
6076 /* Now check resource conflicts on the modified bundle. */
6077 if (resources_conflict (vinsn
))
6079 as_where (&file_name
, &line
);
6080 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6081 fprintf (stderr
, " ops were: ");
6082 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6083 fprintf (stderr
, " %s;",
6084 xtensa_opcode_name (xtensa_default_isa
,
6085 vinsn
->slots
[i
].opcode
));
6086 fprintf (stderr
, "\n");
6087 xg_clear_vinsn (vinsn
);
6091 /* First, find a format that works. */
6092 if (vinsn
->format
== XTENSA_UNDEFINED
)
6093 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6095 xg_assemble_vliw_tokens (vinsn
);
6097 xg_clear_vinsn (vinsn
);
6101 /* Given an vliw instruction, what conflicts are there in register
6102 usage and in writes to states and queues?
6104 This function does two things:
6105 1. Reports an error when a vinsn contains illegal combinations
6106 of writes to registers states or queues.
6107 2. Marks individual tinsns as not relaxable if the combination
6108 contains antidependencies.
6110 Job 2 handles things like swap semantics in instructions that need
6111 to be relaxed. For example,
6115 normally would be relaxed to
6120 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6122 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6124 then we can't relax it into
6127 { add a0, a1, a0 ; add a2, a0, a4 ; }
6129 because the value of a0 is trashed before the second add can read it. */
6131 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6134 find_vinsn_conflicts (vliw_insn
*vinsn
)
6138 xtensa_isa isa
= xtensa_default_isa
;
6140 assert (!past_xtensa_end
);
6142 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6144 TInsn
*op1
= &vinsn
->slots
[i
];
6145 if (op1
->is_specific_opcode
)
6146 op1
->keep_wide
= TRUE
;
6148 op1
->keep_wide
= FALSE
;
6151 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6153 TInsn
*op1
= &vinsn
->slots
[i
];
6155 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6158 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6162 TInsn
*op2
= &vinsn
->slots
[j
];
6163 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6164 switch (conflict_type
)
6167 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6168 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6169 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6172 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6173 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6174 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6177 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6178 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6179 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6182 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6183 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6184 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6187 /* Everything is OK. */
6190 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6191 || conflict_type
== 'a');
6198 as_bad (_("multiple branches or jumps in the same bundle"));
6206 /* Check how the state used by t1 and t2 relate.
6209 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6210 case B: no relationship between what is read and written (both could
6211 read the same reg though)
6212 case C: t1 writes a register t2 writes (a register conflict within a
6214 case D: t1 writes a state that t2 also writes
6215 case E: t1 writes a tie queue that t2 also writes
6216 case F: two volatile queue accesses
6220 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6222 xtensa_isa isa
= xtensa_default_isa
;
6223 xtensa_regfile t1_regfile
, t2_regfile
;
6225 int t1_base_reg
, t1_last_reg
;
6226 int t2_base_reg
, t2_last_reg
;
6227 char t1_inout
, t2_inout
;
6229 char conflict
= 'b';
6234 bfd_boolean t1_volatile
= FALSE
;
6235 bfd_boolean t2_volatile
= FALSE
;
6237 /* Check registers. */
6238 for (j
= 0; j
< t2
->ntok
; j
++)
6240 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6243 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6244 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6245 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6247 for (i
= 0; i
< t1
->ntok
; i
++)
6249 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6252 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6254 if (t1_regfile
!= t2_regfile
)
6257 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6258 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6260 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6261 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6263 if (t1_inout
== 'm' || t1_inout
== 'o'
6264 || t2_inout
== 'm' || t2_inout
== 'o')
6271 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6272 t1_last_reg
= (t1_base_reg
6273 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6275 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6277 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6279 if (t1_reg
!= t2_reg
)
6282 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6288 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6294 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6302 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6303 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6304 for (j
= 0; j
< t2_states
; j
++)
6306 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6307 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6308 for (i
= 0; i
< t1_states
; i
++)
6310 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6311 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6315 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6321 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6327 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6332 /* Check tieports. */
6333 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6334 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6335 for (j
= 0; j
< t2_interfaces
; j
++)
6337 xtensa_interface t2_int
6338 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6339 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6341 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6342 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6345 for (i
= 0; i
< t1_interfaces
; i
++)
6347 xtensa_interface t1_int
6348 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6349 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6351 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6352 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6355 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6358 if (t1_int
!= t2_int
)
6361 if (t2_inout
== 'i' && t1_inout
== 'o')
6367 if (t1_inout
== 'i' && t2_inout
== 'o')
6373 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6382 static xtensa_format
6383 xg_find_narrowest_format (vliw_insn
*vinsn
)
6385 /* Right now we assume that the ops within the vinsn are properly
6386 ordered for the slots that the programmer wanted them in. In
6387 other words, we don't rearrange the ops in hopes of finding a
6388 better format. The scheduler handles that. */
6390 xtensa_isa isa
= xtensa_default_isa
;
6391 xtensa_format format
;
6392 vliw_insn v_copy
= *vinsn
;
6393 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6395 if (vinsn
->num_slots
== 1)
6396 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6398 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6401 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6405 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6407 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6409 v_copy
.slots
[slot
].opcode
=
6410 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6411 v_copy
.slots
[slot
].ntok
= 0;
6414 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6417 else if (v_copy
.num_slots
> 1)
6420 /* Try the widened version. */
6421 if (!v_copy
.slots
[slot
].keep_wide
6422 && !v_copy
.slots
[slot
].is_specific_opcode
6423 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6425 && opcode_fits_format_slot (widened
.opcode
,
6428 v_copy
.slots
[slot
] = widened
;
6433 if (fit
== v_copy
.num_slots
)
6436 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6437 vinsn
->format
= format
;
6443 if (format
== xtensa_isa_num_formats (isa
))
6444 return XTENSA_UNDEFINED
;
6450 /* Return the additional space needed in a frag
6451 for possible relaxations of any ops in a VLIW insn.
6452 Also fill out the relaxations that might be required of
6453 each tinsn in the vinsn. */
6456 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6458 bfd_boolean finish_frag
= FALSE
;
6459 int extra_space
= 0;
6462 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6464 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6465 if (!tinsn_has_symbolic_operands (tinsn
))
6467 /* A narrow instruction could be widened later to help
6468 alignment issues. */
6469 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6470 && !tinsn
->is_specific_opcode
6471 && vinsn
->num_slots
== 1)
6473 /* Difference in bytes between narrow and wide insns... */
6475 tinsn
->subtype
= RELAX_NARROW
;
6480 if (workaround_b_j_loop_end
6481 && tinsn
->opcode
== xtensa_jx_opcode
6482 && use_transform ())
6484 /* Add 2 of these. */
6485 extra_space
+= 3; /* for the nop size */
6486 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6489 /* Need to assemble it with space for the relocation. */
6490 if (xg_is_relaxable_insn (tinsn
, 0)
6491 && !tinsn
->is_specific_opcode
)
6493 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6494 int max_literal_size
=
6495 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6497 tinsn
->literal_space
= max_literal_size
;
6499 tinsn
->subtype
= RELAX_IMMED
;
6500 extra_space
+= max_size
;
6504 /* A fix record will be added for this instruction prior
6505 to relaxation, so make it end the frag. */
6510 *pfinish_frag
= finish_frag
;
6516 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6518 xtensa_isa isa
= xtensa_default_isa
;
6519 int slot
, chosen_slot
;
6521 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6522 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6523 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6525 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6526 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6528 if (slot
== chosen_slot
)
6529 vinsn
->slots
[slot
] = *tinsn
;
6532 vinsn
->slots
[slot
].opcode
=
6533 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6534 vinsn
->slots
[slot
].ntok
= 0;
6535 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6542 emit_single_op (TInsn
*orig_insn
)
6545 IStack istack
; /* put instructions into here */
6546 symbolS
*lit_sym
= NULL
;
6547 symbolS
*label_sym
= NULL
;
6549 istack_init (&istack
);
6551 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6552 Because the scheduling and bundling characteristics of movi and
6553 l32r or const16 are so different, we can do much better if we relax
6554 it prior to scheduling and bundling, rather than after. */
6555 if ((orig_insn
->opcode
== xtensa_movi_opcode
6556 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6557 && !cur_vinsn
.inside_bundle
6558 && (orig_insn
->tok
[1].X_op
== O_symbol
6559 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6560 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6562 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6565 for (i
= 0; i
< istack
.ninsn
; i
++)
6567 TInsn
*insn
= &istack
.insn
[i
];
6568 switch (insn
->insn_type
)
6571 assert (lit_sym
== NULL
);
6572 lit_sym
= xg_assemble_literal (insn
);
6576 static int relaxed_sym_idx
= 0;
6577 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6578 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6580 assert (label_sym
== NULL
);
6581 label_sym
= symbol_find_or_make (label
);
6590 xg_resolve_literals (insn
, lit_sym
);
6592 xg_resolve_labels (insn
, label_sym
);
6594 bundle_tinsn (insn
, &v
);
6609 total_frag_text_expansion (fragS
*fragP
)
6612 int total_expansion
= 0;
6614 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6615 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6617 return total_expansion
;
6621 /* Emit a vliw instruction to the current fragment. */
6624 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6626 bfd_boolean finish_frag
;
6627 bfd_boolean is_jump
= FALSE
;
6628 bfd_boolean is_branch
= FALSE
;
6629 xtensa_isa isa
= xtensa_default_isa
;
6635 unsigned current_line
, best_linenum
;
6638 best_linenum
= UINT_MAX
;
6640 if (generating_literals
)
6642 static int reported
= 0;
6644 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6645 _("cannot assemble into a literal fragment"));
6652 if (frag_now_fix () != 0
6653 && (! frag_now
->tc_frag_data
.is_insn
6654 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6655 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6656 || (directive_state
[directive_longcalls
]
6657 != frag_now
->tc_frag_data
.use_longcalls
)
6658 || (directive_state
[directive_absolute_literals
]
6659 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6661 frag_wane (frag_now
);
6663 xtensa_set_frag_assembly_state (frag_now
);
6666 if (workaround_a0_b_retw
6667 && vinsn
->num_slots
== 1
6668 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6669 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6670 && use_transform ())
6672 has_a0_b_retw
= TRUE
;
6674 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6675 After the first assembly pass we will check all of them and
6676 add a nop if needed. */
6677 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6678 frag_var (rs_machine_dependent
, 4, 4,
6679 RELAX_ADD_NOP_IF_A0_B_RETW
,
6680 frag_now
->fr_symbol
,
6681 frag_now
->fr_offset
,
6683 xtensa_set_frag_assembly_state (frag_now
);
6684 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6685 frag_var (rs_machine_dependent
, 4, 4,
6686 RELAX_ADD_NOP_IF_A0_B_RETW
,
6687 frag_now
->fr_symbol
,
6688 frag_now
->fr_offset
,
6690 xtensa_set_frag_assembly_state (frag_now
);
6693 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6695 /* See if the instruction implies an aligned section. */
6696 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6697 record_alignment (now_seg
, 2);
6699 /* Also determine the best line number for debug info. */
6700 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6701 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6704 /* Special cases for instructions that force an alignment... */
6705 /* None of these opcodes are bundle-able. */
6706 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6710 xtensa_set_frag_assembly_state (frag_now
);
6711 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6713 max_fill
= get_text_align_max_fill_size
6714 (get_text_align_power (xtensa_fetch_width
),
6715 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6717 if (use_transform ())
6718 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6719 RELAX_ALIGN_NEXT_OPCODE
,
6720 frag_now
->fr_symbol
,
6721 frag_now
->fr_offset
,
6724 frag_var (rs_machine_dependent
, 0, 0,
6725 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6726 xtensa_set_frag_assembly_state (frag_now
);
6728 xtensa_move_labels (frag_now
, 0, FALSE
);
6731 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6732 && !vinsn
->slots
[0].is_specific_opcode
)
6734 xtensa_mark_literal_pool_location ();
6735 xtensa_move_labels (frag_now
, 0, TRUE
);
6736 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6739 if (vinsn
->num_slots
== 1)
6741 if (workaround_a0_b_retw
&& use_transform ())
6742 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6743 is_register_writer (&vinsn
->slots
[0], "a", 0));
6745 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6746 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6749 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6751 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6753 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6755 /* vinsn_to_insnbuf will produce the error. */
6756 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6758 f
= frag_more (insn_size
+ extra_space
);
6759 xtensa_set_frag_assembly_state (frag_now
);
6760 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6763 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6764 if (vinsn
->format
== XTENSA_UNDEFINED
)
6767 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6769 /* Temporarily set the logical line number to the one we want to appear
6770 in the debug information. */
6771 as_where (¤t_file
, ¤t_line
);
6772 new_logical_line (current_file
, best_linenum
);
6773 dwarf2_emit_insn (insn_size
+ extra_space
);
6774 new_logical_line (current_file
, current_line
);
6776 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6778 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6779 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6780 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6781 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6782 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6783 if (tinsn
->literal_space
!= 0)
6784 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6786 if (tinsn
->subtype
== RELAX_NARROW
)
6787 assert (vinsn
->num_slots
== 1);
6788 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6790 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6793 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6794 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6798 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6799 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6803 frag_variant (rs_machine_dependent
,
6804 extra_space
, extra_space
, RELAX_SLOTS
,
6805 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6806 xtensa_set_frag_assembly_state (frag_now
);
6809 /* Special cases for loops:
6810 close_loop_end should be inserted AFTER short_loop.
6811 Make sure that CLOSE loops are processed BEFORE short_loops
6812 when converting them. */
6814 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6815 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6816 && !vinsn
->slots
[0].is_specific_opcode
)
6818 if (workaround_short_loop
&& use_transform ())
6820 maybe_has_short_loop
= TRUE
;
6821 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6822 frag_var (rs_machine_dependent
, 4, 4,
6823 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6824 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6825 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6826 frag_var (rs_machine_dependent
, 4, 4,
6827 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6828 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6831 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6832 loop at least 12 bytes away from another loop's end. */
6833 if (workaround_close_loop_end
&& use_transform ())
6835 maybe_has_close_loop_end
= TRUE
;
6836 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6837 frag_var (rs_machine_dependent
, 12, 12,
6838 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6839 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6843 if (use_transform ())
6847 assert (finish_frag
);
6848 frag_var (rs_machine_dependent
,
6849 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6851 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6852 xtensa_set_frag_assembly_state (frag_now
);
6854 else if (is_branch
&& do_align_targets ())
6856 assert (finish_frag
);
6857 frag_var (rs_machine_dependent
,
6858 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6859 RELAX_MAYBE_UNREACHABLE
,
6860 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6861 xtensa_set_frag_assembly_state (frag_now
);
6862 frag_var (rs_machine_dependent
,
6864 RELAX_MAYBE_DESIRE_ALIGN
,
6865 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6866 xtensa_set_frag_assembly_state (frag_now
);
6870 /* Now, if the original opcode was a call... */
6871 if (do_align_targets ()
6872 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6874 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6875 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6876 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6877 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6878 xtensa_set_frag_assembly_state (frag_now
);
6881 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6883 frag_wane (frag_now
);
6885 xtensa_set_frag_assembly_state (frag_now
);
6890 /* xtensa_end and helper functions. */
6892 static void xtensa_cleanup_align_frags (void);
6893 static void xtensa_fix_target_frags (void);
6894 static void xtensa_mark_narrow_branches (void);
6895 static void xtensa_mark_zcl_first_insns (void);
6896 static void xtensa_fix_a0_b_retw_frags (void);
6897 static void xtensa_fix_b_j_loop_end_frags (void);
6898 static void xtensa_fix_close_loop_end_frags (void);
6899 static void xtensa_fix_short_loop_frags (void);
6900 static void xtensa_sanity_check (void);
6905 directive_balance ();
6906 xtensa_flush_pending_output ();
6908 past_xtensa_end
= TRUE
;
6910 xtensa_move_literals ();
6912 xtensa_reorder_segments ();
6913 xtensa_cleanup_align_frags ();
6914 xtensa_fix_target_frags ();
6915 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6916 xtensa_fix_a0_b_retw_frags ();
6917 if (workaround_b_j_loop_end
)
6918 xtensa_fix_b_j_loop_end_frags ();
6920 /* "close_loop_end" should be processed BEFORE "short_loop". */
6921 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6922 xtensa_fix_close_loop_end_frags ();
6924 if (workaround_short_loop
&& maybe_has_short_loop
)
6925 xtensa_fix_short_loop_frags ();
6926 xtensa_mark_narrow_branches ();
6927 xtensa_mark_zcl_first_insns ();
6929 xtensa_sanity_check ();
6934 xtensa_cleanup_align_frags (void)
6938 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
6941 /* Walk over all of the fragments in a subsection. */
6942 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6944 if ((fragP
->fr_type
== rs_align
6945 || fragP
->fr_type
== rs_align_code
6946 || (fragP
->fr_type
== rs_machine_dependent
6947 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6948 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6949 && fragP
->fr_fix
== 0)
6951 fragS
*next
= fragP
->fr_next
;
6954 && next
->fr_fix
== 0
6955 && next
->fr_type
== rs_machine_dependent
6956 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6959 next
= next
->fr_next
;
6962 /* If we don't widen branch targets, then they
6963 will be easier to align. */
6964 if (fragP
->tc_frag_data
.is_branch_target
6965 && fragP
->fr_opcode
== fragP
->fr_literal
6966 && fragP
->fr_type
== rs_machine_dependent
6967 && fragP
->fr_subtype
== RELAX_SLOTS
6968 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6970 if (fragP
->fr_type
== rs_machine_dependent
6971 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6972 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
6978 /* Re-process all of the fragments looking to convert all of the
6979 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
6980 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
6981 Otherwise, convert to a .fill 0. */
6984 xtensa_fix_target_frags (void)
6988 /* When this routine is called, all of the subsections are still intact
6989 so we walk over subsections instead of sections. */
6990 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
6994 /* Walk over all of the fragments in a subsection. */
6995 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6997 if (fragP
->fr_type
== rs_machine_dependent
6998 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7000 if (next_frag_is_branch_target (fragP
))
7001 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7010 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7013 xtensa_mark_narrow_branches (void)
7017 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7020 /* Walk over all of the fragments in a subsection. */
7021 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7023 if (fragP
->fr_type
== rs_machine_dependent
7024 && fragP
->fr_subtype
== RELAX_SLOTS
7025 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7029 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7030 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7032 if (vinsn
.num_slots
== 1
7033 && xtensa_opcode_is_branch (xtensa_default_isa
,
7034 vinsn
.slots
[0].opcode
)
7035 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7036 && is_narrow_branch_guaranteed_in_range (fragP
,
7039 fragP
->fr_subtype
= RELAX_SLOTS
;
7040 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7041 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7049 /* A branch is typically widened only when its target is out of
7050 range. However, we would like to widen them to align a subsequent
7051 branch target when possible.
7053 Because the branch relaxation code is so convoluted, the optimal solution
7054 (combining the two cases) is difficult to get right in all circumstances.
7055 We therefore go with an "almost as good" solution, where we only
7056 use for alignment narrow branches that definitely will not expand to a
7057 jump and a branch. These functions find and mark these cases. */
7059 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7060 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7061 We start counting beginning with the frag after the 2-byte branch, so the
7062 maximum offset is (4 - 2) + 63 = 65. */
7063 #define MAX_IMMED6 65
7065 static offsetT
unrelaxed_frag_max_size (fragS
*);
7068 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7070 const expressionS
*expr
= &tinsn
->tok
[1];
7071 symbolS
*symbolP
= expr
->X_add_symbol
;
7072 offsetT max_distance
= expr
->X_add_number
;
7075 if (expr
->X_op
!= O_symbol
)
7078 target_frag
= symbol_get_frag (symbolP
);
7080 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7081 if (is_branch_jmp_to_next (tinsn
, fragP
))
7084 /* The branch doesn't branch over it's own frag,
7085 but over the subsequent ones. */
7086 fragP
= fragP
->fr_next
;
7087 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7089 max_distance
+= unrelaxed_frag_max_size (fragP
);
7090 fragP
= fragP
->fr_next
;
7092 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7099 xtensa_mark_zcl_first_insns (void)
7103 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7106 /* Walk over all of the fragments in a subsection. */
7107 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7109 if (fragP
->fr_type
== rs_machine_dependent
7110 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7111 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7113 /* Find the loop frag. */
7114 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7115 /* Find the first insn frag. */
7116 targ_frag
= next_non_empty_frag (targ_frag
);
7118 /* Of course, sometimes (mostly for toy test cases) a
7119 zero-cost loop instruction is the last in a section. */
7121 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7122 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7130 /* Re-process all of the fragments looking to convert all of the
7131 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7132 conditional branch or a retw/retw.n, convert this frag to one that
7133 will generate a NOP. In any case close it off with a .fill 0. */
7135 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7138 xtensa_fix_a0_b_retw_frags (void)
7142 /* When this routine is called, all of the subsections are still intact
7143 so we walk over subsections instead of sections. */
7144 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7148 /* Walk over all of the fragments in a subsection. */
7149 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7151 if (fragP
->fr_type
== rs_machine_dependent
7152 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7154 if (next_instrs_are_b_retw (fragP
))
7156 if (fragP
->tc_frag_data
.is_no_transform
)
7157 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7159 relax_frag_add_nop (fragP
);
7169 next_instrs_are_b_retw (fragS
*fragP
)
7171 xtensa_opcode opcode
;
7173 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7174 static xtensa_insnbuf insnbuf
= NULL
;
7175 static xtensa_insnbuf slotbuf
= NULL
;
7176 xtensa_isa isa
= xtensa_default_isa
;
7179 bfd_boolean branch_seen
= FALSE
;
7183 insnbuf
= xtensa_insnbuf_alloc (isa
);
7184 slotbuf
= xtensa_insnbuf_alloc (isa
);
7187 if (next_fragP
== NULL
)
7190 /* Check for the conditional branch. */
7191 xtensa_insnbuf_from_chars
7192 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7193 fmt
= xtensa_format_decode (isa
, insnbuf
);
7194 if (fmt
== XTENSA_UNDEFINED
)
7197 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7199 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7200 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7202 branch_seen
= (branch_seen
7203 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7209 offset
+= xtensa_format_length (isa
, fmt
);
7210 if (offset
== next_fragP
->fr_fix
)
7212 next_fragP
= next_non_empty_frag (next_fragP
);
7216 if (next_fragP
== NULL
)
7219 /* Check for the retw/retw.n. */
7220 xtensa_insnbuf_from_chars
7221 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7222 fmt
= xtensa_format_decode (isa
, insnbuf
);
7224 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7225 have no problems. */
7226 if (fmt
== XTENSA_UNDEFINED
7227 || xtensa_format_num_slots (isa
, fmt
) != 1)
7230 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7231 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7233 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7240 /* Re-process all of the fragments looking to convert all of the
7241 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7242 loop end label, convert this frag to one that will generate a NOP.
7243 In any case close it off with a .fill 0. */
7245 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7248 xtensa_fix_b_j_loop_end_frags (void)
7252 /* When this routine is called, all of the subsections are still intact
7253 so we walk over subsections instead of sections. */
7254 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7258 /* Walk over all of the fragments in a subsection. */
7259 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7261 if (fragP
->fr_type
== rs_machine_dependent
7262 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7264 if (next_instr_is_loop_end (fragP
))
7266 if (fragP
->tc_frag_data
.is_no_transform
)
7267 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7269 relax_frag_add_nop (fragP
);
7279 next_instr_is_loop_end (fragS
*fragP
)
7281 const fragS
*next_fragP
;
7283 if (next_frag_is_loop_target (fragP
))
7286 next_fragP
= next_non_empty_frag (fragP
);
7287 if (next_fragP
== NULL
)
7290 if (!next_frag_is_loop_target (next_fragP
))
7293 /* If the size is >= 3 then there is more than one instruction here.
7294 The hardware bug will not fire. */
7295 if (next_fragP
->fr_fix
> 3)
7302 /* Re-process all of the fragments looking to convert all of the
7303 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7304 not MY loop's loop end within 12 bytes, add enough nops here to
7305 make it at least 12 bytes away. In any case close it off with a
7308 static offsetT min_bytes_to_other_loop_end
7309 (fragS
*, fragS
*, offsetT
, offsetT
);
7312 xtensa_fix_close_loop_end_frags (void)
7316 /* When this routine is called, all of the subsections are still intact
7317 so we walk over subsections instead of sections. */
7318 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7322 fragS
*current_target
= NULL
;
7323 offsetT current_offset
= 0;
7325 /* Walk over all of the fragments in a subsection. */
7326 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7328 if (fragP
->fr_type
== rs_machine_dependent
7329 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7330 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7331 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7334 /* Read it. If the instruction is a loop, get the target. */
7336 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7337 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7338 t_insn
.opcode
) == 1)
7340 /* Get the current fragment target. */
7341 if (fragP
->tc_frag_data
.slot_symbols
[0])
7343 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7344 current_target
= symbol_get_frag (sym
);
7345 current_offset
= fragP
->fr_offset
;
7351 && fragP
->fr_type
== rs_machine_dependent
7352 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7355 int bytes_added
= 0;
7357 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7358 /* Max out at 12. */
7359 min_bytes
= min_bytes_to_other_loop_end
7360 (fragP
->fr_next
, current_target
, current_offset
,
7361 REQUIRED_LOOP_DIVIDING_BYTES
);
7363 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7365 if (fragP
->tc_frag_data
.is_no_transform
)
7366 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7369 while (min_bytes
+ bytes_added
7370 < REQUIRED_LOOP_DIVIDING_BYTES
)
7374 if (fragP
->fr_var
< length
)
7375 as_fatal (_("fr_var %lu < length %d"),
7376 (long) fragP
->fr_var
, length
);
7379 assemble_nop (length
,
7380 fragP
->fr_literal
+ fragP
->fr_fix
);
7381 fragP
->fr_fix
+= length
;
7382 fragP
->fr_var
-= length
;
7384 bytes_added
+= length
;
7390 assert (fragP
->fr_type
!= rs_machine_dependent
7391 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7397 static offsetT
unrelaxed_frag_min_size (fragS
*);
7400 min_bytes_to_other_loop_end (fragS
*fragP
,
7401 fragS
*current_target
,
7402 offsetT current_offset
,
7406 fragS
*current_fragP
;
7408 for (current_fragP
= fragP
;
7410 current_fragP
= current_fragP
->fr_next
)
7412 if (current_fragP
->tc_frag_data
.is_loop_target
7413 && current_fragP
!= current_target
)
7414 return offset
+ current_offset
;
7416 offset
+= unrelaxed_frag_min_size (current_fragP
);
7418 if (offset
+ current_offset
>= max_size
)
7426 unrelaxed_frag_min_size (fragS
*fragP
)
7428 offsetT size
= fragP
->fr_fix
;
7430 /* Add fill size. */
7431 if (fragP
->fr_type
== rs_fill
)
7432 size
+= fragP
->fr_offset
;
7439 unrelaxed_frag_max_size (fragS
*fragP
)
7441 offsetT size
= fragP
->fr_fix
;
7442 switch (fragP
->fr_type
)
7445 /* Empty frags created by the obstack allocation scheme
7446 end up with type 0. */
7451 size
+= fragP
->fr_offset
;
7459 /* No further adjustments needed. */
7461 case rs_machine_dependent
:
7462 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7463 size
+= fragP
->fr_var
;
7466 /* We had darn well better know how big it is. */
7475 /* Re-process all of the fragments looking to convert all
7476 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7479 1) the instruction size count to the loop end label
7480 is too short (<= 2 instructions),
7481 2) loop has a jump or branch in it
7484 1) workaround_all_short_loops is TRUE
7485 2) The generating loop was a 'loopgtz' or 'loopnez'
7486 3) the instruction size count to the loop end label is too short
7488 then convert this frag (and maybe the next one) to generate a NOP.
7489 In any case close it off with a .fill 0. */
7491 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7492 static bfd_boolean
branch_before_loop_end (fragS
*);
7495 xtensa_fix_short_loop_frags (void)
7499 /* When this routine is called, all of the subsections are still intact
7500 so we walk over subsections instead of sections. */
7501 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7504 fragS
*current_target
= NULL
;
7505 offsetT current_offset
= 0;
7506 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7508 /* Walk over all of the fragments in a subsection. */
7509 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7511 /* Check on the current loop. */
7512 if (fragP
->fr_type
== rs_machine_dependent
7513 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7514 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7515 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7520 /* Read it. If the instruction is a loop, get the target. */
7521 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7522 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7523 t_insn
.opcode
) == 1)
7525 /* Get the current fragment target. */
7526 if (fragP
->tc_frag_data
.slot_symbols
[0])
7528 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7529 current_target
= symbol_get_frag (sym
);
7530 current_offset
= fragP
->fr_offset
;
7531 current_opcode
= t_insn
.opcode
;
7536 if (fragP
->fr_type
== rs_machine_dependent
7537 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7539 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7540 && (branch_before_loop_end (fragP
->fr_next
)
7541 || (workaround_all_short_loops
7542 && current_opcode
!= XTENSA_UNDEFINED
7543 && current_opcode
!= xtensa_loop_opcode
)))
7545 if (fragP
->tc_frag_data
.is_no_transform
)
7546 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7548 relax_frag_add_nop (fragP
);
7557 static int unrelaxed_frag_min_insn_count (fragS
*);
7560 count_insns_to_loop_end (fragS
*base_fragP
,
7561 bfd_boolean count_relax_add
,
7564 fragS
*fragP
= NULL
;
7569 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7571 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7572 if (insn_count
>= max_count
)
7575 if (count_relax_add
)
7577 if (fragP
->fr_type
== rs_machine_dependent
7578 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7580 /* In order to add the appropriate number of
7581 NOPs, we count an instruction for downstream
7584 if (insn_count
>= max_count
)
7594 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7596 xtensa_isa isa
= xtensa_default_isa
;
7597 static xtensa_insnbuf insnbuf
= NULL
;
7601 if (!fragP
->tc_frag_data
.is_insn
)
7605 insnbuf
= xtensa_insnbuf_alloc (isa
);
7607 /* Decode the fixed instructions. */
7608 while (offset
< fragP
->fr_fix
)
7612 xtensa_insnbuf_from_chars
7613 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7614 fmt
= xtensa_format_decode (isa
, insnbuf
);
7616 if (fmt
== XTENSA_UNDEFINED
)
7618 as_fatal (_("undecodable instruction in instruction frag"));
7621 offset
+= xtensa_format_length (isa
, fmt
);
7629 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7632 branch_before_loop_end (fragS
*base_fragP
)
7636 for (fragP
= base_fragP
;
7637 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7638 fragP
= fragP
->fr_next
)
7640 if (unrelaxed_frag_has_b_j (fragP
))
7648 unrelaxed_frag_has_b_j (fragS
*fragP
)
7650 static xtensa_insnbuf insnbuf
= NULL
;
7651 xtensa_isa isa
= xtensa_default_isa
;
7654 if (!fragP
->tc_frag_data
.is_insn
)
7658 insnbuf
= xtensa_insnbuf_alloc (isa
);
7660 /* Decode the fixed instructions. */
7661 while (offset
< fragP
->fr_fix
)
7666 xtensa_insnbuf_from_chars
7667 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7668 fmt
= xtensa_format_decode (isa
, insnbuf
);
7669 if (fmt
== XTENSA_UNDEFINED
)
7672 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7674 xtensa_opcode opcode
=
7675 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7676 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7677 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7680 offset
+= xtensa_format_length (isa
, fmt
);
7686 /* Checks to be made after initial assembly but before relaxation. */
7688 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7689 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7692 xtensa_sanity_check (void)
7699 as_where (&file_name
, &line
);
7700 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7704 /* Walk over all of the fragments in a subsection. */
7705 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7707 /* Currently we only check for empty loops here. */
7708 if (fragP
->fr_type
== rs_machine_dependent
7709 && fragP
->fr_subtype
== RELAX_IMMED
)
7711 static xtensa_insnbuf insnbuf
= NULL
;
7714 if (fragP
->fr_opcode
!= NULL
)
7717 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7718 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7719 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7721 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7722 t_insn
.opcode
) == 1)
7724 if (is_empty_loop (&t_insn
, fragP
))
7726 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7727 as_bad (_("invalid empty loop"));
7729 if (!is_local_forward_loop (&t_insn
, fragP
))
7731 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7732 as_bad (_("loop target does not follow "
7733 "loop instruction in section"));
7740 new_logical_line (file_name
, line
);
7744 #define LOOP_IMMED_OPN 1
7746 /* Return TRUE if the loop target is the next non-zero fragment. */
7749 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7751 const expressionS
*expr
;
7755 if (insn
->insn_type
!= ITYPE_INSN
)
7758 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7761 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7764 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7766 if (expr
->X_op
!= O_symbol
)
7769 symbolP
= expr
->X_add_symbol
;
7773 if (symbol_get_frag (symbolP
) == NULL
)
7776 if (S_GET_VALUE (symbolP
) != 0)
7779 /* Walk through the zero-size fragments from this one. If we find
7780 the target fragment, then this is a zero-size loop. */
7782 for (next_fragP
= fragP
->fr_next
;
7784 next_fragP
= next_fragP
->fr_next
)
7786 if (next_fragP
== symbol_get_frag (symbolP
))
7788 if (next_fragP
->fr_fix
!= 0)
7796 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7798 const expressionS
*expr
;
7802 if (insn
->insn_type
!= ITYPE_INSN
)
7805 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7808 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7811 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7813 if (expr
->X_op
!= O_symbol
)
7816 symbolP
= expr
->X_add_symbol
;
7820 if (symbol_get_frag (symbolP
) == NULL
)
7823 /* Walk through fragments until we find the target.
7824 If we do not find the target, then this is an invalid loop. */
7826 for (next_fragP
= fragP
->fr_next
;
7828 next_fragP
= next_fragP
->fr_next
)
7830 if (next_fragP
== symbol_get_frag (symbolP
))
7838 /* Alignment Functions. */
7841 get_text_align_power (unsigned target_size
)
7846 assert (target_size
<= INT_MAX
);
7847 while (target_size
> power
)
7857 get_text_align_max_fill_size (int align_pow
,
7858 bfd_boolean use_nops
,
7859 bfd_boolean use_no_density
)
7862 return (1 << align_pow
);
7864 return 3 * (1 << align_pow
);
7866 return 1 + (1 << align_pow
);
7870 /* Calculate the minimum bytes of fill needed at "address" to align a
7871 target instruction of size "target_size" so that it does not cross a
7872 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7873 the fill can be an arbitrary number of bytes. Otherwise, the space must
7874 be filled by NOP instructions. */
7877 get_text_align_fill_size (addressT address
,
7880 bfd_boolean use_nops
,
7881 bfd_boolean use_no_density
)
7883 addressT alignment
, fill
, fill_limit
, fill_step
;
7884 bfd_boolean skip_one
= FALSE
;
7886 alignment
= (1 << align_pow
);
7887 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7891 fill_limit
= alignment
;
7894 else if (!use_no_density
)
7896 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7897 fill_limit
= alignment
* 2;
7903 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7904 fill_limit
= alignment
* 3;
7908 /* Try all fill sizes until finding one that works. */
7909 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7911 if (skip_one
&& fill
== 1)
7913 if ((address
+ fill
) >> align_pow
7914 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7923 branch_align_power (segT sec
)
7925 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7926 is aligned to at least an 8-byte boundary, then a branch target need
7927 only fit within an 8-byte aligned block of memory to avoid a stall.
7928 Otherwise, try to fit branch targets within 4-byte aligned blocks
7929 (which may be insufficient, e.g., if the section has no alignment, but
7930 it's good enough). */
7931 if (xtensa_fetch_width
== 8)
7933 if (get_recorded_alignment (sec
) >= 3)
7937 assert (xtensa_fetch_width
== 4);
7943 /* This will assert if it is not possible. */
7946 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7952 assert (fill_size
% 3 == 0);
7953 return (fill_size
/ 3);
7956 assert (fill_size
!= 1); /* Bad argument. */
7958 while (fill_size
> 1)
7961 if (fill_size
== 2 || fill_size
== 4)
7963 fill_size
-= insn_size
;
7966 assert (fill_size
!= 1); /* Bad algorithm. */
7972 get_text_align_nth_nop_size (offsetT fill_size
,
7974 bfd_boolean use_no_density
)
7981 assert (fill_size
!= 1); /* Bad argument. */
7983 while (fill_size
> 1)
7986 if (fill_size
== 2 || fill_size
== 4)
7988 fill_size
-= insn_size
;
7998 /* For the given fragment, find the appropriate address
7999 for it to begin at if we are using NOPs to align it. */
8002 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8004 /* The rule is: get next fragment's FIRST instruction. Find
8005 the smallest number of bytes that need to be added to
8006 ensure that the next fragment's FIRST instruction will fit
8009 E.G., 2 bytes : 0, 1, 2 mod 4
8012 If the FIRST instruction MIGHT be relaxed,
8013 assume that it will become a 3-byte instruction.
8015 Note again here that LOOP instructions are not bundleable,
8016 and this relaxation only applies to LOOP opcodes. */
8019 int first_insn_size
;
8021 addressT pre_opcode_bytes
;
8024 xtensa_opcode opcode
;
8025 bfd_boolean is_loop
;
8027 assert (fragP
->fr_type
== rs_machine_dependent
);
8028 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8030 /* Find the loop frag. */
8031 first_insn
= next_non_empty_frag (fragP
);
8032 /* Now find the first insn frag. */
8033 first_insn
= next_non_empty_frag (first_insn
);
8035 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8037 loop_insn_size
= xg_get_single_size (opcode
);
8039 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8040 pre_opcode_bytes
+= loop_insn_size
;
8042 /* For loops, the alignment depends on the size of the
8043 instruction following the loop, not the LOOP instruction. */
8045 if (first_insn
== NULL
)
8048 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8050 first_insn_size
= frag_format_size (first_insn
);
8052 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8053 first_insn_size
= 3; /* ISA specifies this */
8055 /* If it was 8, then we'll need a larger alignment for the section. */
8056 align_power
= get_text_align_power (first_insn_size
);
8057 record_alignment (now_seg
, align_power
);
8059 fill_size
= get_text_align_fill_size
8060 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8061 fragP
->tc_frag_data
.is_no_density
);
8063 return address
+ fill_size
;
8067 /* 3 mechanisms for relaxing an alignment:
8069 Align to a power of 2.
8070 Align so the next fragment's instruction does not cross a word boundary.
8071 Align the current instruction so that if the next instruction
8072 were 3 bytes, it would not cross a word boundary.
8076 zeros - This is easy; always insert zeros.
8077 nops - 3-byte and 2-byte instructions
8081 >=5 : 3-byte instruction + fn (n-3)
8082 widening - widen previous instructions. */
8085 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8087 addressT target_address
, loop_insn_offset
;
8089 xtensa_opcode loop_opcode
;
8090 bfd_boolean is_loop
;
8093 offsetT branch_align
;
8095 assert (fragP
->fr_type
== rs_machine_dependent
);
8096 switch (fragP
->fr_subtype
)
8098 case RELAX_DESIRE_ALIGN
:
8099 target_size
= next_frag_format_size (fragP
);
8100 if (target_size
== XTENSA_UNDEFINED
)
8102 align_power
= branch_align_power (now_seg
);
8103 branch_align
= 1 << align_power
;
8104 /* Don't count on the section alignment being as large as the target. */
8105 if (target_size
> branch_align
)
8106 target_size
= branch_align
;
8107 opt_diff
= get_text_align_fill_size (address
, align_power
,
8108 target_size
, FALSE
, FALSE
);
8110 *max_diff
= (opt_diff
+ branch_align
8111 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8112 assert (*max_diff
>= opt_diff
);
8115 case RELAX_ALIGN_NEXT_OPCODE
:
8116 target_size
= next_frag_format_size (fragP
);
8117 loop_insn_offset
= 0;
8118 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8121 /* If the loop has been expanded then the LOOP instruction
8122 could be at an offset from this fragment. */
8123 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8125 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8127 if (target_size
== 2)
8128 target_size
= 3; /* ISA specifies this */
8130 /* In an ideal world, which is what we are shooting for here,
8131 we wouldn't need to use any NOPs immediately prior to the
8132 LOOP instruction. If this approach fails, relax_frag_loop_align
8133 will call get_noop_aligned_address. */
8135 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8136 align_power
= get_text_align_power (target_size
),
8137 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8138 target_size
, FALSE
, FALSE
);
8140 *max_diff
= xtensa_fetch_width
8141 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8142 - target_size
+ opt_diff
;
8143 assert (*max_diff
>= opt_diff
);
8154 /* md_relax_frag Hook and Helper Functions. */
8156 static long relax_frag_loop_align (fragS
*, long);
8157 static long relax_frag_for_align (fragS
*, long);
8158 static long relax_frag_immed
8159 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8162 /* Return the number of bytes added to this fragment, given that the
8163 input has been stretched already by "stretch". */
8166 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8168 xtensa_isa isa
= xtensa_default_isa
;
8169 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8170 long new_stretch
= 0;
8174 static xtensa_insnbuf vbuf
= NULL
;
8175 int slot
, num_slots
;
8178 as_where (&file_name
, &line
);
8179 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8181 fragP
->tc_frag_data
.unreported_expansion
= 0;
8183 switch (fragP
->fr_subtype
)
8185 case RELAX_ALIGN_NEXT_OPCODE
:
8186 /* Always convert. */
8187 if (fragP
->tc_frag_data
.relax_seen
)
8188 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8191 case RELAX_LOOP_END
:
8195 case RELAX_LOOP_END_ADD_NOP
:
8196 /* Add a NOP and switch to .fill 0. */
8197 new_stretch
= relax_frag_add_nop (fragP
);
8201 case RELAX_DESIRE_ALIGN
:
8202 /* Do nothing. The narrowing before this frag will either align
8207 case RELAX_LITERAL_FINAL
:
8210 case RELAX_LITERAL_NR
:
8212 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8213 assert (unreported
== lit_size
);
8214 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8215 fragP
->fr_var
-= lit_size
;
8216 fragP
->fr_fix
+= lit_size
;
8222 vbuf
= xtensa_insnbuf_alloc (isa
);
8224 xtensa_insnbuf_from_chars
8225 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8226 fmt
= xtensa_format_decode (isa
, vbuf
);
8227 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8229 for (slot
= 0; slot
< num_slots
; slot
++)
8231 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8234 if (fragP
->tc_frag_data
.relax_seen
)
8235 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8239 case RELAX_IMMED_STEP1
:
8240 case RELAX_IMMED_STEP2
:
8241 /* Place the immediate. */
8242 new_stretch
+= relax_frag_immed
8243 (now_seg
, fragP
, stretch
,
8244 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8245 fmt
, slot
, stretched_p
, FALSE
);
8249 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8255 case RELAX_LITERAL_POOL_BEGIN
:
8256 case RELAX_LITERAL_POOL_END
:
8257 case RELAX_MAYBE_UNREACHABLE
:
8258 case RELAX_MAYBE_DESIRE_ALIGN
:
8259 /* No relaxation required. */
8262 case RELAX_FILL_NOP
:
8263 case RELAX_UNREACHABLE
:
8264 if (fragP
->tc_frag_data
.relax_seen
)
8265 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8269 as_bad (_("bad relaxation state"));
8272 /* Tell gas we need another relaxation pass. */
8273 if (! fragP
->tc_frag_data
.relax_seen
)
8275 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8279 new_logical_line (file_name
, line
);
8285 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8287 addressT old_address
, old_next_address
, old_size
;
8288 addressT new_address
, new_next_address
, new_size
;
8291 /* All the frags with relax_frag_for_alignment prior to this one in the
8292 section have been done, hopefully eliminating the need for a NOP here.
8293 But, this will put it in if necessary. */
8295 /* Calculate the old address of this fragment and the next fragment. */
8296 old_address
= fragP
->fr_address
- stretch
;
8297 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8298 fragP
->tc_frag_data
.text_expansion
[0]);
8299 old_size
= old_next_address
- old_address
;
8301 /* Calculate the new address of this fragment and the next fragment. */
8302 new_address
= fragP
->fr_address
;
8304 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8305 new_size
= new_next_address
- new_address
;
8307 growth
= new_size
- old_size
;
8309 /* Fix up the text_expansion field and return the new growth. */
8310 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8315 /* Add a NOP instruction. */
8318 relax_frag_add_nop (fragS
*fragP
)
8320 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8321 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8322 assemble_nop (length
, nop_buf
);
8323 fragP
->tc_frag_data
.is_insn
= TRUE
;
8325 if (fragP
->fr_var
< length
)
8327 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8331 fragP
->fr_fix
+= length
;
8332 fragP
->fr_var
-= length
;
8337 static long future_alignment_required (fragS
*, long);
8340 relax_frag_for_align (fragS
*fragP
, long stretch
)
8342 /* Overview of the relaxation procedure for alignment:
8343 We can widen with NOPs or by widening instructions or by filling
8344 bytes after jump instructions. Find the opportune places and widen
8345 them if necessary. */
8350 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8351 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8352 || (fragP
->fr_subtype
== RELAX_SLOTS
8353 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8355 stretch_me
= future_alignment_required (fragP
, stretch
);
8356 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8362 /* We expanded on a previous pass. Can we shrink now? */
8363 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8364 if (shrink
<= stretch
&& stretch
> 0)
8366 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8372 /* Below here, diff > 0. */
8373 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8379 /* Return the address of the next frag that should be aligned.
8381 By "address" we mean the address it _would_ be at if there
8382 is no action taken to align it between here and the target frag.
8383 In other words, if no narrows and no fill nops are used between
8384 here and the frag to align, _even_if_ some of the frags we use
8385 to align targets have already expanded on a previous relaxation
8388 Also, count each frag that may be used to help align the target.
8390 Return 0 if there are no frags left in the chain that need to be
8394 find_address_of_next_align_frag (fragS
**fragPP
,
8398 bfd_boolean
*paddable
)
8400 fragS
*fragP
= *fragPP
;
8401 addressT address
= fragP
->fr_address
;
8403 /* Do not reset the counts to 0. */
8407 /* Limit this to a small search. */
8408 if (*widens
>= (int) xtensa_fetch_width
)
8413 address
+= fragP
->fr_fix
;
8415 if (fragP
->fr_type
== rs_fill
)
8416 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8417 else if (fragP
->fr_type
== rs_machine_dependent
)
8419 switch (fragP
->fr_subtype
)
8421 case RELAX_UNREACHABLE
:
8425 case RELAX_FILL_NOP
:
8427 if (!fragP
->tc_frag_data
.is_no_density
)
8432 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8437 address
+= total_frag_text_expansion (fragP
);;
8441 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8444 case RELAX_ALIGN_NEXT_OPCODE
:
8445 case RELAX_DESIRE_ALIGN
:
8449 case RELAX_MAYBE_UNREACHABLE
:
8450 case RELAX_MAYBE_DESIRE_ALIGN
:
8455 /* Just punt if we don't know the type. */
8462 /* Just punt if we don't know the type. */
8466 fragP
= fragP
->fr_next
;
8474 static long bytes_to_stretch (fragS
*, int, int, int, int);
8477 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8479 fragS
*this_frag
= fragP
;
8483 int narrow_nops
= 0;
8484 bfd_boolean paddable
= FALSE
;
8485 offsetT local_opt_diff
;
8488 int stretch_amount
= 0;
8489 int local_stretch_amount
;
8490 int global_stretch_amount
;
8492 address
= find_address_of_next_align_frag
8493 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8497 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8498 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8500 frag_wane (this_frag
);
8504 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8505 opt_diff
= local_opt_diff
;
8506 assert (opt_diff
>= 0);
8507 assert (max_diff
>= opt_diff
);
8512 fragP
= fragP
->fr_next
;
8514 while (fragP
&& opt_diff
< max_diff
&& address
)
8516 /* We only use these to determine if we can exit early
8517 because there will be plenty of ways to align future
8519 int glob_widens
= 0;
8522 bfd_boolean glob_pad
= 0;
8523 address
= find_address_of_next_align_frag
8524 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8525 /* If there is a padable portion, then skip. */
8526 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8531 offsetT next_m_diff
;
8532 offsetT next_o_diff
;
8534 /* Downrange frags haven't had stretch added to them yet. */
8537 /* The address also includes any text expansion from this
8538 frag in a previous pass, but we don't want that. */
8539 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8541 /* Assume we are going to move at least opt_diff. In
8542 reality, we might not be able to, but assuming that
8543 we will helps catch cases where moving opt_diff pushes
8544 the next target from aligned to unaligned. */
8545 address
+= opt_diff
;
8547 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8549 /* Now cleanup for the adjustments to address. */
8550 next_o_diff
+= opt_diff
;
8551 next_m_diff
+= opt_diff
;
8552 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8553 opt_diff
= next_o_diff
;
8554 if (next_m_diff
< max_diff
)
8555 max_diff
= next_m_diff
;
8556 fragP
= fragP
->fr_next
;
8560 /* If there are enough wideners in between, do it. */
8563 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8565 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8570 local_stretch_amount
8571 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8572 num_widens
, local_opt_diff
);
8573 global_stretch_amount
8574 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8575 num_widens
, opt_diff
);
8576 /* If the condition below is true, then the frag couldn't
8577 stretch the correct amount for the global case, so we just
8578 optimize locally. We'll rely on the subsequent frags to get
8579 the correct alignment in the global case. */
8580 if (global_stretch_amount
< local_stretch_amount
)
8581 stretch_amount
= local_stretch_amount
;
8583 stretch_amount
= global_stretch_amount
;
8585 if (this_frag
->fr_subtype
== RELAX_SLOTS
8586 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8587 assert (stretch_amount
<= 1);
8588 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8590 if (this_frag
->tc_frag_data
.is_no_density
)
8591 assert (stretch_amount
== 3 || stretch_amount
== 0);
8593 assert (stretch_amount
<= 3);
8596 return stretch_amount
;
8600 /* The idea: widen everything you can to get a target or loop aligned,
8601 then start using NOPs.
8603 When we must have a NOP, here is a table of how we decide
8604 (so you don't have to fight through the control flow below):
8606 wide_nops = the number of wide NOPs available for aligning
8607 narrow_nops = the number of narrow NOPs available for aligning
8608 (a subset of wide_nops)
8609 widens = the number of narrow instructions that should be widened
8616 b 0 1 1 (case 3a makes this case unnecessary)
8619 c 0 1 2 (case 4a makes this case unnecessary)
8622 c 0 2 1 (case 5b makes this case unnecessary)
8625 c 0 1 4 (case 6b makes this case unneccesary)
8626 d 1 1 1 (case 6a makes this case unnecessary)
8627 e 0 2 2 (case 6a makes this case unnecessary)
8628 f 0 3 0 (case 6a makes this case unnecessary)
8631 c 1 1 2 (case 7b makes this case unnecessary)
8632 d 0 1 5 (case 7a makes this case unnecessary)
8633 e 0 2 3 (case 7b makes this case unnecessary)
8634 f 0 3 1 (case 7b makes this case unnecessary)
8635 g 1 2 1 (case 7b makes this case unnecessary)
8639 bytes_to_stretch (fragS
*this_frag
,
8645 int bytes_short
= desired_diff
- num_widens
;
8647 assert (desired_diff
>= 0 && desired_diff
< 8);
8648 if (desired_diff
== 0)
8651 assert (wide_nops
> 0 || num_widens
> 0);
8653 /* Always prefer widening to NOP-filling. */
8654 if (bytes_short
< 0)
8656 /* There are enough RELAX_NARROW frags after this one
8657 to align the target without widening this frag in any way. */
8661 if (bytes_short
== 0)
8663 /* Widen every narrow between here and the align target
8664 and the align target will be properly aligned. */
8665 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8671 /* From here we will need at least one NOP to get an alignment.
8672 However, we may not be able to align at all, in which case,
8674 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8676 switch (desired_diff
)
8681 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8682 return 2; /* case 2 */
8688 return 3; /* case 3a */
8690 if (num_widens
>= 1 && wide_nops
== 1)
8691 return 3; /* case 4a */
8692 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8693 return 2; /* case 4b */
8696 if (num_widens
>= 2 && wide_nops
== 1)
8697 return 3; /* case 5a */
8698 /* We will need two nops. Are there enough nops
8699 between here and the align target? */
8700 if (wide_nops
< 2 || narrow_nops
== 0)
8702 /* Are there other nops closer that can serve instead? */
8703 if (wide_nops
> 2 && narrow_nops
> 1)
8705 /* Take the density one first, because there might not be
8706 another density one available. */
8707 if (!this_frag
->tc_frag_data
.is_no_density
)
8708 return 2; /* case 5b narrow */
8710 return 3; /* case 5b wide */
8714 return 3; /* case 6a */
8715 else if (num_widens
>= 3 && wide_nops
== 1)
8716 return 3; /* case 6b */
8719 if (wide_nops
== 1 && num_widens
>= 4)
8720 return 3; /* case 7a */
8721 else if (wide_nops
== 2 && num_widens
>= 1)
8722 return 3; /* case 7b */
8730 /* We will need a NOP no matter what, but should we widen
8731 this instruction to help?
8733 This is a RELAX_FRAG_NARROW frag. */
8734 switch (desired_diff
)
8743 if (wide_nops
>= 1 && num_widens
== 1)
8744 return 1; /* case 4a */
8747 if (wide_nops
>= 1 && num_widens
== 2)
8748 return 1; /* case 5a */
8752 return 0; /* case 6a */
8753 else if (wide_nops
>= 1 && num_widens
== 3)
8754 return 1; /* case 6b */
8757 if (wide_nops
>= 1 && num_widens
== 4)
8758 return 1; /* case 7a */
8759 else if (wide_nops
>= 2 && num_widens
== 1)
8760 return 1; /* case 7b */
8773 relax_frag_immed (segT segP
,
8780 bfd_boolean estimate_only
)
8784 bfd_boolean negatable_branch
= FALSE
;
8785 bfd_boolean branch_jmp_to_next
= FALSE
;
8786 bfd_boolean wide_insn
= FALSE
;
8787 xtensa_isa isa
= xtensa_default_isa
;
8789 offsetT frag_offset
;
8792 int num_text_bytes
, num_literal_bytes
;
8793 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8795 assert (fragP
->fr_opcode
!= NULL
);
8797 xg_clear_vinsn (&cur_vinsn
);
8798 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8799 if (cur_vinsn
.num_slots
> 1)
8802 tinsn
= cur_vinsn
.slots
[slot
];
8803 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8805 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8808 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8809 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8811 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8813 old_size
= xtensa_format_length (isa
, fmt
);
8815 /* Special case: replace a branch to the next instruction with a NOP.
8816 This is required to work around a hardware bug in T1040.0 and also
8817 serves as an optimization. */
8819 if (branch_jmp_to_next
8820 && ((old_size
== 2) || (old_size
== 3))
8821 && !next_frag_is_loop_target (fragP
))
8824 /* Here is the fun stuff: Get the immediate field from this
8825 instruction. If it fits, we are done. If not, find the next
8826 instruction sequence that fits. */
8828 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8829 istack_init (&istack
);
8830 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8831 min_steps
, stretch
);
8832 if (num_steps
< min_steps
)
8834 as_fatal (_("internal error: relaxation failed"));
8838 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8840 as_fatal (_("internal error: relaxation requires too many steps"));
8844 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8846 /* Figure out the number of bytes needed. */
8848 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8850 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8852 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8854 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8857 num_text_bytes
+= old_size
;
8858 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8859 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8861 total_text_diff
= num_text_bytes
- old_size
;
8862 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8864 /* It MUST get larger. If not, we could get an infinite loop. */
8865 assert (num_text_bytes
>= 0);
8866 assert (literal_diff
>= 0);
8867 assert (total_text_diff
>= 0);
8869 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8870 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8871 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8872 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8874 /* Find the associated expandable literal for this. */
8875 if (literal_diff
!= 0)
8877 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8880 assert (literal_diff
== 4);
8881 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8883 /* We expect that the literal section state has NOT been
8885 assert (lit_fragP
->fr_type
== rs_machine_dependent
8886 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8887 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8889 /* We need to mark this section for another iteration
8895 if (negatable_branch
&& istack
.ninsn
> 1)
8896 update_next_frag_state (fragP
);
8898 return this_text_diff
;
8902 /* md_convert_frag Hook and Helper Functions. */
8904 static void convert_frag_align_next_opcode (fragS
*);
8905 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8906 static void convert_frag_fill_nop (fragS
*);
8907 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8910 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8912 static xtensa_insnbuf vbuf
= NULL
;
8913 xtensa_isa isa
= xtensa_default_isa
;
8920 as_where (&file_name
, &line
);
8921 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8923 switch (fragp
->fr_subtype
)
8925 case RELAX_ALIGN_NEXT_OPCODE
:
8926 /* Always convert. */
8927 convert_frag_align_next_opcode (fragp
);
8930 case RELAX_DESIRE_ALIGN
:
8931 /* Do nothing. If not aligned already, too bad. */
8935 case RELAX_LITERAL_FINAL
:
8940 vbuf
= xtensa_insnbuf_alloc (isa
);
8942 xtensa_insnbuf_from_chars
8943 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8944 fmt
= xtensa_format_decode (isa
, vbuf
);
8945 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8947 for (slot
= 0; slot
< num_slots
; slot
++)
8949 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8952 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8956 case RELAX_IMMED_STEP1
:
8957 case RELAX_IMMED_STEP2
:
8958 /* Place the immediate. */
8961 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8966 /* This is OK because some slots could have
8967 relaxations and others have none. */
8973 case RELAX_UNREACHABLE
:
8974 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
8975 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
8976 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
8980 case RELAX_MAYBE_UNREACHABLE
:
8981 case RELAX_MAYBE_DESIRE_ALIGN
:
8985 case RELAX_FILL_NOP
:
8986 convert_frag_fill_nop (fragp
);
8989 case RELAX_LITERAL_NR
:
8990 if (use_literal_section
)
8992 /* This should have been handled during relaxation. When
8993 relaxing a code segment, literals sometimes need to be
8994 added to the corresponding literal segment. If that
8995 literal segment has already been relaxed, then we end up
8996 in this situation. Marking the literal segments as data
8997 would make this happen less often (since GAS always relaxes
8998 code before data), but we could still get into trouble if
8999 there are instructions in a segment that is not marked as
9000 containing code. Until we can implement a better solution,
9001 cheat and adjust the addresses of all the following frags.
9002 This could break subsequent alignments, but the linker's
9003 literal coalescing will do that anyway. */
9006 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9007 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9008 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9011 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9015 as_bad (_("invalid relaxation fragment result"));
9020 new_logical_line (file_name
, line
);
9025 convert_frag_align_next_opcode (fragS
*fragp
)
9027 char *nop_buf
; /* Location for Writing. */
9028 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9029 addressT aligned_address
;
9033 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9035 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9036 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9037 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9039 for (nop
= 0; nop
< nop_count
; nop
++)
9042 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9044 assemble_nop (nop_size
, nop_buf
);
9045 nop_buf
+= nop_size
;
9048 fragp
->fr_fix
+= fill_size
;
9049 fragp
->fr_var
-= fill_size
;
9054 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9056 TInsn tinsn
, single_target
;
9057 int size
, old_size
, diff
;
9058 offsetT frag_offset
;
9061 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9063 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9065 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9066 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9067 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9072 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9074 /* No conversion. */
9079 assert (fragP
->fr_opcode
!= NULL
);
9081 /* Frags in this relaxation state should only contain
9082 single instruction bundles. */
9083 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9085 /* Just convert it to a wide form.... */
9087 old_size
= xg_get_single_size (tinsn
.opcode
);
9089 tinsn_init (&single_target
);
9090 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9092 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9094 as_bad (_("unable to widen instruction"));
9098 size
= xg_get_single_size (single_target
.opcode
);
9099 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9102 diff
= size
- old_size
;
9104 assert (diff
<= fragP
->fr_var
);
9105 fragP
->fr_var
-= diff
;
9106 fragP
->fr_fix
+= diff
;
9114 convert_frag_fill_nop (fragS
*fragP
)
9116 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9117 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9118 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9119 - fragP
->fr_address
- fragP
->fr_fix
));
9122 /* No conversion. */
9126 assemble_nop (size
, loc
);
9127 fragP
->tc_frag_data
.is_insn
= TRUE
;
9128 fragP
->fr_var
-= size
;
9129 fragP
->fr_fix
+= size
;
9134 static fixS
*fix_new_exp_in_seg
9135 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9136 bfd_reloc_code_real_type
);
9137 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9140 convert_frag_immed (segT segP
,
9146 char *immed_instr
= fragP
->fr_opcode
;
9148 bfd_boolean expanded
= FALSE
;
9149 bfd_boolean branch_jmp_to_next
= FALSE
;
9150 char *fr_opcode
= fragP
->fr_opcode
;
9151 xtensa_isa isa
= xtensa_default_isa
;
9152 bfd_boolean wide_insn
= FALSE
;
9154 bfd_boolean is_loop
;
9156 assert (fr_opcode
!= NULL
);
9158 xg_clear_vinsn (&cur_vinsn
);
9160 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9161 if (cur_vinsn
.num_slots
> 1)
9164 orig_tinsn
= cur_vinsn
.slots
[slot
];
9165 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9167 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9169 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9170 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9172 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9174 /* Conversion just inserts a NOP and marks the fix as completed. */
9175 bytes
= xtensa_format_length (isa
, fmt
);
9178 cur_vinsn
.slots
[slot
].opcode
=
9179 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9180 cur_vinsn
.slots
[slot
].ntok
= 0;
9184 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9185 assert (bytes
== 2 || bytes
== 3);
9186 build_nop (&cur_vinsn
.slots
[0], bytes
);
9187 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9189 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9190 xtensa_insnbuf_to_chars
9191 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9196 /* Here is the fun stuff: Get the immediate field from this
9197 instruction. If it fits, we're done. If not, find the next
9198 instruction sequence that fits. */
9202 symbolS
*lit_sym
= NULL
;
9204 int target_offset
= 0;
9207 symbolS
*gen_label
= NULL
;
9208 offsetT frag_offset
;
9209 bfd_boolean first
= TRUE
;
9210 bfd_boolean last_is_jump
;
9212 /* It does not fit. Find something that does and
9213 convert immediately. */
9214 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9215 istack_init (&istack
);
9216 xg_assembly_relax (&istack
, &orig_tinsn
,
9217 segP
, fragP
, frag_offset
, min_steps
, 0);
9219 old_size
= xtensa_format_length (isa
, fmt
);
9221 /* Assemble this right inline. */
9223 /* First, create the mapping from a label name to the REAL label. */
9225 for (i
= 0; i
< istack
.ninsn
; i
++)
9227 TInsn
*tinsn
= &istack
.insn
[i
];
9230 switch (tinsn
->insn_type
)
9233 if (lit_sym
!= NULL
)
9234 as_bad (_("multiple literals in expansion"));
9235 /* First find the appropriate space in the literal pool. */
9236 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9237 if (lit_frag
== NULL
)
9238 as_bad (_("no registered fragment for literal"));
9239 if (tinsn
->ntok
!= 1)
9240 as_bad (_("number of literal tokens != 1"));
9242 /* Set the literal symbol and add a fixup. */
9243 lit_sym
= lit_frag
->fr_symbol
;
9247 if (align_targets
&& !is_loop
)
9249 fragS
*unreach
= fragP
->fr_next
;
9250 while (!(unreach
->fr_type
== rs_machine_dependent
9251 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9252 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9254 unreach
= unreach
->fr_next
;
9257 assert (unreach
->fr_type
== rs_machine_dependent
9258 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9259 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9261 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9263 assert (gen_label
== NULL
);
9264 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9265 fr_opcode
- fragP
->fr_literal
9266 + target_offset
, fragP
);
9270 if (first
&& wide_insn
)
9272 target_offset
+= xtensa_format_length (isa
, fmt
);
9274 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9275 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9278 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9285 last_is_jump
= FALSE
;
9286 for (i
= 0; i
< istack
.ninsn
; i
++)
9288 TInsn
*tinsn
= &istack
.insn
[i
];
9292 bfd_reloc_code_real_type reloc_type
;
9294 switch (tinsn
->insn_type
)
9297 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9298 /* Already checked. */
9299 assert (lit_frag
!= NULL
);
9300 assert (lit_sym
!= NULL
);
9301 assert (tinsn
->ntok
== 1);
9303 target_seg
= S_GET_SEGMENT (lit_sym
);
9304 assert (target_seg
);
9305 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9306 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9308 reloc_type
= BFD_RELOC_32
;
9309 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9310 &tinsn
->tok
[0], FALSE
, reloc_type
);
9317 xg_resolve_labels (tinsn
, gen_label
);
9318 xg_resolve_literals (tinsn
, lit_sym
);
9319 if (wide_insn
&& first
)
9322 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9324 cur_vinsn
.slots
[slot
] = *tinsn
;
9328 cur_vinsn
.slots
[slot
].opcode
=
9329 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9330 cur_vinsn
.slots
[slot
].ntok
= 0;
9332 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9333 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9334 (unsigned char *) immed_instr
, 0);
9335 fragP
->tc_frag_data
.is_insn
= TRUE
;
9336 size
= xtensa_format_length (isa
, fmt
);
9337 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9340 (tinsn
, immed_instr
+ size
, fragP
,
9341 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9342 size
+= xg_get_single_size (tinsn
->opcode
);
9347 size
= xg_get_single_size (tinsn
->opcode
);
9348 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9349 immed_instr
- fragP
->fr_literal
, TRUE
);
9351 immed_instr
+= size
;
9357 diff
= total_size
- old_size
;
9361 assert (diff
<= fragP
->fr_var
);
9362 fragP
->fr_var
-= diff
;
9363 fragP
->fr_fix
+= diff
;
9366 /* Check for undefined immediates in LOOP instructions. */
9370 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9371 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9373 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9376 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9377 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9379 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9384 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9385 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9387 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9389 /* Add an expansion note on the expanded instruction. */
9390 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9391 &orig_tinsn
.tok
[0], TRUE
,
9392 BFD_RELOC_XTENSA_ASM_EXPAND
);
9397 /* Add a new fix expression into the desired segment. We have to
9398 switch to that segment to do this. */
9401 fix_new_exp_in_seg (segT new_seg
,
9408 bfd_reloc_code_real_type r_type
)
9412 subsegT subseg
= now_subseg
;
9414 assert (new_seg
!= 0);
9415 subseg_set (new_seg
, new_subseg
);
9417 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9418 subseg_set (seg
, subseg
);
9423 /* Relax a loop instruction so that it can span loop >256 bytes.
9429 addi as, as, lo8 (label-.L1)
9430 addmi as, as, mid8 (label-.L1)
9441 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9446 unsigned long target
;
9447 static xtensa_insnbuf insnbuf
= NULL
;
9448 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9449 xtensa_isa isa
= xtensa_default_isa
;
9450 addressT loop_offset
;
9451 addressT addi_offset
= 9;
9452 addressT addmi_offset
= 12;
9457 insnbuf
= xtensa_insnbuf_alloc (isa
);
9459 /* Get the loop offset. */
9460 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9462 /* Validate that there really is a LOOP at the loop_offset. Because
9463 loops are not bundleable, we can assume that the instruction will be
9465 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9466 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9468 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9469 addi_offset
+= loop_offset
;
9470 addmi_offset
+= loop_offset
;
9472 assert (tinsn
->ntok
== 2);
9473 if (tinsn
->tok
[1].X_op
== O_constant
)
9474 target
= tinsn
->tok
[1].X_add_number
;
9475 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9477 /* Find the fragment. */
9478 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9479 assert (S_GET_SEGMENT (sym
) == segP
9480 || S_GET_SEGMENT (sym
) == absolute_section
);
9481 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9485 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9490 know (symbolP
->sy_frag
);
9491 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9492 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9494 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9495 loop_length_hi
= loop_length
& ~0x0ff;
9496 loop_length_lo
= loop_length
& 0x0ff;
9497 if (loop_length_lo
>= 128)
9499 loop_length_lo
-= 256;
9500 loop_length_hi
+= 256;
9503 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9504 32512. If the loop is larger than that, then we just fail. */
9505 if (loop_length_hi
> 32512)
9506 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9507 _("loop too long for LOOP instruction"));
9509 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9510 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9512 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9513 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9515 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9516 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9518 fragP
->tc_frag_data
.is_insn
= TRUE
;
9519 xtensa_insnbuf_to_chars
9520 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9522 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9523 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9524 xtensa_insnbuf_to_chars
9525 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9527 /* Walk through all of the frags from here to the loop end
9528 and mark them as no_transform to keep them from being modified
9529 by the linker. If we ever have a relocation for the
9530 addi/addmi of the difference of two symbols we can remove this. */
9533 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9534 next_fragP
= next_fragP
->fr_next
)
9536 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9537 if (next_fragP
->tc_frag_data
.is_loop_target
)
9539 if (target_count
== 2)
9545 /* A map that keeps information on a per-subsegment basis. This is
9546 maintained during initial assembly, but is invalid once the
9547 subsegments are smashed together. I.E., it cannot be used during
9550 typedef struct subseg_map_struct
9558 float total_freq
; /* fall-through + branch target frequency */
9559 float target_freq
; /* branch target frequency alone */
9561 struct subseg_map_struct
*next
;
9565 static subseg_map
*sseg_map
= NULL
;
9568 get_subseg_info (segT seg
, subsegT subseg
)
9570 subseg_map
*subseg_e
;
9572 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9574 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9582 add_subseg_info (segT seg
, subsegT subseg
)
9584 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9585 memset (subseg_e
, 0, sizeof (subseg_map
));
9586 subseg_e
->seg
= seg
;
9587 subseg_e
->subseg
= subseg
;
9588 subseg_e
->flags
= 0;
9589 /* Start off considering every branch target very important. */
9590 subseg_e
->target_freq
= 1.0;
9591 subseg_e
->total_freq
= 1.0;
9592 subseg_e
->next
= sseg_map
;
9593 sseg_map
= subseg_e
;
9599 get_last_insn_flags (segT seg
, subsegT subseg
)
9601 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9603 return subseg_e
->flags
;
9609 set_last_insn_flags (segT seg
,
9614 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9616 subseg_e
= add_subseg_info (seg
, subseg
);
9618 subseg_e
->flags
|= fl
;
9620 subseg_e
->flags
&= ~fl
;
9625 get_subseg_total_freq (segT seg
, subsegT subseg
)
9627 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9629 return subseg_e
->total_freq
;
9635 get_subseg_target_freq (segT seg
, subsegT subseg
)
9637 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9639 return subseg_e
->target_freq
;
9645 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9647 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9649 subseg_e
= add_subseg_info (seg
, subseg
);
9650 subseg_e
->total_freq
= total_f
;
9651 subseg_e
->target_freq
= target_f
;
9655 /* Segment Lists and emit_state Stuff. */
9658 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9663 segT literal_section
= head
->seg
;
9665 /* Move the literal section to the front of the section list. */
9666 assert (literal_section
);
9667 if (literal_section
!= stdoutput
->sections
)
9669 bfd_section_list_remove (stdoutput
, literal_section
);
9670 bfd_section_list_prepend (stdoutput
, literal_section
);
9677 static void mark_literal_frags (seg_list
*);
9680 xtensa_move_literals (void)
9683 frchainS
*frchain_from
, *frchain_to
;
9684 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9685 fragS
**frag_splice
;
9688 fixS
*fix
, *next_fix
, **fix_splice
;
9691 mark_literal_frags (literal_head
->next
);
9692 mark_literal_frags (init_literal_head
->next
);
9693 mark_literal_frags (fini_literal_head
->next
);
9695 if (use_literal_section
)
9698 segment
= literal_head
->next
;
9701 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9702 search_frag
= frchain_from
->frch_root
;
9703 literal_pool
= NULL
;
9705 frag_splice
= &(frchain_from
->frch_root
);
9707 while (!search_frag
->tc_frag_data
.literal_frag
)
9709 assert (search_frag
->fr_fix
== 0
9710 || search_frag
->fr_type
== rs_align
);
9711 search_frag
= search_frag
->fr_next
;
9714 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9715 == RELAX_LITERAL_POOL_BEGIN
);
9716 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9718 /* Make sure that all the frags in this series are closed, and
9719 that there is at least one left over of zero-size. This
9720 prevents us from making a segment with an frchain without any
9722 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9723 xtensa_set_frag_assembly_state (frag_now
);
9724 last_frag
= frag_now
;
9725 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9726 xtensa_set_frag_assembly_state (frag_now
);
9728 while (search_frag
!= frag_now
)
9730 next_frag
= search_frag
->fr_next
;
9732 /* First, move the frag out of the literal section and
9733 to the appropriate place. */
9734 if (search_frag
->tc_frag_data
.literal_frag
)
9736 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9737 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9738 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9739 assert (frchain_to
);
9741 insert_after
= literal_pool
;
9743 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9744 insert_after
= insert_after
->fr_next
;
9746 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9748 *frag_splice
= next_frag
;
9749 search_frag
->fr_next
= insert_after
->fr_next
;
9750 insert_after
->fr_next
= search_frag
;
9751 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9753 /* Now move any fixups associated with this frag to the
9755 fix
= frchain_from
->fix_root
;
9756 fix_splice
= &(frchain_from
->fix_root
);
9759 next_fix
= fix
->fx_next
;
9760 if (fix
->fx_frag
== search_frag
)
9762 *fix_splice
= next_fix
;
9763 fix
->fx_next
= frchain_to
->fix_root
;
9764 frchain_to
->fix_root
= fix
;
9765 if (frchain_to
->fix_tail
== NULL
)
9766 frchain_to
->fix_tail
= fix
;
9769 fix_splice
= &(fix
->fx_next
);
9772 search_frag
= next_frag
;
9775 if (frchain_from
->fix_root
!= NULL
)
9777 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9778 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9780 assert (frchain_from
->fix_root
== NULL
);
9782 frchain_from
->fix_tail
= NULL
;
9783 xtensa_restore_emit_state (&state
);
9784 segment
= segment
->next
;
9787 /* Now fix up the SEGMENT value for all the literal symbols. */
9788 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9790 symbolS
*lit_sym
= lit
->sym
;
9791 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9793 S_SET_SEGMENT (lit_sym
, dest_seg
);
9798 /* Walk over all the frags for segments in a list and mark them as
9799 containing literals. As clunky as this is, we can't rely on frag_var
9800 and frag_variant to get called in all situations. */
9803 mark_literal_frags (seg_list
*segment
)
9805 frchainS
*frchain_from
;
9810 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9811 search_frag
= frchain_from
->frch_root
;
9814 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9815 search_frag
= search_frag
->fr_next
;
9817 segment
= segment
->next
;
9823 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9825 /* Move all of the sections in the section list to come
9826 after "after" in the gnu segment list. */
9831 segT literal_section
= head
->seg
;
9833 /* Move the literal section after "after". */
9834 assert (literal_section
);
9835 if (literal_section
!= after
)
9837 bfd_section_list_remove (stdoutput
, literal_section
);
9838 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9846 /* Push all the literal segments to the end of the gnu list. */
9849 xtensa_reorder_segments (void)
9856 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9862 /* Now that we have the last section, push all the literal
9863 sections to the end. */
9864 xtensa_reorder_seg_list (literal_head
, last_sec
);
9865 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
9866 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
9868 /* Now perform the final error check. */
9869 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9871 assert (new_count
== old_count
);
9875 /* Change the emit state (seg, subseg, and frag related stuff) to the
9876 correct location. Return a emit_state which can be passed to
9877 xtensa_restore_emit_state to return to current fragment. */
9880 xtensa_switch_to_literal_fragment (emit_state
*result
)
9882 if (directive_state
[directive_absolute_literals
])
9884 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
9885 &default_lit_sections
.lit4_seg
, FALSE
);
9886 xtensa_switch_section_emit_state (result
,
9887 default_lit_sections
.lit4_seg
, 0);
9890 xtensa_switch_to_non_abs_literal_fragment (result
);
9892 /* Do a 4-byte align here. */
9893 frag_align (2, 0, 0);
9894 record_alignment (now_seg
, 2);
9899 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9901 /* When we mark a literal pool location, we want to put a frag in
9902 the literal pool that points to it. But to do that, we want to
9903 switch_to_literal_fragment. But literal sections don't have
9904 literal pools, so their location is always null, so we would
9905 recurse forever. This is kind of hacky, but it works. */
9907 static bfd_boolean recursive
= FALSE
;
9908 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9909 bfd_boolean is_init
=
9910 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9912 bfd_boolean is_fini
=
9913 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9915 if (pool_location
== NULL
9916 && !use_literal_section
9918 && !is_init
&& ! is_fini
)
9920 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9922 xtensa_mark_literal_pool_location ();
9926 /* Special case: If we are in the ".fini" or ".init" section, then
9927 we will ALWAYS be generating to the ".fini.literal" and
9928 ".init.literal" sections. */
9932 cache_literal_section (init_literal_head
,
9933 default_lit_sections
.init_lit_seg_name
,
9934 &default_lit_sections
.init_lit_seg
, TRUE
);
9935 xtensa_switch_section_emit_state (result
,
9936 default_lit_sections
.init_lit_seg
, 0);
9940 cache_literal_section (fini_literal_head
,
9941 default_lit_sections
.fini_lit_seg_name
,
9942 &default_lit_sections
.fini_lit_seg
, TRUE
);
9943 xtensa_switch_section_emit_state (result
,
9944 default_lit_sections
.fini_lit_seg
, 0);
9948 cache_literal_section (literal_head
,
9949 default_lit_sections
.lit_seg_name
,
9950 &default_lit_sections
.lit_seg
, TRUE
);
9951 xtensa_switch_section_emit_state (result
,
9952 default_lit_sections
.lit_seg
, 0);
9955 if (!use_literal_section
9956 && !is_init
&& !is_fini
9957 && get_literal_pool_location (now_seg
) != pool_location
)
9959 /* Close whatever frag is there. */
9960 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9961 xtensa_set_frag_assembly_state (frag_now
);
9962 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9963 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9964 xtensa_set_frag_assembly_state (frag_now
);
9969 /* Call this function before emitting data into the literal section.
9970 This is a helper function for xtensa_switch_to_literal_fragment.
9971 This is similar to a .section new_now_seg subseg. */
9974 xtensa_switch_section_emit_state (emit_state
*state
,
9976 subsegT new_now_subseg
)
9978 state
->name
= now_seg
->name
;
9979 state
->now_seg
= now_seg
;
9980 state
->now_subseg
= now_subseg
;
9981 state
->generating_literals
= generating_literals
;
9982 generating_literals
++;
9983 subseg_set (new_now_seg
, new_now_subseg
);
9987 /* Use to restore the emitting into the normal place. */
9990 xtensa_restore_emit_state (emit_state
*state
)
9992 generating_literals
= state
->generating_literals
;
9993 subseg_set (state
->now_seg
, state
->now_subseg
);
9997 /* Get a segment of a given name. If the segment is already
9998 present, return it; otherwise, create a new one. */
10001 cache_literal_section (seg_list
*head
,
10004 bfd_boolean is_code
)
10006 segT current_section
= now_seg
;
10007 int current_subsec
= now_subseg
;
10013 /* Check if the named section exists. */
10014 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10016 if (!strcmp (segment_name (seg
), name
))
10022 /* Create a new literal section. */
10023 seg
= subseg_new (name
, (subsegT
) 0);
10026 /* Add the newly created literal segment to the specified list. */
10027 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10029 n
->next
= head
->next
;
10032 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10033 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10034 | (is_code
? SEC_CODE
: SEC_DATA
));
10035 bfd_set_section_alignment (stdoutput
, seg
, 2);
10039 subseg_set (current_section
, current_subsec
);
10043 /* Property Tables Stuff. */
10045 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10046 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10047 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10049 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10050 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10052 static bfd_boolean
get_frag_is_literal (const fragS
*);
10053 static void xtensa_create_property_segments
10054 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10055 static void xtensa_create_xproperty_segments
10056 (frag_flags_fn
, const char *, xt_section_type
);
10057 static segment_info_type
*retrieve_segment_info (segT
);
10058 static segT
retrieve_xtensa_section (char *);
10059 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10060 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10061 static void add_xt_block_frags
10062 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10063 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10064 static void xtensa_frag_flags_init (frag_flags
*);
10065 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10066 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10067 static void add_xt_prop_frags
10068 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10070 /* Set up property tables after relaxation. */
10073 xtensa_post_relax_hook (void)
10075 xtensa_move_seg_list_to_beginning (literal_head
);
10076 xtensa_move_seg_list_to_beginning (init_literal_head
);
10077 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10079 xtensa_find_unmarked_state_frags ();
10081 xtensa_create_property_segments (get_frag_is_literal
,
10083 XTENSA_LIT_SEC_NAME
,
10085 xtensa_create_xproperty_segments (get_frag_property_flags
,
10086 XTENSA_PROP_SEC_NAME
,
10089 if (warn_unaligned_branch_targets
)
10090 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10091 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10095 /* This function is only meaningful after xtensa_move_literals. */
10098 get_frag_is_literal (const fragS
*fragP
)
10100 assert (fragP
!= NULL
);
10101 return fragP
->tc_frag_data
.is_literal
;
10106 xtensa_create_property_segments (frag_predicate property_function
,
10107 frag_predicate end_property_function
,
10108 const char *section_name_base
,
10109 xt_section_type sec_type
)
10113 /* Walk over all of the current segments.
10114 Walk over each fragment
10115 For each non-empty fragment,
10116 Build a property record (append where possible). */
10118 for (seclist
= &stdoutput
->sections
;
10119 seclist
&& *seclist
;
10120 seclist
= &(*seclist
)->next
)
10122 segT sec
= *seclist
;
10125 flags
= bfd_get_section_flags (stdoutput
, sec
);
10126 if (flags
& SEC_DEBUGGING
)
10128 if (!(flags
& SEC_ALLOC
))
10131 if (section_has_property (sec
, property_function
))
10133 char *property_section_name
=
10134 xtensa_get_property_section_name (sec
, section_name_base
);
10135 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10136 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10137 xtensa_block_info
**xt_blocks
=
10138 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10139 /* Walk over all of the frchains here and add new sections. */
10140 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10141 end_property_function
);
10145 /* Now we fill them out.... */
10147 for (seclist
= &stdoutput
->sections
;
10148 seclist
&& *seclist
;
10149 seclist
= &(*seclist
)->next
)
10151 segment_info_type
*seginfo
;
10152 xtensa_block_info
*block
;
10153 segT sec
= *seclist
;
10155 seginfo
= seg_info (sec
);
10156 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10160 xtensa_block_info
*cur_block
;
10161 /* This is a section with some data. */
10163 bfd_size_type rec_size
;
10165 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10168 rec_size
= num_recs
* 8;
10169 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10171 /* In order to make this work with the assembler, we have to
10172 build some frags and then build the "fixups" for it. It
10173 would be easier to just set the contents then set the
10178 /* Allocate a fragment and leak it. */
10180 bfd_size_type frag_size
;
10182 frchainS
*frchainP
;
10186 frag_size
= sizeof (fragS
) + rec_size
;
10187 fragP
= (fragS
*) xmalloc (frag_size
);
10189 memset (fragP
, 0, frag_size
);
10190 fragP
->fr_address
= 0;
10191 fragP
->fr_next
= NULL
;
10192 fragP
->fr_fix
= rec_size
;
10194 fragP
->fr_type
= rs_fill
;
10195 /* The rest are zeros. */
10197 frchainP
= seginfo
->frchainP
;
10198 frchainP
->frch_root
= fragP
;
10199 frchainP
->frch_last
= fragP
;
10201 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10202 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10204 seginfo
->fix_root
= fixes
;
10205 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10207 frag_data
= &fragP
->fr_literal
[0];
10208 for (i
= 0; i
< num_recs
; i
++)
10210 fixS
*fix
= &fixes
[i
];
10211 assert (cur_block
);
10213 /* Write the fixup. */
10214 if (i
!= num_recs
- 1)
10215 fix
->fx_next
= &fixes
[i
+ 1];
10217 fix
->fx_next
= NULL
;
10220 fix
->fx_frag
= fragP
;
10221 fix
->fx_where
= i
* 8;
10222 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10223 fix
->fx_offset
= cur_block
->offset
;
10224 fix
->fx_r_type
= BFD_RELOC_32
;
10225 fix
->fx_file
= "Internal Assembly";
10228 /* Write the length. */
10229 md_number_to_chars (&frag_data
[4 + 8 * i
],
10230 cur_block
->size
, 4);
10231 cur_block
= cur_block
->next
;
10240 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10241 const char *section_name_base
,
10242 xt_section_type sec_type
)
10246 /* Walk over all of the current segments.
10247 Walk over each fragment.
10248 For each fragment that has instructions,
10249 build an instruction record (append where possible). */
10251 for (seclist
= &stdoutput
->sections
;
10252 seclist
&& *seclist
;
10253 seclist
= &(*seclist
)->next
)
10255 segT sec
= *seclist
;
10258 flags
= bfd_get_section_flags (stdoutput
, sec
);
10259 if ((flags
& SEC_DEBUGGING
)
10260 || !(flags
& SEC_ALLOC
)
10261 || (flags
& SEC_MERGE
))
10264 if (section_has_xproperty (sec
, flag_fn
))
10266 char *property_section_name
=
10267 xtensa_get_property_section_name (sec
, section_name_base
);
10268 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10269 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10270 xtensa_block_info
**xt_blocks
=
10271 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10272 /* Walk over all of the frchains here and add new sections. */
10273 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10277 /* Now we fill them out.... */
10279 for (seclist
= &stdoutput
->sections
;
10280 seclist
&& *seclist
;
10281 seclist
= &(*seclist
)->next
)
10283 segment_info_type
*seginfo
;
10284 xtensa_block_info
*block
;
10285 segT sec
= *seclist
;
10287 seginfo
= seg_info (sec
);
10288 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10292 xtensa_block_info
*cur_block
;
10293 /* This is a section with some data. */
10295 bfd_size_type rec_size
;
10297 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10300 rec_size
= num_recs
* (8 + 4);
10301 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10303 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10305 /* In order to make this work with the assembler, we have to build
10306 some frags then build the "fixups" for it. It would be easier to
10307 just set the contents then set the arlents. */
10311 /* Allocate a fragment and (unfortunately) leak it. */
10313 bfd_size_type frag_size
;
10315 frchainS
*frchainP
;
10319 frag_size
= sizeof (fragS
) + rec_size
;
10320 fragP
= (fragS
*) xmalloc (frag_size
);
10322 memset (fragP
, 0, frag_size
);
10323 fragP
->fr_address
= 0;
10324 fragP
->fr_next
= NULL
;
10325 fragP
->fr_fix
= rec_size
;
10327 fragP
->fr_type
= rs_fill
;
10328 /* The rest are zeros. */
10330 frchainP
= seginfo
->frchainP
;
10331 frchainP
->frch_root
= fragP
;
10332 frchainP
->frch_last
= fragP
;
10334 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10335 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10337 seginfo
->fix_root
= fixes
;
10338 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10340 frag_data
= &fragP
->fr_literal
[0];
10341 for (i
= 0; i
< num_recs
; i
++)
10343 fixS
*fix
= &fixes
[i
];
10344 assert (cur_block
);
10346 /* Write the fixup. */
10347 if (i
!= num_recs
- 1)
10348 fix
->fx_next
= &fixes
[i
+ 1];
10350 fix
->fx_next
= NULL
;
10353 fix
->fx_frag
= fragP
;
10354 fix
->fx_where
= i
* (8 + 4);
10355 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10356 fix
->fx_offset
= cur_block
->offset
;
10357 fix
->fx_r_type
= BFD_RELOC_32
;
10358 fix
->fx_file
= "Internal Assembly";
10361 /* Write the length. */
10362 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10363 cur_block
->size
, 4);
10364 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10365 frag_flags_to_number (&cur_block
->flags
),
10367 cur_block
= cur_block
->next
;
10375 static segment_info_type
*
10376 retrieve_segment_info (segT seg
)
10378 segment_info_type
*seginfo
;
10379 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10382 frchainS
*frchainP
;
10384 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10385 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10386 seginfo
->fix_root
= NULL
;
10387 seginfo
->fix_tail
= NULL
;
10388 seginfo
->bfd_section
= seg
;
10390 /* We will not be dealing with these, only our special ones. */
10391 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10393 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10394 frchainP
->frch_root
= NULL
;
10395 frchainP
->frch_last
= NULL
;
10396 frchainP
->frch_next
= NULL
;
10397 frchainP
->frch_seg
= seg
;
10398 frchainP
->frch_subseg
= 0;
10399 frchainP
->fix_root
= NULL
;
10400 frchainP
->fix_tail
= NULL
;
10401 /* Do not init the objstack. */
10402 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10403 /* frchainP->frch_frag_now = fragP; */
10404 frchainP
->frch_frag_now
= NULL
;
10406 seginfo
->frchainP
= frchainP
;
10414 retrieve_xtensa_section (char *sec_name
)
10416 bfd
*abfd
= stdoutput
;
10417 flagword flags
, out_flags
, link_once_flags
;
10420 flags
= bfd_get_section_flags (abfd
, now_seg
);
10421 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10422 if (link_once_flags
)
10423 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10424 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10426 s
= bfd_make_section_old_way (abfd
, sec_name
);
10428 as_bad (_("could not create section %s"), sec_name
);
10429 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10430 as_bad (_("invalid flag combination on section %s"), sec_name
);
10437 section_has_property (segT sec
, frag_predicate property_function
)
10439 segment_info_type
*seginfo
= seg_info (sec
);
10442 if (seginfo
&& seginfo
->frchainP
)
10444 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10446 if (property_function (fragP
)
10447 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10456 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10458 segment_info_type
*seginfo
= seg_info (sec
);
10461 if (seginfo
&& seginfo
->frchainP
)
10463 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10465 frag_flags prop_flags
;
10466 property_function (fragP
, &prop_flags
);
10467 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10475 /* Two types of block sections exist right now: literal and insns. */
10478 add_xt_block_frags (segT sec
,
10480 xtensa_block_info
**xt_block
,
10481 frag_predicate property_function
,
10482 frag_predicate end_property_function
)
10484 segment_info_type
*seg_info
;
10485 segment_info_type
*xt_seg_info
;
10486 bfd_vma seg_offset
;
10489 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10490 seg_info
= retrieve_segment_info (sec
);
10492 /* Build it if needed. */
10493 while (*xt_block
!= NULL
)
10494 xt_block
= &(*xt_block
)->next
;
10495 /* We are either at NULL at the beginning or at the end. */
10497 /* Walk through the frags. */
10500 if (seg_info
->frchainP
)
10502 for (fragP
= seg_info
->frchainP
->frch_root
;
10504 fragP
= fragP
->fr_next
)
10506 if (property_function (fragP
)
10507 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10509 if (*xt_block
!= NULL
)
10511 if ((*xt_block
)->offset
+ (*xt_block
)->size
10512 == fragP
->fr_address
)
10513 (*xt_block
)->size
+= fragP
->fr_fix
;
10515 xt_block
= &((*xt_block
)->next
);
10517 if (*xt_block
== NULL
)
10519 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10520 xmalloc (sizeof (xtensa_block_info
));
10521 new_block
->sec
= sec
;
10522 new_block
->offset
= fragP
->fr_address
;
10523 new_block
->size
= fragP
->fr_fix
;
10524 new_block
->next
= NULL
;
10525 xtensa_frag_flags_init (&new_block
->flags
);
10526 *xt_block
= new_block
;
10528 if (end_property_function
10529 && end_property_function (fragP
))
10531 xt_block
= &((*xt_block
)->next
);
10539 /* Break the encapsulation of add_xt_prop_frags here. */
10542 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10544 if (prop_flags
->is_literal
10545 || prop_flags
->is_insn
10546 || prop_flags
->is_data
10547 || prop_flags
->is_unreachable
)
10554 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10556 memset (prop_flags
, 0, sizeof (frag_flags
));
10561 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10563 xtensa_frag_flags_init (prop_flags
);
10564 if (fragP
->tc_frag_data
.is_literal
)
10565 prop_flags
->is_literal
= TRUE
;
10566 if (fragP
->tc_frag_data
.is_unreachable
)
10567 prop_flags
->is_unreachable
= TRUE
;
10568 else if (fragP
->tc_frag_data
.is_insn
)
10570 prop_flags
->is_insn
= TRUE
;
10571 if (fragP
->tc_frag_data
.is_loop_target
)
10572 prop_flags
->insn
.is_loop_target
= TRUE
;
10573 if (fragP
->tc_frag_data
.is_branch_target
)
10574 prop_flags
->insn
.is_branch_target
= TRUE
;
10575 if (fragP
->tc_frag_data
.is_specific_opcode
10576 || fragP
->tc_frag_data
.is_no_transform
)
10577 prop_flags
->insn
.is_no_transform
= TRUE
;
10578 if (fragP
->tc_frag_data
.is_no_density
)
10579 prop_flags
->insn
.is_no_density
= TRUE
;
10580 if (fragP
->tc_frag_data
.use_absolute_literals
)
10581 prop_flags
->insn
.is_abslit
= TRUE
;
10583 if (fragP
->tc_frag_data
.is_align
)
10585 prop_flags
->is_align
= TRUE
;
10586 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10587 if (xtensa_frag_flags_is_empty (prop_flags
))
10588 prop_flags
->is_data
= TRUE
;
10594 frag_flags_to_number (const frag_flags
*prop_flags
)
10597 if (prop_flags
->is_literal
)
10598 num
|= XTENSA_PROP_LITERAL
;
10599 if (prop_flags
->is_insn
)
10600 num
|= XTENSA_PROP_INSN
;
10601 if (prop_flags
->is_data
)
10602 num
|= XTENSA_PROP_DATA
;
10603 if (prop_flags
->is_unreachable
)
10604 num
|= XTENSA_PROP_UNREACHABLE
;
10605 if (prop_flags
->insn
.is_loop_target
)
10606 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10607 if (prop_flags
->insn
.is_branch_target
)
10609 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10610 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10613 if (prop_flags
->insn
.is_no_density
)
10614 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10615 if (prop_flags
->insn
.is_no_transform
)
10616 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10617 if (prop_flags
->insn
.is_no_reorder
)
10618 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10619 if (prop_flags
->insn
.is_abslit
)
10620 num
|= XTENSA_PROP_INSN_ABSLIT
;
10622 if (prop_flags
->is_align
)
10624 num
|= XTENSA_PROP_ALIGN
;
10625 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10633 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10634 const frag_flags
*prop_flags_2
)
10636 /* Cannot combine with an end marker. */
10638 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10640 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10642 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10645 if (prop_flags_1
->is_insn
)
10647 /* Properties of the beginning of the frag. */
10648 if (prop_flags_2
->insn
.is_loop_target
)
10650 if (prop_flags_2
->insn
.is_branch_target
)
10652 if (prop_flags_1
->insn
.is_no_density
!=
10653 prop_flags_2
->insn
.is_no_density
)
10655 if (prop_flags_1
->insn
.is_no_transform
!=
10656 prop_flags_2
->insn
.is_no_transform
)
10658 if (prop_flags_1
->insn
.is_no_reorder
!=
10659 prop_flags_2
->insn
.is_no_reorder
)
10661 if (prop_flags_1
->insn
.is_abslit
!=
10662 prop_flags_2
->insn
.is_abslit
)
10666 if (prop_flags_1
->is_align
)
10674 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10677 unsigned align_bits
;
10679 if (!xt_block
->flags
.is_align
)
10680 return xt_block
->size
;
10682 end_addr
= xt_block
->offset
+ xt_block
->size
;
10683 align_bits
= xt_block
->flags
.alignment
;
10684 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10685 return end_addr
- xt_block
->offset
;
10690 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10691 const xtensa_block_info
*xt_block_2
)
10693 if (xt_block
->sec
!= xt_block_2
->sec
)
10695 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10696 != xt_block_2
->offset
)
10699 if (xt_block_2
->size
== 0
10700 && (!xt_block_2
->flags
.is_unreachable
10701 || xt_block
->flags
.is_unreachable
))
10703 if (xt_block_2
->flags
.is_align
10704 && xt_block
->flags
.is_align
)
10706 /* Nothing needed. */
10707 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10712 if (xt_block_2
->flags
.is_align
)
10714 /* Push alignment to previous entry. */
10715 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10716 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10721 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10722 &xt_block_2
->flags
))
10725 xt_block
->size
+= xt_block_2
->size
;
10727 if (xt_block_2
->flags
.is_align
)
10729 xt_block
->flags
.is_align
= TRUE
;
10730 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10738 add_xt_prop_frags (segT sec
,
10740 xtensa_block_info
**xt_block
,
10741 frag_flags_fn property_function
)
10743 segment_info_type
*seg_info
;
10744 segment_info_type
*xt_seg_info
;
10745 bfd_vma seg_offset
;
10748 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10749 seg_info
= retrieve_segment_info (sec
);
10750 /* Build it if needed. */
10751 while (*xt_block
!= NULL
)
10753 xt_block
= &(*xt_block
)->next
;
10755 /* We are either at NULL at the beginning or at the end. */
10757 /* Walk through the frags. */
10760 if (seg_info
->frchainP
)
10762 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10763 fragP
= fragP
->fr_next
)
10765 xtensa_block_info tmp_block
;
10766 tmp_block
.sec
= sec
;
10767 tmp_block
.offset
= fragP
->fr_address
;
10768 tmp_block
.size
= fragP
->fr_fix
;
10769 tmp_block
.next
= NULL
;
10770 property_function (fragP
, &tmp_block
.flags
);
10772 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10773 /* && fragP->fr_fix != 0) */
10775 if ((*xt_block
) == NULL
10776 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10778 xtensa_block_info
*new_block
;
10779 if ((*xt_block
) != NULL
)
10780 xt_block
= &(*xt_block
)->next
;
10781 new_block
= (xtensa_block_info
*)
10782 xmalloc (sizeof (xtensa_block_info
));
10783 *new_block
= tmp_block
;
10784 *xt_block
= new_block
;
10792 /* op_placement_info_table */
10794 /* op_placement_info makes it easier to determine which
10795 ops can go in which slots. */
10798 init_op_placement_info_table (void)
10800 xtensa_isa isa
= xtensa_default_isa
;
10801 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10802 xtensa_opcode opcode
;
10805 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10807 op_placement_table
= (op_placement_info_table
)
10808 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10809 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10811 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10813 op_placement_info
*opi
= &op_placement_table
[opcode
];
10814 /* FIXME: Make tinsn allocation dynamic. */
10815 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10816 as_fatal (_("too many operands in instruction"));
10817 opi
->narrowest
= XTENSA_UNDEFINED
;
10818 opi
->narrowest_size
= 0x7F;
10819 opi
->narrowest_slot
= 0;
10821 opi
->num_formats
= 0;
10823 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10825 opi
->slots
[fmt
] = 0;
10826 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10828 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10830 int fmt_length
= xtensa_format_length (isa
, fmt
);
10832 set_bit (fmt
, opi
->formats
);
10833 set_bit (slot
, opi
->slots
[fmt
]);
10834 /* opi->slot_count[fmt]++; */
10835 if (fmt_length
< opi
->narrowest_size
)
10837 opi
->narrowest
= fmt
;
10838 opi
->narrowest_size
= fmt_length
;
10839 opi
->narrowest_slot
= slot
;
10844 opi
->num_formats
++;
10847 xtensa_insnbuf_free (isa
, ibuf
);
10852 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10854 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10858 /* If the opcode is available in a single slot format, return its size. */
10861 xg_get_single_size (xtensa_opcode opcode
)
10863 return op_placement_table
[opcode
].narrowest_size
;
10867 static xtensa_format
10868 xg_get_single_format (xtensa_opcode opcode
)
10870 return op_placement_table
[opcode
].narrowest
;
10875 xg_get_single_slot (xtensa_opcode opcode
)
10877 return op_placement_table
[opcode
].narrowest_slot
;
10881 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10884 istack_init (IStack
*stack
)
10886 memset (stack
, 0, sizeof (IStack
));
10892 istack_empty (IStack
*stack
)
10894 return (stack
->ninsn
== 0);
10899 istack_full (IStack
*stack
)
10901 return (stack
->ninsn
== MAX_ISTACK
);
10905 /* Return a pointer to the top IStack entry.
10906 It is an error to call this if istack_empty () is TRUE. */
10909 istack_top (IStack
*stack
)
10911 int rec
= stack
->ninsn
- 1;
10912 assert (!istack_empty (stack
));
10913 return &stack
->insn
[rec
];
10917 /* Add a new TInsn to an IStack.
10918 It is an error to call this if istack_full () is TRUE. */
10921 istack_push (IStack
*stack
, TInsn
*insn
)
10923 int rec
= stack
->ninsn
;
10924 assert (!istack_full (stack
));
10925 stack
->insn
[rec
] = *insn
;
10930 /* Clear space for the next TInsn on the IStack and return a pointer
10931 to it. It is an error to call this if istack_full () is TRUE. */
10934 istack_push_space (IStack
*stack
)
10936 int rec
= stack
->ninsn
;
10938 assert (!istack_full (stack
));
10939 insn
= &stack
->insn
[rec
];
10940 memset (insn
, 0, sizeof (TInsn
));
10946 /* Remove the last pushed instruction. It is an error to call this if
10947 istack_empty () returns TRUE. */
10950 istack_pop (IStack
*stack
)
10952 int rec
= stack
->ninsn
- 1;
10953 assert (!istack_empty (stack
));
10955 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
10959 /* TInsn functions. */
10962 tinsn_init (TInsn
*dst
)
10964 memset (dst
, 0, sizeof (TInsn
));
10968 /* Get the ``num''th token of the TInsn.
10969 It is illegal to call this if num > insn->ntoks. */
10972 tinsn_get_tok (TInsn
*insn
, int num
)
10974 assert (num
< insn
->ntok
);
10975 return &insn
->tok
[num
];
10979 /* Return TRUE if ANY of the operands in the insn are symbolic. */
10982 tinsn_has_symbolic_operands (const TInsn
*insn
)
10985 int n
= insn
->ntok
;
10987 assert (insn
->insn_type
== ITYPE_INSN
);
10989 for (i
= 0; i
< n
; ++i
)
10991 switch (insn
->tok
[i
].X_op
)
11005 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11007 xtensa_isa isa
= xtensa_default_isa
;
11009 int n
= insn
->ntok
;
11011 assert (insn
->insn_type
== ITYPE_INSN
);
11013 for (i
= 0; i
< n
; ++i
)
11015 switch (insn
->tok
[i
].X_op
)
11023 /* Errors for these types are caught later. */
11028 /* Symbolic immediates are only allowed on the last immediate
11029 operand. At this time, CONST16 is the only opcode where we
11030 support non-PC-relative relocations. */
11031 if (i
!= get_relaxable_immed (insn
->opcode
)
11032 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11033 && insn
->opcode
!= xtensa_const16_opcode
))
11035 as_bad (_("invalid symbolic operand"));
11044 /* For assembly code with complex expressions (e.g. subtraction),
11045 we have to build them in the literal pool so that
11046 their results are calculated correctly after relaxation.
11047 The relaxation only handles expressions that
11048 boil down to SYMBOL + OFFSET. */
11051 tinsn_has_complex_operands (const TInsn
*insn
)
11054 int n
= insn
->ntok
;
11055 assert (insn
->insn_type
== ITYPE_INSN
);
11056 for (i
= 0; i
< n
; ++i
)
11058 switch (insn
->tok
[i
].X_op
)
11074 /* Encode a TInsn opcode and its constant operands into slotbuf.
11075 Return TRUE if there is a symbol in the immediate field. This
11076 function assumes that:
11077 1) The number of operands are correct.
11078 2) The insn_type is ITYPE_INSN.
11079 3) The opcode can be encoded in the specified format and slot.
11080 4) Operands are either O_constant or O_symbol, and all constants fit. */
11083 tinsn_to_slotbuf (xtensa_format fmt
,
11086 xtensa_insnbuf slotbuf
)
11088 xtensa_isa isa
= xtensa_default_isa
;
11089 xtensa_opcode opcode
= tinsn
->opcode
;
11090 bfd_boolean has_fixup
= FALSE
;
11091 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11094 assert (tinsn
->insn_type
== ITYPE_INSN
);
11095 if (noperands
!= tinsn
->ntok
)
11096 as_fatal (_("operand number mismatch"));
11098 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11100 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11101 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11105 for (i
= 0; i
< noperands
; i
++)
11107 expressionS
*expr
= &tinsn
->tok
[i
];
11113 switch (expr
->X_op
)
11116 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11118 /* The register number has already been checked in
11119 expression_maybe_register, so we don't need to check here. */
11120 opnd_value
= expr
->X_add_number
;
11121 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11122 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11125 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11129 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11131 as_where (&file_name
, &line
);
11132 /* It is a constant and we called this function
11133 then we have to try to fit it. */
11134 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11135 expr
->X_add_number
, file_name
, line
);
11148 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11149 into a multi-slot instruction, fill the other slots with NOPs.
11150 Return TRUE if there is a symbol in the immediate field. See also the
11151 assumptions listed for tinsn_to_slotbuf. */
11154 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11156 static xtensa_insnbuf slotbuf
= 0;
11157 static vliw_insn vinsn
;
11158 xtensa_isa isa
= xtensa_default_isa
;
11159 bfd_boolean has_fixup
= FALSE
;
11164 slotbuf
= xtensa_insnbuf_alloc (isa
);
11165 xg_init_vinsn (&vinsn
);
11168 xg_clear_vinsn (&vinsn
);
11170 bundle_tinsn (tinsn
, &vinsn
);
11172 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11174 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11176 /* Only one slot may have a fix-up because the rest contains NOPs. */
11178 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11179 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11186 /* Check the instruction arguments. Return TRUE on failure. */
11189 tinsn_check_arguments (const TInsn
*insn
)
11191 xtensa_isa isa
= xtensa_default_isa
;
11192 xtensa_opcode opcode
= insn
->opcode
;
11194 if (opcode
== XTENSA_UNDEFINED
)
11196 as_bad (_("invalid opcode"));
11200 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11202 as_bad (_("too few operands"));
11206 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11208 as_bad (_("too many operands"));
11215 /* Load an instruction from its encoded form. */
11218 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11222 xg_init_vinsn (&vinsn
);
11223 vinsn_from_chars (&vinsn
, f
);
11225 *tinsn
= vinsn
.slots
[slot
];
11226 xg_free_vinsn (&vinsn
);
11231 tinsn_from_insnbuf (TInsn
*tinsn
,
11232 xtensa_insnbuf slotbuf
,
11237 xtensa_isa isa
= xtensa_default_isa
;
11239 /* Find the immed. */
11240 tinsn_init (tinsn
);
11241 tinsn
->insn_type
= ITYPE_INSN
;
11242 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11243 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11244 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11245 for (i
= 0; i
< tinsn
->ntok
; i
++)
11247 set_expr_const (&tinsn
->tok
[i
],
11248 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11249 tinsn
->opcode
, i
));
11254 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11257 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11259 xtensa_opcode opcode
= tinsn
->opcode
;
11262 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11264 opnum
= get_relaxable_immed (opcode
);
11265 assert (opnum
>= 0);
11266 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11267 fragP
->tc_frag_data
.slot_symbols
[slot
],
11268 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11274 get_num_stack_text_bytes (IStack
*istack
)
11277 int text_bytes
= 0;
11279 for (i
= 0; i
< istack
->ninsn
; i
++)
11281 TInsn
*tinsn
= &istack
->insn
[i
];
11282 if (tinsn
->insn_type
== ITYPE_INSN
)
11283 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11290 get_num_stack_literal_bytes (IStack
*istack
)
11295 for (i
= 0; i
< istack
->ninsn
; i
++)
11297 TInsn
*tinsn
= &istack
->insn
[i
];
11298 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11305 /* vliw_insn functions. */
11308 xg_init_vinsn (vliw_insn
*v
)
11311 xtensa_isa isa
= xtensa_default_isa
;
11313 xg_clear_vinsn (v
);
11315 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11316 if (v
->insnbuf
== NULL
)
11317 as_fatal (_("out of memory"));
11319 for (i
= 0; i
< MAX_SLOTS
; i
++)
11321 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11322 if (v
->slotbuf
[i
] == NULL
)
11323 as_fatal (_("out of memory"));
11329 xg_clear_vinsn (vliw_insn
*v
)
11333 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11335 v
->format
= XTENSA_UNDEFINED
;
11337 v
->inside_bundle
= FALSE
;
11339 if (xt_saved_debug_type
!= DEBUG_NONE
)
11340 debug_type
= xt_saved_debug_type
;
11342 for (i
= 0; i
< MAX_SLOTS
; i
++)
11343 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11348 vinsn_has_specific_opcodes (vliw_insn
*v
)
11352 for (i
= 0; i
< v
->num_slots
; i
++)
11354 if (v
->slots
[i
].is_specific_opcode
)
11362 xg_free_vinsn (vliw_insn
*v
)
11365 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11366 for (i
= 0; i
< MAX_SLOTS
; i
++)
11367 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11371 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11372 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11375 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11378 bfd_boolean record_fixup
)
11380 xtensa_isa isa
= xtensa_default_isa
;
11381 xtensa_format fmt
= vinsn
->format
;
11382 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11384 bfd_boolean has_fixup
= FALSE
;
11386 xtensa_format_encode (isa
, fmt
, insnbuf
);
11388 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11390 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11391 bfd_boolean tinsn_has_fixup
=
11392 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11393 vinsn
->slotbuf
[slot
]);
11395 xtensa_format_set_slot (isa
, fmt
, slot
,
11396 insnbuf
, vinsn
->slotbuf
[slot
]);
11397 if (tinsn_has_fixup
)
11400 xtensa_opcode opcode
= tinsn
->opcode
;
11401 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11404 for (i
= 0; i
< noperands
; i
++)
11406 expressionS
* expr
= &tinsn
->tok
[i
];
11407 switch (expr
->X_op
)
11412 if (get_relaxable_immed (opcode
) == i
)
11414 /* Add a fix record for the instruction, except if this
11415 function is being called prior to relaxation, i.e.,
11416 if record_fixup is false, and the instruction might
11417 be relaxed later. */
11419 || tinsn
->is_specific_opcode
11420 || !xg_is_relaxable_insn (tinsn
, 0))
11422 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11423 frag_offset
- fragP
->fr_literal
);
11427 if (expr
->X_op
!= O_symbol
)
11428 as_bad (_("invalid operand"));
11429 tinsn
->symbol
= expr
->X_add_symbol
;
11430 tinsn
->offset
= expr
->X_add_number
;
11434 as_bad (_("symbolic operand not allowed"));
11442 as_bad (_("expression too complex"));
11454 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11456 static xtensa_insnbuf insnbuf
= NULL
;
11457 static xtensa_insnbuf slotbuf
= NULL
;
11460 xtensa_isa isa
= xtensa_default_isa
;
11464 insnbuf
= xtensa_insnbuf_alloc (isa
);
11465 slotbuf
= xtensa_insnbuf_alloc (isa
);
11468 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11469 fmt
= xtensa_format_decode (isa
, insnbuf
);
11470 if (fmt
== XTENSA_UNDEFINED
)
11471 as_fatal (_("cannot decode instruction format"));
11472 vinsn
->format
= fmt
;
11473 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11475 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11477 TInsn
*tinsn
= &vinsn
->slots
[i
];
11478 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11479 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11484 /* Expression utilities. */
11486 /* Return TRUE if the expression is an integer constant. */
11489 expr_is_const (const expressionS
*s
)
11491 return (s
->X_op
== O_constant
);
11495 /* Get the expression constant.
11496 Calling this is illegal if expr_is_const () returns TRUE. */
11499 get_expr_const (const expressionS
*s
)
11501 assert (expr_is_const (s
));
11502 return s
->X_add_number
;
11506 /* Set the expression to a constant value. */
11509 set_expr_const (expressionS
*s
, offsetT val
)
11511 s
->X_op
= O_constant
;
11512 s
->X_add_number
= val
;
11513 s
->X_add_symbol
= NULL
;
11514 s
->X_op_symbol
= NULL
;
11519 expr_is_register (const expressionS
*s
)
11521 return (s
->X_op
== O_register
);
11525 /* Get the expression constant.
11526 Calling this is illegal if expr_is_const () returns TRUE. */
11529 get_expr_register (const expressionS
*s
)
11531 assert (expr_is_register (s
));
11532 return s
->X_add_number
;
11536 /* Set the expression to a symbol + constant offset. */
11539 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11541 s
->X_op
= O_symbol
;
11542 s
->X_add_symbol
= sym
;
11543 s
->X_op_symbol
= NULL
; /* unused */
11544 s
->X_add_number
= offset
;
11548 /* Return TRUE if the two expressions are equal. */
11551 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11553 if (s1
->X_op
!= s2
->X_op
)
11555 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11557 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11559 if (s1
->X_add_number
!= s2
->X_add_number
)
11566 copy_expr (expressionS
*dst
, const expressionS
*src
)
11568 memcpy (dst
, src
, sizeof (expressionS
));
11572 /* Support for the "--rename-section" option. */
11574 struct rename_section_struct
11578 struct rename_section_struct
*next
;
11581 static struct rename_section_struct
*section_rename
;
11584 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11585 entries to the section_rename list. Note: Specifying multiple
11586 renamings separated by colons is not documented and is retained only
11587 for backward compatibility. */
11590 build_section_rename (const char *arg
)
11592 struct rename_section_struct
*r
;
11593 char *this_arg
= NULL
;
11594 char *next_arg
= NULL
;
11596 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11598 char *old_name
, *new_name
;
11602 next_arg
= strchr (this_arg
, ':');
11610 old_name
= this_arg
;
11611 new_name
= strchr (this_arg
, '=');
11613 if (*old_name
== '\0')
11615 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11618 if (!new_name
|| new_name
[1] == '\0')
11620 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11627 /* Check for invalid section renaming. */
11628 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11630 if (strcmp (r
->old_name
, old_name
) == 0)
11631 as_bad (_("section %s renamed multiple times"), old_name
);
11632 if (strcmp (r
->new_name
, new_name
) == 0)
11633 as_bad (_("multiple sections remapped to output section %s"),
11638 r
= (struct rename_section_struct
*)
11639 xmalloc (sizeof (struct rename_section_struct
));
11640 r
->old_name
= xstrdup (old_name
);
11641 r
->new_name
= xstrdup (new_name
);
11642 r
->next
= section_rename
;
11643 section_rename
= r
;
11649 xtensa_section_rename (char *name
)
11651 struct rename_section_struct
*r
= section_rename
;
11653 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11655 if (strcmp (r
->old_name
, name
) == 0)
11656 return r
->new_name
;