1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "xtensa-istack.h"
29 #include "dwarf2dbg.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
268 unsigned is_loop_target
: 1;
269 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
270 unsigned bt_align_priority
: 2;
272 unsigned is_no_density
: 1;
273 /* no_longcalls flag does not need to be placed in the object file. */
274 /* is_specific_opcode implies no_transform. */
275 unsigned is_no_transform
: 1;
277 unsigned is_no_reorder
: 1;
279 /* Uses absolute literal addressing for l32r. */
280 unsigned is_abslit
: 1;
282 unsigned is_align
: 1;
283 unsigned alignment
: 5;
287 /* Structure for saving information about a block of property data
288 for frags that have the same flags. */
289 struct xtensa_block_info_struct
295 struct xtensa_block_info_struct
*next
;
299 /* Structure for saving the current state before emitting literals. */
300 typedef struct emit_state_struct
305 int generating_literals
;
309 /* Opcode placement information */
311 typedef unsigned long long bitfield
;
312 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
313 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
314 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
316 #define MAX_FORMATS 32
318 typedef struct op_placement_info_struct
321 /* A number describing how restrictive the issue is for this
322 opcode. For example, an opcode that fits lots of different
323 formats has a high freedom, as does an opcode that fits
324 only one format but many slots in that format. The most
325 restrictive is the opcode that fits only one slot in one
328 xtensa_format narrowest
;
332 /* formats is a bitfield with the Nth bit set
333 if the opcode fits in the Nth xtensa_format. */
336 /* slots[N]'s Mth bit is set if the op fits in the
337 Mth slot of the Nth xtensa_format. */
338 bitfield slots
[MAX_FORMATS
];
340 /* A count of the number of slots in a given format
341 an op can fit (i.e., the bitcount of the slot field above). */
342 char slots_in_format
[MAX_FORMATS
];
344 } op_placement_info
, *op_placement_info_table
;
346 op_placement_info_table op_placement_table
;
349 /* Extra expression types. */
351 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
352 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
353 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
355 struct suffix_reloc_map
359 bfd_reloc_code_real_type reloc
;
360 unsigned char operator;
363 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
365 static struct suffix_reloc_map suffix_relocs
[] =
367 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
368 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
369 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
370 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
384 directive_literal_prefix
,
386 directive_absolute_literals
,
387 directive_last_directive
393 bfd_boolean can_be_negated
;
396 const directive_infoS directive_info
[] =
399 { "literal", FALSE
},
401 { "transform", TRUE
},
402 { "freeregs", FALSE
},
403 { "longcalls", TRUE
},
404 { "literal_prefix", FALSE
},
405 { "schedule", TRUE
},
406 { "absolute-literals", TRUE
}
409 bfd_boolean directive_state
[] =
413 #if !XCHAL_HAVE_DENSITY
418 TRUE
, /* transform */
419 FALSE
, /* freeregs */
420 FALSE
, /* longcalls */
421 FALSE
, /* literal_prefix */
422 FALSE
, /* schedule */
423 #if XSHAL_USE_ABSOLUTE_LITERALS
424 TRUE
/* absolute_literals */
426 FALSE
/* absolute_literals */
431 /* Directive functions. */
433 static void xtensa_begin_directive (int);
434 static void xtensa_end_directive (int);
435 static void xtensa_literal_prefix (void);
436 static void xtensa_literal_position (int);
437 static void xtensa_literal_pseudo (int);
438 static void xtensa_frequency_pseudo (int);
439 static void xtensa_elf_cons (int);
441 /* Parsing and Idiom Translation. */
443 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
445 /* Various Other Internal Functions. */
447 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
448 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
449 static void xtensa_mark_literal_pool_location (void);
450 static addressT
get_expanded_loop_offset (xtensa_opcode
);
451 static fragS
*get_literal_pool_location (segT
);
452 static void set_literal_pool_location (segT
, fragS
*);
453 static void xtensa_set_frag_assembly_state (fragS
*);
454 static void finish_vinsn (vliw_insn
*);
455 static bfd_boolean
emit_single_op (TInsn
*);
456 static int total_frag_text_expansion (fragS
*);
458 /* Alignment Functions. */
460 static int get_text_align_power (unsigned);
461 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
462 static int branch_align_power (segT
);
464 /* Helpers for xtensa_relax_frag(). */
466 static long relax_frag_add_nop (fragS
*);
468 /* Accessors for additional per-subsegment information. */
470 static unsigned get_last_insn_flags (segT
, subsegT
);
471 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
472 static float get_subseg_total_freq (segT
, subsegT
);
473 static float get_subseg_target_freq (segT
, subsegT
);
474 static void set_subseg_freq (segT
, subsegT
, float, float);
476 /* Segment list functions. */
478 static void xtensa_move_literals (void);
479 static void xtensa_reorder_segments (void);
480 static void xtensa_switch_to_literal_fragment (emit_state
*);
481 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
482 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
483 static void xtensa_restore_emit_state (emit_state
*);
484 static segT
cache_literal_section (bfd_boolean
);
486 /* Import from elf32-xtensa.c in BFD library. */
488 extern asection
*xtensa_get_property_section (asection
*, const char *);
490 /* op_placement_info functions. */
492 static void init_op_placement_info_table (void);
493 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
494 static int xg_get_single_size (xtensa_opcode
);
495 static xtensa_format
xg_get_single_format (xtensa_opcode
);
496 static int xg_get_single_slot (xtensa_opcode
);
498 /* TInsn and IStack functions. */
500 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
501 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
502 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
503 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
504 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
505 static void tinsn_from_chars (TInsn
*, char *, int);
506 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
507 static int get_num_stack_text_bytes (IStack
*);
508 static int get_num_stack_literal_bytes (IStack
*);
510 /* vliw_insn functions. */
512 static void xg_init_vinsn (vliw_insn
*);
513 static void xg_clear_vinsn (vliw_insn
*);
514 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
515 static void xg_free_vinsn (vliw_insn
*);
516 static bfd_boolean vinsn_to_insnbuf
517 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
518 static void vinsn_from_chars (vliw_insn
*, char *);
520 /* Expression Utilities. */
522 bfd_boolean
expr_is_const (const expressionS
*);
523 offsetT
get_expr_const (const expressionS
*);
524 void set_expr_const (expressionS
*, offsetT
);
525 bfd_boolean
expr_is_register (const expressionS
*);
526 offsetT
get_expr_register (const expressionS
*);
527 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
528 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
529 static void copy_expr (expressionS
*, const expressionS
*);
531 /* Section renaming. */
533 static void build_section_rename (const char *);
536 /* ISA imported from bfd. */
537 extern xtensa_isa xtensa_default_isa
;
539 extern int target_big_endian
;
541 static xtensa_opcode xtensa_addi_opcode
;
542 static xtensa_opcode xtensa_addmi_opcode
;
543 static xtensa_opcode xtensa_call0_opcode
;
544 static xtensa_opcode xtensa_call4_opcode
;
545 static xtensa_opcode xtensa_call8_opcode
;
546 static xtensa_opcode xtensa_call12_opcode
;
547 static xtensa_opcode xtensa_callx0_opcode
;
548 static xtensa_opcode xtensa_callx4_opcode
;
549 static xtensa_opcode xtensa_callx8_opcode
;
550 static xtensa_opcode xtensa_callx12_opcode
;
551 static xtensa_opcode xtensa_const16_opcode
;
552 static xtensa_opcode xtensa_entry_opcode
;
553 static xtensa_opcode xtensa_movi_opcode
;
554 static xtensa_opcode xtensa_movi_n_opcode
;
555 static xtensa_opcode xtensa_isync_opcode
;
556 static xtensa_opcode xtensa_jx_opcode
;
557 static xtensa_opcode xtensa_l32r_opcode
;
558 static xtensa_opcode xtensa_loop_opcode
;
559 static xtensa_opcode xtensa_loopnez_opcode
;
560 static xtensa_opcode xtensa_loopgtz_opcode
;
561 static xtensa_opcode xtensa_nop_opcode
;
562 static xtensa_opcode xtensa_nop_n_opcode
;
563 static xtensa_opcode xtensa_or_opcode
;
564 static xtensa_opcode xtensa_ret_opcode
;
565 static xtensa_opcode xtensa_ret_n_opcode
;
566 static xtensa_opcode xtensa_retw_opcode
;
567 static xtensa_opcode xtensa_retw_n_opcode
;
568 static xtensa_opcode xtensa_rsr_lcount_opcode
;
569 static xtensa_opcode xtensa_waiti_opcode
;
572 /* Command-line Options. */
574 bfd_boolean use_literal_section
= TRUE
;
575 static bfd_boolean align_targets
= TRUE
;
576 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
577 static bfd_boolean has_a0_b_retw
= FALSE
;
578 static bfd_boolean workaround_a0_b_retw
= FALSE
;
579 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
580 static bfd_boolean workaround_short_loop
= FALSE
;
581 static bfd_boolean maybe_has_short_loop
= FALSE
;
582 static bfd_boolean workaround_close_loop_end
= FALSE
;
583 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
584 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
586 /* When workaround_short_loops is TRUE, all loops with early exits must
587 have at least 3 instructions. workaround_all_short_loops is a modifier
588 to the workaround_short_loop flag. In addition to the
589 workaround_short_loop actions, all straightline loopgtz and loopnez
590 must have at least 3 instructions. */
592 static bfd_boolean workaround_all_short_loops
= FALSE
;
596 xtensa_setup_hw_workarounds (int earliest
, int latest
)
598 if (earliest
> latest
)
599 as_fatal (_("illegal range of target hardware versions"));
601 /* Enable all workarounds for pre-T1050.0 hardware. */
602 if (earliest
< 105000 || latest
< 105000)
604 workaround_a0_b_retw
|= TRUE
;
605 workaround_b_j_loop_end
|= TRUE
;
606 workaround_short_loop
|= TRUE
;
607 workaround_close_loop_end
|= TRUE
;
608 workaround_all_short_loops
|= TRUE
;
609 enforce_three_byte_loop_align
= TRUE
;
616 option_density
= OPTION_MD_BASE
,
623 option_no_link_relax
,
631 option_text_section_literals
,
632 option_no_text_section_literals
,
634 option_absolute_literals
,
635 option_no_absolute_literals
,
637 option_align_targets
,
638 option_no_align_targets
,
640 option_warn_unaligned_targets
,
645 option_workaround_a0_b_retw
,
646 option_no_workaround_a0_b_retw
,
648 option_workaround_b_j_loop_end
,
649 option_no_workaround_b_j_loop_end
,
651 option_workaround_short_loop
,
652 option_no_workaround_short_loop
,
654 option_workaround_all_short_loops
,
655 option_no_workaround_all_short_loops
,
657 option_workaround_close_loop_end
,
658 option_no_workaround_close_loop_end
,
660 option_no_workarounds
,
662 option_rename_section_name
,
665 option_prefer_const16
,
667 option_target_hardware
670 const char *md_shortopts
= "";
672 struct option md_longopts
[] =
674 { "density", no_argument
, NULL
, option_density
},
675 { "no-density", no_argument
, NULL
, option_no_density
},
677 /* Both "relax" and "generics" are deprecated and treated as equivalent
678 to the "transform" option. */
679 { "relax", no_argument
, NULL
, option_relax
},
680 { "no-relax", no_argument
, NULL
, option_no_relax
},
681 { "generics", no_argument
, NULL
, option_generics
},
682 { "no-generics", no_argument
, NULL
, option_no_generics
},
684 { "transform", no_argument
, NULL
, option_transform
},
685 { "no-transform", no_argument
, NULL
, option_no_transform
},
686 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
687 { "no-text-section-literals", no_argument
, NULL
,
688 option_no_text_section_literals
},
689 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
690 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
691 /* This option was changed from -align-target to -target-align
692 because it conflicted with the "-al" option. */
693 { "target-align", no_argument
, NULL
, option_align_targets
},
694 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
695 { "warn-unaligned-targets", no_argument
, NULL
,
696 option_warn_unaligned_targets
},
697 { "longcalls", no_argument
, NULL
, option_longcalls
},
698 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
700 { "no-workaround-a0-b-retw", no_argument
, NULL
,
701 option_no_workaround_a0_b_retw
},
702 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
704 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
705 option_no_workaround_b_j_loop_end
},
706 { "workaround-b-j-loop-end", no_argument
, NULL
,
707 option_workaround_b_j_loop_end
},
709 { "no-workaround-short-loops", no_argument
, NULL
,
710 option_no_workaround_short_loop
},
711 { "workaround-short-loops", no_argument
, NULL
,
712 option_workaround_short_loop
},
714 { "no-workaround-all-short-loops", no_argument
, NULL
,
715 option_no_workaround_all_short_loops
},
716 { "workaround-all-short-loop", no_argument
, NULL
,
717 option_workaround_all_short_loops
},
719 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
720 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
722 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
724 { "no-workaround-close-loop-end", no_argument
, NULL
,
725 option_no_workaround_close_loop_end
},
726 { "workaround-close-loop-end", no_argument
, NULL
,
727 option_workaround_close_loop_end
},
729 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
731 { "link-relax", no_argument
, NULL
, option_link_relax
},
732 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
734 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
736 { NULL
, no_argument
, NULL
, 0 }
739 size_t md_longopts_size
= sizeof md_longopts
;
743 md_parse_option (int c
, char *arg
)
748 as_warn (_("--density option is ignored"));
750 case option_no_density
:
751 as_warn (_("--no-density option is ignored"));
753 case option_link_relax
:
756 case option_no_link_relax
:
759 case option_generics
:
760 as_warn (_("--generics is deprecated; use --transform instead"));
761 return md_parse_option (option_transform
, arg
);
762 case option_no_generics
:
763 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
764 return md_parse_option (option_no_transform
, arg
);
766 as_warn (_("--relax is deprecated; use --transform instead"));
767 return md_parse_option (option_transform
, arg
);
768 case option_no_relax
:
769 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
770 return md_parse_option (option_no_transform
, arg
);
771 case option_longcalls
:
772 directive_state
[directive_longcalls
] = TRUE
;
774 case option_no_longcalls
:
775 directive_state
[directive_longcalls
] = FALSE
;
777 case option_text_section_literals
:
778 use_literal_section
= FALSE
;
780 case option_no_text_section_literals
:
781 use_literal_section
= TRUE
;
783 case option_absolute_literals
:
784 if (!absolute_literals_supported
)
786 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
789 directive_state
[directive_absolute_literals
] = TRUE
;
791 case option_no_absolute_literals
:
792 directive_state
[directive_absolute_literals
] = FALSE
;
795 case option_workaround_a0_b_retw
:
796 workaround_a0_b_retw
= TRUE
;
798 case option_no_workaround_a0_b_retw
:
799 workaround_a0_b_retw
= FALSE
;
801 case option_workaround_b_j_loop_end
:
802 workaround_b_j_loop_end
= TRUE
;
804 case option_no_workaround_b_j_loop_end
:
805 workaround_b_j_loop_end
= FALSE
;
808 case option_workaround_short_loop
:
809 workaround_short_loop
= TRUE
;
811 case option_no_workaround_short_loop
:
812 workaround_short_loop
= FALSE
;
815 case option_workaround_all_short_loops
:
816 workaround_all_short_loops
= TRUE
;
818 case option_no_workaround_all_short_loops
:
819 workaround_all_short_loops
= FALSE
;
822 case option_workaround_close_loop_end
:
823 workaround_close_loop_end
= TRUE
;
825 case option_no_workaround_close_loop_end
:
826 workaround_close_loop_end
= FALSE
;
829 case option_no_workarounds
:
830 workaround_a0_b_retw
= FALSE
;
831 workaround_b_j_loop_end
= FALSE
;
832 workaround_short_loop
= FALSE
;
833 workaround_all_short_loops
= FALSE
;
834 workaround_close_loop_end
= FALSE
;
837 case option_align_targets
:
838 align_targets
= TRUE
;
840 case option_no_align_targets
:
841 align_targets
= FALSE
;
844 case option_warn_unaligned_targets
:
845 warn_unaligned_branch_targets
= TRUE
;
848 case option_rename_section_name
:
849 build_section_rename (arg
);
853 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
854 should be emitted or not. FIXME: Not implemented. */
857 case option_prefer_l32r
:
859 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
863 case option_prefer_const16
:
865 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
869 case option_target_hardware
:
871 int earliest
, latest
= 0;
872 if (*arg
== 0 || *arg
== '-')
873 as_fatal (_("invalid target hardware version"));
875 earliest
= strtol (arg
, &arg
, 0);
879 else if (*arg
== '-')
882 as_fatal (_("invalid target hardware version"));
883 latest
= strtol (arg
, &arg
, 0);
886 as_fatal (_("invalid target hardware version"));
888 xtensa_setup_hw_workarounds (earliest
, latest
);
892 case option_transform
:
893 /* This option has no affect other than to use the defaults,
894 which are already set. */
897 case option_no_transform
:
898 /* This option turns off all transformations of any kind.
899 However, because we want to preserve the state of other
900 directives, we only change its own field. Thus, before
901 you perform any transformation, always check if transform
902 is available. If you use the functions we provide for this
903 purpose, you will be ok. */
904 directive_state
[directive_transform
] = FALSE
;
914 md_show_usage (FILE *stream
)
918 --[no-]text-section-literals\n\
919 [Do not] put literals in the text section\n\
920 --[no-]absolute-literals\n\
921 [Do not] default to use non-PC-relative literals\n\
922 --[no-]target-align [Do not] try to align branch targets\n\
923 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
924 --[no-]transform [Do not] transform instructions\n\
925 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
929 /* Functions related to the list of current label symbols. */
932 xtensa_add_insn_label (symbolS
*sym
)
936 if (!free_insn_labels
)
937 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
940 l
= free_insn_labels
;
941 free_insn_labels
= l
->next
;
945 l
->next
= insn_labels
;
951 xtensa_clear_insn_labels (void)
955 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
962 /* The "loops_ok" argument is provided to allow ignoring labels that
963 define loop ends. This fixes a bug where the NOPs to align a
964 loop opcode were included in a previous zero-cost loop:
983 This argument is used to prevent moving the NOP to before the
984 loop-end label, which is what you want in this special case. */
987 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
991 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
993 symbolS
*lit_sym
= lit
->sym
;
994 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
996 S_SET_VALUE (lit_sym
, new_offset
);
997 symbol_set_frag (lit_sym
, new_frag
);
1003 /* Directive data and functions. */
1005 typedef struct state_stackS_struct
1007 directiveE directive
;
1008 bfd_boolean negated
;
1009 bfd_boolean old_state
;
1013 struct state_stackS_struct
*prev
;
1016 state_stackS
*directive_state_stack
;
1018 const pseudo_typeS md_pseudo_table
[] =
1020 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1021 { "literal_position", xtensa_literal_position
, 0 },
1022 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1023 { "long", xtensa_elf_cons
, 4 },
1024 { "word", xtensa_elf_cons
, 4 },
1025 { "short", xtensa_elf_cons
, 2 },
1026 { "begin", xtensa_begin_directive
, 0 },
1027 { "end", xtensa_end_directive
, 0 },
1028 { "literal", xtensa_literal_pseudo
, 0 },
1029 { "frequency", xtensa_frequency_pseudo
, 0 },
1035 use_transform (void)
1037 /* After md_end, you should be checking frag by frag, rather
1038 than state directives. */
1039 assert (!past_xtensa_end
);
1040 return directive_state
[directive_transform
];
1045 do_align_targets (void)
1047 /* Do not use this function after md_end; just look at align_targets
1048 instead. There is no target-align directive, so alignment is either
1049 enabled for all frags or not done at all. */
1050 assert (!past_xtensa_end
);
1051 return align_targets
&& use_transform ();
1056 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1060 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1062 as_where (&file
, &line
);
1064 stack
->directive
= directive
;
1065 stack
->negated
= negated
;
1066 stack
->old_state
= directive_state
[directive
];
1069 stack
->datum
= datum
;
1070 stack
->prev
= directive_state_stack
;
1071 directive_state_stack
= stack
;
1073 directive_state
[directive
] = !negated
;
1078 directive_pop (directiveE
*directive
,
1079 bfd_boolean
*negated
,
1084 state_stackS
*top
= directive_state_stack
;
1086 if (!directive_state_stack
)
1088 as_bad (_("unmatched end directive"));
1089 *directive
= directive_none
;
1093 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1094 *directive
= top
->directive
;
1095 *negated
= top
->negated
;
1098 *datum
= top
->datum
;
1099 directive_state_stack
= top
->prev
;
1105 directive_balance (void)
1107 while (directive_state_stack
)
1109 directiveE directive
;
1110 bfd_boolean negated
;
1115 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1116 as_warn_where ((char *) file
, line
,
1117 _(".begin directive with no matching .end directive"));
1123 inside_directive (directiveE dir
)
1125 state_stackS
*top
= directive_state_stack
;
1127 while (top
&& top
->directive
!= dir
)
1130 return (top
!= NULL
);
1135 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1139 char *directive_string
;
1141 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1146 input_line_pointer
+= 3;
1149 len
= strspn (input_line_pointer
,
1150 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1152 /* This code is a hack to make .begin [no-][generics|relax] exactly
1153 equivalent to .begin [no-]transform. We should remove it when
1154 we stop accepting those options. */
1156 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1158 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1159 directive_string
= "transform";
1161 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1163 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1164 directive_string
= "transform";
1167 directive_string
= input_line_pointer
;
1169 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1171 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1173 input_line_pointer
+= len
;
1174 *directive
= (directiveE
) i
;
1175 if (*negated
&& !directive_info
[i
].can_be_negated
)
1176 as_bad (_("directive %s cannot be negated"),
1177 directive_info
[i
].name
);
1182 as_bad (_("unknown directive"));
1183 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1188 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1190 directiveE directive
;
1191 bfd_boolean negated
;
1195 get_directive (&directive
, &negated
);
1196 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1198 discard_rest_of_line ();
1202 if (cur_vinsn
.inside_bundle
)
1203 as_bad (_("directives are not valid inside bundles"));
1207 case directive_literal
:
1208 if (!inside_directive (directive_literal
))
1210 /* Previous labels go with whatever follows this directive, not with
1211 the literal, so save them now. */
1212 saved_insn_labels
= insn_labels
;
1215 as_warn (_(".begin literal is deprecated; use .literal instead"));
1216 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1217 xtensa_switch_to_literal_fragment (state
);
1218 directive_push (directive_literal
, negated
, state
);
1221 case directive_literal_prefix
:
1222 /* Have to flush pending output because a movi relaxed to an l32r
1223 might produce a literal. */
1224 md_flush_pending_output ();
1225 /* Check to see if the current fragment is a literal
1226 fragment. If it is, then this operation is not allowed. */
1227 if (generating_literals
)
1229 as_bad (_("cannot set literal_prefix inside literal fragment"));
1233 /* Allocate the literal state for this section and push
1234 onto the directive stack. */
1235 ls
= xmalloc (sizeof (lit_state
));
1238 *ls
= default_lit_sections
;
1239 directive_push (directive_literal_prefix
, negated
, ls
);
1241 /* Process the new prefix. */
1242 xtensa_literal_prefix ();
1245 case directive_freeregs
:
1246 /* This information is currently unused, but we'll accept the statement
1247 and just discard the rest of the line. This won't check the syntax,
1248 but it will accept every correct freeregs directive. */
1249 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1250 directive_push (directive_freeregs
, negated
, 0);
1253 case directive_schedule
:
1254 md_flush_pending_output ();
1255 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1256 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1257 directive_push (directive_schedule
, negated
, 0);
1258 xtensa_set_frag_assembly_state (frag_now
);
1261 case directive_density
:
1262 as_warn (_(".begin [no-]density is ignored"));
1265 case directive_absolute_literals
:
1266 md_flush_pending_output ();
1267 if (!absolute_literals_supported
&& !negated
)
1269 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1272 xtensa_set_frag_assembly_state (frag_now
);
1273 directive_push (directive
, negated
, 0);
1277 md_flush_pending_output ();
1278 xtensa_set_frag_assembly_state (frag_now
);
1279 directive_push (directive
, negated
, 0);
1283 demand_empty_rest_of_line ();
1288 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1290 directiveE begin_directive
, end_directive
;
1291 bfd_boolean begin_negated
, end_negated
;
1295 emit_state
**state_ptr
;
1298 if (cur_vinsn
.inside_bundle
)
1299 as_bad (_("directives are not valid inside bundles"));
1301 get_directive (&end_directive
, &end_negated
);
1303 md_flush_pending_output ();
1305 switch (end_directive
)
1307 case (directiveE
) XTENSA_UNDEFINED
:
1308 discard_rest_of_line ();
1311 case directive_density
:
1312 as_warn (_(".end [no-]density is ignored"));
1313 demand_empty_rest_of_line ();
1316 case directive_absolute_literals
:
1317 if (!absolute_literals_supported
&& !end_negated
)
1319 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1320 demand_empty_rest_of_line ();
1329 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1330 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1331 (const void **) state_ptr
);
1333 if (begin_directive
!= directive_none
)
1335 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1337 as_bad (_("does not match begin %s%s at %s:%d"),
1338 begin_negated
? "no-" : "",
1339 directive_info
[begin_directive
].name
, file
, line
);
1343 switch (end_directive
)
1345 case directive_literal
:
1346 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1347 xtensa_restore_emit_state (state
);
1348 xtensa_set_frag_assembly_state (frag_now
);
1350 if (!inside_directive (directive_literal
))
1352 /* Restore the list of current labels. */
1353 xtensa_clear_insn_labels ();
1354 insn_labels
= saved_insn_labels
;
1358 case directive_literal_prefix
:
1359 /* Restore the default collection sections from saved state. */
1360 s
= (lit_state
*) state
;
1362 default_lit_sections
= *s
;
1364 /* Free the state storage. */
1365 free (s
->lit_prefix
);
1369 case directive_schedule
:
1370 case directive_freeregs
:
1374 xtensa_set_frag_assembly_state (frag_now
);
1380 demand_empty_rest_of_line ();
1384 /* Place an aligned literal fragment at the current location. */
1387 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1389 md_flush_pending_output ();
1391 if (inside_directive (directive_literal
))
1392 as_warn (_(".literal_position inside literal directive; ignoring"));
1393 xtensa_mark_literal_pool_location ();
1395 demand_empty_rest_of_line ();
1396 xtensa_clear_insn_labels ();
1400 /* Support .literal label, expr, ... */
1403 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1406 char *p
, *base_name
;
1410 if (inside_directive (directive_literal
))
1412 as_bad (_(".literal not allowed inside .begin literal region"));
1413 ignore_rest_of_line ();
1417 md_flush_pending_output ();
1419 /* Previous labels go with whatever follows this directive, not with
1420 the literal, so save them now. */
1421 saved_insn_labels
= insn_labels
;
1424 /* If we are using text-section literals, then this is the right value... */
1427 base_name
= input_line_pointer
;
1429 xtensa_switch_to_literal_fragment (&state
);
1431 /* ...but if we aren't using text-section-literals, then we
1432 need to put them in the section we just switched to. */
1433 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1436 /* All literals are aligned to four-byte boundaries. */
1437 frag_align (2, 0, 0);
1438 record_alignment (now_seg
, 2);
1440 c
= get_symbol_end ();
1441 /* Just after name is now '\0'. */
1442 p
= input_line_pointer
;
1446 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1448 as_bad (_("expected comma or colon after symbol name; "
1449 "rest of line ignored"));
1450 ignore_rest_of_line ();
1451 xtensa_restore_emit_state (&state
);
1459 input_line_pointer
++; /* skip ',' or ':' */
1461 xtensa_elf_cons (4);
1463 xtensa_restore_emit_state (&state
);
1465 /* Restore the list of current labels. */
1466 xtensa_clear_insn_labels ();
1467 insn_labels
= saved_insn_labels
;
1472 xtensa_literal_prefix (void)
1477 /* Parse the new prefix from the input_line_pointer. */
1479 len
= strspn (input_line_pointer
,
1480 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1481 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1483 /* Get a null-terminated copy of the name. */
1484 name
= xmalloc (len
+ 1);
1486 strncpy (name
, input_line_pointer
, len
);
1489 /* Skip the name in the input line. */
1490 input_line_pointer
+= len
;
1492 default_lit_sections
.lit_prefix
= name
;
1494 /* Clear cached literal sections, since the prefix has changed. */
1495 default_lit_sections
.lit_seg
= NULL
;
1496 default_lit_sections
.lit4_seg
= NULL
;
1500 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1503 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1505 float fall_through_f
, target_f
;
1507 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1508 if (fall_through_f
< 0)
1510 as_bad (_("fall through frequency must be greater than 0"));
1511 ignore_rest_of_line ();
1515 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1518 as_bad (_("branch target frequency must be greater than 0"));
1519 ignore_rest_of_line ();
1523 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1525 demand_empty_rest_of_line ();
1529 /* Like normal .long/.short/.word, except support @plt, etc.
1530 Clobbers input_line_pointer, checks end-of-line. */
1533 xtensa_elf_cons (int nbytes
)
1536 bfd_reloc_code_real_type reloc
;
1538 md_flush_pending_output ();
1540 if (cur_vinsn
.inside_bundle
)
1541 as_bad (_("directives are not valid inside bundles"));
1543 if (is_it_end_of_statement ())
1545 demand_empty_rest_of_line ();
1552 if (exp
.X_op
== O_symbol
1553 && *input_line_pointer
== '@'
1554 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1557 reloc_howto_type
*reloc_howto
=
1558 bfd_reloc_type_lookup (stdoutput
, reloc
);
1560 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1561 as_bad (_("unsupported relocation"));
1562 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1563 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1564 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1565 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1566 as_bad (_("opcode-specific %s relocation used outside "
1567 "an instruction"), reloc_howto
->name
);
1568 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1569 as_bad (_("%s relocations do not fit in %d bytes"),
1570 reloc_howto
->name
, nbytes
);
1573 char *p
= frag_more ((int) nbytes
);
1574 xtensa_set_frag_assembly_state (frag_now
);
1575 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1576 nbytes
, &exp
, 0, reloc
);
1580 emit_expr (&exp
, (unsigned int) nbytes
);
1582 while (*input_line_pointer
++ == ',');
1584 input_line_pointer
--; /* Put terminator back into stream. */
1585 demand_empty_rest_of_line ();
1589 /* Parsing and Idiom Translation. */
1591 /* Parse @plt, etc. and return the desired relocation. */
1592 static bfd_reloc_code_real_type
1593 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1600 struct suffix_reloc_map
*ptr
;
1603 return BFD_RELOC_NONE
;
1605 for (ch
= *str
, str2
= ident
;
1606 (str2
< ident
+ sizeof (ident
) - 1
1607 && (ISALNUM (ch
) || ch
== '@'));
1610 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1617 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1618 if (ch
== ptr
->suffix
[0]
1619 && len
== ptr
->length
1620 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1622 /* Now check for "identifier@suffix+constant". */
1623 if (*str
== '-' || *str
== '+')
1625 char *orig_line
= input_line_pointer
;
1626 expressionS new_exp
;
1628 input_line_pointer
= str
;
1629 expression (&new_exp
);
1630 if (new_exp
.X_op
== O_constant
)
1632 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1633 str
= input_line_pointer
;
1636 if (&input_line_pointer
!= str_p
)
1637 input_line_pointer
= orig_line
;
1644 return BFD_RELOC_UNUSED
;
1648 /* Find the matching operator type. */
1649 static unsigned char
1650 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1652 struct suffix_reloc_map
*sfx
;
1653 unsigned char operator = (unsigned char) -1;
1655 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1657 if (sfx
->reloc
== reloc
)
1659 operator = sfx
->operator;
1663 assert (operator != (unsigned char) -1);
1668 /* Find the matching reloc type. */
1669 static bfd_reloc_code_real_type
1670 map_operator_to_reloc (unsigned char operator)
1672 struct suffix_reloc_map
*sfx
;
1673 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1675 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1677 if (sfx
->operator == operator)
1684 if (reloc
== BFD_RELOC_UNUSED
)
1685 return BFD_RELOC_32
;
1692 expression_end (const char *name
)
1715 #define ERROR_REG_NUM ((unsigned) -1)
1718 tc_get_register (const char *prefix
)
1721 const char *next_expr
;
1722 const char *old_line_pointer
;
1725 old_line_pointer
= input_line_pointer
;
1727 if (*input_line_pointer
== '$')
1728 ++input_line_pointer
;
1730 /* Accept "sp" as a synonym for "a1". */
1731 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1732 && expression_end (input_line_pointer
+ 2))
1734 input_line_pointer
+= 2;
1735 return 1; /* AR[1] */
1738 while (*input_line_pointer
++ == *prefix
++)
1740 --input_line_pointer
;
1745 as_bad (_("bad register name: %s"), old_line_pointer
);
1746 return ERROR_REG_NUM
;
1749 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1751 as_bad (_("bad register number: %s"), input_line_pointer
);
1752 return ERROR_REG_NUM
;
1757 while (ISDIGIT ((int) *input_line_pointer
))
1758 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1760 if (!(next_expr
= expression_end (input_line_pointer
)))
1762 as_bad (_("bad register name: %s"), old_line_pointer
);
1763 return ERROR_REG_NUM
;
1766 input_line_pointer
= (char *) next_expr
;
1773 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1775 xtensa_isa isa
= xtensa_default_isa
;
1777 /* Check if this is an immediate operand. */
1778 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1780 bfd_reloc_code_real_type reloc
;
1781 segT t
= expression (tok
);
1782 if (t
== absolute_section
1783 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1785 assert (tok
->X_op
== O_constant
);
1786 tok
->X_op
= O_symbol
;
1787 tok
->X_add_symbol
= &abs_symbol
;
1790 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1791 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1794 if (reloc
== BFD_RELOC_UNUSED
)
1796 as_bad (_("unsupported relocation"));
1800 if (tok
->X_op
== O_constant
)
1804 case BFD_RELOC_LO16
:
1805 tok
->X_add_number
&= 0xffff;
1808 case BFD_RELOC_HI16
:
1809 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1816 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1821 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1822 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1824 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1827 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1828 as_bad (_("register number out of range"));
1831 tok
->X_op
= O_register
;
1832 tok
->X_add_symbol
= 0;
1833 tok
->X_add_number
= reg
;
1838 /* Split up the arguments for an opcode or pseudo-op. */
1841 tokenize_arguments (char **args
, char *str
)
1843 char *old_input_line_pointer
;
1844 bfd_boolean saw_comma
= FALSE
;
1845 bfd_boolean saw_arg
= FALSE
;
1846 bfd_boolean saw_colon
= FALSE
;
1848 char *arg_end
, *arg
;
1851 /* Save and restore input_line_pointer around this function. */
1852 old_input_line_pointer
= input_line_pointer
;
1853 input_line_pointer
= str
;
1855 while (*input_line_pointer
)
1858 switch (*input_line_pointer
)
1865 input_line_pointer
++;
1866 if (saw_comma
|| saw_colon
|| !saw_arg
)
1872 input_line_pointer
++;
1873 if (saw_comma
|| saw_colon
|| !saw_arg
)
1879 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1882 arg_end
= input_line_pointer
+ 1;
1883 while (!expression_end (arg_end
))
1886 arg_len
= arg_end
- input_line_pointer
;
1887 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1888 args
[num_args
] = arg
;
1892 strncpy (arg
, input_line_pointer
, arg_len
);
1893 arg
[arg_len
] = '\0';
1895 input_line_pointer
= arg_end
;
1905 if (saw_comma
|| saw_colon
)
1907 input_line_pointer
= old_input_line_pointer
;
1912 as_bad (_("extra comma"));
1914 as_bad (_("extra colon"));
1916 as_bad (_("missing argument"));
1918 as_bad (_("missing comma or colon"));
1919 input_line_pointer
= old_input_line_pointer
;
1924 /* Parse the arguments to an opcode. Return TRUE on error. */
1927 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1929 expressionS
*tok
, *last_tok
;
1930 xtensa_opcode opcode
= insn
->opcode
;
1931 bfd_boolean had_error
= TRUE
;
1932 xtensa_isa isa
= xtensa_default_isa
;
1933 int n
, num_regs
= 0;
1934 int opcode_operand_count
;
1935 int opnd_cnt
, last_opnd_cnt
;
1936 unsigned int next_reg
= 0;
1937 char *old_input_line_pointer
;
1939 if (insn
->insn_type
== ITYPE_LITERAL
)
1940 opcode_operand_count
= 1;
1942 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1945 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1947 /* Save and restore input_line_pointer around this function. */
1948 old_input_line_pointer
= input_line_pointer
;
1954 /* Skip invisible operands. */
1955 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1961 for (n
= 0; n
< num_args
; n
++)
1963 input_line_pointer
= arg_strings
[n
];
1964 if (*input_line_pointer
== ':')
1966 xtensa_regfile opnd_rf
;
1967 input_line_pointer
++;
1970 assert (opnd_cnt
> 0);
1972 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1974 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1975 as_warn (_("incorrect register number, ignoring"));
1980 if (opnd_cnt
>= opcode_operand_count
)
1982 as_warn (_("too many arguments"));
1985 assert (opnd_cnt
< MAX_INSN_ARGS
);
1987 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1988 next_reg
= tok
->X_add_number
+ 1;
1990 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1992 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1994 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1995 /* minus 1 because we are seeing one right now */
2001 last_opnd_cnt
= opnd_cnt
;
2008 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2012 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2015 insn
->ntok
= tok
- insn
->tok
;
2019 input_line_pointer
= old_input_line_pointer
;
2025 get_invisible_operands (TInsn
*insn
)
2027 xtensa_isa isa
= xtensa_default_isa
;
2028 static xtensa_insnbuf slotbuf
= NULL
;
2030 xtensa_opcode opc
= insn
->opcode
;
2031 int slot
, opnd
, fmt_found
;
2035 slotbuf
= xtensa_insnbuf_alloc (isa
);
2037 /* Find format/slot where this can be encoded. */
2040 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2042 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2044 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2050 if (fmt_found
) break;
2055 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2059 /* First encode all the visible operands
2060 (to deal with shared field operands). */
2061 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2063 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2064 && (insn
->tok
[opnd
].X_op
== O_register
2065 || insn
->tok
[opnd
].X_op
== O_constant
))
2067 val
= insn
->tok
[opnd
].X_add_number
;
2068 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2069 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2073 /* Then pull out the values for the invisible ones. */
2074 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2076 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2078 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2079 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2080 insn
->tok
[opnd
].X_add_number
= val
;
2081 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2082 insn
->tok
[opnd
].X_op
= O_register
;
2084 insn
->tok
[opnd
].X_op
= O_constant
;
2093 xg_reverse_shift_count (char **cnt_argp
)
2095 char *cnt_arg
, *new_arg
;
2096 cnt_arg
= *cnt_argp
;
2098 /* replace the argument with "31-(argument)" */
2099 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2100 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2103 *cnt_argp
= new_arg
;
2107 /* If "arg" is a constant expression, return non-zero with the value
2111 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2114 char *save_ptr
= input_line_pointer
;
2116 input_line_pointer
= arg
;
2118 input_line_pointer
= save_ptr
;
2120 if (exp
.X_op
== O_constant
)
2122 *valp
= exp
.X_add_number
;
2131 xg_replace_opname (char **popname
, char *newop
)
2134 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2135 strcpy (*popname
, newop
);
2140 xg_check_num_args (int *pnum_args
,
2145 int num_args
= *pnum_args
;
2147 if (num_args
< expected_num
)
2149 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2150 num_args
, opname
, expected_num
);
2154 if (num_args
> expected_num
)
2156 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2157 num_args
, opname
, expected_num
);
2158 while (num_args
-- > expected_num
)
2160 free (arg_strings
[num_args
]);
2161 arg_strings
[num_args
] = 0;
2163 *pnum_args
= expected_num
;
2171 /* If the register is not specified as part of the opcode,
2172 then get it from the operand and move it to the opcode. */
2175 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2177 xtensa_isa isa
= xtensa_default_isa
;
2179 char *opname
, *new_opname
;
2180 const char *sr_name
;
2181 int is_user
, is_write
;
2186 is_user
= (opname
[1] == 'u');
2187 is_write
= (opname
[0] == 'w');
2189 /* Opname == [rw]ur or [rwx]sr... */
2191 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2194 /* Check if the argument is a symbolic register name. */
2195 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2196 /* Handle WSR to "INTSET" as a special case. */
2197 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2198 && !strcasecmp (arg_strings
[1], "intset"))
2199 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2200 if (sr
== XTENSA_UNDEFINED
2201 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2203 /* Maybe it's a register number.... */
2205 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2207 as_bad (_("invalid register '%s' for '%s' instruction"),
2208 arg_strings
[1], opname
);
2211 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2212 if (sr
== XTENSA_UNDEFINED
)
2214 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2215 (long) val
, opname
);
2220 /* Remove the last argument, which is now part of the opcode. */
2221 free (arg_strings
[1]);
2225 /* Translate the opcode. */
2226 sr_name
= xtensa_sysreg_name (isa
, sr
);
2227 /* Another special case for "WSR.INTSET".... */
2228 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2230 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2231 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2233 *popname
= new_opname
;
2240 xtensa_translate_old_userreg_ops (char **popname
)
2242 xtensa_isa isa
= xtensa_default_isa
;
2244 char *opname
, *new_opname
;
2245 const char *sr_name
;
2246 bfd_boolean has_underbar
= FALSE
;
2249 if (opname
[0] == '_')
2251 has_underbar
= TRUE
;
2255 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2256 if (sr
!= XTENSA_UNDEFINED
)
2258 /* The new default name ("nnn") is different from the old default
2259 name ("URnnn"). The old default is handled below, and we don't
2260 want to recognize [RW]nnn, so do nothing if the name is the (new)
2262 static char namebuf
[10];
2263 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2264 if (strcmp (namebuf
, opname
+ 1) == 0)
2272 /* Only continue if the reg name is "URnnn". */
2273 if (opname
[1] != 'u' || opname
[2] != 'r')
2275 val
= strtoul (opname
+ 3, &end
, 10);
2279 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2280 if (sr
== XTENSA_UNDEFINED
)
2282 as_bad (_("invalid register number (%ld) for '%s'"),
2283 (long) val
, opname
);
2288 /* Translate the opcode. */
2289 sr_name
= xtensa_sysreg_name (isa
, sr
);
2290 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2291 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2292 opname
[0], sr_name
);
2294 *popname
= new_opname
;
2301 xtensa_translate_zero_immed (char *old_op
,
2311 assert (opname
[0] != '_');
2313 if (strcmp (opname
, old_op
) != 0)
2316 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2318 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2320 xg_replace_opname (popname
, new_op
);
2321 free (arg_strings
[1]);
2322 arg_strings
[1] = arg_strings
[2];
2331 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2332 Returns non-zero if an error was found. */
2335 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2337 char *opname
= *popname
;
2338 bfd_boolean has_underbar
= FALSE
;
2340 if (cur_vinsn
.inside_bundle
)
2345 has_underbar
= TRUE
;
2349 if (strcmp (opname
, "mov") == 0)
2351 if (use_transform () && !has_underbar
&& density_supported
)
2352 xg_replace_opname (popname
, "mov.n");
2355 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2357 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2358 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2359 strcpy (arg_strings
[2], arg_strings
[1]);
2365 if (strcmp (opname
, "bbsi.l") == 0)
2367 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2369 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2370 if (target_big_endian
)
2371 xg_reverse_shift_count (&arg_strings
[1]);
2375 if (strcmp (opname
, "bbci.l") == 0)
2377 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2379 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2380 if (target_big_endian
)
2381 xg_reverse_shift_count (&arg_strings
[1]);
2385 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2386 && strcmp (opname
, "nop") == 0)
2388 if (use_transform () && !has_underbar
&& density_supported
)
2389 xg_replace_opname (popname
, "nop.n");
2392 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2394 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2395 arg_strings
[0] = (char *) xmalloc (3);
2396 arg_strings
[1] = (char *) xmalloc (3);
2397 arg_strings
[2] = (char *) xmalloc (3);
2398 strcpy (arg_strings
[0], "a1");
2399 strcpy (arg_strings
[1], "a1");
2400 strcpy (arg_strings
[2], "a1");
2406 /* Recognize [RW]UR and [RWX]SR. */
2407 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2408 && (opname
[1] == 'u' || opname
[1] == 's'))
2409 || (opname
[0] == 'x' && opname
[1] == 's'))
2411 && opname
[3] == '\0')
2412 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2414 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2415 [RW]<name> if <name> is the non-default name of a user register. */
2416 if ((opname
[0] == 'r' || opname
[0] == 'w')
2417 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2418 return xtensa_translate_old_userreg_ops (popname
);
2420 /* Relax branches that don't allow comparisons against an immediate value
2421 of zero to the corresponding branches with implicit zero immediates. */
2422 if (!has_underbar
&& use_transform ())
2424 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2425 pnum_args
, arg_strings
))
2428 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2429 pnum_args
, arg_strings
))
2432 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2433 pnum_args
, arg_strings
))
2436 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2437 pnum_args
, arg_strings
))
2445 /* Functions for dealing with the Xtensa ISA. */
2447 /* Currently the assembler only allows us to use a single target per
2448 fragment. Because of this, only one operand for a given
2449 instruction may be symbolic. If there is a PC-relative operand,
2450 the last one is chosen. Otherwise, the result is the number of the
2451 last immediate operand, and if there are none of those, we fail and
2455 get_relaxable_immed (xtensa_opcode opcode
)
2457 int last_immed
= -1;
2460 if (opcode
== XTENSA_UNDEFINED
)
2463 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2464 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2466 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2468 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2470 if (last_immed
== -1
2471 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2478 static xtensa_opcode
2479 get_opcode_from_buf (const char *buf
, int slot
)
2481 static xtensa_insnbuf insnbuf
= NULL
;
2482 static xtensa_insnbuf slotbuf
= NULL
;
2483 xtensa_isa isa
= xtensa_default_isa
;
2488 insnbuf
= xtensa_insnbuf_alloc (isa
);
2489 slotbuf
= xtensa_insnbuf_alloc (isa
);
2492 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2493 fmt
= xtensa_format_decode (isa
, insnbuf
);
2494 if (fmt
== XTENSA_UNDEFINED
)
2495 return XTENSA_UNDEFINED
;
2497 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2498 return XTENSA_UNDEFINED
;
2500 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2501 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2505 #ifdef TENSILICA_DEBUG
2507 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2510 xtensa_print_insn_table (void)
2512 int num_opcodes
, num_operands
;
2513 xtensa_opcode opcode
;
2514 xtensa_isa isa
= xtensa_default_isa
;
2516 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2517 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2520 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2521 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2522 for (opn
= 0; opn
< num_operands
; opn
++)
2524 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2526 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2528 xtensa_regfile opnd_rf
=
2529 xtensa_operand_regfile (isa
, opcode
, opn
);
2530 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2532 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2533 fputs ("[lLr] ", stderr
);
2535 fputs ("i ", stderr
);
2537 fprintf (stderr
, "\n");
2543 print_vliw_insn (xtensa_insnbuf vbuf
)
2545 xtensa_isa isa
= xtensa_default_isa
;
2546 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2547 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2550 fprintf (stderr
, "format = %d\n", f
);
2552 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2554 xtensa_opcode opcode
;
2558 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2559 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2560 opname
= xtensa_opcode_name (isa
, opcode
);
2562 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2563 fprintf (stderr
, " operands = ");
2565 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2569 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2571 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2572 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2573 fprintf (stderr
, "%d ", val
);
2575 fprintf (stderr
, "\n");
2577 xtensa_insnbuf_free (isa
, sbuf
);
2580 #endif /* TENSILICA_DEBUG */
2584 is_direct_call_opcode (xtensa_opcode opcode
)
2586 xtensa_isa isa
= xtensa_default_isa
;
2587 int n
, num_operands
;
2589 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2592 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2593 for (n
= 0; n
< num_operands
; n
++)
2595 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2596 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2603 /* Convert from BFD relocation type code to slot and operand number.
2604 Returns non-zero on failure. */
2607 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2609 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2610 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2612 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2615 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2616 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2618 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2628 /* Convert from slot number to BFD relocation type code for the
2629 standard PC-relative relocations. Return BFD_RELOC_NONE on
2632 static bfd_reloc_code_real_type
2633 encode_reloc (int slot
)
2635 if (slot
< 0 || slot
> 14)
2636 return BFD_RELOC_NONE
;
2638 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2642 /* Convert from slot numbers to BFD relocation type code for the
2643 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2645 static bfd_reloc_code_real_type
2646 encode_alt_reloc (int slot
)
2648 if (slot
< 0 || slot
> 14)
2649 return BFD_RELOC_NONE
;
2651 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2656 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2659 xtensa_opcode opcode
,
2665 uint32 valbuf
= value
;
2667 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2669 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2671 as_bad_where ((char *) file
, line
,
2672 _("operand %d of '%s' has out of range value '%u'"),
2674 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2677 as_bad_where ((char *) file
, line
,
2678 _("operand %d of '%s' has invalid value '%u'"),
2680 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2685 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2691 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2694 xtensa_opcode opcode
,
2698 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2699 fmt
, slot
, slotbuf
, &val
);
2700 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2705 /* Checks for rules from xtensa-relax tables. */
2707 /* The routine xg_instruction_matches_option_term must return TRUE
2708 when a given option term is true. The meaning of all of the option
2709 terms is given interpretation by this function. This is needed when
2710 an option depends on the state of a directive, but there are no such
2711 options in use right now. */
2714 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2715 const ReqOrOption
*option
)
2717 if (strcmp (option
->option_name
, "realnop") == 0
2718 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2720 /* These conditions were evaluated statically when building the
2721 relaxation table. There's no need to reevaluate them now. */
2726 as_fatal (_("internal error: unknown option name '%s'"),
2727 option
->option_name
);
2733 xg_instruction_matches_or_options (TInsn
*insn
,
2734 const ReqOrOptionList
*or_option
)
2736 const ReqOrOption
*option
;
2737 /* Must match each of the AND terms. */
2738 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2740 if (xg_instruction_matches_option_term (insn
, option
))
2748 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2750 const ReqOption
*req_options
;
2751 /* Must match each of the AND terms. */
2752 for (req_options
= options
;
2753 req_options
!= NULL
;
2754 req_options
= req_options
->next
)
2756 /* Must match one of the OR clauses. */
2757 if (!xg_instruction_matches_or_options (insn
,
2758 req_options
->or_option_terms
))
2765 /* Return the transition rule that matches or NULL if none matches. */
2768 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2770 PreconditionList
*condition_l
;
2772 if (rule
->opcode
!= insn
->opcode
)
2775 for (condition_l
= rule
->conditions
;
2776 condition_l
!= NULL
;
2777 condition_l
= condition_l
->next
)
2781 Precondition
*cond
= condition_l
->precond
;
2786 /* The expression must be the constant. */
2787 assert (cond
->op_num
< insn
->ntok
);
2788 exp1
= &insn
->tok
[cond
->op_num
];
2789 if (expr_is_const (exp1
))
2794 if (get_expr_const (exp1
) != cond
->op_data
)
2798 if (get_expr_const (exp1
) == cond
->op_data
)
2805 else if (expr_is_register (exp1
))
2810 if (get_expr_register (exp1
) != cond
->op_data
)
2814 if (get_expr_register (exp1
) == cond
->op_data
)
2826 assert (cond
->op_num
< insn
->ntok
);
2827 assert (cond
->op_data
< insn
->ntok
);
2828 exp1
= &insn
->tok
[cond
->op_num
];
2829 exp2
= &insn
->tok
[cond
->op_data
];
2834 if (!expr_is_equal (exp1
, exp2
))
2838 if (expr_is_equal (exp1
, exp2
))
2850 if (!xg_instruction_matches_options (insn
, rule
->options
))
2858 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2860 bfd_boolean a_greater
= FALSE
;
2861 bfd_boolean b_greater
= FALSE
;
2863 ReqOptionList
*l_a
= a
->options
;
2864 ReqOptionList
*l_b
= b
->options
;
2866 /* We only care if they both are the same except for
2867 a const16 vs. an l32r. */
2869 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2871 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2872 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2873 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2875 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2877 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2879 /* This is the case we care about. */
2880 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2881 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2888 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2889 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2899 l_or_a
= l_or_a
->next
;
2900 l_or_b
= l_or_b
->next
;
2902 if (l_or_a
|| l_or_b
)
2911 /* Incomparable if the substitution was used differently in two cases. */
2912 if (a_greater
&& b_greater
)
2924 static TransitionRule
*
2925 xg_instruction_match (TInsn
*insn
)
2927 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2929 assert (insn
->opcode
< table
->num_opcodes
);
2931 /* Walk through all of the possible transitions. */
2932 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2934 TransitionRule
*rule
= l
->rule
;
2935 if (xg_instruction_matches_rule (insn
, rule
))
2942 /* Various Other Internal Functions. */
2945 is_unique_insn_expansion (TransitionRule
*r
)
2947 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2949 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2955 /* Check if there is exactly one relaxation for INSN that converts it to
2956 another instruction of equal or larger size. If so, and if TARG is
2957 non-null, go ahead and generate the relaxed instruction into TARG. If
2958 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2959 instruction, i.e., ignore relaxations that convert to an instruction of
2960 equal size. In some contexts where this function is used, only
2961 a single widening is allowed and the NARROW_ONLY argument is used to
2962 exclude cases like ADDI being "widened" to an ADDMI, which may
2963 later be relaxed to an ADDMI/ADDI pair. */
2966 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2968 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2970 TransitionRule
*match
= 0;
2972 assert (insn
->insn_type
== ITYPE_INSN
);
2973 assert (insn
->opcode
< table
->num_opcodes
);
2975 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2977 TransitionRule
*rule
= l
->rule
;
2979 if (xg_instruction_matches_rule (insn
, rule
)
2980 && is_unique_insn_expansion (rule
)
2981 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2982 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2993 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2998 /* Return the maximum number of bytes this opcode can expand to. */
3001 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3003 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3005 int max_size
= xg_get_single_size (opcode
);
3007 assert (opcode
< table
->num_opcodes
);
3009 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3011 TransitionRule
*rule
= l
->rule
;
3012 BuildInstr
*build_list
;
3017 build_list
= rule
->to_instr
;
3018 if (is_unique_insn_expansion (rule
))
3020 assert (build_list
->typ
== INSTR_INSTR
);
3021 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3024 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3026 switch (build_list
->typ
)
3029 this_size
+= xg_get_single_size (build_list
->opcode
);
3031 case INSTR_LITERAL_DEF
:
3032 case INSTR_LABEL_DEF
:
3037 if (this_size
> max_size
)
3038 max_size
= this_size
;
3044 /* Return the maximum number of literal bytes this opcode can generate. */
3047 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3049 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3053 assert (opcode
< table
->num_opcodes
);
3055 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3057 TransitionRule
*rule
= l
->rule
;
3058 BuildInstr
*build_list
;
3063 build_list
= rule
->to_instr
;
3064 if (is_unique_insn_expansion (rule
))
3066 assert (build_list
->typ
== INSTR_INSTR
);
3067 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3070 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3072 switch (build_list
->typ
)
3074 case INSTR_LITERAL_DEF
:
3075 /* Hard-coded 4-byte literal. */
3079 case INSTR_LABEL_DEF
:
3084 if (this_size
> max_size
)
3085 max_size
= this_size
;
3092 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3094 int steps_taken
= 0;
3095 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3098 assert (insn
->insn_type
== ITYPE_INSN
);
3099 assert (insn
->opcode
< table
->num_opcodes
);
3101 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3103 TransitionRule
*rule
= l
->rule
;
3105 if (xg_instruction_matches_rule (insn
, rule
))
3107 if (steps_taken
== lateral_steps
)
3117 get_special_literal_symbol (void)
3119 static symbolS
*sym
= NULL
;
3122 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3128 get_special_label_symbol (void)
3130 static symbolS
*sym
= NULL
;
3133 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3139 xg_valid_literal_expression (const expressionS
*exp
)
3156 /* This will check to see if the value can be converted into the
3157 operand type. It will return TRUE if it does not fit. */
3160 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3162 uint32 valbuf
= value
;
3163 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3169 /* Assumes: All immeds are constants. Check that all constants fit
3170 into their immeds; return FALSE if not. */
3173 xg_immeds_fit (const TInsn
*insn
)
3175 xtensa_isa isa
= xtensa_default_isa
;
3179 assert (insn
->insn_type
== ITYPE_INSN
);
3180 for (i
= 0; i
< n
; ++i
)
3182 const expressionS
*expr
= &insn
->tok
[i
];
3183 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3190 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3195 /* The symbol should have a fixup associated with it. */
3204 /* This should only be called after we have an initial
3205 estimate of the addresses. */
3208 xg_symbolic_immeds_fit (const TInsn
*insn
,
3214 xtensa_isa isa
= xtensa_default_isa
;
3222 assert (insn
->insn_type
== ITYPE_INSN
);
3224 for (i
= 0; i
< n
; ++i
)
3226 const expressionS
*expr
= &insn
->tok
[i
];
3227 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3234 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3240 /* Check for the worst case. */
3241 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3246 /* We only allow symbols for PC-relative references.
3247 If pc_frag == 0, then we don't have frag locations yet. */
3249 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3252 /* If it is a weak symbol, then assume it won't reach. */
3253 if (S_IS_WEAK (expr
->X_add_symbol
))
3256 if (is_direct_call_opcode (insn
->opcode
)
3257 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3259 /* If callee is undefined or in a different segment, be
3260 optimistic and assume it will be in range. */
3261 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3265 /* Only references within a segment can be known to fit in the
3266 operands at assembly time. */
3267 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3270 symbolP
= expr
->X_add_symbol
;
3271 sym_frag
= symbol_get_frag (symbolP
);
3272 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3273 pc
= pc_frag
->fr_address
+ pc_offset
;
3275 /* If frag has yet to be reached on this pass, assume it
3276 will move by STRETCH just as we did. If this is not so,
3277 it will be because some frag between grows, and that will
3278 force another pass. Beware zero-length frags. There
3279 should be a faster way to do this. */
3282 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3283 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3288 new_offset
= target
;
3289 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3290 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3295 /* The symbol should have a fixup associated with it. */
3304 /* Return TRUE on success. */
3307 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3312 memset (targ
, 0, sizeof (TInsn
));
3313 targ
->linenum
= insn
->linenum
;
3318 targ
->opcode
= bi
->opcode
;
3319 targ
->insn_type
= ITYPE_INSN
;
3320 targ
->is_specific_opcode
= FALSE
;
3322 for (; op
!= NULL
; op
= op
->next
)
3324 int op_num
= op
->op_num
;
3325 int op_data
= op
->op_data
;
3327 assert (op
->op_num
< MAX_INSN_ARGS
);
3329 if (targ
->ntok
<= op_num
)
3330 targ
->ntok
= op_num
+ 1;
3335 set_expr_const (&targ
->tok
[op_num
], op_data
);
3338 assert (op_data
< insn
->ntok
);
3339 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3342 sym
= get_special_literal_symbol ();
3343 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3346 sym
= get_special_label_symbol ();
3347 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3349 case OP_OPERAND_HI16U
:
3350 case OP_OPERAND_LOW16U
:
3351 assert (op_data
< insn
->ntok
);
3352 if (expr_is_const (&insn
->tok
[op_data
]))
3355 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3356 val
= xg_apply_userdef_op_fn (op
->typ
,
3359 targ
->tok
[op_num
].X_add_number
= val
;
3363 /* For const16 we can create relocations for these. */
3364 if (targ
->opcode
== XTENSA_UNDEFINED
3365 || (targ
->opcode
!= xtensa_const16_opcode
))
3367 assert (op_data
< insn
->ntok
);
3368 /* Need to build a O_lo16 or O_hi16. */
3369 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3370 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3372 if (op
->typ
== OP_OPERAND_HI16U
)
3373 targ
->tok
[op_num
].X_op
= O_hi16
;
3374 else if (op
->typ
== OP_OPERAND_LOW16U
)
3375 targ
->tok
[op_num
].X_op
= O_lo16
;
3382 /* currently handles:
3385 OP_OPERAND_F32MINUS */
3386 if (xg_has_userdef_op_fn (op
->typ
))
3388 assert (op_data
< insn
->ntok
);
3389 if (expr_is_const (&insn
->tok
[op_data
]))
3392 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3393 val
= xg_apply_userdef_op_fn (op
->typ
,
3396 targ
->tok
[op_num
].X_add_number
= val
;
3399 return FALSE
; /* We cannot use a relocation for this. */
3408 case INSTR_LITERAL_DEF
:
3410 targ
->opcode
= XTENSA_UNDEFINED
;
3411 targ
->insn_type
= ITYPE_LITERAL
;
3412 targ
->is_specific_opcode
= FALSE
;
3413 for (; op
!= NULL
; op
= op
->next
)
3415 int op_num
= op
->op_num
;
3416 int op_data
= op
->op_data
;
3417 assert (op
->op_num
< MAX_INSN_ARGS
);
3419 if (targ
->ntok
<= op_num
)
3420 targ
->ntok
= op_num
+ 1;
3425 assert (op_data
< insn
->ntok
);
3426 /* We can only pass resolvable literals through. */
3427 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3429 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3441 case INSTR_LABEL_DEF
:
3443 targ
->opcode
= XTENSA_UNDEFINED
;
3444 targ
->insn_type
= ITYPE_LABEL
;
3445 targ
->is_specific_opcode
= FALSE
;
3446 /* Literal with no ops is a label? */
3447 assert (op
== NULL
);
3458 /* Return TRUE on success. */
3461 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3463 for (; bi
!= NULL
; bi
= bi
->next
)
3465 TInsn
*next_insn
= istack_push_space (istack
);
3467 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3474 /* Return TRUE on valid expansion. */
3477 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3479 int stack_size
= istack
->ninsn
;
3480 int steps_taken
= 0;
3481 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3484 assert (insn
->insn_type
== ITYPE_INSN
);
3485 assert (insn
->opcode
< table
->num_opcodes
);
3487 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3489 TransitionRule
*rule
= l
->rule
;
3491 if (xg_instruction_matches_rule (insn
, rule
))
3493 if (lateral_steps
== steps_taken
)
3497 /* This is it. Expand the rule to the stack. */
3498 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3501 /* Check to see if it fits. */
3502 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3504 TInsn
*insn
= &istack
->insn
[i
];
3506 if (insn
->insn_type
== ITYPE_INSN
3507 && !tinsn_has_symbolic_operands (insn
)
3508 && !xg_immeds_fit (insn
))
3510 istack
->ninsn
= stack_size
;
3523 /* Relax the assembly instruction at least "min_steps".
3524 Return the number of steps taken. */
3527 xg_assembly_relax (IStack
*istack
,
3530 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3531 offsetT pc_offset
, /* offset in fragment */
3532 int min_steps
, /* minimum conversion steps */
3533 long stretch
) /* number of bytes stretched so far */
3535 int steps_taken
= 0;
3537 /* assert (has no symbolic operands)
3538 Some of its immeds don't fit.
3539 Try to build a relaxed version.
3540 This may go through a couple of stages
3541 of single instruction transformations before
3544 TInsn single_target
;
3546 int lateral_steps
= 0;
3547 int istack_size
= istack
->ninsn
;
3549 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3550 && steps_taken
>= min_steps
)
3552 istack_push (istack
, insn
);
3555 current_insn
= *insn
;
3557 /* Walk through all of the single instruction expansions. */
3558 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3561 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3564 if (steps_taken
>= min_steps
)
3566 istack_push (istack
, &single_target
);
3570 current_insn
= single_target
;
3573 /* Now check for a multi-instruction expansion. */
3574 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3576 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3579 if (steps_taken
>= min_steps
)
3581 istack_push (istack
, ¤t_insn
);
3586 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3588 if (steps_taken
>= min_steps
)
3592 istack
->ninsn
= istack_size
;
3595 /* It's not going to work -- use the original. */
3596 istack_push (istack
, insn
);
3602 xg_force_frag_space (int size
)
3604 /* This may have the side effect of creating a new fragment for the
3605 space to go into. I just do not like the name of the "frag"
3612 xg_finish_frag (char *last_insn
,
3613 enum xtensa_relax_statesE frag_state
,
3614 enum xtensa_relax_statesE slot0_state
,
3616 bfd_boolean is_insn
)
3618 /* Finish off this fragment so that it has at LEAST the desired
3619 max_growth. If it doesn't fit in this fragment, close this one
3620 and start a new one. In either case, return a pointer to the
3621 beginning of the growth area. */
3625 xg_force_frag_space (max_growth
);
3627 old_frag
= frag_now
;
3629 frag_now
->fr_opcode
= last_insn
;
3631 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3633 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3634 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3636 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3637 xtensa_set_frag_assembly_state (frag_now
);
3639 /* Just to make sure that we did not split it up. */
3640 assert (old_frag
->fr_next
== frag_now
);
3644 /* Return TRUE if the target frag is one of the next non-empty frags. */
3647 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3652 for (; fragP
; fragP
= fragP
->fr_next
)
3654 if (fragP
== target
)
3656 if (fragP
->fr_fix
!= 0)
3658 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3660 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3661 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3663 if (fragP
->fr_type
== rs_space
)
3671 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3673 xtensa_isa isa
= xtensa_default_isa
;
3675 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3680 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3681 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3684 for (i
= 0; i
< num_ops
; i
++)
3686 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3692 if (target_op
== -1)
3695 if (insn
->ntok
<= target_op
)
3698 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3701 sym
= insn
->tok
[target_op
].X_add_symbol
;
3705 if (insn
->tok
[target_op
].X_add_number
!= 0)
3708 target_frag
= symbol_get_frag (sym
);
3709 if (target_frag
== NULL
)
3712 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3713 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3721 xg_add_branch_and_loop_targets (TInsn
*insn
)
3723 xtensa_isa isa
= xtensa_default_isa
;
3724 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3726 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3729 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3730 && insn
->tok
[i
].X_op
== O_symbol
)
3731 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3735 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3736 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3740 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3742 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3743 && insn
->tok
[i
].X_op
== O_symbol
)
3745 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3746 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3747 if (S_IS_DEFINED (sym
))
3748 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3755 /* Return FALSE if no error. */
3758 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3763 switch (instr_spec
->typ
)
3766 new_insn
->insn_type
= ITYPE_INSN
;
3767 new_insn
->opcode
= instr_spec
->opcode
;
3768 new_insn
->is_specific_opcode
= FALSE
;
3769 new_insn
->linenum
= old_insn
->linenum
;
3771 case INSTR_LITERAL_DEF
:
3772 new_insn
->insn_type
= ITYPE_LITERAL
;
3773 new_insn
->opcode
= XTENSA_UNDEFINED
;
3774 new_insn
->is_specific_opcode
= FALSE
;
3775 new_insn
->linenum
= old_insn
->linenum
;
3777 case INSTR_LABEL_DEF
:
3778 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3782 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3785 const expressionS
*src_exp
;
3791 /* The expression must be the constant. */
3792 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3793 exp
= &new_insn
->tok
[b_op
->op_num
];
3794 set_expr_const (exp
, b_op
->op_data
);
3798 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3799 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3800 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3801 exp
= &new_insn
->tok
[b_op
->op_num
];
3802 copy_expr (exp
, src_exp
);
3807 as_bad (_("can't handle generation of literal/labels yet"));
3811 as_bad (_("can't handle undefined OP TYPE"));
3816 new_insn
->ntok
= num_ops
;
3821 /* Return TRUE if it was simplified. */
3824 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3826 TransitionRule
*rule
;
3827 BuildInstr
*insn_spec
;
3829 if (old_insn
->is_specific_opcode
|| !density_supported
)
3832 rule
= xg_instruction_match (old_insn
);
3836 insn_spec
= rule
->to_instr
;
3837 /* There should only be one. */
3838 assert (insn_spec
!= NULL
);
3839 assert (insn_spec
->next
== NULL
);
3840 if (insn_spec
->next
!= NULL
)
3843 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3849 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3850 l32i.n. (2) Check the number of operands. (3) Place the instruction
3851 tokens into the stack or relax it and place multiple
3852 instructions/literals onto the stack. Return FALSE if no error. */
3855 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3859 bfd_boolean do_expand
;
3861 memset (&new_insn
, 0, sizeof (TInsn
));
3863 /* Narrow it if we can. xg_simplify_insn now does all the
3864 appropriate checking (e.g., for the density option). */
3865 if (xg_simplify_insn (orig_insn
, &new_insn
))
3866 orig_insn
= &new_insn
;
3868 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3870 if (orig_insn
->ntok
< noperands
)
3872 as_bad (_("found %d operands for '%s': Expected %d"),
3874 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3878 if (orig_insn
->ntok
> noperands
)
3879 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3881 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3884 /* If there are not enough operands, we will assert above. If there
3885 are too many, just cut out the extras here. */
3886 orig_insn
->ntok
= noperands
;
3888 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3891 /* If the instruction will definitely need to be relaxed, it is better
3892 to expand it now for better scheduling. Decide whether to expand
3894 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3896 /* Calls should be expanded to longcalls only in the backend relaxation
3897 so that the assembly scheduler will keep the L32R/CALLX instructions
3899 if (is_direct_call_opcode (orig_insn
->opcode
))
3902 if (tinsn_has_symbolic_operands (orig_insn
))
3904 /* The values of symbolic operands are not known yet, so only expand
3905 now if an operand is "complex" (e.g., difference of symbols) and
3906 will have to be stored as a literal regardless of the value. */
3907 if (!tinsn_has_complex_operands (orig_insn
))
3910 else if (xg_immeds_fit (orig_insn
))
3914 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3916 istack_push (istack
, orig_insn
);
3922 /* Return TRUE if the section flags are marked linkonce
3923 or the name is .gnu.linkonce.*. */
3925 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3928 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3930 flagword flags
, link_once_flags
;
3932 flags
= bfd_get_section_flags (abfd
, sec
);
3933 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3935 /* Flags might not be set yet. */
3936 if (!link_once_flags
3937 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3938 link_once_flags
= SEC_LINK_ONCE
;
3940 return (link_once_flags
!= 0);
3945 xtensa_add_literal_sym (symbolS
*sym
)
3949 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3951 l
->next
= literal_syms
;
3957 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3959 static int lit_num
= 0;
3960 static char name
[256];
3963 sprintf (name
, ".L_lit_sym%d", lit_num
);
3965 /* Create a local symbol. If it is in a linkonce section, we have to
3966 be careful to make sure that if it is used in a relocation that the
3967 symbol will be in the output file. */
3968 if (get_is_linkonce_section (stdoutput
, sec
))
3970 symbolP
= symbol_new (name
, sec
, 0, frag
);
3971 S_CLEAR_EXTERNAL (symbolP
);
3972 /* symbolP->local = 1; */
3975 symbolP
= symbol_new (name
, sec
, 0, frag
);
3977 xtensa_add_literal_sym (symbolP
);
3984 /* Currently all literals that are generated here are 32-bit L32R targets. */
3987 xg_assemble_literal (/* const */ TInsn
*insn
)
3990 symbolS
*lit_sym
= NULL
;
3991 bfd_reloc_code_real_type reloc
;
3994 /* size = 4 for L32R. It could easily be larger when we move to
3995 larger constants. Add a parameter later. */
3996 offsetT litsize
= 4;
3997 offsetT litalign
= 2; /* 2^2 = 4 */
3998 expressionS saved_loc
;
3999 expressionS
* emit_val
;
4001 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4003 assert (insn
->insn_type
== ITYPE_LITERAL
);
4004 assert (insn
->ntok
== 1); /* must be only one token here */
4006 xtensa_switch_to_literal_fragment (&state
);
4008 emit_val
= &insn
->tok
[0];
4009 if (emit_val
->X_op
== O_big
)
4011 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4014 /* This happens when someone writes a "movi a2, big_number". */
4015 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4016 _("invalid immediate"));
4017 xtensa_restore_emit_state (&state
);
4022 /* Force a 4-byte align here. Note that this opens a new frag, so all
4023 literals done with this function have a frag to themselves. That's
4024 important for the way text section literals work. */
4025 frag_align (litalign
, 0, 0);
4026 record_alignment (now_seg
, litalign
);
4028 switch (emit_val
->X_op
)
4031 p
= frag_more (litsize
);
4032 xtensa_set_frag_assembly_state (frag_now
);
4033 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4034 if (emit_val
->X_add_symbol
)
4035 emit_val
->X_op
= O_symbol
;
4037 emit_val
->X_op
= O_constant
;
4038 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4039 litsize
, emit_val
, 0, reloc
);
4043 emit_expr (emit_val
, litsize
);
4047 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4048 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4049 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4050 lit_sym
= frag_now
->fr_symbol
;
4053 xtensa_restore_emit_state (&state
);
4059 xg_assemble_literal_space (/* const */ int size
, int slot
)
4062 /* We might have to do something about this alignment. It only
4063 takes effect if something is placed here. */
4064 offsetT litalign
= 2; /* 2^2 = 4 */
4065 fragS
*lit_saved_frag
;
4067 assert (size
% 4 == 0);
4069 xtensa_switch_to_literal_fragment (&state
);
4071 /* Force a 4-byte align here. */
4072 frag_align (litalign
, 0, 0);
4073 record_alignment (now_seg
, litalign
);
4075 xg_force_frag_space (size
);
4077 lit_saved_frag
= frag_now
;
4078 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4079 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4080 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4083 xtensa_restore_emit_state (&state
);
4084 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4088 /* Put in a fixup record based on the opcode.
4089 Return TRUE on success. */
4092 xg_add_opcode_fix (TInsn
*tinsn
,
4100 xtensa_opcode opcode
= tinsn
->opcode
;
4101 bfd_reloc_code_real_type reloc
;
4102 reloc_howto_type
*howto
;
4106 reloc
= BFD_RELOC_NONE
;
4108 /* First try the special cases for "alternate" relocs. */
4109 if (opcode
== xtensa_l32r_opcode
)
4111 if (fragP
->tc_frag_data
.use_absolute_literals
)
4112 reloc
= encode_alt_reloc (slot
);
4114 else if (opcode
== xtensa_const16_opcode
)
4116 if (expr
->X_op
== O_lo16
)
4118 reloc
= encode_reloc (slot
);
4119 expr
->X_op
= O_symbol
;
4121 else if (expr
->X_op
== O_hi16
)
4123 reloc
= encode_alt_reloc (slot
);
4124 expr
->X_op
= O_symbol
;
4128 if (opnum
!= get_relaxable_immed (opcode
))
4130 as_bad (_("invalid relocation for operand %i of '%s'"),
4131 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4135 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4136 into the symbol table where the generic portions of the assembler
4137 won't know what to do with them. */
4138 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4140 as_bad (_("invalid expression for operand %i of '%s'"),
4141 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4145 /* Next try the generic relocs. */
4146 if (reloc
== BFD_RELOC_NONE
)
4147 reloc
= encode_reloc (slot
);
4148 if (reloc
== BFD_RELOC_NONE
)
4150 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4154 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4157 as_bad (_("undefined symbol for opcode \"%s\""),
4158 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4162 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4163 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4164 howto
->pc_relative
, reloc
);
4165 the_fix
->fx_no_overflow
= 1;
4166 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4167 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4168 the_fix
->tc_fix_data
.slot
= slot
;
4175 xg_emit_insn_to_buf (TInsn
*tinsn
,
4179 bfd_boolean build_fix
)
4181 static xtensa_insnbuf insnbuf
= NULL
;
4182 bfd_boolean has_symbolic_immed
= FALSE
;
4183 bfd_boolean ok
= TRUE
;
4186 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4188 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4189 if (has_symbolic_immed
&& build_fix
)
4192 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4193 int slot
= xg_get_single_slot (tinsn
->opcode
);
4194 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4195 expressionS
*exp
= &tinsn
->tok
[opnum
];
4197 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4200 fragP
->tc_frag_data
.is_insn
= TRUE
;
4201 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4202 (unsigned char *) buf
, 0);
4208 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4210 symbolS
*sym
= get_special_literal_symbol ();
4214 assert (insn
->insn_type
== ITYPE_INSN
);
4215 for (i
= 0; i
< insn
->ntok
; i
++)
4216 if (insn
->tok
[i
].X_add_symbol
== sym
)
4217 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4223 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4225 symbolS
*sym
= get_special_label_symbol ();
4227 for (i
= 0; i
< insn
->ntok
; i
++)
4228 if (insn
->tok
[i
].X_add_symbol
== sym
)
4229 insn
->tok
[i
].X_add_symbol
= label_sym
;
4234 /* Return TRUE if the instruction can write to the specified
4235 integer register. */
4238 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4242 xtensa_isa isa
= xtensa_default_isa
;
4244 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4246 for (i
= 0; i
< num_ops
; i
++)
4249 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4250 if ((inout
== 'o' || inout
== 'm')
4251 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4253 xtensa_regfile opnd_rf
=
4254 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4255 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4257 if ((insn
->tok
[i
].X_op
== O_register
)
4258 && (insn
->tok
[i
].X_add_number
== regnum
))
4268 is_bad_loopend_opcode (const TInsn
*tinsn
)
4270 xtensa_opcode opcode
= tinsn
->opcode
;
4272 if (opcode
== XTENSA_UNDEFINED
)
4275 if (opcode
== xtensa_call0_opcode
4276 || opcode
== xtensa_callx0_opcode
4277 || opcode
== xtensa_call4_opcode
4278 || opcode
== xtensa_callx4_opcode
4279 || opcode
== xtensa_call8_opcode
4280 || opcode
== xtensa_callx8_opcode
4281 || opcode
== xtensa_call12_opcode
4282 || opcode
== xtensa_callx12_opcode
4283 || opcode
== xtensa_isync_opcode
4284 || opcode
== xtensa_ret_opcode
4285 || opcode
== xtensa_ret_n_opcode
4286 || opcode
== xtensa_retw_opcode
4287 || opcode
== xtensa_retw_n_opcode
4288 || opcode
== xtensa_waiti_opcode
4289 || opcode
== xtensa_rsr_lcount_opcode
)
4296 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4297 This allows the debugger to add unaligned labels.
4298 Also, the assembler generates stabs labels that need
4299 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4302 is_unaligned_label (symbolS
*sym
)
4304 const char *name
= S_GET_NAME (sym
);
4305 static size_t fake_size
= 0;
4309 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4312 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4314 fake_size
= strlen (FAKE_LABEL_NAME
);
4317 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4318 && (name
[fake_size
] == 'F'
4319 || name
[fake_size
] == 'L'
4320 || (name
[fake_size
] == 'e'
4321 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4329 next_non_empty_frag (const fragS
*fragP
)
4331 fragS
*next_fragP
= fragP
->fr_next
;
4333 /* Sometimes an empty will end up here due storage allocation issues.
4334 So we have to skip until we find something legit. */
4335 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4336 next_fragP
= next_fragP
->fr_next
;
4338 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4346 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4348 xtensa_opcode out_opcode
;
4349 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4351 if (next_fragP
== NULL
)
4354 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4355 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4357 *opcode
= out_opcode
;
4365 frag_format_size (const fragS
*fragP
)
4367 static xtensa_insnbuf insnbuf
= NULL
;
4368 xtensa_isa isa
= xtensa_default_isa
;
4373 insnbuf
= xtensa_insnbuf_alloc (isa
);
4376 return XTENSA_UNDEFINED
;
4378 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4379 (unsigned char *) fragP
->fr_literal
, 0);
4381 fmt
= xtensa_format_decode (isa
, insnbuf
);
4382 if (fmt
== XTENSA_UNDEFINED
)
4383 return XTENSA_UNDEFINED
;
4384 fmt_size
= xtensa_format_length (isa
, fmt
);
4386 /* If the next format won't be changing due to relaxation, just
4387 return the length of the first format. */
4388 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4391 /* If during relaxation we have to pull an instruction out of a
4392 multi-slot instruction, we will return the more conservative
4393 number. This works because alignment on bigger instructions
4394 is more restrictive than alignment on smaller instructions.
4395 This is more conservative than we would like, but it happens
4398 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4401 /* If we aren't doing one of our own relaxations or it isn't
4402 slot-based, then the insn size won't change. */
4403 if (fragP
->fr_type
!= rs_machine_dependent
)
4405 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4408 /* If an instruction is about to grow, return the longer size. */
4409 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4410 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4413 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4414 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4421 next_frag_format_size (const fragS
*fragP
)
4423 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4424 return frag_format_size (next_fragP
);
4428 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4429 required two-byte instructions to be treated as three-byte instructions
4430 for loop instruction alignment. This restriction was removed beginning
4431 with Xtensa LX. Now the only requirement on loop instruction alignment
4432 is that the first instruction of the loop must appear at an address that
4433 does not cross a fetch boundary. */
4436 get_loop_align_size (int insn_size
)
4438 if (insn_size
== XTENSA_UNDEFINED
)
4439 return xtensa_fetch_width
;
4441 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4448 /* If the next legit fragment is an end-of-loop marker,
4449 switch its state so it will instantiate a NOP. */
4452 update_next_frag_state (fragS
*fragP
)
4454 fragS
*next_fragP
= fragP
->fr_next
;
4455 fragS
*new_target
= NULL
;
4459 /* We are guaranteed there will be one of these... */
4460 while (!(next_fragP
->fr_type
== rs_machine_dependent
4461 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4462 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4463 next_fragP
= next_fragP
->fr_next
;
4465 assert (next_fragP
->fr_type
== rs_machine_dependent
4466 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4467 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4469 /* ...and one of these. */
4470 new_target
= next_fragP
->fr_next
;
4471 while (!(new_target
->fr_type
== rs_machine_dependent
4472 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4473 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4474 new_target
= new_target
->fr_next
;
4476 assert (new_target
->fr_type
== rs_machine_dependent
4477 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4478 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4481 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4483 if (next_fragP
->fr_type
== rs_machine_dependent
4484 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4486 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4490 next_fragP
= next_fragP
->fr_next
;
4496 next_frag_is_branch_target (const fragS
*fragP
)
4498 /* Sometimes an empty will end up here due to storage allocation issues,
4499 so we have to skip until we find something legit. */
4500 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4502 if (fragP
->tc_frag_data
.is_branch_target
)
4504 if (fragP
->fr_fix
!= 0)
4512 next_frag_is_loop_target (const fragS
*fragP
)
4514 /* Sometimes an empty will end up here due storage allocation issues.
4515 So we have to skip until we find something legit. */
4516 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4518 if (fragP
->tc_frag_data
.is_loop_target
)
4520 if (fragP
->fr_fix
!= 0)
4528 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4530 const fragS
*next_fragp
= fragp
->fr_next
;
4531 xtensa_opcode next_opcode
;
4533 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4536 /* Sometimes an empty will end up here due to storage allocation issues,
4537 so we have to skip until we find something legit. */
4538 while (next_fragp
->fr_fix
== 0)
4539 next_fragp
= next_fragp
->fr_next
;
4541 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4544 /* There is some implicit knowledge encoded in here.
4545 The LOOP instructions that are NOT RELAX_IMMED have
4546 been relaxed. Note that we can assume that the LOOP
4547 instruction is in slot 0 because loops aren't bundleable. */
4548 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4549 return get_expanded_loop_offset (next_opcode
);
4555 /* Mark a location where we can later insert literal frags. Update
4556 the section's literal_pool_loc, so subsequent literals can be
4557 placed nearest to their use. */
4560 xtensa_mark_literal_pool_location (void)
4562 /* Any labels pointing to the current location need
4563 to be adjusted to after the literal pool. */
4565 fragS
*pool_location
;
4567 if (use_literal_section
)
4570 /* We stash info in these frags so we can later move the literal's
4571 fixes into this frchain's fix list. */
4572 pool_location
= frag_now
;
4573 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4574 frag_variant (rs_machine_dependent
, 0, 0,
4575 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4576 xtensa_set_frag_assembly_state (frag_now
);
4577 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4578 frag_variant (rs_machine_dependent
, 0, 0,
4579 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4580 xtensa_set_frag_assembly_state (frag_now
);
4582 /* Now put a frag into the literal pool that points to this location. */
4583 set_literal_pool_location (now_seg
, pool_location
);
4584 xtensa_switch_to_non_abs_literal_fragment (&s
);
4585 frag_align (2, 0, 0);
4586 record_alignment (now_seg
, 2);
4588 /* Close whatever frag is there. */
4589 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4590 xtensa_set_frag_assembly_state (frag_now
);
4591 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4592 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4593 xtensa_restore_emit_state (&s
);
4594 xtensa_set_frag_assembly_state (frag_now
);
4598 /* Build a nop of the correct size into tinsn. */
4601 build_nop (TInsn
*tinsn
, int size
)
4607 tinsn
->opcode
= xtensa_nop_n_opcode
;
4609 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4610 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4614 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4616 tinsn
->opcode
= xtensa_or_opcode
;
4617 set_expr_const (&tinsn
->tok
[0], 1);
4618 set_expr_const (&tinsn
->tok
[1], 1);
4619 set_expr_const (&tinsn
->tok
[2], 1);
4623 tinsn
->opcode
= xtensa_nop_opcode
;
4625 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4630 /* Assemble a NOP of the requested size in the buffer. User must have
4631 allocated "buf" with at least "size" bytes. */
4634 assemble_nop (int size
, char *buf
)
4636 static xtensa_insnbuf insnbuf
= NULL
;
4639 build_nop (&tinsn
, size
);
4642 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4644 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4645 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4646 (unsigned char *) buf
, 0);
4650 /* Return the number of bytes for the offset of the expanded loop
4651 instruction. This should be incorporated into the relaxation
4652 specification but is hard-coded here. This is used to auto-align
4653 the loop instruction. It is invalid to call this function if the
4654 configuration does not have loops or if the opcode is not a loop
4658 get_expanded_loop_offset (xtensa_opcode opcode
)
4660 /* This is the OFFSET of the loop instruction in the expanded loop.
4661 This MUST correspond directly to the specification of the loop
4662 expansion. It will be validated on fragment conversion. */
4663 assert (opcode
!= XTENSA_UNDEFINED
);
4664 if (opcode
== xtensa_loop_opcode
)
4666 if (opcode
== xtensa_loopnez_opcode
)
4668 if (opcode
== xtensa_loopgtz_opcode
)
4670 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4676 get_literal_pool_location (segT seg
)
4678 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4683 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4685 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4689 /* Set frag assembly state should be called when a new frag is
4690 opened and after a frag has been closed. */
4693 xtensa_set_frag_assembly_state (fragS
*fragP
)
4695 if (!density_supported
)
4696 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4698 /* This function is called from subsegs_finish, which is called
4699 after xtensa_end, so we can't use "use_transform" or
4700 "use_schedule" here. */
4701 if (!directive_state
[directive_transform
])
4702 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4703 if (directive_state
[directive_longcalls
])
4704 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4705 fragP
->tc_frag_data
.use_absolute_literals
=
4706 directive_state
[directive_absolute_literals
];
4707 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4712 relaxable_section (asection
*sec
)
4714 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4719 xtensa_find_unmarked_state_frags (void)
4723 /* Walk over each fragment of all of the current segments. For each
4724 unmarked fragment, mark it with the same info as the previous
4726 for (seclist
= &stdoutput
->sections
;
4727 seclist
&& *seclist
;
4728 seclist
= &(*seclist
)->next
)
4730 segT sec
= *seclist
;
4731 segment_info_type
*seginfo
;
4734 flags
= bfd_get_section_flags (stdoutput
, sec
);
4735 if (flags
& SEC_DEBUGGING
)
4737 if (!(flags
& SEC_ALLOC
))
4740 seginfo
= seg_info (sec
);
4741 if (seginfo
&& seginfo
->frchainP
)
4743 fragS
*last_fragP
= 0;
4744 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4745 fragP
= fragP
->fr_next
)
4747 if (fragP
->fr_fix
!= 0
4748 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4750 if (last_fragP
== 0)
4752 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4753 _("assembly state not set for first frag in section %s"),
4758 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4759 fragP
->tc_frag_data
.is_no_density
=
4760 last_fragP
->tc_frag_data
.is_no_density
;
4761 fragP
->tc_frag_data
.is_no_transform
=
4762 last_fragP
->tc_frag_data
.is_no_transform
;
4763 fragP
->tc_frag_data
.use_longcalls
=
4764 last_fragP
->tc_frag_data
.use_longcalls
;
4765 fragP
->tc_frag_data
.use_absolute_literals
=
4766 last_fragP
->tc_frag_data
.use_absolute_literals
;
4769 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4778 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4780 void *unused ATTRIBUTE_UNUSED
)
4782 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4783 segment_info_type
*seginfo
= seg_info (sec
);
4784 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4786 if (flags
& SEC_CODE
)
4788 xtensa_isa isa
= xtensa_default_isa
;
4789 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4790 while (frag
!= NULL
)
4792 if (frag
->tc_frag_data
.is_branch_target
)
4795 addressT branch_align
, frag_addr
;
4798 xtensa_insnbuf_from_chars
4799 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4800 fmt
= xtensa_format_decode (isa
, insnbuf
);
4801 op_size
= xtensa_format_length (isa
, fmt
);
4802 branch_align
= 1 << branch_align_power (sec
);
4803 frag_addr
= frag
->fr_address
% branch_align
;
4804 if (frag_addr
+ op_size
> branch_align
)
4805 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4806 _("unaligned branch target: %d bytes at 0x%lx"),
4807 op_size
, (long) frag
->fr_address
);
4809 frag
= frag
->fr_next
;
4811 xtensa_insnbuf_free (isa
, insnbuf
);
4817 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4819 void *unused ATTRIBUTE_UNUSED
)
4821 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4822 segment_info_type
*seginfo
= seg_info (sec
);
4823 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4824 xtensa_isa isa
= xtensa_default_isa
;
4826 if (flags
& SEC_CODE
)
4828 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4829 while (frag
!= NULL
)
4831 if (frag
->tc_frag_data
.is_first_loop_insn
)
4837 xtensa_insnbuf_from_chars
4838 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4839 fmt
= xtensa_format_decode (isa
, insnbuf
);
4840 op_size
= xtensa_format_length (isa
, fmt
);
4841 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4843 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4844 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4845 _("unaligned loop: %d bytes at 0x%lx"),
4846 op_size
, (long) frag
->fr_address
);
4848 frag
= frag
->fr_next
;
4850 xtensa_insnbuf_free (isa
, insnbuf
);
4856 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4858 xtensa_isa isa
= xtensa_default_isa
;
4859 static xtensa_insnbuf insnbuf
= NULL
;
4860 static xtensa_insnbuf slotbuf
= NULL
;
4863 bfd_boolean alt_reloc
;
4864 xtensa_opcode opcode
;
4865 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4867 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4869 as_fatal (_("unexpected fix"));
4873 insnbuf
= xtensa_insnbuf_alloc (isa
);
4874 slotbuf
= xtensa_insnbuf_alloc (isa
);
4877 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4878 fmt
= xtensa_format_decode (isa
, insnbuf
);
4879 if (fmt
== XTENSA_UNDEFINED
)
4880 as_fatal (_("undecodable fix"));
4881 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4882 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4883 if (opcode
== XTENSA_UNDEFINED
)
4884 as_fatal (_("undecodable fix"));
4886 /* CONST16 immediates are not PC-relative, despite the fact that we
4887 reuse the normal PC-relative operand relocations for the low part
4888 of a CONST16 operand. */
4889 if (opcode
== xtensa_const16_opcode
)
4892 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4893 get_relaxable_immed (opcode
), val
,
4894 fixP
->fx_file
, fixP
->fx_line
);
4896 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4897 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4903 /* External Functions and Other GAS Hooks. */
4906 xtensa_target_format (void)
4908 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4913 xtensa_file_arch_init (bfd
*abfd
)
4915 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4920 md_number_to_chars (char *buf
, valueT val
, int n
)
4922 if (target_big_endian
)
4923 number_to_chars_bigendian (buf
, val
, n
);
4925 number_to_chars_littleendian (buf
, val
, n
);
4929 /* This function is called once, at assembler startup time. It should
4930 set up all the tables, etc. that the MD part of the assembler will
4936 segT current_section
= now_seg
;
4937 int current_subsec
= now_subseg
;
4940 xtensa_default_isa
= xtensa_isa_init (0, 0);
4941 isa
= xtensa_default_isa
;
4945 /* Set up the literal sections. */
4946 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4948 subseg_set (current_section
, current_subsec
);
4950 xg_init_vinsn (&cur_vinsn
);
4952 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4953 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4954 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4955 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4956 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4957 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4958 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4959 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4960 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4961 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4962 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4963 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4964 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4965 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4966 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4967 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4968 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4969 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4970 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4971 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4972 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4973 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4974 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4975 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4976 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4977 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4978 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4979 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4980 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4982 init_op_placement_info_table ();
4984 /* Set up the assembly state. */
4985 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4986 xtensa_set_frag_assembly_state (frag_now
);
4990 /* TC_INIT_FIX_DATA hook */
4993 xtensa_init_fix_data (fixS
*x
)
4995 x
->tc_fix_data
.slot
= 0;
4996 x
->tc_fix_data
.X_add_symbol
= NULL
;
4997 x
->tc_fix_data
.X_add_number
= 0;
5001 /* tc_frob_label hook */
5004 xtensa_frob_label (symbolS
*sym
)
5008 if (cur_vinsn
.inside_bundle
)
5010 as_bad (_("labels are not valid inside bundles"));
5014 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5016 /* Since the label was already attached to a frag associated with the
5017 previous basic block, it now needs to be reset to the current frag. */
5018 symbol_set_frag (sym
, frag_now
);
5019 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5021 if (generating_literals
)
5022 xtensa_add_literal_sym (sym
);
5024 xtensa_add_insn_label (sym
);
5026 if (symbol_get_tc (sym
)->is_loop_target
)
5028 if ((get_last_insn_flags (now_seg
, now_subseg
)
5029 & FLAG_IS_BAD_LOOPEND
) != 0)
5030 as_bad (_("invalid last instruction for a zero-overhead loop"));
5032 xtensa_set_frag_assembly_state (frag_now
);
5033 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5034 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5036 xtensa_set_frag_assembly_state (frag_now
);
5037 xtensa_move_labels (frag_now
, 0, TRUE
);
5040 /* No target aligning in the absolute section. */
5041 if (now_seg
!= absolute_section
5042 && do_align_targets ()
5043 && !is_unaligned_label (sym
)
5044 && !generating_literals
)
5046 xtensa_set_frag_assembly_state (frag_now
);
5048 frag_var (rs_machine_dependent
,
5050 RELAX_DESIRE_ALIGN_IF_TARGET
,
5051 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5052 xtensa_set_frag_assembly_state (frag_now
);
5053 xtensa_move_labels (frag_now
, 0, TRUE
);
5056 /* We need to mark the following properties even if we aren't aligning. */
5058 /* If the label is already known to be a branch target, i.e., a
5059 forward branch, mark the frag accordingly. Backward branches
5060 are handled by xg_add_branch_and_loop_targets. */
5061 if (symbol_get_tc (sym
)->is_branch_target
)
5062 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5064 /* Loops only go forward, so they can be identified here. */
5065 if (symbol_get_tc (sym
)->is_loop_target
)
5066 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5068 dwarf2_emit_label (sym
);
5072 /* tc_unrecognized_line hook */
5075 xtensa_unrecognized_line (int ch
)
5080 if (cur_vinsn
.inside_bundle
== 0)
5082 /* PR8110: Cannot emit line number info inside a FLIX bundle
5083 when using --gstabs. Temporarily disable debug info. */
5084 generate_lineno_debug ();
5085 if (debug_type
== DEBUG_STABS
)
5087 xt_saved_debug_type
= debug_type
;
5088 debug_type
= DEBUG_NONE
;
5091 cur_vinsn
.inside_bundle
= 1;
5095 as_bad (_("extra opening brace"));
5101 if (cur_vinsn
.inside_bundle
)
5102 finish_vinsn (&cur_vinsn
);
5105 as_bad (_("extra closing brace"));
5110 as_bad (_("syntax error"));
5117 /* md_flush_pending_output hook */
5120 xtensa_flush_pending_output (void)
5122 if (cur_vinsn
.inside_bundle
)
5123 as_bad (_("missing closing brace"));
5125 /* If there is a non-zero instruction fragment, close it. */
5126 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5128 frag_wane (frag_now
);
5130 xtensa_set_frag_assembly_state (frag_now
);
5132 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5134 xtensa_clear_insn_labels ();
5138 /* We had an error while parsing an instruction. The string might look
5139 like this: "insn arg1, arg2 }". If so, we need to see the closing
5140 brace and reset some fields. Otherwise, the vinsn never gets closed
5141 and the num_slots field will grow past the end of the array of slots,
5142 and bad things happen. */
5145 error_reset_cur_vinsn (void)
5147 if (cur_vinsn
.inside_bundle
)
5149 if (*input_line_pointer
== '}'
5150 || *(input_line_pointer
- 1) == '}'
5151 || *(input_line_pointer
- 2) == '}')
5152 xg_clear_vinsn (&cur_vinsn
);
5158 md_assemble (char *str
)
5160 xtensa_isa isa
= xtensa_default_isa
;
5161 char *opname
, *file_name
;
5163 bfd_boolean has_underbar
= FALSE
;
5164 char *arg_strings
[MAX_INSN_ARGS
];
5166 TInsn orig_insn
; /* Original instruction from the input. */
5168 tinsn_init (&orig_insn
);
5170 /* Split off the opcode. */
5171 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5172 opname
= xmalloc (opnamelen
+ 1);
5173 memcpy (opname
, str
, opnamelen
);
5174 opname
[opnamelen
] = '\0';
5176 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5179 as_bad (_("syntax error"));
5183 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5186 /* Check for an underbar prefix. */
5189 has_underbar
= TRUE
;
5193 orig_insn
.insn_type
= ITYPE_INSN
;
5195 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5197 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5198 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5200 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5201 if (fmt
== XTENSA_UNDEFINED
)
5203 as_bad (_("unknown opcode or format name '%s'"), opname
);
5204 error_reset_cur_vinsn ();
5207 if (!cur_vinsn
.inside_bundle
)
5209 as_bad (_("format names only valid inside bundles"));
5210 error_reset_cur_vinsn ();
5213 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5214 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5216 cur_vinsn
.format
= fmt
;
5217 free (has_underbar
? opname
- 1 : opname
);
5218 error_reset_cur_vinsn ();
5222 /* Parse the arguments. */
5223 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5225 as_bad (_("syntax error"));
5226 error_reset_cur_vinsn ();
5230 /* Free the opcode and argument strings, now that they've been parsed. */
5231 free (has_underbar
? opname
- 1 : opname
);
5233 while (num_args
-- > 0)
5234 free (arg_strings
[num_args
]);
5236 /* Get expressions for invisible operands. */
5237 if (get_invisible_operands (&orig_insn
))
5239 error_reset_cur_vinsn ();
5243 /* Check for the right number and type of arguments. */
5244 if (tinsn_check_arguments (&orig_insn
))
5246 error_reset_cur_vinsn ();
5250 /* A FLIX bundle may be spread across multiple input lines. We want to
5251 report the first such line in the debug information. Record the line
5252 number for each TInsn (assume the file name doesn't change), so the
5253 first line can be found later. */
5254 as_where (&file_name
, &orig_insn
.linenum
);
5256 xg_add_branch_and_loop_targets (&orig_insn
);
5258 /* Check that immediate value for ENTRY is >= 16. */
5259 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5261 expressionS
*exp
= &orig_insn
.tok
[2];
5262 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5263 as_warn (_("entry instruction with stack decrement < 16"));
5267 assemble_tokens (opcode, tok, ntok);
5268 expand the tokens from the orig_insn into the
5269 stack of instructions that will not expand
5270 unless required at relaxation time. */
5272 if (!cur_vinsn
.inside_bundle
)
5273 emit_single_op (&orig_insn
);
5274 else /* We are inside a bundle. */
5276 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5277 cur_vinsn
.num_slots
++;
5278 if (*input_line_pointer
== '}'
5279 || *(input_line_pointer
- 1) == '}'
5280 || *(input_line_pointer
- 2) == '}')
5281 finish_vinsn (&cur_vinsn
);
5284 /* We've just emitted a new instruction so clear the list of labels. */
5285 xtensa_clear_insn_labels ();
5289 /* HANDLE_ALIGN hook */
5291 /* For a .align directive, we mark the previous block with the alignment
5292 information. This will be placed in the object file in the
5293 property section corresponding to this section. */
5296 xtensa_handle_align (fragS
*fragP
)
5299 && ! fragP
->tc_frag_data
.is_literal
5300 && (fragP
->fr_type
== rs_align
5301 || fragP
->fr_type
== rs_align_code
)
5302 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5303 && fragP
->fr_offset
> 0
5304 && now_seg
!= bss_section
)
5306 fragP
->tc_frag_data
.is_align
= TRUE
;
5307 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5310 if (fragP
->fr_type
== rs_align_test
)
5313 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5315 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5316 _("unaligned entry instruction"));
5321 /* TC_FRAG_INIT hook */
5324 xtensa_frag_init (fragS
*frag
)
5326 xtensa_set_frag_assembly_state (frag
);
5331 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5337 /* Round up a section size to the appropriate boundary. */
5340 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5342 return size
; /* Byte alignment is fine. */
5347 md_pcrel_from (fixS
*fixP
)
5350 static xtensa_insnbuf insnbuf
= NULL
;
5351 static xtensa_insnbuf slotbuf
= NULL
;
5354 xtensa_opcode opcode
;
5357 xtensa_isa isa
= xtensa_default_isa
;
5358 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5359 bfd_boolean alt_reloc
;
5361 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5366 insnbuf
= xtensa_insnbuf_alloc (isa
);
5367 slotbuf
= xtensa_insnbuf_alloc (isa
);
5370 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5371 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5372 fmt
= xtensa_format_decode (isa
, insnbuf
);
5374 if (fmt
== XTENSA_UNDEFINED
)
5375 as_fatal (_("bad instruction format"));
5377 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5378 as_fatal (_("invalid relocation"));
5380 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5381 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5383 /* Check for "alternate" relocations (operand not specified). None
5384 of the current uses for these are really PC-relative. */
5385 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5387 if (opcode
!= xtensa_l32r_opcode
5388 && opcode
!= xtensa_const16_opcode
)
5389 as_fatal (_("invalid relocation for '%s' instruction"),
5390 xtensa_opcode_name (isa
, opcode
));
5394 opnum
= get_relaxable_immed (opcode
);
5396 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5397 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5399 as_bad_where (fixP
->fx_file
,
5401 _("invalid relocation for operand %d of '%s'"),
5402 opnum
, xtensa_opcode_name (isa
, opcode
));
5405 return 0 - opnd_value
;
5409 /* TC_FORCE_RELOCATION hook */
5412 xtensa_force_relocation (fixS
*fix
)
5414 switch (fix
->fx_r_type
)
5416 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5417 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5418 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5419 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5420 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5421 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5422 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5423 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5424 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5425 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5426 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5427 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5428 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5429 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5430 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5431 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5437 if (linkrelax
&& fix
->fx_addsy
5438 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5441 return generic_force_reloc (fix
);
5445 /* TC_VALIDATE_FIX_SUB hook */
5448 xtensa_validate_fix_sub (fixS
*fix
)
5450 segT add_symbol_segment
, sub_symbol_segment
;
5452 /* The difference of two symbols should be resolved by the assembler when
5453 linkrelax is not set. If the linker may relax the section containing
5454 the symbols, then an Xtensa DIFF relocation must be generated so that
5455 the linker knows to adjust the difference value. */
5456 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5459 /* Make sure both symbols are in the same segment, and that segment is
5460 "normal" and relaxable. If the segment is not "normal", then the
5461 fix is not valid. If the segment is not "relaxable", then the fix
5462 should have been handled earlier. */
5463 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5464 if (! SEG_NORMAL (add_symbol_segment
) ||
5465 ! relaxable_section (add_symbol_segment
))
5467 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5468 return (sub_symbol_segment
== add_symbol_segment
);
5472 /* NO_PSEUDO_DOT hook */
5474 /* This function has nothing to do with pseudo dots, but this is the
5475 nearest macro to where the check needs to take place. FIXME: This
5479 xtensa_check_inside_bundle (void)
5481 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5482 as_bad (_("directives are not valid inside bundles"));
5484 /* This function must always return FALSE because it is called via a
5485 macro that has nothing to do with bundling. */
5490 /* md_elf_section_change_hook */
5493 xtensa_elf_section_change_hook (void)
5495 /* Set up the assembly state. */
5496 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5497 xtensa_set_frag_assembly_state (frag_now
);
5501 /* tc_fix_adjustable hook */
5504 xtensa_fix_adjustable (fixS
*fixP
)
5506 /* An offset is not allowed in combination with the difference of two
5507 symbols, but that cannot be easily detected after a local symbol
5508 has been adjusted to a (section+offset) form. Return 0 so that such
5509 an fix will not be adjusted. */
5510 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5511 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5514 /* We need the symbol name for the VTABLE entries. */
5515 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5516 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5524 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5526 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5529 /* Subtracted symbols are only allowed for a few relocation types, and
5530 unless linkrelax is enabled, they should not make it to this point. */
5531 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5532 || fixP
->fx_r_type
== BFD_RELOC_16
5533 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5536 switch (fixP
->fx_r_type
)
5543 switch (fixP
->fx_r_type
)
5546 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5549 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5552 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5558 /* An offset is only allowed when it results from adjusting a
5559 local symbol into a section-relative offset. If the offset
5560 came from the original expression, tc_fix_adjustable will have
5561 prevented the fix from being converted to a section-relative
5562 form so that we can flag the error here. */
5563 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5565 _("cannot represent subtraction with an offset"));
5567 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5568 - S_GET_VALUE (fixP
->fx_subsy
));
5570 /* The difference value gets written out, and the DIFF reloc
5571 identifies the address of the subtracted symbol (i.e., the one
5572 with the lowest address). */
5574 fixP
->fx_offset
-= val
;
5575 fixP
->fx_subsy
= NULL
;
5577 else if (! fixP
->fx_addsy
)
5584 case BFD_RELOC_XTENSA_PLT
:
5585 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5586 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5589 case BFD_RELOC_XTENSA_SLOT0_OP
:
5590 case BFD_RELOC_XTENSA_SLOT1_OP
:
5591 case BFD_RELOC_XTENSA_SLOT2_OP
:
5592 case BFD_RELOC_XTENSA_SLOT3_OP
:
5593 case BFD_RELOC_XTENSA_SLOT4_OP
:
5594 case BFD_RELOC_XTENSA_SLOT5_OP
:
5595 case BFD_RELOC_XTENSA_SLOT6_OP
:
5596 case BFD_RELOC_XTENSA_SLOT7_OP
:
5597 case BFD_RELOC_XTENSA_SLOT8_OP
:
5598 case BFD_RELOC_XTENSA_SLOT9_OP
:
5599 case BFD_RELOC_XTENSA_SLOT10_OP
:
5600 case BFD_RELOC_XTENSA_SLOT11_OP
:
5601 case BFD_RELOC_XTENSA_SLOT12_OP
:
5602 case BFD_RELOC_XTENSA_SLOT13_OP
:
5603 case BFD_RELOC_XTENSA_SLOT14_OP
:
5606 /* Write the tentative value of a PC-relative relocation to a
5607 local symbol into the instruction. The value will be ignored
5608 by the linker, and it makes the object file disassembly
5609 readable when all branch targets are encoded in relocations. */
5611 assert (fixP
->fx_addsy
);
5612 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5613 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5615 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5616 - md_pcrel_from (fixP
));
5617 (void) xg_apply_fix_value (fixP
, val
);
5620 else if (! fixP
->fx_addsy
)
5623 if (xg_apply_fix_value (fixP
, val
))
5628 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5629 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5630 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5631 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5632 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5633 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5634 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5635 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5636 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5637 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5638 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5639 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5640 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5641 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5642 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5643 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5644 /* These all need to be resolved at link-time. Do nothing now. */
5647 case BFD_RELOC_VTABLE_INHERIT
:
5648 case BFD_RELOC_VTABLE_ENTRY
:
5653 as_bad (_("unhandled local relocation fix %s"),
5654 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5660 md_atof (int type
, char *litP
, int *sizeP
)
5663 LITTLENUM_TYPE words
[4];
5679 return "bad call to md_atof";
5682 t
= atof_ieee (input_line_pointer
, type
, words
);
5684 input_line_pointer
= t
;
5688 for (i
= prec
- 1; i
>= 0; i
--)
5691 if (target_big_endian
)
5692 idx
= (prec
- 1 - i
);
5694 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5703 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5705 return total_frag_text_expansion (fragP
);
5709 /* Translate internal representation of relocation info to BFD target
5713 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5717 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5718 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5719 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5720 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5722 /* Make sure none of our internal relocations make it this far.
5723 They'd better have been fully resolved by this point. */
5724 assert ((int) fixp
->fx_r_type
> 0);
5726 reloc
->addend
= fixp
->fx_offset
;
5728 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5729 if (reloc
->howto
== NULL
)
5731 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5732 _("cannot represent `%s' relocation in object file"),
5733 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5734 free (reloc
->sym_ptr_ptr
);
5739 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5740 as_fatal (_("internal error? cannot generate `%s' relocation"),
5741 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5747 /* Checks for resource conflicts between instructions. */
5749 /* The func unit stuff could be implemented as bit-vectors rather
5750 than the iterative approach here. If it ends up being too
5751 slow, we will switch it. */
5754 new_resource_table (void *data
,
5757 unit_num_copies_func uncf
,
5758 opcode_num_units_func onuf
,
5759 opcode_funcUnit_use_unit_func ouuf
,
5760 opcode_funcUnit_use_stage_func ousf
)
5763 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5765 rt
->cycles
= cycles
;
5766 rt
->allocated_cycles
= cycles
;
5768 rt
->unit_num_copies
= uncf
;
5769 rt
->opcode_num_units
= onuf
;
5770 rt
->opcode_unit_use
= ouuf
;
5771 rt
->opcode_unit_stage
= ousf
;
5773 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5774 for (i
= 0; i
< cycles
; i
++)
5775 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5782 clear_resource_table (resource_table
*rt
)
5785 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5786 for (j
= 0; j
< rt
->num_units
; j
++)
5787 rt
->units
[i
][j
] = 0;
5791 /* We never shrink it, just fake it into thinking so. */
5794 resize_resource_table (resource_table
*rt
, int cycles
)
5798 rt
->cycles
= cycles
;
5799 if (cycles
<= rt
->allocated_cycles
)
5802 old_cycles
= rt
->allocated_cycles
;
5803 rt
->allocated_cycles
= cycles
;
5805 rt
->units
= xrealloc (rt
->units
,
5806 rt
->allocated_cycles
* sizeof (unsigned char *));
5807 for (i
= 0; i
< old_cycles
; i
++)
5808 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5809 rt
->num_units
* sizeof (unsigned char));
5810 for (i
= old_cycles
; i
< cycles
; i
++)
5811 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5816 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5819 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5821 for (i
= 0; i
< uses
; i
++)
5823 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5824 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5825 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5826 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5827 if (copies_in_use
>= copies
)
5835 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5838 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5840 for (i
= 0; i
< uses
; i
++)
5842 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5843 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5844 /* Note that this allows resources to be oversubscribed. That's
5845 essential to the way the optional scheduler works.
5846 resources_available reports when a resource is over-subscribed,
5847 so it's easy to tell. */
5848 rt
->units
[stage
+ cycle
][unit
]++;
5854 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5857 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5859 for (i
= 0; i
< uses
; i
++)
5861 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5862 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5863 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5864 rt
->units
[stage
+ cycle
][unit
]--;
5869 /* Wrapper functions make parameterized resource reservation
5873 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5875 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5881 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5883 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5888 /* Note that this function does not check issue constraints, but
5889 solely whether the hardware is available to execute the given
5890 instructions together. It also doesn't check if the tinsns
5891 write the same state, or access the same tieports. That is
5892 checked by check_t1_t2_reads_and_writes. */
5895 resources_conflict (vliw_insn
*vinsn
)
5898 static resource_table
*rt
= NULL
;
5900 /* This is the most common case by far. Optimize it. */
5901 if (vinsn
->num_slots
== 1)
5906 xtensa_isa isa
= xtensa_default_isa
;
5907 rt
= new_resource_table
5908 (isa
, xtensa_isa_num_pipe_stages (isa
),
5909 xtensa_isa_num_funcUnits (isa
),
5910 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5911 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5912 opcode_funcUnit_use_unit
,
5913 opcode_funcUnit_use_stage
);
5916 clear_resource_table (rt
);
5918 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5920 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5922 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5929 /* finish_vinsn, emit_single_op and helper functions. */
5931 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5932 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5933 static void xg_assemble_vliw_tokens (vliw_insn
*);
5936 /* We have reached the end of a bundle; emit into the frag. */
5939 finish_vinsn (vliw_insn
*vinsn
)
5946 if (find_vinsn_conflicts (vinsn
))
5948 xg_clear_vinsn (vinsn
);
5952 /* First, find a format that works. */
5953 if (vinsn
->format
== XTENSA_UNDEFINED
)
5954 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5956 if (vinsn
->format
== XTENSA_UNDEFINED
)
5958 as_where (&file_name
, &line
);
5959 as_bad_where (file_name
, line
,
5960 _("couldn't find a valid instruction format"));
5961 fprintf (stderr
, _(" ops were: "));
5962 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5963 fprintf (stderr
, _(" %s;"),
5964 xtensa_opcode_name (xtensa_default_isa
,
5965 vinsn
->slots
[i
].opcode
));
5966 fprintf (stderr
, _("\n"));
5967 xg_clear_vinsn (vinsn
);
5971 if (vinsn
->num_slots
5972 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5974 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5975 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5976 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5978 xg_clear_vinsn (vinsn
);
5982 if (resources_conflict (vinsn
))
5984 as_where (&file_name
, &line
);
5985 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5986 fprintf (stderr
, " ops were: ");
5987 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5988 fprintf (stderr
, " %s;",
5989 xtensa_opcode_name (xtensa_default_isa
,
5990 vinsn
->slots
[i
].opcode
));
5991 fprintf (stderr
, "\n");
5992 xg_clear_vinsn (vinsn
);
5996 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5998 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6000 symbolS
*lit_sym
= NULL
;
6002 bfd_boolean e
= FALSE
;
6003 bfd_boolean saved_density
= density_supported
;
6005 /* We don't want to narrow ops inside multi-slot bundles. */
6006 if (vinsn
->num_slots
> 1)
6007 density_supported
= FALSE
;
6009 istack_init (&slotstack
);
6010 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6012 vinsn
->slots
[i
].opcode
=
6013 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6015 vinsn
->slots
[i
].ntok
= 0;
6018 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6024 density_supported
= saved_density
;
6028 xg_clear_vinsn (vinsn
);
6032 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6034 TInsn
*insn
= &slotstack
.insn
[j
];
6035 if (insn
->insn_type
== ITYPE_LITERAL
)
6037 assert (lit_sym
== NULL
);
6038 lit_sym
= xg_assemble_literal (insn
);
6042 assert (insn
->insn_type
== ITYPE_INSN
);
6044 xg_resolve_literals (insn
, lit_sym
);
6045 if (j
!= slotstack
.ninsn
- 1)
6046 emit_single_op (insn
);
6050 if (vinsn
->num_slots
> 1)
6052 if (opcode_fits_format_slot
6053 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6056 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6060 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6061 if (vinsn
->format
== XTENSA_UNDEFINED
)
6062 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6064 vinsn
->slots
[i
].opcode
6065 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6068 vinsn
->slots
[i
].ntok
= 0;
6073 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6074 vinsn
->format
= XTENSA_UNDEFINED
;
6079 /* Now check resource conflicts on the modified bundle. */
6080 if (resources_conflict (vinsn
))
6082 as_where (&file_name
, &line
);
6083 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6084 fprintf (stderr
, " ops were: ");
6085 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6086 fprintf (stderr
, " %s;",
6087 xtensa_opcode_name (xtensa_default_isa
,
6088 vinsn
->slots
[i
].opcode
));
6089 fprintf (stderr
, "\n");
6090 xg_clear_vinsn (vinsn
);
6094 /* First, find a format that works. */
6095 if (vinsn
->format
== XTENSA_UNDEFINED
)
6096 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6098 xg_assemble_vliw_tokens (vinsn
);
6100 xg_clear_vinsn (vinsn
);
6104 /* Given an vliw instruction, what conflicts are there in register
6105 usage and in writes to states and queues?
6107 This function does two things:
6108 1. Reports an error when a vinsn contains illegal combinations
6109 of writes to registers states or queues.
6110 2. Marks individual tinsns as not relaxable if the combination
6111 contains antidependencies.
6113 Job 2 handles things like swap semantics in instructions that need
6114 to be relaxed. For example,
6118 normally would be relaxed to
6123 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6125 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6127 then we can't relax it into
6130 { add a0, a1, a0 ; add a2, a0, a4 ; }
6132 because the value of a0 is trashed before the second add can read it. */
6134 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6137 find_vinsn_conflicts (vliw_insn
*vinsn
)
6141 xtensa_isa isa
= xtensa_default_isa
;
6143 assert (!past_xtensa_end
);
6145 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6147 TInsn
*op1
= &vinsn
->slots
[i
];
6148 if (op1
->is_specific_opcode
)
6149 op1
->keep_wide
= TRUE
;
6151 op1
->keep_wide
= FALSE
;
6154 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6156 TInsn
*op1
= &vinsn
->slots
[i
];
6158 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6161 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6165 TInsn
*op2
= &vinsn
->slots
[j
];
6166 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6167 switch (conflict_type
)
6170 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6171 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6172 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6175 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6176 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6177 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6180 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6181 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6182 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6185 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6186 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6187 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6190 /* Everything is OK. */
6193 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6194 || conflict_type
== 'a');
6201 as_bad (_("multiple branches or jumps in the same bundle"));
6209 /* Check how the state used by t1 and t2 relate.
6212 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6213 case B: no relationship between what is read and written (both could
6214 read the same reg though)
6215 case C: t1 writes a register t2 writes (a register conflict within a
6217 case D: t1 writes a state that t2 also writes
6218 case E: t1 writes a tie queue that t2 also writes
6219 case F: two volatile queue accesses
6223 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6225 xtensa_isa isa
= xtensa_default_isa
;
6226 xtensa_regfile t1_regfile
, t2_regfile
;
6228 int t1_base_reg
, t1_last_reg
;
6229 int t2_base_reg
, t2_last_reg
;
6230 char t1_inout
, t2_inout
;
6232 char conflict
= 'b';
6237 bfd_boolean t1_volatile
= FALSE
;
6238 bfd_boolean t2_volatile
= FALSE
;
6240 /* Check registers. */
6241 for (j
= 0; j
< t2
->ntok
; j
++)
6243 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6246 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6247 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6248 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6250 for (i
= 0; i
< t1
->ntok
; i
++)
6252 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6255 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6257 if (t1_regfile
!= t2_regfile
)
6260 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6261 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6263 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6264 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6266 if (t1_inout
== 'm' || t1_inout
== 'o'
6267 || t2_inout
== 'm' || t2_inout
== 'o')
6274 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6275 t1_last_reg
= (t1_base_reg
6276 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6278 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6280 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6282 if (t1_reg
!= t2_reg
)
6285 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6291 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6297 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6305 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6306 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6307 for (j
= 0; j
< t2_states
; j
++)
6309 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6310 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6311 for (i
= 0; i
< t1_states
; i
++)
6313 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6314 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6318 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6324 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6330 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6335 /* Check tieports. */
6336 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6337 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6338 for (j
= 0; j
< t2_interfaces
; j
++)
6340 xtensa_interface t2_int
6341 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6342 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6344 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6345 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6348 for (i
= 0; i
< t1_interfaces
; i
++)
6350 xtensa_interface t1_int
6351 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6352 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6354 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6355 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6358 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6361 if (t1_int
!= t2_int
)
6364 if (t2_inout
== 'i' && t1_inout
== 'o')
6370 if (t1_inout
== 'i' && t2_inout
== 'o')
6376 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6385 static xtensa_format
6386 xg_find_narrowest_format (vliw_insn
*vinsn
)
6388 /* Right now we assume that the ops within the vinsn are properly
6389 ordered for the slots that the programmer wanted them in. In
6390 other words, we don't rearrange the ops in hopes of finding a
6391 better format. The scheduler handles that. */
6393 xtensa_isa isa
= xtensa_default_isa
;
6394 xtensa_format format
;
6395 vliw_insn v_copy
= *vinsn
;
6396 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6398 if (vinsn
->num_slots
== 1)
6399 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6401 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6404 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6408 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6410 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6412 v_copy
.slots
[slot
].opcode
=
6413 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6414 v_copy
.slots
[slot
].ntok
= 0;
6417 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6420 else if (v_copy
.num_slots
> 1)
6423 /* Try the widened version. */
6424 if (!v_copy
.slots
[slot
].keep_wide
6425 && !v_copy
.slots
[slot
].is_specific_opcode
6426 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6428 && opcode_fits_format_slot (widened
.opcode
,
6431 v_copy
.slots
[slot
] = widened
;
6436 if (fit
== v_copy
.num_slots
)
6439 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6440 vinsn
->format
= format
;
6446 if (format
== xtensa_isa_num_formats (isa
))
6447 return XTENSA_UNDEFINED
;
6453 /* Return the additional space needed in a frag
6454 for possible relaxations of any ops in a VLIW insn.
6455 Also fill out the relaxations that might be required of
6456 each tinsn in the vinsn. */
6459 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6461 bfd_boolean finish_frag
= FALSE
;
6462 int extra_space
= 0;
6465 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6467 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6468 if (!tinsn_has_symbolic_operands (tinsn
))
6470 /* A narrow instruction could be widened later to help
6471 alignment issues. */
6472 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6473 && !tinsn
->is_specific_opcode
6474 && vinsn
->num_slots
== 1)
6476 /* Difference in bytes between narrow and wide insns... */
6478 tinsn
->subtype
= RELAX_NARROW
;
6483 if (workaround_b_j_loop_end
6484 && tinsn
->opcode
== xtensa_jx_opcode
6485 && use_transform ())
6487 /* Add 2 of these. */
6488 extra_space
+= 3; /* for the nop size */
6489 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6492 /* Need to assemble it with space for the relocation. */
6493 if (xg_is_relaxable_insn (tinsn
, 0)
6494 && !tinsn
->is_specific_opcode
)
6496 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6497 int max_literal_size
=
6498 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6500 tinsn
->literal_space
= max_literal_size
;
6502 tinsn
->subtype
= RELAX_IMMED
;
6503 extra_space
+= max_size
;
6507 /* A fix record will be added for this instruction prior
6508 to relaxation, so make it end the frag. */
6513 *pfinish_frag
= finish_frag
;
6519 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6521 xtensa_isa isa
= xtensa_default_isa
;
6522 int slot
, chosen_slot
;
6524 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6525 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6526 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6528 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6529 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6531 if (slot
== chosen_slot
)
6532 vinsn
->slots
[slot
] = *tinsn
;
6535 vinsn
->slots
[slot
].opcode
=
6536 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6537 vinsn
->slots
[slot
].ntok
= 0;
6538 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6545 emit_single_op (TInsn
*orig_insn
)
6548 IStack istack
; /* put instructions into here */
6549 symbolS
*lit_sym
= NULL
;
6550 symbolS
*label_sym
= NULL
;
6552 istack_init (&istack
);
6554 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6555 Because the scheduling and bundling characteristics of movi and
6556 l32r or const16 are so different, we can do much better if we relax
6557 it prior to scheduling and bundling, rather than after. */
6558 if ((orig_insn
->opcode
== xtensa_movi_opcode
6559 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6560 && !cur_vinsn
.inside_bundle
6561 && (orig_insn
->tok
[1].X_op
== O_symbol
6562 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6563 && !orig_insn
->is_specific_opcode
&& use_transform ())
6564 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6566 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6569 for (i
= 0; i
< istack
.ninsn
; i
++)
6571 TInsn
*insn
= &istack
.insn
[i
];
6572 switch (insn
->insn_type
)
6575 assert (lit_sym
== NULL
);
6576 lit_sym
= xg_assemble_literal (insn
);
6580 static int relaxed_sym_idx
= 0;
6581 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6582 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6584 assert (label_sym
== NULL
);
6585 label_sym
= symbol_find_or_make (label
);
6594 xg_resolve_literals (insn
, lit_sym
);
6596 xg_resolve_labels (insn
, label_sym
);
6598 bundle_tinsn (insn
, &v
);
6613 total_frag_text_expansion (fragS
*fragP
)
6616 int total_expansion
= 0;
6618 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6619 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6621 return total_expansion
;
6625 /* Emit a vliw instruction to the current fragment. */
6628 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6630 bfd_boolean finish_frag
;
6631 bfd_boolean is_jump
= FALSE
;
6632 bfd_boolean is_branch
= FALSE
;
6633 xtensa_isa isa
= xtensa_default_isa
;
6639 unsigned current_line
, best_linenum
;
6642 best_linenum
= UINT_MAX
;
6644 if (generating_literals
)
6646 static int reported
= 0;
6648 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6649 _("cannot assemble into a literal fragment"));
6656 if (frag_now_fix () != 0
6657 && (! frag_now
->tc_frag_data
.is_insn
6658 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6659 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6660 || (directive_state
[directive_longcalls
]
6661 != frag_now
->tc_frag_data
.use_longcalls
)
6662 || (directive_state
[directive_absolute_literals
]
6663 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6665 frag_wane (frag_now
);
6667 xtensa_set_frag_assembly_state (frag_now
);
6670 if (workaround_a0_b_retw
6671 && vinsn
->num_slots
== 1
6672 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6673 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6674 && use_transform ())
6676 has_a0_b_retw
= TRUE
;
6678 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6679 After the first assembly pass we will check all of them and
6680 add a nop if needed. */
6681 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6682 frag_var (rs_machine_dependent
, 4, 4,
6683 RELAX_ADD_NOP_IF_A0_B_RETW
,
6684 frag_now
->fr_symbol
,
6685 frag_now
->fr_offset
,
6687 xtensa_set_frag_assembly_state (frag_now
);
6688 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6689 frag_var (rs_machine_dependent
, 4, 4,
6690 RELAX_ADD_NOP_IF_A0_B_RETW
,
6691 frag_now
->fr_symbol
,
6692 frag_now
->fr_offset
,
6694 xtensa_set_frag_assembly_state (frag_now
);
6697 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6699 /* See if the instruction implies an aligned section. */
6700 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6701 record_alignment (now_seg
, 2);
6703 /* Also determine the best line number for debug info. */
6704 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6705 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6708 /* Special cases for instructions that force an alignment... */
6709 /* None of these opcodes are bundle-able. */
6710 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6714 /* Remember the symbol that marks the end of the loop in the frag
6715 that marks the start of the loop. This way we can easily find
6716 the end of the loop at the beginning, without adding special code
6717 to mark the loop instructions themselves. */
6718 symbolS
*target_sym
= NULL
;
6719 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6720 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6722 xtensa_set_frag_assembly_state (frag_now
);
6723 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6725 max_fill
= get_text_align_max_fill_size
6726 (get_text_align_power (xtensa_fetch_width
),
6727 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6729 if (use_transform ())
6730 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6731 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6733 frag_var (rs_machine_dependent
, 0, 0,
6734 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6735 xtensa_set_frag_assembly_state (frag_now
);
6737 xtensa_move_labels (frag_now
, 0, FALSE
);
6740 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6741 && !vinsn
->slots
[0].is_specific_opcode
)
6743 xtensa_mark_literal_pool_location ();
6744 xtensa_move_labels (frag_now
, 0, TRUE
);
6745 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6748 if (vinsn
->num_slots
== 1)
6750 if (workaround_a0_b_retw
&& use_transform ())
6751 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6752 is_register_writer (&vinsn
->slots
[0], "a", 0));
6754 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6755 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6758 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6760 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6762 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6764 /* vinsn_to_insnbuf will produce the error. */
6765 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6767 f
= frag_more (insn_size
+ extra_space
);
6768 xtensa_set_frag_assembly_state (frag_now
);
6769 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6772 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6773 if (vinsn
->format
== XTENSA_UNDEFINED
)
6776 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6778 /* Temporarily set the logical line number to the one we want to appear
6779 in the debug information. */
6780 as_where (¤t_file
, ¤t_line
);
6781 new_logical_line (current_file
, best_linenum
);
6782 dwarf2_emit_insn (insn_size
+ extra_space
);
6783 new_logical_line (current_file
, current_line
);
6785 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6787 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6788 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6789 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6790 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6791 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6792 if (tinsn
->literal_space
!= 0)
6793 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6795 if (tinsn
->subtype
== RELAX_NARROW
)
6796 assert (vinsn
->num_slots
== 1);
6797 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6799 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6802 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6803 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6807 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6808 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6812 frag_variant (rs_machine_dependent
,
6813 extra_space
, extra_space
, RELAX_SLOTS
,
6814 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6815 xtensa_set_frag_assembly_state (frag_now
);
6818 /* Special cases for loops:
6819 close_loop_end should be inserted AFTER short_loop.
6820 Make sure that CLOSE loops are processed BEFORE short_loops
6821 when converting them. */
6823 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6824 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6825 && !vinsn
->slots
[0].is_specific_opcode
)
6827 if (workaround_short_loop
&& use_transform ())
6829 maybe_has_short_loop
= TRUE
;
6830 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6831 frag_var (rs_machine_dependent
, 4, 4,
6832 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6833 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6834 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6835 frag_var (rs_machine_dependent
, 4, 4,
6836 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6837 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6840 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6841 loop at least 12 bytes away from another loop's end. */
6842 if (workaround_close_loop_end
&& use_transform ())
6844 maybe_has_close_loop_end
= TRUE
;
6845 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6846 frag_var (rs_machine_dependent
, 12, 12,
6847 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6848 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6852 if (use_transform ())
6856 assert (finish_frag
);
6857 frag_var (rs_machine_dependent
,
6858 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6860 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6861 xtensa_set_frag_assembly_state (frag_now
);
6863 else if (is_branch
&& do_align_targets ())
6865 assert (finish_frag
);
6866 frag_var (rs_machine_dependent
,
6867 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6868 RELAX_MAYBE_UNREACHABLE
,
6869 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6870 xtensa_set_frag_assembly_state (frag_now
);
6871 frag_var (rs_machine_dependent
,
6873 RELAX_MAYBE_DESIRE_ALIGN
,
6874 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6875 xtensa_set_frag_assembly_state (frag_now
);
6879 /* Now, if the original opcode was a call... */
6880 if (do_align_targets ()
6881 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6883 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6884 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6885 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6886 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6887 xtensa_set_frag_assembly_state (frag_now
);
6890 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6892 frag_wane (frag_now
);
6894 xtensa_set_frag_assembly_state (frag_now
);
6899 /* xtensa_end and helper functions. */
6901 static void xtensa_cleanup_align_frags (void);
6902 static void xtensa_fix_target_frags (void);
6903 static void xtensa_mark_narrow_branches (void);
6904 static void xtensa_mark_zcl_first_insns (void);
6905 static void xtensa_fix_a0_b_retw_frags (void);
6906 static void xtensa_fix_b_j_loop_end_frags (void);
6907 static void xtensa_fix_close_loop_end_frags (void);
6908 static void xtensa_fix_short_loop_frags (void);
6909 static void xtensa_sanity_check (void);
6910 static void xtensa_add_config_info (void);
6915 directive_balance ();
6916 xtensa_flush_pending_output ();
6918 past_xtensa_end
= TRUE
;
6920 xtensa_move_literals ();
6922 xtensa_reorder_segments ();
6923 xtensa_cleanup_align_frags ();
6924 xtensa_fix_target_frags ();
6925 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6926 xtensa_fix_a0_b_retw_frags ();
6927 if (workaround_b_j_loop_end
)
6928 xtensa_fix_b_j_loop_end_frags ();
6930 /* "close_loop_end" should be processed BEFORE "short_loop". */
6931 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6932 xtensa_fix_close_loop_end_frags ();
6934 if (workaround_short_loop
&& maybe_has_short_loop
)
6935 xtensa_fix_short_loop_frags ();
6937 xtensa_mark_narrow_branches ();
6938 xtensa_mark_zcl_first_insns ();
6940 xtensa_sanity_check ();
6942 xtensa_add_config_info ();
6947 xtensa_cleanup_align_frags (void)
6952 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6953 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6956 /* Walk over all of the fragments in a subsection. */
6957 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6959 if ((fragP
->fr_type
== rs_align
6960 || fragP
->fr_type
== rs_align_code
6961 || (fragP
->fr_type
== rs_machine_dependent
6962 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6963 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6964 && fragP
->fr_fix
== 0)
6966 fragS
*next
= fragP
->fr_next
;
6969 && next
->fr_fix
== 0
6970 && next
->fr_type
== rs_machine_dependent
6971 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6974 next
= next
->fr_next
;
6977 /* If we don't widen branch targets, then they
6978 will be easier to align. */
6979 if (fragP
->tc_frag_data
.is_branch_target
6980 && fragP
->fr_opcode
== fragP
->fr_literal
6981 && fragP
->fr_type
== rs_machine_dependent
6982 && fragP
->fr_subtype
== RELAX_SLOTS
6983 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6985 if (fragP
->fr_type
== rs_machine_dependent
6986 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6987 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
6993 /* Re-process all of the fragments looking to convert all of the
6994 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
6995 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
6996 Otherwise, convert to a .fill 0. */
6999 xtensa_fix_target_frags (void)
7004 /* When this routine is called, all of the subsections are still intact
7005 so we walk over subsections instead of sections. */
7006 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7007 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7011 /* Walk over all of the fragments in a subsection. */
7012 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7014 if (fragP
->fr_type
== rs_machine_dependent
7015 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7017 if (next_frag_is_branch_target (fragP
))
7018 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7027 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7030 xtensa_mark_narrow_branches (void)
7035 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7036 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7039 /* Walk over all of the fragments in a subsection. */
7040 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7042 if (fragP
->fr_type
== rs_machine_dependent
7043 && fragP
->fr_subtype
== RELAX_SLOTS
7044 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7048 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7049 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7051 if (vinsn
.num_slots
== 1
7052 && xtensa_opcode_is_branch (xtensa_default_isa
,
7053 vinsn
.slots
[0].opcode
) == 1
7054 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7055 && is_narrow_branch_guaranteed_in_range (fragP
,
7058 fragP
->fr_subtype
= RELAX_SLOTS
;
7059 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7060 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7068 /* A branch is typically widened only when its target is out of
7069 range. However, we would like to widen them to align a subsequent
7070 branch target when possible.
7072 Because the branch relaxation code is so convoluted, the optimal solution
7073 (combining the two cases) is difficult to get right in all circumstances.
7074 We therefore go with an "almost as good" solution, where we only
7075 use for alignment narrow branches that definitely will not expand to a
7076 jump and a branch. These functions find and mark these cases. */
7078 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7079 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7080 We start counting beginning with the frag after the 2-byte branch, so the
7081 maximum offset is (4 - 2) + 63 = 65. */
7082 #define MAX_IMMED6 65
7084 static offsetT
unrelaxed_frag_max_size (fragS
*);
7087 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7089 const expressionS
*expr
= &tinsn
->tok
[1];
7090 symbolS
*symbolP
= expr
->X_add_symbol
;
7091 offsetT max_distance
= expr
->X_add_number
;
7094 if (expr
->X_op
!= O_symbol
)
7097 target_frag
= symbol_get_frag (symbolP
);
7099 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7100 if (is_branch_jmp_to_next (tinsn
, fragP
))
7103 /* The branch doesn't branch over it's own frag,
7104 but over the subsequent ones. */
7105 fragP
= fragP
->fr_next
;
7106 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7108 max_distance
+= unrelaxed_frag_max_size (fragP
);
7109 fragP
= fragP
->fr_next
;
7111 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7118 xtensa_mark_zcl_first_insns (void)
7123 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7124 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7127 /* Walk over all of the fragments in a subsection. */
7128 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7130 if (fragP
->fr_type
== rs_machine_dependent
7131 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7132 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7134 /* Find the loop frag. */
7135 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7136 /* Find the first insn frag. */
7137 targ_frag
= next_non_empty_frag (targ_frag
);
7139 /* Of course, sometimes (mostly for toy test cases) a
7140 zero-cost loop instruction is the last in a section. */
7143 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7144 /* Do not widen a frag that is the first instruction of a
7145 zero-cost loop. It makes that loop harder to align. */
7146 if (targ_frag
->fr_type
== rs_machine_dependent
7147 && targ_frag
->fr_subtype
== RELAX_SLOTS
7148 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7151 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7152 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7155 frag_wane (targ_frag
);
7156 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7160 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7168 /* Re-process all of the fragments looking to convert all of the
7169 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7170 conditional branch or a retw/retw.n, convert this frag to one that
7171 will generate a NOP. In any case close it off with a .fill 0. */
7173 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7176 xtensa_fix_a0_b_retw_frags (void)
7181 /* When this routine is called, all of the subsections are still intact
7182 so we walk over subsections instead of sections. */
7183 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7184 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7188 /* Walk over all of the fragments in a subsection. */
7189 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7191 if (fragP
->fr_type
== rs_machine_dependent
7192 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7194 if (next_instrs_are_b_retw (fragP
))
7196 if (fragP
->tc_frag_data
.is_no_transform
)
7197 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7199 relax_frag_add_nop (fragP
);
7209 next_instrs_are_b_retw (fragS
*fragP
)
7211 xtensa_opcode opcode
;
7213 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7214 static xtensa_insnbuf insnbuf
= NULL
;
7215 static xtensa_insnbuf slotbuf
= NULL
;
7216 xtensa_isa isa
= xtensa_default_isa
;
7219 bfd_boolean branch_seen
= FALSE
;
7223 insnbuf
= xtensa_insnbuf_alloc (isa
);
7224 slotbuf
= xtensa_insnbuf_alloc (isa
);
7227 if (next_fragP
== NULL
)
7230 /* Check for the conditional branch. */
7231 xtensa_insnbuf_from_chars
7232 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7233 fmt
= xtensa_format_decode (isa
, insnbuf
);
7234 if (fmt
== XTENSA_UNDEFINED
)
7237 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7239 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7240 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7242 branch_seen
= (branch_seen
7243 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7249 offset
+= xtensa_format_length (isa
, fmt
);
7250 if (offset
== next_fragP
->fr_fix
)
7252 next_fragP
= next_non_empty_frag (next_fragP
);
7256 if (next_fragP
== NULL
)
7259 /* Check for the retw/retw.n. */
7260 xtensa_insnbuf_from_chars
7261 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7262 fmt
= xtensa_format_decode (isa
, insnbuf
);
7264 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7265 have no problems. */
7266 if (fmt
== XTENSA_UNDEFINED
7267 || xtensa_format_num_slots (isa
, fmt
) != 1)
7270 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7271 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7273 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7280 /* Re-process all of the fragments looking to convert all of the
7281 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7282 loop end label, convert this frag to one that will generate a NOP.
7283 In any case close it off with a .fill 0. */
7285 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7288 xtensa_fix_b_j_loop_end_frags (void)
7293 /* When this routine is called, all of the subsections are still intact
7294 so we walk over subsections instead of sections. */
7295 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7296 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7300 /* Walk over all of the fragments in a subsection. */
7301 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7303 if (fragP
->fr_type
== rs_machine_dependent
7304 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7306 if (next_instr_is_loop_end (fragP
))
7308 if (fragP
->tc_frag_data
.is_no_transform
)
7309 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7311 relax_frag_add_nop (fragP
);
7321 next_instr_is_loop_end (fragS
*fragP
)
7323 const fragS
*next_fragP
;
7325 if (next_frag_is_loop_target (fragP
))
7328 next_fragP
= next_non_empty_frag (fragP
);
7329 if (next_fragP
== NULL
)
7332 if (!next_frag_is_loop_target (next_fragP
))
7335 /* If the size is >= 3 then there is more than one instruction here.
7336 The hardware bug will not fire. */
7337 if (next_fragP
->fr_fix
> 3)
7344 /* Re-process all of the fragments looking to convert all of the
7345 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7346 not MY loop's loop end within 12 bytes, add enough nops here to
7347 make it at least 12 bytes away. In any case close it off with a
7350 static offsetT min_bytes_to_other_loop_end
7351 (fragS
*, fragS
*, offsetT
);
7354 xtensa_fix_close_loop_end_frags (void)
7359 /* When this routine is called, all of the subsections are still intact
7360 so we walk over subsections instead of sections. */
7361 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7362 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7366 fragS
*current_target
= NULL
;
7368 /* Walk over all of the fragments in a subsection. */
7369 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7371 if (fragP
->fr_type
== rs_machine_dependent
7372 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7373 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7374 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7377 && fragP
->fr_type
== rs_machine_dependent
7378 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7381 int bytes_added
= 0;
7383 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7384 /* Max out at 12. */
7385 min_bytes
= min_bytes_to_other_loop_end
7386 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7388 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7390 if (fragP
->tc_frag_data
.is_no_transform
)
7391 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7394 while (min_bytes
+ bytes_added
7395 < REQUIRED_LOOP_DIVIDING_BYTES
)
7399 if (fragP
->fr_var
< length
)
7400 as_fatal (_("fr_var %lu < length %d"),
7401 (long) fragP
->fr_var
, length
);
7404 assemble_nop (length
,
7405 fragP
->fr_literal
+ fragP
->fr_fix
);
7406 fragP
->fr_fix
+= length
;
7407 fragP
->fr_var
-= length
;
7409 bytes_added
+= length
;
7415 assert (fragP
->fr_type
!= rs_machine_dependent
7416 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7422 static offsetT
unrelaxed_frag_min_size (fragS
*);
7425 min_bytes_to_other_loop_end (fragS
*fragP
,
7426 fragS
*current_target
,
7430 fragS
*current_fragP
;
7432 for (current_fragP
= fragP
;
7434 current_fragP
= current_fragP
->fr_next
)
7436 if (current_fragP
->tc_frag_data
.is_loop_target
7437 && current_fragP
!= current_target
)
7440 offset
+= unrelaxed_frag_min_size (current_fragP
);
7442 if (offset
>= max_size
)
7450 unrelaxed_frag_min_size (fragS
*fragP
)
7452 offsetT size
= fragP
->fr_fix
;
7454 /* Add fill size. */
7455 if (fragP
->fr_type
== rs_fill
)
7456 size
+= fragP
->fr_offset
;
7463 unrelaxed_frag_max_size (fragS
*fragP
)
7465 offsetT size
= fragP
->fr_fix
;
7466 switch (fragP
->fr_type
)
7469 /* Empty frags created by the obstack allocation scheme
7470 end up with type 0. */
7475 size
+= fragP
->fr_offset
;
7483 /* No further adjustments needed. */
7485 case rs_machine_dependent
:
7486 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7487 size
+= fragP
->fr_var
;
7490 /* We had darn well better know how big it is. */
7499 /* Re-process all of the fragments looking to convert all
7500 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7503 1) the instruction size count to the loop end label
7504 is too short (<= 2 instructions),
7505 2) loop has a jump or branch in it
7508 1) workaround_all_short_loops is TRUE
7509 2) The generating loop was a 'loopgtz' or 'loopnez'
7510 3) the instruction size count to the loop end label is too short
7512 then convert this frag (and maybe the next one) to generate a NOP.
7513 In any case close it off with a .fill 0. */
7515 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7516 static bfd_boolean
branch_before_loop_end (fragS
*);
7519 xtensa_fix_short_loop_frags (void)
7524 /* When this routine is called, all of the subsections are still intact
7525 so we walk over subsections instead of sections. */
7526 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7527 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7530 fragS
*current_target
= NULL
;
7531 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7533 /* Walk over all of the fragments in a subsection. */
7534 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7536 if (fragP
->fr_type
== rs_machine_dependent
7537 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7538 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7541 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7542 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7543 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7544 current_opcode
= t_insn
.opcode
;
7545 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7546 current_opcode
) == 1);
7549 if (fragP
->fr_type
== rs_machine_dependent
7550 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7552 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7553 && (branch_before_loop_end (fragP
->fr_next
)
7554 || (workaround_all_short_loops
7555 && current_opcode
!= XTENSA_UNDEFINED
7556 && current_opcode
!= xtensa_loop_opcode
)))
7558 if (fragP
->tc_frag_data
.is_no_transform
)
7559 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7561 relax_frag_add_nop (fragP
);
7570 static int unrelaxed_frag_min_insn_count (fragS
*);
7573 count_insns_to_loop_end (fragS
*base_fragP
,
7574 bfd_boolean count_relax_add
,
7577 fragS
*fragP
= NULL
;
7582 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7584 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7585 if (insn_count
>= max_count
)
7588 if (count_relax_add
)
7590 if (fragP
->fr_type
== rs_machine_dependent
7591 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7593 /* In order to add the appropriate number of
7594 NOPs, we count an instruction for downstream
7597 if (insn_count
>= max_count
)
7607 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7609 xtensa_isa isa
= xtensa_default_isa
;
7610 static xtensa_insnbuf insnbuf
= NULL
;
7614 if (!fragP
->tc_frag_data
.is_insn
)
7618 insnbuf
= xtensa_insnbuf_alloc (isa
);
7620 /* Decode the fixed instructions. */
7621 while (offset
< fragP
->fr_fix
)
7625 xtensa_insnbuf_from_chars
7626 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7627 fmt
= xtensa_format_decode (isa
, insnbuf
);
7629 if (fmt
== XTENSA_UNDEFINED
)
7631 as_fatal (_("undecodable instruction in instruction frag"));
7634 offset
+= xtensa_format_length (isa
, fmt
);
7642 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7645 branch_before_loop_end (fragS
*base_fragP
)
7649 for (fragP
= base_fragP
;
7650 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7651 fragP
= fragP
->fr_next
)
7653 if (unrelaxed_frag_has_b_j (fragP
))
7661 unrelaxed_frag_has_b_j (fragS
*fragP
)
7663 static xtensa_insnbuf insnbuf
= NULL
;
7664 xtensa_isa isa
= xtensa_default_isa
;
7667 if (!fragP
->tc_frag_data
.is_insn
)
7671 insnbuf
= xtensa_insnbuf_alloc (isa
);
7673 /* Decode the fixed instructions. */
7674 while (offset
< fragP
->fr_fix
)
7679 xtensa_insnbuf_from_chars
7680 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7681 fmt
= xtensa_format_decode (isa
, insnbuf
);
7682 if (fmt
== XTENSA_UNDEFINED
)
7685 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7687 xtensa_opcode opcode
=
7688 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7689 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7690 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7693 offset
+= xtensa_format_length (isa
, fmt
);
7699 /* Checks to be made after initial assembly but before relaxation. */
7701 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7702 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7705 xtensa_sanity_check (void)
7712 as_where (&file_name
, &line
);
7713 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7714 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7718 /* Walk over all of the fragments in a subsection. */
7719 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7721 if (fragP
->fr_type
== rs_machine_dependent
7722 && fragP
->fr_subtype
== RELAX_SLOTS
7723 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7725 static xtensa_insnbuf insnbuf
= NULL
;
7728 if (fragP
->fr_opcode
!= NULL
)
7731 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7732 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7733 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7735 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7736 t_insn
.opcode
) == 1)
7738 if (is_empty_loop (&t_insn
, fragP
))
7740 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7741 as_bad (_("invalid empty loop"));
7743 if (!is_local_forward_loop (&t_insn
, fragP
))
7745 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7746 as_bad (_("loop target does not follow "
7747 "loop instruction in section"));
7754 new_logical_line (file_name
, line
);
7758 #define LOOP_IMMED_OPN 1
7760 /* Return TRUE if the loop target is the next non-zero fragment. */
7763 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7765 const expressionS
*expr
;
7769 if (insn
->insn_type
!= ITYPE_INSN
)
7772 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7775 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7778 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7780 if (expr
->X_op
!= O_symbol
)
7783 symbolP
= expr
->X_add_symbol
;
7787 if (symbol_get_frag (symbolP
) == NULL
)
7790 if (S_GET_VALUE (symbolP
) != 0)
7793 /* Walk through the zero-size fragments from this one. If we find
7794 the target fragment, then this is a zero-size loop. */
7796 for (next_fragP
= fragP
->fr_next
;
7798 next_fragP
= next_fragP
->fr_next
)
7800 if (next_fragP
== symbol_get_frag (symbolP
))
7802 if (next_fragP
->fr_fix
!= 0)
7810 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7812 const expressionS
*expr
;
7816 if (insn
->insn_type
!= ITYPE_INSN
)
7819 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7822 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7825 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7827 if (expr
->X_op
!= O_symbol
)
7830 symbolP
= expr
->X_add_symbol
;
7834 if (symbol_get_frag (symbolP
) == NULL
)
7837 /* Walk through fragments until we find the target.
7838 If we do not find the target, then this is an invalid loop. */
7840 for (next_fragP
= fragP
->fr_next
;
7842 next_fragP
= next_fragP
->fr_next
)
7844 if (next_fragP
== symbol_get_frag (symbolP
))
7852 #define XTINFO_NAME "Xtensa_Info"
7853 #define XTINFO_NAMESZ 12
7854 #define XTINFO_TYPE 1
7857 xtensa_add_config_info (void)
7863 info_sec
= subseg_new (".xtensa.info", 0);
7864 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7866 data
= xmalloc (100);
7867 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7868 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
7869 sz
= strlen (data
) + 1;
7871 /* Add enough null terminators to pad to a word boundary. */
7874 while ((sz
& 3) != 0);
7876 /* Follow the standard note section layout:
7877 First write the length of the name string. */
7879 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
7881 /* Next comes the length of the "descriptor", i.e., the actual data. */
7883 md_number_to_chars (p
, (valueT
) sz
, 4);
7885 /* Write the note type. */
7887 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
7889 /* Write the name field. */
7890 p
= frag_more (XTINFO_NAMESZ
);
7891 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
7893 /* Finally, write the descriptor. */
7895 memcpy (p
, data
, sz
);
7901 /* Alignment Functions. */
7904 get_text_align_power (unsigned target_size
)
7906 if (target_size
<= 4)
7908 assert (target_size
== 8);
7914 get_text_align_max_fill_size (int align_pow
,
7915 bfd_boolean use_nops
,
7916 bfd_boolean use_no_density
)
7919 return (1 << align_pow
);
7921 return 3 * (1 << align_pow
);
7923 return 1 + (1 << align_pow
);
7927 /* Calculate the minimum bytes of fill needed at "address" to align a
7928 target instruction of size "target_size" so that it does not cross a
7929 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7930 the fill can be an arbitrary number of bytes. Otherwise, the space must
7931 be filled by NOP instructions. */
7934 get_text_align_fill_size (addressT address
,
7937 bfd_boolean use_nops
,
7938 bfd_boolean use_no_density
)
7940 addressT alignment
, fill
, fill_limit
, fill_step
;
7941 bfd_boolean skip_one
= FALSE
;
7943 alignment
= (1 << align_pow
);
7944 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7948 fill_limit
= alignment
;
7951 else if (!use_no_density
)
7953 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7954 fill_limit
= alignment
* 2;
7960 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7961 fill_limit
= alignment
* 3;
7965 /* Try all fill sizes until finding one that works. */
7966 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7968 if (skip_one
&& fill
== 1)
7970 if ((address
+ fill
) >> align_pow
7971 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7980 branch_align_power (segT sec
)
7982 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7983 is aligned to at least an 8-byte boundary, then a branch target need
7984 only fit within an 8-byte aligned block of memory to avoid a stall.
7985 Otherwise, try to fit branch targets within 4-byte aligned blocks
7986 (which may be insufficient, e.g., if the section has no alignment, but
7987 it's good enough). */
7988 if (xtensa_fetch_width
== 8)
7990 if (get_recorded_alignment (sec
) >= 3)
7994 assert (xtensa_fetch_width
== 4);
8000 /* This will assert if it is not possible. */
8003 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8009 assert (fill_size
% 3 == 0);
8010 return (fill_size
/ 3);
8013 assert (fill_size
!= 1); /* Bad argument. */
8015 while (fill_size
> 1)
8018 if (fill_size
== 2 || fill_size
== 4)
8020 fill_size
-= insn_size
;
8023 assert (fill_size
!= 1); /* Bad algorithm. */
8029 get_text_align_nth_nop_size (offsetT fill_size
,
8031 bfd_boolean use_no_density
)
8038 assert (fill_size
!= 1); /* Bad argument. */
8040 while (fill_size
> 1)
8043 if (fill_size
== 2 || fill_size
== 4)
8045 fill_size
-= insn_size
;
8055 /* For the given fragment, find the appropriate address
8056 for it to begin at if we are using NOPs to align it. */
8059 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8061 /* The rule is: get next fragment's FIRST instruction. Find
8062 the smallest number of bytes that need to be added to
8063 ensure that the next fragment's FIRST instruction will fit
8066 E.G., 2 bytes : 0, 1, 2 mod 4
8069 If the FIRST instruction MIGHT be relaxed,
8070 assume that it will become a 3-byte instruction.
8072 Note again here that LOOP instructions are not bundleable,
8073 and this relaxation only applies to LOOP opcodes. */
8076 int first_insn_size
;
8078 addressT pre_opcode_bytes
;
8081 xtensa_opcode opcode
;
8082 bfd_boolean is_loop
;
8084 assert (fragP
->fr_type
== rs_machine_dependent
);
8085 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8087 /* Find the loop frag. */
8088 first_insn
= next_non_empty_frag (fragP
);
8089 /* Now find the first insn frag. */
8090 first_insn
= next_non_empty_frag (first_insn
);
8092 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8094 loop_insn_size
= xg_get_single_size (opcode
);
8096 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8097 pre_opcode_bytes
+= loop_insn_size
;
8099 /* For loops, the alignment depends on the size of the
8100 instruction following the loop, not the LOOP instruction. */
8102 if (first_insn
== NULL
)
8103 first_insn_size
= xtensa_fetch_width
;
8105 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8107 /* If it was 8, then we'll need a larger alignment for the section. */
8108 align_power
= get_text_align_power (first_insn_size
);
8109 record_alignment (now_seg
, align_power
);
8111 fill_size
= get_text_align_fill_size
8112 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8113 fragP
->tc_frag_data
.is_no_density
);
8115 return address
+ fill_size
;
8119 /* 3 mechanisms for relaxing an alignment:
8121 Align to a power of 2.
8122 Align so the next fragment's instruction does not cross a word boundary.
8123 Align the current instruction so that if the next instruction
8124 were 3 bytes, it would not cross a word boundary.
8128 zeros - This is easy; always insert zeros.
8129 nops - 3-byte and 2-byte instructions
8133 >=5 : 3-byte instruction + fn (n-3)
8134 widening - widen previous instructions. */
8137 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8139 addressT target_address
, loop_insn_offset
;
8141 xtensa_opcode loop_opcode
;
8142 bfd_boolean is_loop
;
8145 offsetT branch_align
;
8147 assert (fragP
->fr_type
== rs_machine_dependent
);
8148 switch (fragP
->fr_subtype
)
8150 case RELAX_DESIRE_ALIGN
:
8151 target_size
= next_frag_format_size (fragP
);
8152 if (target_size
== XTENSA_UNDEFINED
)
8154 align_power
= branch_align_power (now_seg
);
8155 branch_align
= 1 << align_power
;
8156 /* Don't count on the section alignment being as large as the target. */
8157 if (target_size
> branch_align
)
8158 target_size
= branch_align
;
8159 opt_diff
= get_text_align_fill_size (address
, align_power
,
8160 target_size
, FALSE
, FALSE
);
8162 *max_diff
= (opt_diff
+ branch_align
8163 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8164 assert (*max_diff
>= opt_diff
);
8167 case RELAX_ALIGN_NEXT_OPCODE
:
8168 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8169 loop_insn_offset
= 0;
8170 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8173 /* If the loop has been expanded then the LOOP instruction
8174 could be at an offset from this fragment. */
8175 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8177 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8179 /* In an ideal world, which is what we are shooting for here,
8180 we wouldn't need to use any NOPs immediately prior to the
8181 LOOP instruction. If this approach fails, relax_frag_loop_align
8182 will call get_noop_aligned_address. */
8184 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8185 align_power
= get_text_align_power (target_size
),
8186 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8187 target_size
, FALSE
, FALSE
);
8189 *max_diff
= xtensa_fetch_width
8190 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8191 - target_size
+ opt_diff
;
8192 assert (*max_diff
>= opt_diff
);
8203 /* md_relax_frag Hook and Helper Functions. */
8205 static long relax_frag_loop_align (fragS
*, long);
8206 static long relax_frag_for_align (fragS
*, long);
8207 static long relax_frag_immed
8208 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8211 /* Return the number of bytes added to this fragment, given that the
8212 input has been stretched already by "stretch". */
8215 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8217 xtensa_isa isa
= xtensa_default_isa
;
8218 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8219 long new_stretch
= 0;
8223 static xtensa_insnbuf vbuf
= NULL
;
8224 int slot
, num_slots
;
8227 as_where (&file_name
, &line
);
8228 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8230 fragP
->tc_frag_data
.unreported_expansion
= 0;
8232 switch (fragP
->fr_subtype
)
8234 case RELAX_ALIGN_NEXT_OPCODE
:
8235 /* Always convert. */
8236 if (fragP
->tc_frag_data
.relax_seen
)
8237 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8240 case RELAX_LOOP_END
:
8244 case RELAX_LOOP_END_ADD_NOP
:
8245 /* Add a NOP and switch to .fill 0. */
8246 new_stretch
= relax_frag_add_nop (fragP
);
8250 case RELAX_DESIRE_ALIGN
:
8251 /* Do nothing. The narrowing before this frag will either align
8256 case RELAX_LITERAL_FINAL
:
8259 case RELAX_LITERAL_NR
:
8261 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8262 assert (unreported
== lit_size
);
8263 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8264 fragP
->fr_var
-= lit_size
;
8265 fragP
->fr_fix
+= lit_size
;
8271 vbuf
= xtensa_insnbuf_alloc (isa
);
8273 xtensa_insnbuf_from_chars
8274 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8275 fmt
= xtensa_format_decode (isa
, vbuf
);
8276 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8278 for (slot
= 0; slot
< num_slots
; slot
++)
8280 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8283 if (fragP
->tc_frag_data
.relax_seen
)
8284 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8288 case RELAX_IMMED_STEP1
:
8289 case RELAX_IMMED_STEP2
:
8290 /* Place the immediate. */
8291 new_stretch
+= relax_frag_immed
8292 (now_seg
, fragP
, stretch
,
8293 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8294 fmt
, slot
, stretched_p
, FALSE
);
8298 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8304 case RELAX_LITERAL_POOL_BEGIN
:
8305 case RELAX_LITERAL_POOL_END
:
8306 case RELAX_MAYBE_UNREACHABLE
:
8307 case RELAX_MAYBE_DESIRE_ALIGN
:
8308 /* No relaxation required. */
8311 case RELAX_FILL_NOP
:
8312 case RELAX_UNREACHABLE
:
8313 if (fragP
->tc_frag_data
.relax_seen
)
8314 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8318 as_bad (_("bad relaxation state"));
8321 /* Tell gas we need another relaxation pass. */
8322 if (! fragP
->tc_frag_data
.relax_seen
)
8324 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8328 new_logical_line (file_name
, line
);
8334 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8336 addressT old_address
, old_next_address
, old_size
;
8337 addressT new_address
, new_next_address
, new_size
;
8340 /* All the frags with relax_frag_for_alignment prior to this one in the
8341 section have been done, hopefully eliminating the need for a NOP here.
8342 But, this will put it in if necessary. */
8344 /* Calculate the old address of this fragment and the next fragment. */
8345 old_address
= fragP
->fr_address
- stretch
;
8346 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8347 fragP
->tc_frag_data
.text_expansion
[0]);
8348 old_size
= old_next_address
- old_address
;
8350 /* Calculate the new address of this fragment and the next fragment. */
8351 new_address
= fragP
->fr_address
;
8353 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8354 new_size
= new_next_address
- new_address
;
8356 growth
= new_size
- old_size
;
8358 /* Fix up the text_expansion field and return the new growth. */
8359 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8364 /* Add a NOP instruction. */
8367 relax_frag_add_nop (fragS
*fragP
)
8369 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8370 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8371 assemble_nop (length
, nop_buf
);
8372 fragP
->tc_frag_data
.is_insn
= TRUE
;
8374 if (fragP
->fr_var
< length
)
8376 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8380 fragP
->fr_fix
+= length
;
8381 fragP
->fr_var
-= length
;
8386 static long future_alignment_required (fragS
*, long);
8389 relax_frag_for_align (fragS
*fragP
, long stretch
)
8391 /* Overview of the relaxation procedure for alignment:
8392 We can widen with NOPs or by widening instructions or by filling
8393 bytes after jump instructions. Find the opportune places and widen
8394 them if necessary. */
8399 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8400 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8401 || (fragP
->fr_subtype
== RELAX_SLOTS
8402 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8404 stretch_me
= future_alignment_required (fragP
, stretch
);
8405 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8411 /* We expanded on a previous pass. Can we shrink now? */
8412 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8413 if (shrink
<= stretch
&& stretch
> 0)
8415 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8421 /* Below here, diff > 0. */
8422 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8428 /* Return the address of the next frag that should be aligned.
8430 By "address" we mean the address it _would_ be at if there
8431 is no action taken to align it between here and the target frag.
8432 In other words, if no narrows and no fill nops are used between
8433 here and the frag to align, _even_if_ some of the frags we use
8434 to align targets have already expanded on a previous relaxation
8437 Also, count each frag that may be used to help align the target.
8439 Return 0 if there are no frags left in the chain that need to be
8443 find_address_of_next_align_frag (fragS
**fragPP
,
8447 bfd_boolean
*paddable
)
8449 fragS
*fragP
= *fragPP
;
8450 addressT address
= fragP
->fr_address
;
8452 /* Do not reset the counts to 0. */
8456 /* Limit this to a small search. */
8457 if (*widens
>= (int) xtensa_fetch_width
)
8462 address
+= fragP
->fr_fix
;
8464 if (fragP
->fr_type
== rs_fill
)
8465 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8466 else if (fragP
->fr_type
== rs_machine_dependent
)
8468 switch (fragP
->fr_subtype
)
8470 case RELAX_UNREACHABLE
:
8474 case RELAX_FILL_NOP
:
8476 if (!fragP
->tc_frag_data
.is_no_density
)
8481 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8486 address
+= total_frag_text_expansion (fragP
);;
8490 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8493 case RELAX_ALIGN_NEXT_OPCODE
:
8494 case RELAX_DESIRE_ALIGN
:
8498 case RELAX_MAYBE_UNREACHABLE
:
8499 case RELAX_MAYBE_DESIRE_ALIGN
:
8504 /* Just punt if we don't know the type. */
8511 /* Just punt if we don't know the type. */
8515 fragP
= fragP
->fr_next
;
8523 static long bytes_to_stretch (fragS
*, int, int, int, int);
8526 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8528 fragS
*this_frag
= fragP
;
8532 int narrow_nops
= 0;
8533 bfd_boolean paddable
= FALSE
;
8534 offsetT local_opt_diff
;
8537 int stretch_amount
= 0;
8538 int local_stretch_amount
;
8539 int global_stretch_amount
;
8541 address
= find_address_of_next_align_frag
8542 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8546 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8547 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8549 frag_wane (this_frag
);
8553 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8554 opt_diff
= local_opt_diff
;
8555 assert (opt_diff
>= 0);
8556 assert (max_diff
>= opt_diff
);
8561 fragP
= fragP
->fr_next
;
8563 while (fragP
&& opt_diff
< max_diff
&& address
)
8565 /* We only use these to determine if we can exit early
8566 because there will be plenty of ways to align future
8568 int glob_widens
= 0;
8571 bfd_boolean glob_pad
= 0;
8572 address
= find_address_of_next_align_frag
8573 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8574 /* If there is a padable portion, then skip. */
8575 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8580 offsetT next_m_diff
;
8581 offsetT next_o_diff
;
8583 /* Downrange frags haven't had stretch added to them yet. */
8586 /* The address also includes any text expansion from this
8587 frag in a previous pass, but we don't want that. */
8588 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8590 /* Assume we are going to move at least opt_diff. In
8591 reality, we might not be able to, but assuming that
8592 we will helps catch cases where moving opt_diff pushes
8593 the next target from aligned to unaligned. */
8594 address
+= opt_diff
;
8596 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8598 /* Now cleanup for the adjustments to address. */
8599 next_o_diff
+= opt_diff
;
8600 next_m_diff
+= opt_diff
;
8601 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8602 opt_diff
= next_o_diff
;
8603 if (next_m_diff
< max_diff
)
8604 max_diff
= next_m_diff
;
8605 fragP
= fragP
->fr_next
;
8609 /* If there are enough wideners in between, do it. */
8612 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8614 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8619 local_stretch_amount
8620 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8621 num_widens
, local_opt_diff
);
8622 global_stretch_amount
8623 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8624 num_widens
, opt_diff
);
8625 /* If the condition below is true, then the frag couldn't
8626 stretch the correct amount for the global case, so we just
8627 optimize locally. We'll rely on the subsequent frags to get
8628 the correct alignment in the global case. */
8629 if (global_stretch_amount
< local_stretch_amount
)
8630 stretch_amount
= local_stretch_amount
;
8632 stretch_amount
= global_stretch_amount
;
8634 if (this_frag
->fr_subtype
== RELAX_SLOTS
8635 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8636 assert (stretch_amount
<= 1);
8637 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8639 if (this_frag
->tc_frag_data
.is_no_density
)
8640 assert (stretch_amount
== 3 || stretch_amount
== 0);
8642 assert (stretch_amount
<= 3);
8645 return stretch_amount
;
8649 /* The idea: widen everything you can to get a target or loop aligned,
8650 then start using NOPs.
8652 When we must have a NOP, here is a table of how we decide
8653 (so you don't have to fight through the control flow below):
8655 wide_nops = the number of wide NOPs available for aligning
8656 narrow_nops = the number of narrow NOPs available for aligning
8657 (a subset of wide_nops)
8658 widens = the number of narrow instructions that should be widened
8665 b 0 1 1 (case 3a makes this case unnecessary)
8668 c 0 1 2 (case 4a makes this case unnecessary)
8671 c 0 2 1 (case 5b makes this case unnecessary)
8674 c 0 1 4 (case 6b makes this case unnecessary)
8675 d 1 1 1 (case 6a makes this case unnecessary)
8676 e 0 2 2 (case 6a makes this case unnecessary)
8677 f 0 3 0 (case 6a makes this case unnecessary)
8680 c 1 1 2 (case 7b makes this case unnecessary)
8681 d 0 1 5 (case 7a makes this case unnecessary)
8682 e 0 2 3 (case 7b makes this case unnecessary)
8683 f 0 3 1 (case 7b makes this case unnecessary)
8684 g 1 2 1 (case 7b makes this case unnecessary)
8688 bytes_to_stretch (fragS
*this_frag
,
8694 int bytes_short
= desired_diff
- num_widens
;
8696 assert (desired_diff
>= 0 && desired_diff
< 8);
8697 if (desired_diff
== 0)
8700 assert (wide_nops
> 0 || num_widens
> 0);
8702 /* Always prefer widening to NOP-filling. */
8703 if (bytes_short
< 0)
8705 /* There are enough RELAX_NARROW frags after this one
8706 to align the target without widening this frag in any way. */
8710 if (bytes_short
== 0)
8712 /* Widen every narrow between here and the align target
8713 and the align target will be properly aligned. */
8714 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8720 /* From here we will need at least one NOP to get an alignment.
8721 However, we may not be able to align at all, in which case,
8723 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8725 switch (desired_diff
)
8730 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8731 return 2; /* case 2 */
8737 return 3; /* case 3a */
8739 if (num_widens
>= 1 && wide_nops
== 1)
8740 return 3; /* case 4a */
8741 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8742 return 2; /* case 4b */
8745 if (num_widens
>= 2 && wide_nops
== 1)
8746 return 3; /* case 5a */
8747 /* We will need two nops. Are there enough nops
8748 between here and the align target? */
8749 if (wide_nops
< 2 || narrow_nops
== 0)
8751 /* Are there other nops closer that can serve instead? */
8752 if (wide_nops
> 2 && narrow_nops
> 1)
8754 /* Take the density one first, because there might not be
8755 another density one available. */
8756 if (!this_frag
->tc_frag_data
.is_no_density
)
8757 return 2; /* case 5b narrow */
8759 return 3; /* case 5b wide */
8763 return 3; /* case 6a */
8764 else if (num_widens
>= 3 && wide_nops
== 1)
8765 return 3; /* case 6b */
8768 if (wide_nops
== 1 && num_widens
>= 4)
8769 return 3; /* case 7a */
8770 else if (wide_nops
== 2 && num_widens
>= 1)
8771 return 3; /* case 7b */
8779 /* We will need a NOP no matter what, but should we widen
8780 this instruction to help?
8782 This is a RELAX_NARROW frag. */
8783 switch (desired_diff
)
8792 if (wide_nops
>= 1 && num_widens
== 1)
8793 return 1; /* case 4a */
8796 if (wide_nops
>= 1 && num_widens
== 2)
8797 return 1; /* case 5a */
8801 return 0; /* case 6a */
8802 else if (wide_nops
>= 1 && num_widens
== 3)
8803 return 1; /* case 6b */
8806 if (wide_nops
>= 1 && num_widens
== 4)
8807 return 1; /* case 7a */
8808 else if (wide_nops
>= 2 && num_widens
== 1)
8809 return 1; /* case 7b */
8822 relax_frag_immed (segT segP
,
8829 bfd_boolean estimate_only
)
8833 bfd_boolean negatable_branch
= FALSE
;
8834 bfd_boolean branch_jmp_to_next
= FALSE
;
8835 bfd_boolean wide_insn
= FALSE
;
8836 xtensa_isa isa
= xtensa_default_isa
;
8838 offsetT frag_offset
;
8841 int num_text_bytes
, num_literal_bytes
;
8842 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8844 assert (fragP
->fr_opcode
!= NULL
);
8846 xg_clear_vinsn (&cur_vinsn
);
8847 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8848 if (cur_vinsn
.num_slots
> 1)
8851 tinsn
= cur_vinsn
.slots
[slot
];
8852 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8854 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8857 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8858 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8860 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8862 old_size
= xtensa_format_length (isa
, fmt
);
8864 /* Special case: replace a branch to the next instruction with a NOP.
8865 This is required to work around a hardware bug in T1040.0 and also
8866 serves as an optimization. */
8868 if (branch_jmp_to_next
8869 && ((old_size
== 2) || (old_size
== 3))
8870 && !next_frag_is_loop_target (fragP
))
8873 /* Here is the fun stuff: Get the immediate field from this
8874 instruction. If it fits, we are done. If not, find the next
8875 instruction sequence that fits. */
8877 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8878 istack_init (&istack
);
8879 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8880 min_steps
, stretch
);
8881 if (num_steps
< min_steps
)
8883 as_fatal (_("internal error: relaxation failed"));
8887 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8889 as_fatal (_("internal error: relaxation requires too many steps"));
8893 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8895 /* Figure out the number of bytes needed. */
8897 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8899 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8901 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8903 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8906 num_text_bytes
+= old_size
;
8907 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8908 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8910 total_text_diff
= num_text_bytes
- old_size
;
8911 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8913 /* It MUST get larger. If not, we could get an infinite loop. */
8914 assert (num_text_bytes
>= 0);
8915 assert (literal_diff
>= 0);
8916 assert (total_text_diff
>= 0);
8918 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8919 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8920 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8921 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8923 /* Find the associated expandable literal for this. */
8924 if (literal_diff
!= 0)
8926 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8929 assert (literal_diff
== 4);
8930 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8932 /* We expect that the literal section state has NOT been
8934 assert (lit_fragP
->fr_type
== rs_machine_dependent
8935 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8936 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8938 /* We need to mark this section for another iteration
8944 if (negatable_branch
&& istack
.ninsn
> 1)
8945 update_next_frag_state (fragP
);
8947 return this_text_diff
;
8951 /* md_convert_frag Hook and Helper Functions. */
8953 static void convert_frag_align_next_opcode (fragS
*);
8954 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8955 static void convert_frag_fill_nop (fragS
*);
8956 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8959 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8961 static xtensa_insnbuf vbuf
= NULL
;
8962 xtensa_isa isa
= xtensa_default_isa
;
8969 as_where (&file_name
, &line
);
8970 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8972 switch (fragp
->fr_subtype
)
8974 case RELAX_ALIGN_NEXT_OPCODE
:
8975 /* Always convert. */
8976 convert_frag_align_next_opcode (fragp
);
8979 case RELAX_DESIRE_ALIGN
:
8980 /* Do nothing. If not aligned already, too bad. */
8984 case RELAX_LITERAL_FINAL
:
8989 vbuf
= xtensa_insnbuf_alloc (isa
);
8991 xtensa_insnbuf_from_chars
8992 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8993 fmt
= xtensa_format_decode (isa
, vbuf
);
8994 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8996 for (slot
= 0; slot
< num_slots
; slot
++)
8998 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9001 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9005 case RELAX_IMMED_STEP1
:
9006 case RELAX_IMMED_STEP2
:
9007 /* Place the immediate. */
9010 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9015 /* This is OK because some slots could have
9016 relaxations and others have none. */
9022 case RELAX_UNREACHABLE
:
9023 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9024 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9025 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9029 case RELAX_MAYBE_UNREACHABLE
:
9030 case RELAX_MAYBE_DESIRE_ALIGN
:
9034 case RELAX_FILL_NOP
:
9035 convert_frag_fill_nop (fragp
);
9038 case RELAX_LITERAL_NR
:
9039 if (use_literal_section
)
9041 /* This should have been handled during relaxation. When
9042 relaxing a code segment, literals sometimes need to be
9043 added to the corresponding literal segment. If that
9044 literal segment has already been relaxed, then we end up
9045 in this situation. Marking the literal segments as data
9046 would make this happen less often (since GAS always relaxes
9047 code before data), but we could still get into trouble if
9048 there are instructions in a segment that is not marked as
9049 containing code. Until we can implement a better solution,
9050 cheat and adjust the addresses of all the following frags.
9051 This could break subsequent alignments, but the linker's
9052 literal coalescing will do that anyway. */
9055 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9056 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9057 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9060 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9064 as_bad (_("invalid relaxation fragment result"));
9069 new_logical_line (file_name
, line
);
9074 convert_frag_align_next_opcode (fragS
*fragp
)
9076 char *nop_buf
; /* Location for Writing. */
9077 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9078 addressT aligned_address
;
9082 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9084 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9085 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9086 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9088 for (nop
= 0; nop
< nop_count
; nop
++)
9091 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9093 assemble_nop (nop_size
, nop_buf
);
9094 nop_buf
+= nop_size
;
9097 fragp
->fr_fix
+= fill_size
;
9098 fragp
->fr_var
-= fill_size
;
9103 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9105 TInsn tinsn
, single_target
;
9106 int size
, old_size
, diff
;
9107 offsetT frag_offset
;
9110 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9112 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9114 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9115 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9116 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9121 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9123 /* No conversion. */
9128 assert (fragP
->fr_opcode
!= NULL
);
9130 /* Frags in this relaxation state should only contain
9131 single instruction bundles. */
9132 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9134 /* Just convert it to a wide form.... */
9136 old_size
= xg_get_single_size (tinsn
.opcode
);
9138 tinsn_init (&single_target
);
9139 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9141 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9143 as_bad (_("unable to widen instruction"));
9147 size
= xg_get_single_size (single_target
.opcode
);
9148 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9151 diff
= size
- old_size
;
9153 assert (diff
<= fragP
->fr_var
);
9154 fragP
->fr_var
-= diff
;
9155 fragP
->fr_fix
+= diff
;
9163 convert_frag_fill_nop (fragS
*fragP
)
9165 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9166 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9167 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9168 - fragP
->fr_address
- fragP
->fr_fix
));
9171 /* No conversion. */
9175 assemble_nop (size
, loc
);
9176 fragP
->tc_frag_data
.is_insn
= TRUE
;
9177 fragP
->fr_var
-= size
;
9178 fragP
->fr_fix
+= size
;
9183 static fixS
*fix_new_exp_in_seg
9184 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9185 bfd_reloc_code_real_type
);
9186 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9189 convert_frag_immed (segT segP
,
9195 char *immed_instr
= fragP
->fr_opcode
;
9197 bfd_boolean expanded
= FALSE
;
9198 bfd_boolean branch_jmp_to_next
= FALSE
;
9199 char *fr_opcode
= fragP
->fr_opcode
;
9200 xtensa_isa isa
= xtensa_default_isa
;
9201 bfd_boolean wide_insn
= FALSE
;
9203 bfd_boolean is_loop
;
9205 assert (fr_opcode
!= NULL
);
9207 xg_clear_vinsn (&cur_vinsn
);
9209 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9210 if (cur_vinsn
.num_slots
> 1)
9213 orig_tinsn
= cur_vinsn
.slots
[slot
];
9214 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9216 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9218 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9219 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9221 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9223 /* Conversion just inserts a NOP and marks the fix as completed. */
9224 bytes
= xtensa_format_length (isa
, fmt
);
9227 cur_vinsn
.slots
[slot
].opcode
=
9228 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9229 cur_vinsn
.slots
[slot
].ntok
= 0;
9233 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9234 assert (bytes
== 2 || bytes
== 3);
9235 build_nop (&cur_vinsn
.slots
[0], bytes
);
9236 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9238 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9239 xtensa_insnbuf_to_chars
9240 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9245 /* Here is the fun stuff: Get the immediate field from this
9246 instruction. If it fits, we're done. If not, find the next
9247 instruction sequence that fits. */
9251 symbolS
*lit_sym
= NULL
;
9253 int target_offset
= 0;
9256 symbolS
*gen_label
= NULL
;
9257 offsetT frag_offset
;
9258 bfd_boolean first
= TRUE
;
9259 bfd_boolean last_is_jump
;
9261 /* It does not fit. Find something that does and
9262 convert immediately. */
9263 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9264 istack_init (&istack
);
9265 xg_assembly_relax (&istack
, &orig_tinsn
,
9266 segP
, fragP
, frag_offset
, min_steps
, 0);
9268 old_size
= xtensa_format_length (isa
, fmt
);
9270 /* Assemble this right inline. */
9272 /* First, create the mapping from a label name to the REAL label. */
9274 for (i
= 0; i
< istack
.ninsn
; i
++)
9276 TInsn
*tinsn
= &istack
.insn
[i
];
9279 switch (tinsn
->insn_type
)
9282 if (lit_sym
!= NULL
)
9283 as_bad (_("multiple literals in expansion"));
9284 /* First find the appropriate space in the literal pool. */
9285 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9286 if (lit_frag
== NULL
)
9287 as_bad (_("no registered fragment for literal"));
9288 if (tinsn
->ntok
!= 1)
9289 as_bad (_("number of literal tokens != 1"));
9291 /* Set the literal symbol and add a fixup. */
9292 lit_sym
= lit_frag
->fr_symbol
;
9296 if (align_targets
&& !is_loop
)
9298 fragS
*unreach
= fragP
->fr_next
;
9299 while (!(unreach
->fr_type
== rs_machine_dependent
9300 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9301 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9303 unreach
= unreach
->fr_next
;
9306 assert (unreach
->fr_type
== rs_machine_dependent
9307 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9308 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9310 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9312 assert (gen_label
== NULL
);
9313 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9314 fr_opcode
- fragP
->fr_literal
9315 + target_offset
, fragP
);
9319 if (first
&& wide_insn
)
9321 target_offset
+= xtensa_format_length (isa
, fmt
);
9323 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9324 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9327 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9334 last_is_jump
= FALSE
;
9335 for (i
= 0; i
< istack
.ninsn
; i
++)
9337 TInsn
*tinsn
= &istack
.insn
[i
];
9341 bfd_reloc_code_real_type reloc_type
;
9343 switch (tinsn
->insn_type
)
9346 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9347 /* Already checked. */
9348 assert (lit_frag
!= NULL
);
9349 assert (lit_sym
!= NULL
);
9350 assert (tinsn
->ntok
== 1);
9352 target_seg
= S_GET_SEGMENT (lit_sym
);
9353 assert (target_seg
);
9354 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9355 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9356 &tinsn
->tok
[0], FALSE
, reloc_type
);
9363 xg_resolve_labels (tinsn
, gen_label
);
9364 xg_resolve_literals (tinsn
, lit_sym
);
9365 if (wide_insn
&& first
)
9368 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9370 cur_vinsn
.slots
[slot
] = *tinsn
;
9374 cur_vinsn
.slots
[slot
].opcode
=
9375 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9376 cur_vinsn
.slots
[slot
].ntok
= 0;
9378 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9379 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9380 (unsigned char *) immed_instr
, 0);
9381 fragP
->tc_frag_data
.is_insn
= TRUE
;
9382 size
= xtensa_format_length (isa
, fmt
);
9383 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9386 (tinsn
, immed_instr
+ size
, fragP
,
9387 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9388 size
+= xg_get_single_size (tinsn
->opcode
);
9393 size
= xg_get_single_size (tinsn
->opcode
);
9394 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9395 immed_instr
- fragP
->fr_literal
, TRUE
);
9397 immed_instr
+= size
;
9403 diff
= total_size
- old_size
;
9407 assert (diff
<= fragP
->fr_var
);
9408 fragP
->fr_var
-= diff
;
9409 fragP
->fr_fix
+= diff
;
9412 /* Check for undefined immediates in LOOP instructions. */
9416 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9417 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9419 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9422 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9423 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9425 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9430 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9431 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9433 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9435 /* Add an expansion note on the expanded instruction. */
9436 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9437 &orig_tinsn
.tok
[0], TRUE
,
9438 BFD_RELOC_XTENSA_ASM_EXPAND
);
9443 /* Add a new fix expression into the desired segment. We have to
9444 switch to that segment to do this. */
9447 fix_new_exp_in_seg (segT new_seg
,
9454 bfd_reloc_code_real_type r_type
)
9458 subsegT subseg
= now_subseg
;
9460 assert (new_seg
!= 0);
9461 subseg_set (new_seg
, new_subseg
);
9463 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9464 subseg_set (seg
, subseg
);
9469 /* Relax a loop instruction so that it can span loop >256 bytes.
9475 addi as, as, lo8 (label-.L1)
9476 addmi as, as, mid8 (label-.L1)
9487 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9492 unsigned long target
;
9493 static xtensa_insnbuf insnbuf
= NULL
;
9494 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9495 xtensa_isa isa
= xtensa_default_isa
;
9496 addressT loop_offset
;
9497 addressT addi_offset
= 9;
9498 addressT addmi_offset
= 12;
9503 insnbuf
= xtensa_insnbuf_alloc (isa
);
9505 /* Get the loop offset. */
9506 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9508 /* Validate that there really is a LOOP at the loop_offset. Because
9509 loops are not bundleable, we can assume that the instruction will be
9511 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9512 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9514 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9515 addi_offset
+= loop_offset
;
9516 addmi_offset
+= loop_offset
;
9518 assert (tinsn
->ntok
== 2);
9519 if (tinsn
->tok
[1].X_op
== O_constant
)
9520 target
= tinsn
->tok
[1].X_add_number
;
9521 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9523 /* Find the fragment. */
9524 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9525 assert (S_GET_SEGMENT (sym
) == segP
9526 || S_GET_SEGMENT (sym
) == absolute_section
);
9527 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9531 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9536 know (symbolP
->sy_frag
);
9537 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9538 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9540 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9541 loop_length_hi
= loop_length
& ~0x0ff;
9542 loop_length_lo
= loop_length
& 0x0ff;
9543 if (loop_length_lo
>= 128)
9545 loop_length_lo
-= 256;
9546 loop_length_hi
+= 256;
9549 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9550 32512. If the loop is larger than that, then we just fail. */
9551 if (loop_length_hi
> 32512)
9552 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9553 _("loop too long for LOOP instruction"));
9555 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9556 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9558 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9559 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9561 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9562 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9564 fragP
->tc_frag_data
.is_insn
= TRUE
;
9565 xtensa_insnbuf_to_chars
9566 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9568 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9569 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9570 xtensa_insnbuf_to_chars
9571 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9573 /* Walk through all of the frags from here to the loop end
9574 and mark them as no_transform to keep them from being modified
9575 by the linker. If we ever have a relocation for the
9576 addi/addmi of the difference of two symbols we can remove this. */
9579 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9580 next_fragP
= next_fragP
->fr_next
)
9582 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9583 if (next_fragP
->tc_frag_data
.is_loop_target
)
9585 if (target_count
== 2)
9591 /* A map that keeps information on a per-subsegment basis. This is
9592 maintained during initial assembly, but is invalid once the
9593 subsegments are smashed together. I.E., it cannot be used during
9596 typedef struct subseg_map_struct
9604 float total_freq
; /* fall-through + branch target frequency */
9605 float target_freq
; /* branch target frequency alone */
9607 struct subseg_map_struct
*next
;
9611 static subseg_map
*sseg_map
= NULL
;
9614 get_subseg_info (segT seg
, subsegT subseg
)
9616 subseg_map
*subseg_e
;
9618 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9620 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9628 add_subseg_info (segT seg
, subsegT subseg
)
9630 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9631 memset (subseg_e
, 0, sizeof (subseg_map
));
9632 subseg_e
->seg
= seg
;
9633 subseg_e
->subseg
= subseg
;
9634 subseg_e
->flags
= 0;
9635 /* Start off considering every branch target very important. */
9636 subseg_e
->target_freq
= 1.0;
9637 subseg_e
->total_freq
= 1.0;
9638 subseg_e
->next
= sseg_map
;
9639 sseg_map
= subseg_e
;
9645 get_last_insn_flags (segT seg
, subsegT subseg
)
9647 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9649 return subseg_e
->flags
;
9655 set_last_insn_flags (segT seg
,
9660 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9662 subseg_e
= add_subseg_info (seg
, subseg
);
9664 subseg_e
->flags
|= fl
;
9666 subseg_e
->flags
&= ~fl
;
9671 get_subseg_total_freq (segT seg
, subsegT subseg
)
9673 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9675 return subseg_e
->total_freq
;
9681 get_subseg_target_freq (segT seg
, subsegT subseg
)
9683 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9685 return subseg_e
->target_freq
;
9691 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9693 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9695 subseg_e
= add_subseg_info (seg
, subseg
);
9696 subseg_e
->total_freq
= total_f
;
9697 subseg_e
->target_freq
= target_f
;
9701 /* Segment Lists and emit_state Stuff. */
9704 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9709 segT literal_section
= head
->seg
;
9711 /* Move the literal section to the front of the section list. */
9712 assert (literal_section
);
9713 if (literal_section
!= stdoutput
->sections
)
9715 bfd_section_list_remove (stdoutput
, literal_section
);
9716 bfd_section_list_prepend (stdoutput
, literal_section
);
9723 static void mark_literal_frags (seg_list
*);
9726 xtensa_move_literals (void)
9729 frchainS
*frchain_from
, *frchain_to
;
9730 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9731 fragS
**frag_splice
;
9734 fixS
*fix
, *next_fix
, **fix_splice
;
9737 mark_literal_frags (literal_head
->next
);
9739 if (use_literal_section
)
9742 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9744 /* Keep the literals for .init and .fini in separate sections. */
9745 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9746 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9749 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9750 search_frag
= frchain_from
->frch_root
;
9751 literal_pool
= NULL
;
9753 frag_splice
= &(frchain_from
->frch_root
);
9755 while (!search_frag
->tc_frag_data
.literal_frag
)
9757 assert (search_frag
->fr_fix
== 0
9758 || search_frag
->fr_type
== rs_align
);
9759 search_frag
= search_frag
->fr_next
;
9762 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9763 == RELAX_LITERAL_POOL_BEGIN
);
9764 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9766 /* Make sure that all the frags in this series are closed, and
9767 that there is at least one left over of zero-size. This
9768 prevents us from making a segment with an frchain without any
9770 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9771 xtensa_set_frag_assembly_state (frag_now
);
9772 last_frag
= frag_now
;
9773 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9774 xtensa_set_frag_assembly_state (frag_now
);
9776 while (search_frag
!= frag_now
)
9778 next_frag
= search_frag
->fr_next
;
9780 /* First, move the frag out of the literal section and
9781 to the appropriate place. */
9782 if (search_frag
->tc_frag_data
.literal_frag
)
9784 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9785 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9786 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9787 assert (frchain_to
);
9789 insert_after
= literal_pool
;
9791 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9792 insert_after
= insert_after
->fr_next
;
9794 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9796 *frag_splice
= next_frag
;
9797 search_frag
->fr_next
= insert_after
->fr_next
;
9798 insert_after
->fr_next
= search_frag
;
9799 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9801 /* Now move any fixups associated with this frag to the
9803 fix
= frchain_from
->fix_root
;
9804 fix_splice
= &(frchain_from
->fix_root
);
9807 next_fix
= fix
->fx_next
;
9808 if (fix
->fx_frag
== search_frag
)
9810 *fix_splice
= next_fix
;
9811 fix
->fx_next
= frchain_to
->fix_root
;
9812 frchain_to
->fix_root
= fix
;
9813 if (frchain_to
->fix_tail
== NULL
)
9814 frchain_to
->fix_tail
= fix
;
9817 fix_splice
= &(fix
->fx_next
);
9820 search_frag
= next_frag
;
9823 if (frchain_from
->fix_root
!= NULL
)
9825 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9826 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9828 assert (frchain_from
->fix_root
== NULL
);
9830 frchain_from
->fix_tail
= NULL
;
9831 xtensa_restore_emit_state (&state
);
9834 /* Now fix up the SEGMENT value for all the literal symbols. */
9835 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9837 symbolS
*lit_sym
= lit
->sym
;
9838 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9840 S_SET_SEGMENT (lit_sym
, dest_seg
);
9845 /* Walk over all the frags for segments in a list and mark them as
9846 containing literals. As clunky as this is, we can't rely on frag_var
9847 and frag_variant to get called in all situations. */
9850 mark_literal_frags (seg_list
*segment
)
9852 frchainS
*frchain_from
;
9857 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9858 search_frag
= frchain_from
->frch_root
;
9861 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9862 search_frag
= search_frag
->fr_next
;
9864 segment
= segment
->next
;
9870 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9872 /* Move all of the sections in the section list to come
9873 after "after" in the gnu segment list. */
9878 segT literal_section
= head
->seg
;
9880 /* Move the literal section after "after". */
9881 assert (literal_section
);
9882 if (literal_section
!= after
)
9884 bfd_section_list_remove (stdoutput
, literal_section
);
9885 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9893 /* Push all the literal segments to the end of the gnu list. */
9896 xtensa_reorder_segments (void)
9903 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9909 /* Now that we have the last section, push all the literal
9910 sections to the end. */
9911 xtensa_reorder_seg_list (literal_head
, last_sec
);
9913 /* Now perform the final error check. */
9914 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9916 assert (new_count
== old_count
);
9920 /* Change the emit state (seg, subseg, and frag related stuff) to the
9921 correct location. Return a emit_state which can be passed to
9922 xtensa_restore_emit_state to return to current fragment. */
9925 xtensa_switch_to_literal_fragment (emit_state
*result
)
9927 if (directive_state
[directive_absolute_literals
])
9929 segT lit4_seg
= cache_literal_section (TRUE
);
9930 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
9933 xtensa_switch_to_non_abs_literal_fragment (result
);
9935 /* Do a 4-byte align here. */
9936 frag_align (2, 0, 0);
9937 record_alignment (now_seg
, 2);
9942 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9944 static bfd_boolean recursive
= FALSE
;
9945 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9947 bfd_boolean is_init
=
9948 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9949 bfd_boolean is_fini
=
9950 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9952 if (pool_location
== NULL
9953 && !use_literal_section
9955 && !is_init
&& ! is_fini
)
9957 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9959 /* When we mark a literal pool location, we want to put a frag in
9960 the literal pool that points to it. But to do that, we want to
9961 switch_to_literal_fragment. But literal sections don't have
9962 literal pools, so their location is always null, so we would
9963 recurse forever. This is kind of hacky, but it works. */
9966 xtensa_mark_literal_pool_location ();
9970 lit_seg
= cache_literal_section (FALSE
);
9971 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
9973 if (!use_literal_section
9974 && !is_init
&& !is_fini
9975 && get_literal_pool_location (now_seg
) != pool_location
)
9977 /* Close whatever frag is there. */
9978 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9979 xtensa_set_frag_assembly_state (frag_now
);
9980 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9981 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9982 xtensa_set_frag_assembly_state (frag_now
);
9987 /* Call this function before emitting data into the literal section.
9988 This is a helper function for xtensa_switch_to_literal_fragment.
9989 This is similar to a .section new_now_seg subseg. */
9992 xtensa_switch_section_emit_state (emit_state
*state
,
9994 subsegT new_now_subseg
)
9996 state
->name
= now_seg
->name
;
9997 state
->now_seg
= now_seg
;
9998 state
->now_subseg
= now_subseg
;
9999 state
->generating_literals
= generating_literals
;
10000 generating_literals
++;
10001 subseg_set (new_now_seg
, new_now_subseg
);
10005 /* Use to restore the emitting into the normal place. */
10008 xtensa_restore_emit_state (emit_state
*state
)
10010 generating_literals
= state
->generating_literals
;
10011 subseg_set (state
->now_seg
, state
->now_subseg
);
10015 /* Predicate function used to look up a section in a particular group. */
10018 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10020 const char *gname
= inf
;
10021 const char *group_name
= elf_group_name (sec
);
10023 return (group_name
== gname
10024 || (group_name
!= NULL
10026 && strcmp (group_name
, gname
) == 0));
10030 /* Get the literal section to be used for the current text section.
10031 The result may be cached in the default_lit_sections structure. */
10034 cache_literal_section (bfd_boolean use_abs_literals
)
10036 const char *text_name
, *group_name
= 0;
10037 char *base_name
, *name
, *suffix
;
10039 segT seg
, current_section
;
10040 int current_subsec
;
10041 bfd_boolean linkonce
= FALSE
;
10043 /* Save the current section/subsection. */
10044 current_section
= now_seg
;
10045 current_subsec
= now_subseg
;
10047 /* Clear the cached values if they are no longer valid. */
10048 if (now_seg
!= default_lit_sections
.current_text_seg
)
10050 default_lit_sections
.current_text_seg
= now_seg
;
10051 default_lit_sections
.lit_seg
= NULL
;
10052 default_lit_sections
.lit4_seg
= NULL
;
10055 /* Check if the literal section is already cached. */
10056 if (use_abs_literals
)
10057 pcached
= &default_lit_sections
.lit4_seg
;
10059 pcached
= &default_lit_sections
.lit_seg
;
10064 text_name
= default_lit_sections
.lit_prefix
;
10065 if (! text_name
|| ! *text_name
)
10067 text_name
= segment_name (current_section
);
10068 group_name
= elf_group_name (current_section
);
10069 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10072 base_name
= use_abs_literals
? ".lit4" : ".literal";
10075 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10076 sprintf (name
, "%s.%s", base_name
, group_name
);
10078 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10080 suffix
= strchr (text_name
+ linkonce_len
, '.');
10082 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10083 + (suffix
? strlen (suffix
) : 0));
10084 strcpy (name
, ".gnu.linkonce");
10085 strcat (name
, base_name
);
10087 strcat (name
, suffix
);
10092 /* If the section name ends with ".text", then replace that suffix
10093 instead of appending an additional suffix. */
10094 size_t len
= strlen (text_name
);
10095 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10098 name
= xmalloc (len
+ strlen (base_name
) + 1);
10099 strcpy (name
, text_name
);
10100 strcpy (name
+ len
, base_name
);
10103 /* Canonicalize section names to allow renaming literal sections.
10104 The group name, if any, came from the current text section and
10105 has already been canonicalized. */
10106 name
= tc_canonicalize_symbol_name (name
);
10108 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10109 (void *) group_name
);
10114 seg
= subseg_force_new (name
, 0);
10116 if (! use_abs_literals
)
10118 /* Add the newly created literal segment to the list. */
10119 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10121 n
->next
= literal_head
->next
;
10122 literal_head
->next
= n
;
10125 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10126 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10127 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10129 elf_group_name (seg
) = group_name
;
10131 bfd_set_section_flags (stdoutput
, seg
, flags
);
10132 bfd_set_section_alignment (stdoutput
, seg
, 2);
10136 subseg_set (current_section
, current_subsec
);
10141 /* Property Tables Stuff. */
10143 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10144 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10145 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10147 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10148 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10150 static bfd_boolean
get_frag_is_literal (const fragS
*);
10151 static void xtensa_create_property_segments
10152 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10153 static void xtensa_create_xproperty_segments
10154 (frag_flags_fn
, const char *, xt_section_type
);
10155 static segment_info_type
*retrieve_segment_info (segT
);
10156 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10157 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10158 static void add_xt_block_frags
10159 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10160 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10161 static void xtensa_frag_flags_init (frag_flags
*);
10162 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10163 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10164 static void add_xt_prop_frags
10165 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10167 /* Set up property tables after relaxation. */
10170 xtensa_post_relax_hook (void)
10172 xtensa_move_seg_list_to_beginning (literal_head
);
10174 xtensa_find_unmarked_state_frags ();
10176 xtensa_create_property_segments (get_frag_is_literal
,
10178 XTENSA_LIT_SEC_NAME
,
10180 xtensa_create_xproperty_segments (get_frag_property_flags
,
10181 XTENSA_PROP_SEC_NAME
,
10184 if (warn_unaligned_branch_targets
)
10185 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10186 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10190 /* This function is only meaningful after xtensa_move_literals. */
10193 get_frag_is_literal (const fragS
*fragP
)
10195 assert (fragP
!= NULL
);
10196 return fragP
->tc_frag_data
.is_literal
;
10201 xtensa_create_property_segments (frag_predicate property_function
,
10202 frag_predicate end_property_function
,
10203 const char *section_name_base
,
10204 xt_section_type sec_type
)
10208 /* Walk over all of the current segments.
10209 Walk over each fragment
10210 For each non-empty fragment,
10211 Build a property record (append where possible). */
10213 for (seclist
= &stdoutput
->sections
;
10214 seclist
&& *seclist
;
10215 seclist
= &(*seclist
)->next
)
10217 segT sec
= *seclist
;
10220 flags
= bfd_get_section_flags (stdoutput
, sec
);
10221 if (flags
& SEC_DEBUGGING
)
10223 if (!(flags
& SEC_ALLOC
))
10226 if (section_has_property (sec
, property_function
))
10229 xtensa_get_property_section (sec
, section_name_base
);
10230 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10231 xtensa_block_info
**xt_blocks
=
10232 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10233 /* Walk over all of the frchains here and add new sections. */
10234 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10235 end_property_function
);
10239 /* Now we fill them out.... */
10241 for (seclist
= &stdoutput
->sections
;
10242 seclist
&& *seclist
;
10243 seclist
= &(*seclist
)->next
)
10245 segment_info_type
*seginfo
;
10246 xtensa_block_info
*block
;
10247 segT sec
= *seclist
;
10249 seginfo
= seg_info (sec
);
10250 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10254 xtensa_block_info
*cur_block
;
10255 /* This is a section with some data. */
10257 bfd_size_type rec_size
;
10259 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10262 rec_size
= num_recs
* 8;
10263 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10265 /* In order to make this work with the assembler, we have to
10266 build some frags and then build the "fixups" for it. It
10267 would be easier to just set the contents then set the
10272 /* Allocate a fragment and leak it. */
10274 bfd_size_type frag_size
;
10276 frchainS
*frchainP
;
10280 frag_size
= sizeof (fragS
) + rec_size
;
10281 fragP
= (fragS
*) xmalloc (frag_size
);
10283 memset (fragP
, 0, frag_size
);
10284 fragP
->fr_address
= 0;
10285 fragP
->fr_next
= NULL
;
10286 fragP
->fr_fix
= rec_size
;
10288 fragP
->fr_type
= rs_fill
;
10289 /* The rest are zeros. */
10291 frchainP
= seginfo
->frchainP
;
10292 frchainP
->frch_root
= fragP
;
10293 frchainP
->frch_last
= fragP
;
10295 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10296 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10298 seginfo
->fix_root
= fixes
;
10299 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10301 frag_data
= &fragP
->fr_literal
[0];
10302 for (i
= 0; i
< num_recs
; i
++)
10304 fixS
*fix
= &fixes
[i
];
10305 assert (cur_block
);
10307 /* Write the fixup. */
10308 if (i
!= num_recs
- 1)
10309 fix
->fx_next
= &fixes
[i
+ 1];
10311 fix
->fx_next
= NULL
;
10314 fix
->fx_frag
= fragP
;
10315 fix
->fx_where
= i
* 8;
10316 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10317 fix
->fx_offset
= cur_block
->offset
;
10318 fix
->fx_r_type
= BFD_RELOC_32
;
10319 fix
->fx_file
= "Internal Assembly";
10322 /* Write the length. */
10323 md_number_to_chars (&frag_data
[4 + 8 * i
],
10324 cur_block
->size
, 4);
10325 cur_block
= cur_block
->next
;
10334 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10335 const char *section_name_base
,
10336 xt_section_type sec_type
)
10340 /* Walk over all of the current segments.
10341 Walk over each fragment.
10342 For each fragment that has instructions,
10343 build an instruction record (append where possible). */
10345 for (seclist
= &stdoutput
->sections
;
10346 seclist
&& *seclist
;
10347 seclist
= &(*seclist
)->next
)
10349 segT sec
= *seclist
;
10352 flags
= bfd_get_section_flags (stdoutput
, sec
);
10353 if ((flags
& SEC_DEBUGGING
)
10354 || !(flags
& SEC_ALLOC
)
10355 || (flags
& SEC_MERGE
))
10358 if (section_has_xproperty (sec
, flag_fn
))
10361 xtensa_get_property_section (sec
, section_name_base
);
10362 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10363 xtensa_block_info
**xt_blocks
=
10364 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10365 /* Walk over all of the frchains here and add new sections. */
10366 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10370 /* Now we fill them out.... */
10372 for (seclist
= &stdoutput
->sections
;
10373 seclist
&& *seclist
;
10374 seclist
= &(*seclist
)->next
)
10376 segment_info_type
*seginfo
;
10377 xtensa_block_info
*block
;
10378 segT sec
= *seclist
;
10380 seginfo
= seg_info (sec
);
10381 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10385 xtensa_block_info
*cur_block
;
10386 /* This is a section with some data. */
10388 bfd_size_type rec_size
;
10390 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10393 rec_size
= num_recs
* (8 + 4);
10394 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10396 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10398 /* In order to make this work with the assembler, we have to build
10399 some frags then build the "fixups" for it. It would be easier to
10400 just set the contents then set the arlents. */
10404 /* Allocate a fragment and (unfortunately) leak it. */
10406 bfd_size_type frag_size
;
10408 frchainS
*frchainP
;
10412 frag_size
= sizeof (fragS
) + rec_size
;
10413 fragP
= (fragS
*) xmalloc (frag_size
);
10415 memset (fragP
, 0, frag_size
);
10416 fragP
->fr_address
= 0;
10417 fragP
->fr_next
= NULL
;
10418 fragP
->fr_fix
= rec_size
;
10420 fragP
->fr_type
= rs_fill
;
10421 /* The rest are zeros. */
10423 frchainP
= seginfo
->frchainP
;
10424 frchainP
->frch_root
= fragP
;
10425 frchainP
->frch_last
= fragP
;
10427 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10428 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10430 seginfo
->fix_root
= fixes
;
10431 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10433 frag_data
= &fragP
->fr_literal
[0];
10434 for (i
= 0; i
< num_recs
; i
++)
10436 fixS
*fix
= &fixes
[i
];
10437 assert (cur_block
);
10439 /* Write the fixup. */
10440 if (i
!= num_recs
- 1)
10441 fix
->fx_next
= &fixes
[i
+ 1];
10443 fix
->fx_next
= NULL
;
10446 fix
->fx_frag
= fragP
;
10447 fix
->fx_where
= i
* (8 + 4);
10448 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10449 fix
->fx_offset
= cur_block
->offset
;
10450 fix
->fx_r_type
= BFD_RELOC_32
;
10451 fix
->fx_file
= "Internal Assembly";
10454 /* Write the length. */
10455 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10456 cur_block
->size
, 4);
10457 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10458 frag_flags_to_number (&cur_block
->flags
),
10460 cur_block
= cur_block
->next
;
10468 static segment_info_type
*
10469 retrieve_segment_info (segT seg
)
10471 segment_info_type
*seginfo
;
10472 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10475 frchainS
*frchainP
;
10477 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10478 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10479 seginfo
->fix_root
= NULL
;
10480 seginfo
->fix_tail
= NULL
;
10481 seginfo
->bfd_section
= seg
;
10483 /* We will not be dealing with these, only our special ones. */
10484 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10486 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10487 frchainP
->frch_root
= NULL
;
10488 frchainP
->frch_last
= NULL
;
10489 frchainP
->frch_next
= NULL
;
10490 frchainP
->frch_subseg
= 0;
10491 frchainP
->fix_root
= NULL
;
10492 frchainP
->fix_tail
= NULL
;
10493 /* Do not init the objstack. */
10494 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10495 /* frchainP->frch_frag_now = fragP; */
10496 frchainP
->frch_frag_now
= NULL
;
10498 seginfo
->frchainP
= frchainP
;
10506 section_has_property (segT sec
, frag_predicate property_function
)
10508 segment_info_type
*seginfo
= seg_info (sec
);
10511 if (seginfo
&& seginfo
->frchainP
)
10513 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10515 if (property_function (fragP
)
10516 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10525 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10527 segment_info_type
*seginfo
= seg_info (sec
);
10530 if (seginfo
&& seginfo
->frchainP
)
10532 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10534 frag_flags prop_flags
;
10535 property_function (fragP
, &prop_flags
);
10536 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10544 /* Two types of block sections exist right now: literal and insns. */
10547 add_xt_block_frags (segT sec
,
10549 xtensa_block_info
**xt_block
,
10550 frag_predicate property_function
,
10551 frag_predicate end_property_function
)
10553 segment_info_type
*seg_info
;
10554 segment_info_type
*xt_seg_info
;
10555 bfd_vma seg_offset
;
10558 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10559 seg_info
= retrieve_segment_info (sec
);
10561 /* Build it if needed. */
10562 while (*xt_block
!= NULL
)
10563 xt_block
= &(*xt_block
)->next
;
10564 /* We are either at NULL at the beginning or at the end. */
10566 /* Walk through the frags. */
10569 if (seg_info
->frchainP
)
10571 for (fragP
= seg_info
->frchainP
->frch_root
;
10573 fragP
= fragP
->fr_next
)
10575 if (property_function (fragP
)
10576 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10578 if (*xt_block
!= NULL
)
10580 if ((*xt_block
)->offset
+ (*xt_block
)->size
10581 == fragP
->fr_address
)
10582 (*xt_block
)->size
+= fragP
->fr_fix
;
10584 xt_block
= &((*xt_block
)->next
);
10586 if (*xt_block
== NULL
)
10588 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10589 xmalloc (sizeof (xtensa_block_info
));
10590 new_block
->sec
= sec
;
10591 new_block
->offset
= fragP
->fr_address
;
10592 new_block
->size
= fragP
->fr_fix
;
10593 new_block
->next
= NULL
;
10594 xtensa_frag_flags_init (&new_block
->flags
);
10595 *xt_block
= new_block
;
10597 if (end_property_function
10598 && end_property_function (fragP
))
10600 xt_block
= &((*xt_block
)->next
);
10608 /* Break the encapsulation of add_xt_prop_frags here. */
10611 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10613 if (prop_flags
->is_literal
10614 || prop_flags
->is_insn
10615 || prop_flags
->is_data
10616 || prop_flags
->is_unreachable
)
10623 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10625 memset (prop_flags
, 0, sizeof (frag_flags
));
10630 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10632 xtensa_frag_flags_init (prop_flags
);
10633 if (fragP
->tc_frag_data
.is_literal
)
10634 prop_flags
->is_literal
= TRUE
;
10635 if (fragP
->tc_frag_data
.is_unreachable
)
10636 prop_flags
->is_unreachable
= TRUE
;
10637 else if (fragP
->tc_frag_data
.is_insn
)
10639 prop_flags
->is_insn
= TRUE
;
10640 if (fragP
->tc_frag_data
.is_loop_target
)
10641 prop_flags
->insn
.is_loop_target
= TRUE
;
10642 if (fragP
->tc_frag_data
.is_branch_target
)
10643 prop_flags
->insn
.is_branch_target
= TRUE
;
10644 if (fragP
->tc_frag_data
.is_specific_opcode
10645 || fragP
->tc_frag_data
.is_no_transform
)
10646 prop_flags
->insn
.is_no_transform
= TRUE
;
10647 if (fragP
->tc_frag_data
.is_no_density
)
10648 prop_flags
->insn
.is_no_density
= TRUE
;
10649 if (fragP
->tc_frag_data
.use_absolute_literals
)
10650 prop_flags
->insn
.is_abslit
= TRUE
;
10652 if (fragP
->tc_frag_data
.is_align
)
10654 prop_flags
->is_align
= TRUE
;
10655 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10656 if (xtensa_frag_flags_is_empty (prop_flags
))
10657 prop_flags
->is_data
= TRUE
;
10663 frag_flags_to_number (const frag_flags
*prop_flags
)
10666 if (prop_flags
->is_literal
)
10667 num
|= XTENSA_PROP_LITERAL
;
10668 if (prop_flags
->is_insn
)
10669 num
|= XTENSA_PROP_INSN
;
10670 if (prop_flags
->is_data
)
10671 num
|= XTENSA_PROP_DATA
;
10672 if (prop_flags
->is_unreachable
)
10673 num
|= XTENSA_PROP_UNREACHABLE
;
10674 if (prop_flags
->insn
.is_loop_target
)
10675 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10676 if (prop_flags
->insn
.is_branch_target
)
10678 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10679 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10682 if (prop_flags
->insn
.is_no_density
)
10683 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10684 if (prop_flags
->insn
.is_no_transform
)
10685 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10686 if (prop_flags
->insn
.is_no_reorder
)
10687 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10688 if (prop_flags
->insn
.is_abslit
)
10689 num
|= XTENSA_PROP_INSN_ABSLIT
;
10691 if (prop_flags
->is_align
)
10693 num
|= XTENSA_PROP_ALIGN
;
10694 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10702 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10703 const frag_flags
*prop_flags_2
)
10705 /* Cannot combine with an end marker. */
10707 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10709 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10711 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10714 if (prop_flags_1
->is_insn
)
10716 /* Properties of the beginning of the frag. */
10717 if (prop_flags_2
->insn
.is_loop_target
)
10719 if (prop_flags_2
->insn
.is_branch_target
)
10721 if (prop_flags_1
->insn
.is_no_density
!=
10722 prop_flags_2
->insn
.is_no_density
)
10724 if (prop_flags_1
->insn
.is_no_transform
!=
10725 prop_flags_2
->insn
.is_no_transform
)
10727 if (prop_flags_1
->insn
.is_no_reorder
!=
10728 prop_flags_2
->insn
.is_no_reorder
)
10730 if (prop_flags_1
->insn
.is_abslit
!=
10731 prop_flags_2
->insn
.is_abslit
)
10735 if (prop_flags_1
->is_align
)
10743 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10746 unsigned align_bits
;
10748 if (!xt_block
->flags
.is_align
)
10749 return xt_block
->size
;
10751 end_addr
= xt_block
->offset
+ xt_block
->size
;
10752 align_bits
= xt_block
->flags
.alignment
;
10753 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10754 return end_addr
- xt_block
->offset
;
10759 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10760 const xtensa_block_info
*xt_block_2
)
10762 if (xt_block
->sec
!= xt_block_2
->sec
)
10764 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10765 != xt_block_2
->offset
)
10768 if (xt_block_2
->size
== 0
10769 && (!xt_block_2
->flags
.is_unreachable
10770 || xt_block
->flags
.is_unreachable
))
10772 if (xt_block_2
->flags
.is_align
10773 && xt_block
->flags
.is_align
)
10775 /* Nothing needed. */
10776 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10781 if (xt_block_2
->flags
.is_align
)
10783 /* Push alignment to previous entry. */
10784 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10785 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10790 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10791 &xt_block_2
->flags
))
10794 xt_block
->size
+= xt_block_2
->size
;
10796 if (xt_block_2
->flags
.is_align
)
10798 xt_block
->flags
.is_align
= TRUE
;
10799 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10807 add_xt_prop_frags (segT sec
,
10809 xtensa_block_info
**xt_block
,
10810 frag_flags_fn property_function
)
10812 segment_info_type
*seg_info
;
10813 segment_info_type
*xt_seg_info
;
10814 bfd_vma seg_offset
;
10817 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10818 seg_info
= retrieve_segment_info (sec
);
10819 /* Build it if needed. */
10820 while (*xt_block
!= NULL
)
10822 xt_block
= &(*xt_block
)->next
;
10824 /* We are either at NULL at the beginning or at the end. */
10826 /* Walk through the frags. */
10829 if (seg_info
->frchainP
)
10831 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10832 fragP
= fragP
->fr_next
)
10834 xtensa_block_info tmp_block
;
10835 tmp_block
.sec
= sec
;
10836 tmp_block
.offset
= fragP
->fr_address
;
10837 tmp_block
.size
= fragP
->fr_fix
;
10838 tmp_block
.next
= NULL
;
10839 property_function (fragP
, &tmp_block
.flags
);
10841 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10842 /* && fragP->fr_fix != 0) */
10844 if ((*xt_block
) == NULL
10845 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10847 xtensa_block_info
*new_block
;
10848 if ((*xt_block
) != NULL
)
10849 xt_block
= &(*xt_block
)->next
;
10850 new_block
= (xtensa_block_info
*)
10851 xmalloc (sizeof (xtensa_block_info
));
10852 *new_block
= tmp_block
;
10853 *xt_block
= new_block
;
10861 /* op_placement_info_table */
10863 /* op_placement_info makes it easier to determine which
10864 ops can go in which slots. */
10867 init_op_placement_info_table (void)
10869 xtensa_isa isa
= xtensa_default_isa
;
10870 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10871 xtensa_opcode opcode
;
10874 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10876 op_placement_table
= (op_placement_info_table
)
10877 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10878 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10880 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10882 op_placement_info
*opi
= &op_placement_table
[opcode
];
10883 /* FIXME: Make tinsn allocation dynamic. */
10884 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10885 as_fatal (_("too many operands in instruction"));
10886 opi
->narrowest
= XTENSA_UNDEFINED
;
10887 opi
->narrowest_size
= 0x7F;
10888 opi
->narrowest_slot
= 0;
10890 opi
->num_formats
= 0;
10892 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10894 opi
->slots
[fmt
] = 0;
10895 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10897 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10899 int fmt_length
= xtensa_format_length (isa
, fmt
);
10901 set_bit (fmt
, opi
->formats
);
10902 set_bit (slot
, opi
->slots
[fmt
]);
10903 if (fmt_length
< opi
->narrowest_size
10904 || (fmt_length
== opi
->narrowest_size
10905 && (xtensa_format_num_slots (isa
, fmt
)
10906 < xtensa_format_num_slots (isa
,
10909 opi
->narrowest
= fmt
;
10910 opi
->narrowest_size
= fmt_length
;
10911 opi
->narrowest_slot
= slot
;
10916 opi
->num_formats
++;
10919 xtensa_insnbuf_free (isa
, ibuf
);
10924 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10926 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10930 /* If the opcode is available in a single slot format, return its size. */
10933 xg_get_single_size (xtensa_opcode opcode
)
10935 return op_placement_table
[opcode
].narrowest_size
;
10939 static xtensa_format
10940 xg_get_single_format (xtensa_opcode opcode
)
10942 return op_placement_table
[opcode
].narrowest
;
10947 xg_get_single_slot (xtensa_opcode opcode
)
10949 return op_placement_table
[opcode
].narrowest_slot
;
10953 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10956 istack_init (IStack
*stack
)
10958 memset (stack
, 0, sizeof (IStack
));
10964 istack_empty (IStack
*stack
)
10966 return (stack
->ninsn
== 0);
10971 istack_full (IStack
*stack
)
10973 return (stack
->ninsn
== MAX_ISTACK
);
10977 /* Return a pointer to the top IStack entry.
10978 It is an error to call this if istack_empty () is TRUE. */
10981 istack_top (IStack
*stack
)
10983 int rec
= stack
->ninsn
- 1;
10984 assert (!istack_empty (stack
));
10985 return &stack
->insn
[rec
];
10989 /* Add a new TInsn to an IStack.
10990 It is an error to call this if istack_full () is TRUE. */
10993 istack_push (IStack
*stack
, TInsn
*insn
)
10995 int rec
= stack
->ninsn
;
10996 assert (!istack_full (stack
));
10997 stack
->insn
[rec
] = *insn
;
11002 /* Clear space for the next TInsn on the IStack and return a pointer
11003 to it. It is an error to call this if istack_full () is TRUE. */
11006 istack_push_space (IStack
*stack
)
11008 int rec
= stack
->ninsn
;
11010 assert (!istack_full (stack
));
11011 insn
= &stack
->insn
[rec
];
11012 memset (insn
, 0, sizeof (TInsn
));
11018 /* Remove the last pushed instruction. It is an error to call this if
11019 istack_empty () returns TRUE. */
11022 istack_pop (IStack
*stack
)
11024 int rec
= stack
->ninsn
- 1;
11025 assert (!istack_empty (stack
));
11027 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11031 /* TInsn functions. */
11034 tinsn_init (TInsn
*dst
)
11036 memset (dst
, 0, sizeof (TInsn
));
11040 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11043 tinsn_has_symbolic_operands (const TInsn
*insn
)
11046 int n
= insn
->ntok
;
11048 assert (insn
->insn_type
== ITYPE_INSN
);
11050 for (i
= 0; i
< n
; ++i
)
11052 switch (insn
->tok
[i
].X_op
)
11066 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11068 xtensa_isa isa
= xtensa_default_isa
;
11070 int n
= insn
->ntok
;
11072 assert (insn
->insn_type
== ITYPE_INSN
);
11074 for (i
= 0; i
< n
; ++i
)
11076 switch (insn
->tok
[i
].X_op
)
11084 /* Errors for these types are caught later. */
11089 /* Symbolic immediates are only allowed on the last immediate
11090 operand. At this time, CONST16 is the only opcode where we
11091 support non-PC-relative relocations. */
11092 if (i
!= get_relaxable_immed (insn
->opcode
)
11093 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11094 && insn
->opcode
!= xtensa_const16_opcode
))
11096 as_bad (_("invalid symbolic operand"));
11105 /* For assembly code with complex expressions (e.g. subtraction),
11106 we have to build them in the literal pool so that
11107 their results are calculated correctly after relaxation.
11108 The relaxation only handles expressions that
11109 boil down to SYMBOL + OFFSET. */
11112 tinsn_has_complex_operands (const TInsn
*insn
)
11115 int n
= insn
->ntok
;
11116 assert (insn
->insn_type
== ITYPE_INSN
);
11117 for (i
= 0; i
< n
; ++i
)
11119 switch (insn
->tok
[i
].X_op
)
11135 /* Encode a TInsn opcode and its constant operands into slotbuf.
11136 Return TRUE if there is a symbol in the immediate field. This
11137 function assumes that:
11138 1) The number of operands are correct.
11139 2) The insn_type is ITYPE_INSN.
11140 3) The opcode can be encoded in the specified format and slot.
11141 4) Operands are either O_constant or O_symbol, and all constants fit. */
11144 tinsn_to_slotbuf (xtensa_format fmt
,
11147 xtensa_insnbuf slotbuf
)
11149 xtensa_isa isa
= xtensa_default_isa
;
11150 xtensa_opcode opcode
= tinsn
->opcode
;
11151 bfd_boolean has_fixup
= FALSE
;
11152 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11155 assert (tinsn
->insn_type
== ITYPE_INSN
);
11156 if (noperands
!= tinsn
->ntok
)
11157 as_fatal (_("operand number mismatch"));
11159 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11161 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11162 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11166 for (i
= 0; i
< noperands
; i
++)
11168 expressionS
*expr
= &tinsn
->tok
[i
];
11174 switch (expr
->X_op
)
11177 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11179 /* The register number has already been checked in
11180 expression_maybe_register, so we don't need to check here. */
11181 opnd_value
= expr
->X_add_number
;
11182 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11183 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11186 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11190 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11192 as_where (&file_name
, &line
);
11193 /* It is a constant and we called this function
11194 then we have to try to fit it. */
11195 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11196 expr
->X_add_number
, file_name
, line
);
11209 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11210 into a multi-slot instruction, fill the other slots with NOPs.
11211 Return TRUE if there is a symbol in the immediate field. See also the
11212 assumptions listed for tinsn_to_slotbuf. */
11215 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11217 static xtensa_insnbuf slotbuf
= 0;
11218 static vliw_insn vinsn
;
11219 xtensa_isa isa
= xtensa_default_isa
;
11220 bfd_boolean has_fixup
= FALSE
;
11225 slotbuf
= xtensa_insnbuf_alloc (isa
);
11226 xg_init_vinsn (&vinsn
);
11229 xg_clear_vinsn (&vinsn
);
11231 bundle_tinsn (tinsn
, &vinsn
);
11233 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11235 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11237 /* Only one slot may have a fix-up because the rest contains NOPs. */
11239 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11240 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11247 /* Check the instruction arguments. Return TRUE on failure. */
11250 tinsn_check_arguments (const TInsn
*insn
)
11252 xtensa_isa isa
= xtensa_default_isa
;
11253 xtensa_opcode opcode
= insn
->opcode
;
11255 if (opcode
== XTENSA_UNDEFINED
)
11257 as_bad (_("invalid opcode"));
11261 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11263 as_bad (_("too few operands"));
11267 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11269 as_bad (_("too many operands"));
11276 /* Load an instruction from its encoded form. */
11279 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11283 xg_init_vinsn (&vinsn
);
11284 vinsn_from_chars (&vinsn
, f
);
11286 *tinsn
= vinsn
.slots
[slot
];
11287 xg_free_vinsn (&vinsn
);
11292 tinsn_from_insnbuf (TInsn
*tinsn
,
11293 xtensa_insnbuf slotbuf
,
11298 xtensa_isa isa
= xtensa_default_isa
;
11300 /* Find the immed. */
11301 tinsn_init (tinsn
);
11302 tinsn
->insn_type
= ITYPE_INSN
;
11303 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11304 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11305 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11306 for (i
= 0; i
< tinsn
->ntok
; i
++)
11308 set_expr_const (&tinsn
->tok
[i
],
11309 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11310 tinsn
->opcode
, i
));
11315 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11318 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11320 xtensa_opcode opcode
= tinsn
->opcode
;
11323 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11325 opnum
= get_relaxable_immed (opcode
);
11326 assert (opnum
>= 0);
11327 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11328 fragP
->tc_frag_data
.slot_symbols
[slot
],
11329 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11335 get_num_stack_text_bytes (IStack
*istack
)
11338 int text_bytes
= 0;
11340 for (i
= 0; i
< istack
->ninsn
; i
++)
11342 TInsn
*tinsn
= &istack
->insn
[i
];
11343 if (tinsn
->insn_type
== ITYPE_INSN
)
11344 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11351 get_num_stack_literal_bytes (IStack
*istack
)
11356 for (i
= 0; i
< istack
->ninsn
; i
++)
11358 TInsn
*tinsn
= &istack
->insn
[i
];
11359 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11366 /* vliw_insn functions. */
11369 xg_init_vinsn (vliw_insn
*v
)
11372 xtensa_isa isa
= xtensa_default_isa
;
11374 xg_clear_vinsn (v
);
11376 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11377 if (v
->insnbuf
== NULL
)
11378 as_fatal (_("out of memory"));
11380 for (i
= 0; i
< MAX_SLOTS
; i
++)
11382 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11383 if (v
->slotbuf
[i
] == NULL
)
11384 as_fatal (_("out of memory"));
11390 xg_clear_vinsn (vliw_insn
*v
)
11394 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11396 v
->format
= XTENSA_UNDEFINED
;
11398 v
->inside_bundle
= FALSE
;
11400 if (xt_saved_debug_type
!= DEBUG_NONE
)
11401 debug_type
= xt_saved_debug_type
;
11403 for (i
= 0; i
< MAX_SLOTS
; i
++)
11404 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11409 vinsn_has_specific_opcodes (vliw_insn
*v
)
11413 for (i
= 0; i
< v
->num_slots
; i
++)
11415 if (v
->slots
[i
].is_specific_opcode
)
11423 xg_free_vinsn (vliw_insn
*v
)
11426 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11427 for (i
= 0; i
< MAX_SLOTS
; i
++)
11428 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11432 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11433 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11436 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11439 bfd_boolean record_fixup
)
11441 xtensa_isa isa
= xtensa_default_isa
;
11442 xtensa_format fmt
= vinsn
->format
;
11443 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11445 bfd_boolean has_fixup
= FALSE
;
11447 xtensa_format_encode (isa
, fmt
, insnbuf
);
11449 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11451 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11452 bfd_boolean tinsn_has_fixup
=
11453 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11454 vinsn
->slotbuf
[slot
]);
11456 xtensa_format_set_slot (isa
, fmt
, slot
,
11457 insnbuf
, vinsn
->slotbuf
[slot
]);
11458 if (tinsn_has_fixup
)
11461 xtensa_opcode opcode
= tinsn
->opcode
;
11462 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11465 for (i
= 0; i
< noperands
; i
++)
11467 expressionS
* expr
= &tinsn
->tok
[i
];
11468 switch (expr
->X_op
)
11473 if (get_relaxable_immed (opcode
) == i
)
11475 /* Add a fix record for the instruction, except if this
11476 function is being called prior to relaxation, i.e.,
11477 if record_fixup is false, and the instruction might
11478 be relaxed later. */
11480 || tinsn
->is_specific_opcode
11481 || !xg_is_relaxable_insn (tinsn
, 0))
11483 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11484 frag_offset
- fragP
->fr_literal
);
11488 if (expr
->X_op
!= O_symbol
)
11489 as_bad (_("invalid operand"));
11490 tinsn
->symbol
= expr
->X_add_symbol
;
11491 tinsn
->offset
= expr
->X_add_number
;
11495 as_bad (_("symbolic operand not allowed"));
11503 as_bad (_("expression too complex"));
11515 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11517 static xtensa_insnbuf insnbuf
= NULL
;
11518 static xtensa_insnbuf slotbuf
= NULL
;
11521 xtensa_isa isa
= xtensa_default_isa
;
11525 insnbuf
= xtensa_insnbuf_alloc (isa
);
11526 slotbuf
= xtensa_insnbuf_alloc (isa
);
11529 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11530 fmt
= xtensa_format_decode (isa
, insnbuf
);
11531 if (fmt
== XTENSA_UNDEFINED
)
11532 as_fatal (_("cannot decode instruction format"));
11533 vinsn
->format
= fmt
;
11534 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11536 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11538 TInsn
*tinsn
= &vinsn
->slots
[i
];
11539 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11540 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11545 /* Expression utilities. */
11547 /* Return TRUE if the expression is an integer constant. */
11550 expr_is_const (const expressionS
*s
)
11552 return (s
->X_op
== O_constant
);
11556 /* Get the expression constant.
11557 Calling this is illegal if expr_is_const () returns TRUE. */
11560 get_expr_const (const expressionS
*s
)
11562 assert (expr_is_const (s
));
11563 return s
->X_add_number
;
11567 /* Set the expression to a constant value. */
11570 set_expr_const (expressionS
*s
, offsetT val
)
11572 s
->X_op
= O_constant
;
11573 s
->X_add_number
= val
;
11574 s
->X_add_symbol
= NULL
;
11575 s
->X_op_symbol
= NULL
;
11580 expr_is_register (const expressionS
*s
)
11582 return (s
->X_op
== O_register
);
11586 /* Get the expression constant.
11587 Calling this is illegal if expr_is_const () returns TRUE. */
11590 get_expr_register (const expressionS
*s
)
11592 assert (expr_is_register (s
));
11593 return s
->X_add_number
;
11597 /* Set the expression to a symbol + constant offset. */
11600 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11602 s
->X_op
= O_symbol
;
11603 s
->X_add_symbol
= sym
;
11604 s
->X_op_symbol
= NULL
; /* unused */
11605 s
->X_add_number
= offset
;
11609 /* Return TRUE if the two expressions are equal. */
11612 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11614 if (s1
->X_op
!= s2
->X_op
)
11616 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11618 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11620 if (s1
->X_add_number
!= s2
->X_add_number
)
11627 copy_expr (expressionS
*dst
, const expressionS
*src
)
11629 memcpy (dst
, src
, sizeof (expressionS
));
11633 /* Support for the "--rename-section" option. */
11635 struct rename_section_struct
11639 struct rename_section_struct
*next
;
11642 static struct rename_section_struct
*section_rename
;
11645 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11646 entries to the section_rename list. Note: Specifying multiple
11647 renamings separated by colons is not documented and is retained only
11648 for backward compatibility. */
11651 build_section_rename (const char *arg
)
11653 struct rename_section_struct
*r
;
11654 char *this_arg
= NULL
;
11655 char *next_arg
= NULL
;
11657 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11659 char *old_name
, *new_name
;
11663 next_arg
= strchr (this_arg
, ':');
11671 old_name
= this_arg
;
11672 new_name
= strchr (this_arg
, '=');
11674 if (*old_name
== '\0')
11676 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11679 if (!new_name
|| new_name
[1] == '\0')
11681 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11688 /* Check for invalid section renaming. */
11689 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11691 if (strcmp (r
->old_name
, old_name
) == 0)
11692 as_bad (_("section %s renamed multiple times"), old_name
);
11693 if (strcmp (r
->new_name
, new_name
) == 0)
11694 as_bad (_("multiple sections remapped to output section %s"),
11699 r
= (struct rename_section_struct
*)
11700 xmalloc (sizeof (struct rename_section_struct
));
11701 r
->old_name
= xstrdup (old_name
);
11702 r
->new_name
= xstrdup (new_name
);
11703 r
->next
= section_rename
;
11704 section_rename
= r
;
11710 xtensa_section_rename (char *name
)
11712 struct rename_section_struct
*r
= section_rename
;
11714 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11716 if (strcmp (r
->old_name
, name
) == 0)
11717 return r
->new_name
;