1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_num_pipe_stages
;
80 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
82 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
84 /* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
87 static bfd_boolean past_xtensa_end
= FALSE
;
89 /* Flags for properties of the last instruction in a segment. */
90 #define FLAG_IS_A0_WRITER 0x1
91 #define FLAG_IS_BAD_LOOPEND 0x2
94 /* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
99 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
100 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
105 /* This type is used for the directive_stack to keep track of the
106 state of the literal collection pools. If lit_prefix is set, it is
107 used to determine the literal section names; otherwise, the literal
108 sections are determined based on the current text section. The
109 lit_seg and lit4_seg fields cache these literal sections, with the
110 current_text_seg field used a tag to indicate whether the cached
113 typedef struct lit_state_struct
116 segT current_text_seg
;
121 static lit_state default_lit_sections
;
124 /* We keep a list of literal segments. The seg_list type is the node
125 for this list. The literal_head pointer is the head of the list,
126 with the literal_head_h dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
138 /* Lists of symbols. We keep a list of symbols that label the current
139 instruction, so that we can adjust the symbols when inserting alignment
140 for various instructions. We also keep a list of all the symbols on
141 literals, so that we can fix up those symbols when the literals are
142 later moved into the text sections. */
144 typedef struct sym_list_struct
146 struct sym_list_struct
*next
;
150 static sym_list
*insn_labels
= NULL
;
151 static sym_list
*free_insn_labels
= NULL
;
152 static sym_list
*saved_insn_labels
= NULL
;
154 static sym_list
*literal_syms
;
157 /* Flags to determine whether to prefer const16 or l32r
158 if both options are available. */
159 int prefer_const16
= 0;
162 /* Global flag to indicate when we are emitting literals. */
163 int generating_literals
= 0;
165 /* The following PROPERTY table definitions are copied from
166 <elf/xtensa.h> and must be kept in sync with the code there. */
168 /* Flags in the property tables to specify whether blocks of memory
169 are literals, instructions, data, or unreachable. For
170 instructions, blocks that begin loop targets and branch targets are
171 designated. Blocks that do not allow density, instruction
172 reordering or transformation are also specified. Finally, for
173 branch targets, branch target alignment priority is included.
174 Alignment of the next block is specified in the current block
175 and the size of the current block does not include any fill required
176 to align to the next block. */
178 #define XTENSA_PROP_LITERAL 0x00000001
179 #define XTENSA_PROP_INSN 0x00000002
180 #define XTENSA_PROP_DATA 0x00000004
181 #define XTENSA_PROP_UNREACHABLE 0x00000008
182 /* Instruction only properties at beginning of code. */
183 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
184 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
185 /* Instruction only properties about code. */
186 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
187 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
188 /* Historically, NO_TRANSFORM was a property of instructions,
189 but it should apply to literals under certain circumstances. */
190 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
266 /* is_specific_opcode implies no_transform. */
267 unsigned is_no_transform
: 1;
271 unsigned is_loop_target
: 1;
272 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
273 unsigned bt_align_priority
: 2;
275 unsigned is_no_density
: 1;
276 /* no_longcalls flag does not need to be placed in the object file. */
278 unsigned is_no_reorder
: 1;
280 /* Uses absolute literal addressing for l32r. */
281 unsigned is_abslit
: 1;
283 unsigned is_align
: 1;
284 unsigned alignment
: 5;
288 /* Structure for saving information about a block of property data
289 for frags that have the same flags. */
290 struct xtensa_block_info_struct
296 struct xtensa_block_info_struct
*next
;
300 /* Structure for saving the current state before emitting literals. */
301 typedef struct emit_state_struct
306 int generating_literals
;
310 /* Opcode placement information */
312 typedef unsigned long long bitfield
;
313 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
314 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
315 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
317 #define MAX_FORMATS 32
319 typedef struct op_placement_info_struct
322 /* A number describing how restrictive the issue is for this
323 opcode. For example, an opcode that fits lots of different
324 formats has a high freedom, as does an opcode that fits
325 only one format but many slots in that format. The most
326 restrictive is the opcode that fits only one slot in one
329 xtensa_format narrowest
;
333 /* formats is a bitfield with the Nth bit set
334 if the opcode fits in the Nth xtensa_format. */
337 /* slots[N]'s Mth bit is set if the op fits in the
338 Mth slot of the Nth xtensa_format. */
339 bitfield slots
[MAX_FORMATS
];
341 /* A count of the number of slots in a given format
342 an op can fit (i.e., the bitcount of the slot field above). */
343 char slots_in_format
[MAX_FORMATS
];
345 } op_placement_info
, *op_placement_info_table
;
347 op_placement_info_table op_placement_table
;
350 /* Extra expression types. */
352 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
353 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
354 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
355 #define O_pcrel O_md4 /* value is a PC-relative offset */
356 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
357 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
358 #define O_tlscall O_md7 /* TLS_CALL relocation */
359 #define O_tpoff O_md8 /* TPOFF relocation */
360 #define O_dtpoff O_md9 /* DTPOFF relocation */
362 struct suffix_reloc_map
366 bfd_reloc_code_real_type reloc
;
367 unsigned char operator;
370 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
372 static struct suffix_reloc_map suffix_relocs
[] =
374 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
375 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
376 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
377 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
378 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
379 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
380 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
381 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
382 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
383 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
397 directive_literal_prefix
,
399 directive_absolute_literals
,
400 directive_last_directive
406 bfd_boolean can_be_negated
;
409 const directive_infoS directive_info
[] =
412 { "literal", FALSE
},
414 { "transform", TRUE
},
415 { "freeregs", FALSE
},
416 { "longcalls", TRUE
},
417 { "literal_prefix", FALSE
},
418 { "schedule", TRUE
},
419 { "absolute-literals", TRUE
}
422 bfd_boolean directive_state
[] =
426 #if !XCHAL_HAVE_DENSITY
431 TRUE
, /* transform */
432 FALSE
, /* freeregs */
433 FALSE
, /* longcalls */
434 FALSE
, /* literal_prefix */
435 FALSE
, /* schedule */
436 #if XSHAL_USE_ABSOLUTE_LITERALS
437 TRUE
/* absolute_literals */
439 FALSE
/* absolute_literals */
444 /* Directive functions. */
446 static void xtensa_begin_directive (int);
447 static void xtensa_end_directive (int);
448 static void xtensa_literal_prefix (void);
449 static void xtensa_literal_position (int);
450 static void xtensa_literal_pseudo (int);
451 static void xtensa_frequency_pseudo (int);
452 static void xtensa_elf_cons (int);
453 static void xtensa_leb128 (int);
455 /* Parsing and Idiom Translation. */
457 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
459 /* Various Other Internal Functions. */
461 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
462 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
463 static void xtensa_mark_literal_pool_location (void);
464 static addressT
get_expanded_loop_offset (xtensa_opcode
);
465 static fragS
*get_literal_pool_location (segT
);
466 static void set_literal_pool_location (segT
, fragS
*);
467 static void xtensa_set_frag_assembly_state (fragS
*);
468 static void finish_vinsn (vliw_insn
*);
469 static bfd_boolean
emit_single_op (TInsn
*);
470 static int total_frag_text_expansion (fragS
*);
471 static bfd_boolean use_trampolines
= TRUE
;
472 static void xtensa_check_frag_count (void);
473 static void xtensa_create_trampoline_frag (bfd_boolean
);
474 static void xtensa_maybe_create_trampoline_frag (void);
475 struct trampoline_frag
;
476 static int init_trampoline_frag (struct trampoline_frag
*);
478 /* Alignment Functions. */
480 static int get_text_align_power (unsigned);
481 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
482 static int branch_align_power (segT
);
484 /* Helpers for xtensa_relax_frag(). */
486 static long relax_frag_add_nop (fragS
*);
488 /* Accessors for additional per-subsegment information. */
490 static unsigned get_last_insn_flags (segT
, subsegT
);
491 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
492 static float get_subseg_total_freq (segT
, subsegT
);
493 static float get_subseg_target_freq (segT
, subsegT
);
494 static void set_subseg_freq (segT
, subsegT
, float, float);
496 /* Segment list functions. */
498 static void xtensa_move_literals (void);
499 static void xtensa_reorder_segments (void);
500 static void xtensa_switch_to_literal_fragment (emit_state
*);
501 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
502 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
503 static void xtensa_restore_emit_state (emit_state
*);
504 static segT
cache_literal_section (bfd_boolean
);
506 /* Import from elf32-xtensa.c in BFD library. */
508 extern asection
*xtensa_make_property_section (asection
*, const char *);
510 /* op_placement_info functions. */
512 static void init_op_placement_info_table (void);
513 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
514 static int xg_get_single_size (xtensa_opcode
);
515 static xtensa_format
xg_get_single_format (xtensa_opcode
);
516 static int xg_get_single_slot (xtensa_opcode
);
518 /* TInsn and IStack functions. */
520 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
521 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
522 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
523 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
524 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
525 static void tinsn_from_chars (TInsn
*, char *, int);
526 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
527 static int get_num_stack_text_bytes (IStack
*);
528 static int get_num_stack_literal_bytes (IStack
*);
529 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
531 /* vliw_insn functions. */
533 static void xg_init_vinsn (vliw_insn
*);
534 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
535 static void xg_clear_vinsn (vliw_insn
*);
536 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
537 static void xg_free_vinsn (vliw_insn
*);
538 static bfd_boolean vinsn_to_insnbuf
539 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
540 static void vinsn_from_chars (vliw_insn
*, char *);
542 /* Expression Utilities. */
544 bfd_boolean
expr_is_const (const expressionS
*);
545 offsetT
get_expr_const (const expressionS
*);
546 void set_expr_const (expressionS
*, offsetT
);
547 bfd_boolean
expr_is_register (const expressionS
*);
548 offsetT
get_expr_register (const expressionS
*);
549 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
550 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
551 static void copy_expr (expressionS
*, const expressionS
*);
553 /* Section renaming. */
555 static void build_section_rename (const char *);
558 /* ISA imported from bfd. */
559 extern xtensa_isa xtensa_default_isa
;
561 extern int target_big_endian
;
563 static xtensa_opcode xtensa_addi_opcode
;
564 static xtensa_opcode xtensa_addmi_opcode
;
565 static xtensa_opcode xtensa_call0_opcode
;
566 static xtensa_opcode xtensa_call4_opcode
;
567 static xtensa_opcode xtensa_call8_opcode
;
568 static xtensa_opcode xtensa_call12_opcode
;
569 static xtensa_opcode xtensa_callx0_opcode
;
570 static xtensa_opcode xtensa_callx4_opcode
;
571 static xtensa_opcode xtensa_callx8_opcode
;
572 static xtensa_opcode xtensa_callx12_opcode
;
573 static xtensa_opcode xtensa_const16_opcode
;
574 static xtensa_opcode xtensa_entry_opcode
;
575 static xtensa_opcode xtensa_extui_opcode
;
576 static xtensa_opcode xtensa_movi_opcode
;
577 static xtensa_opcode xtensa_movi_n_opcode
;
578 static xtensa_opcode xtensa_isync_opcode
;
579 static xtensa_opcode xtensa_j_opcode
;
580 static xtensa_opcode xtensa_jx_opcode
;
581 static xtensa_opcode xtensa_l32r_opcode
;
582 static xtensa_opcode xtensa_loop_opcode
;
583 static xtensa_opcode xtensa_loopnez_opcode
;
584 static xtensa_opcode xtensa_loopgtz_opcode
;
585 static xtensa_opcode xtensa_nop_opcode
;
586 static xtensa_opcode xtensa_nop_n_opcode
;
587 static xtensa_opcode xtensa_or_opcode
;
588 static xtensa_opcode xtensa_ret_opcode
;
589 static xtensa_opcode xtensa_ret_n_opcode
;
590 static xtensa_opcode xtensa_retw_opcode
;
591 static xtensa_opcode xtensa_retw_n_opcode
;
592 static xtensa_opcode xtensa_rsr_lcount_opcode
;
593 static xtensa_opcode xtensa_waiti_opcode
;
594 static int config_max_slots
= 0;
597 /* Command-line Options. */
599 bfd_boolean use_literal_section
= TRUE
;
600 enum flix_level produce_flix
= FLIX_ALL
;
601 static bfd_boolean align_targets
= TRUE
;
602 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
603 static bfd_boolean has_a0_b_retw
= FALSE
;
604 static bfd_boolean workaround_a0_b_retw
= FALSE
;
605 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
606 static bfd_boolean workaround_short_loop
= FALSE
;
607 static bfd_boolean maybe_has_short_loop
= FALSE
;
608 static bfd_boolean workaround_close_loop_end
= FALSE
;
609 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
610 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
612 /* When workaround_short_loops is TRUE, all loops with early exits must
613 have at least 3 instructions. workaround_all_short_loops is a modifier
614 to the workaround_short_loop flag. In addition to the
615 workaround_short_loop actions, all straightline loopgtz and loopnez
616 must have at least 3 instructions. */
618 static bfd_boolean workaround_all_short_loops
= FALSE
;
622 xtensa_setup_hw_workarounds (int earliest
, int latest
)
624 if (earliest
> latest
)
625 as_fatal (_("illegal range of target hardware versions"));
627 /* Enable all workarounds for pre-T1050.0 hardware. */
628 if (earliest
< 105000 || latest
< 105000)
630 workaround_a0_b_retw
|= TRUE
;
631 workaround_b_j_loop_end
|= TRUE
;
632 workaround_short_loop
|= TRUE
;
633 workaround_close_loop_end
|= TRUE
;
634 workaround_all_short_loops
|= TRUE
;
635 enforce_three_byte_loop_align
= TRUE
;
642 option_density
= OPTION_MD_BASE
,
646 option_no_generate_flix
,
653 option_no_link_relax
,
661 option_text_section_literals
,
662 option_no_text_section_literals
,
664 option_absolute_literals
,
665 option_no_absolute_literals
,
667 option_align_targets
,
668 option_no_align_targets
,
670 option_warn_unaligned_targets
,
675 option_workaround_a0_b_retw
,
676 option_no_workaround_a0_b_retw
,
678 option_workaround_b_j_loop_end
,
679 option_no_workaround_b_j_loop_end
,
681 option_workaround_short_loop
,
682 option_no_workaround_short_loop
,
684 option_workaround_all_short_loops
,
685 option_no_workaround_all_short_loops
,
687 option_workaround_close_loop_end
,
688 option_no_workaround_close_loop_end
,
690 option_no_workarounds
,
692 option_rename_section_name
,
695 option_prefer_const16
,
697 option_target_hardware
,
700 option_no_trampolines
,
703 const char *md_shortopts
= "";
705 struct option md_longopts
[] =
707 { "density", no_argument
, NULL
, option_density
},
708 { "no-density", no_argument
, NULL
, option_no_density
},
710 { "flix", no_argument
, NULL
, option_flix
},
711 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
712 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
714 /* Both "relax" and "generics" are deprecated and treated as equivalent
715 to the "transform" option. */
716 { "relax", no_argument
, NULL
, option_relax
},
717 { "no-relax", no_argument
, NULL
, option_no_relax
},
718 { "generics", no_argument
, NULL
, option_generics
},
719 { "no-generics", no_argument
, NULL
, option_no_generics
},
721 { "transform", no_argument
, NULL
, option_transform
},
722 { "no-transform", no_argument
, NULL
, option_no_transform
},
723 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
724 { "no-text-section-literals", no_argument
, NULL
,
725 option_no_text_section_literals
},
726 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
727 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
728 /* This option was changed from -align-target to -target-align
729 because it conflicted with the "-al" option. */
730 { "target-align", no_argument
, NULL
, option_align_targets
},
731 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
732 { "warn-unaligned-targets", no_argument
, NULL
,
733 option_warn_unaligned_targets
},
734 { "longcalls", no_argument
, NULL
, option_longcalls
},
735 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
737 { "no-workaround-a0-b-retw", no_argument
, NULL
,
738 option_no_workaround_a0_b_retw
},
739 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
741 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
742 option_no_workaround_b_j_loop_end
},
743 { "workaround-b-j-loop-end", no_argument
, NULL
,
744 option_workaround_b_j_loop_end
},
746 { "no-workaround-short-loops", no_argument
, NULL
,
747 option_no_workaround_short_loop
},
748 { "workaround-short-loops", no_argument
, NULL
,
749 option_workaround_short_loop
},
751 { "no-workaround-all-short-loops", no_argument
, NULL
,
752 option_no_workaround_all_short_loops
},
753 { "workaround-all-short-loop", no_argument
, NULL
,
754 option_workaround_all_short_loops
},
756 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
757 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
759 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
761 { "no-workaround-close-loop-end", no_argument
, NULL
,
762 option_no_workaround_close_loop_end
},
763 { "workaround-close-loop-end", no_argument
, NULL
,
764 option_workaround_close_loop_end
},
766 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
768 { "link-relax", no_argument
, NULL
, option_link_relax
},
769 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
771 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
773 { "trampolines", no_argument
, NULL
, option_trampolines
},
774 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
776 { NULL
, no_argument
, NULL
, 0 }
779 size_t md_longopts_size
= sizeof md_longopts
;
783 md_parse_option (int c
, char *arg
)
788 as_warn (_("--density option is ignored"));
790 case option_no_density
:
791 as_warn (_("--no-density option is ignored"));
793 case option_link_relax
:
796 case option_no_link_relax
:
800 produce_flix
= FLIX_ALL
;
802 case option_no_generate_flix
:
803 produce_flix
= FLIX_NO_GENERATE
;
806 produce_flix
= FLIX_NONE
;
808 case option_generics
:
809 as_warn (_("--generics is deprecated; use --transform instead"));
810 return md_parse_option (option_transform
, arg
);
811 case option_no_generics
:
812 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
813 return md_parse_option (option_no_transform
, arg
);
815 as_warn (_("--relax is deprecated; use --transform instead"));
816 return md_parse_option (option_transform
, arg
);
817 case option_no_relax
:
818 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
819 return md_parse_option (option_no_transform
, arg
);
820 case option_longcalls
:
821 directive_state
[directive_longcalls
] = TRUE
;
823 case option_no_longcalls
:
824 directive_state
[directive_longcalls
] = FALSE
;
826 case option_text_section_literals
:
827 use_literal_section
= FALSE
;
829 case option_no_text_section_literals
:
830 use_literal_section
= TRUE
;
832 case option_absolute_literals
:
833 if (!absolute_literals_supported
)
835 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
838 directive_state
[directive_absolute_literals
] = TRUE
;
840 case option_no_absolute_literals
:
841 directive_state
[directive_absolute_literals
] = FALSE
;
844 case option_workaround_a0_b_retw
:
845 workaround_a0_b_retw
= TRUE
;
847 case option_no_workaround_a0_b_retw
:
848 workaround_a0_b_retw
= FALSE
;
850 case option_workaround_b_j_loop_end
:
851 workaround_b_j_loop_end
= TRUE
;
853 case option_no_workaround_b_j_loop_end
:
854 workaround_b_j_loop_end
= FALSE
;
857 case option_workaround_short_loop
:
858 workaround_short_loop
= TRUE
;
860 case option_no_workaround_short_loop
:
861 workaround_short_loop
= FALSE
;
864 case option_workaround_all_short_loops
:
865 workaround_all_short_loops
= TRUE
;
867 case option_no_workaround_all_short_loops
:
868 workaround_all_short_loops
= FALSE
;
871 case option_workaround_close_loop_end
:
872 workaround_close_loop_end
= TRUE
;
874 case option_no_workaround_close_loop_end
:
875 workaround_close_loop_end
= FALSE
;
878 case option_no_workarounds
:
879 workaround_a0_b_retw
= FALSE
;
880 workaround_b_j_loop_end
= FALSE
;
881 workaround_short_loop
= FALSE
;
882 workaround_all_short_loops
= FALSE
;
883 workaround_close_loop_end
= FALSE
;
886 case option_align_targets
:
887 align_targets
= TRUE
;
889 case option_no_align_targets
:
890 align_targets
= FALSE
;
893 case option_warn_unaligned_targets
:
894 warn_unaligned_branch_targets
= TRUE
;
897 case option_rename_section_name
:
898 build_section_rename (arg
);
902 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
903 should be emitted or not. FIXME: Not implemented. */
906 case option_prefer_l32r
:
908 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
912 case option_prefer_const16
:
914 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
918 case option_target_hardware
:
920 int earliest
, latest
= 0;
921 if (*arg
== 0 || *arg
== '-')
922 as_fatal (_("invalid target hardware version"));
924 earliest
= strtol (arg
, &arg
, 0);
928 else if (*arg
== '-')
931 as_fatal (_("invalid target hardware version"));
932 latest
= strtol (arg
, &arg
, 0);
935 as_fatal (_("invalid target hardware version"));
937 xtensa_setup_hw_workarounds (earliest
, latest
);
941 case option_transform
:
942 /* This option has no affect other than to use the defaults,
943 which are already set. */
946 case option_no_transform
:
947 /* This option turns off all transformations of any kind.
948 However, because we want to preserve the state of other
949 directives, we only change its own field. Thus, before
950 you perform any transformation, always check if transform
951 is available. If you use the functions we provide for this
952 purpose, you will be ok. */
953 directive_state
[directive_transform
] = FALSE
;
956 case option_trampolines
:
957 use_trampolines
= TRUE
;
960 case option_no_trampolines
:
961 use_trampolines
= FALSE
;
971 md_show_usage (FILE *stream
)
975 --[no-]text-section-literals\n\
976 [Do not] put literals in the text section\n\
977 --[no-]absolute-literals\n\
978 [Do not] default to use non-PC-relative literals\n\
979 --[no-]target-align [Do not] try to align branch targets\n\
980 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
981 --[no-]transform [Do not] transform instructions\n\
982 --flix both allow hand-written and generate flix bundles\n\
983 --no-generate-flix allow hand-written but do not generate\n\
985 --no-allow-flix neither allow hand-written nor generate\n\
987 --rename-section old=new Rename section 'old' to 'new'\n\
988 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
989 when jumps do not reach their targets\n", stream
);
993 /* Functions related to the list of current label symbols. */
996 xtensa_add_insn_label (symbolS
*sym
)
1000 if (!free_insn_labels
)
1001 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
1004 l
= free_insn_labels
;
1005 free_insn_labels
= l
->next
;
1009 l
->next
= insn_labels
;
1015 xtensa_clear_insn_labels (void)
1019 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1027 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1031 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1033 symbolS
*lit_sym
= lit
->sym
;
1034 S_SET_VALUE (lit_sym
, new_offset
);
1035 symbol_set_frag (lit_sym
, new_frag
);
1040 /* Directive data and functions. */
1042 typedef struct state_stackS_struct
1044 directiveE directive
;
1045 bfd_boolean negated
;
1046 bfd_boolean old_state
;
1050 struct state_stackS_struct
*prev
;
1053 state_stackS
*directive_state_stack
;
1055 const pseudo_typeS md_pseudo_table
[] =
1057 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1058 { "literal_position", xtensa_literal_position
, 0 },
1059 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1060 { "long", xtensa_elf_cons
, 4 },
1061 { "word", xtensa_elf_cons
, 4 },
1062 { "4byte", xtensa_elf_cons
, 4 },
1063 { "short", xtensa_elf_cons
, 2 },
1064 { "2byte", xtensa_elf_cons
, 2 },
1065 { "sleb128", xtensa_leb128
, 1},
1066 { "uleb128", xtensa_leb128
, 0},
1067 { "begin", xtensa_begin_directive
, 0 },
1068 { "end", xtensa_end_directive
, 0 },
1069 { "literal", xtensa_literal_pseudo
, 0 },
1070 { "frequency", xtensa_frequency_pseudo
, 0 },
1076 use_transform (void)
1078 /* After md_end, you should be checking frag by frag, rather
1079 than state directives. */
1080 gas_assert (!past_xtensa_end
);
1081 return directive_state
[directive_transform
];
1086 do_align_targets (void)
1088 /* Do not use this function after md_end; just look at align_targets
1089 instead. There is no target-align directive, so alignment is either
1090 enabled for all frags or not done at all. */
1091 gas_assert (!past_xtensa_end
);
1092 return align_targets
&& use_transform ();
1097 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1101 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1103 as_where (&file
, &line
);
1105 stack
->directive
= directive
;
1106 stack
->negated
= negated
;
1107 stack
->old_state
= directive_state
[directive
];
1110 stack
->datum
= datum
;
1111 stack
->prev
= directive_state_stack
;
1112 directive_state_stack
= stack
;
1114 directive_state
[directive
] = !negated
;
1119 directive_pop (directiveE
*directive
,
1120 bfd_boolean
*negated
,
1125 state_stackS
*top
= directive_state_stack
;
1127 if (!directive_state_stack
)
1129 as_bad (_("unmatched end directive"));
1130 *directive
= directive_none
;
1134 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1135 *directive
= top
->directive
;
1136 *negated
= top
->negated
;
1139 *datum
= top
->datum
;
1140 directive_state_stack
= top
->prev
;
1146 directive_balance (void)
1148 while (directive_state_stack
)
1150 directiveE directive
;
1151 bfd_boolean negated
;
1156 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1157 as_warn_where ((char *) file
, line
,
1158 _(".begin directive with no matching .end directive"));
1164 inside_directive (directiveE dir
)
1166 state_stackS
*top
= directive_state_stack
;
1168 while (top
&& top
->directive
!= dir
)
1171 return (top
!= NULL
);
1176 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1180 char *directive_string
;
1182 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1187 input_line_pointer
+= 3;
1190 len
= strspn (input_line_pointer
,
1191 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1193 /* This code is a hack to make .begin [no-][generics|relax] exactly
1194 equivalent to .begin [no-]transform. We should remove it when
1195 we stop accepting those options. */
1197 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1199 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1200 directive_string
= "transform";
1202 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1204 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1205 directive_string
= "transform";
1208 directive_string
= input_line_pointer
;
1210 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1212 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1214 input_line_pointer
+= len
;
1215 *directive
= (directiveE
) i
;
1216 if (*negated
&& !directive_info
[i
].can_be_negated
)
1217 as_bad (_("directive %s cannot be negated"),
1218 directive_info
[i
].name
);
1223 as_bad (_("unknown directive"));
1224 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1229 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1231 directiveE directive
;
1232 bfd_boolean negated
;
1236 get_directive (&directive
, &negated
);
1237 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1239 discard_rest_of_line ();
1243 if (cur_vinsn
.inside_bundle
)
1244 as_bad (_("directives are not valid inside bundles"));
1248 case directive_literal
:
1249 if (!inside_directive (directive_literal
))
1251 /* Previous labels go with whatever follows this directive, not with
1252 the literal, so save them now. */
1253 saved_insn_labels
= insn_labels
;
1256 as_warn (_(".begin literal is deprecated; use .literal instead"));
1257 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1258 xtensa_switch_to_literal_fragment (state
);
1259 directive_push (directive_literal
, negated
, state
);
1262 case directive_literal_prefix
:
1263 /* Have to flush pending output because a movi relaxed to an l32r
1264 might produce a literal. */
1265 md_flush_pending_output ();
1266 /* Check to see if the current fragment is a literal
1267 fragment. If it is, then this operation is not allowed. */
1268 if (generating_literals
)
1270 as_bad (_("cannot set literal_prefix inside literal fragment"));
1274 /* Allocate the literal state for this section and push
1275 onto the directive stack. */
1276 ls
= xmalloc (sizeof (lit_state
));
1279 *ls
= default_lit_sections
;
1280 directive_push (directive_literal_prefix
, negated
, ls
);
1282 /* Process the new prefix. */
1283 xtensa_literal_prefix ();
1286 case directive_freeregs
:
1287 /* This information is currently unused, but we'll accept the statement
1288 and just discard the rest of the line. This won't check the syntax,
1289 but it will accept every correct freeregs directive. */
1290 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1291 directive_push (directive_freeregs
, negated
, 0);
1294 case directive_schedule
:
1295 md_flush_pending_output ();
1296 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1297 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1298 directive_push (directive_schedule
, negated
, 0);
1299 xtensa_set_frag_assembly_state (frag_now
);
1302 case directive_density
:
1303 as_warn (_(".begin [no-]density is ignored"));
1306 case directive_absolute_literals
:
1307 md_flush_pending_output ();
1308 if (!absolute_literals_supported
&& !negated
)
1310 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1313 xtensa_set_frag_assembly_state (frag_now
);
1314 directive_push (directive
, negated
, 0);
1318 md_flush_pending_output ();
1319 xtensa_set_frag_assembly_state (frag_now
);
1320 directive_push (directive
, negated
, 0);
1324 demand_empty_rest_of_line ();
1329 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1331 directiveE begin_directive
, end_directive
;
1332 bfd_boolean begin_negated
, end_negated
;
1336 emit_state
**state_ptr
;
1339 if (cur_vinsn
.inside_bundle
)
1340 as_bad (_("directives are not valid inside bundles"));
1342 get_directive (&end_directive
, &end_negated
);
1344 md_flush_pending_output ();
1346 switch ((int) end_directive
)
1348 case XTENSA_UNDEFINED
:
1349 discard_rest_of_line ();
1352 case (int) directive_density
:
1353 as_warn (_(".end [no-]density is ignored"));
1354 demand_empty_rest_of_line ();
1357 case (int) directive_absolute_literals
:
1358 if (!absolute_literals_supported
&& !end_negated
)
1360 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1361 demand_empty_rest_of_line ();
1370 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1371 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1372 (const void **) state_ptr
);
1374 if (begin_directive
!= directive_none
)
1376 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1378 as_bad (_("does not match begin %s%s at %s:%d"),
1379 begin_negated
? "no-" : "",
1380 directive_info
[begin_directive
].name
, file
, line
);
1384 switch (end_directive
)
1386 case directive_literal
:
1387 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1388 xtensa_restore_emit_state (state
);
1389 xtensa_set_frag_assembly_state (frag_now
);
1391 if (!inside_directive (directive_literal
))
1393 /* Restore the list of current labels. */
1394 xtensa_clear_insn_labels ();
1395 insn_labels
= saved_insn_labels
;
1399 case directive_literal_prefix
:
1400 /* Restore the default collection sections from saved state. */
1401 s
= (lit_state
*) state
;
1403 default_lit_sections
= *s
;
1405 /* Free the state storage. */
1406 free (s
->lit_prefix
);
1410 case directive_schedule
:
1411 case directive_freeregs
:
1415 xtensa_set_frag_assembly_state (frag_now
);
1421 demand_empty_rest_of_line ();
1425 /* Place an aligned literal fragment at the current location. */
1428 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1430 md_flush_pending_output ();
1432 if (inside_directive (directive_literal
))
1433 as_warn (_(".literal_position inside literal directive; ignoring"));
1434 xtensa_mark_literal_pool_location ();
1436 demand_empty_rest_of_line ();
1437 xtensa_clear_insn_labels ();
1441 /* Support .literal label, expr, ... */
1444 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1447 char *p
, *base_name
;
1451 if (inside_directive (directive_literal
))
1453 as_bad (_(".literal not allowed inside .begin literal region"));
1454 ignore_rest_of_line ();
1458 md_flush_pending_output ();
1460 /* Previous labels go with whatever follows this directive, not with
1461 the literal, so save them now. */
1462 saved_insn_labels
= insn_labels
;
1465 /* If we are using text-section literals, then this is the right value... */
1468 base_name
= input_line_pointer
;
1470 xtensa_switch_to_literal_fragment (&state
);
1472 /* ...but if we aren't using text-section-literals, then we
1473 need to put them in the section we just switched to. */
1474 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1477 /* FIXME, despite the previous comments, dest_seg is unused... */
1480 /* All literals are aligned to four-byte boundaries. */
1481 frag_align (2, 0, 0);
1482 record_alignment (now_seg
, 2);
1484 c
= get_symbol_end ();
1485 /* Just after name is now '\0'. */
1486 p
= input_line_pointer
;
1490 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1492 as_bad (_("expected comma or colon after symbol name; "
1493 "rest of line ignored"));
1494 ignore_rest_of_line ();
1495 xtensa_restore_emit_state (&state
);
1503 input_line_pointer
++; /* skip ',' or ':' */
1505 xtensa_elf_cons (4);
1507 xtensa_restore_emit_state (&state
);
1509 /* Restore the list of current labels. */
1510 xtensa_clear_insn_labels ();
1511 insn_labels
= saved_insn_labels
;
1516 xtensa_literal_prefix (void)
1521 /* Parse the new prefix from the input_line_pointer. */
1523 len
= strspn (input_line_pointer
,
1524 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1525 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1527 /* Get a null-terminated copy of the name. */
1528 name
= xmalloc (len
+ 1);
1530 strncpy (name
, input_line_pointer
, len
);
1533 /* Skip the name in the input line. */
1534 input_line_pointer
+= len
;
1536 default_lit_sections
.lit_prefix
= name
;
1538 /* Clear cached literal sections, since the prefix has changed. */
1539 default_lit_sections
.lit_seg
= NULL
;
1540 default_lit_sections
.lit4_seg
= NULL
;
1544 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1547 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1549 float fall_through_f
, target_f
;
1551 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1552 if (fall_through_f
< 0)
1554 as_bad (_("fall through frequency must be greater than 0"));
1555 ignore_rest_of_line ();
1559 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1562 as_bad (_("branch target frequency must be greater than 0"));
1563 ignore_rest_of_line ();
1567 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1569 demand_empty_rest_of_line ();
1573 /* Like normal .long/.short/.word, except support @plt, etc.
1574 Clobbers input_line_pointer, checks end-of-line. */
1577 xtensa_elf_cons (int nbytes
)
1580 bfd_reloc_code_real_type reloc
;
1582 md_flush_pending_output ();
1584 if (cur_vinsn
.inside_bundle
)
1585 as_bad (_("directives are not valid inside bundles"));
1587 if (is_it_end_of_statement ())
1589 demand_empty_rest_of_line ();
1596 if (exp
.X_op
== O_symbol
1597 && *input_line_pointer
== '@'
1598 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1601 reloc_howto_type
*reloc_howto
=
1602 bfd_reloc_type_lookup (stdoutput
, reloc
);
1604 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1605 as_bad (_("unsupported relocation"));
1606 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1607 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1608 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1609 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1610 as_bad (_("opcode-specific %s relocation used outside "
1611 "an instruction"), reloc_howto
->name
);
1612 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1613 as_bad (_("%s relocations do not fit in %d bytes"),
1614 reloc_howto
->name
, nbytes
);
1615 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1616 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1617 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1618 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1621 char *p
= frag_more ((int) nbytes
);
1622 xtensa_set_frag_assembly_state (frag_now
);
1623 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1624 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1629 xtensa_set_frag_assembly_state (frag_now
);
1630 emit_expr (&exp
, (unsigned int) nbytes
);
1633 while (*input_line_pointer
++ == ',');
1635 input_line_pointer
--; /* Put terminator back into stream. */
1636 demand_empty_rest_of_line ();
1639 static bfd_boolean is_leb128_expr
;
1642 xtensa_leb128 (int sign
)
1644 is_leb128_expr
= TRUE
;
1646 is_leb128_expr
= FALSE
;
1650 /* Parsing and Idiom Translation. */
1652 /* Parse @plt, etc. and return the desired relocation. */
1653 static bfd_reloc_code_real_type
1654 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1661 struct suffix_reloc_map
*ptr
;
1664 return BFD_RELOC_NONE
;
1666 for (ch
= *str
, str2
= ident
;
1667 (str2
< ident
+ sizeof (ident
) - 1
1668 && (ISALNUM (ch
) || ch
== '@'));
1671 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1678 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1679 if (ch
== ptr
->suffix
[0]
1680 && len
== ptr
->length
1681 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1683 /* Now check for "identifier@suffix+constant". */
1684 if (*str
== '-' || *str
== '+')
1686 char *orig_line
= input_line_pointer
;
1687 expressionS new_exp
;
1689 input_line_pointer
= str
;
1690 expression (&new_exp
);
1691 if (new_exp
.X_op
== O_constant
)
1693 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1694 str
= input_line_pointer
;
1697 if (&input_line_pointer
!= str_p
)
1698 input_line_pointer
= orig_line
;
1705 return BFD_RELOC_UNUSED
;
1709 /* Find the matching operator type. */
1710 static unsigned char
1711 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1713 struct suffix_reloc_map
*sfx
;
1714 unsigned char operator = (unsigned char) -1;
1716 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1718 if (sfx
->reloc
== reloc
)
1720 operator = sfx
->operator;
1724 gas_assert (operator != (unsigned char) -1);
1729 /* Find the matching reloc type. */
1730 static bfd_reloc_code_real_type
1731 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1733 struct suffix_reloc_map
*sfx
;
1734 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1736 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1738 if (sfx
->operator == operator)
1747 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1748 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1749 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1750 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1753 if (reloc
== BFD_RELOC_UNUSED
)
1754 return BFD_RELOC_32
;
1761 expression_end (const char *name
)
1784 #define ERROR_REG_NUM ((unsigned) -1)
1787 tc_get_register (const char *prefix
)
1790 const char *next_expr
;
1791 const char *old_line_pointer
;
1794 old_line_pointer
= input_line_pointer
;
1796 if (*input_line_pointer
== '$')
1797 ++input_line_pointer
;
1799 /* Accept "sp" as a synonym for "a1". */
1800 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1801 && expression_end (input_line_pointer
+ 2))
1803 input_line_pointer
+= 2;
1804 return 1; /* AR[1] */
1807 while (*input_line_pointer
++ == *prefix
++)
1809 --input_line_pointer
;
1814 as_bad (_("bad register name: %s"), old_line_pointer
);
1815 return ERROR_REG_NUM
;
1818 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1820 as_bad (_("bad register number: %s"), input_line_pointer
);
1821 return ERROR_REG_NUM
;
1826 while (ISDIGIT ((int) *input_line_pointer
))
1827 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1829 if (!(next_expr
= expression_end (input_line_pointer
)))
1831 as_bad (_("bad register name: %s"), old_line_pointer
);
1832 return ERROR_REG_NUM
;
1835 input_line_pointer
= (char *) next_expr
;
1842 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1844 xtensa_isa isa
= xtensa_default_isa
;
1846 /* Check if this is an immediate operand. */
1847 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1849 bfd_reloc_code_real_type reloc
;
1850 segT t
= expression (tok
);
1852 if (t
== absolute_section
1853 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1855 gas_assert (tok
->X_op
== O_constant
);
1856 tok
->X_op
= O_symbol
;
1857 tok
->X_add_symbol
= &abs_symbol
;
1860 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1861 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1866 case BFD_RELOC_LO16
:
1867 if (tok
->X_op
== O_constant
)
1869 tok
->X_add_number
&= 0xffff;
1873 case BFD_RELOC_HI16
:
1874 if (tok
->X_op
== O_constant
)
1876 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1880 case BFD_RELOC_UNUSED
:
1881 as_bad (_("unsupported relocation"));
1883 case BFD_RELOC_32_PCREL
:
1884 as_bad (_("pcrel relocation not allowed in an instruction"));
1889 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1894 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1895 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1897 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1900 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1901 as_bad (_("register number out of range"));
1904 tok
->X_op
= O_register
;
1905 tok
->X_add_symbol
= 0;
1906 tok
->X_add_number
= reg
;
1911 /* Split up the arguments for an opcode or pseudo-op. */
1914 tokenize_arguments (char **args
, char *str
)
1916 char *old_input_line_pointer
;
1917 bfd_boolean saw_comma
= FALSE
;
1918 bfd_boolean saw_arg
= FALSE
;
1919 bfd_boolean saw_colon
= FALSE
;
1921 char *arg_end
, *arg
;
1924 /* Save and restore input_line_pointer around this function. */
1925 old_input_line_pointer
= input_line_pointer
;
1926 input_line_pointer
= str
;
1928 while (*input_line_pointer
)
1931 switch (*input_line_pointer
)
1938 input_line_pointer
++;
1939 if (saw_comma
|| saw_colon
|| !saw_arg
)
1945 input_line_pointer
++;
1946 if (saw_comma
|| saw_colon
|| !saw_arg
)
1952 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1955 arg_end
= input_line_pointer
+ 1;
1956 while (!expression_end (arg_end
))
1959 arg_len
= arg_end
- input_line_pointer
;
1960 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1961 args
[num_args
] = arg
;
1965 strncpy (arg
, input_line_pointer
, arg_len
);
1966 arg
[arg_len
] = '\0';
1968 input_line_pointer
= arg_end
;
1978 if (saw_comma
|| saw_colon
)
1980 input_line_pointer
= old_input_line_pointer
;
1985 as_bad (_("extra comma"));
1987 as_bad (_("extra colon"));
1989 as_bad (_("missing argument"));
1991 as_bad (_("missing comma or colon"));
1992 input_line_pointer
= old_input_line_pointer
;
1997 /* Parse the arguments to an opcode. Return TRUE on error. */
2000 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2002 expressionS
*tok
, *last_tok
;
2003 xtensa_opcode opcode
= insn
->opcode
;
2004 bfd_boolean had_error
= TRUE
;
2005 xtensa_isa isa
= xtensa_default_isa
;
2006 int n
, num_regs
= 0;
2007 int opcode_operand_count
;
2008 int opnd_cnt
, last_opnd_cnt
;
2009 unsigned int next_reg
= 0;
2010 char *old_input_line_pointer
;
2012 if (insn
->insn_type
== ITYPE_LITERAL
)
2013 opcode_operand_count
= 1;
2015 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2018 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2020 /* Save and restore input_line_pointer around this function. */
2021 old_input_line_pointer
= input_line_pointer
;
2027 /* Skip invisible operands. */
2028 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2034 for (n
= 0; n
< num_args
; n
++)
2036 input_line_pointer
= arg_strings
[n
];
2037 if (*input_line_pointer
== ':')
2039 xtensa_regfile opnd_rf
;
2040 input_line_pointer
++;
2043 gas_assert (opnd_cnt
> 0);
2045 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2047 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2048 as_warn (_("incorrect register number, ignoring"));
2053 if (opnd_cnt
>= opcode_operand_count
)
2055 as_warn (_("too many arguments"));
2058 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2060 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2061 next_reg
= tok
->X_add_number
+ 1;
2063 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2065 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2067 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2068 /* minus 1 because we are seeing one right now */
2074 last_opnd_cnt
= opnd_cnt
;
2075 demand_empty_rest_of_line ();
2082 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2086 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2089 insn
->ntok
= tok
- insn
->tok
;
2093 input_line_pointer
= old_input_line_pointer
;
2099 get_invisible_operands (TInsn
*insn
)
2101 xtensa_isa isa
= xtensa_default_isa
;
2102 static xtensa_insnbuf slotbuf
= NULL
;
2104 xtensa_opcode opc
= insn
->opcode
;
2105 int slot
, opnd
, fmt_found
;
2109 slotbuf
= xtensa_insnbuf_alloc (isa
);
2111 /* Find format/slot where this can be encoded. */
2114 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2116 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2118 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2124 if (fmt_found
) break;
2129 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2133 /* First encode all the visible operands
2134 (to deal with shared field operands). */
2135 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2137 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2138 && (insn
->tok
[opnd
].X_op
== O_register
2139 || insn
->tok
[opnd
].X_op
== O_constant
))
2141 val
= insn
->tok
[opnd
].X_add_number
;
2142 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2143 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2147 /* Then pull out the values for the invisible ones. */
2148 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2150 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2152 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2153 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2154 insn
->tok
[opnd
].X_add_number
= val
;
2155 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2156 insn
->tok
[opnd
].X_op
= O_register
;
2158 insn
->tok
[opnd
].X_op
= O_constant
;
2167 xg_reverse_shift_count (char **cnt_argp
)
2169 char *cnt_arg
, *new_arg
;
2170 cnt_arg
= *cnt_argp
;
2172 /* replace the argument with "31-(argument)" */
2173 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2174 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2177 *cnt_argp
= new_arg
;
2181 /* If "arg" is a constant expression, return non-zero with the value
2185 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2188 char *save_ptr
= input_line_pointer
;
2190 input_line_pointer
= arg
;
2192 input_line_pointer
= save_ptr
;
2194 if (exp
.X_op
== O_constant
)
2196 *valp
= exp
.X_add_number
;
2205 xg_replace_opname (char **popname
, char *newop
)
2208 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2209 strcpy (*popname
, newop
);
2214 xg_check_num_args (int *pnum_args
,
2219 int num_args
= *pnum_args
;
2221 if (num_args
< expected_num
)
2223 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2224 num_args
, opname
, expected_num
);
2228 if (num_args
> expected_num
)
2230 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2231 num_args
, opname
, expected_num
);
2232 while (num_args
-- > expected_num
)
2234 free (arg_strings
[num_args
]);
2235 arg_strings
[num_args
] = 0;
2237 *pnum_args
= expected_num
;
2245 /* If the register is not specified as part of the opcode,
2246 then get it from the operand and move it to the opcode. */
2249 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2251 xtensa_isa isa
= xtensa_default_isa
;
2253 char *opname
, *new_opname
;
2254 const char *sr_name
;
2255 int is_user
, is_write
;
2260 is_user
= (opname
[1] == 'u');
2261 is_write
= (opname
[0] == 'w');
2263 /* Opname == [rw]ur or [rwx]sr... */
2265 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2268 /* Check if the argument is a symbolic register name. */
2269 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2270 /* Handle WSR to "INTSET" as a special case. */
2271 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2272 && !strcasecmp (arg_strings
[1], "intset"))
2273 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2274 if (sr
== XTENSA_UNDEFINED
2275 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2277 /* Maybe it's a register number.... */
2279 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2281 as_bad (_("invalid register '%s' for '%s' instruction"),
2282 arg_strings
[1], opname
);
2285 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2286 if (sr
== XTENSA_UNDEFINED
)
2288 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2289 (long) val
, opname
);
2294 /* Remove the last argument, which is now part of the opcode. */
2295 free (arg_strings
[1]);
2299 /* Translate the opcode. */
2300 sr_name
= xtensa_sysreg_name (isa
, sr
);
2301 /* Another special case for "WSR.INTSET".... */
2302 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2304 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2305 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2307 *popname
= new_opname
;
2314 xtensa_translate_old_userreg_ops (char **popname
)
2316 xtensa_isa isa
= xtensa_default_isa
;
2318 char *opname
, *new_opname
;
2319 const char *sr_name
;
2320 bfd_boolean has_underbar
= FALSE
;
2323 if (opname
[0] == '_')
2325 has_underbar
= TRUE
;
2329 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2330 if (sr
!= XTENSA_UNDEFINED
)
2332 /* The new default name ("nnn") is different from the old default
2333 name ("URnnn"). The old default is handled below, and we don't
2334 want to recognize [RW]nnn, so do nothing if the name is the (new)
2336 static char namebuf
[10];
2337 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2338 if (strcmp (namebuf
, opname
+ 1) == 0)
2346 /* Only continue if the reg name is "URnnn". */
2347 if (opname
[1] != 'u' || opname
[2] != 'r')
2349 val
= strtoul (opname
+ 3, &end
, 10);
2353 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2354 if (sr
== XTENSA_UNDEFINED
)
2356 as_bad (_("invalid register number (%ld) for '%s'"),
2357 (long) val
, opname
);
2362 /* Translate the opcode. */
2363 sr_name
= xtensa_sysreg_name (isa
, sr
);
2364 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2365 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2366 opname
[0], sr_name
);
2368 *popname
= new_opname
;
2375 xtensa_translate_zero_immed (char *old_op
,
2385 gas_assert (opname
[0] != '_');
2387 if (strcmp (opname
, old_op
) != 0)
2390 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2392 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2394 xg_replace_opname (popname
, new_op
);
2395 free (arg_strings
[1]);
2396 arg_strings
[1] = arg_strings
[2];
2405 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2406 Returns non-zero if an error was found. */
2409 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2411 char *opname
= *popname
;
2412 bfd_boolean has_underbar
= FALSE
;
2416 has_underbar
= TRUE
;
2420 if (strcmp (opname
, "mov") == 0)
2422 if (use_transform () && !has_underbar
&& density_supported
)
2423 xg_replace_opname (popname
, "mov.n");
2426 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2428 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2429 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2430 strcpy (arg_strings
[2], arg_strings
[1]);
2436 if (strcmp (opname
, "bbsi.l") == 0)
2438 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2440 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2441 if (target_big_endian
)
2442 xg_reverse_shift_count (&arg_strings
[1]);
2446 if (strcmp (opname
, "bbci.l") == 0)
2448 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2450 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2451 if (target_big_endian
)
2452 xg_reverse_shift_count (&arg_strings
[1]);
2456 /* Don't do anything special with NOPs inside FLIX instructions. They
2457 are handled elsewhere. Real NOP instructions are always available
2458 in configurations with FLIX, so this should never be an issue but
2459 check for it anyway. */
2460 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2461 && strcmp (opname
, "nop") == 0)
2463 if (use_transform () && !has_underbar
&& density_supported
)
2464 xg_replace_opname (popname
, "nop.n");
2467 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2469 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2470 arg_strings
[0] = (char *) xmalloc (3);
2471 arg_strings
[1] = (char *) xmalloc (3);
2472 arg_strings
[2] = (char *) xmalloc (3);
2473 strcpy (arg_strings
[0], "a1");
2474 strcpy (arg_strings
[1], "a1");
2475 strcpy (arg_strings
[2], "a1");
2481 /* Recognize [RW]UR and [RWX]SR. */
2482 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2483 && (opname
[1] == 'u' || opname
[1] == 's'))
2484 || (opname
[0] == 'x' && opname
[1] == 's'))
2486 && opname
[3] == '\0')
2487 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2489 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2490 [RW]<name> if <name> is the non-default name of a user register. */
2491 if ((opname
[0] == 'r' || opname
[0] == 'w')
2492 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2493 return xtensa_translate_old_userreg_ops (popname
);
2495 /* Relax branches that don't allow comparisons against an immediate value
2496 of zero to the corresponding branches with implicit zero immediates. */
2497 if (!has_underbar
&& use_transform ())
2499 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2500 pnum_args
, arg_strings
))
2503 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2504 pnum_args
, arg_strings
))
2507 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2508 pnum_args
, arg_strings
))
2511 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2512 pnum_args
, arg_strings
))
2520 /* Functions for dealing with the Xtensa ISA. */
2522 /* Currently the assembler only allows us to use a single target per
2523 fragment. Because of this, only one operand for a given
2524 instruction may be symbolic. If there is a PC-relative operand,
2525 the last one is chosen. Otherwise, the result is the number of the
2526 last immediate operand, and if there are none of those, we fail and
2530 get_relaxable_immed (xtensa_opcode opcode
)
2532 int last_immed
= -1;
2535 if (opcode
== XTENSA_UNDEFINED
)
2538 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2539 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2541 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2543 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2545 if (last_immed
== -1
2546 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2553 static xtensa_opcode
2554 get_opcode_from_buf (const char *buf
, int slot
)
2556 static xtensa_insnbuf insnbuf
= NULL
;
2557 static xtensa_insnbuf slotbuf
= NULL
;
2558 xtensa_isa isa
= xtensa_default_isa
;
2563 insnbuf
= xtensa_insnbuf_alloc (isa
);
2564 slotbuf
= xtensa_insnbuf_alloc (isa
);
2567 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2568 fmt
= xtensa_format_decode (isa
, insnbuf
);
2569 if (fmt
== XTENSA_UNDEFINED
)
2570 return XTENSA_UNDEFINED
;
2572 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2573 return XTENSA_UNDEFINED
;
2575 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2576 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2580 #ifdef TENSILICA_DEBUG
2582 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2585 xtensa_print_insn_table (void)
2587 int num_opcodes
, num_operands
;
2588 xtensa_opcode opcode
;
2589 xtensa_isa isa
= xtensa_default_isa
;
2591 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2592 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2595 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2596 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2597 for (opn
= 0; opn
< num_operands
; opn
++)
2599 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2601 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2603 xtensa_regfile opnd_rf
=
2604 xtensa_operand_regfile (isa
, opcode
, opn
);
2605 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2607 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2608 fputs ("[lLr] ", stderr
);
2610 fputs ("i ", stderr
);
2612 fprintf (stderr
, "\n");
2618 print_vliw_insn (xtensa_insnbuf vbuf
)
2620 xtensa_isa isa
= xtensa_default_isa
;
2621 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2622 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2625 fprintf (stderr
, "format = %d\n", f
);
2627 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2629 xtensa_opcode opcode
;
2633 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2634 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2635 opname
= xtensa_opcode_name (isa
, opcode
);
2637 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2638 fprintf (stderr
, " operands = ");
2640 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2644 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2646 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2647 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2648 fprintf (stderr
, "%d ", val
);
2650 fprintf (stderr
, "\n");
2652 xtensa_insnbuf_free (isa
, sbuf
);
2655 #endif /* TENSILICA_DEBUG */
2659 is_direct_call_opcode (xtensa_opcode opcode
)
2661 xtensa_isa isa
= xtensa_default_isa
;
2662 int n
, num_operands
;
2664 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2667 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2668 for (n
= 0; n
< num_operands
; n
++)
2670 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2671 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2678 /* Convert from BFD relocation type code to slot and operand number.
2679 Returns non-zero on failure. */
2682 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2684 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2685 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2687 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2690 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2691 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2693 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2703 /* Convert from slot number to BFD relocation type code for the
2704 standard PC-relative relocations. Return BFD_RELOC_NONE on
2707 static bfd_reloc_code_real_type
2708 encode_reloc (int slot
)
2710 if (slot
< 0 || slot
> 14)
2711 return BFD_RELOC_NONE
;
2713 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2717 /* Convert from slot numbers to BFD relocation type code for the
2718 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2720 static bfd_reloc_code_real_type
2721 encode_alt_reloc (int slot
)
2723 if (slot
< 0 || slot
> 14)
2724 return BFD_RELOC_NONE
;
2726 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2731 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2734 xtensa_opcode opcode
,
2740 uint32 valbuf
= value
;
2742 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2744 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2746 as_bad_where ((char *) file
, line
,
2747 _("operand %d of '%s' has out of range value '%u'"),
2749 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2752 as_bad_where ((char *) file
, line
,
2753 _("operand %d of '%s' has invalid value '%u'"),
2755 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2760 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2766 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2769 xtensa_opcode opcode
,
2773 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2774 fmt
, slot
, slotbuf
, &val
);
2775 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2780 /* Checks for rules from xtensa-relax tables. */
2782 /* The routine xg_instruction_matches_option_term must return TRUE
2783 when a given option term is true. The meaning of all of the option
2784 terms is given interpretation by this function. */
2787 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2789 if (strcmp (option
->option_name
, "realnop") == 0
2790 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2792 /* These conditions were evaluated statically when building the
2793 relaxation table. There's no need to reevaluate them now. */
2796 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2797 return insn
->extra_arg
.X_op
== O_register
;
2800 as_fatal (_("internal error: unknown option name '%s'"),
2801 option
->option_name
);
2807 xg_instruction_matches_or_options (TInsn
*insn
,
2808 const ReqOrOptionList
*or_option
)
2810 const ReqOrOption
*option
;
2811 /* Must match each of the AND terms. */
2812 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2814 if (xg_instruction_matches_option_term (insn
, option
))
2822 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2824 const ReqOption
*req_options
;
2825 /* Must match each of the AND terms. */
2826 for (req_options
= options
;
2827 req_options
!= NULL
;
2828 req_options
= req_options
->next
)
2830 /* Must match one of the OR clauses. */
2831 if (!xg_instruction_matches_or_options (insn
,
2832 req_options
->or_option_terms
))
2839 /* Return the transition rule that matches or NULL if none matches. */
2842 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2844 PreconditionList
*condition_l
;
2846 if (rule
->opcode
!= insn
->opcode
)
2849 for (condition_l
= rule
->conditions
;
2850 condition_l
!= NULL
;
2851 condition_l
= condition_l
->next
)
2855 Precondition
*cond
= condition_l
->precond
;
2860 /* The expression must be the constant. */
2861 gas_assert (cond
->op_num
< insn
->ntok
);
2862 exp1
= &insn
->tok
[cond
->op_num
];
2863 if (expr_is_const (exp1
))
2868 if (get_expr_const (exp1
) != cond
->op_data
)
2872 if (get_expr_const (exp1
) == cond
->op_data
)
2879 else if (expr_is_register (exp1
))
2884 if (get_expr_register (exp1
) != cond
->op_data
)
2888 if (get_expr_register (exp1
) == cond
->op_data
)
2900 gas_assert (cond
->op_num
< insn
->ntok
);
2901 gas_assert (cond
->op_data
< insn
->ntok
);
2902 exp1
= &insn
->tok
[cond
->op_num
];
2903 exp2
= &insn
->tok
[cond
->op_data
];
2908 if (!expr_is_equal (exp1
, exp2
))
2912 if (expr_is_equal (exp1
, exp2
))
2924 if (!xg_instruction_matches_options (insn
, rule
->options
))
2932 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2934 bfd_boolean a_greater
= FALSE
;
2935 bfd_boolean b_greater
= FALSE
;
2937 ReqOptionList
*l_a
= a
->options
;
2938 ReqOptionList
*l_b
= b
->options
;
2940 /* We only care if they both are the same except for
2941 a const16 vs. an l32r. */
2943 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2945 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2946 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2947 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2949 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2951 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2953 /* This is the case we care about. */
2954 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2955 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2962 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2963 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2973 l_or_a
= l_or_a
->next
;
2974 l_or_b
= l_or_b
->next
;
2976 if (l_or_a
|| l_or_b
)
2985 /* Incomparable if the substitution was used differently in two cases. */
2986 if (a_greater
&& b_greater
)
2998 static TransitionRule
*
2999 xg_instruction_match (TInsn
*insn
)
3001 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3003 gas_assert (insn
->opcode
< table
->num_opcodes
);
3005 /* Walk through all of the possible transitions. */
3006 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3008 TransitionRule
*rule
= l
->rule
;
3009 if (xg_instruction_matches_rule (insn
, rule
))
3016 /* Various Other Internal Functions. */
3019 is_unique_insn_expansion (TransitionRule
*r
)
3021 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3023 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3029 /* Check if there is exactly one relaxation for INSN that converts it to
3030 another instruction of equal or larger size. If so, and if TARG is
3031 non-null, go ahead and generate the relaxed instruction into TARG. If
3032 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3033 instruction, i.e., ignore relaxations that convert to an instruction of
3034 equal size. In some contexts where this function is used, only
3035 a single widening is allowed and the NARROW_ONLY argument is used to
3036 exclude cases like ADDI being "widened" to an ADDMI, which may
3037 later be relaxed to an ADDMI/ADDI pair. */
3040 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3042 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3044 TransitionRule
*match
= 0;
3046 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3047 gas_assert (insn
->opcode
< table
->num_opcodes
);
3049 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3051 TransitionRule
*rule
= l
->rule
;
3053 if (xg_instruction_matches_rule (insn
, rule
)
3054 && is_unique_insn_expansion (rule
)
3055 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3056 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3067 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3072 /* Return the maximum number of bytes this opcode can expand to. */
3075 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3077 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3079 int max_size
= xg_get_single_size (opcode
);
3081 gas_assert (opcode
< table
->num_opcodes
);
3083 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3085 TransitionRule
*rule
= l
->rule
;
3086 BuildInstr
*build_list
;
3091 build_list
= rule
->to_instr
;
3092 if (is_unique_insn_expansion (rule
))
3094 gas_assert (build_list
->typ
== INSTR_INSTR
);
3095 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3098 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3100 switch (build_list
->typ
)
3103 this_size
+= xg_get_single_size (build_list
->opcode
);
3105 case INSTR_LITERAL_DEF
:
3106 case INSTR_LABEL_DEF
:
3111 if (this_size
> max_size
)
3112 max_size
= this_size
;
3118 /* Return the maximum number of literal bytes this opcode can generate. */
3121 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3123 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3127 gas_assert (opcode
< table
->num_opcodes
);
3129 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3131 TransitionRule
*rule
= l
->rule
;
3132 BuildInstr
*build_list
;
3137 build_list
= rule
->to_instr
;
3138 if (is_unique_insn_expansion (rule
))
3140 gas_assert (build_list
->typ
== INSTR_INSTR
);
3141 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3144 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3146 switch (build_list
->typ
)
3148 case INSTR_LITERAL_DEF
:
3149 /* Hard-coded 4-byte literal. */
3153 case INSTR_LABEL_DEF
:
3158 if (this_size
> max_size
)
3159 max_size
= this_size
;
3166 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3168 int steps_taken
= 0;
3169 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3172 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3173 gas_assert (insn
->opcode
< table
->num_opcodes
);
3175 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3177 TransitionRule
*rule
= l
->rule
;
3179 if (xg_instruction_matches_rule (insn
, rule
))
3181 if (steps_taken
== lateral_steps
)
3191 get_special_literal_symbol (void)
3193 static symbolS
*sym
= NULL
;
3196 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3202 get_special_label_symbol (void)
3204 static symbolS
*sym
= NULL
;
3207 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3213 xg_valid_literal_expression (const expressionS
*exp
)
3235 /* This will check to see if the value can be converted into the
3236 operand type. It will return TRUE if it does not fit. */
3239 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3241 uint32 valbuf
= value
;
3242 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3248 /* Assumes: All immeds are constants. Check that all constants fit
3249 into their immeds; return FALSE if not. */
3252 xg_immeds_fit (const TInsn
*insn
)
3254 xtensa_isa isa
= xtensa_default_isa
;
3258 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3259 for (i
= 0; i
< n
; ++i
)
3261 const expressionS
*exp
= &insn
->tok
[i
];
3263 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3270 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3275 /* The symbol should have a fixup associated with it. */
3284 /* This should only be called after we have an initial
3285 estimate of the addresses. */
3288 xg_symbolic_immeds_fit (const TInsn
*insn
,
3294 xtensa_isa isa
= xtensa_default_isa
;
3302 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3304 for (i
= 0; i
< n
; ++i
)
3306 const expressionS
*exp
= &insn
->tok
[i
];
3308 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3315 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3321 /* Check for the worst case. */
3322 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3327 /* We only allow symbols for PC-relative references.
3328 If pc_frag == 0, then we don't have frag locations yet. */
3330 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3333 /* If it is a weak symbol or a symbol in a different section,
3334 it cannot be known to fit at assembly time. */
3335 if (S_IS_WEAK (exp
->X_add_symbol
)
3336 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3338 /* For a direct call with --no-longcalls, be optimistic and
3339 assume it will be in range. If the symbol is weak and
3340 undefined, it may remain undefined at link-time, in which
3341 case it will have a zero value and almost certainly be out
3342 of range for a direct call; thus, relax for undefined weak
3343 symbols even if longcalls is not enabled. */
3344 if (is_direct_call_opcode (insn
->opcode
)
3345 && ! pc_frag
->tc_frag_data
.use_longcalls
3346 && (! S_IS_WEAK (exp
->X_add_symbol
)
3347 || S_IS_DEFINED (exp
->X_add_symbol
)))
3353 symbolP
= exp
->X_add_symbol
;
3354 sym_frag
= symbol_get_frag (symbolP
);
3355 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3356 pc
= pc_frag
->fr_address
+ pc_offset
;
3358 /* If frag has yet to be reached on this pass, assume it
3359 will move by STRETCH just as we did. If this is not so,
3360 it will be because some frag between grows, and that will
3361 force another pass. Beware zero-length frags. There
3362 should be a faster way to do this. */
3365 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3366 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3371 new_offset
= target
;
3372 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3373 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3378 /* The symbol should have a fixup associated with it. */
3387 /* Return TRUE on success. */
3390 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3396 targ
->debug_line
= insn
->debug_line
;
3397 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3402 targ
->opcode
= bi
->opcode
;
3403 targ
->insn_type
= ITYPE_INSN
;
3404 targ
->is_specific_opcode
= FALSE
;
3406 for (; op
!= NULL
; op
= op
->next
)
3408 int op_num
= op
->op_num
;
3409 int op_data
= op
->op_data
;
3411 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3413 if (targ
->ntok
<= op_num
)
3414 targ
->ntok
= op_num
+ 1;
3419 set_expr_const (&targ
->tok
[op_num
], op_data
);
3422 gas_assert (op_data
< insn
->ntok
);
3423 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3426 if (insn
->extra_arg
.X_op
!= O_register
)
3428 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3431 sym
= get_special_literal_symbol ();
3432 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3433 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3434 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3435 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3438 sym
= get_special_label_symbol ();
3439 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3441 case OP_OPERAND_HI16U
:
3442 case OP_OPERAND_LOW16U
:
3443 gas_assert (op_data
< insn
->ntok
);
3444 if (expr_is_const (&insn
->tok
[op_data
]))
3447 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3448 val
= xg_apply_userdef_op_fn (op
->typ
,
3451 targ
->tok
[op_num
].X_add_number
= val
;
3455 /* For const16 we can create relocations for these. */
3456 if (targ
->opcode
== XTENSA_UNDEFINED
3457 || (targ
->opcode
!= xtensa_const16_opcode
))
3459 gas_assert (op_data
< insn
->ntok
);
3460 /* Need to build a O_lo16 or O_hi16. */
3461 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3462 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3464 if (op
->typ
== OP_OPERAND_HI16U
)
3465 targ
->tok
[op_num
].X_op
= O_hi16
;
3466 else if (op
->typ
== OP_OPERAND_LOW16U
)
3467 targ
->tok
[op_num
].X_op
= O_lo16
;
3474 /* currently handles:
3477 OP_OPERAND_F32MINUS */
3478 if (xg_has_userdef_op_fn (op
->typ
))
3480 gas_assert (op_data
< insn
->ntok
);
3481 if (expr_is_const (&insn
->tok
[op_data
]))
3484 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3485 val
= xg_apply_userdef_op_fn (op
->typ
,
3488 targ
->tok
[op_num
].X_add_number
= val
;
3491 return FALSE
; /* We cannot use a relocation for this. */
3500 case INSTR_LITERAL_DEF
:
3502 targ
->opcode
= XTENSA_UNDEFINED
;
3503 targ
->insn_type
= ITYPE_LITERAL
;
3504 targ
->is_specific_opcode
= FALSE
;
3505 for (; op
!= NULL
; op
= op
->next
)
3507 int op_num
= op
->op_num
;
3508 int op_data
= op
->op_data
;
3509 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3511 if (targ
->ntok
<= op_num
)
3512 targ
->ntok
= op_num
+ 1;
3517 gas_assert (op_data
< insn
->ntok
);
3518 /* We can only pass resolvable literals through. */
3519 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3521 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3533 case INSTR_LABEL_DEF
:
3535 targ
->opcode
= XTENSA_UNDEFINED
;
3536 targ
->insn_type
= ITYPE_LABEL
;
3537 targ
->is_specific_opcode
= FALSE
;
3538 /* Literal with no ops is a label? */
3539 gas_assert (op
== NULL
);
3550 /* Return TRUE on success. */
3553 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3555 for (; bi
!= NULL
; bi
= bi
->next
)
3557 TInsn
*next_insn
= istack_push_space (istack
);
3559 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3566 /* Return TRUE on valid expansion. */
3569 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3571 int stack_size
= istack
->ninsn
;
3572 int steps_taken
= 0;
3573 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3576 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3577 gas_assert (insn
->opcode
< table
->num_opcodes
);
3579 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3581 TransitionRule
*rule
= l
->rule
;
3583 if (xg_instruction_matches_rule (insn
, rule
))
3585 if (lateral_steps
== steps_taken
)
3589 /* This is it. Expand the rule to the stack. */
3590 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3593 /* Check to see if it fits. */
3594 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3596 TInsn
*tinsn
= &istack
->insn
[i
];
3598 if (tinsn
->insn_type
== ITYPE_INSN
3599 && !tinsn_has_symbolic_operands (tinsn
)
3600 && !xg_immeds_fit (tinsn
))
3602 istack
->ninsn
= stack_size
;
3615 /* Relax the assembly instruction at least "min_steps".
3616 Return the number of steps taken.
3618 For relaxation to correctly terminate, every relaxation chain must
3619 terminate in one of two ways:
3621 1. If the chain from one instruction to the next consists entirely of
3622 single instructions, then the chain *must* handle all possible
3623 immediates without failing. It must not ever fail because an
3624 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3625 chain is one example. L32R loads 32 bits, and there cannot be an
3626 immediate larger than 32 bits, so it satisfies this condition.
3627 Single instruction relaxation chains are as defined by
3628 xg_is_single_relaxable_instruction.
3630 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3631 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3633 Strictly speaking, in most cases you can violate condition 1 and be OK
3634 -- in particular when the last two instructions have the same single
3635 size. But nevertheless, you should guarantee the above two conditions.
3637 We could fix this so that single-instruction expansions correctly
3638 terminate when they can't handle the range, but the error messages are
3639 worse, and it actually turns out that in every case but one (18-bit wide
3640 branches), you need a multi-instruction expansion to get the full range
3641 anyway. And because 18-bit branches are handled identically to 15-bit
3642 branches, there isn't any point in changing it. */
3645 xg_assembly_relax (IStack
*istack
,
3648 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3649 offsetT pc_offset
, /* offset in fragment */
3650 int min_steps
, /* minimum conversion steps */
3651 long stretch
) /* number of bytes stretched so far */
3653 int steps_taken
= 0;
3655 /* Some of its immeds don't fit. Try to build a relaxed version.
3656 This may go through a couple of stages of single instruction
3657 transformations before we get there. */
3659 TInsn single_target
;
3661 int lateral_steps
= 0;
3662 int istack_size
= istack
->ninsn
;
3664 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3665 && steps_taken
>= min_steps
)
3667 istack_push (istack
, insn
);
3670 current_insn
= *insn
;
3672 /* Walk through all of the single instruction expansions. */
3673 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3676 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3679 if (steps_taken
>= min_steps
)
3681 istack_push (istack
, &single_target
);
3685 current_insn
= single_target
;
3688 /* Now check for a multi-instruction expansion. */
3689 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3691 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3694 if (steps_taken
>= min_steps
)
3696 istack_push (istack
, ¤t_insn
);
3701 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3703 if (steps_taken
>= min_steps
)
3707 istack
->ninsn
= istack_size
;
3710 /* It's not going to work -- use the original. */
3711 istack_push (istack
, insn
);
3717 xg_finish_frag (char *last_insn
,
3718 enum xtensa_relax_statesE frag_state
,
3719 enum xtensa_relax_statesE slot0_state
,
3721 bfd_boolean is_insn
)
3723 /* Finish off this fragment so that it has at LEAST the desired
3724 max_growth. If it doesn't fit in this fragment, close this one
3725 and start a new one. In either case, return a pointer to the
3726 beginning of the growth area. */
3730 frag_grow (max_growth
);
3731 old_frag
= frag_now
;
3733 frag_now
->fr_opcode
= last_insn
;
3735 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3737 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3738 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3740 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3741 xtensa_set_frag_assembly_state (frag_now
);
3743 /* Just to make sure that we did not split it up. */
3744 gas_assert (old_frag
->fr_next
== frag_now
);
3748 /* Return TRUE if the target frag is one of the next non-empty frags. */
3751 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3756 for (; fragP
; fragP
= fragP
->fr_next
)
3758 if (fragP
== target
)
3760 if (fragP
->fr_fix
!= 0)
3762 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3764 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3765 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3767 if (fragP
->fr_type
== rs_space
)
3775 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3777 xtensa_isa isa
= xtensa_default_isa
;
3779 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3784 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3785 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3788 for (i
= 0; i
< num_ops
; i
++)
3790 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3796 if (target_op
== -1)
3799 if (insn
->ntok
<= target_op
)
3802 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3805 sym
= insn
->tok
[target_op
].X_add_symbol
;
3809 if (insn
->tok
[target_op
].X_add_number
!= 0)
3812 target_frag
= symbol_get_frag (sym
);
3813 if (target_frag
== NULL
)
3816 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3817 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3825 xg_add_branch_and_loop_targets (TInsn
*insn
)
3827 xtensa_isa isa
= xtensa_default_isa
;
3828 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3830 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3833 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3834 && insn
->tok
[i
].X_op
== O_symbol
)
3835 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3839 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3840 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3844 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3846 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3847 && insn
->tok
[i
].X_op
== O_symbol
)
3849 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3850 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3851 if (S_IS_DEFINED (sym
))
3852 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3859 /* Return FALSE if no error. */
3862 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3867 switch (instr_spec
->typ
)
3870 new_insn
->insn_type
= ITYPE_INSN
;
3871 new_insn
->opcode
= instr_spec
->opcode
;
3873 case INSTR_LITERAL_DEF
:
3874 new_insn
->insn_type
= ITYPE_LITERAL
;
3875 new_insn
->opcode
= XTENSA_UNDEFINED
;
3877 case INSTR_LABEL_DEF
:
3880 new_insn
->is_specific_opcode
= FALSE
;
3881 new_insn
->debug_line
= old_insn
->debug_line
;
3882 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3884 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3887 const expressionS
*src_exp
;
3893 /* The expression must be the constant. */
3894 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3895 exp
= &new_insn
->tok
[b_op
->op_num
];
3896 set_expr_const (exp
, b_op
->op_data
);
3900 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3901 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3902 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3903 exp
= &new_insn
->tok
[b_op
->op_num
];
3904 copy_expr (exp
, src_exp
);
3909 as_bad (_("can't handle generation of literal/labels yet"));
3913 as_bad (_("can't handle undefined OP TYPE"));
3918 new_insn
->ntok
= num_ops
;
3923 /* Return TRUE if it was simplified. */
3926 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3928 TransitionRule
*rule
;
3929 BuildInstr
*insn_spec
;
3931 if (old_insn
->is_specific_opcode
|| !density_supported
)
3934 rule
= xg_instruction_match (old_insn
);
3938 insn_spec
= rule
->to_instr
;
3939 /* There should only be one. */
3940 gas_assert (insn_spec
!= NULL
);
3941 gas_assert (insn_spec
->next
== NULL
);
3942 if (insn_spec
->next
!= NULL
)
3945 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3951 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3952 l32i.n. (2) Check the number of operands. (3) Place the instruction
3953 tokens into the stack or relax it and place multiple
3954 instructions/literals onto the stack. Return FALSE if no error. */
3957 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3961 bfd_boolean do_expand
;
3963 tinsn_init (&new_insn
);
3965 /* Narrow it if we can. xg_simplify_insn now does all the
3966 appropriate checking (e.g., for the density option). */
3967 if (xg_simplify_insn (orig_insn
, &new_insn
))
3968 orig_insn
= &new_insn
;
3970 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3972 if (orig_insn
->ntok
< noperands
)
3974 as_bad (_("found %d operands for '%s': Expected %d"),
3976 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3980 if (orig_insn
->ntok
> noperands
)
3981 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3983 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3986 /* If there are not enough operands, we will assert above. If there
3987 are too many, just cut out the extras here. */
3988 orig_insn
->ntok
= noperands
;
3990 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3993 /* Special case for extui opcode which has constraints not handled
3994 by the ordinary operand encoding checks. The number of operands
3995 and related syntax issues have already been checked. */
3996 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3998 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3999 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4000 if (shiftimm
+ maskimm
> 32)
4002 as_bad (_("immediate operands sum to greater than 32"));
4007 /* If the instruction will definitely need to be relaxed, it is better
4008 to expand it now for better scheduling. Decide whether to expand
4010 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4012 /* Calls should be expanded to longcalls only in the backend relaxation
4013 so that the assembly scheduler will keep the L32R/CALLX instructions
4015 if (is_direct_call_opcode (orig_insn
->opcode
))
4018 if (tinsn_has_symbolic_operands (orig_insn
))
4020 /* The values of symbolic operands are not known yet, so only expand
4021 now if an operand is "complex" (e.g., difference of symbols) and
4022 will have to be stored as a literal regardless of the value. */
4023 if (!tinsn_has_complex_operands (orig_insn
))
4026 else if (xg_immeds_fit (orig_insn
))
4030 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4032 istack_push (istack
, orig_insn
);
4038 /* Return TRUE if the section flags are marked linkonce
4039 or the name is .gnu.linkonce.*. */
4041 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4044 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4046 flagword flags
, link_once_flags
;
4048 flags
= bfd_get_section_flags (abfd
, sec
);
4049 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4051 /* Flags might not be set yet. */
4052 if (!link_once_flags
4053 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4054 link_once_flags
= SEC_LINK_ONCE
;
4056 return (link_once_flags
!= 0);
4061 xtensa_add_literal_sym (symbolS
*sym
)
4065 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4067 l
->next
= literal_syms
;
4073 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4075 static int lit_num
= 0;
4076 static char name
[256];
4079 sprintf (name
, ".L_lit_sym%d", lit_num
);
4081 /* Create a local symbol. If it is in a linkonce section, we have to
4082 be careful to make sure that if it is used in a relocation that the
4083 symbol will be in the output file. */
4084 if (get_is_linkonce_section (stdoutput
, sec
))
4086 symbolP
= symbol_new (name
, sec
, 0, frag
);
4087 S_CLEAR_EXTERNAL (symbolP
);
4088 /* symbolP->local = 1; */
4091 symbolP
= symbol_new (name
, sec
, 0, frag
);
4093 xtensa_add_literal_sym (symbolP
);
4100 /* Currently all literals that are generated here are 32-bit L32R targets. */
4103 xg_assemble_literal (/* const */ TInsn
*insn
)
4106 symbolS
*lit_sym
= NULL
;
4107 bfd_reloc_code_real_type reloc
;
4108 bfd_boolean pcrel
= FALSE
;
4111 /* size = 4 for L32R. It could easily be larger when we move to
4112 larger constants. Add a parameter later. */
4113 offsetT litsize
= 4;
4114 offsetT litalign
= 2; /* 2^2 = 4 */
4115 expressionS saved_loc
;
4116 expressionS
* emit_val
;
4118 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4120 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4121 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4123 xtensa_switch_to_literal_fragment (&state
);
4125 emit_val
= &insn
->tok
[0];
4126 if (emit_val
->X_op
== O_big
)
4128 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4131 /* This happens when someone writes a "movi a2, big_number". */
4132 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4133 _("invalid immediate"));
4134 xtensa_restore_emit_state (&state
);
4139 /* Force a 4-byte align here. Note that this opens a new frag, so all
4140 literals done with this function have a frag to themselves. That's
4141 important for the way text section literals work. */
4142 frag_align (litalign
, 0, 0);
4143 record_alignment (now_seg
, litalign
);
4145 switch (emit_val
->X_op
)
4155 p
= frag_more (litsize
);
4156 xtensa_set_frag_assembly_state (frag_now
);
4157 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4158 if (emit_val
->X_add_symbol
)
4159 emit_val
->X_op
= O_symbol
;
4161 emit_val
->X_op
= O_constant
;
4162 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4163 litsize
, emit_val
, pcrel
, reloc
);
4167 emit_expr (emit_val
, litsize
);
4171 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4172 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4173 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4174 lit_sym
= frag_now
->fr_symbol
;
4177 xtensa_restore_emit_state (&state
);
4183 xg_assemble_literal_space (/* const */ int size
, int slot
)
4186 /* We might have to do something about this alignment. It only
4187 takes effect if something is placed here. */
4188 offsetT litalign
= 2; /* 2^2 = 4 */
4189 fragS
*lit_saved_frag
;
4191 gas_assert (size
% 4 == 0);
4193 xtensa_switch_to_literal_fragment (&state
);
4195 /* Force a 4-byte align here. */
4196 frag_align (litalign
, 0, 0);
4197 record_alignment (now_seg
, litalign
);
4201 lit_saved_frag
= frag_now
;
4202 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4203 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4204 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4207 xtensa_restore_emit_state (&state
);
4208 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4212 /* Put in a fixup record based on the opcode.
4213 Return TRUE on success. */
4216 xg_add_opcode_fix (TInsn
*tinsn
,
4224 xtensa_opcode opcode
= tinsn
->opcode
;
4225 bfd_reloc_code_real_type reloc
;
4226 reloc_howto_type
*howto
;
4230 reloc
= BFD_RELOC_NONE
;
4232 /* First try the special cases for "alternate" relocs. */
4233 if (opcode
== xtensa_l32r_opcode
)
4235 if (fragP
->tc_frag_data
.use_absolute_literals
)
4236 reloc
= encode_alt_reloc (slot
);
4238 else if (opcode
== xtensa_const16_opcode
)
4240 if (exp
->X_op
== O_lo16
)
4242 reloc
= encode_reloc (slot
);
4243 exp
->X_op
= O_symbol
;
4245 else if (exp
->X_op
== O_hi16
)
4247 reloc
= encode_alt_reloc (slot
);
4248 exp
->X_op
= O_symbol
;
4252 if (opnum
!= get_relaxable_immed (opcode
))
4254 as_bad (_("invalid relocation for operand %i of '%s'"),
4255 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4259 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4260 into the symbol table where the generic portions of the assembler
4261 won't know what to do with them. */
4262 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4264 as_bad (_("invalid expression for operand %i of '%s'"),
4265 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4269 /* Next try the generic relocs. */
4270 if (reloc
== BFD_RELOC_NONE
)
4271 reloc
= encode_reloc (slot
);
4272 if (reloc
== BFD_RELOC_NONE
)
4274 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4278 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4281 as_bad (_("undefined symbol for opcode \"%s\""),
4282 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4286 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4287 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4288 howto
->pc_relative
, reloc
);
4289 the_fix
->fx_no_overflow
= 1;
4290 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4291 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4292 the_fix
->tc_fix_data
.slot
= slot
;
4299 xg_emit_insn_to_buf (TInsn
*tinsn
,
4303 bfd_boolean build_fix
)
4305 static xtensa_insnbuf insnbuf
= NULL
;
4306 bfd_boolean has_symbolic_immed
= FALSE
;
4307 bfd_boolean ok
= TRUE
;
4310 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4312 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4313 if (has_symbolic_immed
&& build_fix
)
4316 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4317 int slot
= xg_get_single_slot (tinsn
->opcode
);
4318 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4319 expressionS
*exp
= &tinsn
->tok
[opnum
];
4321 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4324 fragP
->tc_frag_data
.is_insn
= TRUE
;
4325 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4326 (unsigned char *) buf
, 0);
4332 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4334 symbolS
*sym
= get_special_literal_symbol ();
4338 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4339 for (i
= 0; i
< insn
->ntok
; i
++)
4340 if (insn
->tok
[i
].X_add_symbol
== sym
)
4341 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4347 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4349 symbolS
*sym
= get_special_label_symbol ();
4351 for (i
= 0; i
< insn
->ntok
; i
++)
4352 if (insn
->tok
[i
].X_add_symbol
== sym
)
4353 insn
->tok
[i
].X_add_symbol
= label_sym
;
4358 /* Return TRUE if the instruction can write to the specified
4359 integer register. */
4362 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4366 xtensa_isa isa
= xtensa_default_isa
;
4368 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4370 for (i
= 0; i
< num_ops
; i
++)
4373 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4374 if ((inout
== 'o' || inout
== 'm')
4375 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4377 xtensa_regfile opnd_rf
=
4378 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4379 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4381 if ((insn
->tok
[i
].X_op
== O_register
)
4382 && (insn
->tok
[i
].X_add_number
== regnum
))
4392 is_bad_loopend_opcode (const TInsn
*tinsn
)
4394 xtensa_opcode opcode
= tinsn
->opcode
;
4396 if (opcode
== XTENSA_UNDEFINED
)
4399 if (opcode
== xtensa_call0_opcode
4400 || opcode
== xtensa_callx0_opcode
4401 || opcode
== xtensa_call4_opcode
4402 || opcode
== xtensa_callx4_opcode
4403 || opcode
== xtensa_call8_opcode
4404 || opcode
== xtensa_callx8_opcode
4405 || opcode
== xtensa_call12_opcode
4406 || opcode
== xtensa_callx12_opcode
4407 || opcode
== xtensa_isync_opcode
4408 || opcode
== xtensa_ret_opcode
4409 || opcode
== xtensa_ret_n_opcode
4410 || opcode
== xtensa_retw_opcode
4411 || opcode
== xtensa_retw_n_opcode
4412 || opcode
== xtensa_waiti_opcode
4413 || opcode
== xtensa_rsr_lcount_opcode
)
4420 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4421 This allows the debugger to add unaligned labels.
4422 Also, the assembler generates stabs labels that need
4423 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4426 is_unaligned_label (symbolS
*sym
)
4428 const char *name
= S_GET_NAME (sym
);
4429 static size_t fake_size
= 0;
4433 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4436 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4438 fake_size
= strlen (FAKE_LABEL_NAME
);
4441 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4442 && (name
[fake_size
] == 'F'
4443 || name
[fake_size
] == 'L'
4444 || (name
[fake_size
] == 'e'
4445 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4453 next_non_empty_frag (const fragS
*fragP
)
4455 fragS
*next_fragP
= fragP
->fr_next
;
4457 /* Sometimes an empty will end up here due storage allocation issues.
4458 So we have to skip until we find something legit. */
4459 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4460 next_fragP
= next_fragP
->fr_next
;
4462 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4470 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4472 xtensa_opcode out_opcode
;
4473 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4475 if (next_fragP
== NULL
)
4478 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4479 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4481 *opcode
= out_opcode
;
4489 frag_format_size (const fragS
*fragP
)
4491 static xtensa_insnbuf insnbuf
= NULL
;
4492 xtensa_isa isa
= xtensa_default_isa
;
4497 insnbuf
= xtensa_insnbuf_alloc (isa
);
4500 return XTENSA_UNDEFINED
;
4502 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4503 (unsigned char *) fragP
->fr_literal
, 0);
4505 fmt
= xtensa_format_decode (isa
, insnbuf
);
4506 if (fmt
== XTENSA_UNDEFINED
)
4507 return XTENSA_UNDEFINED
;
4508 fmt_size
= xtensa_format_length (isa
, fmt
);
4510 /* If the next format won't be changing due to relaxation, just
4511 return the length of the first format. */
4512 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4515 /* If during relaxation we have to pull an instruction out of a
4516 multi-slot instruction, we will return the more conservative
4517 number. This works because alignment on bigger instructions
4518 is more restrictive than alignment on smaller instructions.
4519 This is more conservative than we would like, but it happens
4522 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4525 /* If we aren't doing one of our own relaxations or it isn't
4526 slot-based, then the insn size won't change. */
4527 if (fragP
->fr_type
!= rs_machine_dependent
)
4529 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4532 /* If an instruction is about to grow, return the longer size. */
4533 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4534 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4535 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4537 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4538 instruction in the relaxed version is of length 3. (The case
4539 where we have to pull the instruction out of a FLIX bundle
4540 is handled conservatively above.) However, frags with opcodes
4541 that are expanding to wide branches end up having formats that
4542 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4543 we can't tell directly what format the relaxer picked. This
4544 is a wart in the design of the relaxer that should someday be
4545 fixed, but would require major changes, or at least should
4546 be accompanied by major changes to make use of that data.
4548 In any event, we can tell that we are expanding from a single-slot
4549 format to a wider one with the logic below. */
4552 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4554 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4556 if (relaxed_size
== xtensa_format_length (isa
, i
))
4557 return relaxed_size
;
4563 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4564 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4571 next_frag_format_size (const fragS
*fragP
)
4573 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4574 return frag_format_size (next_fragP
);
4578 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4579 required two-byte instructions to be treated as three-byte instructions
4580 for loop instruction alignment. This restriction was removed beginning
4581 with Xtensa LX. Now the only requirement on loop instruction alignment
4582 is that the first instruction of the loop must appear at an address that
4583 does not cross a fetch boundary. */
4586 get_loop_align_size (int insn_size
)
4588 if (insn_size
== XTENSA_UNDEFINED
)
4589 return xtensa_fetch_width
;
4591 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4598 /* If the next legit fragment is an end-of-loop marker,
4599 switch its state so it will instantiate a NOP. */
4602 update_next_frag_state (fragS
*fragP
)
4604 fragS
*next_fragP
= fragP
->fr_next
;
4605 fragS
*new_target
= NULL
;
4609 /* We are guaranteed there will be one of these... */
4610 while (!(next_fragP
->fr_type
== rs_machine_dependent
4611 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4612 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4613 next_fragP
= next_fragP
->fr_next
;
4615 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4616 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4617 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4619 /* ...and one of these. */
4620 new_target
= next_fragP
->fr_next
;
4621 while (!(new_target
->fr_type
== rs_machine_dependent
4622 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4623 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4624 new_target
= new_target
->fr_next
;
4626 gas_assert (new_target
->fr_type
== rs_machine_dependent
4627 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4628 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4631 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4633 if (next_fragP
->fr_type
== rs_machine_dependent
4634 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4636 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4640 next_fragP
= next_fragP
->fr_next
;
4646 next_frag_is_branch_target (const fragS
*fragP
)
4648 /* Sometimes an empty will end up here due to storage allocation issues,
4649 so we have to skip until we find something legit. */
4650 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4652 if (fragP
->tc_frag_data
.is_branch_target
)
4654 if (fragP
->fr_fix
!= 0)
4662 next_frag_is_loop_target (const fragS
*fragP
)
4664 /* Sometimes an empty will end up here due storage allocation issues.
4665 So we have to skip until we find something legit. */
4666 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4668 if (fragP
->tc_frag_data
.is_loop_target
)
4670 if (fragP
->fr_fix
!= 0)
4677 /* As specified in the relaxation table, when a loop instruction is
4678 relaxed, there are 24 bytes between the loop instruction itself and
4679 the first instruction in the loop. */
4681 #define RELAXED_LOOP_INSN_BYTES 24
4684 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4686 const fragS
*next_fragp
= fragp
->fr_next
;
4687 xtensa_opcode next_opcode
;
4689 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4692 /* Sometimes an empty will end up here due to storage allocation issues,
4693 so we have to skip until we find something legit. */
4694 while (next_fragp
->fr_fix
== 0)
4695 next_fragp
= next_fragp
->fr_next
;
4697 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4700 /* There is some implicit knowledge encoded in here.
4701 The LOOP instructions that are NOT RELAX_IMMED have
4702 been relaxed. Note that we can assume that the LOOP
4703 instruction is in slot 0 because loops aren't bundleable. */
4704 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4705 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4711 /* Mark a location where we can later insert literal frags. Update
4712 the section's literal_pool_loc, so subsequent literals can be
4713 placed nearest to their use. */
4716 xtensa_mark_literal_pool_location (void)
4718 /* Any labels pointing to the current location need
4719 to be adjusted to after the literal pool. */
4721 fragS
*pool_location
;
4723 if (use_literal_section
)
4726 /* We stash info in these frags so we can later move the literal's
4727 fixes into this frchain's fix list. */
4728 pool_location
= frag_now
;
4729 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4730 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4731 frag_variant (rs_machine_dependent
, 0, 0,
4732 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4733 xtensa_set_frag_assembly_state (frag_now
);
4734 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4735 frag_variant (rs_machine_dependent
, 0, 0,
4736 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4737 xtensa_set_frag_assembly_state (frag_now
);
4739 /* Now put a frag into the literal pool that points to this location. */
4740 set_literal_pool_location (now_seg
, pool_location
);
4741 xtensa_switch_to_non_abs_literal_fragment (&s
);
4742 frag_align (2, 0, 0);
4743 record_alignment (now_seg
, 2);
4745 /* Close whatever frag is there. */
4746 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4747 xtensa_set_frag_assembly_state (frag_now
);
4748 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4749 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4750 xtensa_restore_emit_state (&s
);
4751 xtensa_set_frag_assembly_state (frag_now
);
4755 /* Build a nop of the correct size into tinsn. */
4758 build_nop (TInsn
*tinsn
, int size
)
4764 tinsn
->opcode
= xtensa_nop_n_opcode
;
4766 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4767 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4771 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4773 tinsn
->opcode
= xtensa_or_opcode
;
4774 set_expr_const (&tinsn
->tok
[0], 1);
4775 set_expr_const (&tinsn
->tok
[1], 1);
4776 set_expr_const (&tinsn
->tok
[2], 1);
4780 tinsn
->opcode
= xtensa_nop_opcode
;
4782 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4787 /* Assemble a NOP of the requested size in the buffer. User must have
4788 allocated "buf" with at least "size" bytes. */
4791 assemble_nop (int size
, char *buf
)
4793 static xtensa_insnbuf insnbuf
= NULL
;
4796 build_nop (&tinsn
, size
);
4799 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4801 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4802 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4803 (unsigned char *) buf
, 0);
4807 /* Return the number of bytes for the offset of the expanded loop
4808 instruction. This should be incorporated into the relaxation
4809 specification but is hard-coded here. This is used to auto-align
4810 the loop instruction. It is invalid to call this function if the
4811 configuration does not have loops or if the opcode is not a loop
4815 get_expanded_loop_offset (xtensa_opcode opcode
)
4817 /* This is the OFFSET of the loop instruction in the expanded loop.
4818 This MUST correspond directly to the specification of the loop
4819 expansion. It will be validated on fragment conversion. */
4820 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4821 if (opcode
== xtensa_loop_opcode
)
4823 if (opcode
== xtensa_loopnez_opcode
)
4825 if (opcode
== xtensa_loopgtz_opcode
)
4827 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4833 get_literal_pool_location (segT seg
)
4835 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4840 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4842 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4846 /* Set frag assembly state should be called when a new frag is
4847 opened and after a frag has been closed. */
4850 xtensa_set_frag_assembly_state (fragS
*fragP
)
4852 if (!density_supported
)
4853 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4855 /* This function is called from subsegs_finish, which is called
4856 after xtensa_end, so we can't use "use_transform" or
4857 "use_schedule" here. */
4858 if (!directive_state
[directive_transform
])
4859 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4860 if (directive_state
[directive_longcalls
])
4861 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4862 fragP
->tc_frag_data
.use_absolute_literals
=
4863 directive_state
[directive_absolute_literals
];
4864 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4869 relaxable_section (asection
*sec
)
4871 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4872 && strcmp (sec
->name
, ".eh_frame") != 0);
4877 xtensa_mark_frags_for_org (void)
4881 /* Walk over each fragment of all of the current segments. If we find
4882 a .org frag in any of the segments, mark all frags prior to it as
4883 "no transform", which will prevent linker optimizations from messing
4884 up the .org distance. This should be done after
4885 xtensa_find_unmarked_state_frags, because we don't want to worry here
4886 about that function trashing the data we save here. */
4888 for (seclist
= &stdoutput
->sections
;
4889 seclist
&& *seclist
;
4890 seclist
= &(*seclist
)->next
)
4892 segT sec
= *seclist
;
4893 segment_info_type
*seginfo
;
4896 flags
= bfd_get_section_flags (stdoutput
, sec
);
4897 if (flags
& SEC_DEBUGGING
)
4899 if (!(flags
& SEC_ALLOC
))
4902 seginfo
= seg_info (sec
);
4903 if (seginfo
&& seginfo
->frchainP
)
4905 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4906 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4907 fragP
= fragP
->fr_next
)
4909 /* cvt_frag_to_fill has changed the fr_type of org frags to
4910 rs_fill, so use the value as cached in rs_subtype here. */
4911 if (fragP
->fr_subtype
== RELAX_ORG
)
4913 while (last_fragP
!= fragP
->fr_next
)
4915 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4916 last_fragP
= last_fragP
->fr_next
;
4926 xtensa_find_unmarked_state_frags (void)
4930 /* Walk over each fragment of all of the current segments. For each
4931 unmarked fragment, mark it with the same info as the previous
4933 for (seclist
= &stdoutput
->sections
;
4934 seclist
&& *seclist
;
4935 seclist
= &(*seclist
)->next
)
4937 segT sec
= *seclist
;
4938 segment_info_type
*seginfo
;
4941 flags
= bfd_get_section_flags (stdoutput
, sec
);
4942 if (flags
& SEC_DEBUGGING
)
4944 if (!(flags
& SEC_ALLOC
))
4947 seginfo
= seg_info (sec
);
4948 if (seginfo
&& seginfo
->frchainP
)
4950 fragS
*last_fragP
= 0;
4951 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4952 fragP
= fragP
->fr_next
)
4954 if (fragP
->fr_fix
!= 0
4955 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4957 if (last_fragP
== 0)
4959 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4960 _("assembly state not set for first frag in section %s"),
4965 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4966 fragP
->tc_frag_data
.is_no_density
=
4967 last_fragP
->tc_frag_data
.is_no_density
;
4968 fragP
->tc_frag_data
.is_no_transform
=
4969 last_fragP
->tc_frag_data
.is_no_transform
;
4970 fragP
->tc_frag_data
.use_longcalls
=
4971 last_fragP
->tc_frag_data
.use_longcalls
;
4972 fragP
->tc_frag_data
.use_absolute_literals
=
4973 last_fragP
->tc_frag_data
.use_absolute_literals
;
4976 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4985 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4987 void *unused ATTRIBUTE_UNUSED
)
4989 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4990 segment_info_type
*seginfo
= seg_info (sec
);
4991 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4993 if (flags
& SEC_CODE
)
4995 xtensa_isa isa
= xtensa_default_isa
;
4996 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4997 while (frag
!= NULL
)
4999 if (frag
->tc_frag_data
.is_branch_target
)
5002 addressT branch_align
, frag_addr
;
5005 xtensa_insnbuf_from_chars
5006 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5007 fmt
= xtensa_format_decode (isa
, insnbuf
);
5008 op_size
= xtensa_format_length (isa
, fmt
);
5009 branch_align
= 1 << branch_align_power (sec
);
5010 frag_addr
= frag
->fr_address
% branch_align
;
5011 if (frag_addr
+ op_size
> branch_align
)
5012 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5013 _("unaligned branch target: %d bytes at 0x%lx"),
5014 op_size
, (long) frag
->fr_address
);
5016 frag
= frag
->fr_next
;
5018 xtensa_insnbuf_free (isa
, insnbuf
);
5024 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5026 void *unused ATTRIBUTE_UNUSED
)
5028 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5029 segment_info_type
*seginfo
= seg_info (sec
);
5030 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5031 xtensa_isa isa
= xtensa_default_isa
;
5033 if (flags
& SEC_CODE
)
5035 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5036 while (frag
!= NULL
)
5038 if (frag
->tc_frag_data
.is_first_loop_insn
)
5044 if (frag
->fr_fix
== 0)
5045 frag
= next_non_empty_frag (frag
);
5049 xtensa_insnbuf_from_chars
5050 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5051 fmt
= xtensa_format_decode (isa
, insnbuf
);
5052 op_size
= xtensa_format_length (isa
, fmt
);
5053 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5055 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5056 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5057 _("unaligned loop: %d bytes at 0x%lx"),
5058 op_size
, (long) frag
->fr_address
);
5061 frag
= frag
->fr_next
;
5063 xtensa_insnbuf_free (isa
, insnbuf
);
5069 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5071 xtensa_isa isa
= xtensa_default_isa
;
5072 static xtensa_insnbuf insnbuf
= NULL
;
5073 static xtensa_insnbuf slotbuf
= NULL
;
5076 bfd_boolean alt_reloc
;
5077 xtensa_opcode opcode
;
5078 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5080 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5082 as_fatal (_("unexpected fix"));
5086 insnbuf
= xtensa_insnbuf_alloc (isa
);
5087 slotbuf
= xtensa_insnbuf_alloc (isa
);
5090 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5091 fmt
= xtensa_format_decode (isa
, insnbuf
);
5092 if (fmt
== XTENSA_UNDEFINED
)
5093 as_fatal (_("undecodable fix"));
5094 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5095 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5096 if (opcode
== XTENSA_UNDEFINED
)
5097 as_fatal (_("undecodable fix"));
5099 /* CONST16 immediates are not PC-relative, despite the fact that we
5100 reuse the normal PC-relative operand relocations for the low part
5101 of a CONST16 operand. */
5102 if (opcode
== xtensa_const16_opcode
)
5105 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5106 get_relaxable_immed (opcode
), val
,
5107 fixP
->fx_file
, fixP
->fx_line
);
5109 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5110 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5116 /* External Functions and Other GAS Hooks. */
5119 xtensa_target_format (void)
5121 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5126 xtensa_file_arch_init (bfd
*abfd
)
5128 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5133 md_number_to_chars (char *buf
, valueT val
, int n
)
5135 if (target_big_endian
)
5136 number_to_chars_bigendian (buf
, val
, n
);
5138 number_to_chars_littleendian (buf
, val
, n
);
5142 /* This function is called once, at assembler startup time. It should
5143 set up all the tables, etc. that the MD part of the assembler will
5149 segT current_section
= now_seg
;
5150 int current_subsec
= now_subseg
;
5154 xtensa_default_isa
= xtensa_isa_init (0, 0);
5155 isa
= xtensa_default_isa
;
5159 /* Set up the literal sections. */
5160 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5162 subseg_set (current_section
, current_subsec
);
5164 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5165 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5166 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5167 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5168 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5169 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5170 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5171 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5172 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5173 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5174 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5175 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5176 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5177 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5178 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5179 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5180 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5181 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5182 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5183 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5184 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5185 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5186 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5187 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5188 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5189 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5190 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5191 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5192 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5193 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5194 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5196 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5198 int format_slots
= xtensa_format_num_slots (isa
, i
);
5199 if (format_slots
> config_max_slots
)
5200 config_max_slots
= format_slots
;
5203 xg_init_vinsn (&cur_vinsn
);
5205 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5207 init_op_placement_info_table ();
5209 /* Set up the assembly state. */
5210 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5211 xtensa_set_frag_assembly_state (frag_now
);
5215 /* TC_INIT_FIX_DATA hook */
5218 xtensa_init_fix_data (fixS
*x
)
5220 x
->tc_fix_data
.slot
= 0;
5221 x
->tc_fix_data
.X_add_symbol
= NULL
;
5222 x
->tc_fix_data
.X_add_number
= 0;
5226 /* tc_frob_label hook */
5229 xtensa_frob_label (symbolS
*sym
)
5233 if (cur_vinsn
.inside_bundle
)
5235 as_bad (_("labels are not valid inside bundles"));
5239 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5241 /* Since the label was already attached to a frag associated with the
5242 previous basic block, it now needs to be reset to the current frag. */
5243 symbol_set_frag (sym
, frag_now
);
5244 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5246 if (generating_literals
)
5247 xtensa_add_literal_sym (sym
);
5249 xtensa_add_insn_label (sym
);
5251 if (symbol_get_tc (sym
)->is_loop_target
)
5253 if ((get_last_insn_flags (now_seg
, now_subseg
)
5254 & FLAG_IS_BAD_LOOPEND
) != 0)
5255 as_bad (_("invalid last instruction for a zero-overhead loop"));
5257 xtensa_set_frag_assembly_state (frag_now
);
5258 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5259 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5261 xtensa_set_frag_assembly_state (frag_now
);
5262 xtensa_move_labels (frag_now
, 0);
5265 /* No target aligning in the absolute section. */
5266 if (now_seg
!= absolute_section
5267 && !is_unaligned_label (sym
)
5268 && !generating_literals
)
5270 xtensa_set_frag_assembly_state (frag_now
);
5272 if (do_align_targets ())
5273 frag_var (rs_machine_dependent
, 0, (int) freq
,
5274 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5275 frag_now
->fr_offset
, NULL
);
5277 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5278 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5279 xtensa_set_frag_assembly_state (frag_now
);
5280 xtensa_move_labels (frag_now
, 0);
5283 /* We need to mark the following properties even if we aren't aligning. */
5285 /* If the label is already known to be a branch target, i.e., a
5286 forward branch, mark the frag accordingly. Backward branches
5287 are handled by xg_add_branch_and_loop_targets. */
5288 if (symbol_get_tc (sym
)->is_branch_target
)
5289 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5291 /* Loops only go forward, so they can be identified here. */
5292 if (symbol_get_tc (sym
)->is_loop_target
)
5293 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5295 dwarf2_emit_label (sym
);
5299 /* tc_unrecognized_line hook */
5302 xtensa_unrecognized_line (int ch
)
5307 if (cur_vinsn
.inside_bundle
== 0)
5309 /* PR8110: Cannot emit line number info inside a FLIX bundle
5310 when using --gstabs. Temporarily disable debug info. */
5311 generate_lineno_debug ();
5312 if (debug_type
== DEBUG_STABS
)
5314 xt_saved_debug_type
= debug_type
;
5315 debug_type
= DEBUG_NONE
;
5318 cur_vinsn
.inside_bundle
= 1;
5322 as_bad (_("extra opening brace"));
5328 if (cur_vinsn
.inside_bundle
)
5329 finish_vinsn (&cur_vinsn
);
5332 as_bad (_("extra closing brace"));
5337 as_bad (_("syntax error"));
5344 /* md_flush_pending_output hook */
5347 xtensa_flush_pending_output (void)
5349 /* This line fixes a bug where automatically generated gstabs info
5350 separates a function label from its entry instruction, ending up
5351 with the literal position between the function label and the entry
5352 instruction and crashing code. It only happens with --gstabs and
5353 --text-section-literals, and when several other obscure relaxation
5354 conditions are met. */
5355 if (outputting_stabs_line_debug
)
5358 if (cur_vinsn
.inside_bundle
)
5359 as_bad (_("missing closing brace"));
5361 /* If there is a non-zero instruction fragment, close it. */
5362 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5364 frag_wane (frag_now
);
5366 xtensa_set_frag_assembly_state (frag_now
);
5368 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5370 xtensa_clear_insn_labels ();
5374 /* We had an error while parsing an instruction. The string might look
5375 like this: "insn arg1, arg2 }". If so, we need to see the closing
5376 brace and reset some fields. Otherwise, the vinsn never gets closed
5377 and the num_slots field will grow past the end of the array of slots,
5378 and bad things happen. */
5381 error_reset_cur_vinsn (void)
5383 if (cur_vinsn
.inside_bundle
)
5385 if (*input_line_pointer
== '}'
5386 || *(input_line_pointer
- 1) == '}'
5387 || *(input_line_pointer
- 2) == '}')
5388 xg_clear_vinsn (&cur_vinsn
);
5394 md_assemble (char *str
)
5396 xtensa_isa isa
= xtensa_default_isa
;
5399 bfd_boolean has_underbar
= FALSE
;
5400 char *arg_strings
[MAX_INSN_ARGS
];
5402 TInsn orig_insn
; /* Original instruction from the input. */
5404 tinsn_init (&orig_insn
);
5406 /* Split off the opcode. */
5407 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5408 opname
= xmalloc (opnamelen
+ 1);
5409 memcpy (opname
, str
, opnamelen
);
5410 opname
[opnamelen
] = '\0';
5412 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5415 as_bad (_("syntax error"));
5419 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5422 /* Check for an underbar prefix. */
5425 has_underbar
= TRUE
;
5429 orig_insn
.insn_type
= ITYPE_INSN
;
5431 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5432 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5434 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5435 extra argument and set the opcode to "CALLXn". */
5436 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5437 && strncasecmp (opname
, "callx", 5) == 0)
5439 unsigned long window_size
;
5442 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5443 if (suffix
!= opname
+ 5
5444 && (window_size
== 0
5447 || window_size
== 12)
5448 && strcasecmp (suffix
, ".tls") == 0)
5450 switch (window_size
)
5452 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5453 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5454 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5455 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5459 as_bad (_("wrong number of operands for '%s'"), opname
);
5462 bfd_reloc_code_real_type reloc
;
5463 char *old_input_line_pointer
;
5464 expressionS
*tok
= &orig_insn
.extra_arg
;
5466 old_input_line_pointer
= input_line_pointer
;
5467 input_line_pointer
= arg_strings
[num_args
- 1];
5470 if (tok
->X_op
== O_symbol
5471 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5472 == BFD_RELOC_XTENSA_TLS_CALL
))
5473 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5475 as_bad (_("bad relocation expression for '%s'"), opname
);
5477 input_line_pointer
= old_input_line_pointer
;
5483 /* Special case: Check for "j.l" psuedo op. */
5484 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5485 && strncasecmp (opname
, "j.l", 3) == 0)
5488 as_bad (_("wrong number of operands for '%s'"), opname
);
5491 char *old_input_line_pointer
;
5492 expressionS
*tok
= &orig_insn
.extra_arg
;
5494 old_input_line_pointer
= input_line_pointer
;
5495 input_line_pointer
= arg_strings
[num_args
- 1];
5497 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5498 input_line_pointer
= old_input_line_pointer
;
5501 orig_insn
.opcode
= xtensa_j_opcode
;
5505 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5507 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5508 if (fmt
== XTENSA_UNDEFINED
)
5510 as_bad (_("unknown opcode or format name '%s'"), opname
);
5511 error_reset_cur_vinsn ();
5514 if (!cur_vinsn
.inside_bundle
)
5516 as_bad (_("format names only valid inside bundles"));
5517 error_reset_cur_vinsn ();
5520 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5521 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5523 cur_vinsn
.format
= fmt
;
5524 free (has_underbar
? opname
- 1 : opname
);
5525 error_reset_cur_vinsn ();
5529 /* Parse the arguments. */
5530 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5532 as_bad (_("syntax error"));
5533 error_reset_cur_vinsn ();
5537 /* Free the opcode and argument strings, now that they've been parsed. */
5538 free (has_underbar
? opname
- 1 : opname
);
5540 while (num_args
-- > 0)
5541 free (arg_strings
[num_args
]);
5543 /* Get expressions for invisible operands. */
5544 if (get_invisible_operands (&orig_insn
))
5546 error_reset_cur_vinsn ();
5550 /* Check for the right number and type of arguments. */
5551 if (tinsn_check_arguments (&orig_insn
))
5553 error_reset_cur_vinsn ();
5557 /* Record the line number for each TInsn, because a FLIX bundle may be
5558 spread across multiple input lines and individual instructions may be
5559 moved around in some cases. */
5560 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5561 dwarf2_where (&orig_insn
.debug_line
);
5562 dwarf2_consume_line_info ();
5564 xg_add_branch_and_loop_targets (&orig_insn
);
5566 /* Check that immediate value for ENTRY is >= 16. */
5567 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5569 expressionS
*exp
= &orig_insn
.tok
[2];
5570 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5571 as_warn (_("entry instruction with stack decrement < 16"));
5575 assemble_tokens (opcode, tok, ntok);
5576 expand the tokens from the orig_insn into the
5577 stack of instructions that will not expand
5578 unless required at relaxation time. */
5580 if (!cur_vinsn
.inside_bundle
)
5581 emit_single_op (&orig_insn
);
5582 else /* We are inside a bundle. */
5584 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5585 cur_vinsn
.num_slots
++;
5586 if (*input_line_pointer
== '}'
5587 || *(input_line_pointer
- 1) == '}'
5588 || *(input_line_pointer
- 2) == '}')
5589 finish_vinsn (&cur_vinsn
);
5592 /* We've just emitted a new instruction so clear the list of labels. */
5593 xtensa_clear_insn_labels ();
5595 xtensa_check_frag_count ();
5599 /* HANDLE_ALIGN hook */
5601 /* For a .align directive, we mark the previous block with the alignment
5602 information. This will be placed in the object file in the
5603 property section corresponding to this section. */
5606 xtensa_handle_align (fragS
*fragP
)
5609 && ! fragP
->tc_frag_data
.is_literal
5610 && (fragP
->fr_type
== rs_align
5611 || fragP
->fr_type
== rs_align_code
)
5612 && fragP
->fr_offset
> 0
5613 && now_seg
!= bss_section
)
5615 fragP
->tc_frag_data
.is_align
= TRUE
;
5616 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5619 if (fragP
->fr_type
== rs_align_test
)
5622 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5624 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5625 _("unaligned entry instruction"));
5628 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5629 fragP
->fr_subtype
= RELAX_ORG
;
5633 /* TC_FRAG_INIT hook */
5636 xtensa_frag_init (fragS
*frag
)
5638 xtensa_set_frag_assembly_state (frag
);
5643 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5649 /* Round up a section size to the appropriate boundary. */
5652 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5654 return size
; /* Byte alignment is fine. */
5659 md_pcrel_from (fixS
*fixP
)
5662 static xtensa_insnbuf insnbuf
= NULL
;
5663 static xtensa_insnbuf slotbuf
= NULL
;
5666 xtensa_opcode opcode
;
5669 xtensa_isa isa
= xtensa_default_isa
;
5670 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5671 bfd_boolean alt_reloc
;
5673 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5676 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5681 insnbuf
= xtensa_insnbuf_alloc (isa
);
5682 slotbuf
= xtensa_insnbuf_alloc (isa
);
5685 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5686 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5687 fmt
= xtensa_format_decode (isa
, insnbuf
);
5689 if (fmt
== XTENSA_UNDEFINED
)
5690 as_fatal (_("bad instruction format"));
5692 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5693 as_fatal (_("invalid relocation"));
5695 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5696 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5698 /* Check for "alternate" relocations (operand not specified). None
5699 of the current uses for these are really PC-relative. */
5700 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5702 if (opcode
!= xtensa_l32r_opcode
5703 && opcode
!= xtensa_const16_opcode
)
5704 as_fatal (_("invalid relocation for '%s' instruction"),
5705 xtensa_opcode_name (isa
, opcode
));
5709 opnum
= get_relaxable_immed (opcode
);
5711 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5712 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5714 as_bad_where (fixP
->fx_file
,
5716 _("invalid relocation for operand %d of '%s'"),
5717 opnum
, xtensa_opcode_name (isa
, opcode
));
5720 return 0 - opnd_value
;
5724 /* TC_FORCE_RELOCATION hook */
5727 xtensa_force_relocation (fixS
*fix
)
5729 switch (fix
->fx_r_type
)
5731 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5732 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5733 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5734 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5735 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5736 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5737 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5738 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5739 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5740 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5741 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5742 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5743 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5744 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5745 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5746 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5752 if (linkrelax
&& fix
->fx_addsy
5753 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5756 return generic_force_reloc (fix
);
5760 /* TC_VALIDATE_FIX_SUB hook */
5763 xtensa_validate_fix_sub (fixS
*fix
)
5765 segT add_symbol_segment
, sub_symbol_segment
;
5767 /* The difference of two symbols should be resolved by the assembler when
5768 linkrelax is not set. If the linker may relax the section containing
5769 the symbols, then an Xtensa DIFF relocation must be generated so that
5770 the linker knows to adjust the difference value. */
5771 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5774 /* Make sure both symbols are in the same segment, and that segment is
5775 "normal" and relaxable. If the segment is not "normal", then the
5776 fix is not valid. If the segment is not "relaxable", then the fix
5777 should have been handled earlier. */
5778 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5779 if (! SEG_NORMAL (add_symbol_segment
) ||
5780 ! relaxable_section (add_symbol_segment
))
5782 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5783 return (sub_symbol_segment
== add_symbol_segment
);
5787 /* NO_PSEUDO_DOT hook */
5789 /* This function has nothing to do with pseudo dots, but this is the
5790 nearest macro to where the check needs to take place. FIXME: This
5794 xtensa_check_inside_bundle (void)
5796 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5797 as_bad (_("directives are not valid inside bundles"));
5799 /* This function must always return FALSE because it is called via a
5800 macro that has nothing to do with bundling. */
5805 /* md_elf_section_change_hook */
5808 xtensa_elf_section_change_hook (void)
5810 /* Set up the assembly state. */
5811 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5812 xtensa_set_frag_assembly_state (frag_now
);
5816 /* tc_fix_adjustable hook */
5819 xtensa_fix_adjustable (fixS
*fixP
)
5821 /* We need the symbol name for the VTABLE entries. */
5822 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5823 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5830 /* tc_symbol_new_hook */
5832 symbolS
*expr_symbols
= NULL
;
5835 xtensa_symbol_new_hook (symbolS
*sym
)
5837 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5839 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5846 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5848 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5851 /* Subtracted symbols are only allowed for a few relocation types, and
5852 unless linkrelax is enabled, they should not make it to this point. */
5853 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5854 || fixP
->fx_r_type
== BFD_RELOC_16
5855 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5858 switch (fixP
->fx_r_type
)
5860 case BFD_RELOC_32_PCREL
:
5866 switch (fixP
->fx_r_type
)
5869 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5870 fixP
->fx_signed
= 1;
5873 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5874 fixP
->fx_signed
= 1;
5877 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5878 fixP
->fx_signed
= 1;
5884 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5885 - S_GET_VALUE (fixP
->fx_subsy
));
5887 /* The difference value gets written out, and the DIFF reloc
5888 identifies the address of the subtracted symbol (i.e., the one
5889 with the lowest address). */
5891 fixP
->fx_offset
-= val
;
5892 fixP
->fx_subsy
= NULL
;
5894 else if (! fixP
->fx_addsy
)
5901 case BFD_RELOC_XTENSA_PLT
:
5902 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5903 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5906 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5907 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5908 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5909 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5910 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5911 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5912 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5915 case BFD_RELOC_XTENSA_SLOT0_OP
:
5916 case BFD_RELOC_XTENSA_SLOT1_OP
:
5917 case BFD_RELOC_XTENSA_SLOT2_OP
:
5918 case BFD_RELOC_XTENSA_SLOT3_OP
:
5919 case BFD_RELOC_XTENSA_SLOT4_OP
:
5920 case BFD_RELOC_XTENSA_SLOT5_OP
:
5921 case BFD_RELOC_XTENSA_SLOT6_OP
:
5922 case BFD_RELOC_XTENSA_SLOT7_OP
:
5923 case BFD_RELOC_XTENSA_SLOT8_OP
:
5924 case BFD_RELOC_XTENSA_SLOT9_OP
:
5925 case BFD_RELOC_XTENSA_SLOT10_OP
:
5926 case BFD_RELOC_XTENSA_SLOT11_OP
:
5927 case BFD_RELOC_XTENSA_SLOT12_OP
:
5928 case BFD_RELOC_XTENSA_SLOT13_OP
:
5929 case BFD_RELOC_XTENSA_SLOT14_OP
:
5932 /* Write the tentative value of a PC-relative relocation to a
5933 local symbol into the instruction. The value will be ignored
5934 by the linker, and it makes the object file disassembly
5935 readable when all branch targets are encoded in relocations. */
5937 gas_assert (fixP
->fx_addsy
);
5938 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5939 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5941 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5942 - md_pcrel_from (fixP
));
5943 (void) xg_apply_fix_value (fixP
, val
);
5946 else if (! fixP
->fx_addsy
)
5949 if (xg_apply_fix_value (fixP
, val
))
5954 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5955 case BFD_RELOC_XTENSA_TLS_FUNC
:
5956 case BFD_RELOC_XTENSA_TLS_ARG
:
5957 case BFD_RELOC_XTENSA_TLS_CALL
:
5958 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5959 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5960 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5961 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5962 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5963 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5964 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5965 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5966 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5967 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5968 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5969 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5970 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5971 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5972 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5973 /* These all need to be resolved at link-time. Do nothing now. */
5976 case BFD_RELOC_VTABLE_INHERIT
:
5977 case BFD_RELOC_VTABLE_ENTRY
:
5982 as_bad (_("unhandled local relocation fix %s"),
5983 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5989 md_atof (int type
, char *litP
, int *sizeP
)
5991 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5996 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5998 return total_frag_text_expansion (fragP
);
6002 /* Translate internal representation of relocation info to BFD target
6006 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6010 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
6011 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6012 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6013 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6015 /* Make sure none of our internal relocations make it this far.
6016 They'd better have been fully resolved by this point. */
6017 gas_assert ((int) fixp
->fx_r_type
> 0);
6019 reloc
->addend
= fixp
->fx_offset
;
6021 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6022 if (reloc
->howto
== NULL
)
6024 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6025 _("cannot represent `%s' relocation in object file"),
6026 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6027 free (reloc
->sym_ptr_ptr
);
6032 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6033 as_fatal (_("internal error; cannot generate `%s' relocation"),
6034 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6040 /* Checks for resource conflicts between instructions. */
6042 /* The func unit stuff could be implemented as bit-vectors rather
6043 than the iterative approach here. If it ends up being too
6044 slow, we will switch it. */
6047 new_resource_table (void *data
,
6050 unit_num_copies_func uncf
,
6051 opcode_num_units_func onuf
,
6052 opcode_funcUnit_use_unit_func ouuf
,
6053 opcode_funcUnit_use_stage_func ousf
)
6056 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
6058 rt
->cycles
= cycles
;
6059 rt
->allocated_cycles
= cycles
;
6061 rt
->unit_num_copies
= uncf
;
6062 rt
->opcode_num_units
= onuf
;
6063 rt
->opcode_unit_use
= ouuf
;
6064 rt
->opcode_unit_stage
= ousf
;
6066 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6067 for (i
= 0; i
< cycles
; i
++)
6068 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6075 clear_resource_table (resource_table
*rt
)
6078 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6079 for (j
= 0; j
< rt
->num_units
; j
++)
6080 rt
->units
[i
][j
] = 0;
6084 /* We never shrink it, just fake it into thinking so. */
6087 resize_resource_table (resource_table
*rt
, int cycles
)
6091 rt
->cycles
= cycles
;
6092 if (cycles
<= rt
->allocated_cycles
)
6095 old_cycles
= rt
->allocated_cycles
;
6096 rt
->allocated_cycles
= cycles
;
6098 rt
->units
= xrealloc (rt
->units
,
6099 rt
->allocated_cycles
* sizeof (unsigned char *));
6100 for (i
= 0; i
< old_cycles
; i
++)
6101 rt
->units
[i
] = xrealloc (rt
->units
[i
],
6102 rt
->num_units
* sizeof (unsigned char));
6103 for (i
= old_cycles
; i
< cycles
; i
++)
6104 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6109 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6112 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6114 for (i
= 0; i
< uses
; i
++)
6116 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6117 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6118 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6119 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6120 if (copies_in_use
>= copies
)
6128 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6131 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6133 for (i
= 0; i
< uses
; i
++)
6135 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6136 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6137 /* Note that this allows resources to be oversubscribed. That's
6138 essential to the way the optional scheduler works.
6139 resources_available reports when a resource is over-subscribed,
6140 so it's easy to tell. */
6141 rt
->units
[stage
+ cycle
][unit
]++;
6147 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6150 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6152 for (i
= 0; i
< uses
; i
++)
6154 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6155 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6156 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6157 rt
->units
[stage
+ cycle
][unit
]--;
6162 /* Wrapper functions make parameterized resource reservation
6166 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6168 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6174 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6176 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6181 /* Note that this function does not check issue constraints, but
6182 solely whether the hardware is available to execute the given
6183 instructions together. It also doesn't check if the tinsns
6184 write the same state, or access the same tieports. That is
6185 checked by check_t1_t2_reads_and_writes. */
6188 resources_conflict (vliw_insn
*vinsn
)
6191 static resource_table
*rt
= NULL
;
6193 /* This is the most common case by far. Optimize it. */
6194 if (vinsn
->num_slots
== 1)
6199 xtensa_isa isa
= xtensa_default_isa
;
6200 rt
= new_resource_table
6201 (isa
, xtensa_num_pipe_stages
,
6202 xtensa_isa_num_funcUnits (isa
),
6203 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6204 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6205 opcode_funcUnit_use_unit
,
6206 opcode_funcUnit_use_stage
);
6209 clear_resource_table (rt
);
6211 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6213 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6215 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6222 /* finish_vinsn, emit_single_op and helper functions. */
6224 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6225 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6226 static void xg_assemble_vliw_tokens (vliw_insn
*);
6229 /* We have reached the end of a bundle; emit into the frag. */
6232 finish_vinsn (vliw_insn
*vinsn
)
6239 if (find_vinsn_conflicts (vinsn
))
6241 xg_clear_vinsn (vinsn
);
6245 /* First, find a format that works. */
6246 if (vinsn
->format
== XTENSA_UNDEFINED
)
6247 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6249 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6250 && produce_flix
== FLIX_NONE
)
6252 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6253 xg_clear_vinsn (vinsn
);
6257 if (vinsn
->format
== XTENSA_UNDEFINED
)
6259 as_where (&file_name
, &line
);
6260 as_bad_where (file_name
, line
,
6261 _("couldn't find a valid instruction format"));
6262 fprintf (stderr
, _(" ops were: "));
6263 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6264 fprintf (stderr
, _(" %s;"),
6265 xtensa_opcode_name (xtensa_default_isa
,
6266 vinsn
->slots
[i
].opcode
));
6267 fprintf (stderr
, _("\n"));
6268 xg_clear_vinsn (vinsn
);
6272 if (vinsn
->num_slots
6273 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6275 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6276 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6277 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6279 xg_clear_vinsn (vinsn
);
6283 if (resources_conflict (vinsn
))
6285 as_where (&file_name
, &line
);
6286 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6287 fprintf (stderr
, " ops were: ");
6288 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6289 fprintf (stderr
, " %s;",
6290 xtensa_opcode_name (xtensa_default_isa
,
6291 vinsn
->slots
[i
].opcode
));
6292 fprintf (stderr
, "\n");
6293 xg_clear_vinsn (vinsn
);
6297 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6299 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6301 symbolS
*lit_sym
= NULL
;
6303 bfd_boolean e
= FALSE
;
6304 bfd_boolean saved_density
= density_supported
;
6306 /* We don't want to narrow ops inside multi-slot bundles. */
6307 if (vinsn
->num_slots
> 1)
6308 density_supported
= FALSE
;
6310 istack_init (&slotstack
);
6311 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6313 vinsn
->slots
[i
].opcode
=
6314 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6316 vinsn
->slots
[i
].ntok
= 0;
6319 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6325 density_supported
= saved_density
;
6329 xg_clear_vinsn (vinsn
);
6333 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6335 TInsn
*insn
= &slotstack
.insn
[j
];
6336 if (insn
->insn_type
== ITYPE_LITERAL
)
6338 gas_assert (lit_sym
== NULL
);
6339 lit_sym
= xg_assemble_literal (insn
);
6343 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6345 xg_resolve_literals (insn
, lit_sym
);
6346 if (j
!= slotstack
.ninsn
- 1)
6347 emit_single_op (insn
);
6351 if (vinsn
->num_slots
> 1)
6353 if (opcode_fits_format_slot
6354 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6357 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6361 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6362 if (vinsn
->format
== XTENSA_UNDEFINED
)
6363 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6365 vinsn
->slots
[i
].opcode
6366 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6369 vinsn
->slots
[i
].ntok
= 0;
6374 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6375 vinsn
->format
= XTENSA_UNDEFINED
;
6380 /* Now check resource conflicts on the modified bundle. */
6381 if (resources_conflict (vinsn
))
6383 as_where (&file_name
, &line
);
6384 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6385 fprintf (stderr
, " ops were: ");
6386 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6387 fprintf (stderr
, " %s;",
6388 xtensa_opcode_name (xtensa_default_isa
,
6389 vinsn
->slots
[i
].opcode
));
6390 fprintf (stderr
, "\n");
6391 xg_clear_vinsn (vinsn
);
6395 /* First, find a format that works. */
6396 if (vinsn
->format
== XTENSA_UNDEFINED
)
6397 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6399 xg_assemble_vliw_tokens (vinsn
);
6401 xg_clear_vinsn (vinsn
);
6403 xtensa_check_frag_count ();
6407 /* Given an vliw instruction, what conflicts are there in register
6408 usage and in writes to states and queues?
6410 This function does two things:
6411 1. Reports an error when a vinsn contains illegal combinations
6412 of writes to registers states or queues.
6413 2. Marks individual tinsns as not relaxable if the combination
6414 contains antidependencies.
6416 Job 2 handles things like swap semantics in instructions that need
6417 to be relaxed. For example,
6421 normally would be relaxed to
6426 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6428 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6430 then we can't relax it into
6433 { add a0, a1, a0 ; add a2, a0, a4 ; }
6435 because the value of a0 is trashed before the second add can read it. */
6437 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6440 find_vinsn_conflicts (vliw_insn
*vinsn
)
6444 xtensa_isa isa
= xtensa_default_isa
;
6446 gas_assert (!past_xtensa_end
);
6448 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6450 TInsn
*op1
= &vinsn
->slots
[i
];
6451 if (op1
->is_specific_opcode
)
6452 op1
->keep_wide
= TRUE
;
6454 op1
->keep_wide
= FALSE
;
6457 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6459 TInsn
*op1
= &vinsn
->slots
[i
];
6461 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6464 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6468 TInsn
*op2
= &vinsn
->slots
[j
];
6469 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6470 switch (conflict_type
)
6473 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6474 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6475 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6478 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6479 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6480 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6483 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6484 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6485 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6488 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6489 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6490 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6493 /* Everything is OK. */
6496 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6497 || conflict_type
== 'a');
6504 as_bad (_("multiple branches or jumps in the same bundle"));
6512 /* Check how the state used by t1 and t2 relate.
6515 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6516 case B: no relationship between what is read and written (both could
6517 read the same reg though)
6518 case C: t1 writes a register t2 writes (a register conflict within a
6520 case D: t1 writes a state that t2 also writes
6521 case E: t1 writes a tie queue that t2 also writes
6522 case F: two volatile queue accesses
6526 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6528 xtensa_isa isa
= xtensa_default_isa
;
6529 xtensa_regfile t1_regfile
, t2_regfile
;
6531 int t1_base_reg
, t1_last_reg
;
6532 int t2_base_reg
, t2_last_reg
;
6533 char t1_inout
, t2_inout
;
6535 char conflict
= 'b';
6540 bfd_boolean t1_volatile
= FALSE
;
6541 bfd_boolean t2_volatile
= FALSE
;
6543 /* Check registers. */
6544 for (j
= 0; j
< t2
->ntok
; j
++)
6546 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6549 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6550 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6551 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6553 for (i
= 0; i
< t1
->ntok
; i
++)
6555 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6558 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6560 if (t1_regfile
!= t2_regfile
)
6563 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6564 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6566 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6567 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6569 if (t1_inout
== 'm' || t1_inout
== 'o'
6570 || t2_inout
== 'm' || t2_inout
== 'o')
6577 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6578 t1_last_reg
= (t1_base_reg
6579 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6581 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6583 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6585 if (t1_reg
!= t2_reg
)
6588 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6594 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6600 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6608 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6609 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6610 for (j
= 0; j
< t2_states
; j
++)
6612 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6613 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6614 for (i
= 0; i
< t1_states
; i
++)
6616 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6617 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6618 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6621 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6627 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6633 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6638 /* Check tieports. */
6639 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6640 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6641 for (j
= 0; j
< t2_interfaces
; j
++)
6643 xtensa_interface t2_int
6644 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6645 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6647 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6648 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6651 for (i
= 0; i
< t1_interfaces
; i
++)
6653 xtensa_interface t1_int
6654 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6655 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6657 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6658 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6661 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6664 if (t1_int
!= t2_int
)
6667 if (t2_inout
== 'i' && t1_inout
== 'o')
6673 if (t1_inout
== 'i' && t2_inout
== 'o')
6679 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6688 static xtensa_format
6689 xg_find_narrowest_format (vliw_insn
*vinsn
)
6691 /* Right now we assume that the ops within the vinsn are properly
6692 ordered for the slots that the programmer wanted them in. In
6693 other words, we don't rearrange the ops in hopes of finding a
6694 better format. The scheduler handles that. */
6696 xtensa_isa isa
= xtensa_default_isa
;
6697 xtensa_format format
;
6698 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6700 if (vinsn
->num_slots
== 1)
6701 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6703 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6706 xg_copy_vinsn (&v_copy
, vinsn
);
6707 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6711 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6713 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6715 v_copy
.slots
[slot
].opcode
=
6716 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6717 v_copy
.slots
[slot
].ntok
= 0;
6720 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6723 else if (v_copy
.num_slots
> 1)
6726 /* Try the widened version. */
6727 if (!v_copy
.slots
[slot
].keep_wide
6728 && !v_copy
.slots
[slot
].is_specific_opcode
6729 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6731 && opcode_fits_format_slot (widened
.opcode
,
6734 v_copy
.slots
[slot
] = widened
;
6739 if (fit
== v_copy
.num_slots
)
6741 xg_copy_vinsn (vinsn
, &v_copy
);
6742 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6743 vinsn
->format
= format
;
6749 if (format
== xtensa_isa_num_formats (isa
))
6750 return XTENSA_UNDEFINED
;
6756 /* Return the additional space needed in a frag
6757 for possible relaxations of any ops in a VLIW insn.
6758 Also fill out the relaxations that might be required of
6759 each tinsn in the vinsn. */
6762 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6764 bfd_boolean finish_frag
= FALSE
;
6765 int extra_space
= 0;
6768 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6770 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6771 if (!tinsn_has_symbolic_operands (tinsn
))
6773 /* A narrow instruction could be widened later to help
6774 alignment issues. */
6775 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6776 && !tinsn
->is_specific_opcode
6777 && vinsn
->num_slots
== 1)
6779 /* Difference in bytes between narrow and wide insns... */
6781 tinsn
->subtype
= RELAX_NARROW
;
6786 if (workaround_b_j_loop_end
6787 && tinsn
->opcode
== xtensa_jx_opcode
6788 && use_transform ())
6790 /* Add 2 of these. */
6791 extra_space
+= 3; /* for the nop size */
6792 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6795 /* Need to assemble it with space for the relocation. */
6796 if (xg_is_relaxable_insn (tinsn
, 0)
6797 && !tinsn
->is_specific_opcode
)
6799 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6800 int max_literal_size
=
6801 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6803 tinsn
->literal_space
= max_literal_size
;
6805 tinsn
->subtype
= RELAX_IMMED
;
6806 extra_space
+= max_size
;
6810 /* A fix record will be added for this instruction prior
6811 to relaxation, so make it end the frag. */
6816 *pfinish_frag
= finish_frag
;
6822 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6824 xtensa_isa isa
= xtensa_default_isa
;
6825 int slot
, chosen_slot
;
6827 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6828 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6829 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6831 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6832 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6834 if (slot
== chosen_slot
)
6835 vinsn
->slots
[slot
] = *tinsn
;
6838 vinsn
->slots
[slot
].opcode
=
6839 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6840 vinsn
->slots
[slot
].ntok
= 0;
6841 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6848 emit_single_op (TInsn
*orig_insn
)
6851 IStack istack
; /* put instructions into here */
6852 symbolS
*lit_sym
= NULL
;
6853 symbolS
*label_sym
= NULL
;
6855 istack_init (&istack
);
6857 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6858 Because the scheduling and bundling characteristics of movi and
6859 l32r or const16 are so different, we can do much better if we relax
6860 it prior to scheduling and bundling, rather than after. */
6861 if ((orig_insn
->opcode
== xtensa_movi_opcode
6862 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6863 && !cur_vinsn
.inside_bundle
6864 && (orig_insn
->tok
[1].X_op
== O_symbol
6865 || orig_insn
->tok
[1].X_op
== O_pltrel
6866 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6867 || orig_insn
->tok
[1].X_op
== O_tlsarg
6868 || orig_insn
->tok
[1].X_op
== O_tpoff
6869 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6870 && !orig_insn
->is_specific_opcode
&& use_transform ())
6871 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6873 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6876 for (i
= 0; i
< istack
.ninsn
; i
++)
6878 TInsn
*insn
= &istack
.insn
[i
];
6879 switch (insn
->insn_type
)
6882 gas_assert (lit_sym
== NULL
);
6883 lit_sym
= xg_assemble_literal (insn
);
6887 static int relaxed_sym_idx
= 0;
6888 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6889 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6891 gas_assert (label_sym
== NULL
);
6892 label_sym
= symbol_find_or_make (label
);
6893 gas_assert (label_sym
);
6901 xg_resolve_literals (insn
, lit_sym
);
6903 xg_resolve_labels (insn
, label_sym
);
6905 bundle_tinsn (insn
, &v
);
6920 total_frag_text_expansion (fragS
*fragP
)
6923 int total_expansion
= 0;
6925 for (slot
= 0; slot
< config_max_slots
; slot
++)
6926 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6928 return total_expansion
;
6932 /* Emit a vliw instruction to the current fragment. */
6935 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6937 bfd_boolean finish_frag
;
6938 bfd_boolean is_jump
= FALSE
;
6939 bfd_boolean is_branch
= FALSE
;
6940 xtensa_isa isa
= xtensa_default_isa
;
6945 struct dwarf2_line_info debug_line
;
6946 bfd_boolean loc_directive_seen
= FALSE
;
6949 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6951 if (generating_literals
)
6953 static int reported
= 0;
6955 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6956 _("cannot assemble into a literal fragment"));
6963 if (frag_now_fix () != 0
6964 && (! frag_now
->tc_frag_data
.is_insn
6965 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6966 || (!use_transform ()) != frag_now
->tc_frag_data
.is_no_transform
6967 || (directive_state
[directive_longcalls
]
6968 != frag_now
->tc_frag_data
.use_longcalls
)
6969 || (directive_state
[directive_absolute_literals
]
6970 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6972 frag_wane (frag_now
);
6974 xtensa_set_frag_assembly_state (frag_now
);
6977 if (workaround_a0_b_retw
6978 && vinsn
->num_slots
== 1
6979 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6980 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6981 && use_transform ())
6983 has_a0_b_retw
= TRUE
;
6985 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6986 After the first assembly pass we will check all of them and
6987 add a nop if needed. */
6988 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6989 frag_var (rs_machine_dependent
, 4, 4,
6990 RELAX_ADD_NOP_IF_A0_B_RETW
,
6991 frag_now
->fr_symbol
,
6992 frag_now
->fr_offset
,
6994 xtensa_set_frag_assembly_state (frag_now
);
6995 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6996 frag_var (rs_machine_dependent
, 4, 4,
6997 RELAX_ADD_NOP_IF_A0_B_RETW
,
6998 frag_now
->fr_symbol
,
6999 frag_now
->fr_offset
,
7001 xtensa_set_frag_assembly_state (frag_now
);
7004 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7006 tinsn
= &vinsn
->slots
[slot
];
7008 /* See if the instruction implies an aligned section. */
7009 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7010 record_alignment (now_seg
, 2);
7012 /* Determine the best line number for debug info. */
7013 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7014 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7015 || tinsn
->debug_line
.line
< debug_line
.line
7016 || tinsn
->debug_line
.column
< debug_line
.column
))
7017 debug_line
= tinsn
->debug_line
;
7018 if (tinsn
->loc_directive_seen
)
7019 loc_directive_seen
= TRUE
;
7022 /* Special cases for instructions that force an alignment... */
7023 /* None of these opcodes are bundle-able. */
7024 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7028 /* Remember the symbol that marks the end of the loop in the frag
7029 that marks the start of the loop. This way we can easily find
7030 the end of the loop at the beginning, without adding special code
7031 to mark the loop instructions themselves. */
7032 symbolS
*target_sym
= NULL
;
7033 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7034 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7036 xtensa_set_frag_assembly_state (frag_now
);
7037 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7039 max_fill
= get_text_align_max_fill_size
7040 (get_text_align_power (xtensa_fetch_width
),
7041 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7043 if (use_transform ())
7044 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7045 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7047 frag_var (rs_machine_dependent
, 0, 0,
7048 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7049 xtensa_set_frag_assembly_state (frag_now
);
7052 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7053 && !vinsn
->slots
[0].is_specific_opcode
)
7055 xtensa_mark_literal_pool_location ();
7056 xtensa_move_labels (frag_now
, 0);
7057 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7060 if (vinsn
->num_slots
== 1)
7062 if (workaround_a0_b_retw
&& use_transform ())
7063 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7064 is_register_writer (&vinsn
->slots
[0], "a", 0));
7066 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7067 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7070 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7072 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7074 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7076 /* vinsn_to_insnbuf will produce the error. */
7077 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7079 f
= frag_more (insn_size
+ extra_space
);
7080 xtensa_set_frag_assembly_state (frag_now
);
7081 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7084 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7085 if (vinsn
->format
== XTENSA_UNDEFINED
)
7088 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7090 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7091 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7094 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7096 tinsn
= &vinsn
->slots
[slot
];
7097 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7098 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7099 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7100 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7101 if (tinsn
->literal_space
!= 0)
7102 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7103 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7105 if (tinsn
->subtype
== RELAX_NARROW
)
7106 gas_assert (vinsn
->num_slots
== 1);
7107 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7109 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7112 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7113 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7117 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7118 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7122 frag_variant (rs_machine_dependent
,
7123 extra_space
, extra_space
, RELAX_SLOTS
,
7124 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7125 xtensa_set_frag_assembly_state (frag_now
);
7128 /* Special cases for loops:
7129 close_loop_end should be inserted AFTER short_loop.
7130 Make sure that CLOSE loops are processed BEFORE short_loops
7131 when converting them. */
7133 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7134 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7135 && !vinsn
->slots
[0].is_specific_opcode
)
7137 if (workaround_short_loop
&& use_transform ())
7139 maybe_has_short_loop
= TRUE
;
7140 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7141 frag_var (rs_machine_dependent
, 4, 4,
7142 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7143 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7144 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7145 frag_var (rs_machine_dependent
, 4, 4,
7146 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7147 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7150 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7151 loop at least 12 bytes away from another loop's end. */
7152 if (workaround_close_loop_end
&& use_transform ())
7154 maybe_has_close_loop_end
= TRUE
;
7155 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7156 frag_var (rs_machine_dependent
, 12, 12,
7157 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7158 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7162 if (use_transform ())
7166 gas_assert (finish_frag
);
7167 frag_var (rs_machine_dependent
,
7168 xtensa_fetch_width
, xtensa_fetch_width
,
7170 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7171 xtensa_set_frag_assembly_state (frag_now
);
7172 xtensa_maybe_create_trampoline_frag ();
7174 else if (is_branch
&& do_align_targets ())
7176 gas_assert (finish_frag
);
7177 frag_var (rs_machine_dependent
,
7178 xtensa_fetch_width
, xtensa_fetch_width
,
7179 RELAX_MAYBE_UNREACHABLE
,
7180 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7181 xtensa_set_frag_assembly_state (frag_now
);
7182 frag_var (rs_machine_dependent
,
7184 RELAX_MAYBE_DESIRE_ALIGN
,
7185 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7186 xtensa_set_frag_assembly_state (frag_now
);
7190 /* Now, if the original opcode was a call... */
7191 if (do_align_targets ()
7192 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7194 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7195 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7196 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7197 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7198 xtensa_set_frag_assembly_state (frag_now
);
7201 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7203 frag_wane (frag_now
);
7205 xtensa_set_frag_assembly_state (frag_now
);
7210 /* xtensa_end and helper functions. */
7212 static void xtensa_cleanup_align_frags (void);
7213 static void xtensa_fix_target_frags (void);
7214 static void xtensa_mark_narrow_branches (void);
7215 static void xtensa_mark_zcl_first_insns (void);
7216 static void xtensa_mark_difference_of_two_symbols (void);
7217 static void xtensa_fix_a0_b_retw_frags (void);
7218 static void xtensa_fix_b_j_loop_end_frags (void);
7219 static void xtensa_fix_close_loop_end_frags (void);
7220 static void xtensa_fix_short_loop_frags (void);
7221 static void xtensa_sanity_check (void);
7222 static void xtensa_add_config_info (void);
7227 directive_balance ();
7228 xtensa_flush_pending_output ();
7230 past_xtensa_end
= TRUE
;
7232 xtensa_move_literals ();
7234 xtensa_reorder_segments ();
7235 xtensa_cleanup_align_frags ();
7236 xtensa_fix_target_frags ();
7237 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7238 xtensa_fix_a0_b_retw_frags ();
7239 if (workaround_b_j_loop_end
)
7240 xtensa_fix_b_j_loop_end_frags ();
7242 /* "close_loop_end" should be processed BEFORE "short_loop". */
7243 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7244 xtensa_fix_close_loop_end_frags ();
7246 if (workaround_short_loop
&& maybe_has_short_loop
)
7247 xtensa_fix_short_loop_frags ();
7249 xtensa_mark_narrow_branches ();
7250 xtensa_mark_zcl_first_insns ();
7252 xtensa_sanity_check ();
7254 xtensa_add_config_info ();
7256 xtensa_check_frag_count ();
7260 struct trampoline_frag
7262 struct trampoline_frag
*next
;
7263 bfd_boolean needs_jump_around
;
7268 struct trampoline_seg
7270 struct trampoline_seg
*next
;
7272 struct trampoline_frag trampoline_list
;
7275 static struct trampoline_seg trampoline_seg_list
;
7276 #define J_RANGE (128 * 1024)
7278 static int unreachable_count
= 0;
7282 xtensa_maybe_create_trampoline_frag (void)
7284 if (!use_trampolines
)
7287 /* We create an area for possible trampolines every 10 unreachable frags.
7288 These are preferred over the ones not preceded by an unreachable frag,
7289 because we don't have to jump around them. This function is called after
7290 each RELAX_UNREACHABLE frag is created. */
7292 if (++unreachable_count
> 10)
7294 xtensa_create_trampoline_frag (FALSE
);
7295 clear_frag_count ();
7296 unreachable_count
= 0;
7301 xtensa_check_frag_count (void)
7303 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7306 /* We create an area for possible trampolines every 8000 frags or so. This
7307 is an estimate based on the max range of a "j" insn (+/-128K) divided
7308 by a typical frag byte count (16), minus a few for safety. This function
7309 is called after each source line is processed. */
7311 if (get_frag_count () > 8000)
7313 xtensa_create_trampoline_frag (TRUE
);
7314 clear_frag_count ();
7315 unreachable_count
= 0;
7319 static xtensa_insnbuf trampoline_buf
= NULL
;
7320 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7322 #define TRAMPOLINE_FRAG_SIZE 3000
7325 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7327 /* Emit a frag where we can place intermediate jump instructions,
7328 in case we need to jump farther than 128K bytes.
7329 Each jump instruction takes three bytes.
7330 We allocate enough for 1000 trampolines in each frag.
7331 If that's not enough, oh well. */
7333 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7334 struct trampoline_frag
*tf
;
7337 int size
= TRAMPOLINE_FRAG_SIZE
;
7339 for ( ; ts
; ts
= ts
->next
)
7341 if (ts
->seg
== now_seg
)
7347 ts
= (struct trampoline_seg
*)xcalloc(sizeof (struct trampoline_seg
), 1);
7348 ts
->next
= trampoline_seg_list
.next
;
7349 trampoline_seg_list
.next
= ts
;
7353 frag_wane (frag_now
);
7355 xtensa_set_frag_assembly_state (frag_now
);
7356 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7357 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7358 if (trampoline_buf
== NULL
)
7360 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7361 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7363 tf
= (struct trampoline_frag
*)xmalloc(sizeof (struct trampoline_frag
));
7364 tf
->next
= ts
->trampoline_list
.next
;
7365 ts
->trampoline_list
.next
= tf
;
7366 tf
->needs_jump_around
= needs_jump_around
;
7372 static struct trampoline_seg
*
7373 find_trampoline_seg (asection
*seg
)
7375 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7377 for ( ; ts
; ts
= ts
->next
)
7387 void dump_trampolines (void);
7390 dump_trampolines (void)
7392 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7394 for ( ; ts
; ts
= ts
->next
)
7396 asection
*seg
= ts
->seg
;
7400 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7401 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
7402 for ( ; tf
; tf
= tf
->next
)
7404 if (tf
->fragP
== NULL
)
7406 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7407 (int)tf
->fragP
->fr_address
, (int)tf
->fragP
->fr_fix
,
7408 tf
->needs_jump_around
? "T" : "F");
7414 xtensa_cleanup_align_frags (void)
7419 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7420 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7423 /* Walk over all of the fragments in a subsection. */
7424 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7426 if ((fragP
->fr_type
== rs_align
7427 || fragP
->fr_type
== rs_align_code
7428 || (fragP
->fr_type
== rs_machine_dependent
7429 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7430 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7431 && fragP
->fr_fix
== 0)
7433 fragS
*next
= fragP
->fr_next
;
7436 && next
->fr_fix
== 0
7437 && next
->fr_type
== rs_machine_dependent
7438 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7441 next
= next
->fr_next
;
7444 /* If we don't widen branch targets, then they
7445 will be easier to align. */
7446 if (fragP
->tc_frag_data
.is_branch_target
7447 && fragP
->fr_opcode
== fragP
->fr_literal
7448 && fragP
->fr_type
== rs_machine_dependent
7449 && fragP
->fr_subtype
== RELAX_SLOTS
7450 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7452 if (fragP
->fr_type
== rs_machine_dependent
7453 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7454 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7460 /* Re-process all of the fragments looking to convert all of the
7461 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7462 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7463 Otherwise, convert to a .fill 0. */
7466 xtensa_fix_target_frags (void)
7471 /* When this routine is called, all of the subsections are still intact
7472 so we walk over subsections instead of sections. */
7473 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7474 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7478 /* Walk over all of the fragments in a subsection. */
7479 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7481 if (fragP
->fr_type
== rs_machine_dependent
7482 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7484 if (next_frag_is_branch_target (fragP
))
7485 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7494 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7497 xtensa_mark_narrow_branches (void)
7502 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7503 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7506 /* Walk over all of the fragments in a subsection. */
7507 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7509 if (fragP
->fr_type
== rs_machine_dependent
7510 && fragP
->fr_subtype
== RELAX_SLOTS
7511 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7515 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7516 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7518 if (vinsn
.num_slots
== 1
7519 && xtensa_opcode_is_branch (xtensa_default_isa
,
7520 vinsn
.slots
[0].opcode
) == 1
7521 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7522 && is_narrow_branch_guaranteed_in_range (fragP
,
7525 fragP
->fr_subtype
= RELAX_SLOTS
;
7526 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7527 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7535 /* A branch is typically widened only when its target is out of
7536 range. However, we would like to widen them to align a subsequent
7537 branch target when possible.
7539 Because the branch relaxation code is so convoluted, the optimal solution
7540 (combining the two cases) is difficult to get right in all circumstances.
7541 We therefore go with an "almost as good" solution, where we only
7542 use for alignment narrow branches that definitely will not expand to a
7543 jump and a branch. These functions find and mark these cases. */
7545 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7546 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7547 We start counting beginning with the frag after the 2-byte branch, so the
7548 maximum offset is (4 - 2) + 63 = 65. */
7549 #define MAX_IMMED6 65
7551 static offsetT
unrelaxed_frag_max_size (fragS
*);
7554 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7556 const expressionS
*exp
= &tinsn
->tok
[1];
7557 symbolS
*symbolP
= exp
->X_add_symbol
;
7558 offsetT max_distance
= exp
->X_add_number
;
7561 if (exp
->X_op
!= O_symbol
)
7564 target_frag
= symbol_get_frag (symbolP
);
7566 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7567 if (is_branch_jmp_to_next (tinsn
, fragP
))
7570 /* The branch doesn't branch over it's own frag,
7571 but over the subsequent ones. */
7572 fragP
= fragP
->fr_next
;
7573 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7575 max_distance
+= unrelaxed_frag_max_size (fragP
);
7576 fragP
= fragP
->fr_next
;
7578 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7585 xtensa_mark_zcl_first_insns (void)
7590 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7591 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7594 /* Walk over all of the fragments in a subsection. */
7595 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7597 if (fragP
->fr_type
== rs_machine_dependent
7598 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7599 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7601 /* Find the loop frag. */
7602 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7603 /* Find the first insn frag. */
7604 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
7606 /* Handle a corner case that comes up in hardware
7607 diagnostics. The original assembly looks like this:
7610 <empty_frag>--not found by next_non_empty_frag
7613 Depending on the start address, the assembler may or
7614 may not change it to look something like this:
7617 nop--frag isn't empty anymore
7620 So set up to check the alignment of the nop if it
7622 while (loop_frag
!= targ_frag
)
7624 if (loop_frag
->fr_type
== rs_machine_dependent
7625 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7626 || loop_frag
->fr_subtype
7627 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7628 targ_frag
= loop_frag
;
7630 loop_frag
= loop_frag
->fr_next
;
7633 /* Of course, sometimes (mostly for toy test cases) a
7634 zero-cost loop instruction is the last in a section. */
7637 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7638 /* Do not widen a frag that is the first instruction of a
7639 zero-cost loop. It makes that loop harder to align. */
7640 if (targ_frag
->fr_type
== rs_machine_dependent
7641 && targ_frag
->fr_subtype
== RELAX_SLOTS
7642 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7645 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7646 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7649 frag_wane (targ_frag
);
7650 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7654 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7662 /* When a difference-of-symbols expression is encoded as a uleb128 or
7663 sleb128 value, the linker is unable to adjust that value to account for
7664 link-time relaxation. Mark all the code between such symbols so that
7665 its size cannot be changed by linker relaxation. */
7668 xtensa_mark_difference_of_two_symbols (void)
7672 for (expr_sym
= expr_symbols
; expr_sym
;
7673 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7675 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7677 if (exp
->X_op
== O_subtract
)
7679 symbolS
*left
= exp
->X_add_symbol
;
7680 symbolS
*right
= exp
->X_op_symbol
;
7682 /* Difference of two symbols not in the same section
7683 are handled with relocations in the linker. */
7684 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7690 if (symbol_get_frag (left
)->fr_address
7691 <= symbol_get_frag (right
)->fr_address
)
7693 start
= symbol_get_frag (left
);
7694 end
= symbol_get_frag (right
);
7698 start
= symbol_get_frag (right
);
7699 end
= symbol_get_frag (left
);
7702 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7703 walk
= start
->tc_frag_data
.no_transform_end
;
7708 walk
->tc_frag_data
.is_no_transform
= 1;
7709 walk
= walk
->fr_next
;
7711 while (walk
&& walk
->fr_address
< end
->fr_address
);
7713 start
->tc_frag_data
.no_transform_end
= walk
;
7720 /* Re-process all of the fragments looking to convert all of the
7721 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7722 conditional branch or a retw/retw.n, convert this frag to one that
7723 will generate a NOP. In any case close it off with a .fill 0. */
7725 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7728 xtensa_fix_a0_b_retw_frags (void)
7733 /* When this routine is called, all of the subsections are still intact
7734 so we walk over subsections instead of sections. */
7735 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7736 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7740 /* Walk over all of the fragments in a subsection. */
7741 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7743 if (fragP
->fr_type
== rs_machine_dependent
7744 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7746 if (next_instrs_are_b_retw (fragP
))
7748 if (fragP
->tc_frag_data
.is_no_transform
)
7749 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7751 relax_frag_add_nop (fragP
);
7761 next_instrs_are_b_retw (fragS
*fragP
)
7763 xtensa_opcode opcode
;
7765 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7766 static xtensa_insnbuf insnbuf
= NULL
;
7767 static xtensa_insnbuf slotbuf
= NULL
;
7768 xtensa_isa isa
= xtensa_default_isa
;
7771 bfd_boolean branch_seen
= FALSE
;
7775 insnbuf
= xtensa_insnbuf_alloc (isa
);
7776 slotbuf
= xtensa_insnbuf_alloc (isa
);
7779 if (next_fragP
== NULL
)
7782 /* Check for the conditional branch. */
7783 xtensa_insnbuf_from_chars
7784 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7785 fmt
= xtensa_format_decode (isa
, insnbuf
);
7786 if (fmt
== XTENSA_UNDEFINED
)
7789 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7791 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7792 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7794 branch_seen
= (branch_seen
7795 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7801 offset
+= xtensa_format_length (isa
, fmt
);
7802 if (offset
== next_fragP
->fr_fix
)
7804 next_fragP
= next_non_empty_frag (next_fragP
);
7808 if (next_fragP
== NULL
)
7811 /* Check for the retw/retw.n. */
7812 xtensa_insnbuf_from_chars
7813 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7814 fmt
= xtensa_format_decode (isa
, insnbuf
);
7816 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7817 have no problems. */
7818 if (fmt
== XTENSA_UNDEFINED
7819 || xtensa_format_num_slots (isa
, fmt
) != 1)
7822 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7823 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7825 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7832 /* Re-process all of the fragments looking to convert all of the
7833 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7834 loop end label, convert this frag to one that will generate a NOP.
7835 In any case close it off with a .fill 0. */
7837 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7840 xtensa_fix_b_j_loop_end_frags (void)
7845 /* When this routine is called, all of the subsections are still intact
7846 so we walk over subsections instead of sections. */
7847 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7848 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7852 /* Walk over all of the fragments in a subsection. */
7853 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7855 if (fragP
->fr_type
== rs_machine_dependent
7856 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7858 if (next_instr_is_loop_end (fragP
))
7860 if (fragP
->tc_frag_data
.is_no_transform
)
7861 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7863 relax_frag_add_nop (fragP
);
7873 next_instr_is_loop_end (fragS
*fragP
)
7875 const fragS
*next_fragP
;
7877 if (next_frag_is_loop_target (fragP
))
7880 next_fragP
= next_non_empty_frag (fragP
);
7881 if (next_fragP
== NULL
)
7884 if (!next_frag_is_loop_target (next_fragP
))
7887 /* If the size is >= 3 then there is more than one instruction here.
7888 The hardware bug will not fire. */
7889 if (next_fragP
->fr_fix
> 3)
7896 /* Re-process all of the fragments looking to convert all of the
7897 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7898 not MY loop's loop end within 12 bytes, add enough nops here to
7899 make it at least 12 bytes away. In any case close it off with a
7902 static offsetT min_bytes_to_other_loop_end
7903 (fragS
*, fragS
*, offsetT
);
7906 xtensa_fix_close_loop_end_frags (void)
7911 /* When this routine is called, all of the subsections are still intact
7912 so we walk over subsections instead of sections. */
7913 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7914 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7918 fragS
*current_target
= NULL
;
7920 /* Walk over all of the fragments in a subsection. */
7921 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7923 if (fragP
->fr_type
== rs_machine_dependent
7924 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7925 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7926 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7929 && fragP
->fr_type
== rs_machine_dependent
7930 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7933 int bytes_added
= 0;
7935 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7936 /* Max out at 12. */
7937 min_bytes
= min_bytes_to_other_loop_end
7938 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7940 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7942 if (fragP
->tc_frag_data
.is_no_transform
)
7943 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7946 while (min_bytes
+ bytes_added
7947 < REQUIRED_LOOP_DIVIDING_BYTES
)
7951 if (fragP
->fr_var
< length
)
7952 as_fatal (_("fr_var %lu < length %d"),
7953 (long) fragP
->fr_var
, length
);
7956 assemble_nop (length
,
7957 fragP
->fr_literal
+ fragP
->fr_fix
);
7958 fragP
->fr_fix
+= length
;
7959 fragP
->fr_var
-= length
;
7961 bytes_added
+= length
;
7967 gas_assert (fragP
->fr_type
!= rs_machine_dependent
7968 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7974 static offsetT
unrelaxed_frag_min_size (fragS
*);
7977 min_bytes_to_other_loop_end (fragS
*fragP
,
7978 fragS
*current_target
,
7982 fragS
*current_fragP
;
7984 for (current_fragP
= fragP
;
7986 current_fragP
= current_fragP
->fr_next
)
7988 if (current_fragP
->tc_frag_data
.is_loop_target
7989 && current_fragP
!= current_target
)
7992 offset
+= unrelaxed_frag_min_size (current_fragP
);
7994 if (offset
>= max_size
)
8002 unrelaxed_frag_min_size (fragS
*fragP
)
8004 offsetT size
= fragP
->fr_fix
;
8006 /* Add fill size. */
8007 if (fragP
->fr_type
== rs_fill
)
8008 size
+= fragP
->fr_offset
;
8015 unrelaxed_frag_max_size (fragS
*fragP
)
8017 offsetT size
= fragP
->fr_fix
;
8018 switch (fragP
->fr_type
)
8021 /* Empty frags created by the obstack allocation scheme
8022 end up with type 0. */
8027 size
+= fragP
->fr_offset
;
8035 /* No further adjustments needed. */
8037 case rs_machine_dependent
:
8038 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8039 size
+= fragP
->fr_var
;
8042 /* We had darn well better know how big it is. */
8051 /* Re-process all of the fragments looking to convert all
8052 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8055 1) the instruction size count to the loop end label
8056 is too short (<= 2 instructions),
8057 2) loop has a jump or branch in it
8060 1) workaround_all_short_loops is TRUE
8061 2) The generating loop was a 'loopgtz' or 'loopnez'
8062 3) the instruction size count to the loop end label is too short
8064 then convert this frag (and maybe the next one) to generate a NOP.
8065 In any case close it off with a .fill 0. */
8067 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8068 static bfd_boolean
branch_before_loop_end (fragS
*);
8071 xtensa_fix_short_loop_frags (void)
8076 /* When this routine is called, all of the subsections are still intact
8077 so we walk over subsections instead of sections. */
8078 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8079 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8082 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8084 /* Walk over all of the fragments in a subsection. */
8085 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8087 if (fragP
->fr_type
== rs_machine_dependent
8088 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8089 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8092 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8093 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8094 current_opcode
= t_insn
.opcode
;
8095 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8096 current_opcode
) == 1);
8099 if (fragP
->fr_type
== rs_machine_dependent
8100 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8102 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8103 && (branch_before_loop_end (fragP
->fr_next
)
8104 || (workaround_all_short_loops
8105 && current_opcode
!= XTENSA_UNDEFINED
8106 && current_opcode
!= xtensa_loop_opcode
)))
8108 if (fragP
->tc_frag_data
.is_no_transform
)
8109 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8111 relax_frag_add_nop (fragP
);
8120 static int unrelaxed_frag_min_insn_count (fragS
*);
8123 count_insns_to_loop_end (fragS
*base_fragP
,
8124 bfd_boolean count_relax_add
,
8127 fragS
*fragP
= NULL
;
8132 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8134 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8135 if (insn_count
>= max_count
)
8138 if (count_relax_add
)
8140 if (fragP
->fr_type
== rs_machine_dependent
8141 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8143 /* In order to add the appropriate number of
8144 NOPs, we count an instruction for downstream
8147 if (insn_count
>= max_count
)
8157 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8159 xtensa_isa isa
= xtensa_default_isa
;
8160 static xtensa_insnbuf insnbuf
= NULL
;
8164 if (!fragP
->tc_frag_data
.is_insn
)
8168 insnbuf
= xtensa_insnbuf_alloc (isa
);
8170 /* Decode the fixed instructions. */
8171 while (offset
< fragP
->fr_fix
)
8175 xtensa_insnbuf_from_chars
8176 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8177 fmt
= xtensa_format_decode (isa
, insnbuf
);
8179 if (fmt
== XTENSA_UNDEFINED
)
8181 as_fatal (_("undecodable instruction in instruction frag"));
8184 offset
+= xtensa_format_length (isa
, fmt
);
8192 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8195 branch_before_loop_end (fragS
*base_fragP
)
8199 for (fragP
= base_fragP
;
8200 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8201 fragP
= fragP
->fr_next
)
8203 if (unrelaxed_frag_has_b_j (fragP
))
8211 unrelaxed_frag_has_b_j (fragS
*fragP
)
8213 static xtensa_insnbuf insnbuf
= NULL
;
8214 xtensa_isa isa
= xtensa_default_isa
;
8217 if (!fragP
->tc_frag_data
.is_insn
)
8221 insnbuf
= xtensa_insnbuf_alloc (isa
);
8223 /* Decode the fixed instructions. */
8224 while (offset
< fragP
->fr_fix
)
8229 xtensa_insnbuf_from_chars
8230 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8231 fmt
= xtensa_format_decode (isa
, insnbuf
);
8232 if (fmt
== XTENSA_UNDEFINED
)
8235 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8237 xtensa_opcode opcode
=
8238 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8239 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8240 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8243 offset
+= xtensa_format_length (isa
, fmt
);
8249 /* Checks to be made after initial assembly but before relaxation. */
8251 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8252 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8255 xtensa_sanity_check (void)
8262 as_where (&file_name
, &line
);
8263 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8264 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8268 /* Walk over all of the fragments in a subsection. */
8269 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8271 if (fragP
->fr_type
== rs_machine_dependent
8272 && fragP
->fr_subtype
== RELAX_SLOTS
8273 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8275 static xtensa_insnbuf insnbuf
= NULL
;
8278 if (fragP
->fr_opcode
!= NULL
)
8281 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8282 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8283 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8285 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8286 t_insn
.opcode
) == 1)
8288 if (is_empty_loop (&t_insn
, fragP
))
8290 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8291 as_bad (_("invalid empty loop"));
8293 if (!is_local_forward_loop (&t_insn
, fragP
))
8295 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8296 as_bad (_("loop target does not follow "
8297 "loop instruction in section"));
8304 new_logical_line (file_name
, line
);
8308 #define LOOP_IMMED_OPN 1
8310 /* Return TRUE if the loop target is the next non-zero fragment. */
8313 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8315 const expressionS
*exp
;
8319 if (insn
->insn_type
!= ITYPE_INSN
)
8322 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8325 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8328 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8330 if (exp
->X_op
!= O_symbol
)
8333 symbolP
= exp
->X_add_symbol
;
8337 if (symbol_get_frag (symbolP
) == NULL
)
8340 if (S_GET_VALUE (symbolP
) != 0)
8343 /* Walk through the zero-size fragments from this one. If we find
8344 the target fragment, then this is a zero-size loop. */
8346 for (next_fragP
= fragP
->fr_next
;
8348 next_fragP
= next_fragP
->fr_next
)
8350 if (next_fragP
== symbol_get_frag (symbolP
))
8352 if (next_fragP
->fr_fix
!= 0)
8360 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8362 const expressionS
*exp
;
8366 if (insn
->insn_type
!= ITYPE_INSN
)
8369 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8372 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8375 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8377 if (exp
->X_op
!= O_symbol
)
8380 symbolP
= exp
->X_add_symbol
;
8384 if (symbol_get_frag (symbolP
) == NULL
)
8387 /* Walk through fragments until we find the target.
8388 If we do not find the target, then this is an invalid loop. */
8390 for (next_fragP
= fragP
->fr_next
;
8392 next_fragP
= next_fragP
->fr_next
)
8394 if (next_fragP
== symbol_get_frag (symbolP
))
8402 #define XTINFO_NAME "Xtensa_Info"
8403 #define XTINFO_NAMESZ 12
8404 #define XTINFO_TYPE 1
8407 xtensa_add_config_info (void)
8413 info_sec
= subseg_new (".xtensa.info", 0);
8414 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8416 data
= xmalloc (100);
8417 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8418 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8419 sz
= strlen (data
) + 1;
8421 /* Add enough null terminators to pad to a word boundary. */
8424 while ((sz
& 3) != 0);
8426 /* Follow the standard note section layout:
8427 First write the length of the name string. */
8429 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8431 /* Next comes the length of the "descriptor", i.e., the actual data. */
8433 md_number_to_chars (p
, (valueT
) sz
, 4);
8435 /* Write the note type. */
8437 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8439 /* Write the name field. */
8440 p
= frag_more (XTINFO_NAMESZ
);
8441 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8443 /* Finally, write the descriptor. */
8445 memcpy (p
, data
, sz
);
8451 /* Alignment Functions. */
8454 get_text_align_power (unsigned target_size
)
8456 if (target_size
<= 4)
8459 if (target_size
<= 8)
8462 if (target_size
<= 16)
8465 if (target_size
<= 32)
8468 if (target_size
<= 64)
8471 if (target_size
<= 128)
8474 if (target_size
<= 256)
8477 if (target_size
<= 512)
8480 if (target_size
<= 1024)
8489 get_text_align_max_fill_size (int align_pow
,
8490 bfd_boolean use_nops
,
8491 bfd_boolean use_no_density
)
8494 return (1 << align_pow
);
8496 return 3 * (1 << align_pow
);
8498 return 1 + (1 << align_pow
);
8502 /* Calculate the minimum bytes of fill needed at "address" to align a
8503 target instruction of size "target_size" so that it does not cross a
8504 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8505 the fill can be an arbitrary number of bytes. Otherwise, the space must
8506 be filled by NOP instructions. */
8509 get_text_align_fill_size (addressT address
,
8512 bfd_boolean use_nops
,
8513 bfd_boolean use_no_density
)
8515 addressT alignment
, fill
, fill_limit
, fill_step
;
8516 bfd_boolean skip_one
= FALSE
;
8518 alignment
= (1 << align_pow
);
8519 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8523 fill_limit
= alignment
;
8526 else if (!use_no_density
)
8528 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8529 fill_limit
= alignment
* 2;
8535 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8536 fill_limit
= alignment
* 3;
8540 /* Try all fill sizes until finding one that works. */
8541 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8543 if (skip_one
&& fill
== 1)
8545 if ((address
+ fill
) >> align_pow
8546 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8555 branch_align_power (segT sec
)
8557 /* If the Xtensa processor has a fetch width of X, and
8558 the section is aligned to at least that boundary, then a branch
8559 target need only fit within that aligned block of memory to avoid
8560 a stall. Otherwise, try to fit branch targets within 4-byte
8561 aligned blocks (which may be insufficient, e.g., if the section
8562 has no alignment, but it's good enough). */
8563 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8564 int sec_align
= get_recorded_alignment (sec
);
8566 if (sec_align
>= fetch_align
)
8573 /* This will assert if it is not possible. */
8576 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8582 gas_assert (fill_size
% 3 == 0);
8583 return (fill_size
/ 3);
8586 gas_assert (fill_size
!= 1); /* Bad argument. */
8588 while (fill_size
> 1)
8591 if (fill_size
== 2 || fill_size
== 4)
8593 fill_size
-= insn_size
;
8596 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8602 get_text_align_nth_nop_size (offsetT fill_size
,
8604 bfd_boolean use_no_density
)
8611 gas_assert (fill_size
!= 1); /* Bad argument. */
8613 while (fill_size
> 1)
8616 if (fill_size
== 2 || fill_size
== 4)
8618 fill_size
-= insn_size
;
8628 /* For the given fragment, find the appropriate address
8629 for it to begin at if we are using NOPs to align it. */
8632 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8634 /* The rule is: get next fragment's FIRST instruction. Find
8635 the smallest number of bytes that need to be added to
8636 ensure that the next fragment's FIRST instruction will fit
8639 E.G., 2 bytes : 0, 1, 2 mod 4
8642 If the FIRST instruction MIGHT be relaxed,
8643 assume that it will become a 3-byte instruction.
8645 Note again here that LOOP instructions are not bundleable,
8646 and this relaxation only applies to LOOP opcodes. */
8649 int first_insn_size
;
8651 addressT pre_opcode_bytes
;
8654 xtensa_opcode opcode
;
8655 bfd_boolean is_loop
;
8657 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8658 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8660 /* Find the loop frag. */
8661 first_insn
= next_non_empty_frag (fragP
);
8662 /* Now find the first insn frag. */
8663 first_insn
= next_non_empty_frag (first_insn
);
8665 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8666 gas_assert (is_loop
);
8667 loop_insn_size
= xg_get_single_size (opcode
);
8669 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8670 pre_opcode_bytes
+= loop_insn_size
;
8672 /* For loops, the alignment depends on the size of the
8673 instruction following the loop, not the LOOP instruction. */
8675 if (first_insn
== NULL
)
8676 first_insn_size
= xtensa_fetch_width
;
8678 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8680 /* If it was 8, then we'll need a larger alignment for the section. */
8681 align_power
= get_text_align_power (first_insn_size
);
8682 record_alignment (now_seg
, align_power
);
8684 fill_size
= get_text_align_fill_size
8685 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8686 fragP
->tc_frag_data
.is_no_density
);
8688 return address
+ fill_size
;
8692 /* 3 mechanisms for relaxing an alignment:
8694 Align to a power of 2.
8695 Align so the next fragment's instruction does not cross a word boundary.
8696 Align the current instruction so that if the next instruction
8697 were 3 bytes, it would not cross a word boundary.
8701 zeros - This is easy; always insert zeros.
8702 nops - 3-byte and 2-byte instructions
8706 >=5 : 3-byte instruction + fn (n-3)
8707 widening - widen previous instructions. */
8710 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8712 addressT target_address
, loop_insn_offset
;
8714 xtensa_opcode loop_opcode
;
8715 bfd_boolean is_loop
;
8718 offsetT branch_align
;
8721 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8722 switch (fragP
->fr_subtype
)
8724 case RELAX_DESIRE_ALIGN
:
8725 target_size
= next_frag_format_size (fragP
);
8726 if (target_size
== XTENSA_UNDEFINED
)
8728 align_power
= branch_align_power (now_seg
);
8729 branch_align
= 1 << align_power
;
8730 /* Don't count on the section alignment being as large as the target. */
8731 if (target_size
> branch_align
)
8732 target_size
= branch_align
;
8733 opt_diff
= get_text_align_fill_size (address
, align_power
,
8734 target_size
, FALSE
, FALSE
);
8736 *max_diff
= (opt_diff
+ branch_align
8737 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8738 gas_assert (*max_diff
>= opt_diff
);
8741 case RELAX_ALIGN_NEXT_OPCODE
:
8742 /* The next non-empty frag after this one holds the LOOP instruction
8743 that needs to be aligned. The required alignment depends on the
8744 size of the next non-empty frag after the loop frag, i.e., the
8745 first instruction in the loop. */
8746 loop_frag
= next_non_empty_frag (fragP
);
8747 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8748 loop_insn_offset
= 0;
8749 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8750 gas_assert (is_loop
);
8752 /* If the loop has been expanded then the LOOP instruction
8753 could be at an offset from this fragment. */
8754 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8755 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8757 /* In an ideal world, which is what we are shooting for here,
8758 we wouldn't need to use any NOPs immediately prior to the
8759 LOOP instruction. If this approach fails, relax_frag_loop_align
8760 will call get_noop_aligned_address. */
8762 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8763 align_power
= get_text_align_power (target_size
);
8764 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8765 target_size
, FALSE
, FALSE
);
8767 *max_diff
= xtensa_fetch_width
8768 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8769 - target_size
+ opt_diff
;
8770 gas_assert (*max_diff
>= opt_diff
);
8781 /* md_relax_frag Hook and Helper Functions. */
8783 static long relax_frag_loop_align (fragS
*, long);
8784 static long relax_frag_for_align (fragS
*, long);
8785 static long relax_frag_immed
8786 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8788 typedef struct cached_fixup cached_fixupS
;
8797 typedef struct fixup_cache fixup_cacheS
;
8800 cached_fixupS
*fixups
;
8808 static int fixup_order (const void *a
, const void *b
)
8810 const cached_fixupS
*pa
= a
;
8811 const cached_fixupS
*pb
= b
;
8813 if (pa
->addr
== pb
->addr
)
8815 if (pa
->target
== pb
->target
)
8817 if (pa
->fixP
->fx_r_type
== pb
->fixP
->fx_r_type
)
8819 return pa
->fixP
->fx_r_type
< pb
->fixP
->fx_r_type
? -1 : 1;
8821 return pa
->target
- pb
->target
;
8823 return pa
->addr
- pb
->addr
;
8826 static bfd_boolean
xtensa_make_cached_fixup (cached_fixupS
*o
, fixS
*fixP
)
8828 xtensa_isa isa
= xtensa_default_isa
;
8829 int addr
= fixP
->fx_frag
->fr_address
;
8832 symbolS
*s
= fixP
->fx_addsy
;
8835 xtensa_opcode opcode
;
8837 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
8838 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
8840 target
= S_GET_VALUE (s
);
8841 delta
= target
- addr
;
8843 if (abs(delta
) < J_RANGE
/ 2)
8846 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
8847 (unsigned char *) fixP
->fx_frag
->fr_literal
+
8849 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
8850 gas_assert (fmt
!= XTENSA_UNDEFINED
);
8851 slot
= fixP
->tc_fix_data
.slot
;
8852 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
8853 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
8854 if (opcode
!= xtensa_j_opcode
)
8865 static void xtensa_realloc_fixup_cache (fixup_cacheS
*cache
, unsigned add
)
8867 if (cache
->n_fixups
+ add
> cache
->n_max
)
8869 cache
->n_max
= (cache
->n_fixups
+ add
) * 2;
8870 cache
->fixups
= xrealloc (cache
->fixups
,
8871 sizeof (*cache
->fixups
) * cache
->n_max
);
8875 static void xtensa_cache_relaxable_fixups (fixup_cacheS
*cache
,
8876 segment_info_type
*seginfo
)
8880 cache
->n_fixups
= 0;
8882 for (fixP
= seginfo
->fix_root
; fixP
; fixP
= fixP
->fx_next
)
8884 xtensa_realloc_fixup_cache (cache
, 1);
8886 if (xtensa_make_cached_fixup (cache
->fixups
+ cache
->n_fixups
, fixP
))
8889 qsort (cache
->fixups
, cache
->n_fixups
, sizeof (*cache
->fixups
), fixup_order
);
8892 static unsigned xtensa_find_first_cached_fixup (const fixup_cacheS
*cache
,
8896 unsigned b
= cache
->n_fixups
;
8900 unsigned c
= (a
+ b
) / 2;
8902 if (cache
->fixups
[c
].addr
< addr
)
8910 static void xtensa_delete_cached_fixup (fixup_cacheS
*cache
, unsigned i
)
8912 memmove (cache
->fixups
+ i
, cache
->fixups
+ i
+ 1,
8913 (cache
->n_fixups
- i
- 1) * sizeof (*cache
->fixups
));
8917 static bfd_boolean
xtensa_add_cached_fixup (fixup_cacheS
*cache
, fixS
*fixP
)
8922 if (!xtensa_make_cached_fixup (&o
, fixP
))
8924 xtensa_realloc_fixup_cache (cache
, 1);
8925 i
= xtensa_find_first_cached_fixup (cache
, o
.addr
);
8926 if (i
< cache
->n_fixups
)
8929 memmove (cache
->fixups
+ i
+ 1, cache
->fixups
+ i
,
8930 (cache
->n_fixups
- i
) * sizeof (*cache
->fixups
));
8932 cache
->fixups
[i
] = o
;
8937 /* Return the number of bytes added to this fragment, given that the
8938 input has been stretched already by "stretch". */
8941 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8943 xtensa_isa isa
= xtensa_default_isa
;
8944 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8945 long new_stretch
= 0;
8949 static xtensa_insnbuf vbuf
= NULL
;
8950 int slot
, num_slots
;
8953 as_where (&file_name
, &line
);
8954 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8956 fragP
->tc_frag_data
.unreported_expansion
= 0;
8958 switch (fragP
->fr_subtype
)
8960 case RELAX_ALIGN_NEXT_OPCODE
:
8961 /* Always convert. */
8962 if (fragP
->tc_frag_data
.relax_seen
)
8963 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8966 case RELAX_LOOP_END
:
8970 case RELAX_LOOP_END_ADD_NOP
:
8971 /* Add a NOP and switch to .fill 0. */
8972 new_stretch
= relax_frag_add_nop (fragP
);
8976 case RELAX_DESIRE_ALIGN
:
8977 /* Do nothing. The narrowing before this frag will either align
8982 case RELAX_LITERAL_FINAL
:
8985 case RELAX_LITERAL_NR
:
8987 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8988 gas_assert (unreported
== lit_size
);
8989 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8990 fragP
->fr_var
-= lit_size
;
8991 fragP
->fr_fix
+= lit_size
;
8997 vbuf
= xtensa_insnbuf_alloc (isa
);
8999 xtensa_insnbuf_from_chars
9000 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
9001 fmt
= xtensa_format_decode (isa
, vbuf
);
9002 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9004 for (slot
= 0; slot
< num_slots
; slot
++)
9006 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9009 if (fragP
->tc_frag_data
.relax_seen
)
9010 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9014 case RELAX_IMMED_STEP1
:
9015 case RELAX_IMMED_STEP2
:
9016 case RELAX_IMMED_STEP3
:
9017 /* Place the immediate. */
9018 new_stretch
+= relax_frag_immed
9019 (now_seg
, fragP
, stretch
,
9020 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9021 fmt
, slot
, stretched_p
, FALSE
);
9025 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9031 case RELAX_LITERAL_POOL_BEGIN
:
9032 case RELAX_LITERAL_POOL_END
:
9033 case RELAX_MAYBE_UNREACHABLE
:
9034 case RELAX_MAYBE_DESIRE_ALIGN
:
9035 /* No relaxation required. */
9038 case RELAX_FILL_NOP
:
9039 case RELAX_UNREACHABLE
:
9040 if (fragP
->tc_frag_data
.relax_seen
)
9041 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9044 case RELAX_TRAMPOLINE
:
9045 if (fragP
->tc_frag_data
.relax_seen
)
9047 static fixup_cacheS fixup_cache
;
9048 segment_info_type
*seginfo
= seg_info (now_seg
);
9049 int trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9050 int searchaddr
= trampaddr
< J_RANGE
? 0 : trampaddr
- J_RANGE
;
9053 if (now_seg
!= fixup_cache
.seg
||
9054 fragP
== fixup_cache
.first_frag
||
9055 fixup_cache
.first_frag
== NULL
)
9057 xtensa_cache_relaxable_fixups (&fixup_cache
, seginfo
);
9058 fixup_cache
.seg
= now_seg
;
9059 fixup_cache
.first_frag
= fragP
;
9062 /* Scan for jumps that will not reach. */
9063 for (i
= xtensa_find_first_cached_fixup (&fixup_cache
, searchaddr
);
9064 i
< fixup_cache
.n_fixups
; ++i
)
9067 fixS
*fixP
= fixup_cache
.fixups
[i
].fixP
;
9068 int target
= fixup_cache
.fixups
[i
].target
;
9069 int addr
= fixup_cache
.fixups
[i
].addr
;
9070 int delta
= fixup_cache
.fixups
[i
].delta
+ stretch
;
9072 trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9074 if (addr
+ J_RANGE
< trampaddr
)
9076 if (addr
> trampaddr
+ J_RANGE
)
9078 if (abs (delta
) < J_RANGE
)
9081 slot
= fixP
->tc_fix_data
.slot
;
9083 if (delta
> J_RANGE
|| delta
< -1 * J_RANGE
)
9084 { /* Found an out-of-range jump; scan the list of trampolines for the best match. */
9085 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9086 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9087 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9088 int lower
= (target
< addr
) ? target
: addr
;
9089 int upper
= (target
> addr
) ? target
: addr
;
9090 int midpoint
= lower
+ (upper
- lower
) / 2;
9092 if ((upper
- lower
) > 2 * J_RANGE
)
9094 /* One trampoline won't suffice; we need multiple jumps.
9095 Jump to the trampoline that's farthest, but still in
9096 range relative to the original "j" instruction. */
9097 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9099 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9100 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0 ;
9105 if (this_addr
- addr
< J_RANGE
)
9110 /* Backward jump. */
9111 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9118 struct trampoline_frag
*best_tf
= NULL
;
9121 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9123 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9124 int this_delta
= abs (this_addr
- midpoint
);
9126 if (!best_tf
|| this_delta
< best_delta
)
9129 best_delta
= this_delta
;
9134 if (tf
->fragP
== fragP
)
9136 if (abs (addr
- trampaddr
) < J_RANGE
)
9137 { /* The trampoline is in range of original; fix it! */
9142 fragS
*fP
; /* The out-of-range jump. */
9144 new_stretch
+= init_trampoline_frag (tf
);
9145 offset
= fragP
->fr_fix
; /* Where to assemble the j insn. */
9146 lsym
= fragP
->fr_symbol
;
9148 /* Assemble a jump to the target label here. */
9150 insn
.insn_type
= ITYPE_INSN
;
9151 insn
.opcode
= xtensa_j_opcode
;
9153 set_expr_symbol_offset (&insn
.tok
[0], lsym
, offset
);
9154 fmt
= xg_get_single_format (xtensa_j_opcode
);
9155 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9156 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9157 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fragP
->fr_literal
+ offset
, 3);
9160 /* Add a fix-up for the original j insn. */
9161 newfixP
= fix_new (fP
, fixP
->fx_where
, fixP
->fx_size
, lsym
, fragP
->fr_fix
- 3, TRUE
, fixP
->fx_r_type
);
9162 newfixP
->fx_no_overflow
= 1;
9163 newfixP
->tc_fix_data
.X_add_symbol
= lsym
;
9164 newfixP
->tc_fix_data
.X_add_number
= offset
;
9165 newfixP
->tc_fix_data
.slot
= slot
;
9167 xtensa_delete_cached_fixup (&fixup_cache
, i
);
9168 xtensa_add_cached_fixup (&fixup_cache
, newfixP
);
9170 /* Move the fix-up from the original j insn to this one. */
9171 fixP
->fx_frag
= fragP
;
9172 fixP
->fx_where
= fragP
->fr_fix
- 3;
9173 fixP
->tc_fix_data
.slot
= 0;
9175 xtensa_add_cached_fixup (&fixup_cache
, fixP
);
9177 /* re-do current fixup */
9180 /* Adjust the jump around this trampoline (if present). */
9181 if (tf
->fixP
!= NULL
)
9183 tf
->fixP
->fx_offset
+= 3;
9186 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9187 /* Do we have room for more? */
9188 if (fragP
->fr_var
< 3)
9189 { /* No, convert to fill. */
9191 fragP
->fr_subtype
= 0;
9192 /* Remove from the trampoline_list. */
9193 prev
->next
= tf
->next
;
9194 if (fragP
== fixup_cache
.first_frag
)
9195 fixup_cache
.first_frag
= NULL
;
9206 as_bad (_("bad relaxation state"));
9209 /* Tell gas we need another relaxation pass. */
9210 if (! fragP
->tc_frag_data
.relax_seen
)
9212 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9216 new_logical_line (file_name
, line
);
9222 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9224 addressT old_address
, old_next_address
, old_size
;
9225 addressT new_address
, new_next_address
, new_size
;
9228 /* All the frags with relax_frag_for_alignment prior to this one in the
9229 section have been done, hopefully eliminating the need for a NOP here.
9230 But, this will put it in if necessary. */
9232 /* Calculate the old address of this fragment and the next fragment. */
9233 old_address
= fragP
->fr_address
- stretch
;
9234 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9235 fragP
->tc_frag_data
.text_expansion
[0]);
9236 old_size
= old_next_address
- old_address
;
9238 /* Calculate the new address of this fragment and the next fragment. */
9239 new_address
= fragP
->fr_address
;
9241 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9242 new_size
= new_next_address
- new_address
;
9244 growth
= new_size
- old_size
;
9246 /* Fix up the text_expansion field and return the new growth. */
9247 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9252 /* Add a NOP instruction. */
9255 relax_frag_add_nop (fragS
*fragP
)
9257 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9258 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9259 assemble_nop (length
, nop_buf
);
9260 fragP
->tc_frag_data
.is_insn
= TRUE
;
9262 if (fragP
->fr_var
< length
)
9264 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9268 fragP
->fr_fix
+= length
;
9269 fragP
->fr_var
-= length
;
9274 static long future_alignment_required (fragS
*, long);
9277 relax_frag_for_align (fragS
*fragP
, long stretch
)
9279 /* Overview of the relaxation procedure for alignment:
9280 We can widen with NOPs or by widening instructions or by filling
9281 bytes after jump instructions. Find the opportune places and widen
9282 them if necessary. */
9287 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9288 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9289 || (fragP
->fr_subtype
== RELAX_SLOTS
9290 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9292 stretch_me
= future_alignment_required (fragP
, stretch
);
9293 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9299 /* We expanded on a previous pass. Can we shrink now? */
9300 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9301 if (shrink
<= stretch
&& stretch
> 0)
9303 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9309 /* Below here, diff > 0. */
9310 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9316 /* Return the address of the next frag that should be aligned.
9318 By "address" we mean the address it _would_ be at if there
9319 is no action taken to align it between here and the target frag.
9320 In other words, if no narrows and no fill nops are used between
9321 here and the frag to align, _even_if_ some of the frags we use
9322 to align targets have already expanded on a previous relaxation
9325 Also, count each frag that may be used to help align the target.
9327 Return 0 if there are no frags left in the chain that need to be
9331 find_address_of_next_align_frag (fragS
**fragPP
,
9335 bfd_boolean
*paddable
)
9337 fragS
*fragP
= *fragPP
;
9338 addressT address
= fragP
->fr_address
;
9340 /* Do not reset the counts to 0. */
9344 /* Limit this to a small search. */
9345 if (*widens
>= (int) xtensa_fetch_width
)
9350 address
+= fragP
->fr_fix
;
9352 if (fragP
->fr_type
== rs_fill
)
9353 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9354 else if (fragP
->fr_type
== rs_machine_dependent
)
9356 switch (fragP
->fr_subtype
)
9358 case RELAX_UNREACHABLE
:
9362 case RELAX_FILL_NOP
:
9364 if (!fragP
->tc_frag_data
.is_no_density
)
9369 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9374 address
+= total_frag_text_expansion (fragP
);
9378 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9381 case RELAX_ALIGN_NEXT_OPCODE
:
9382 case RELAX_DESIRE_ALIGN
:
9386 case RELAX_MAYBE_UNREACHABLE
:
9387 case RELAX_MAYBE_DESIRE_ALIGN
:
9392 /* Just punt if we don't know the type. */
9399 /* Just punt if we don't know the type. */
9403 fragP
= fragP
->fr_next
;
9411 static long bytes_to_stretch (fragS
*, int, int, int, int);
9414 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9416 fragS
*this_frag
= fragP
;
9420 int narrow_nops
= 0;
9421 bfd_boolean paddable
= FALSE
;
9422 offsetT local_opt_diff
;
9425 int stretch_amount
= 0;
9426 int local_stretch_amount
;
9427 int global_stretch_amount
;
9429 address
= find_address_of_next_align_frag
9430 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9434 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9435 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9437 frag_wane (this_frag
);
9441 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9442 opt_diff
= local_opt_diff
;
9443 gas_assert (opt_diff
>= 0);
9444 gas_assert (max_diff
>= opt_diff
);
9449 fragP
= fragP
->fr_next
;
9451 while (fragP
&& opt_diff
< max_diff
&& address
)
9453 /* We only use these to determine if we can exit early
9454 because there will be plenty of ways to align future
9456 int glob_widens
= 0;
9459 bfd_boolean glob_pad
= 0;
9460 address
= find_address_of_next_align_frag
9461 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9462 /* If there is a padable portion, then skip. */
9463 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9468 offsetT next_m_diff
;
9469 offsetT next_o_diff
;
9471 /* Downrange frags haven't had stretch added to them yet. */
9474 /* The address also includes any text expansion from this
9475 frag in a previous pass, but we don't want that. */
9476 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9478 /* Assume we are going to move at least opt_diff. In
9479 reality, we might not be able to, but assuming that
9480 we will helps catch cases where moving opt_diff pushes
9481 the next target from aligned to unaligned. */
9482 address
+= opt_diff
;
9484 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9486 /* Now cleanup for the adjustments to address. */
9487 next_o_diff
+= opt_diff
;
9488 next_m_diff
+= opt_diff
;
9489 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9490 opt_diff
= next_o_diff
;
9491 if (next_m_diff
< max_diff
)
9492 max_diff
= next_m_diff
;
9493 fragP
= fragP
->fr_next
;
9497 /* If there are enough wideners in between, do it. */
9500 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9502 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9507 local_stretch_amount
9508 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9509 num_widens
, local_opt_diff
);
9510 global_stretch_amount
9511 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9512 num_widens
, opt_diff
);
9513 /* If the condition below is true, then the frag couldn't
9514 stretch the correct amount for the global case, so we just
9515 optimize locally. We'll rely on the subsequent frags to get
9516 the correct alignment in the global case. */
9517 if (global_stretch_amount
< local_stretch_amount
)
9518 stretch_amount
= local_stretch_amount
;
9520 stretch_amount
= global_stretch_amount
;
9522 if (this_frag
->fr_subtype
== RELAX_SLOTS
9523 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9524 gas_assert (stretch_amount
<= 1);
9525 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9527 if (this_frag
->tc_frag_data
.is_no_density
)
9528 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9530 gas_assert (stretch_amount
<= 3);
9533 return stretch_amount
;
9537 /* The idea: widen everything you can to get a target or loop aligned,
9538 then start using NOPs.
9540 wide_nops = the number of wide NOPs available for aligning
9541 narrow_nops = the number of narrow NOPs available for aligning
9542 (a subset of wide_nops)
9543 widens = the number of narrow instructions that should be widened
9548 bytes_to_stretch (fragS
*this_frag
,
9557 int bytes_short
= desired_diff
- num_widens
;
9559 gas_assert (desired_diff
>= 0
9560 && desired_diff
< (signed) xtensa_fetch_width
);
9561 if (desired_diff
== 0)
9564 gas_assert (wide_nops
> 0 || num_widens
> 0);
9566 /* Always prefer widening to NOP-filling. */
9567 if (bytes_short
< 0)
9569 /* There are enough RELAX_NARROW frags after this one
9570 to align the target without widening this frag in any way. */
9574 if (bytes_short
== 0)
9576 /* Widen every narrow between here and the align target
9577 and the align target will be properly aligned. */
9578 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9584 /* From here we will need at least one NOP to get an alignment.
9585 However, we may not be able to align at all, in which case,
9587 nops_needed
= desired_diff
/ 3;
9589 /* If there aren't enough nops, don't widen. */
9590 if (nops_needed
> wide_nops
)
9593 /* First try it with all wide nops. */
9594 nop_bytes
= nops_needed
* 3;
9595 extra_bytes
= desired_diff
- nop_bytes
;
9597 if (nop_bytes
+ num_widens
>= desired_diff
)
9599 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9601 else if (num_widens
== extra_bytes
)
9606 /* Add a narrow nop. */
9610 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9613 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9615 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9616 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9617 else if (num_widens
== extra_bytes
)
9622 /* Replace a wide nop with a narrow nop--we can get here if
9623 extra_bytes was negative in the previous conditional. */
9624 if (narrow_nops
== 1)
9628 if (nop_bytes
+ num_widens
>= desired_diff
)
9630 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9631 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9632 else if (num_widens
== extra_bytes
)
9637 /* If we can't satisfy any of the above cases, then we can't align
9638 using padding or fill nops. */
9643 static struct trampoline_frag
*
9644 search_trampolines (TInsn
*tinsn
, fragS
*fragP
, bfd_boolean unreachable_only
)
9646 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9647 struct trampoline_frag
*tf
= (ts
) ? ts
->trampoline_list
.next
: NULL
;
9648 struct trampoline_frag
*best_tf
= NULL
;
9651 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
9652 offsetT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
9653 offsetT addr
= fragP
->fr_address
;
9654 offsetT lower
= (addr
< target
) ? addr
: target
;
9655 offsetT upper
= (addr
> target
) ? addr
: target
;
9656 int delta
= upper
- lower
;
9657 offsetT midpoint
= lower
+ delta
/ 2;
9658 int this_delta
= -1;
9661 if (delta
> 2 * J_RANGE
)
9663 /* One trampoline won't do; we need multiple.
9664 Choose the farthest trampoline that's still in range of the original
9665 and let a later pass finish the job. */
9666 for ( ; tf
; tf
= tf
->next
)
9668 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0;
9670 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9674 if (this_addr
- addr
< J_RANGE
)
9679 /* Backward jump. */
9680 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9684 if (abs (addr
- this_addr
) < J_RANGE
)
9689 for ( ; tf
; tf
= tf
->next
)
9691 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9692 this_delta
= abs (this_addr
- midpoint
);
9693 if (unreachable_only
&& tf
->needs_jump_around
)
9695 if (!best_tf
|| this_delta
< best_delta
)
9698 best_delta
= this_delta
;
9699 best_addr
= this_addr
;
9704 best_delta
< J_RANGE
&&
9705 abs(best_addr
- lower
) < J_RANGE
&&
9706 abs(best_addr
- upper
) < J_RANGE
)
9709 return NULL
; /* No suitable trampoline found. */
9713 static struct trampoline_frag
*
9714 get_best_trampoline (TInsn
*tinsn
, fragS
*fragP
)
9716 struct trampoline_frag
*tf
= NULL
;
9718 tf
= search_trampolines (tinsn
, fragP
, TRUE
); /* Try unreachable first. */
9721 tf
= search_trampolines (tinsn
, fragP
, FALSE
); /* Try ones needing a jump-around, too. */
9728 check_and_update_trampolines (void)
9730 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9731 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9732 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9734 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9736 if (tf
->fragP
->fr_var
< 3)
9738 frag_wane (tf
->fragP
);
9739 prev
->next
= tf
->next
;
9747 init_trampoline_frag (struct trampoline_frag
*trampP
)
9749 fragS
*fp
= trampP
->fragP
;
9752 if (fp
->fr_fix
== 0)
9755 char label
[10 + 2 * sizeof(fp
)];
9756 sprintf (label
, ".L0_TR_%p", fp
);
9758 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
9759 fp
->fr_symbol
= lsym
;
9760 if (trampP
->needs_jump_around
)
9762 /* Add a jump around this block of jumps, in case
9763 control flows into this block. */
9767 xtensa_isa isa
= xtensa_default_isa
;
9769 fp
->tc_frag_data
.is_insn
= 1;
9770 /* Assemble a jump insn. */
9772 insn
.insn_type
= ITYPE_INSN
;
9773 insn
.opcode
= xtensa_j_opcode
;
9775 set_expr_symbol_offset (&insn
.tok
[0], lsym
, 3);
9776 fmt
= xg_get_single_format (xtensa_j_opcode
);
9777 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9778 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9779 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fp
->fr_literal
, 3);
9783 fixP
= fix_new (fp
, 0, 3, lsym
, 3, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
9784 trampP
->fixP
= fixP
;
9792 add_jump_to_trampoline (struct trampoline_frag
*trampP
, fragS
*origfrag
)
9794 fragS
*tramp
= trampP
->fragP
;
9796 int offset
= tramp
->fr_fix
; /* Where to assemble the j insn. */
9802 xtensa_isa isa
= xtensa_default_isa
;
9805 lsym
= tramp
->fr_symbol
;
9806 /* Assemble a jump to the target label in the trampoline frag. */
9807 tsym
= origfrag
->tc_frag_data
.slot_symbols
[0];
9808 toffset
= origfrag
-> tc_frag_data
.slot_offsets
[0];
9810 insn
.insn_type
= ITYPE_INSN
;
9811 insn
.opcode
= xtensa_j_opcode
;
9813 set_expr_symbol_offset (&insn
.tok
[0], tsym
, toffset
);
9814 fmt
= xg_get_single_format (xtensa_j_opcode
);
9815 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9816 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9817 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)tramp
->fr_literal
+ offset
, 3);
9821 /* add a fix-up for the trampoline jump. */
9822 fixP
= fix_new (tramp
, tramp
->fr_fix
- 3, 3, tsym
, toffset
, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
9823 /* Modify the jump at the start of this trampoline to point past the newly-added jump. */
9824 fixP
= trampP
->fixP
;
9826 fixP
->fx_offset
+= 3;
9827 /* Modify the original j to point here. */
9828 origfrag
->tc_frag_data
.slot_symbols
[0] = lsym
;
9829 origfrag
->tc_frag_data
.slot_offsets
[0] = tramp
->fr_fix
- 3;
9830 /* If trampoline is full, remove it from the list. */
9831 check_and_update_trampolines ();
9838 relax_frag_immed (segT segP
,
9845 bfd_boolean estimate_only
)
9849 bfd_boolean negatable_branch
= FALSE
;
9850 bfd_boolean branch_jmp_to_next
= FALSE
;
9851 bfd_boolean from_wide_insn
= FALSE
;
9852 xtensa_isa isa
= xtensa_default_isa
;
9854 offsetT frag_offset
;
9856 int num_text_bytes
, num_literal_bytes
;
9857 int literal_diff
, total_text_diff
, this_text_diff
;
9859 gas_assert (fragP
->fr_opcode
!= NULL
);
9861 xg_clear_vinsn (&cur_vinsn
);
9862 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9863 if (cur_vinsn
.num_slots
> 1)
9864 from_wide_insn
= TRUE
;
9866 tinsn
= cur_vinsn
.slots
[slot
];
9867 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9869 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9872 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9873 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9875 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9877 old_size
= xtensa_format_length (isa
, fmt
);
9879 /* Special case: replace a branch to the next instruction with a NOP.
9880 This is required to work around a hardware bug in T1040.0 and also
9881 serves as an optimization. */
9883 if (branch_jmp_to_next
9884 && ((old_size
== 2) || (old_size
== 3))
9885 && !next_frag_is_loop_target (fragP
))
9888 /* Here is the fun stuff: Get the immediate field from this
9889 instruction. If it fits, we are done. If not, find the next
9890 instruction sequence that fits. */
9892 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9893 istack_init (&istack
);
9894 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9895 min_steps
, stretch
);
9896 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9898 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9900 /* Figure out the number of bytes needed. */
9901 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9903 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9904 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9909 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9912 num_text_bytes
+= old_size
;
9913 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9914 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9917 /* The first instruction in the relaxed sequence will go after
9918 the current wide instruction, and thus its symbolic immediates
9921 istack_init (&istack
);
9922 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
9923 frag_offset
+ old_size
,
9924 min_steps
, stretch
+ old_size
);
9925 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9927 fragP
->tc_frag_data
.slot_subtypes
[slot
]
9928 = (int) RELAX_IMMED
+ num_steps
;
9930 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9932 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9934 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
9938 total_text_diff
= num_text_bytes
- old_size
;
9939 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9941 /* It MUST get larger. If not, we could get an infinite loop. */
9942 gas_assert (num_text_bytes
>= 0);
9943 gas_assert (literal_diff
>= 0);
9944 gas_assert (total_text_diff
>= 0);
9946 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9947 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9948 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9949 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9951 /* Find the associated expandable literal for this. */
9952 if (literal_diff
!= 0)
9954 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9957 gas_assert (literal_diff
== 4);
9958 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9960 /* We expect that the literal section state has NOT been
9962 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
9963 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9964 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9966 /* We need to mark this section for another iteration
9972 if (negatable_branch
&& istack
.ninsn
> 1)
9973 update_next_frag_state (fragP
);
9975 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
9976 if (istack
.ninsn
> 2 &&
9977 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
9978 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
9979 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
9981 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
9983 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
, total_text_diff
))
9985 struct trampoline_frag
*tf
= get_best_trampoline (jinsn
, fragP
);
9989 this_text_diff
+= init_trampoline_frag (tf
);
9990 this_text_diff
+= add_jump_to_trampoline (tf
, fragP
);
9994 /* If target symbol is undefined, assume it will reach once linked. */
9995 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
9997 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
9999 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10000 _("jump target out of range; no usable trampoline found"));
10006 return this_text_diff
;
10010 /* md_convert_frag Hook and Helper Functions. */
10012 static void convert_frag_align_next_opcode (fragS
*);
10013 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
10014 static void convert_frag_fill_nop (fragS
*);
10015 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
10018 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
10020 static xtensa_insnbuf vbuf
= NULL
;
10021 xtensa_isa isa
= xtensa_default_isa
;
10028 as_where (&file_name
, &line
);
10029 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
10031 switch (fragp
->fr_subtype
)
10033 case RELAX_ALIGN_NEXT_OPCODE
:
10034 /* Always convert. */
10035 convert_frag_align_next_opcode (fragp
);
10038 case RELAX_DESIRE_ALIGN
:
10039 /* Do nothing. If not aligned already, too bad. */
10042 case RELAX_LITERAL
:
10043 case RELAX_LITERAL_FINAL
:
10048 vbuf
= xtensa_insnbuf_alloc (isa
);
10050 xtensa_insnbuf_from_chars
10051 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
10052 fmt
= xtensa_format_decode (isa
, vbuf
);
10053 num_slots
= xtensa_format_num_slots (isa
, fmt
);
10055 for (slot
= 0; slot
< num_slots
; slot
++)
10057 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
10060 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
10064 case RELAX_IMMED_STEP1
:
10065 case RELAX_IMMED_STEP2
:
10066 case RELAX_IMMED_STEP3
:
10067 /* Place the immediate. */
10070 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
10075 /* This is OK because some slots could have
10076 relaxations and others have none. */
10082 case RELAX_UNREACHABLE
:
10083 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
10084 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
10085 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
10089 case RELAX_MAYBE_UNREACHABLE
:
10090 case RELAX_MAYBE_DESIRE_ALIGN
:
10094 case RELAX_FILL_NOP
:
10095 convert_frag_fill_nop (fragp
);
10098 case RELAX_LITERAL_NR
:
10099 if (use_literal_section
)
10101 /* This should have been handled during relaxation. When
10102 relaxing a code segment, literals sometimes need to be
10103 added to the corresponding literal segment. If that
10104 literal segment has already been relaxed, then we end up
10105 in this situation. Marking the literal segments as data
10106 would make this happen less often (since GAS always relaxes
10107 code before data), but we could still get into trouble if
10108 there are instructions in a segment that is not marked as
10109 containing code. Until we can implement a better solution,
10110 cheat and adjust the addresses of all the following frags.
10111 This could break subsequent alignments, but the linker's
10112 literal coalescing will do that anyway. */
10115 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
10116 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
10117 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
10118 fragp
->fr_var
-= 4;
10119 fragp
->fr_fix
+= 4;
10120 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
10121 f
->fr_address
+= 4;
10124 as_bad (_("invalid relaxation fragment result"));
10127 case RELAX_TRAMPOLINE
:
10132 new_logical_line (file_name
, line
);
10137 convert_frag_align_next_opcode (fragS
*fragp
)
10139 char *nop_buf
; /* Location for Writing. */
10140 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10141 addressT aligned_address
;
10143 int nop
, nop_count
;
10145 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10147 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10148 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10149 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10151 for (nop
= 0; nop
< nop_count
; nop
++)
10154 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
10156 assemble_nop (nop_size
, nop_buf
);
10157 nop_buf
+= nop_size
;
10160 fragp
->fr_fix
+= fill_size
;
10161 fragp
->fr_var
-= fill_size
;
10166 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10168 TInsn tinsn
, single_target
;
10169 int size
, old_size
, diff
;
10170 offsetT frag_offset
;
10172 gas_assert (slot
== 0);
10173 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10175 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10177 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10178 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10179 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10184 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10186 /* No conversion. */
10191 gas_assert (fragP
->fr_opcode
!= NULL
);
10193 /* Frags in this relaxation state should only contain
10194 single instruction bundles. */
10195 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10197 /* Just convert it to a wide form.... */
10199 old_size
= xg_get_single_size (tinsn
.opcode
);
10201 tinsn_init (&single_target
);
10202 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10204 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10206 as_bad (_("unable to widen instruction"));
10210 size
= xg_get_single_size (single_target
.opcode
);
10211 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10212 frag_offset
, TRUE
);
10214 diff
= size
- old_size
;
10215 gas_assert (diff
>= 0);
10216 gas_assert (diff
<= fragP
->fr_var
);
10217 fragP
->fr_var
-= diff
;
10218 fragP
->fr_fix
+= diff
;
10226 convert_frag_fill_nop (fragS
*fragP
)
10228 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10229 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10230 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10231 - fragP
->fr_address
- fragP
->fr_fix
));
10234 /* No conversion. */
10238 assemble_nop (size
, loc
);
10239 fragP
->tc_frag_data
.is_insn
= TRUE
;
10240 fragP
->fr_var
-= size
;
10241 fragP
->fr_fix
+= size
;
10246 static fixS
*fix_new_exp_in_seg
10247 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10248 bfd_reloc_code_real_type
);
10249 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
10252 convert_frag_immed (segT segP
,
10258 char *immed_instr
= fragP
->fr_opcode
;
10260 bfd_boolean expanded
= FALSE
;
10261 bfd_boolean branch_jmp_to_next
= FALSE
;
10262 char *fr_opcode
= fragP
->fr_opcode
;
10263 xtensa_isa isa
= xtensa_default_isa
;
10264 bfd_boolean from_wide_insn
= FALSE
;
10266 bfd_boolean is_loop
;
10268 gas_assert (fr_opcode
!= NULL
);
10270 xg_clear_vinsn (&cur_vinsn
);
10272 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10273 if (cur_vinsn
.num_slots
> 1)
10274 from_wide_insn
= TRUE
;
10276 orig_tinsn
= cur_vinsn
.slots
[slot
];
10277 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10279 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10281 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10282 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10284 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10286 /* Conversion just inserts a NOP and marks the fix as completed. */
10287 bytes
= xtensa_format_length (isa
, fmt
);
10290 cur_vinsn
.slots
[slot
].opcode
=
10291 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10292 cur_vinsn
.slots
[slot
].ntok
= 0;
10296 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10297 gas_assert (bytes
== 2 || bytes
== 3);
10298 build_nop (&cur_vinsn
.slots
[0], bytes
);
10299 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10301 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10302 xtensa_insnbuf_to_chars
10303 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10308 /* Here is the fun stuff: Get the immediate field from this
10309 instruction. If it fits, we're done. If not, find the next
10310 instruction sequence that fits. */
10314 symbolS
*lit_sym
= NULL
;
10315 int total_size
= 0;
10316 int target_offset
= 0;
10319 symbolS
*gen_label
= NULL
;
10320 offsetT frag_offset
;
10321 bfd_boolean first
= TRUE
;
10323 /* It does not fit. Find something that does and
10324 convert immediately. */
10325 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10326 istack_init (&istack
);
10327 xg_assembly_relax (&istack
, &orig_tinsn
,
10328 segP
, fragP
, frag_offset
, min_steps
, 0);
10330 old_size
= xtensa_format_length (isa
, fmt
);
10332 /* Assemble this right inline. */
10334 /* First, create the mapping from a label name to the REAL label. */
10336 for (i
= 0; i
< istack
.ninsn
; i
++)
10338 TInsn
*tinsn
= &istack
.insn
[i
];
10341 switch (tinsn
->insn_type
)
10343 case ITYPE_LITERAL
:
10344 if (lit_sym
!= NULL
)
10345 as_bad (_("multiple literals in expansion"));
10346 /* First find the appropriate space in the literal pool. */
10347 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10348 if (lit_frag
== NULL
)
10349 as_bad (_("no registered fragment for literal"));
10350 if (tinsn
->ntok
!= 1)
10351 as_bad (_("number of literal tokens != 1"));
10353 /* Set the literal symbol and add a fixup. */
10354 lit_sym
= lit_frag
->fr_symbol
;
10358 if (align_targets
&& !is_loop
)
10360 fragS
*unreach
= fragP
->fr_next
;
10361 while (!(unreach
->fr_type
== rs_machine_dependent
10362 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10363 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10365 unreach
= unreach
->fr_next
;
10368 gas_assert (unreach
->fr_type
== rs_machine_dependent
10369 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10370 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10372 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10374 gas_assert (gen_label
== NULL
);
10375 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10376 fr_opcode
- fragP
->fr_literal
10377 + target_offset
, fragP
);
10381 if (first
&& from_wide_insn
)
10383 target_offset
+= xtensa_format_length (isa
, fmt
);
10385 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10386 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10389 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10396 for (i
= 0; i
< istack
.ninsn
; i
++)
10398 TInsn
*tinsn
= &istack
.insn
[i
];
10402 bfd_reloc_code_real_type reloc_type
;
10404 switch (tinsn
->insn_type
)
10406 case ITYPE_LITERAL
:
10407 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10408 /* Already checked. */
10409 gas_assert (lit_frag
!= NULL
);
10410 gas_assert (lit_sym
!= NULL
);
10411 gas_assert (tinsn
->ntok
== 1);
10413 target_seg
= S_GET_SEGMENT (lit_sym
);
10414 gas_assert (target_seg
);
10415 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10416 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10417 &tinsn
->tok
[0], FALSE
, reloc_type
);
10424 xg_resolve_labels (tinsn
, gen_label
);
10425 xg_resolve_literals (tinsn
, lit_sym
);
10426 if (from_wide_insn
&& first
)
10429 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10431 cur_vinsn
.slots
[slot
] = *tinsn
;
10435 cur_vinsn
.slots
[slot
].opcode
=
10436 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10437 cur_vinsn
.slots
[slot
].ntok
= 0;
10439 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10440 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10441 (unsigned char *) immed_instr
, 0);
10442 fragP
->tc_frag_data
.is_insn
= TRUE
;
10443 size
= xtensa_format_length (isa
, fmt
);
10444 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10446 xg_emit_insn_to_buf
10447 (tinsn
, immed_instr
+ size
, fragP
,
10448 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10449 size
+= xg_get_single_size (tinsn
->opcode
);
10454 size
= xg_get_single_size (tinsn
->opcode
);
10455 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10456 immed_instr
- fragP
->fr_literal
, TRUE
);
10458 immed_instr
+= size
;
10459 total_size
+= size
;
10464 diff
= total_size
- old_size
;
10465 gas_assert (diff
>= 0);
10468 gas_assert (diff
<= fragP
->fr_var
);
10469 fragP
->fr_var
-= diff
;
10470 fragP
->fr_fix
+= diff
;
10473 /* Check for undefined immediates in LOOP instructions. */
10477 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10478 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10480 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10483 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10484 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10486 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10491 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10492 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10494 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10496 /* Add an expansion note on the expanded instruction. */
10497 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10498 &orig_tinsn
.tok
[0], TRUE
,
10499 BFD_RELOC_XTENSA_ASM_EXPAND
);
10504 /* Add a new fix expression into the desired segment. We have to
10505 switch to that segment to do this. */
10508 fix_new_exp_in_seg (segT new_seg
,
10509 subsegT new_subseg
,
10515 bfd_reloc_code_real_type r_type
)
10518 segT seg
= now_seg
;
10519 subsegT subseg
= now_subseg
;
10521 gas_assert (new_seg
!= 0);
10522 subseg_set (new_seg
, new_subseg
);
10524 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10525 subseg_set (seg
, subseg
);
10530 /* Relax a loop instruction so that it can span loop >256 bytes.
10536 addi as, as, lo8 (label-.L1)
10537 addmi as, as, mid8 (label-.L1)
10548 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
10553 unsigned long target
;
10554 static xtensa_insnbuf insnbuf
= NULL
;
10555 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10556 xtensa_isa isa
= xtensa_default_isa
;
10557 addressT loop_offset
;
10558 addressT addi_offset
= 9;
10559 addressT addmi_offset
= 12;
10564 insnbuf
= xtensa_insnbuf_alloc (isa
);
10566 /* Get the loop offset. */
10567 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10569 /* Validate that there really is a LOOP at the loop_offset. Because
10570 loops are not bundleable, we can assume that the instruction will be
10572 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10573 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10575 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10576 addi_offset
+= loop_offset
;
10577 addmi_offset
+= loop_offset
;
10579 gas_assert (tinsn
->ntok
== 2);
10580 if (tinsn
->tok
[1].X_op
== O_constant
)
10581 target
= tinsn
->tok
[1].X_add_number
;
10582 else if (tinsn
->tok
[1].X_op
== O_symbol
)
10584 /* Find the fragment. */
10585 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
10586 gas_assert (S_GET_SEGMENT (sym
) == segP
10587 || S_GET_SEGMENT (sym
) == absolute_section
);
10588 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
10592 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
10596 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
10597 loop_length_hi
= loop_length
& ~0x0ff;
10598 loop_length_lo
= loop_length
& 0x0ff;
10599 if (loop_length_lo
>= 128)
10601 loop_length_lo
-= 256;
10602 loop_length_hi
+= 256;
10605 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
10606 32512. If the loop is larger than that, then we just fail. */
10607 if (loop_length_hi
> 32512)
10608 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10609 _("loop too long for LOOP instruction"));
10611 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
10612 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
10614 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
10615 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
10617 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
10618 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
10620 fragP
->tc_frag_data
.is_insn
= TRUE
;
10621 xtensa_insnbuf_to_chars
10622 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
10624 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
10625 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
10626 xtensa_insnbuf_to_chars
10627 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
10629 /* Walk through all of the frags from here to the loop end
10630 and mark them as no_transform to keep them from being modified
10631 by the linker. If we ever have a relocation for the
10632 addi/addmi of the difference of two symbols we can remove this. */
10635 for (next_fragP
= fragP
; next_fragP
!= NULL
;
10636 next_fragP
= next_fragP
->fr_next
)
10638 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
10639 if (next_fragP
->tc_frag_data
.is_loop_target
)
10641 if (target_count
== 2)
10647 /* A map that keeps information on a per-subsegment basis. This is
10648 maintained during initial assembly, but is invalid once the
10649 subsegments are smashed together. I.E., it cannot be used during
10652 typedef struct subseg_map_struct
10660 float total_freq
; /* fall-through + branch target frequency */
10661 float target_freq
; /* branch target frequency alone */
10663 struct subseg_map_struct
*next
;
10667 static subseg_map
*sseg_map
= NULL
;
10669 static subseg_map
*
10670 get_subseg_info (segT seg
, subsegT subseg
)
10672 subseg_map
*subseg_e
;
10674 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
10676 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
10683 static subseg_map
*
10684 add_subseg_info (segT seg
, subsegT subseg
)
10686 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
10687 memset (subseg_e
, 0, sizeof (subseg_map
));
10688 subseg_e
->seg
= seg
;
10689 subseg_e
->subseg
= subseg
;
10690 subseg_e
->flags
= 0;
10691 /* Start off considering every branch target very important. */
10692 subseg_e
->target_freq
= 1.0;
10693 subseg_e
->total_freq
= 1.0;
10694 subseg_e
->next
= sseg_map
;
10695 sseg_map
= subseg_e
;
10701 get_last_insn_flags (segT seg
, subsegT subseg
)
10703 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10705 return subseg_e
->flags
;
10711 set_last_insn_flags (segT seg
,
10716 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10718 subseg_e
= add_subseg_info (seg
, subseg
);
10720 subseg_e
->flags
|= fl
;
10722 subseg_e
->flags
&= ~fl
;
10727 get_subseg_total_freq (segT seg
, subsegT subseg
)
10729 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10731 return subseg_e
->total_freq
;
10737 get_subseg_target_freq (segT seg
, subsegT subseg
)
10739 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10741 return subseg_e
->target_freq
;
10747 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
10749 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10751 subseg_e
= add_subseg_info (seg
, subseg
);
10752 subseg_e
->total_freq
= total_f
;
10753 subseg_e
->target_freq
= target_f
;
10757 /* Segment Lists and emit_state Stuff. */
10760 xtensa_move_seg_list_to_beginning (seg_list
*head
)
10765 segT literal_section
= head
->seg
;
10767 /* Move the literal section to the front of the section list. */
10768 gas_assert (literal_section
);
10769 if (literal_section
!= stdoutput
->sections
)
10771 bfd_section_list_remove (stdoutput
, literal_section
);
10772 bfd_section_list_prepend (stdoutput
, literal_section
);
10779 static void mark_literal_frags (seg_list
*);
10782 xtensa_move_literals (void)
10785 frchainS
*frchain_from
, *frchain_to
;
10786 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
10787 fragS
**frag_splice
;
10790 fixS
*fix
, *next_fix
, **fix_splice
;
10793 mark_literal_frags (literal_head
->next
);
10795 if (use_literal_section
)
10798 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
10800 /* Keep the literals for .init and .fini in separate sections. */
10801 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
10802 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
10805 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10806 search_frag
= frchain_from
->frch_root
;
10807 literal_pool
= NULL
;
10809 frag_splice
= &(frchain_from
->frch_root
);
10811 while (!search_frag
->tc_frag_data
.literal_frag
)
10813 gas_assert (search_frag
->fr_fix
== 0
10814 || search_frag
->fr_type
== rs_align
);
10815 search_frag
= search_frag
->fr_next
;
10818 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10819 == RELAX_LITERAL_POOL_BEGIN
);
10820 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10822 /* Make sure that all the frags in this series are closed, and
10823 that there is at least one left over of zero-size. This
10824 prevents us from making a segment with an frchain without any
10826 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10827 xtensa_set_frag_assembly_state (frag_now
);
10828 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10829 xtensa_set_frag_assembly_state (frag_now
);
10831 while (search_frag
!= frag_now
)
10833 next_frag
= search_frag
->fr_next
;
10835 /* First, move the frag out of the literal section and
10836 to the appropriate place. */
10837 if (search_frag
->tc_frag_data
.literal_frag
)
10839 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10840 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10841 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
10842 gas_assert (frchain_to
);
10844 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
10845 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
10847 *frag_splice
= next_frag
;
10848 search_frag
->fr_next
= insert_after
->fr_next
;
10849 insert_after
->fr_next
= search_frag
;
10850 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10851 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
10853 /* Now move any fixups associated with this frag to the
10855 fix
= frchain_from
->fix_root
;
10856 fix_splice
= &(frchain_from
->fix_root
);
10859 next_fix
= fix
->fx_next
;
10860 if (fix
->fx_frag
== search_frag
)
10862 *fix_splice
= next_fix
;
10863 fix
->fx_next
= frchain_to
->fix_root
;
10864 frchain_to
->fix_root
= fix
;
10865 if (frchain_to
->fix_tail
== NULL
)
10866 frchain_to
->fix_tail
= fix
;
10869 fix_splice
= &(fix
->fx_next
);
10872 search_frag
= next_frag
;
10875 if (frchain_from
->fix_root
!= NULL
)
10877 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10878 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10880 gas_assert (frchain_from
->fix_root
== NULL
);
10882 frchain_from
->fix_tail
= NULL
;
10883 xtensa_restore_emit_state (&state
);
10886 /* Now fix up the SEGMENT value for all the literal symbols. */
10887 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10889 symbolS
*lit_sym
= lit
->sym
;
10890 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10892 S_SET_SEGMENT (lit_sym
, dseg
);
10897 /* Walk over all the frags for segments in a list and mark them as
10898 containing literals. As clunky as this is, we can't rely on frag_var
10899 and frag_variant to get called in all situations. */
10902 mark_literal_frags (seg_list
*segment
)
10904 frchainS
*frchain_from
;
10905 fragS
*search_frag
;
10909 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10910 search_frag
= frchain_from
->frch_root
;
10911 while (search_frag
)
10913 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10914 search_frag
= search_frag
->fr_next
;
10916 segment
= segment
->next
;
10922 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10924 /* Move all of the sections in the section list to come
10925 after "after" in the gnu segment list. */
10930 segT literal_section
= head
->seg
;
10932 /* Move the literal section after "after". */
10933 gas_assert (literal_section
);
10934 if (literal_section
!= after
)
10936 bfd_section_list_remove (stdoutput
, literal_section
);
10937 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10945 /* Push all the literal segments to the end of the gnu list. */
10948 xtensa_reorder_segments (void)
10955 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10961 /* Now that we have the last section, push all the literal
10962 sections to the end. */
10963 xtensa_reorder_seg_list (literal_head
, last_sec
);
10965 /* Now perform the final error check. */
10966 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10968 gas_assert (new_count
== old_count
);
10972 /* Change the emit state (seg, subseg, and frag related stuff) to the
10973 correct location. Return a emit_state which can be passed to
10974 xtensa_restore_emit_state to return to current fragment. */
10977 xtensa_switch_to_literal_fragment (emit_state
*result
)
10979 if (directive_state
[directive_absolute_literals
])
10981 segT lit4_seg
= cache_literal_section (TRUE
);
10982 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10985 xtensa_switch_to_non_abs_literal_fragment (result
);
10987 /* Do a 4-byte align here. */
10988 frag_align (2, 0, 0);
10989 record_alignment (now_seg
, 2);
10994 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10996 static bfd_boolean recursive
= FALSE
;
10997 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10999 bfd_boolean is_init
=
11000 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
11001 bfd_boolean is_fini
=
11002 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
11004 if (pool_location
== NULL
11005 && !use_literal_section
11007 && !is_init
&& ! is_fini
)
11009 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11011 /* When we mark a literal pool location, we want to put a frag in
11012 the literal pool that points to it. But to do that, we want to
11013 switch_to_literal_fragment. But literal sections don't have
11014 literal pools, so their location is always null, so we would
11015 recurse forever. This is kind of hacky, but it works. */
11018 xtensa_mark_literal_pool_location ();
11022 lit_seg
= cache_literal_section (FALSE
);
11023 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
11025 if (!use_literal_section
11026 && !is_init
&& !is_fini
11027 && get_literal_pool_location (now_seg
) != pool_location
)
11029 /* Close whatever frag is there. */
11030 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11031 xtensa_set_frag_assembly_state (frag_now
);
11032 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
11033 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11034 xtensa_set_frag_assembly_state (frag_now
);
11039 /* Call this function before emitting data into the literal section.
11040 This is a helper function for xtensa_switch_to_literal_fragment.
11041 This is similar to a .section new_now_seg subseg. */
11044 xtensa_switch_section_emit_state (emit_state
*state
,
11046 subsegT new_now_subseg
)
11048 state
->name
= now_seg
->name
;
11049 state
->now_seg
= now_seg
;
11050 state
->now_subseg
= now_subseg
;
11051 state
->generating_literals
= generating_literals
;
11052 generating_literals
++;
11053 subseg_set (new_now_seg
, new_now_subseg
);
11057 /* Use to restore the emitting into the normal place. */
11060 xtensa_restore_emit_state (emit_state
*state
)
11062 generating_literals
= state
->generating_literals
;
11063 subseg_set (state
->now_seg
, state
->now_subseg
);
11067 /* Predicate function used to look up a section in a particular group. */
11070 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
11072 const char *gname
= inf
;
11073 const char *group_name
= elf_group_name (sec
);
11075 return (group_name
== gname
11076 || (group_name
!= NULL
11078 && strcmp (group_name
, gname
) == 0));
11082 /* Get the literal section to be used for the current text section.
11083 The result may be cached in the default_lit_sections structure. */
11086 cache_literal_section (bfd_boolean use_abs_literals
)
11088 const char *text_name
, *group_name
= 0;
11089 char *base_name
, *name
, *suffix
;
11091 segT seg
, current_section
;
11092 int current_subsec
;
11093 bfd_boolean linkonce
= FALSE
;
11095 /* Save the current section/subsection. */
11096 current_section
= now_seg
;
11097 current_subsec
= now_subseg
;
11099 /* Clear the cached values if they are no longer valid. */
11100 if (now_seg
!= default_lit_sections
.current_text_seg
)
11102 default_lit_sections
.current_text_seg
= now_seg
;
11103 default_lit_sections
.lit_seg
= NULL
;
11104 default_lit_sections
.lit4_seg
= NULL
;
11107 /* Check if the literal section is already cached. */
11108 if (use_abs_literals
)
11109 pcached
= &default_lit_sections
.lit4_seg
;
11111 pcached
= &default_lit_sections
.lit_seg
;
11116 text_name
= default_lit_sections
.lit_prefix
;
11117 if (! text_name
|| ! *text_name
)
11119 text_name
= segment_name (current_section
);
11120 group_name
= elf_group_name (current_section
);
11121 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
11124 base_name
= use_abs_literals
? ".lit4" : ".literal";
11127 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
11128 sprintf (name
, "%s.%s", base_name
, group_name
);
11130 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
11132 suffix
= strchr (text_name
+ linkonce_len
, '.');
11134 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
11135 + (suffix
? strlen (suffix
) : 0));
11136 strcpy (name
, ".gnu.linkonce");
11137 strcat (name
, base_name
);
11139 strcat (name
, suffix
);
11144 /* If the section name begins or ends with ".text", then replace
11145 that portion instead of appending an additional suffix. */
11146 size_t len
= strlen (text_name
);
11148 && (strcmp (text_name
+ len
- 5, ".text") == 0
11149 || strncmp (text_name
, ".text", 5) == 0))
11152 name
= xmalloc (len
+ strlen (base_name
) + 1);
11153 if (strncmp (text_name
, ".text", 5) == 0)
11155 strcpy (name
, base_name
);
11156 strcat (name
, text_name
+ 5);
11160 strcpy (name
, text_name
);
11161 strcpy (name
+ len
, base_name
);
11165 /* Canonicalize section names to allow renaming literal sections.
11166 The group name, if any, came from the current text section and
11167 has already been canonicalized. */
11168 name
= tc_canonicalize_symbol_name (name
);
11170 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11171 (void *) group_name
);
11176 seg
= subseg_force_new (name
, 0);
11178 if (! use_abs_literals
)
11180 /* Add the newly created literal segment to the list. */
11181 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
11183 n
->next
= literal_head
->next
;
11184 literal_head
->next
= n
;
11187 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11188 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11189 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11191 elf_group_name (seg
) = group_name
;
11193 bfd_set_section_flags (stdoutput
, seg
, flags
);
11194 bfd_set_section_alignment (stdoutput
, seg
, 2);
11198 subseg_set (current_section
, current_subsec
);
11203 /* Property Tables Stuff. */
11205 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11206 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11207 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11209 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11210 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11212 static bfd_boolean
get_frag_is_literal (const fragS
*);
11213 static void xtensa_create_property_segments
11214 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11215 static void xtensa_create_xproperty_segments
11216 (frag_flags_fn
, const char *, xt_section_type
);
11217 static bfd_boolean
exclude_section_from_property_tables (segT
);
11218 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11219 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11220 static void add_xt_block_frags
11221 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11222 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11223 static void xtensa_frag_flags_init (frag_flags
*);
11224 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11225 static flagword
frag_flags_to_number (const frag_flags
*);
11226 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11228 /* Set up property tables after relaxation. */
11231 xtensa_post_relax_hook (void)
11233 xtensa_move_seg_list_to_beginning (literal_head
);
11235 xtensa_find_unmarked_state_frags ();
11236 xtensa_mark_frags_for_org ();
11237 xtensa_mark_difference_of_two_symbols ();
11239 xtensa_create_property_segments (get_frag_is_literal
,
11241 XTENSA_LIT_SEC_NAME
,
11243 xtensa_create_xproperty_segments (get_frag_property_flags
,
11244 XTENSA_PROP_SEC_NAME
,
11247 if (warn_unaligned_branch_targets
)
11248 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11249 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11253 /* This function is only meaningful after xtensa_move_literals. */
11256 get_frag_is_literal (const fragS
*fragP
)
11258 gas_assert (fragP
!= NULL
);
11259 return fragP
->tc_frag_data
.is_literal
;
11264 xtensa_create_property_segments (frag_predicate property_function
,
11265 frag_predicate end_property_function
,
11266 const char *section_name_base
,
11267 xt_section_type sec_type
)
11271 /* Walk over all of the current segments.
11272 Walk over each fragment
11273 For each non-empty fragment,
11274 Build a property record (append where possible). */
11276 for (seclist
= &stdoutput
->sections
;
11277 seclist
&& *seclist
;
11278 seclist
= &(*seclist
)->next
)
11280 segT sec
= *seclist
;
11282 if (exclude_section_from_property_tables (sec
))
11285 if (section_has_property (sec
, property_function
))
11287 segment_info_type
*xt_seg_info
;
11288 xtensa_block_info
**xt_blocks
;
11289 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11291 prop_sec
->output_section
= prop_sec
;
11292 subseg_set (prop_sec
, 0);
11293 xt_seg_info
= seg_info (prop_sec
);
11294 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11296 /* Walk over all of the frchains here and add new sections. */
11297 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11298 end_property_function
);
11302 /* Now we fill them out.... */
11304 for (seclist
= &stdoutput
->sections
;
11305 seclist
&& *seclist
;
11306 seclist
= &(*seclist
)->next
)
11308 segment_info_type
*seginfo
;
11309 xtensa_block_info
*block
;
11310 segT sec
= *seclist
;
11312 seginfo
= seg_info (sec
);
11313 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11317 xtensa_block_info
*cur_block
;
11319 bfd_size_type rec_size
;
11321 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11324 rec_size
= num_recs
* 8;
11325 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11332 subseg_set (sec
, 0);
11333 frag_data
= frag_more (rec_size
);
11335 for (i
= 0; i
< num_recs
; i
++)
11339 /* Write the fixup. */
11340 gas_assert (cur_block
);
11341 fix
= fix_new (frag_now
, i
* 8, 4,
11342 section_symbol (cur_block
->sec
),
11344 FALSE
, BFD_RELOC_32
);
11345 fix
->fx_file
= "<internal>";
11348 /* Write the length. */
11349 md_number_to_chars (&frag_data
[4 + i
* 8],
11350 cur_block
->size
, 4);
11351 cur_block
= cur_block
->next
;
11353 frag_wane (frag_now
);
11355 frag_wane (frag_now
);
11363 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11364 const char *section_name_base
,
11365 xt_section_type sec_type
)
11369 /* Walk over all of the current segments.
11370 Walk over each fragment.
11371 For each fragment that has instructions,
11372 build an instruction record (append where possible). */
11374 for (seclist
= &stdoutput
->sections
;
11375 seclist
&& *seclist
;
11376 seclist
= &(*seclist
)->next
)
11378 segT sec
= *seclist
;
11380 if (exclude_section_from_property_tables (sec
))
11383 if (section_has_xproperty (sec
, flag_fn
))
11385 segment_info_type
*xt_seg_info
;
11386 xtensa_block_info
**xt_blocks
;
11387 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11389 prop_sec
->output_section
= prop_sec
;
11390 subseg_set (prop_sec
, 0);
11391 xt_seg_info
= seg_info (prop_sec
);
11392 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11394 /* Walk over all of the frchains here and add new sections. */
11395 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11399 /* Now we fill them out.... */
11401 for (seclist
= &stdoutput
->sections
;
11402 seclist
&& *seclist
;
11403 seclist
= &(*seclist
)->next
)
11405 segment_info_type
*seginfo
;
11406 xtensa_block_info
*block
;
11407 segT sec
= *seclist
;
11409 seginfo
= seg_info (sec
);
11410 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11414 xtensa_block_info
*cur_block
;
11416 bfd_size_type rec_size
;
11418 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11421 rec_size
= num_recs
* (8 + 4);
11422 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11423 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11430 subseg_set (sec
, 0);
11431 frag_data
= frag_more (rec_size
);
11433 for (i
= 0; i
< num_recs
; i
++)
11437 /* Write the fixup. */
11438 gas_assert (cur_block
);
11439 fix
= fix_new (frag_now
, i
* 12, 4,
11440 section_symbol (cur_block
->sec
),
11442 FALSE
, BFD_RELOC_32
);
11443 fix
->fx_file
= "<internal>";
11446 /* Write the length. */
11447 md_number_to_chars (&frag_data
[4 + i
* 12],
11448 cur_block
->size
, 4);
11449 md_number_to_chars (&frag_data
[8 + i
* 12],
11450 frag_flags_to_number (&cur_block
->flags
),
11451 sizeof (flagword
));
11452 cur_block
= cur_block
->next
;
11454 frag_wane (frag_now
);
11456 frag_wane (frag_now
);
11464 exclude_section_from_property_tables (segT sec
)
11466 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
11468 /* Sections that don't contribute to the memory footprint are excluded. */
11469 if ((flags
& SEC_DEBUGGING
)
11470 || !(flags
& SEC_ALLOC
)
11471 || (flags
& SEC_MERGE
))
11474 /* Linker cie and fde optimizations mess up property entries for
11475 eh_frame sections, but there is nothing inside them relevant to
11476 property tables anyway. */
11477 if (strcmp (sec
->name
, ".eh_frame") == 0)
11485 section_has_property (segT sec
, frag_predicate property_function
)
11487 segment_info_type
*seginfo
= seg_info (sec
);
11490 if (seginfo
&& seginfo
->frchainP
)
11492 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11494 if (property_function (fragP
)
11495 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11504 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
11506 segment_info_type
*seginfo
= seg_info (sec
);
11509 if (seginfo
&& seginfo
->frchainP
)
11511 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11513 frag_flags prop_flags
;
11514 property_function (fragP
, &prop_flags
);
11515 if (!xtensa_frag_flags_is_empty (&prop_flags
))
11523 /* Two types of block sections exist right now: literal and insns. */
11526 add_xt_block_frags (segT sec
,
11527 xtensa_block_info
**xt_block
,
11528 frag_predicate property_function
,
11529 frag_predicate end_property_function
)
11533 /* Build it if needed. */
11534 while (*xt_block
!= NULL
)
11535 xt_block
= &(*xt_block
)->next
;
11536 /* We are either at NULL at the beginning or at the end. */
11538 /* Walk through the frags. */
11539 if (seg_info (sec
)->frchainP
)
11541 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
11543 fragP
= fragP
->fr_next
)
11545 if (property_function (fragP
)
11546 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11548 if (*xt_block
!= NULL
)
11550 if ((*xt_block
)->offset
+ (*xt_block
)->size
11551 == fragP
->fr_address
)
11552 (*xt_block
)->size
+= fragP
->fr_fix
;
11554 xt_block
= &((*xt_block
)->next
);
11556 if (*xt_block
== NULL
)
11558 xtensa_block_info
*new_block
= (xtensa_block_info
*)
11559 xmalloc (sizeof (xtensa_block_info
));
11560 new_block
->sec
= sec
;
11561 new_block
->offset
= fragP
->fr_address
;
11562 new_block
->size
= fragP
->fr_fix
;
11563 new_block
->next
= NULL
;
11564 xtensa_frag_flags_init (&new_block
->flags
);
11565 *xt_block
= new_block
;
11567 if (end_property_function
11568 && end_property_function (fragP
))
11570 xt_block
= &((*xt_block
)->next
);
11578 /* Break the encapsulation of add_xt_prop_frags here. */
11581 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
11583 if (prop_flags
->is_literal
11584 || prop_flags
->is_insn
11585 || prop_flags
->is_data
11586 || prop_flags
->is_unreachable
)
11593 xtensa_frag_flags_init (frag_flags
*prop_flags
)
11595 memset (prop_flags
, 0, sizeof (frag_flags
));
11600 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
11602 xtensa_frag_flags_init (prop_flags
);
11603 if (fragP
->tc_frag_data
.is_literal
)
11604 prop_flags
->is_literal
= TRUE
;
11605 if (fragP
->tc_frag_data
.is_specific_opcode
11606 || fragP
->tc_frag_data
.is_no_transform
)
11608 prop_flags
->is_no_transform
= TRUE
;
11609 if (xtensa_frag_flags_is_empty (prop_flags
))
11610 prop_flags
->is_data
= TRUE
;
11612 if (fragP
->tc_frag_data
.is_unreachable
)
11613 prop_flags
->is_unreachable
= TRUE
;
11614 else if (fragP
->tc_frag_data
.is_insn
)
11616 prop_flags
->is_insn
= TRUE
;
11617 if (fragP
->tc_frag_data
.is_loop_target
)
11618 prop_flags
->insn
.is_loop_target
= TRUE
;
11619 if (fragP
->tc_frag_data
.is_branch_target
)
11620 prop_flags
->insn
.is_branch_target
= TRUE
;
11621 if (fragP
->tc_frag_data
.is_no_density
)
11622 prop_flags
->insn
.is_no_density
= TRUE
;
11623 if (fragP
->tc_frag_data
.use_absolute_literals
)
11624 prop_flags
->insn
.is_abslit
= TRUE
;
11626 if (fragP
->tc_frag_data
.is_align
)
11628 prop_flags
->is_align
= TRUE
;
11629 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
11630 if (xtensa_frag_flags_is_empty (prop_flags
))
11631 prop_flags
->is_data
= TRUE
;
11637 frag_flags_to_number (const frag_flags
*prop_flags
)
11640 if (prop_flags
->is_literal
)
11641 num
|= XTENSA_PROP_LITERAL
;
11642 if (prop_flags
->is_insn
)
11643 num
|= XTENSA_PROP_INSN
;
11644 if (prop_flags
->is_data
)
11645 num
|= XTENSA_PROP_DATA
;
11646 if (prop_flags
->is_unreachable
)
11647 num
|= XTENSA_PROP_UNREACHABLE
;
11648 if (prop_flags
->insn
.is_loop_target
)
11649 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
11650 if (prop_flags
->insn
.is_branch_target
)
11652 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
11653 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
11656 if (prop_flags
->insn
.is_no_density
)
11657 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
11658 if (prop_flags
->is_no_transform
)
11659 num
|= XTENSA_PROP_NO_TRANSFORM
;
11660 if (prop_flags
->insn
.is_no_reorder
)
11661 num
|= XTENSA_PROP_INSN_NO_REORDER
;
11662 if (prop_flags
->insn
.is_abslit
)
11663 num
|= XTENSA_PROP_INSN_ABSLIT
;
11665 if (prop_flags
->is_align
)
11667 num
|= XTENSA_PROP_ALIGN
;
11668 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
11676 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
11677 const frag_flags
*prop_flags_2
)
11679 /* Cannot combine with an end marker. */
11681 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
11683 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
11685 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
11688 if (prop_flags_1
->is_insn
)
11690 /* Properties of the beginning of the frag. */
11691 if (prop_flags_2
->insn
.is_loop_target
)
11693 if (prop_flags_2
->insn
.is_branch_target
)
11695 if (prop_flags_1
->insn
.is_no_density
!=
11696 prop_flags_2
->insn
.is_no_density
)
11698 if (prop_flags_1
->is_no_transform
!=
11699 prop_flags_2
->is_no_transform
)
11701 if (prop_flags_1
->insn
.is_no_reorder
!=
11702 prop_flags_2
->insn
.is_no_reorder
)
11704 if (prop_flags_1
->insn
.is_abslit
!=
11705 prop_flags_2
->insn
.is_abslit
)
11709 if (prop_flags_1
->is_align
)
11717 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
11720 unsigned align_bits
;
11722 if (!xt_block
->flags
.is_align
)
11723 return xt_block
->size
;
11725 end_addr
= xt_block
->offset
+ xt_block
->size
;
11726 align_bits
= xt_block
->flags
.alignment
;
11727 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
11728 return end_addr
- xt_block
->offset
;
11733 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
11734 const xtensa_block_info
*xt_block_2
)
11736 if (xt_block
->sec
!= xt_block_2
->sec
)
11738 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
11739 != xt_block_2
->offset
)
11742 if (xt_block_2
->size
== 0
11743 && (!xt_block_2
->flags
.is_unreachable
11744 || xt_block
->flags
.is_unreachable
))
11746 if (xt_block_2
->flags
.is_align
11747 && xt_block
->flags
.is_align
)
11749 /* Nothing needed. */
11750 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11755 if (xt_block_2
->flags
.is_align
)
11757 /* Push alignment to previous entry. */
11758 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11759 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11764 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11765 &xt_block_2
->flags
))
11768 xt_block
->size
+= xt_block_2
->size
;
11770 if (xt_block_2
->flags
.is_align
)
11772 xt_block
->flags
.is_align
= TRUE
;
11773 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11781 add_xt_prop_frags (segT sec
,
11782 xtensa_block_info
**xt_block
,
11783 frag_flags_fn property_function
)
11787 /* Build it if needed. */
11788 while (*xt_block
!= NULL
)
11790 xt_block
= &(*xt_block
)->next
;
11792 /* We are either at NULL at the beginning or at the end. */
11794 /* Walk through the frags. */
11795 if (seg_info (sec
)->frchainP
)
11797 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
11798 fragP
= fragP
->fr_next
)
11800 xtensa_block_info tmp_block
;
11801 tmp_block
.sec
= sec
;
11802 tmp_block
.offset
= fragP
->fr_address
;
11803 tmp_block
.size
= fragP
->fr_fix
;
11804 tmp_block
.next
= NULL
;
11805 property_function (fragP
, &tmp_block
.flags
);
11807 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11808 /* && fragP->fr_fix != 0) */
11810 if ((*xt_block
) == NULL
11811 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11813 xtensa_block_info
*new_block
;
11814 if ((*xt_block
) != NULL
)
11815 xt_block
= &(*xt_block
)->next
;
11816 new_block
= (xtensa_block_info
*)
11817 xmalloc (sizeof (xtensa_block_info
));
11818 *new_block
= tmp_block
;
11819 *xt_block
= new_block
;
11827 /* op_placement_info_table */
11829 /* op_placement_info makes it easier to determine which
11830 ops can go in which slots. */
11833 init_op_placement_info_table (void)
11835 xtensa_isa isa
= xtensa_default_isa
;
11836 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11837 xtensa_opcode opcode
;
11840 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11842 op_placement_table
= (op_placement_info_table
)
11843 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11844 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11846 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11848 op_placement_info
*opi
= &op_placement_table
[opcode
];
11849 /* FIXME: Make tinsn allocation dynamic. */
11850 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
11851 as_fatal (_("too many operands in instruction"));
11852 opi
->narrowest
= XTENSA_UNDEFINED
;
11853 opi
->narrowest_size
= 0x7F;
11854 opi
->narrowest_slot
= 0;
11856 opi
->num_formats
= 0;
11858 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11860 opi
->slots
[fmt
] = 0;
11861 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11863 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11865 int fmt_length
= xtensa_format_length (isa
, fmt
);
11867 set_bit (fmt
, opi
->formats
);
11868 set_bit (slot
, opi
->slots
[fmt
]);
11869 if (fmt_length
< opi
->narrowest_size
11870 || (fmt_length
== opi
->narrowest_size
11871 && (xtensa_format_num_slots (isa
, fmt
)
11872 < xtensa_format_num_slots (isa
,
11875 opi
->narrowest
= fmt
;
11876 opi
->narrowest_size
= fmt_length
;
11877 opi
->narrowest_slot
= slot
;
11882 opi
->num_formats
++;
11885 xtensa_insnbuf_free (isa
, ibuf
);
11890 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11892 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11896 /* If the opcode is available in a single slot format, return its size. */
11899 xg_get_single_size (xtensa_opcode opcode
)
11901 return op_placement_table
[opcode
].narrowest_size
;
11905 static xtensa_format
11906 xg_get_single_format (xtensa_opcode opcode
)
11908 return op_placement_table
[opcode
].narrowest
;
11913 xg_get_single_slot (xtensa_opcode opcode
)
11915 return op_placement_table
[opcode
].narrowest_slot
;
11919 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11922 istack_init (IStack
*stack
)
11929 istack_empty (IStack
*stack
)
11931 return (stack
->ninsn
== 0);
11936 istack_full (IStack
*stack
)
11938 return (stack
->ninsn
== MAX_ISTACK
);
11942 /* Return a pointer to the top IStack entry.
11943 It is an error to call this if istack_empty () is TRUE. */
11946 istack_top (IStack
*stack
)
11948 int rec
= stack
->ninsn
- 1;
11949 gas_assert (!istack_empty (stack
));
11950 return &stack
->insn
[rec
];
11954 /* Add a new TInsn to an IStack.
11955 It is an error to call this if istack_full () is TRUE. */
11958 istack_push (IStack
*stack
, TInsn
*insn
)
11960 int rec
= stack
->ninsn
;
11961 gas_assert (!istack_full (stack
));
11962 stack
->insn
[rec
] = *insn
;
11967 /* Clear space for the next TInsn on the IStack and return a pointer
11968 to it. It is an error to call this if istack_full () is TRUE. */
11971 istack_push_space (IStack
*stack
)
11973 int rec
= stack
->ninsn
;
11975 gas_assert (!istack_full (stack
));
11976 insn
= &stack
->insn
[rec
];
11983 /* Remove the last pushed instruction. It is an error to call this if
11984 istack_empty () returns TRUE. */
11987 istack_pop (IStack
*stack
)
11989 int rec
= stack
->ninsn
- 1;
11990 gas_assert (!istack_empty (stack
));
11992 tinsn_init (&stack
->insn
[rec
]);
11996 /* TInsn functions. */
11999 tinsn_init (TInsn
*dst
)
12001 memset (dst
, 0, sizeof (TInsn
));
12005 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12008 tinsn_has_symbolic_operands (const TInsn
*insn
)
12011 int n
= insn
->ntok
;
12013 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12015 for (i
= 0; i
< n
; ++i
)
12017 switch (insn
->tok
[i
].X_op
)
12031 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
12033 xtensa_isa isa
= xtensa_default_isa
;
12035 int n
= insn
->ntok
;
12037 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12039 for (i
= 0; i
< n
; ++i
)
12041 switch (insn
->tok
[i
].X_op
)
12049 /* Errors for these types are caught later. */
12054 /* Symbolic immediates are only allowed on the last immediate
12055 operand. At this time, CONST16 is the only opcode where we
12056 support non-PC-relative relocations. */
12057 if (i
!= get_relaxable_immed (insn
->opcode
)
12058 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12059 && insn
->opcode
!= xtensa_const16_opcode
))
12061 as_bad (_("invalid symbolic operand"));
12070 /* For assembly code with complex expressions (e.g. subtraction),
12071 we have to build them in the literal pool so that
12072 their results are calculated correctly after relaxation.
12073 The relaxation only handles expressions that
12074 boil down to SYMBOL + OFFSET. */
12077 tinsn_has_complex_operands (const TInsn
*insn
)
12080 int n
= insn
->ntok
;
12081 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12082 for (i
= 0; i
< n
; ++i
)
12084 switch (insn
->tok
[i
].X_op
)
12100 /* Encode a TInsn opcode and its constant operands into slotbuf.
12101 Return TRUE if there is a symbol in the immediate field. This
12102 function assumes that:
12103 1) The number of operands are correct.
12104 2) The insn_type is ITYPE_INSN.
12105 3) The opcode can be encoded in the specified format and slot.
12106 4) Operands are either O_constant or O_symbol, and all constants fit. */
12109 tinsn_to_slotbuf (xtensa_format fmt
,
12112 xtensa_insnbuf slotbuf
)
12114 xtensa_isa isa
= xtensa_default_isa
;
12115 xtensa_opcode opcode
= tinsn
->opcode
;
12116 bfd_boolean has_fixup
= FALSE
;
12117 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12120 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
12121 if (noperands
!= tinsn
->ntok
)
12122 as_fatal (_("operand number mismatch"));
12124 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12126 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12127 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12131 for (i
= 0; i
< noperands
; i
++)
12133 expressionS
*exp
= &tinsn
->tok
[i
];
12142 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12144 /* The register number has already been checked in
12145 expression_maybe_register, so we don't need to check here. */
12146 opnd_value
= exp
->X_add_number
;
12147 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12148 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12151 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12155 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12157 as_where (&file_name
, &line
);
12158 /* It is a constant and we called this function
12159 then we have to try to fit it. */
12160 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12161 exp
->X_add_number
, file_name
, line
);
12174 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12175 into a multi-slot instruction, fill the other slots with NOPs.
12176 Return TRUE if there is a symbol in the immediate field. See also the
12177 assumptions listed for tinsn_to_slotbuf. */
12180 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12182 static xtensa_insnbuf slotbuf
= 0;
12183 static vliw_insn vinsn
;
12184 xtensa_isa isa
= xtensa_default_isa
;
12185 bfd_boolean has_fixup
= FALSE
;
12190 slotbuf
= xtensa_insnbuf_alloc (isa
);
12191 xg_init_vinsn (&vinsn
);
12194 xg_clear_vinsn (&vinsn
);
12196 bundle_tinsn (tinsn
, &vinsn
);
12198 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12200 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12202 /* Only one slot may have a fix-up because the rest contains NOPs. */
12204 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12205 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12212 /* Check the instruction arguments. Return TRUE on failure. */
12215 tinsn_check_arguments (const TInsn
*insn
)
12217 xtensa_isa isa
= xtensa_default_isa
;
12218 xtensa_opcode opcode
= insn
->opcode
;
12219 xtensa_regfile t1_regfile
, t2_regfile
;
12220 int t1_reg
, t2_reg
;
12221 int t1_base_reg
, t1_last_reg
;
12222 int t2_base_reg
, t2_last_reg
;
12223 char t1_inout
, t2_inout
;
12226 if (opcode
== XTENSA_UNDEFINED
)
12228 as_bad (_("invalid opcode"));
12232 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12234 as_bad (_("too few operands"));
12238 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12240 as_bad (_("too many operands"));
12244 /* Check registers. */
12245 for (j
= 0; j
< insn
->ntok
; j
++)
12247 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12250 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12251 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12253 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12255 for (i
= 0; i
< insn
->ntok
; i
++)
12260 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12263 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12265 if (t1_regfile
!= t2_regfile
)
12268 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12269 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12271 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12272 t1_last_reg
= (t1_base_reg
12273 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12275 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12277 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12279 if (t1_reg
!= t2_reg
)
12282 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12284 as_bad (_("multiple writes to the same register"));
12295 /* Load an instruction from its encoded form. */
12298 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12302 xg_init_vinsn (&vinsn
);
12303 vinsn_from_chars (&vinsn
, f
);
12305 *tinsn
= vinsn
.slots
[slot
];
12306 xg_free_vinsn (&vinsn
);
12311 tinsn_from_insnbuf (TInsn
*tinsn
,
12312 xtensa_insnbuf slotbuf
,
12317 xtensa_isa isa
= xtensa_default_isa
;
12319 /* Find the immed. */
12320 tinsn_init (tinsn
);
12321 tinsn
->insn_type
= ITYPE_INSN
;
12322 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12323 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12324 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12325 for (i
= 0; i
< tinsn
->ntok
; i
++)
12327 set_expr_const (&tinsn
->tok
[i
],
12328 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12329 tinsn
->opcode
, i
));
12334 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12337 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12339 xtensa_opcode opcode
= tinsn
->opcode
;
12342 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12344 opnum
= get_relaxable_immed (opcode
);
12345 gas_assert (opnum
>= 0);
12346 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12347 fragP
->tc_frag_data
.slot_symbols
[slot
],
12348 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12350 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12355 get_num_stack_text_bytes (IStack
*istack
)
12358 int text_bytes
= 0;
12360 for (i
= 0; i
< istack
->ninsn
; i
++)
12362 TInsn
*tinsn
= &istack
->insn
[i
];
12363 if (tinsn
->insn_type
== ITYPE_INSN
)
12364 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12371 get_num_stack_literal_bytes (IStack
*istack
)
12376 for (i
= 0; i
< istack
->ninsn
; i
++)
12378 TInsn
*tinsn
= &istack
->insn
[i
];
12379 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12386 /* vliw_insn functions. */
12389 xg_init_vinsn (vliw_insn
*v
)
12392 xtensa_isa isa
= xtensa_default_isa
;
12394 xg_clear_vinsn (v
);
12396 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12397 if (v
->insnbuf
== NULL
)
12398 as_fatal (_("out of memory"));
12400 for (i
= 0; i
< config_max_slots
; i
++)
12402 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12403 if (v
->slotbuf
[i
] == NULL
)
12404 as_fatal (_("out of memory"));
12410 xg_clear_vinsn (vliw_insn
*v
)
12414 memset (v
, 0, offsetof (vliw_insn
, slots
)
12415 + sizeof(TInsn
) * config_max_slots
);
12417 v
->format
= XTENSA_UNDEFINED
;
12419 v
->inside_bundle
= FALSE
;
12421 if (xt_saved_debug_type
!= DEBUG_NONE
)
12422 debug_type
= xt_saved_debug_type
;
12424 for (i
= 0; i
< config_max_slots
; i
++)
12425 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12430 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
12433 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
12434 dst
->insnbuf
= src
->insnbuf
;
12435 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
12440 vinsn_has_specific_opcodes (vliw_insn
*v
)
12444 for (i
= 0; i
< v
->num_slots
; i
++)
12446 if (v
->slots
[i
].is_specific_opcode
)
12454 xg_free_vinsn (vliw_insn
*v
)
12457 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
12458 for (i
= 0; i
< config_max_slots
; i
++)
12459 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
12463 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
12464 operands. See also the assumptions listed for tinsn_to_slotbuf. */
12467 vinsn_to_insnbuf (vliw_insn
*vinsn
,
12470 bfd_boolean record_fixup
)
12472 xtensa_isa isa
= xtensa_default_isa
;
12473 xtensa_format fmt
= vinsn
->format
;
12474 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
12476 bfd_boolean has_fixup
= FALSE
;
12478 xtensa_format_encode (isa
, fmt
, insnbuf
);
12480 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
12482 TInsn
*tinsn
= &vinsn
->slots
[slot
];
12483 expressionS
*extra_arg
= &tinsn
->extra_arg
;
12484 bfd_boolean tinsn_has_fixup
=
12485 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
12486 vinsn
->slotbuf
[slot
]);
12488 xtensa_format_set_slot (isa
, fmt
, slot
,
12489 insnbuf
, vinsn
->slotbuf
[slot
]);
12490 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
12492 if (vinsn
->num_slots
!= 1)
12493 as_bad (_("TLS relocation not allowed in FLIX bundle"));
12494 else if (record_fixup
)
12495 /* Instructions that generate TLS relocations should always be
12496 relaxed in the front-end. If "record_fixup" is set, then this
12497 function is being called during back-end relaxation, so flag
12498 the unexpected behavior as an error. */
12499 as_bad (_("unexpected TLS relocation"));
12501 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
12502 xtensa_format_length (isa
, fmt
),
12503 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
12504 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
12506 if (tinsn_has_fixup
)
12509 xtensa_opcode opcode
= tinsn
->opcode
;
12510 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12513 for (i
= 0; i
< noperands
; i
++)
12515 expressionS
* exp
= &tinsn
->tok
[i
];
12521 if (get_relaxable_immed (opcode
) == i
)
12523 /* Add a fix record for the instruction, except if this
12524 function is being called prior to relaxation, i.e.,
12525 if record_fixup is false, and the instruction might
12526 be relaxed later. */
12528 || tinsn
->is_specific_opcode
12529 || !xg_is_relaxable_insn (tinsn
, 0))
12531 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
12532 frag_offset
- fragP
->fr_literal
);
12536 if (exp
->X_op
!= O_symbol
)
12537 as_bad (_("invalid operand"));
12538 tinsn
->symbol
= exp
->X_add_symbol
;
12539 tinsn
->offset
= exp
->X_add_number
;
12543 as_bad (_("symbolic operand not allowed"));
12551 as_bad (_("expression too complex"));
12563 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
12565 static xtensa_insnbuf insnbuf
= NULL
;
12566 static xtensa_insnbuf slotbuf
= NULL
;
12569 xtensa_isa isa
= xtensa_default_isa
;
12573 insnbuf
= xtensa_insnbuf_alloc (isa
);
12574 slotbuf
= xtensa_insnbuf_alloc (isa
);
12577 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
12578 fmt
= xtensa_format_decode (isa
, insnbuf
);
12579 if (fmt
== XTENSA_UNDEFINED
)
12580 as_fatal (_("cannot decode instruction format"));
12581 vinsn
->format
= fmt
;
12582 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
12584 for (i
= 0; i
< vinsn
->num_slots
; i
++)
12586 TInsn
*tinsn
= &vinsn
->slots
[i
];
12587 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
12588 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
12593 /* Expression utilities. */
12595 /* Return TRUE if the expression is an integer constant. */
12598 expr_is_const (const expressionS
*s
)
12600 return (s
->X_op
== O_constant
);
12604 /* Get the expression constant.
12605 Calling this is illegal if expr_is_const () returns TRUE. */
12608 get_expr_const (const expressionS
*s
)
12610 gas_assert (expr_is_const (s
));
12611 return s
->X_add_number
;
12615 /* Set the expression to a constant value. */
12618 set_expr_const (expressionS
*s
, offsetT val
)
12620 s
->X_op
= O_constant
;
12621 s
->X_add_number
= val
;
12622 s
->X_add_symbol
= NULL
;
12623 s
->X_op_symbol
= NULL
;
12628 expr_is_register (const expressionS
*s
)
12630 return (s
->X_op
== O_register
);
12634 /* Get the expression constant.
12635 Calling this is illegal if expr_is_const () returns TRUE. */
12638 get_expr_register (const expressionS
*s
)
12640 gas_assert (expr_is_register (s
));
12641 return s
->X_add_number
;
12645 /* Set the expression to a symbol + constant offset. */
12648 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
12650 s
->X_op
= O_symbol
;
12651 s
->X_add_symbol
= sym
;
12652 s
->X_op_symbol
= NULL
; /* unused */
12653 s
->X_add_number
= offset
;
12657 /* Return TRUE if the two expressions are equal. */
12660 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
12662 if (s1
->X_op
!= s2
->X_op
)
12664 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
12666 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
12668 if (s1
->X_add_number
!= s2
->X_add_number
)
12675 copy_expr (expressionS
*dst
, const expressionS
*src
)
12677 memcpy (dst
, src
, sizeof (expressionS
));
12681 /* Support for the "--rename-section" option. */
12683 struct rename_section_struct
12687 struct rename_section_struct
*next
;
12690 static struct rename_section_struct
*section_rename
;
12693 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
12694 entries to the section_rename list. Note: Specifying multiple
12695 renamings separated by colons is not documented and is retained only
12696 for backward compatibility. */
12699 build_section_rename (const char *arg
)
12701 struct rename_section_struct
*r
;
12702 char *this_arg
= NULL
;
12703 char *next_arg
= NULL
;
12705 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
12707 char *old_name
, *new_name
;
12711 next_arg
= strchr (this_arg
, ':');
12719 old_name
= this_arg
;
12720 new_name
= strchr (this_arg
, '=');
12722 if (*old_name
== '\0')
12724 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12727 if (!new_name
|| new_name
[1] == '\0')
12729 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
12736 /* Check for invalid section renaming. */
12737 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12739 if (strcmp (r
->old_name
, old_name
) == 0)
12740 as_bad (_("section %s renamed multiple times"), old_name
);
12741 if (strcmp (r
->new_name
, new_name
) == 0)
12742 as_bad (_("multiple sections remapped to output section %s"),
12747 r
= (struct rename_section_struct
*)
12748 xmalloc (sizeof (struct rename_section_struct
));
12749 r
->old_name
= xstrdup (old_name
);
12750 r
->new_name
= xstrdup (new_name
);
12751 r
->next
= section_rename
;
12752 section_rename
= r
;
12758 xtensa_section_rename (char *name
)
12760 struct rename_section_struct
*r
= section_rename
;
12762 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12764 if (strcmp (r
->old_name
, name
) == 0)
12765 return r
->new_name
;