1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 /* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
357 #define O_pcrel O_md4 /* value is a PC-relative offset */
359 struct suffix_reloc_map
363 bfd_reloc_code_real_type reloc
;
364 unsigned char operator;
367 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
369 static struct suffix_reloc_map suffix_relocs
[] =
371 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
372 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
373 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
374 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
375 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
389 directive_literal_prefix
,
391 directive_absolute_literals
,
392 directive_last_directive
398 bfd_boolean can_be_negated
;
401 const directive_infoS directive_info
[] =
404 { "literal", FALSE
},
406 { "transform", TRUE
},
407 { "freeregs", FALSE
},
408 { "longcalls", TRUE
},
409 { "literal_prefix", FALSE
},
410 { "schedule", TRUE
},
411 { "absolute-literals", TRUE
}
414 bfd_boolean directive_state
[] =
418 #if !XCHAL_HAVE_DENSITY
423 TRUE
, /* transform */
424 FALSE
, /* freeregs */
425 FALSE
, /* longcalls */
426 FALSE
, /* literal_prefix */
427 FALSE
, /* schedule */
428 #if XSHAL_USE_ABSOLUTE_LITERALS
429 TRUE
/* absolute_literals */
431 FALSE
/* absolute_literals */
436 /* Directive functions. */
438 static void xtensa_begin_directive (int);
439 static void xtensa_end_directive (int);
440 static void xtensa_literal_prefix (void);
441 static void xtensa_literal_position (int);
442 static void xtensa_literal_pseudo (int);
443 static void xtensa_frequency_pseudo (int);
444 static void xtensa_elf_cons (int);
446 /* Parsing and Idiom Translation. */
448 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
450 /* Various Other Internal Functions. */
452 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
453 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
454 static void xtensa_mark_literal_pool_location (void);
455 static addressT
get_expanded_loop_offset (xtensa_opcode
);
456 static fragS
*get_literal_pool_location (segT
);
457 static void set_literal_pool_location (segT
, fragS
*);
458 static void xtensa_set_frag_assembly_state (fragS
*);
459 static void finish_vinsn (vliw_insn
*);
460 static bfd_boolean
emit_single_op (TInsn
*);
461 static int total_frag_text_expansion (fragS
*);
463 /* Alignment Functions. */
465 static int get_text_align_power (unsigned);
466 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
467 static int branch_align_power (segT
);
469 /* Helpers for xtensa_relax_frag(). */
471 static long relax_frag_add_nop (fragS
*);
473 /* Accessors for additional per-subsegment information. */
475 static unsigned get_last_insn_flags (segT
, subsegT
);
476 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
477 static float get_subseg_total_freq (segT
, subsegT
);
478 static float get_subseg_target_freq (segT
, subsegT
);
479 static void set_subseg_freq (segT
, subsegT
, float, float);
481 /* Segment list functions. */
483 static void xtensa_move_literals (void);
484 static void xtensa_reorder_segments (void);
485 static void xtensa_switch_to_literal_fragment (emit_state
*);
486 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
487 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
488 static void xtensa_restore_emit_state (emit_state
*);
489 static segT
cache_literal_section (bfd_boolean
);
491 /* Import from elf32-xtensa.c in BFD library. */
493 extern asection
*xtensa_get_property_section (asection
*, const char *);
495 /* op_placement_info functions. */
497 static void init_op_placement_info_table (void);
498 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
499 static int xg_get_single_size (xtensa_opcode
);
500 static xtensa_format
xg_get_single_format (xtensa_opcode
);
501 static int xg_get_single_slot (xtensa_opcode
);
503 /* TInsn and IStack functions. */
505 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
506 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
507 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
508 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
509 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
510 static void tinsn_from_chars (TInsn
*, char *, int);
511 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
512 static int get_num_stack_text_bytes (IStack
*);
513 static int get_num_stack_literal_bytes (IStack
*);
515 /* vliw_insn functions. */
517 static void xg_init_vinsn (vliw_insn
*);
518 static void xg_clear_vinsn (vliw_insn
*);
519 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
520 static void xg_free_vinsn (vliw_insn
*);
521 static bfd_boolean vinsn_to_insnbuf
522 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
523 static void vinsn_from_chars (vliw_insn
*, char *);
525 /* Expression Utilities. */
527 bfd_boolean
expr_is_const (const expressionS
*);
528 offsetT
get_expr_const (const expressionS
*);
529 void set_expr_const (expressionS
*, offsetT
);
530 bfd_boolean
expr_is_register (const expressionS
*);
531 offsetT
get_expr_register (const expressionS
*);
532 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
533 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
534 static void copy_expr (expressionS
*, const expressionS
*);
536 /* Section renaming. */
538 static void build_section_rename (const char *);
541 /* ISA imported from bfd. */
542 extern xtensa_isa xtensa_default_isa
;
544 extern int target_big_endian
;
546 static xtensa_opcode xtensa_addi_opcode
;
547 static xtensa_opcode xtensa_addmi_opcode
;
548 static xtensa_opcode xtensa_call0_opcode
;
549 static xtensa_opcode xtensa_call4_opcode
;
550 static xtensa_opcode xtensa_call8_opcode
;
551 static xtensa_opcode xtensa_call12_opcode
;
552 static xtensa_opcode xtensa_callx0_opcode
;
553 static xtensa_opcode xtensa_callx4_opcode
;
554 static xtensa_opcode xtensa_callx8_opcode
;
555 static xtensa_opcode xtensa_callx12_opcode
;
556 static xtensa_opcode xtensa_const16_opcode
;
557 static xtensa_opcode xtensa_entry_opcode
;
558 static xtensa_opcode xtensa_extui_opcode
;
559 static xtensa_opcode xtensa_movi_opcode
;
560 static xtensa_opcode xtensa_movi_n_opcode
;
561 static xtensa_opcode xtensa_isync_opcode
;
562 static xtensa_opcode xtensa_jx_opcode
;
563 static xtensa_opcode xtensa_l32r_opcode
;
564 static xtensa_opcode xtensa_loop_opcode
;
565 static xtensa_opcode xtensa_loopnez_opcode
;
566 static xtensa_opcode xtensa_loopgtz_opcode
;
567 static xtensa_opcode xtensa_nop_opcode
;
568 static xtensa_opcode xtensa_nop_n_opcode
;
569 static xtensa_opcode xtensa_or_opcode
;
570 static xtensa_opcode xtensa_ret_opcode
;
571 static xtensa_opcode xtensa_ret_n_opcode
;
572 static xtensa_opcode xtensa_retw_opcode
;
573 static xtensa_opcode xtensa_retw_n_opcode
;
574 static xtensa_opcode xtensa_rsr_lcount_opcode
;
575 static xtensa_opcode xtensa_waiti_opcode
;
578 /* Command-line Options. */
580 bfd_boolean use_literal_section
= TRUE
;
581 static bfd_boolean align_targets
= TRUE
;
582 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
583 static bfd_boolean has_a0_b_retw
= FALSE
;
584 static bfd_boolean workaround_a0_b_retw
= FALSE
;
585 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
586 static bfd_boolean workaround_short_loop
= FALSE
;
587 static bfd_boolean maybe_has_short_loop
= FALSE
;
588 static bfd_boolean workaround_close_loop_end
= FALSE
;
589 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
590 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
592 /* When workaround_short_loops is TRUE, all loops with early exits must
593 have at least 3 instructions. workaround_all_short_loops is a modifier
594 to the workaround_short_loop flag. In addition to the
595 workaround_short_loop actions, all straightline loopgtz and loopnez
596 must have at least 3 instructions. */
598 static bfd_boolean workaround_all_short_loops
= FALSE
;
602 xtensa_setup_hw_workarounds (int earliest
, int latest
)
604 if (earliest
> latest
)
605 as_fatal (_("illegal range of target hardware versions"));
607 /* Enable all workarounds for pre-T1050.0 hardware. */
608 if (earliest
< 105000 || latest
< 105000)
610 workaround_a0_b_retw
|= TRUE
;
611 workaround_b_j_loop_end
|= TRUE
;
612 workaround_short_loop
|= TRUE
;
613 workaround_close_loop_end
|= TRUE
;
614 workaround_all_short_loops
|= TRUE
;
615 enforce_three_byte_loop_align
= TRUE
;
622 option_density
= OPTION_MD_BASE
,
629 option_no_link_relax
,
637 option_text_section_literals
,
638 option_no_text_section_literals
,
640 option_absolute_literals
,
641 option_no_absolute_literals
,
643 option_align_targets
,
644 option_no_align_targets
,
646 option_warn_unaligned_targets
,
651 option_workaround_a0_b_retw
,
652 option_no_workaround_a0_b_retw
,
654 option_workaround_b_j_loop_end
,
655 option_no_workaround_b_j_loop_end
,
657 option_workaround_short_loop
,
658 option_no_workaround_short_loop
,
660 option_workaround_all_short_loops
,
661 option_no_workaround_all_short_loops
,
663 option_workaround_close_loop_end
,
664 option_no_workaround_close_loop_end
,
666 option_no_workarounds
,
668 option_rename_section_name
,
671 option_prefer_const16
,
673 option_target_hardware
676 const char *md_shortopts
= "";
678 struct option md_longopts
[] =
680 { "density", no_argument
, NULL
, option_density
},
681 { "no-density", no_argument
, NULL
, option_no_density
},
683 /* Both "relax" and "generics" are deprecated and treated as equivalent
684 to the "transform" option. */
685 { "relax", no_argument
, NULL
, option_relax
},
686 { "no-relax", no_argument
, NULL
, option_no_relax
},
687 { "generics", no_argument
, NULL
, option_generics
},
688 { "no-generics", no_argument
, NULL
, option_no_generics
},
690 { "transform", no_argument
, NULL
, option_transform
},
691 { "no-transform", no_argument
, NULL
, option_no_transform
},
692 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
693 { "no-text-section-literals", no_argument
, NULL
,
694 option_no_text_section_literals
},
695 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
696 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
697 /* This option was changed from -align-target to -target-align
698 because it conflicted with the "-al" option. */
699 { "target-align", no_argument
, NULL
, option_align_targets
},
700 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
701 { "warn-unaligned-targets", no_argument
, NULL
,
702 option_warn_unaligned_targets
},
703 { "longcalls", no_argument
, NULL
, option_longcalls
},
704 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
706 { "no-workaround-a0-b-retw", no_argument
, NULL
,
707 option_no_workaround_a0_b_retw
},
708 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
710 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
711 option_no_workaround_b_j_loop_end
},
712 { "workaround-b-j-loop-end", no_argument
, NULL
,
713 option_workaround_b_j_loop_end
},
715 { "no-workaround-short-loops", no_argument
, NULL
,
716 option_no_workaround_short_loop
},
717 { "workaround-short-loops", no_argument
, NULL
,
718 option_workaround_short_loop
},
720 { "no-workaround-all-short-loops", no_argument
, NULL
,
721 option_no_workaround_all_short_loops
},
722 { "workaround-all-short-loop", no_argument
, NULL
,
723 option_workaround_all_short_loops
},
725 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
726 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
728 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
730 { "no-workaround-close-loop-end", no_argument
, NULL
,
731 option_no_workaround_close_loop_end
},
732 { "workaround-close-loop-end", no_argument
, NULL
,
733 option_workaround_close_loop_end
},
735 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
737 { "link-relax", no_argument
, NULL
, option_link_relax
},
738 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
740 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
742 { NULL
, no_argument
, NULL
, 0 }
745 size_t md_longopts_size
= sizeof md_longopts
;
749 md_parse_option (int c
, char *arg
)
754 as_warn (_("--density option is ignored"));
756 case option_no_density
:
757 as_warn (_("--no-density option is ignored"));
759 case option_link_relax
:
762 case option_no_link_relax
:
765 case option_generics
:
766 as_warn (_("--generics is deprecated; use --transform instead"));
767 return md_parse_option (option_transform
, arg
);
768 case option_no_generics
:
769 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
770 return md_parse_option (option_no_transform
, arg
);
772 as_warn (_("--relax is deprecated; use --transform instead"));
773 return md_parse_option (option_transform
, arg
);
774 case option_no_relax
:
775 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
776 return md_parse_option (option_no_transform
, arg
);
777 case option_longcalls
:
778 directive_state
[directive_longcalls
] = TRUE
;
780 case option_no_longcalls
:
781 directive_state
[directive_longcalls
] = FALSE
;
783 case option_text_section_literals
:
784 use_literal_section
= FALSE
;
786 case option_no_text_section_literals
:
787 use_literal_section
= TRUE
;
789 case option_absolute_literals
:
790 if (!absolute_literals_supported
)
792 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
795 directive_state
[directive_absolute_literals
] = TRUE
;
797 case option_no_absolute_literals
:
798 directive_state
[directive_absolute_literals
] = FALSE
;
801 case option_workaround_a0_b_retw
:
802 workaround_a0_b_retw
= TRUE
;
804 case option_no_workaround_a0_b_retw
:
805 workaround_a0_b_retw
= FALSE
;
807 case option_workaround_b_j_loop_end
:
808 workaround_b_j_loop_end
= TRUE
;
810 case option_no_workaround_b_j_loop_end
:
811 workaround_b_j_loop_end
= FALSE
;
814 case option_workaround_short_loop
:
815 workaround_short_loop
= TRUE
;
817 case option_no_workaround_short_loop
:
818 workaround_short_loop
= FALSE
;
821 case option_workaround_all_short_loops
:
822 workaround_all_short_loops
= TRUE
;
824 case option_no_workaround_all_short_loops
:
825 workaround_all_short_loops
= FALSE
;
828 case option_workaround_close_loop_end
:
829 workaround_close_loop_end
= TRUE
;
831 case option_no_workaround_close_loop_end
:
832 workaround_close_loop_end
= FALSE
;
835 case option_no_workarounds
:
836 workaround_a0_b_retw
= FALSE
;
837 workaround_b_j_loop_end
= FALSE
;
838 workaround_short_loop
= FALSE
;
839 workaround_all_short_loops
= FALSE
;
840 workaround_close_loop_end
= FALSE
;
843 case option_align_targets
:
844 align_targets
= TRUE
;
846 case option_no_align_targets
:
847 align_targets
= FALSE
;
850 case option_warn_unaligned_targets
:
851 warn_unaligned_branch_targets
= TRUE
;
854 case option_rename_section_name
:
855 build_section_rename (arg
);
859 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
860 should be emitted or not. FIXME: Not implemented. */
863 case option_prefer_l32r
:
865 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
869 case option_prefer_const16
:
871 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
875 case option_target_hardware
:
877 int earliest
, latest
= 0;
878 if (*arg
== 0 || *arg
== '-')
879 as_fatal (_("invalid target hardware version"));
881 earliest
= strtol (arg
, &arg
, 0);
885 else if (*arg
== '-')
888 as_fatal (_("invalid target hardware version"));
889 latest
= strtol (arg
, &arg
, 0);
892 as_fatal (_("invalid target hardware version"));
894 xtensa_setup_hw_workarounds (earliest
, latest
);
898 case option_transform
:
899 /* This option has no affect other than to use the defaults,
900 which are already set. */
903 case option_no_transform
:
904 /* This option turns off all transformations of any kind.
905 However, because we want to preserve the state of other
906 directives, we only change its own field. Thus, before
907 you perform any transformation, always check if transform
908 is available. If you use the functions we provide for this
909 purpose, you will be ok. */
910 directive_state
[directive_transform
] = FALSE
;
920 md_show_usage (FILE *stream
)
924 --[no-]text-section-literals\n\
925 [Do not] put literals in the text section\n\
926 --[no-]absolute-literals\n\
927 [Do not] default to use non-PC-relative literals\n\
928 --[no-]target-align [Do not] try to align branch targets\n\
929 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
930 --[no-]transform [Do not] transform instructions\n\
931 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
935 /* Functions related to the list of current label symbols. */
938 xtensa_add_insn_label (symbolS
*sym
)
942 if (!free_insn_labels
)
943 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
946 l
= free_insn_labels
;
947 free_insn_labels
= l
->next
;
951 l
->next
= insn_labels
;
957 xtensa_clear_insn_labels (void)
961 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
969 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
973 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
975 symbolS
*lit_sym
= lit
->sym
;
976 S_SET_VALUE (lit_sym
, new_offset
);
977 symbol_set_frag (lit_sym
, new_frag
);
982 /* Directive data and functions. */
984 typedef struct state_stackS_struct
986 directiveE directive
;
988 bfd_boolean old_state
;
992 struct state_stackS_struct
*prev
;
995 state_stackS
*directive_state_stack
;
997 const pseudo_typeS md_pseudo_table
[] =
999 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1000 { "literal_position", xtensa_literal_position
, 0 },
1001 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1002 { "long", xtensa_elf_cons
, 4 },
1003 { "word", xtensa_elf_cons
, 4 },
1004 { "4byte", xtensa_elf_cons
, 4 },
1005 { "short", xtensa_elf_cons
, 2 },
1006 { "2byte", xtensa_elf_cons
, 2 },
1007 { "begin", xtensa_begin_directive
, 0 },
1008 { "end", xtensa_end_directive
, 0 },
1009 { "literal", xtensa_literal_pseudo
, 0 },
1010 { "frequency", xtensa_frequency_pseudo
, 0 },
1016 use_transform (void)
1018 /* After md_end, you should be checking frag by frag, rather
1019 than state directives. */
1020 assert (!past_xtensa_end
);
1021 return directive_state
[directive_transform
];
1026 do_align_targets (void)
1028 /* Do not use this function after md_end; just look at align_targets
1029 instead. There is no target-align directive, so alignment is either
1030 enabled for all frags or not done at all. */
1031 assert (!past_xtensa_end
);
1032 return align_targets
&& use_transform ();
1037 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1041 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1043 as_where (&file
, &line
);
1045 stack
->directive
= directive
;
1046 stack
->negated
= negated
;
1047 stack
->old_state
= directive_state
[directive
];
1050 stack
->datum
= datum
;
1051 stack
->prev
= directive_state_stack
;
1052 directive_state_stack
= stack
;
1054 directive_state
[directive
] = !negated
;
1059 directive_pop (directiveE
*directive
,
1060 bfd_boolean
*negated
,
1065 state_stackS
*top
= directive_state_stack
;
1067 if (!directive_state_stack
)
1069 as_bad (_("unmatched end directive"));
1070 *directive
= directive_none
;
1074 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1075 *directive
= top
->directive
;
1076 *negated
= top
->negated
;
1079 *datum
= top
->datum
;
1080 directive_state_stack
= top
->prev
;
1086 directive_balance (void)
1088 while (directive_state_stack
)
1090 directiveE directive
;
1091 bfd_boolean negated
;
1096 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1097 as_warn_where ((char *) file
, line
,
1098 _(".begin directive with no matching .end directive"));
1104 inside_directive (directiveE dir
)
1106 state_stackS
*top
= directive_state_stack
;
1108 while (top
&& top
->directive
!= dir
)
1111 return (top
!= NULL
);
1116 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1120 char *directive_string
;
1122 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1127 input_line_pointer
+= 3;
1130 len
= strspn (input_line_pointer
,
1131 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1133 /* This code is a hack to make .begin [no-][generics|relax] exactly
1134 equivalent to .begin [no-]transform. We should remove it when
1135 we stop accepting those options. */
1137 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1139 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1140 directive_string
= "transform";
1142 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1144 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1145 directive_string
= "transform";
1148 directive_string
= input_line_pointer
;
1150 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1152 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1154 input_line_pointer
+= len
;
1155 *directive
= (directiveE
) i
;
1156 if (*negated
&& !directive_info
[i
].can_be_negated
)
1157 as_bad (_("directive %s cannot be negated"),
1158 directive_info
[i
].name
);
1163 as_bad (_("unknown directive"));
1164 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1169 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1171 directiveE directive
;
1172 bfd_boolean negated
;
1176 get_directive (&directive
, &negated
);
1177 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1179 discard_rest_of_line ();
1183 if (cur_vinsn
.inside_bundle
)
1184 as_bad (_("directives are not valid inside bundles"));
1188 case directive_literal
:
1189 if (!inside_directive (directive_literal
))
1191 /* Previous labels go with whatever follows this directive, not with
1192 the literal, so save them now. */
1193 saved_insn_labels
= insn_labels
;
1196 as_warn (_(".begin literal is deprecated; use .literal instead"));
1197 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1198 xtensa_switch_to_literal_fragment (state
);
1199 directive_push (directive_literal
, negated
, state
);
1202 case directive_literal_prefix
:
1203 /* Have to flush pending output because a movi relaxed to an l32r
1204 might produce a literal. */
1205 md_flush_pending_output ();
1206 /* Check to see if the current fragment is a literal
1207 fragment. If it is, then this operation is not allowed. */
1208 if (generating_literals
)
1210 as_bad (_("cannot set literal_prefix inside literal fragment"));
1214 /* Allocate the literal state for this section and push
1215 onto the directive stack. */
1216 ls
= xmalloc (sizeof (lit_state
));
1219 *ls
= default_lit_sections
;
1220 directive_push (directive_literal_prefix
, negated
, ls
);
1222 /* Process the new prefix. */
1223 xtensa_literal_prefix ();
1226 case directive_freeregs
:
1227 /* This information is currently unused, but we'll accept the statement
1228 and just discard the rest of the line. This won't check the syntax,
1229 but it will accept every correct freeregs directive. */
1230 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1231 directive_push (directive_freeregs
, negated
, 0);
1234 case directive_schedule
:
1235 md_flush_pending_output ();
1236 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1237 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1238 directive_push (directive_schedule
, negated
, 0);
1239 xtensa_set_frag_assembly_state (frag_now
);
1242 case directive_density
:
1243 as_warn (_(".begin [no-]density is ignored"));
1246 case directive_absolute_literals
:
1247 md_flush_pending_output ();
1248 if (!absolute_literals_supported
&& !negated
)
1250 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1253 xtensa_set_frag_assembly_state (frag_now
);
1254 directive_push (directive
, negated
, 0);
1258 md_flush_pending_output ();
1259 xtensa_set_frag_assembly_state (frag_now
);
1260 directive_push (directive
, negated
, 0);
1264 demand_empty_rest_of_line ();
1269 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1271 directiveE begin_directive
, end_directive
;
1272 bfd_boolean begin_negated
, end_negated
;
1276 emit_state
**state_ptr
;
1279 if (cur_vinsn
.inside_bundle
)
1280 as_bad (_("directives are not valid inside bundles"));
1282 get_directive (&end_directive
, &end_negated
);
1284 md_flush_pending_output ();
1286 switch (end_directive
)
1288 case (directiveE
) XTENSA_UNDEFINED
:
1289 discard_rest_of_line ();
1292 case directive_density
:
1293 as_warn (_(".end [no-]density is ignored"));
1294 demand_empty_rest_of_line ();
1297 case directive_absolute_literals
:
1298 if (!absolute_literals_supported
&& !end_negated
)
1300 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1301 demand_empty_rest_of_line ();
1310 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1311 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1312 (const void **) state_ptr
);
1314 if (begin_directive
!= directive_none
)
1316 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1318 as_bad (_("does not match begin %s%s at %s:%d"),
1319 begin_negated
? "no-" : "",
1320 directive_info
[begin_directive
].name
, file
, line
);
1324 switch (end_directive
)
1326 case directive_literal
:
1327 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1328 xtensa_restore_emit_state (state
);
1329 xtensa_set_frag_assembly_state (frag_now
);
1331 if (!inside_directive (directive_literal
))
1333 /* Restore the list of current labels. */
1334 xtensa_clear_insn_labels ();
1335 insn_labels
= saved_insn_labels
;
1339 case directive_literal_prefix
:
1340 /* Restore the default collection sections from saved state. */
1341 s
= (lit_state
*) state
;
1343 default_lit_sections
= *s
;
1345 /* Free the state storage. */
1346 free (s
->lit_prefix
);
1350 case directive_schedule
:
1351 case directive_freeregs
:
1355 xtensa_set_frag_assembly_state (frag_now
);
1361 demand_empty_rest_of_line ();
1365 /* Place an aligned literal fragment at the current location. */
1368 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1370 md_flush_pending_output ();
1372 if (inside_directive (directive_literal
))
1373 as_warn (_(".literal_position inside literal directive; ignoring"));
1374 xtensa_mark_literal_pool_location ();
1376 demand_empty_rest_of_line ();
1377 xtensa_clear_insn_labels ();
1381 /* Support .literal label, expr, ... */
1384 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1387 char *p
, *base_name
;
1391 if (inside_directive (directive_literal
))
1393 as_bad (_(".literal not allowed inside .begin literal region"));
1394 ignore_rest_of_line ();
1398 md_flush_pending_output ();
1400 /* Previous labels go with whatever follows this directive, not with
1401 the literal, so save them now. */
1402 saved_insn_labels
= insn_labels
;
1405 /* If we are using text-section literals, then this is the right value... */
1408 base_name
= input_line_pointer
;
1410 xtensa_switch_to_literal_fragment (&state
);
1412 /* ...but if we aren't using text-section-literals, then we
1413 need to put them in the section we just switched to. */
1414 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1417 /* All literals are aligned to four-byte boundaries. */
1418 frag_align (2, 0, 0);
1419 record_alignment (now_seg
, 2);
1421 c
= get_symbol_end ();
1422 /* Just after name is now '\0'. */
1423 p
= input_line_pointer
;
1427 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1429 as_bad (_("expected comma or colon after symbol name; "
1430 "rest of line ignored"));
1431 ignore_rest_of_line ();
1432 xtensa_restore_emit_state (&state
);
1440 input_line_pointer
++; /* skip ',' or ':' */
1442 xtensa_elf_cons (4);
1444 xtensa_restore_emit_state (&state
);
1446 /* Restore the list of current labels. */
1447 xtensa_clear_insn_labels ();
1448 insn_labels
= saved_insn_labels
;
1453 xtensa_literal_prefix (void)
1458 /* Parse the new prefix from the input_line_pointer. */
1460 len
= strspn (input_line_pointer
,
1461 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1462 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1464 /* Get a null-terminated copy of the name. */
1465 name
= xmalloc (len
+ 1);
1467 strncpy (name
, input_line_pointer
, len
);
1470 /* Skip the name in the input line. */
1471 input_line_pointer
+= len
;
1473 default_lit_sections
.lit_prefix
= name
;
1475 /* Clear cached literal sections, since the prefix has changed. */
1476 default_lit_sections
.lit_seg
= NULL
;
1477 default_lit_sections
.lit4_seg
= NULL
;
1481 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1484 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1486 float fall_through_f
, target_f
;
1488 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1489 if (fall_through_f
< 0)
1491 as_bad (_("fall through frequency must be greater than 0"));
1492 ignore_rest_of_line ();
1496 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1499 as_bad (_("branch target frequency must be greater than 0"));
1500 ignore_rest_of_line ();
1504 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1506 demand_empty_rest_of_line ();
1510 /* Like normal .long/.short/.word, except support @plt, etc.
1511 Clobbers input_line_pointer, checks end-of-line. */
1514 xtensa_elf_cons (int nbytes
)
1517 bfd_reloc_code_real_type reloc
;
1519 md_flush_pending_output ();
1521 if (cur_vinsn
.inside_bundle
)
1522 as_bad (_("directives are not valid inside bundles"));
1524 if (is_it_end_of_statement ())
1526 demand_empty_rest_of_line ();
1533 if (exp
.X_op
== O_symbol
1534 && *input_line_pointer
== '@'
1535 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1538 reloc_howto_type
*reloc_howto
=
1539 bfd_reloc_type_lookup (stdoutput
, reloc
);
1541 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1542 as_bad (_("unsupported relocation"));
1543 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1544 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1545 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1546 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1547 as_bad (_("opcode-specific %s relocation used outside "
1548 "an instruction"), reloc_howto
->name
);
1549 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1550 as_bad (_("%s relocations do not fit in %d bytes"),
1551 reloc_howto
->name
, nbytes
);
1554 char *p
= frag_more ((int) nbytes
);
1555 xtensa_set_frag_assembly_state (frag_now
);
1556 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1557 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1561 emit_expr (&exp
, (unsigned int) nbytes
);
1563 while (*input_line_pointer
++ == ',');
1565 input_line_pointer
--; /* Put terminator back into stream. */
1566 demand_empty_rest_of_line ();
1570 /* Parsing and Idiom Translation. */
1572 /* Parse @plt, etc. and return the desired relocation. */
1573 static bfd_reloc_code_real_type
1574 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1581 struct suffix_reloc_map
*ptr
;
1584 return BFD_RELOC_NONE
;
1586 for (ch
= *str
, str2
= ident
;
1587 (str2
< ident
+ sizeof (ident
) - 1
1588 && (ISALNUM (ch
) || ch
== '@'));
1591 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1598 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1599 if (ch
== ptr
->suffix
[0]
1600 && len
== ptr
->length
1601 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1603 /* Now check for "identifier@suffix+constant". */
1604 if (*str
== '-' || *str
== '+')
1606 char *orig_line
= input_line_pointer
;
1607 expressionS new_exp
;
1609 input_line_pointer
= str
;
1610 expression (&new_exp
);
1611 if (new_exp
.X_op
== O_constant
)
1613 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1614 str
= input_line_pointer
;
1617 if (&input_line_pointer
!= str_p
)
1618 input_line_pointer
= orig_line
;
1625 return BFD_RELOC_UNUSED
;
1629 /* Find the matching operator type. */
1630 static unsigned char
1631 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1633 struct suffix_reloc_map
*sfx
;
1634 unsigned char operator = (unsigned char) -1;
1636 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1638 if (sfx
->reloc
== reloc
)
1640 operator = sfx
->operator;
1644 assert (operator != (unsigned char) -1);
1649 /* Find the matching reloc type. */
1650 static bfd_reloc_code_real_type
1651 map_operator_to_reloc (unsigned char operator)
1653 struct suffix_reloc_map
*sfx
;
1654 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1656 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1658 if (sfx
->operator == operator)
1665 if (reloc
== BFD_RELOC_UNUSED
)
1666 return BFD_RELOC_32
;
1673 expression_end (const char *name
)
1696 #define ERROR_REG_NUM ((unsigned) -1)
1699 tc_get_register (const char *prefix
)
1702 const char *next_expr
;
1703 const char *old_line_pointer
;
1706 old_line_pointer
= input_line_pointer
;
1708 if (*input_line_pointer
== '$')
1709 ++input_line_pointer
;
1711 /* Accept "sp" as a synonym for "a1". */
1712 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1713 && expression_end (input_line_pointer
+ 2))
1715 input_line_pointer
+= 2;
1716 return 1; /* AR[1] */
1719 while (*input_line_pointer
++ == *prefix
++)
1721 --input_line_pointer
;
1726 as_bad (_("bad register name: %s"), old_line_pointer
);
1727 return ERROR_REG_NUM
;
1730 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1732 as_bad (_("bad register number: %s"), input_line_pointer
);
1733 return ERROR_REG_NUM
;
1738 while (ISDIGIT ((int) *input_line_pointer
))
1739 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1741 if (!(next_expr
= expression_end (input_line_pointer
)))
1743 as_bad (_("bad register name: %s"), old_line_pointer
);
1744 return ERROR_REG_NUM
;
1747 input_line_pointer
= (char *) next_expr
;
1754 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1756 xtensa_isa isa
= xtensa_default_isa
;
1758 /* Check if this is an immediate operand. */
1759 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1761 bfd_reloc_code_real_type reloc
;
1762 segT t
= expression (tok
);
1763 if (t
== absolute_section
1764 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1766 assert (tok
->X_op
== O_constant
);
1767 tok
->X_op
= O_symbol
;
1768 tok
->X_add_symbol
= &abs_symbol
;
1771 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1772 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1777 case BFD_RELOC_LO16
:
1778 if (tok
->X_op
== O_constant
)
1780 tok
->X_add_number
&= 0xffff;
1784 case BFD_RELOC_HI16
:
1785 if (tok
->X_op
== O_constant
)
1787 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1791 case BFD_RELOC_UNUSED
:
1792 as_bad (_("unsupported relocation"));
1794 case BFD_RELOC_32_PCREL
:
1795 as_bad (_("pcrel relocation not allowed in an instruction"));
1800 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1805 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1806 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1808 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1811 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1812 as_bad (_("register number out of range"));
1815 tok
->X_op
= O_register
;
1816 tok
->X_add_symbol
= 0;
1817 tok
->X_add_number
= reg
;
1822 /* Split up the arguments for an opcode or pseudo-op. */
1825 tokenize_arguments (char **args
, char *str
)
1827 char *old_input_line_pointer
;
1828 bfd_boolean saw_comma
= FALSE
;
1829 bfd_boolean saw_arg
= FALSE
;
1830 bfd_boolean saw_colon
= FALSE
;
1832 char *arg_end
, *arg
;
1835 /* Save and restore input_line_pointer around this function. */
1836 old_input_line_pointer
= input_line_pointer
;
1837 input_line_pointer
= str
;
1839 while (*input_line_pointer
)
1842 switch (*input_line_pointer
)
1849 input_line_pointer
++;
1850 if (saw_comma
|| saw_colon
|| !saw_arg
)
1856 input_line_pointer
++;
1857 if (saw_comma
|| saw_colon
|| !saw_arg
)
1863 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1866 arg_end
= input_line_pointer
+ 1;
1867 while (!expression_end (arg_end
))
1870 arg_len
= arg_end
- input_line_pointer
;
1871 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1872 args
[num_args
] = arg
;
1876 strncpy (arg
, input_line_pointer
, arg_len
);
1877 arg
[arg_len
] = '\0';
1879 input_line_pointer
= arg_end
;
1889 if (saw_comma
|| saw_colon
)
1891 input_line_pointer
= old_input_line_pointer
;
1896 as_bad (_("extra comma"));
1898 as_bad (_("extra colon"));
1900 as_bad (_("missing argument"));
1902 as_bad (_("missing comma or colon"));
1903 input_line_pointer
= old_input_line_pointer
;
1908 /* Parse the arguments to an opcode. Return TRUE on error. */
1911 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1913 expressionS
*tok
, *last_tok
;
1914 xtensa_opcode opcode
= insn
->opcode
;
1915 bfd_boolean had_error
= TRUE
;
1916 xtensa_isa isa
= xtensa_default_isa
;
1917 int n
, num_regs
= 0;
1918 int opcode_operand_count
;
1919 int opnd_cnt
, last_opnd_cnt
;
1920 unsigned int next_reg
= 0;
1921 char *old_input_line_pointer
;
1923 if (insn
->insn_type
== ITYPE_LITERAL
)
1924 opcode_operand_count
= 1;
1926 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1929 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1931 /* Save and restore input_line_pointer around this function. */
1932 old_input_line_pointer
= input_line_pointer
;
1938 /* Skip invisible operands. */
1939 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1945 for (n
= 0; n
< num_args
; n
++)
1947 input_line_pointer
= arg_strings
[n
];
1948 if (*input_line_pointer
== ':')
1950 xtensa_regfile opnd_rf
;
1951 input_line_pointer
++;
1954 assert (opnd_cnt
> 0);
1956 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1958 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1959 as_warn (_("incorrect register number, ignoring"));
1964 if (opnd_cnt
>= opcode_operand_count
)
1966 as_warn (_("too many arguments"));
1969 assert (opnd_cnt
< MAX_INSN_ARGS
);
1971 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1972 next_reg
= tok
->X_add_number
+ 1;
1974 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1976 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1978 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1979 /* minus 1 because we are seeing one right now */
1985 last_opnd_cnt
= opnd_cnt
;
1992 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1996 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1999 insn
->ntok
= tok
- insn
->tok
;
2003 input_line_pointer
= old_input_line_pointer
;
2009 get_invisible_operands (TInsn
*insn
)
2011 xtensa_isa isa
= xtensa_default_isa
;
2012 static xtensa_insnbuf slotbuf
= NULL
;
2014 xtensa_opcode opc
= insn
->opcode
;
2015 int slot
, opnd
, fmt_found
;
2019 slotbuf
= xtensa_insnbuf_alloc (isa
);
2021 /* Find format/slot where this can be encoded. */
2024 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2026 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2028 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2034 if (fmt_found
) break;
2039 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2043 /* First encode all the visible operands
2044 (to deal with shared field operands). */
2045 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2047 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2048 && (insn
->tok
[opnd
].X_op
== O_register
2049 || insn
->tok
[opnd
].X_op
== O_constant
))
2051 val
= insn
->tok
[opnd
].X_add_number
;
2052 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2053 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2057 /* Then pull out the values for the invisible ones. */
2058 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2060 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2062 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2063 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2064 insn
->tok
[opnd
].X_add_number
= val
;
2065 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2066 insn
->tok
[opnd
].X_op
= O_register
;
2068 insn
->tok
[opnd
].X_op
= O_constant
;
2077 xg_reverse_shift_count (char **cnt_argp
)
2079 char *cnt_arg
, *new_arg
;
2080 cnt_arg
= *cnt_argp
;
2082 /* replace the argument with "31-(argument)" */
2083 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2084 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2087 *cnt_argp
= new_arg
;
2091 /* If "arg" is a constant expression, return non-zero with the value
2095 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2098 char *save_ptr
= input_line_pointer
;
2100 input_line_pointer
= arg
;
2102 input_line_pointer
= save_ptr
;
2104 if (exp
.X_op
== O_constant
)
2106 *valp
= exp
.X_add_number
;
2115 xg_replace_opname (char **popname
, char *newop
)
2118 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2119 strcpy (*popname
, newop
);
2124 xg_check_num_args (int *pnum_args
,
2129 int num_args
= *pnum_args
;
2131 if (num_args
< expected_num
)
2133 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2134 num_args
, opname
, expected_num
);
2138 if (num_args
> expected_num
)
2140 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2141 num_args
, opname
, expected_num
);
2142 while (num_args
-- > expected_num
)
2144 free (arg_strings
[num_args
]);
2145 arg_strings
[num_args
] = 0;
2147 *pnum_args
= expected_num
;
2155 /* If the register is not specified as part of the opcode,
2156 then get it from the operand and move it to the opcode. */
2159 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2161 xtensa_isa isa
= xtensa_default_isa
;
2163 char *opname
, *new_opname
;
2164 const char *sr_name
;
2165 int is_user
, is_write
;
2170 is_user
= (opname
[1] == 'u');
2171 is_write
= (opname
[0] == 'w');
2173 /* Opname == [rw]ur or [rwx]sr... */
2175 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2178 /* Check if the argument is a symbolic register name. */
2179 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2180 /* Handle WSR to "INTSET" as a special case. */
2181 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2182 && !strcasecmp (arg_strings
[1], "intset"))
2183 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2184 if (sr
== XTENSA_UNDEFINED
2185 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2187 /* Maybe it's a register number.... */
2189 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2191 as_bad (_("invalid register '%s' for '%s' instruction"),
2192 arg_strings
[1], opname
);
2195 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2196 if (sr
== XTENSA_UNDEFINED
)
2198 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2199 (long) val
, opname
);
2204 /* Remove the last argument, which is now part of the opcode. */
2205 free (arg_strings
[1]);
2209 /* Translate the opcode. */
2210 sr_name
= xtensa_sysreg_name (isa
, sr
);
2211 /* Another special case for "WSR.INTSET".... */
2212 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2214 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2215 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2217 *popname
= new_opname
;
2224 xtensa_translate_old_userreg_ops (char **popname
)
2226 xtensa_isa isa
= xtensa_default_isa
;
2228 char *opname
, *new_opname
;
2229 const char *sr_name
;
2230 bfd_boolean has_underbar
= FALSE
;
2233 if (opname
[0] == '_')
2235 has_underbar
= TRUE
;
2239 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2240 if (sr
!= XTENSA_UNDEFINED
)
2242 /* The new default name ("nnn") is different from the old default
2243 name ("URnnn"). The old default is handled below, and we don't
2244 want to recognize [RW]nnn, so do nothing if the name is the (new)
2246 static char namebuf
[10];
2247 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2248 if (strcmp (namebuf
, opname
+ 1) == 0)
2256 /* Only continue if the reg name is "URnnn". */
2257 if (opname
[1] != 'u' || opname
[2] != 'r')
2259 val
= strtoul (opname
+ 3, &end
, 10);
2263 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2264 if (sr
== XTENSA_UNDEFINED
)
2266 as_bad (_("invalid register number (%ld) for '%s'"),
2267 (long) val
, opname
);
2272 /* Translate the opcode. */
2273 sr_name
= xtensa_sysreg_name (isa
, sr
);
2274 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2275 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2276 opname
[0], sr_name
);
2278 *popname
= new_opname
;
2285 xtensa_translate_zero_immed (char *old_op
,
2295 assert (opname
[0] != '_');
2297 if (strcmp (opname
, old_op
) != 0)
2300 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2302 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2304 xg_replace_opname (popname
, new_op
);
2305 free (arg_strings
[1]);
2306 arg_strings
[1] = arg_strings
[2];
2315 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2316 Returns non-zero if an error was found. */
2319 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2321 char *opname
= *popname
;
2322 bfd_boolean has_underbar
= FALSE
;
2326 has_underbar
= TRUE
;
2330 if (strcmp (opname
, "mov") == 0)
2332 if (use_transform () && !has_underbar
&& density_supported
)
2333 xg_replace_opname (popname
, "mov.n");
2336 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2338 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2339 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2340 strcpy (arg_strings
[2], arg_strings
[1]);
2346 if (strcmp (opname
, "bbsi.l") == 0)
2348 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2350 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2351 if (target_big_endian
)
2352 xg_reverse_shift_count (&arg_strings
[1]);
2356 if (strcmp (opname
, "bbci.l") == 0)
2358 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2360 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2361 if (target_big_endian
)
2362 xg_reverse_shift_count (&arg_strings
[1]);
2366 /* Don't do anything special with NOPs inside FLIX instructions. They
2367 are handled elsewhere. Real NOP instructions are always available
2368 in configurations with FLIX, so this should never be an issue but
2369 check for it anyway. */
2370 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2371 && strcmp (opname
, "nop") == 0)
2373 if (use_transform () && !has_underbar
&& density_supported
)
2374 xg_replace_opname (popname
, "nop.n");
2377 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2379 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2380 arg_strings
[0] = (char *) xmalloc (3);
2381 arg_strings
[1] = (char *) xmalloc (3);
2382 arg_strings
[2] = (char *) xmalloc (3);
2383 strcpy (arg_strings
[0], "a1");
2384 strcpy (arg_strings
[1], "a1");
2385 strcpy (arg_strings
[2], "a1");
2391 /* Recognize [RW]UR and [RWX]SR. */
2392 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2393 && (opname
[1] == 'u' || opname
[1] == 's'))
2394 || (opname
[0] == 'x' && opname
[1] == 's'))
2396 && opname
[3] == '\0')
2397 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2399 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2400 [RW]<name> if <name> is the non-default name of a user register. */
2401 if ((opname
[0] == 'r' || opname
[0] == 'w')
2402 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2403 return xtensa_translate_old_userreg_ops (popname
);
2405 /* Relax branches that don't allow comparisons against an immediate value
2406 of zero to the corresponding branches with implicit zero immediates. */
2407 if (!has_underbar
&& use_transform ())
2409 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2410 pnum_args
, arg_strings
))
2413 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2414 pnum_args
, arg_strings
))
2417 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2418 pnum_args
, arg_strings
))
2421 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2422 pnum_args
, arg_strings
))
2430 /* Functions for dealing with the Xtensa ISA. */
2432 /* Currently the assembler only allows us to use a single target per
2433 fragment. Because of this, only one operand for a given
2434 instruction may be symbolic. If there is a PC-relative operand,
2435 the last one is chosen. Otherwise, the result is the number of the
2436 last immediate operand, and if there are none of those, we fail and
2440 get_relaxable_immed (xtensa_opcode opcode
)
2442 int last_immed
= -1;
2445 if (opcode
== XTENSA_UNDEFINED
)
2448 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2449 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2451 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2453 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2455 if (last_immed
== -1
2456 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2463 static xtensa_opcode
2464 get_opcode_from_buf (const char *buf
, int slot
)
2466 static xtensa_insnbuf insnbuf
= NULL
;
2467 static xtensa_insnbuf slotbuf
= NULL
;
2468 xtensa_isa isa
= xtensa_default_isa
;
2473 insnbuf
= xtensa_insnbuf_alloc (isa
);
2474 slotbuf
= xtensa_insnbuf_alloc (isa
);
2477 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2478 fmt
= xtensa_format_decode (isa
, insnbuf
);
2479 if (fmt
== XTENSA_UNDEFINED
)
2480 return XTENSA_UNDEFINED
;
2482 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2483 return XTENSA_UNDEFINED
;
2485 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2486 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2490 #ifdef TENSILICA_DEBUG
2492 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2495 xtensa_print_insn_table (void)
2497 int num_opcodes
, num_operands
;
2498 xtensa_opcode opcode
;
2499 xtensa_isa isa
= xtensa_default_isa
;
2501 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2502 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2505 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2506 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2507 for (opn
= 0; opn
< num_operands
; opn
++)
2509 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2511 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2513 xtensa_regfile opnd_rf
=
2514 xtensa_operand_regfile (isa
, opcode
, opn
);
2515 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2517 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2518 fputs ("[lLr] ", stderr
);
2520 fputs ("i ", stderr
);
2522 fprintf (stderr
, "\n");
2528 print_vliw_insn (xtensa_insnbuf vbuf
)
2530 xtensa_isa isa
= xtensa_default_isa
;
2531 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2532 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2535 fprintf (stderr
, "format = %d\n", f
);
2537 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2539 xtensa_opcode opcode
;
2543 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2544 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2545 opname
= xtensa_opcode_name (isa
, opcode
);
2547 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2548 fprintf (stderr
, " operands = ");
2550 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2554 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2556 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2557 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2558 fprintf (stderr
, "%d ", val
);
2560 fprintf (stderr
, "\n");
2562 xtensa_insnbuf_free (isa
, sbuf
);
2565 #endif /* TENSILICA_DEBUG */
2569 is_direct_call_opcode (xtensa_opcode opcode
)
2571 xtensa_isa isa
= xtensa_default_isa
;
2572 int n
, num_operands
;
2574 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2577 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2578 for (n
= 0; n
< num_operands
; n
++)
2580 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2581 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2588 /* Convert from BFD relocation type code to slot and operand number.
2589 Returns non-zero on failure. */
2592 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2594 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2595 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2597 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2600 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2601 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2603 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2613 /* Convert from slot number to BFD relocation type code for the
2614 standard PC-relative relocations. Return BFD_RELOC_NONE on
2617 static bfd_reloc_code_real_type
2618 encode_reloc (int slot
)
2620 if (slot
< 0 || slot
> 14)
2621 return BFD_RELOC_NONE
;
2623 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2627 /* Convert from slot numbers to BFD relocation type code for the
2628 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2630 static bfd_reloc_code_real_type
2631 encode_alt_reloc (int slot
)
2633 if (slot
< 0 || slot
> 14)
2634 return BFD_RELOC_NONE
;
2636 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2641 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2644 xtensa_opcode opcode
,
2650 uint32 valbuf
= value
;
2652 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2654 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2656 as_bad_where ((char *) file
, line
,
2657 _("operand %d of '%s' has out of range value '%u'"),
2659 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2662 as_bad_where ((char *) file
, line
,
2663 _("operand %d of '%s' has invalid value '%u'"),
2665 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2670 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2676 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2679 xtensa_opcode opcode
,
2683 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2684 fmt
, slot
, slotbuf
, &val
);
2685 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2690 /* Checks for rules from xtensa-relax tables. */
2692 /* The routine xg_instruction_matches_option_term must return TRUE
2693 when a given option term is true. The meaning of all of the option
2694 terms is given interpretation by this function. This is needed when
2695 an option depends on the state of a directive, but there are no such
2696 options in use right now. */
2699 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2700 const ReqOrOption
*option
)
2702 if (strcmp (option
->option_name
, "realnop") == 0
2703 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2705 /* These conditions were evaluated statically when building the
2706 relaxation table. There's no need to reevaluate them now. */
2711 as_fatal (_("internal error: unknown option name '%s'"),
2712 option
->option_name
);
2718 xg_instruction_matches_or_options (TInsn
*insn
,
2719 const ReqOrOptionList
*or_option
)
2721 const ReqOrOption
*option
;
2722 /* Must match each of the AND terms. */
2723 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2725 if (xg_instruction_matches_option_term (insn
, option
))
2733 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2735 const ReqOption
*req_options
;
2736 /* Must match each of the AND terms. */
2737 for (req_options
= options
;
2738 req_options
!= NULL
;
2739 req_options
= req_options
->next
)
2741 /* Must match one of the OR clauses. */
2742 if (!xg_instruction_matches_or_options (insn
,
2743 req_options
->or_option_terms
))
2750 /* Return the transition rule that matches or NULL if none matches. */
2753 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2755 PreconditionList
*condition_l
;
2757 if (rule
->opcode
!= insn
->opcode
)
2760 for (condition_l
= rule
->conditions
;
2761 condition_l
!= NULL
;
2762 condition_l
= condition_l
->next
)
2766 Precondition
*cond
= condition_l
->precond
;
2771 /* The expression must be the constant. */
2772 assert (cond
->op_num
< insn
->ntok
);
2773 exp1
= &insn
->tok
[cond
->op_num
];
2774 if (expr_is_const (exp1
))
2779 if (get_expr_const (exp1
) != cond
->op_data
)
2783 if (get_expr_const (exp1
) == cond
->op_data
)
2790 else if (expr_is_register (exp1
))
2795 if (get_expr_register (exp1
) != cond
->op_data
)
2799 if (get_expr_register (exp1
) == cond
->op_data
)
2811 assert (cond
->op_num
< insn
->ntok
);
2812 assert (cond
->op_data
< insn
->ntok
);
2813 exp1
= &insn
->tok
[cond
->op_num
];
2814 exp2
= &insn
->tok
[cond
->op_data
];
2819 if (!expr_is_equal (exp1
, exp2
))
2823 if (expr_is_equal (exp1
, exp2
))
2835 if (!xg_instruction_matches_options (insn
, rule
->options
))
2843 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2845 bfd_boolean a_greater
= FALSE
;
2846 bfd_boolean b_greater
= FALSE
;
2848 ReqOptionList
*l_a
= a
->options
;
2849 ReqOptionList
*l_b
= b
->options
;
2851 /* We only care if they both are the same except for
2852 a const16 vs. an l32r. */
2854 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2856 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2857 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2858 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2860 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2862 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2864 /* This is the case we care about. */
2865 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2866 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2873 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2874 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2884 l_or_a
= l_or_a
->next
;
2885 l_or_b
= l_or_b
->next
;
2887 if (l_or_a
|| l_or_b
)
2896 /* Incomparable if the substitution was used differently in two cases. */
2897 if (a_greater
&& b_greater
)
2909 static TransitionRule
*
2910 xg_instruction_match (TInsn
*insn
)
2912 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2914 assert (insn
->opcode
< table
->num_opcodes
);
2916 /* Walk through all of the possible transitions. */
2917 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2919 TransitionRule
*rule
= l
->rule
;
2920 if (xg_instruction_matches_rule (insn
, rule
))
2927 /* Various Other Internal Functions. */
2930 is_unique_insn_expansion (TransitionRule
*r
)
2932 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2934 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2940 /* Check if there is exactly one relaxation for INSN that converts it to
2941 another instruction of equal or larger size. If so, and if TARG is
2942 non-null, go ahead and generate the relaxed instruction into TARG. If
2943 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2944 instruction, i.e., ignore relaxations that convert to an instruction of
2945 equal size. In some contexts where this function is used, only
2946 a single widening is allowed and the NARROW_ONLY argument is used to
2947 exclude cases like ADDI being "widened" to an ADDMI, which may
2948 later be relaxed to an ADDMI/ADDI pair. */
2951 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2953 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2955 TransitionRule
*match
= 0;
2957 assert (insn
->insn_type
== ITYPE_INSN
);
2958 assert (insn
->opcode
< table
->num_opcodes
);
2960 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2962 TransitionRule
*rule
= l
->rule
;
2964 if (xg_instruction_matches_rule (insn
, rule
)
2965 && is_unique_insn_expansion (rule
)
2966 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2967 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2978 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2983 /* Return the maximum number of bytes this opcode can expand to. */
2986 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2988 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2990 int max_size
= xg_get_single_size (opcode
);
2992 assert (opcode
< table
->num_opcodes
);
2994 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2996 TransitionRule
*rule
= l
->rule
;
2997 BuildInstr
*build_list
;
3002 build_list
= rule
->to_instr
;
3003 if (is_unique_insn_expansion (rule
))
3005 assert (build_list
->typ
== INSTR_INSTR
);
3006 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3009 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3011 switch (build_list
->typ
)
3014 this_size
+= xg_get_single_size (build_list
->opcode
);
3016 case INSTR_LITERAL_DEF
:
3017 case INSTR_LABEL_DEF
:
3022 if (this_size
> max_size
)
3023 max_size
= this_size
;
3029 /* Return the maximum number of literal bytes this opcode can generate. */
3032 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3034 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3038 assert (opcode
< table
->num_opcodes
);
3040 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3042 TransitionRule
*rule
= l
->rule
;
3043 BuildInstr
*build_list
;
3048 build_list
= rule
->to_instr
;
3049 if (is_unique_insn_expansion (rule
))
3051 assert (build_list
->typ
== INSTR_INSTR
);
3052 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3055 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3057 switch (build_list
->typ
)
3059 case INSTR_LITERAL_DEF
:
3060 /* Hard-coded 4-byte literal. */
3064 case INSTR_LABEL_DEF
:
3069 if (this_size
> max_size
)
3070 max_size
= this_size
;
3077 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3079 int steps_taken
= 0;
3080 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3083 assert (insn
->insn_type
== ITYPE_INSN
);
3084 assert (insn
->opcode
< table
->num_opcodes
);
3086 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3088 TransitionRule
*rule
= l
->rule
;
3090 if (xg_instruction_matches_rule (insn
, rule
))
3092 if (steps_taken
== lateral_steps
)
3102 get_special_literal_symbol (void)
3104 static symbolS
*sym
= NULL
;
3107 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3113 get_special_label_symbol (void)
3115 static symbolS
*sym
= NULL
;
3118 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3124 xg_valid_literal_expression (const expressionS
*exp
)
3142 /* This will check to see if the value can be converted into the
3143 operand type. It will return TRUE if it does not fit. */
3146 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3148 uint32 valbuf
= value
;
3149 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3155 /* Assumes: All immeds are constants. Check that all constants fit
3156 into their immeds; return FALSE if not. */
3159 xg_immeds_fit (const TInsn
*insn
)
3161 xtensa_isa isa
= xtensa_default_isa
;
3165 assert (insn
->insn_type
== ITYPE_INSN
);
3166 for (i
= 0; i
< n
; ++i
)
3168 const expressionS
*expr
= &insn
->tok
[i
];
3169 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3176 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3181 /* The symbol should have a fixup associated with it. */
3190 /* This should only be called after we have an initial
3191 estimate of the addresses. */
3194 xg_symbolic_immeds_fit (const TInsn
*insn
,
3200 xtensa_isa isa
= xtensa_default_isa
;
3208 assert (insn
->insn_type
== ITYPE_INSN
);
3210 for (i
= 0; i
< n
; ++i
)
3212 const expressionS
*expr
= &insn
->tok
[i
];
3213 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3220 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3226 /* Check for the worst case. */
3227 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3232 /* We only allow symbols for PC-relative references.
3233 If pc_frag == 0, then we don't have frag locations yet. */
3235 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3238 /* If it is a weak symbol, then assume it won't reach. */
3239 if (S_IS_WEAK (expr
->X_add_symbol
))
3242 if (is_direct_call_opcode (insn
->opcode
)
3243 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3245 /* If callee is undefined or in a different segment, be
3246 optimistic and assume it will be in range. */
3247 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3251 /* Only references within a segment can be known to fit in the
3252 operands at assembly time. */
3253 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3256 symbolP
= expr
->X_add_symbol
;
3257 sym_frag
= symbol_get_frag (symbolP
);
3258 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3259 pc
= pc_frag
->fr_address
+ pc_offset
;
3261 /* If frag has yet to be reached on this pass, assume it
3262 will move by STRETCH just as we did. If this is not so,
3263 it will be because some frag between grows, and that will
3264 force another pass. Beware zero-length frags. There
3265 should be a faster way to do this. */
3268 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3269 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3274 new_offset
= target
;
3275 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3276 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3281 /* The symbol should have a fixup associated with it. */
3290 /* Return TRUE on success. */
3293 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3299 targ
->debug_line
= insn
->debug_line
;
3300 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3305 targ
->opcode
= bi
->opcode
;
3306 targ
->insn_type
= ITYPE_INSN
;
3307 targ
->is_specific_opcode
= FALSE
;
3309 for (; op
!= NULL
; op
= op
->next
)
3311 int op_num
= op
->op_num
;
3312 int op_data
= op
->op_data
;
3314 assert (op
->op_num
< MAX_INSN_ARGS
);
3316 if (targ
->ntok
<= op_num
)
3317 targ
->ntok
= op_num
+ 1;
3322 set_expr_const (&targ
->tok
[op_num
], op_data
);
3325 assert (op_data
< insn
->ntok
);
3326 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3329 sym
= get_special_literal_symbol ();
3330 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3333 sym
= get_special_label_symbol ();
3334 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3336 case OP_OPERAND_HI16U
:
3337 case OP_OPERAND_LOW16U
:
3338 assert (op_data
< insn
->ntok
);
3339 if (expr_is_const (&insn
->tok
[op_data
]))
3342 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3343 val
= xg_apply_userdef_op_fn (op
->typ
,
3346 targ
->tok
[op_num
].X_add_number
= val
;
3350 /* For const16 we can create relocations for these. */
3351 if (targ
->opcode
== XTENSA_UNDEFINED
3352 || (targ
->opcode
!= xtensa_const16_opcode
))
3354 assert (op_data
< insn
->ntok
);
3355 /* Need to build a O_lo16 or O_hi16. */
3356 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3357 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3359 if (op
->typ
== OP_OPERAND_HI16U
)
3360 targ
->tok
[op_num
].X_op
= O_hi16
;
3361 else if (op
->typ
== OP_OPERAND_LOW16U
)
3362 targ
->tok
[op_num
].X_op
= O_lo16
;
3369 /* currently handles:
3372 OP_OPERAND_F32MINUS */
3373 if (xg_has_userdef_op_fn (op
->typ
))
3375 assert (op_data
< insn
->ntok
);
3376 if (expr_is_const (&insn
->tok
[op_data
]))
3379 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3380 val
= xg_apply_userdef_op_fn (op
->typ
,
3383 targ
->tok
[op_num
].X_add_number
= val
;
3386 return FALSE
; /* We cannot use a relocation for this. */
3395 case INSTR_LITERAL_DEF
:
3397 targ
->opcode
= XTENSA_UNDEFINED
;
3398 targ
->insn_type
= ITYPE_LITERAL
;
3399 targ
->is_specific_opcode
= FALSE
;
3400 for (; op
!= NULL
; op
= op
->next
)
3402 int op_num
= op
->op_num
;
3403 int op_data
= op
->op_data
;
3404 assert (op
->op_num
< MAX_INSN_ARGS
);
3406 if (targ
->ntok
<= op_num
)
3407 targ
->ntok
= op_num
+ 1;
3412 assert (op_data
< insn
->ntok
);
3413 /* We can only pass resolvable literals through. */
3414 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3416 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3428 case INSTR_LABEL_DEF
:
3430 targ
->opcode
= XTENSA_UNDEFINED
;
3431 targ
->insn_type
= ITYPE_LABEL
;
3432 targ
->is_specific_opcode
= FALSE
;
3433 /* Literal with no ops is a label? */
3434 assert (op
== NULL
);
3445 /* Return TRUE on success. */
3448 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3450 for (; bi
!= NULL
; bi
= bi
->next
)
3452 TInsn
*next_insn
= istack_push_space (istack
);
3454 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3461 /* Return TRUE on valid expansion. */
3464 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3466 int stack_size
= istack
->ninsn
;
3467 int steps_taken
= 0;
3468 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3471 assert (insn
->insn_type
== ITYPE_INSN
);
3472 assert (insn
->opcode
< table
->num_opcodes
);
3474 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3476 TransitionRule
*rule
= l
->rule
;
3478 if (xg_instruction_matches_rule (insn
, rule
))
3480 if (lateral_steps
== steps_taken
)
3484 /* This is it. Expand the rule to the stack. */
3485 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3488 /* Check to see if it fits. */
3489 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3491 TInsn
*insn
= &istack
->insn
[i
];
3493 if (insn
->insn_type
== ITYPE_INSN
3494 && !tinsn_has_symbolic_operands (insn
)
3495 && !xg_immeds_fit (insn
))
3497 istack
->ninsn
= stack_size
;
3510 /* Relax the assembly instruction at least "min_steps".
3511 Return the number of steps taken.
3513 For relaxation to correctly terminate, every relaxation chain must
3514 terminate in one of two ways:
3516 1. If the chain from one instruction to the next consists entirely of
3517 single instructions, then the chain *must* handle all possible
3518 immediates without failing. It must not ever fail because an
3519 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3520 chain is one example. L32R loads 32 bits, and there cannot be an
3521 immediate larger than 32 bits, so it satisfies this condition.
3522 Single instruction relaxation chains are as defined by
3523 xg_is_single_relaxable_instruction.
3525 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3526 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3528 Strictly speaking, in most cases you can violate condition 1 and be OK
3529 -- in particular when the last two instructions have the same single
3530 size. But nevertheless, you should guarantee the above two conditions.
3532 We could fix this so that single-instruction expansions correctly
3533 terminate when they can't handle the range, but the error messages are
3534 worse, and it actually turns out that in every case but one (18-bit wide
3535 branches), you need a multi-instruction expansion to get the full range
3536 anyway. And because 18-bit branches are handled identically to 15-bit
3537 branches, there isn't any point in changing it. */
3540 xg_assembly_relax (IStack
*istack
,
3543 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3544 offsetT pc_offset
, /* offset in fragment */
3545 int min_steps
, /* minimum conversion steps */
3546 long stretch
) /* number of bytes stretched so far */
3548 int steps_taken
= 0;
3550 /* Some of its immeds don't fit. Try to build a relaxed version.
3551 This may go through a couple of stages of single instruction
3552 transformations before we get there. */
3554 TInsn single_target
;
3556 int lateral_steps
= 0;
3557 int istack_size
= istack
->ninsn
;
3559 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3560 && steps_taken
>= min_steps
)
3562 istack_push (istack
, insn
);
3565 current_insn
= *insn
;
3567 /* Walk through all of the single instruction expansions. */
3568 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3571 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3574 if (steps_taken
>= min_steps
)
3576 istack_push (istack
, &single_target
);
3580 current_insn
= single_target
;
3583 /* Now check for a multi-instruction expansion. */
3584 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3586 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3589 if (steps_taken
>= min_steps
)
3591 istack_push (istack
, ¤t_insn
);
3596 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3598 if (steps_taken
>= min_steps
)
3602 istack
->ninsn
= istack_size
;
3605 /* It's not going to work -- use the original. */
3606 istack_push (istack
, insn
);
3612 xg_finish_frag (char *last_insn
,
3613 enum xtensa_relax_statesE frag_state
,
3614 enum xtensa_relax_statesE slot0_state
,
3616 bfd_boolean is_insn
)
3618 /* Finish off this fragment so that it has at LEAST the desired
3619 max_growth. If it doesn't fit in this fragment, close this one
3620 and start a new one. In either case, return a pointer to the
3621 beginning of the growth area. */
3625 frag_grow (max_growth
);
3626 old_frag
= frag_now
;
3628 frag_now
->fr_opcode
= last_insn
;
3630 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3632 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3633 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3635 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3636 xtensa_set_frag_assembly_state (frag_now
);
3638 /* Just to make sure that we did not split it up. */
3639 assert (old_frag
->fr_next
== frag_now
);
3643 /* Return TRUE if the target frag is one of the next non-empty frags. */
3646 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3651 for (; fragP
; fragP
= fragP
->fr_next
)
3653 if (fragP
== target
)
3655 if (fragP
->fr_fix
!= 0)
3657 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3659 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3660 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3662 if (fragP
->fr_type
== rs_space
)
3670 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3672 xtensa_isa isa
= xtensa_default_isa
;
3674 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3679 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3680 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3683 for (i
= 0; i
< num_ops
; i
++)
3685 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3691 if (target_op
== -1)
3694 if (insn
->ntok
<= target_op
)
3697 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3700 sym
= insn
->tok
[target_op
].X_add_symbol
;
3704 if (insn
->tok
[target_op
].X_add_number
!= 0)
3707 target_frag
= symbol_get_frag (sym
);
3708 if (target_frag
== NULL
)
3711 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3712 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3720 xg_add_branch_and_loop_targets (TInsn
*insn
)
3722 xtensa_isa isa
= xtensa_default_isa
;
3723 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3725 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3728 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3729 && insn
->tok
[i
].X_op
== O_symbol
)
3730 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3734 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3735 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3739 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3741 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3742 && insn
->tok
[i
].X_op
== O_symbol
)
3744 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3745 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3746 if (S_IS_DEFINED (sym
))
3747 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3754 /* Return FALSE if no error. */
3757 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3762 switch (instr_spec
->typ
)
3765 new_insn
->insn_type
= ITYPE_INSN
;
3766 new_insn
->opcode
= instr_spec
->opcode
;
3768 case INSTR_LITERAL_DEF
:
3769 new_insn
->insn_type
= ITYPE_LITERAL
;
3770 new_insn
->opcode
= XTENSA_UNDEFINED
;
3772 case INSTR_LABEL_DEF
:
3775 new_insn
->is_specific_opcode
= FALSE
;
3776 new_insn
->debug_line
= old_insn
->debug_line
;
3777 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3779 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3782 const expressionS
*src_exp
;
3788 /* The expression must be the constant. */
3789 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3790 exp
= &new_insn
->tok
[b_op
->op_num
];
3791 set_expr_const (exp
, b_op
->op_data
);
3795 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3796 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3797 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3798 exp
= &new_insn
->tok
[b_op
->op_num
];
3799 copy_expr (exp
, src_exp
);
3804 as_bad (_("can't handle generation of literal/labels yet"));
3808 as_bad (_("can't handle undefined OP TYPE"));
3813 new_insn
->ntok
= num_ops
;
3818 /* Return TRUE if it was simplified. */
3821 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3823 TransitionRule
*rule
;
3824 BuildInstr
*insn_spec
;
3826 if (old_insn
->is_specific_opcode
|| !density_supported
)
3829 rule
= xg_instruction_match (old_insn
);
3833 insn_spec
= rule
->to_instr
;
3834 /* There should only be one. */
3835 assert (insn_spec
!= NULL
);
3836 assert (insn_spec
->next
== NULL
);
3837 if (insn_spec
->next
!= NULL
)
3840 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3846 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3847 l32i.n. (2) Check the number of operands. (3) Place the instruction
3848 tokens into the stack or relax it and place multiple
3849 instructions/literals onto the stack. Return FALSE if no error. */
3852 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3856 bfd_boolean do_expand
;
3858 tinsn_init (&new_insn
);
3860 /* Narrow it if we can. xg_simplify_insn now does all the
3861 appropriate checking (e.g., for the density option). */
3862 if (xg_simplify_insn (orig_insn
, &new_insn
))
3863 orig_insn
= &new_insn
;
3865 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3867 if (orig_insn
->ntok
< noperands
)
3869 as_bad (_("found %d operands for '%s': Expected %d"),
3871 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3875 if (orig_insn
->ntok
> noperands
)
3876 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3878 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3881 /* If there are not enough operands, we will assert above. If there
3882 are too many, just cut out the extras here. */
3883 orig_insn
->ntok
= noperands
;
3885 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3888 /* Special case for extui opcode which has constraints not handled
3889 by the ordinary operand encoding checks. The number of operands
3890 and related syntax issues have already been checked. */
3891 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3893 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3894 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3895 if (shiftimm
+ maskimm
> 32)
3897 as_bad (_("immediate operands sum to greater than 32"));
3902 /* If the instruction will definitely need to be relaxed, it is better
3903 to expand it now for better scheduling. Decide whether to expand
3905 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3907 /* Calls should be expanded to longcalls only in the backend relaxation
3908 so that the assembly scheduler will keep the L32R/CALLX instructions
3910 if (is_direct_call_opcode (orig_insn
->opcode
))
3913 if (tinsn_has_symbolic_operands (orig_insn
))
3915 /* The values of symbolic operands are not known yet, so only expand
3916 now if an operand is "complex" (e.g., difference of symbols) and
3917 will have to be stored as a literal regardless of the value. */
3918 if (!tinsn_has_complex_operands (orig_insn
))
3921 else if (xg_immeds_fit (orig_insn
))
3925 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3927 istack_push (istack
, orig_insn
);
3933 /* Return TRUE if the section flags are marked linkonce
3934 or the name is .gnu.linkonce.*. */
3936 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3939 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3941 flagword flags
, link_once_flags
;
3943 flags
= bfd_get_section_flags (abfd
, sec
);
3944 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3946 /* Flags might not be set yet. */
3947 if (!link_once_flags
3948 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3949 link_once_flags
= SEC_LINK_ONCE
;
3951 return (link_once_flags
!= 0);
3956 xtensa_add_literal_sym (symbolS
*sym
)
3960 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3962 l
->next
= literal_syms
;
3968 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3970 static int lit_num
= 0;
3971 static char name
[256];
3974 sprintf (name
, ".L_lit_sym%d", lit_num
);
3976 /* Create a local symbol. If it is in a linkonce section, we have to
3977 be careful to make sure that if it is used in a relocation that the
3978 symbol will be in the output file. */
3979 if (get_is_linkonce_section (stdoutput
, sec
))
3981 symbolP
= symbol_new (name
, sec
, 0, frag
);
3982 S_CLEAR_EXTERNAL (symbolP
);
3983 /* symbolP->local = 1; */
3986 symbolP
= symbol_new (name
, sec
, 0, frag
);
3988 xtensa_add_literal_sym (symbolP
);
3995 /* Currently all literals that are generated here are 32-bit L32R targets. */
3998 xg_assemble_literal (/* const */ TInsn
*insn
)
4001 symbolS
*lit_sym
= NULL
;
4002 bfd_reloc_code_real_type reloc
;
4003 bfd_boolean pcrel
= FALSE
;
4006 /* size = 4 for L32R. It could easily be larger when we move to
4007 larger constants. Add a parameter later. */
4008 offsetT litsize
= 4;
4009 offsetT litalign
= 2; /* 2^2 = 4 */
4010 expressionS saved_loc
;
4011 expressionS
* emit_val
;
4013 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4015 assert (insn
->insn_type
== ITYPE_LITERAL
);
4016 assert (insn
->ntok
== 1); /* must be only one token here */
4018 xtensa_switch_to_literal_fragment (&state
);
4020 emit_val
= &insn
->tok
[0];
4021 if (emit_val
->X_op
== O_big
)
4023 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4026 /* This happens when someone writes a "movi a2, big_number". */
4027 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4028 _("invalid immediate"));
4029 xtensa_restore_emit_state (&state
);
4034 /* Force a 4-byte align here. Note that this opens a new frag, so all
4035 literals done with this function have a frag to themselves. That's
4036 important for the way text section literals work. */
4037 frag_align (litalign
, 0, 0);
4038 record_alignment (now_seg
, litalign
);
4040 switch (emit_val
->X_op
)
4046 p
= frag_more (litsize
);
4047 xtensa_set_frag_assembly_state (frag_now
);
4048 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4049 if (emit_val
->X_add_symbol
)
4050 emit_val
->X_op
= O_symbol
;
4052 emit_val
->X_op
= O_constant
;
4053 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4054 litsize
, emit_val
, pcrel
, reloc
);
4058 emit_expr (emit_val
, litsize
);
4062 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4063 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4064 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4065 lit_sym
= frag_now
->fr_symbol
;
4068 xtensa_restore_emit_state (&state
);
4074 xg_assemble_literal_space (/* const */ int size
, int slot
)
4077 /* We might have to do something about this alignment. It only
4078 takes effect if something is placed here. */
4079 offsetT litalign
= 2; /* 2^2 = 4 */
4080 fragS
*lit_saved_frag
;
4082 assert (size
% 4 == 0);
4084 xtensa_switch_to_literal_fragment (&state
);
4086 /* Force a 4-byte align here. */
4087 frag_align (litalign
, 0, 0);
4088 record_alignment (now_seg
, litalign
);
4092 lit_saved_frag
= frag_now
;
4093 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4094 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4095 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4098 xtensa_restore_emit_state (&state
);
4099 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4103 /* Put in a fixup record based on the opcode.
4104 Return TRUE on success. */
4107 xg_add_opcode_fix (TInsn
*tinsn
,
4115 xtensa_opcode opcode
= tinsn
->opcode
;
4116 bfd_reloc_code_real_type reloc
;
4117 reloc_howto_type
*howto
;
4121 reloc
= BFD_RELOC_NONE
;
4123 /* First try the special cases for "alternate" relocs. */
4124 if (opcode
== xtensa_l32r_opcode
)
4126 if (fragP
->tc_frag_data
.use_absolute_literals
)
4127 reloc
= encode_alt_reloc (slot
);
4129 else if (opcode
== xtensa_const16_opcode
)
4131 if (expr
->X_op
== O_lo16
)
4133 reloc
= encode_reloc (slot
);
4134 expr
->X_op
= O_symbol
;
4136 else if (expr
->X_op
== O_hi16
)
4138 reloc
= encode_alt_reloc (slot
);
4139 expr
->X_op
= O_symbol
;
4143 if (opnum
!= get_relaxable_immed (opcode
))
4145 as_bad (_("invalid relocation for operand %i of '%s'"),
4146 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4150 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4151 into the symbol table where the generic portions of the assembler
4152 won't know what to do with them. */
4153 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4155 as_bad (_("invalid expression for operand %i of '%s'"),
4156 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4160 /* Next try the generic relocs. */
4161 if (reloc
== BFD_RELOC_NONE
)
4162 reloc
= encode_reloc (slot
);
4163 if (reloc
== BFD_RELOC_NONE
)
4165 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4169 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4172 as_bad (_("undefined symbol for opcode \"%s\""),
4173 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4177 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4178 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4179 howto
->pc_relative
, reloc
);
4180 the_fix
->fx_no_overflow
= 1;
4181 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4182 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4183 the_fix
->tc_fix_data
.slot
= slot
;
4190 xg_emit_insn_to_buf (TInsn
*tinsn
,
4194 bfd_boolean build_fix
)
4196 static xtensa_insnbuf insnbuf
= NULL
;
4197 bfd_boolean has_symbolic_immed
= FALSE
;
4198 bfd_boolean ok
= TRUE
;
4201 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4203 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4204 if (has_symbolic_immed
&& build_fix
)
4207 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4208 int slot
= xg_get_single_slot (tinsn
->opcode
);
4209 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4210 expressionS
*exp
= &tinsn
->tok
[opnum
];
4212 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4215 fragP
->tc_frag_data
.is_insn
= TRUE
;
4216 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4217 (unsigned char *) buf
, 0);
4223 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4225 symbolS
*sym
= get_special_literal_symbol ();
4229 assert (insn
->insn_type
== ITYPE_INSN
);
4230 for (i
= 0; i
< insn
->ntok
; i
++)
4231 if (insn
->tok
[i
].X_add_symbol
== sym
)
4232 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4238 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4240 symbolS
*sym
= get_special_label_symbol ();
4242 for (i
= 0; i
< insn
->ntok
; i
++)
4243 if (insn
->tok
[i
].X_add_symbol
== sym
)
4244 insn
->tok
[i
].X_add_symbol
= label_sym
;
4249 /* Return TRUE if the instruction can write to the specified
4250 integer register. */
4253 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4257 xtensa_isa isa
= xtensa_default_isa
;
4259 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4261 for (i
= 0; i
< num_ops
; i
++)
4264 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4265 if ((inout
== 'o' || inout
== 'm')
4266 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4268 xtensa_regfile opnd_rf
=
4269 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4270 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4272 if ((insn
->tok
[i
].X_op
== O_register
)
4273 && (insn
->tok
[i
].X_add_number
== regnum
))
4283 is_bad_loopend_opcode (const TInsn
*tinsn
)
4285 xtensa_opcode opcode
= tinsn
->opcode
;
4287 if (opcode
== XTENSA_UNDEFINED
)
4290 if (opcode
== xtensa_call0_opcode
4291 || opcode
== xtensa_callx0_opcode
4292 || opcode
== xtensa_call4_opcode
4293 || opcode
== xtensa_callx4_opcode
4294 || opcode
== xtensa_call8_opcode
4295 || opcode
== xtensa_callx8_opcode
4296 || opcode
== xtensa_call12_opcode
4297 || opcode
== xtensa_callx12_opcode
4298 || opcode
== xtensa_isync_opcode
4299 || opcode
== xtensa_ret_opcode
4300 || opcode
== xtensa_ret_n_opcode
4301 || opcode
== xtensa_retw_opcode
4302 || opcode
== xtensa_retw_n_opcode
4303 || opcode
== xtensa_waiti_opcode
4304 || opcode
== xtensa_rsr_lcount_opcode
)
4311 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4312 This allows the debugger to add unaligned labels.
4313 Also, the assembler generates stabs labels that need
4314 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4317 is_unaligned_label (symbolS
*sym
)
4319 const char *name
= S_GET_NAME (sym
);
4320 static size_t fake_size
= 0;
4324 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4327 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4329 fake_size
= strlen (FAKE_LABEL_NAME
);
4332 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4333 && (name
[fake_size
] == 'F'
4334 || name
[fake_size
] == 'L'
4335 || (name
[fake_size
] == 'e'
4336 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4344 next_non_empty_frag (const fragS
*fragP
)
4346 fragS
*next_fragP
= fragP
->fr_next
;
4348 /* Sometimes an empty will end up here due storage allocation issues.
4349 So we have to skip until we find something legit. */
4350 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4351 next_fragP
= next_fragP
->fr_next
;
4353 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4361 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4363 xtensa_opcode out_opcode
;
4364 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4366 if (next_fragP
== NULL
)
4369 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4370 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4372 *opcode
= out_opcode
;
4380 frag_format_size (const fragS
*fragP
)
4382 static xtensa_insnbuf insnbuf
= NULL
;
4383 xtensa_isa isa
= xtensa_default_isa
;
4388 insnbuf
= xtensa_insnbuf_alloc (isa
);
4391 return XTENSA_UNDEFINED
;
4393 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4394 (unsigned char *) fragP
->fr_literal
, 0);
4396 fmt
= xtensa_format_decode (isa
, insnbuf
);
4397 if (fmt
== XTENSA_UNDEFINED
)
4398 return XTENSA_UNDEFINED
;
4399 fmt_size
= xtensa_format_length (isa
, fmt
);
4401 /* If the next format won't be changing due to relaxation, just
4402 return the length of the first format. */
4403 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4406 /* If during relaxation we have to pull an instruction out of a
4407 multi-slot instruction, we will return the more conservative
4408 number. This works because alignment on bigger instructions
4409 is more restrictive than alignment on smaller instructions.
4410 This is more conservative than we would like, but it happens
4413 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4416 /* If we aren't doing one of our own relaxations or it isn't
4417 slot-based, then the insn size won't change. */
4418 if (fragP
->fr_type
!= rs_machine_dependent
)
4420 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4423 /* If an instruction is about to grow, return the longer size. */
4424 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4425 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4426 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4428 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4429 instruction in the relaxed version is of length 3. (The case
4430 where we have to pull the instruction out of a FLIX bundle
4431 is handled conservatively above.) However, frags with opcodes
4432 that are expanding to wide branches end up having formats that
4433 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4434 we can't tell directly what format the relaxer picked. This
4435 is a wart in the design of the relaxer that should someday be
4436 fixed, but would require major changes, or at least should
4437 be accompanied by major changes to make use of that data.
4439 In any event, we can tell that we are expanding from a single-slot
4440 three-byte format to a wider one with the logic below. */
4442 if (fmt_size
<= 3 && fragP
->tc_frag_data
.text_expansion
[0] != 3)
4443 return 3 + fragP
->tc_frag_data
.text_expansion
[0];
4448 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4449 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4456 next_frag_format_size (const fragS
*fragP
)
4458 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4459 return frag_format_size (next_fragP
);
4463 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4464 required two-byte instructions to be treated as three-byte instructions
4465 for loop instruction alignment. This restriction was removed beginning
4466 with Xtensa LX. Now the only requirement on loop instruction alignment
4467 is that the first instruction of the loop must appear at an address that
4468 does not cross a fetch boundary. */
4471 get_loop_align_size (int insn_size
)
4473 if (insn_size
== XTENSA_UNDEFINED
)
4474 return xtensa_fetch_width
;
4476 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4483 /* If the next legit fragment is an end-of-loop marker,
4484 switch its state so it will instantiate a NOP. */
4487 update_next_frag_state (fragS
*fragP
)
4489 fragS
*next_fragP
= fragP
->fr_next
;
4490 fragS
*new_target
= NULL
;
4494 /* We are guaranteed there will be one of these... */
4495 while (!(next_fragP
->fr_type
== rs_machine_dependent
4496 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4497 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4498 next_fragP
= next_fragP
->fr_next
;
4500 assert (next_fragP
->fr_type
== rs_machine_dependent
4501 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4502 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4504 /* ...and one of these. */
4505 new_target
= next_fragP
->fr_next
;
4506 while (!(new_target
->fr_type
== rs_machine_dependent
4507 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4508 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4509 new_target
= new_target
->fr_next
;
4511 assert (new_target
->fr_type
== rs_machine_dependent
4512 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4513 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4516 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4518 if (next_fragP
->fr_type
== rs_machine_dependent
4519 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4521 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4525 next_fragP
= next_fragP
->fr_next
;
4531 next_frag_is_branch_target (const fragS
*fragP
)
4533 /* Sometimes an empty will end up here due to storage allocation issues,
4534 so we have to skip until we find something legit. */
4535 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4537 if (fragP
->tc_frag_data
.is_branch_target
)
4539 if (fragP
->fr_fix
!= 0)
4547 next_frag_is_loop_target (const fragS
*fragP
)
4549 /* Sometimes an empty will end up here due storage allocation issues.
4550 So we have to skip until we find something legit. */
4551 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4553 if (fragP
->tc_frag_data
.is_loop_target
)
4555 if (fragP
->fr_fix
!= 0)
4563 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4565 const fragS
*next_fragp
= fragp
->fr_next
;
4566 xtensa_opcode next_opcode
;
4568 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4571 /* Sometimes an empty will end up here due to storage allocation issues,
4572 so we have to skip until we find something legit. */
4573 while (next_fragp
->fr_fix
== 0)
4574 next_fragp
= next_fragp
->fr_next
;
4576 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4579 /* There is some implicit knowledge encoded in here.
4580 The LOOP instructions that are NOT RELAX_IMMED have
4581 been relaxed. Note that we can assume that the LOOP
4582 instruction is in slot 0 because loops aren't bundleable. */
4583 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4584 return get_expanded_loop_offset (next_opcode
);
4590 /* Mark a location where we can later insert literal frags. Update
4591 the section's literal_pool_loc, so subsequent literals can be
4592 placed nearest to their use. */
4595 xtensa_mark_literal_pool_location (void)
4597 /* Any labels pointing to the current location need
4598 to be adjusted to after the literal pool. */
4600 fragS
*pool_location
;
4602 if (use_literal_section
)
4605 /* We stash info in these frags so we can later move the literal's
4606 fixes into this frchain's fix list. */
4607 pool_location
= frag_now
;
4608 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4609 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4610 frag_variant (rs_machine_dependent
, 0, 0,
4611 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4612 xtensa_set_frag_assembly_state (frag_now
);
4613 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4614 frag_variant (rs_machine_dependent
, 0, 0,
4615 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4616 xtensa_set_frag_assembly_state (frag_now
);
4618 /* Now put a frag into the literal pool that points to this location. */
4619 set_literal_pool_location (now_seg
, pool_location
);
4620 xtensa_switch_to_non_abs_literal_fragment (&s
);
4621 frag_align (2, 0, 0);
4622 record_alignment (now_seg
, 2);
4624 /* Close whatever frag is there. */
4625 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4626 xtensa_set_frag_assembly_state (frag_now
);
4627 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4628 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4629 xtensa_restore_emit_state (&s
);
4630 xtensa_set_frag_assembly_state (frag_now
);
4634 /* Build a nop of the correct size into tinsn. */
4637 build_nop (TInsn
*tinsn
, int size
)
4643 tinsn
->opcode
= xtensa_nop_n_opcode
;
4645 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4646 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4650 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4652 tinsn
->opcode
= xtensa_or_opcode
;
4653 set_expr_const (&tinsn
->tok
[0], 1);
4654 set_expr_const (&tinsn
->tok
[1], 1);
4655 set_expr_const (&tinsn
->tok
[2], 1);
4659 tinsn
->opcode
= xtensa_nop_opcode
;
4661 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4666 /* Assemble a NOP of the requested size in the buffer. User must have
4667 allocated "buf" with at least "size" bytes. */
4670 assemble_nop (int size
, char *buf
)
4672 static xtensa_insnbuf insnbuf
= NULL
;
4675 build_nop (&tinsn
, size
);
4678 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4680 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4681 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4682 (unsigned char *) buf
, 0);
4686 /* Return the number of bytes for the offset of the expanded loop
4687 instruction. This should be incorporated into the relaxation
4688 specification but is hard-coded here. This is used to auto-align
4689 the loop instruction. It is invalid to call this function if the
4690 configuration does not have loops or if the opcode is not a loop
4694 get_expanded_loop_offset (xtensa_opcode opcode
)
4696 /* This is the OFFSET of the loop instruction in the expanded loop.
4697 This MUST correspond directly to the specification of the loop
4698 expansion. It will be validated on fragment conversion. */
4699 assert (opcode
!= XTENSA_UNDEFINED
);
4700 if (opcode
== xtensa_loop_opcode
)
4702 if (opcode
== xtensa_loopnez_opcode
)
4704 if (opcode
== xtensa_loopgtz_opcode
)
4706 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4712 get_literal_pool_location (segT seg
)
4714 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4719 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4721 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4725 /* Set frag assembly state should be called when a new frag is
4726 opened and after a frag has been closed. */
4729 xtensa_set_frag_assembly_state (fragS
*fragP
)
4731 if (!density_supported
)
4732 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4734 /* This function is called from subsegs_finish, which is called
4735 after xtensa_end, so we can't use "use_transform" or
4736 "use_schedule" here. */
4737 if (!directive_state
[directive_transform
])
4738 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4739 if (directive_state
[directive_longcalls
])
4740 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4741 fragP
->tc_frag_data
.use_absolute_literals
=
4742 directive_state
[directive_absolute_literals
];
4743 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4748 relaxable_section (asection
*sec
)
4750 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4751 && strcmp (sec
->name
, ".eh_frame") != 0);
4756 xtensa_mark_frags_for_org (void)
4760 /* Walk over each fragment of all of the current segments. If we find
4761 a .org frag in any of the segments, mark all frags prior to it as
4762 "no transform", which will prevent linker optimizations from messing
4763 up the .org distance. This should be done after
4764 xtensa_find_unmarked_state_frags, because we don't want to worry here
4765 about that function trashing the data we save here. */
4767 for (seclist
= &stdoutput
->sections
;
4768 seclist
&& *seclist
;
4769 seclist
= &(*seclist
)->next
)
4771 segT sec
= *seclist
;
4772 segment_info_type
*seginfo
;
4775 flags
= bfd_get_section_flags (stdoutput
, sec
);
4776 if (flags
& SEC_DEBUGGING
)
4778 if (!(flags
& SEC_ALLOC
))
4781 seginfo
= seg_info (sec
);
4782 if (seginfo
&& seginfo
->frchainP
)
4784 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4785 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4786 fragP
= fragP
->fr_next
)
4788 /* cvt_frag_to_fill has changed the fr_type of org frags to
4789 rs_fill, so use the value as cached in rs_subtype here. */
4790 if (fragP
->fr_subtype
== RELAX_ORG
)
4792 while (last_fragP
!= fragP
->fr_next
)
4794 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4795 last_fragP
= last_fragP
->fr_next
;
4805 xtensa_find_unmarked_state_frags (void)
4809 /* Walk over each fragment of all of the current segments. For each
4810 unmarked fragment, mark it with the same info as the previous
4812 for (seclist
= &stdoutput
->sections
;
4813 seclist
&& *seclist
;
4814 seclist
= &(*seclist
)->next
)
4816 segT sec
= *seclist
;
4817 segment_info_type
*seginfo
;
4820 flags
= bfd_get_section_flags (stdoutput
, sec
);
4821 if (flags
& SEC_DEBUGGING
)
4823 if (!(flags
& SEC_ALLOC
))
4826 seginfo
= seg_info (sec
);
4827 if (seginfo
&& seginfo
->frchainP
)
4829 fragS
*last_fragP
= 0;
4830 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4831 fragP
= fragP
->fr_next
)
4833 if (fragP
->fr_fix
!= 0
4834 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4836 if (last_fragP
== 0)
4838 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4839 _("assembly state not set for first frag in section %s"),
4844 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4845 fragP
->tc_frag_data
.is_no_density
=
4846 last_fragP
->tc_frag_data
.is_no_density
;
4847 fragP
->tc_frag_data
.is_no_transform
=
4848 last_fragP
->tc_frag_data
.is_no_transform
;
4849 fragP
->tc_frag_data
.use_longcalls
=
4850 last_fragP
->tc_frag_data
.use_longcalls
;
4851 fragP
->tc_frag_data
.use_absolute_literals
=
4852 last_fragP
->tc_frag_data
.use_absolute_literals
;
4855 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4864 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4866 void *unused ATTRIBUTE_UNUSED
)
4868 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4869 segment_info_type
*seginfo
= seg_info (sec
);
4870 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4872 if (flags
& SEC_CODE
)
4874 xtensa_isa isa
= xtensa_default_isa
;
4875 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4876 while (frag
!= NULL
)
4878 if (frag
->tc_frag_data
.is_branch_target
)
4881 addressT branch_align
, frag_addr
;
4884 xtensa_insnbuf_from_chars
4885 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4886 fmt
= xtensa_format_decode (isa
, insnbuf
);
4887 op_size
= xtensa_format_length (isa
, fmt
);
4888 branch_align
= 1 << branch_align_power (sec
);
4889 frag_addr
= frag
->fr_address
% branch_align
;
4890 if (frag_addr
+ op_size
> branch_align
)
4891 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4892 _("unaligned branch target: %d bytes at 0x%lx"),
4893 op_size
, (long) frag
->fr_address
);
4895 frag
= frag
->fr_next
;
4897 xtensa_insnbuf_free (isa
, insnbuf
);
4903 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4905 void *unused ATTRIBUTE_UNUSED
)
4907 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4908 segment_info_type
*seginfo
= seg_info (sec
);
4909 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4910 xtensa_isa isa
= xtensa_default_isa
;
4912 if (flags
& SEC_CODE
)
4914 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4915 while (frag
!= NULL
)
4917 if (frag
->tc_frag_data
.is_first_loop_insn
)
4923 xtensa_insnbuf_from_chars
4924 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4925 fmt
= xtensa_format_decode (isa
, insnbuf
);
4926 op_size
= xtensa_format_length (isa
, fmt
);
4927 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4929 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4930 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4931 _("unaligned loop: %d bytes at 0x%lx"),
4932 op_size
, (long) frag
->fr_address
);
4934 frag
= frag
->fr_next
;
4936 xtensa_insnbuf_free (isa
, insnbuf
);
4942 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4944 xtensa_isa isa
= xtensa_default_isa
;
4945 static xtensa_insnbuf insnbuf
= NULL
;
4946 static xtensa_insnbuf slotbuf
= NULL
;
4949 bfd_boolean alt_reloc
;
4950 xtensa_opcode opcode
;
4951 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4953 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4955 as_fatal (_("unexpected fix"));
4959 insnbuf
= xtensa_insnbuf_alloc (isa
);
4960 slotbuf
= xtensa_insnbuf_alloc (isa
);
4963 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4964 fmt
= xtensa_format_decode (isa
, insnbuf
);
4965 if (fmt
== XTENSA_UNDEFINED
)
4966 as_fatal (_("undecodable fix"));
4967 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4968 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4969 if (opcode
== XTENSA_UNDEFINED
)
4970 as_fatal (_("undecodable fix"));
4972 /* CONST16 immediates are not PC-relative, despite the fact that we
4973 reuse the normal PC-relative operand relocations for the low part
4974 of a CONST16 operand. */
4975 if (opcode
== xtensa_const16_opcode
)
4978 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4979 get_relaxable_immed (opcode
), val
,
4980 fixP
->fx_file
, fixP
->fx_line
);
4982 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4983 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4989 /* External Functions and Other GAS Hooks. */
4992 xtensa_target_format (void)
4994 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4999 xtensa_file_arch_init (bfd
*abfd
)
5001 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5006 md_number_to_chars (char *buf
, valueT val
, int n
)
5008 if (target_big_endian
)
5009 number_to_chars_bigendian (buf
, val
, n
);
5011 number_to_chars_littleendian (buf
, val
, n
);
5015 /* This function is called once, at assembler startup time. It should
5016 set up all the tables, etc. that the MD part of the assembler will
5022 segT current_section
= now_seg
;
5023 int current_subsec
= now_subseg
;
5026 xtensa_default_isa
= xtensa_isa_init (0, 0);
5027 isa
= xtensa_default_isa
;
5031 /* Set up the literal sections. */
5032 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5034 subseg_set (current_section
, current_subsec
);
5036 xg_init_vinsn (&cur_vinsn
);
5038 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5039 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5040 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5041 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5042 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5043 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5044 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5045 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5046 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5047 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5048 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5049 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5050 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5051 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5052 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5053 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5054 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5055 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5056 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5057 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5058 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5059 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5060 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5061 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5062 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5063 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5064 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5065 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5066 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5067 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5069 init_op_placement_info_table ();
5071 /* Set up the assembly state. */
5072 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5073 xtensa_set_frag_assembly_state (frag_now
);
5077 /* TC_INIT_FIX_DATA hook */
5080 xtensa_init_fix_data (fixS
*x
)
5082 x
->tc_fix_data
.slot
= 0;
5083 x
->tc_fix_data
.X_add_symbol
= NULL
;
5084 x
->tc_fix_data
.X_add_number
= 0;
5088 /* tc_frob_label hook */
5091 xtensa_frob_label (symbolS
*sym
)
5095 if (cur_vinsn
.inside_bundle
)
5097 as_bad (_("labels are not valid inside bundles"));
5101 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5103 /* Since the label was already attached to a frag associated with the
5104 previous basic block, it now needs to be reset to the current frag. */
5105 symbol_set_frag (sym
, frag_now
);
5106 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5108 if (generating_literals
)
5109 xtensa_add_literal_sym (sym
);
5111 xtensa_add_insn_label (sym
);
5113 if (symbol_get_tc (sym
)->is_loop_target
)
5115 if ((get_last_insn_flags (now_seg
, now_subseg
)
5116 & FLAG_IS_BAD_LOOPEND
) != 0)
5117 as_bad (_("invalid last instruction for a zero-overhead loop"));
5119 xtensa_set_frag_assembly_state (frag_now
);
5120 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5121 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5123 xtensa_set_frag_assembly_state (frag_now
);
5124 xtensa_move_labels (frag_now
, 0);
5127 /* No target aligning in the absolute section. */
5128 if (now_seg
!= absolute_section
5129 && do_align_targets ()
5130 && !is_unaligned_label (sym
)
5131 && !generating_literals
)
5133 xtensa_set_frag_assembly_state (frag_now
);
5135 frag_var (rs_machine_dependent
,
5137 RELAX_DESIRE_ALIGN_IF_TARGET
,
5138 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5139 xtensa_set_frag_assembly_state (frag_now
);
5140 xtensa_move_labels (frag_now
, 0);
5143 /* We need to mark the following properties even if we aren't aligning. */
5145 /* If the label is already known to be a branch target, i.e., a
5146 forward branch, mark the frag accordingly. Backward branches
5147 are handled by xg_add_branch_and_loop_targets. */
5148 if (symbol_get_tc (sym
)->is_branch_target
)
5149 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5151 /* Loops only go forward, so they can be identified here. */
5152 if (symbol_get_tc (sym
)->is_loop_target
)
5153 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5155 dwarf2_emit_label (sym
);
5159 /* tc_unrecognized_line hook */
5162 xtensa_unrecognized_line (int ch
)
5167 if (cur_vinsn
.inside_bundle
== 0)
5169 /* PR8110: Cannot emit line number info inside a FLIX bundle
5170 when using --gstabs. Temporarily disable debug info. */
5171 generate_lineno_debug ();
5172 if (debug_type
== DEBUG_STABS
)
5174 xt_saved_debug_type
= debug_type
;
5175 debug_type
= DEBUG_NONE
;
5178 cur_vinsn
.inside_bundle
= 1;
5182 as_bad (_("extra opening brace"));
5188 if (cur_vinsn
.inside_bundle
)
5189 finish_vinsn (&cur_vinsn
);
5192 as_bad (_("extra closing brace"));
5197 as_bad (_("syntax error"));
5204 /* md_flush_pending_output hook */
5207 xtensa_flush_pending_output (void)
5209 /* This line fixes a bug where automatically generated gstabs info
5210 separates a function label from its entry instruction, ending up
5211 with the literal position between the function label and the entry
5212 instruction and crashing code. It only happens with --gstabs and
5213 --text-section-literals, and when several other obscure relaxation
5214 conditions are met. */
5215 if (outputting_stabs_line_debug
)
5218 if (cur_vinsn
.inside_bundle
)
5219 as_bad (_("missing closing brace"));
5221 /* If there is a non-zero instruction fragment, close it. */
5222 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5224 frag_wane (frag_now
);
5226 xtensa_set_frag_assembly_state (frag_now
);
5228 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5230 xtensa_clear_insn_labels ();
5234 /* We had an error while parsing an instruction. The string might look
5235 like this: "insn arg1, arg2 }". If so, we need to see the closing
5236 brace and reset some fields. Otherwise, the vinsn never gets closed
5237 and the num_slots field will grow past the end of the array of slots,
5238 and bad things happen. */
5241 error_reset_cur_vinsn (void)
5243 if (cur_vinsn
.inside_bundle
)
5245 if (*input_line_pointer
== '}'
5246 || *(input_line_pointer
- 1) == '}'
5247 || *(input_line_pointer
- 2) == '}')
5248 xg_clear_vinsn (&cur_vinsn
);
5254 md_assemble (char *str
)
5256 xtensa_isa isa
= xtensa_default_isa
;
5259 bfd_boolean has_underbar
= FALSE
;
5260 char *arg_strings
[MAX_INSN_ARGS
];
5262 TInsn orig_insn
; /* Original instruction from the input. */
5264 tinsn_init (&orig_insn
);
5266 /* Split off the opcode. */
5267 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5268 opname
= xmalloc (opnamelen
+ 1);
5269 memcpy (opname
, str
, opnamelen
);
5270 opname
[opnamelen
] = '\0';
5272 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5275 as_bad (_("syntax error"));
5279 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5282 /* Check for an underbar prefix. */
5285 has_underbar
= TRUE
;
5289 orig_insn
.insn_type
= ITYPE_INSN
;
5291 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5293 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5294 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5296 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5297 if (fmt
== XTENSA_UNDEFINED
)
5299 as_bad (_("unknown opcode or format name '%s'"), opname
);
5300 error_reset_cur_vinsn ();
5303 if (!cur_vinsn
.inside_bundle
)
5305 as_bad (_("format names only valid inside bundles"));
5306 error_reset_cur_vinsn ();
5309 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5310 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5312 cur_vinsn
.format
= fmt
;
5313 free (has_underbar
? opname
- 1 : opname
);
5314 error_reset_cur_vinsn ();
5318 /* Parse the arguments. */
5319 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5321 as_bad (_("syntax error"));
5322 error_reset_cur_vinsn ();
5326 /* Free the opcode and argument strings, now that they've been parsed. */
5327 free (has_underbar
? opname
- 1 : opname
);
5329 while (num_args
-- > 0)
5330 free (arg_strings
[num_args
]);
5332 /* Get expressions for invisible operands. */
5333 if (get_invisible_operands (&orig_insn
))
5335 error_reset_cur_vinsn ();
5339 /* Check for the right number and type of arguments. */
5340 if (tinsn_check_arguments (&orig_insn
))
5342 error_reset_cur_vinsn ();
5346 /* Record the line number for each TInsn, because a FLIX bundle may be
5347 spread across multiple input lines and individual instructions may be
5348 moved around in some cases. */
5349 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5350 dwarf2_where (&orig_insn
.debug_line
);
5351 dwarf2_consume_line_info ();
5353 xg_add_branch_and_loop_targets (&orig_insn
);
5355 /* Check that immediate value for ENTRY is >= 16. */
5356 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5358 expressionS
*exp
= &orig_insn
.tok
[2];
5359 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5360 as_warn (_("entry instruction with stack decrement < 16"));
5364 assemble_tokens (opcode, tok, ntok);
5365 expand the tokens from the orig_insn into the
5366 stack of instructions that will not expand
5367 unless required at relaxation time. */
5369 if (!cur_vinsn
.inside_bundle
)
5370 emit_single_op (&orig_insn
);
5371 else /* We are inside a bundle. */
5373 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5374 cur_vinsn
.num_slots
++;
5375 if (*input_line_pointer
== '}'
5376 || *(input_line_pointer
- 1) == '}'
5377 || *(input_line_pointer
- 2) == '}')
5378 finish_vinsn (&cur_vinsn
);
5381 /* We've just emitted a new instruction so clear the list of labels. */
5382 xtensa_clear_insn_labels ();
5386 /* HANDLE_ALIGN hook */
5388 /* For a .align directive, we mark the previous block with the alignment
5389 information. This will be placed in the object file in the
5390 property section corresponding to this section. */
5393 xtensa_handle_align (fragS
*fragP
)
5396 && ! fragP
->tc_frag_data
.is_literal
5397 && (fragP
->fr_type
== rs_align
5398 || fragP
->fr_type
== rs_align_code
)
5399 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5400 && fragP
->fr_offset
> 0
5401 && now_seg
!= bss_section
)
5403 fragP
->tc_frag_data
.is_align
= TRUE
;
5404 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5407 if (fragP
->fr_type
== rs_align_test
)
5410 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5412 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5413 _("unaligned entry instruction"));
5416 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5417 fragP
->fr_subtype
= RELAX_ORG
;
5421 /* TC_FRAG_INIT hook */
5424 xtensa_frag_init (fragS
*frag
)
5426 xtensa_set_frag_assembly_state (frag
);
5431 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5437 /* Round up a section size to the appropriate boundary. */
5440 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5442 return size
; /* Byte alignment is fine. */
5447 md_pcrel_from (fixS
*fixP
)
5450 static xtensa_insnbuf insnbuf
= NULL
;
5451 static xtensa_insnbuf slotbuf
= NULL
;
5454 xtensa_opcode opcode
;
5457 xtensa_isa isa
= xtensa_default_isa
;
5458 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5459 bfd_boolean alt_reloc
;
5461 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5464 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5469 insnbuf
= xtensa_insnbuf_alloc (isa
);
5470 slotbuf
= xtensa_insnbuf_alloc (isa
);
5473 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5474 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5475 fmt
= xtensa_format_decode (isa
, insnbuf
);
5477 if (fmt
== XTENSA_UNDEFINED
)
5478 as_fatal (_("bad instruction format"));
5480 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5481 as_fatal (_("invalid relocation"));
5483 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5484 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5486 /* Check for "alternate" relocations (operand not specified). None
5487 of the current uses for these are really PC-relative. */
5488 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5490 if (opcode
!= xtensa_l32r_opcode
5491 && opcode
!= xtensa_const16_opcode
)
5492 as_fatal (_("invalid relocation for '%s' instruction"),
5493 xtensa_opcode_name (isa
, opcode
));
5497 opnum
= get_relaxable_immed (opcode
);
5499 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5500 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5502 as_bad_where (fixP
->fx_file
,
5504 _("invalid relocation for operand %d of '%s'"),
5505 opnum
, xtensa_opcode_name (isa
, opcode
));
5508 return 0 - opnd_value
;
5512 /* TC_FORCE_RELOCATION hook */
5515 xtensa_force_relocation (fixS
*fix
)
5517 switch (fix
->fx_r_type
)
5519 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5520 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5521 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5522 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5523 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5524 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5525 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5526 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5527 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5528 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5529 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5530 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5531 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5532 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5533 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5534 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5540 if (linkrelax
&& fix
->fx_addsy
5541 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5544 return generic_force_reloc (fix
);
5548 /* TC_VALIDATE_FIX_SUB hook */
5551 xtensa_validate_fix_sub (fixS
*fix
)
5553 segT add_symbol_segment
, sub_symbol_segment
;
5555 /* The difference of two symbols should be resolved by the assembler when
5556 linkrelax is not set. If the linker may relax the section containing
5557 the symbols, then an Xtensa DIFF relocation must be generated so that
5558 the linker knows to adjust the difference value. */
5559 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5562 /* Make sure both symbols are in the same segment, and that segment is
5563 "normal" and relaxable. If the segment is not "normal", then the
5564 fix is not valid. If the segment is not "relaxable", then the fix
5565 should have been handled earlier. */
5566 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5567 if (! SEG_NORMAL (add_symbol_segment
) ||
5568 ! relaxable_section (add_symbol_segment
))
5570 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5571 return (sub_symbol_segment
== add_symbol_segment
);
5575 /* NO_PSEUDO_DOT hook */
5577 /* This function has nothing to do with pseudo dots, but this is the
5578 nearest macro to where the check needs to take place. FIXME: This
5582 xtensa_check_inside_bundle (void)
5584 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5585 as_bad (_("directives are not valid inside bundles"));
5587 /* This function must always return FALSE because it is called via a
5588 macro that has nothing to do with bundling. */
5593 /* md_elf_section_change_hook */
5596 xtensa_elf_section_change_hook (void)
5598 /* Set up the assembly state. */
5599 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5600 xtensa_set_frag_assembly_state (frag_now
);
5604 /* tc_fix_adjustable hook */
5607 xtensa_fix_adjustable (fixS
*fixP
)
5609 /* An offset is not allowed in combination with the difference of two
5610 symbols, but that cannot be easily detected after a local symbol
5611 has been adjusted to a (section+offset) form. Return 0 so that such
5612 an fix will not be adjusted. */
5613 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5614 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5617 /* We need the symbol name for the VTABLE entries. */
5618 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5619 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5626 /* tc_symbol_new_hook */
5628 symbolS
*expr_symbols
= NULL
;
5631 xtensa_symbol_new_hook (symbolS
*sym
)
5633 if (S_GET_SEGMENT (sym
) == expr_section
)
5635 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5642 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5644 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5647 /* Subtracted symbols are only allowed for a few relocation types, and
5648 unless linkrelax is enabled, they should not make it to this point. */
5649 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5650 || fixP
->fx_r_type
== BFD_RELOC_16
5651 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5652 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5654 switch (fixP
->fx_r_type
)
5656 case BFD_RELOC_32_PCREL
:
5662 switch (fixP
->fx_r_type
)
5665 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5668 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5671 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5677 /* An offset is only allowed when it results from adjusting a
5678 local symbol into a section-relative offset. If the offset
5679 came from the original expression, tc_fix_adjustable will have
5680 prevented the fix from being converted to a section-relative
5681 form so that we can flag the error here. */
5682 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5684 _("cannot represent subtraction with an offset"));
5686 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5687 - S_GET_VALUE (fixP
->fx_subsy
));
5689 /* The difference value gets written out, and the DIFF reloc
5690 identifies the address of the subtracted symbol (i.e., the one
5691 with the lowest address). */
5693 fixP
->fx_offset
-= val
;
5694 fixP
->fx_subsy
= NULL
;
5696 else if (! fixP
->fx_addsy
)
5703 case BFD_RELOC_XTENSA_PLT
:
5704 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5705 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5708 case BFD_RELOC_XTENSA_SLOT0_OP
:
5709 case BFD_RELOC_XTENSA_SLOT1_OP
:
5710 case BFD_RELOC_XTENSA_SLOT2_OP
:
5711 case BFD_RELOC_XTENSA_SLOT3_OP
:
5712 case BFD_RELOC_XTENSA_SLOT4_OP
:
5713 case BFD_RELOC_XTENSA_SLOT5_OP
:
5714 case BFD_RELOC_XTENSA_SLOT6_OP
:
5715 case BFD_RELOC_XTENSA_SLOT7_OP
:
5716 case BFD_RELOC_XTENSA_SLOT8_OP
:
5717 case BFD_RELOC_XTENSA_SLOT9_OP
:
5718 case BFD_RELOC_XTENSA_SLOT10_OP
:
5719 case BFD_RELOC_XTENSA_SLOT11_OP
:
5720 case BFD_RELOC_XTENSA_SLOT12_OP
:
5721 case BFD_RELOC_XTENSA_SLOT13_OP
:
5722 case BFD_RELOC_XTENSA_SLOT14_OP
:
5725 /* Write the tentative value of a PC-relative relocation to a
5726 local symbol into the instruction. The value will be ignored
5727 by the linker, and it makes the object file disassembly
5728 readable when all branch targets are encoded in relocations. */
5730 assert (fixP
->fx_addsy
);
5731 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5732 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5734 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5735 - md_pcrel_from (fixP
));
5736 (void) xg_apply_fix_value (fixP
, val
);
5739 else if (! fixP
->fx_addsy
)
5742 if (xg_apply_fix_value (fixP
, val
))
5747 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5748 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5749 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5750 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5751 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5752 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5753 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5754 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5755 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5756 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5757 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5758 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5759 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5760 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5761 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5762 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5763 /* These all need to be resolved at link-time. Do nothing now. */
5766 case BFD_RELOC_VTABLE_INHERIT
:
5767 case BFD_RELOC_VTABLE_ENTRY
:
5772 as_bad (_("unhandled local relocation fix %s"),
5773 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5779 md_atof (int type
, char *litP
, int *sizeP
)
5781 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5786 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5788 return total_frag_text_expansion (fragP
);
5792 /* Translate internal representation of relocation info to BFD target
5796 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5800 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5801 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5802 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5803 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5805 /* Make sure none of our internal relocations make it this far.
5806 They'd better have been fully resolved by this point. */
5807 assert ((int) fixp
->fx_r_type
> 0);
5809 reloc
->addend
= fixp
->fx_offset
;
5811 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5812 if (reloc
->howto
== NULL
)
5814 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5815 _("cannot represent `%s' relocation in object file"),
5816 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5817 free (reloc
->sym_ptr_ptr
);
5822 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5823 as_fatal (_("internal error; cannot generate `%s' relocation"),
5824 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5830 /* Checks for resource conflicts between instructions. */
5832 /* The func unit stuff could be implemented as bit-vectors rather
5833 than the iterative approach here. If it ends up being too
5834 slow, we will switch it. */
5837 new_resource_table (void *data
,
5840 unit_num_copies_func uncf
,
5841 opcode_num_units_func onuf
,
5842 opcode_funcUnit_use_unit_func ouuf
,
5843 opcode_funcUnit_use_stage_func ousf
)
5846 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5848 rt
->cycles
= cycles
;
5849 rt
->allocated_cycles
= cycles
;
5851 rt
->unit_num_copies
= uncf
;
5852 rt
->opcode_num_units
= onuf
;
5853 rt
->opcode_unit_use
= ouuf
;
5854 rt
->opcode_unit_stage
= ousf
;
5856 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5857 for (i
= 0; i
< cycles
; i
++)
5858 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5865 clear_resource_table (resource_table
*rt
)
5868 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5869 for (j
= 0; j
< rt
->num_units
; j
++)
5870 rt
->units
[i
][j
] = 0;
5874 /* We never shrink it, just fake it into thinking so. */
5877 resize_resource_table (resource_table
*rt
, int cycles
)
5881 rt
->cycles
= cycles
;
5882 if (cycles
<= rt
->allocated_cycles
)
5885 old_cycles
= rt
->allocated_cycles
;
5886 rt
->allocated_cycles
= cycles
;
5888 rt
->units
= xrealloc (rt
->units
,
5889 rt
->allocated_cycles
* sizeof (unsigned char *));
5890 for (i
= 0; i
< old_cycles
; i
++)
5891 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5892 rt
->num_units
* sizeof (unsigned char));
5893 for (i
= old_cycles
; i
< cycles
; i
++)
5894 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5899 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5902 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5904 for (i
= 0; i
< uses
; i
++)
5906 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5907 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5908 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5909 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5910 if (copies_in_use
>= copies
)
5918 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5921 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5923 for (i
= 0; i
< uses
; i
++)
5925 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5926 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5927 /* Note that this allows resources to be oversubscribed. That's
5928 essential to the way the optional scheduler works.
5929 resources_available reports when a resource is over-subscribed,
5930 so it's easy to tell. */
5931 rt
->units
[stage
+ cycle
][unit
]++;
5937 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5940 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5942 for (i
= 0; i
< uses
; i
++)
5944 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5945 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5946 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5947 rt
->units
[stage
+ cycle
][unit
]--;
5952 /* Wrapper functions make parameterized resource reservation
5956 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5958 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5964 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5966 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5971 /* Note that this function does not check issue constraints, but
5972 solely whether the hardware is available to execute the given
5973 instructions together. It also doesn't check if the tinsns
5974 write the same state, or access the same tieports. That is
5975 checked by check_t1_t2_reads_and_writes. */
5978 resources_conflict (vliw_insn
*vinsn
)
5981 static resource_table
*rt
= NULL
;
5983 /* This is the most common case by far. Optimize it. */
5984 if (vinsn
->num_slots
== 1)
5989 xtensa_isa isa
= xtensa_default_isa
;
5990 rt
= new_resource_table
5991 (isa
, xtensa_isa_num_pipe_stages (isa
),
5992 xtensa_isa_num_funcUnits (isa
),
5993 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5994 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5995 opcode_funcUnit_use_unit
,
5996 opcode_funcUnit_use_stage
);
5999 clear_resource_table (rt
);
6001 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6003 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6005 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6012 /* finish_vinsn, emit_single_op and helper functions. */
6014 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6015 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6016 static void xg_assemble_vliw_tokens (vliw_insn
*);
6019 /* We have reached the end of a bundle; emit into the frag. */
6022 finish_vinsn (vliw_insn
*vinsn
)
6029 if (find_vinsn_conflicts (vinsn
))
6031 xg_clear_vinsn (vinsn
);
6035 /* First, find a format that works. */
6036 if (vinsn
->format
== XTENSA_UNDEFINED
)
6037 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6039 if (vinsn
->format
== XTENSA_UNDEFINED
)
6041 as_where (&file_name
, &line
);
6042 as_bad_where (file_name
, line
,
6043 _("couldn't find a valid instruction format"));
6044 fprintf (stderr
, _(" ops were: "));
6045 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6046 fprintf (stderr
, _(" %s;"),
6047 xtensa_opcode_name (xtensa_default_isa
,
6048 vinsn
->slots
[i
].opcode
));
6049 fprintf (stderr
, _("\n"));
6050 xg_clear_vinsn (vinsn
);
6054 if (vinsn
->num_slots
6055 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6057 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6058 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6059 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6061 xg_clear_vinsn (vinsn
);
6065 if (resources_conflict (vinsn
))
6067 as_where (&file_name
, &line
);
6068 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6069 fprintf (stderr
, " ops were: ");
6070 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6071 fprintf (stderr
, " %s;",
6072 xtensa_opcode_name (xtensa_default_isa
,
6073 vinsn
->slots
[i
].opcode
));
6074 fprintf (stderr
, "\n");
6075 xg_clear_vinsn (vinsn
);
6079 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6081 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6083 symbolS
*lit_sym
= NULL
;
6085 bfd_boolean e
= FALSE
;
6086 bfd_boolean saved_density
= density_supported
;
6088 /* We don't want to narrow ops inside multi-slot bundles. */
6089 if (vinsn
->num_slots
> 1)
6090 density_supported
= FALSE
;
6092 istack_init (&slotstack
);
6093 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6095 vinsn
->slots
[i
].opcode
=
6096 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6098 vinsn
->slots
[i
].ntok
= 0;
6101 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6107 density_supported
= saved_density
;
6111 xg_clear_vinsn (vinsn
);
6115 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6117 TInsn
*insn
= &slotstack
.insn
[j
];
6118 if (insn
->insn_type
== ITYPE_LITERAL
)
6120 assert (lit_sym
== NULL
);
6121 lit_sym
= xg_assemble_literal (insn
);
6125 assert (insn
->insn_type
== ITYPE_INSN
);
6127 xg_resolve_literals (insn
, lit_sym
);
6128 if (j
!= slotstack
.ninsn
- 1)
6129 emit_single_op (insn
);
6133 if (vinsn
->num_slots
> 1)
6135 if (opcode_fits_format_slot
6136 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6139 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6143 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6144 if (vinsn
->format
== XTENSA_UNDEFINED
)
6145 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6147 vinsn
->slots
[i
].opcode
6148 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6151 vinsn
->slots
[i
].ntok
= 0;
6156 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6157 vinsn
->format
= XTENSA_UNDEFINED
;
6162 /* Now check resource conflicts on the modified bundle. */
6163 if (resources_conflict (vinsn
))
6165 as_where (&file_name
, &line
);
6166 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6167 fprintf (stderr
, " ops were: ");
6168 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6169 fprintf (stderr
, " %s;",
6170 xtensa_opcode_name (xtensa_default_isa
,
6171 vinsn
->slots
[i
].opcode
));
6172 fprintf (stderr
, "\n");
6173 xg_clear_vinsn (vinsn
);
6177 /* First, find a format that works. */
6178 if (vinsn
->format
== XTENSA_UNDEFINED
)
6179 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6181 xg_assemble_vliw_tokens (vinsn
);
6183 xg_clear_vinsn (vinsn
);
6187 /* Given an vliw instruction, what conflicts are there in register
6188 usage and in writes to states and queues?
6190 This function does two things:
6191 1. Reports an error when a vinsn contains illegal combinations
6192 of writes to registers states or queues.
6193 2. Marks individual tinsns as not relaxable if the combination
6194 contains antidependencies.
6196 Job 2 handles things like swap semantics in instructions that need
6197 to be relaxed. For example,
6201 normally would be relaxed to
6206 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6208 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6210 then we can't relax it into
6213 { add a0, a1, a0 ; add a2, a0, a4 ; }
6215 because the value of a0 is trashed before the second add can read it. */
6217 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6220 find_vinsn_conflicts (vliw_insn
*vinsn
)
6224 xtensa_isa isa
= xtensa_default_isa
;
6226 assert (!past_xtensa_end
);
6228 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6230 TInsn
*op1
= &vinsn
->slots
[i
];
6231 if (op1
->is_specific_opcode
)
6232 op1
->keep_wide
= TRUE
;
6234 op1
->keep_wide
= FALSE
;
6237 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6239 TInsn
*op1
= &vinsn
->slots
[i
];
6241 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6244 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6248 TInsn
*op2
= &vinsn
->slots
[j
];
6249 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6250 switch (conflict_type
)
6253 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6254 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6255 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6258 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6259 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6260 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6263 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6264 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6265 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6268 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6269 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6270 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6273 /* Everything is OK. */
6276 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6277 || conflict_type
== 'a');
6284 as_bad (_("multiple branches or jumps in the same bundle"));
6292 /* Check how the state used by t1 and t2 relate.
6295 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6296 case B: no relationship between what is read and written (both could
6297 read the same reg though)
6298 case C: t1 writes a register t2 writes (a register conflict within a
6300 case D: t1 writes a state that t2 also writes
6301 case E: t1 writes a tie queue that t2 also writes
6302 case F: two volatile queue accesses
6306 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6308 xtensa_isa isa
= xtensa_default_isa
;
6309 xtensa_regfile t1_regfile
, t2_regfile
;
6311 int t1_base_reg
, t1_last_reg
;
6312 int t2_base_reg
, t2_last_reg
;
6313 char t1_inout
, t2_inout
;
6315 char conflict
= 'b';
6320 bfd_boolean t1_volatile
= FALSE
;
6321 bfd_boolean t2_volatile
= FALSE
;
6323 /* Check registers. */
6324 for (j
= 0; j
< t2
->ntok
; j
++)
6326 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6329 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6330 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6331 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6333 for (i
= 0; i
< t1
->ntok
; i
++)
6335 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6338 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6340 if (t1_regfile
!= t2_regfile
)
6343 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6344 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6346 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6347 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6349 if (t1_inout
== 'm' || t1_inout
== 'o'
6350 || t2_inout
== 'm' || t2_inout
== 'o')
6357 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6358 t1_last_reg
= (t1_base_reg
6359 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6361 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6363 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6365 if (t1_reg
!= t2_reg
)
6368 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6374 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6380 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6388 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6389 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6390 for (j
= 0; j
< t2_states
; j
++)
6392 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6393 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6394 for (i
= 0; i
< t1_states
; i
++)
6396 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6397 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6401 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6407 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6413 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6418 /* Check tieports. */
6419 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6420 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6421 for (j
= 0; j
< t2_interfaces
; j
++)
6423 xtensa_interface t2_int
6424 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6425 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6427 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6428 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6431 for (i
= 0; i
< t1_interfaces
; i
++)
6433 xtensa_interface t1_int
6434 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6435 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6437 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6438 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6441 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6444 if (t1_int
!= t2_int
)
6447 if (t2_inout
== 'i' && t1_inout
== 'o')
6453 if (t1_inout
== 'i' && t2_inout
== 'o')
6459 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6468 static xtensa_format
6469 xg_find_narrowest_format (vliw_insn
*vinsn
)
6471 /* Right now we assume that the ops within the vinsn are properly
6472 ordered for the slots that the programmer wanted them in. In
6473 other words, we don't rearrange the ops in hopes of finding a
6474 better format. The scheduler handles that. */
6476 xtensa_isa isa
= xtensa_default_isa
;
6477 xtensa_format format
;
6478 vliw_insn v_copy
= *vinsn
;
6479 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6481 if (vinsn
->num_slots
== 1)
6482 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6484 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6487 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6491 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6493 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6495 v_copy
.slots
[slot
].opcode
=
6496 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6497 v_copy
.slots
[slot
].ntok
= 0;
6500 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6503 else if (v_copy
.num_slots
> 1)
6506 /* Try the widened version. */
6507 if (!v_copy
.slots
[slot
].keep_wide
6508 && !v_copy
.slots
[slot
].is_specific_opcode
6509 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6511 && opcode_fits_format_slot (widened
.opcode
,
6514 v_copy
.slots
[slot
] = widened
;
6519 if (fit
== v_copy
.num_slots
)
6522 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6523 vinsn
->format
= format
;
6529 if (format
== xtensa_isa_num_formats (isa
))
6530 return XTENSA_UNDEFINED
;
6536 /* Return the additional space needed in a frag
6537 for possible relaxations of any ops in a VLIW insn.
6538 Also fill out the relaxations that might be required of
6539 each tinsn in the vinsn. */
6542 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6544 bfd_boolean finish_frag
= FALSE
;
6545 int extra_space
= 0;
6548 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6550 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6551 if (!tinsn_has_symbolic_operands (tinsn
))
6553 /* A narrow instruction could be widened later to help
6554 alignment issues. */
6555 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6556 && !tinsn
->is_specific_opcode
6557 && vinsn
->num_slots
== 1)
6559 /* Difference in bytes between narrow and wide insns... */
6561 tinsn
->subtype
= RELAX_NARROW
;
6566 if (workaround_b_j_loop_end
6567 && tinsn
->opcode
== xtensa_jx_opcode
6568 && use_transform ())
6570 /* Add 2 of these. */
6571 extra_space
+= 3; /* for the nop size */
6572 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6575 /* Need to assemble it with space for the relocation. */
6576 if (xg_is_relaxable_insn (tinsn
, 0)
6577 && !tinsn
->is_specific_opcode
)
6579 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6580 int max_literal_size
=
6581 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6583 tinsn
->literal_space
= max_literal_size
;
6585 tinsn
->subtype
= RELAX_IMMED
;
6586 extra_space
+= max_size
;
6590 /* A fix record will be added for this instruction prior
6591 to relaxation, so make it end the frag. */
6596 *pfinish_frag
= finish_frag
;
6602 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6604 xtensa_isa isa
= xtensa_default_isa
;
6605 int slot
, chosen_slot
;
6607 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6608 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6609 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6611 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6612 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6614 if (slot
== chosen_slot
)
6615 vinsn
->slots
[slot
] = *tinsn
;
6618 vinsn
->slots
[slot
].opcode
=
6619 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6620 vinsn
->slots
[slot
].ntok
= 0;
6621 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6628 emit_single_op (TInsn
*orig_insn
)
6631 IStack istack
; /* put instructions into here */
6632 symbolS
*lit_sym
= NULL
;
6633 symbolS
*label_sym
= NULL
;
6635 istack_init (&istack
);
6637 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6638 Because the scheduling and bundling characteristics of movi and
6639 l32r or const16 are so different, we can do much better if we relax
6640 it prior to scheduling and bundling, rather than after. */
6641 if ((orig_insn
->opcode
== xtensa_movi_opcode
6642 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6643 && !cur_vinsn
.inside_bundle
6644 && (orig_insn
->tok
[1].X_op
== O_symbol
6645 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6646 && !orig_insn
->is_specific_opcode
&& use_transform ())
6647 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6649 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6652 for (i
= 0; i
< istack
.ninsn
; i
++)
6654 TInsn
*insn
= &istack
.insn
[i
];
6655 switch (insn
->insn_type
)
6658 assert (lit_sym
== NULL
);
6659 lit_sym
= xg_assemble_literal (insn
);
6663 static int relaxed_sym_idx
= 0;
6664 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6665 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6667 assert (label_sym
== NULL
);
6668 label_sym
= symbol_find_or_make (label
);
6677 xg_resolve_literals (insn
, lit_sym
);
6679 xg_resolve_labels (insn
, label_sym
);
6681 bundle_tinsn (insn
, &v
);
6696 total_frag_text_expansion (fragS
*fragP
)
6699 int total_expansion
= 0;
6701 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6702 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6704 return total_expansion
;
6708 /* Emit a vliw instruction to the current fragment. */
6711 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6713 bfd_boolean finish_frag
;
6714 bfd_boolean is_jump
= FALSE
;
6715 bfd_boolean is_branch
= FALSE
;
6716 xtensa_isa isa
= xtensa_default_isa
;
6721 struct dwarf2_line_info debug_line
;
6722 bfd_boolean loc_directive_seen
= FALSE
;
6725 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6727 if (generating_literals
)
6729 static int reported
= 0;
6731 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6732 _("cannot assemble into a literal fragment"));
6739 if (frag_now_fix () != 0
6740 && (! frag_now
->tc_frag_data
.is_insn
6741 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6742 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6743 || (directive_state
[directive_longcalls
]
6744 != frag_now
->tc_frag_data
.use_longcalls
)
6745 || (directive_state
[directive_absolute_literals
]
6746 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6748 frag_wane (frag_now
);
6750 xtensa_set_frag_assembly_state (frag_now
);
6753 if (workaround_a0_b_retw
6754 && vinsn
->num_slots
== 1
6755 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6756 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6757 && use_transform ())
6759 has_a0_b_retw
= TRUE
;
6761 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6762 After the first assembly pass we will check all of them and
6763 add a nop if needed. */
6764 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6765 frag_var (rs_machine_dependent
, 4, 4,
6766 RELAX_ADD_NOP_IF_A0_B_RETW
,
6767 frag_now
->fr_symbol
,
6768 frag_now
->fr_offset
,
6770 xtensa_set_frag_assembly_state (frag_now
);
6771 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6772 frag_var (rs_machine_dependent
, 4, 4,
6773 RELAX_ADD_NOP_IF_A0_B_RETW
,
6774 frag_now
->fr_symbol
,
6775 frag_now
->fr_offset
,
6777 xtensa_set_frag_assembly_state (frag_now
);
6780 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6782 tinsn
= &vinsn
->slots
[slot
];
6784 /* See if the instruction implies an aligned section. */
6785 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6786 record_alignment (now_seg
, 2);
6788 /* Determine the best line number for debug info. */
6789 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6790 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6791 || tinsn
->debug_line
.line
< debug_line
.line
6792 || tinsn
->debug_line
.column
< debug_line
.column
))
6793 debug_line
= tinsn
->debug_line
;
6794 if (tinsn
->loc_directive_seen
)
6795 loc_directive_seen
= TRUE
;
6798 /* Special cases for instructions that force an alignment... */
6799 /* None of these opcodes are bundle-able. */
6800 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6804 /* Remember the symbol that marks the end of the loop in the frag
6805 that marks the start of the loop. This way we can easily find
6806 the end of the loop at the beginning, without adding special code
6807 to mark the loop instructions themselves. */
6808 symbolS
*target_sym
= NULL
;
6809 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6810 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6812 xtensa_set_frag_assembly_state (frag_now
);
6813 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6815 max_fill
= get_text_align_max_fill_size
6816 (get_text_align_power (xtensa_fetch_width
),
6817 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6819 if (use_transform ())
6820 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6821 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6823 frag_var (rs_machine_dependent
, 0, 0,
6824 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6825 xtensa_set_frag_assembly_state (frag_now
);
6828 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6829 && !vinsn
->slots
[0].is_specific_opcode
)
6831 xtensa_mark_literal_pool_location ();
6832 xtensa_move_labels (frag_now
, 0);
6833 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6836 if (vinsn
->num_slots
== 1)
6838 if (workaround_a0_b_retw
&& use_transform ())
6839 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6840 is_register_writer (&vinsn
->slots
[0], "a", 0));
6842 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6843 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6846 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6848 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6850 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6852 /* vinsn_to_insnbuf will produce the error. */
6853 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6855 f
= frag_more (insn_size
+ extra_space
);
6856 xtensa_set_frag_assembly_state (frag_now
);
6857 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6860 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6861 if (vinsn
->format
== XTENSA_UNDEFINED
)
6864 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6866 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
6867 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
6870 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6872 tinsn
= &vinsn
->slots
[slot
];
6873 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6874 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6875 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6876 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6877 if (tinsn
->literal_space
!= 0)
6878 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6880 if (tinsn
->subtype
== RELAX_NARROW
)
6881 assert (vinsn
->num_slots
== 1);
6882 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6884 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6887 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6888 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6892 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6893 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6897 frag_variant (rs_machine_dependent
,
6898 extra_space
, extra_space
, RELAX_SLOTS
,
6899 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6900 xtensa_set_frag_assembly_state (frag_now
);
6903 /* Special cases for loops:
6904 close_loop_end should be inserted AFTER short_loop.
6905 Make sure that CLOSE loops are processed BEFORE short_loops
6906 when converting them. */
6908 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6909 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6910 && !vinsn
->slots
[0].is_specific_opcode
)
6912 if (workaround_short_loop
&& use_transform ())
6914 maybe_has_short_loop
= TRUE
;
6915 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6916 frag_var (rs_machine_dependent
, 4, 4,
6917 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6918 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6919 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6920 frag_var (rs_machine_dependent
, 4, 4,
6921 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6922 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6925 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6926 loop at least 12 bytes away from another loop's end. */
6927 if (workaround_close_loop_end
&& use_transform ())
6929 maybe_has_close_loop_end
= TRUE
;
6930 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6931 frag_var (rs_machine_dependent
, 12, 12,
6932 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6933 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6937 if (use_transform ())
6941 assert (finish_frag
);
6942 frag_var (rs_machine_dependent
,
6943 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6945 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6946 xtensa_set_frag_assembly_state (frag_now
);
6948 else if (is_branch
&& do_align_targets ())
6950 assert (finish_frag
);
6951 frag_var (rs_machine_dependent
,
6952 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6953 RELAX_MAYBE_UNREACHABLE
,
6954 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6955 xtensa_set_frag_assembly_state (frag_now
);
6956 frag_var (rs_machine_dependent
,
6958 RELAX_MAYBE_DESIRE_ALIGN
,
6959 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6960 xtensa_set_frag_assembly_state (frag_now
);
6964 /* Now, if the original opcode was a call... */
6965 if (do_align_targets ()
6966 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6968 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6969 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6970 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6971 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6972 xtensa_set_frag_assembly_state (frag_now
);
6975 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6977 frag_wane (frag_now
);
6979 xtensa_set_frag_assembly_state (frag_now
);
6984 /* xtensa_end and helper functions. */
6986 static void xtensa_cleanup_align_frags (void);
6987 static void xtensa_fix_target_frags (void);
6988 static void xtensa_mark_narrow_branches (void);
6989 static void xtensa_mark_zcl_first_insns (void);
6990 static void xtensa_mark_difference_of_two_symbols (void);
6991 static void xtensa_fix_a0_b_retw_frags (void);
6992 static void xtensa_fix_b_j_loop_end_frags (void);
6993 static void xtensa_fix_close_loop_end_frags (void);
6994 static void xtensa_fix_short_loop_frags (void);
6995 static void xtensa_sanity_check (void);
6996 static void xtensa_add_config_info (void);
7001 directive_balance ();
7002 xtensa_flush_pending_output ();
7004 past_xtensa_end
= TRUE
;
7006 xtensa_move_literals ();
7008 xtensa_reorder_segments ();
7009 xtensa_cleanup_align_frags ();
7010 xtensa_fix_target_frags ();
7011 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7012 xtensa_fix_a0_b_retw_frags ();
7013 if (workaround_b_j_loop_end
)
7014 xtensa_fix_b_j_loop_end_frags ();
7016 /* "close_loop_end" should be processed BEFORE "short_loop". */
7017 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7018 xtensa_fix_close_loop_end_frags ();
7020 if (workaround_short_loop
&& maybe_has_short_loop
)
7021 xtensa_fix_short_loop_frags ();
7023 xtensa_mark_narrow_branches ();
7024 xtensa_mark_zcl_first_insns ();
7026 xtensa_sanity_check ();
7028 xtensa_add_config_info ();
7033 xtensa_cleanup_align_frags (void)
7038 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7039 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7042 /* Walk over all of the fragments in a subsection. */
7043 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7045 if ((fragP
->fr_type
== rs_align
7046 || fragP
->fr_type
== rs_align_code
7047 || (fragP
->fr_type
== rs_machine_dependent
7048 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7049 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7050 && fragP
->fr_fix
== 0)
7052 fragS
*next
= fragP
->fr_next
;
7055 && next
->fr_fix
== 0
7056 && next
->fr_type
== rs_machine_dependent
7057 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7060 next
= next
->fr_next
;
7063 /* If we don't widen branch targets, then they
7064 will be easier to align. */
7065 if (fragP
->tc_frag_data
.is_branch_target
7066 && fragP
->fr_opcode
== fragP
->fr_literal
7067 && fragP
->fr_type
== rs_machine_dependent
7068 && fragP
->fr_subtype
== RELAX_SLOTS
7069 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7071 if (fragP
->fr_type
== rs_machine_dependent
7072 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7073 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7079 /* Re-process all of the fragments looking to convert all of the
7080 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7081 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7082 Otherwise, convert to a .fill 0. */
7085 xtensa_fix_target_frags (void)
7090 /* When this routine is called, all of the subsections are still intact
7091 so we walk over subsections instead of sections. */
7092 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7093 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7097 /* Walk over all of the fragments in a subsection. */
7098 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7100 if (fragP
->fr_type
== rs_machine_dependent
7101 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7103 if (next_frag_is_branch_target (fragP
))
7104 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7113 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7116 xtensa_mark_narrow_branches (void)
7121 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7122 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7125 /* Walk over all of the fragments in a subsection. */
7126 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7128 if (fragP
->fr_type
== rs_machine_dependent
7129 && fragP
->fr_subtype
== RELAX_SLOTS
7130 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7134 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7135 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7137 if (vinsn
.num_slots
== 1
7138 && xtensa_opcode_is_branch (xtensa_default_isa
,
7139 vinsn
.slots
[0].opcode
) == 1
7140 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7141 && is_narrow_branch_guaranteed_in_range (fragP
,
7144 fragP
->fr_subtype
= RELAX_SLOTS
;
7145 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7146 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7154 /* A branch is typically widened only when its target is out of
7155 range. However, we would like to widen them to align a subsequent
7156 branch target when possible.
7158 Because the branch relaxation code is so convoluted, the optimal solution
7159 (combining the two cases) is difficult to get right in all circumstances.
7160 We therefore go with an "almost as good" solution, where we only
7161 use for alignment narrow branches that definitely will not expand to a
7162 jump and a branch. These functions find and mark these cases. */
7164 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7165 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7166 We start counting beginning with the frag after the 2-byte branch, so the
7167 maximum offset is (4 - 2) + 63 = 65. */
7168 #define MAX_IMMED6 65
7170 static offsetT
unrelaxed_frag_max_size (fragS
*);
7173 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7175 const expressionS
*expr
= &tinsn
->tok
[1];
7176 symbolS
*symbolP
= expr
->X_add_symbol
;
7177 offsetT max_distance
= expr
->X_add_number
;
7180 if (expr
->X_op
!= O_symbol
)
7183 target_frag
= symbol_get_frag (symbolP
);
7185 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7186 if (is_branch_jmp_to_next (tinsn
, fragP
))
7189 /* The branch doesn't branch over it's own frag,
7190 but over the subsequent ones. */
7191 fragP
= fragP
->fr_next
;
7192 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7194 max_distance
+= unrelaxed_frag_max_size (fragP
);
7195 fragP
= fragP
->fr_next
;
7197 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7204 xtensa_mark_zcl_first_insns (void)
7209 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7210 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7213 /* Walk over all of the fragments in a subsection. */
7214 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7216 if (fragP
->fr_type
== rs_machine_dependent
7217 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7218 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7220 /* Find the loop frag. */
7221 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7222 /* Find the first insn frag. */
7223 targ_frag
= next_non_empty_frag (targ_frag
);
7225 /* Of course, sometimes (mostly for toy test cases) a
7226 zero-cost loop instruction is the last in a section. */
7229 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7230 /* Do not widen a frag that is the first instruction of a
7231 zero-cost loop. It makes that loop harder to align. */
7232 if (targ_frag
->fr_type
== rs_machine_dependent
7233 && targ_frag
->fr_subtype
== RELAX_SLOTS
7234 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7237 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7238 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7241 frag_wane (targ_frag
);
7242 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7246 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7254 /* Some difference-of-symbols expressions make it out to the linker. Some
7255 don't. If one does, then the linker can optimize between the two labels.
7256 If it doesn't, then the linker shouldn't. */
7259 xtensa_mark_difference_of_two_symbols (void)
7263 for (expr_sym
= expr_symbols
; expr_sym
;
7264 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7266 expressionS
*expr
= symbol_get_value_expression (expr_sym
);
7268 if (expr
->X_op
== O_subtract
)
7270 symbolS
*left
= expr
->X_add_symbol
;
7271 symbolS
*right
= expr
->X_op_symbol
;
7273 /* Difference of two symbols not in the same section
7274 are handled with relocations in the linker. */
7275 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7280 if (symbol_get_frag (left
)->fr_address
7281 <= symbol_get_frag (right
)->fr_address
)
7283 start
= symbol_get_frag (left
);
7284 end
= symbol_get_frag (right
);
7288 start
= symbol_get_frag (right
);
7289 end
= symbol_get_frag (left
);
7293 start
->tc_frag_data
.is_no_transform
= 1;
7294 start
= start
->fr_next
;
7296 while (start
&& start
->fr_address
< end
->fr_address
);
7303 /* Re-process all of the fragments looking to convert all of the
7304 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7305 conditional branch or a retw/retw.n, convert this frag to one that
7306 will generate a NOP. In any case close it off with a .fill 0. */
7308 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7311 xtensa_fix_a0_b_retw_frags (void)
7316 /* When this routine is called, all of the subsections are still intact
7317 so we walk over subsections instead of sections. */
7318 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7319 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7323 /* Walk over all of the fragments in a subsection. */
7324 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7326 if (fragP
->fr_type
== rs_machine_dependent
7327 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7329 if (next_instrs_are_b_retw (fragP
))
7331 if (fragP
->tc_frag_data
.is_no_transform
)
7332 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7334 relax_frag_add_nop (fragP
);
7344 next_instrs_are_b_retw (fragS
*fragP
)
7346 xtensa_opcode opcode
;
7348 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7349 static xtensa_insnbuf insnbuf
= NULL
;
7350 static xtensa_insnbuf slotbuf
= NULL
;
7351 xtensa_isa isa
= xtensa_default_isa
;
7354 bfd_boolean branch_seen
= FALSE
;
7358 insnbuf
= xtensa_insnbuf_alloc (isa
);
7359 slotbuf
= xtensa_insnbuf_alloc (isa
);
7362 if (next_fragP
== NULL
)
7365 /* Check for the conditional branch. */
7366 xtensa_insnbuf_from_chars
7367 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7368 fmt
= xtensa_format_decode (isa
, insnbuf
);
7369 if (fmt
== XTENSA_UNDEFINED
)
7372 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7374 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7375 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7377 branch_seen
= (branch_seen
7378 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7384 offset
+= xtensa_format_length (isa
, fmt
);
7385 if (offset
== next_fragP
->fr_fix
)
7387 next_fragP
= next_non_empty_frag (next_fragP
);
7391 if (next_fragP
== NULL
)
7394 /* Check for the retw/retw.n. */
7395 xtensa_insnbuf_from_chars
7396 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7397 fmt
= xtensa_format_decode (isa
, insnbuf
);
7399 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7400 have no problems. */
7401 if (fmt
== XTENSA_UNDEFINED
7402 || xtensa_format_num_slots (isa
, fmt
) != 1)
7405 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7406 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7408 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7415 /* Re-process all of the fragments looking to convert all of the
7416 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7417 loop end label, convert this frag to one that will generate a NOP.
7418 In any case close it off with a .fill 0. */
7420 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7423 xtensa_fix_b_j_loop_end_frags (void)
7428 /* When this routine is called, all of the subsections are still intact
7429 so we walk over subsections instead of sections. */
7430 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7431 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7435 /* Walk over all of the fragments in a subsection. */
7436 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7438 if (fragP
->fr_type
== rs_machine_dependent
7439 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7441 if (next_instr_is_loop_end (fragP
))
7443 if (fragP
->tc_frag_data
.is_no_transform
)
7444 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7446 relax_frag_add_nop (fragP
);
7456 next_instr_is_loop_end (fragS
*fragP
)
7458 const fragS
*next_fragP
;
7460 if (next_frag_is_loop_target (fragP
))
7463 next_fragP
= next_non_empty_frag (fragP
);
7464 if (next_fragP
== NULL
)
7467 if (!next_frag_is_loop_target (next_fragP
))
7470 /* If the size is >= 3 then there is more than one instruction here.
7471 The hardware bug will not fire. */
7472 if (next_fragP
->fr_fix
> 3)
7479 /* Re-process all of the fragments looking to convert all of the
7480 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7481 not MY loop's loop end within 12 bytes, add enough nops here to
7482 make it at least 12 bytes away. In any case close it off with a
7485 static offsetT min_bytes_to_other_loop_end
7486 (fragS
*, fragS
*, offsetT
);
7489 xtensa_fix_close_loop_end_frags (void)
7494 /* When this routine is called, all of the subsections are still intact
7495 so we walk over subsections instead of sections. */
7496 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7497 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7501 fragS
*current_target
= NULL
;
7503 /* Walk over all of the fragments in a subsection. */
7504 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7506 if (fragP
->fr_type
== rs_machine_dependent
7507 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7508 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7509 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7512 && fragP
->fr_type
== rs_machine_dependent
7513 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7516 int bytes_added
= 0;
7518 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7519 /* Max out at 12. */
7520 min_bytes
= min_bytes_to_other_loop_end
7521 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7523 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7525 if (fragP
->tc_frag_data
.is_no_transform
)
7526 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7529 while (min_bytes
+ bytes_added
7530 < REQUIRED_LOOP_DIVIDING_BYTES
)
7534 if (fragP
->fr_var
< length
)
7535 as_fatal (_("fr_var %lu < length %d"),
7536 (long) fragP
->fr_var
, length
);
7539 assemble_nop (length
,
7540 fragP
->fr_literal
+ fragP
->fr_fix
);
7541 fragP
->fr_fix
+= length
;
7542 fragP
->fr_var
-= length
;
7544 bytes_added
+= length
;
7550 assert (fragP
->fr_type
!= rs_machine_dependent
7551 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7557 static offsetT
unrelaxed_frag_min_size (fragS
*);
7560 min_bytes_to_other_loop_end (fragS
*fragP
,
7561 fragS
*current_target
,
7565 fragS
*current_fragP
;
7567 for (current_fragP
= fragP
;
7569 current_fragP
= current_fragP
->fr_next
)
7571 if (current_fragP
->tc_frag_data
.is_loop_target
7572 && current_fragP
!= current_target
)
7575 offset
+= unrelaxed_frag_min_size (current_fragP
);
7577 if (offset
>= max_size
)
7585 unrelaxed_frag_min_size (fragS
*fragP
)
7587 offsetT size
= fragP
->fr_fix
;
7589 /* Add fill size. */
7590 if (fragP
->fr_type
== rs_fill
)
7591 size
+= fragP
->fr_offset
;
7598 unrelaxed_frag_max_size (fragS
*fragP
)
7600 offsetT size
= fragP
->fr_fix
;
7601 switch (fragP
->fr_type
)
7604 /* Empty frags created by the obstack allocation scheme
7605 end up with type 0. */
7610 size
+= fragP
->fr_offset
;
7618 /* No further adjustments needed. */
7620 case rs_machine_dependent
:
7621 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7622 size
+= fragP
->fr_var
;
7625 /* We had darn well better know how big it is. */
7634 /* Re-process all of the fragments looking to convert all
7635 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7638 1) the instruction size count to the loop end label
7639 is too short (<= 2 instructions),
7640 2) loop has a jump or branch in it
7643 1) workaround_all_short_loops is TRUE
7644 2) The generating loop was a 'loopgtz' or 'loopnez'
7645 3) the instruction size count to the loop end label is too short
7647 then convert this frag (and maybe the next one) to generate a NOP.
7648 In any case close it off with a .fill 0. */
7650 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7651 static bfd_boolean
branch_before_loop_end (fragS
*);
7654 xtensa_fix_short_loop_frags (void)
7659 /* When this routine is called, all of the subsections are still intact
7660 so we walk over subsections instead of sections. */
7661 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7662 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7665 fragS
*current_target
= NULL
;
7666 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7668 /* Walk over all of the fragments in a subsection. */
7669 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7671 if (fragP
->fr_type
== rs_machine_dependent
7672 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7673 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7676 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7677 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7678 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7679 current_opcode
= t_insn
.opcode
;
7680 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7681 current_opcode
) == 1);
7684 if (fragP
->fr_type
== rs_machine_dependent
7685 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7687 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7688 && (branch_before_loop_end (fragP
->fr_next
)
7689 || (workaround_all_short_loops
7690 && current_opcode
!= XTENSA_UNDEFINED
7691 && current_opcode
!= xtensa_loop_opcode
)))
7693 if (fragP
->tc_frag_data
.is_no_transform
)
7694 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7696 relax_frag_add_nop (fragP
);
7705 static int unrelaxed_frag_min_insn_count (fragS
*);
7708 count_insns_to_loop_end (fragS
*base_fragP
,
7709 bfd_boolean count_relax_add
,
7712 fragS
*fragP
= NULL
;
7717 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7719 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7720 if (insn_count
>= max_count
)
7723 if (count_relax_add
)
7725 if (fragP
->fr_type
== rs_machine_dependent
7726 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7728 /* In order to add the appropriate number of
7729 NOPs, we count an instruction for downstream
7732 if (insn_count
>= max_count
)
7742 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7744 xtensa_isa isa
= xtensa_default_isa
;
7745 static xtensa_insnbuf insnbuf
= NULL
;
7749 if (!fragP
->tc_frag_data
.is_insn
)
7753 insnbuf
= xtensa_insnbuf_alloc (isa
);
7755 /* Decode the fixed instructions. */
7756 while (offset
< fragP
->fr_fix
)
7760 xtensa_insnbuf_from_chars
7761 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7762 fmt
= xtensa_format_decode (isa
, insnbuf
);
7764 if (fmt
== XTENSA_UNDEFINED
)
7766 as_fatal (_("undecodable instruction in instruction frag"));
7769 offset
+= xtensa_format_length (isa
, fmt
);
7777 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7780 branch_before_loop_end (fragS
*base_fragP
)
7784 for (fragP
= base_fragP
;
7785 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7786 fragP
= fragP
->fr_next
)
7788 if (unrelaxed_frag_has_b_j (fragP
))
7796 unrelaxed_frag_has_b_j (fragS
*fragP
)
7798 static xtensa_insnbuf insnbuf
= NULL
;
7799 xtensa_isa isa
= xtensa_default_isa
;
7802 if (!fragP
->tc_frag_data
.is_insn
)
7806 insnbuf
= xtensa_insnbuf_alloc (isa
);
7808 /* Decode the fixed instructions. */
7809 while (offset
< fragP
->fr_fix
)
7814 xtensa_insnbuf_from_chars
7815 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7816 fmt
= xtensa_format_decode (isa
, insnbuf
);
7817 if (fmt
== XTENSA_UNDEFINED
)
7820 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7822 xtensa_opcode opcode
=
7823 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7824 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7825 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7828 offset
+= xtensa_format_length (isa
, fmt
);
7834 /* Checks to be made after initial assembly but before relaxation. */
7836 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7837 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7840 xtensa_sanity_check (void)
7847 as_where (&file_name
, &line
);
7848 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7849 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7853 /* Walk over all of the fragments in a subsection. */
7854 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7856 if (fragP
->fr_type
== rs_machine_dependent
7857 && fragP
->fr_subtype
== RELAX_SLOTS
7858 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7860 static xtensa_insnbuf insnbuf
= NULL
;
7863 if (fragP
->fr_opcode
!= NULL
)
7866 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7867 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7868 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7870 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7871 t_insn
.opcode
) == 1)
7873 if (is_empty_loop (&t_insn
, fragP
))
7875 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7876 as_bad (_("invalid empty loop"));
7878 if (!is_local_forward_loop (&t_insn
, fragP
))
7880 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7881 as_bad (_("loop target does not follow "
7882 "loop instruction in section"));
7889 new_logical_line (file_name
, line
);
7893 #define LOOP_IMMED_OPN 1
7895 /* Return TRUE if the loop target is the next non-zero fragment. */
7898 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7900 const expressionS
*expr
;
7904 if (insn
->insn_type
!= ITYPE_INSN
)
7907 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7910 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7913 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7915 if (expr
->X_op
!= O_symbol
)
7918 symbolP
= expr
->X_add_symbol
;
7922 if (symbol_get_frag (symbolP
) == NULL
)
7925 if (S_GET_VALUE (symbolP
) != 0)
7928 /* Walk through the zero-size fragments from this one. If we find
7929 the target fragment, then this is a zero-size loop. */
7931 for (next_fragP
= fragP
->fr_next
;
7933 next_fragP
= next_fragP
->fr_next
)
7935 if (next_fragP
== symbol_get_frag (symbolP
))
7937 if (next_fragP
->fr_fix
!= 0)
7945 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7947 const expressionS
*expr
;
7951 if (insn
->insn_type
!= ITYPE_INSN
)
7954 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7957 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7960 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7962 if (expr
->X_op
!= O_symbol
)
7965 symbolP
= expr
->X_add_symbol
;
7969 if (symbol_get_frag (symbolP
) == NULL
)
7972 /* Walk through fragments until we find the target.
7973 If we do not find the target, then this is an invalid loop. */
7975 for (next_fragP
= fragP
->fr_next
;
7977 next_fragP
= next_fragP
->fr_next
)
7979 if (next_fragP
== symbol_get_frag (symbolP
))
7987 #define XTINFO_NAME "Xtensa_Info"
7988 #define XTINFO_NAMESZ 12
7989 #define XTINFO_TYPE 1
7992 xtensa_add_config_info (void)
7998 info_sec
= subseg_new (".xtensa.info", 0);
7999 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8001 data
= xmalloc (100);
8002 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8003 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8004 sz
= strlen (data
) + 1;
8006 /* Add enough null terminators to pad to a word boundary. */
8009 while ((sz
& 3) != 0);
8011 /* Follow the standard note section layout:
8012 First write the length of the name string. */
8014 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8016 /* Next comes the length of the "descriptor", i.e., the actual data. */
8018 md_number_to_chars (p
, (valueT
) sz
, 4);
8020 /* Write the note type. */
8022 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8024 /* Write the name field. */
8025 p
= frag_more (XTINFO_NAMESZ
);
8026 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8028 /* Finally, write the descriptor. */
8030 memcpy (p
, data
, sz
);
8036 /* Alignment Functions. */
8039 get_text_align_power (unsigned target_size
)
8041 if (target_size
<= 4)
8043 assert (target_size
== 8);
8049 get_text_align_max_fill_size (int align_pow
,
8050 bfd_boolean use_nops
,
8051 bfd_boolean use_no_density
)
8054 return (1 << align_pow
);
8056 return 3 * (1 << align_pow
);
8058 return 1 + (1 << align_pow
);
8062 /* Calculate the minimum bytes of fill needed at "address" to align a
8063 target instruction of size "target_size" so that it does not cross a
8064 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8065 the fill can be an arbitrary number of bytes. Otherwise, the space must
8066 be filled by NOP instructions. */
8069 get_text_align_fill_size (addressT address
,
8072 bfd_boolean use_nops
,
8073 bfd_boolean use_no_density
)
8075 addressT alignment
, fill
, fill_limit
, fill_step
;
8076 bfd_boolean skip_one
= FALSE
;
8078 alignment
= (1 << align_pow
);
8079 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8083 fill_limit
= alignment
;
8086 else if (!use_no_density
)
8088 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8089 fill_limit
= alignment
* 2;
8095 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8096 fill_limit
= alignment
* 3;
8100 /* Try all fill sizes until finding one that works. */
8101 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8103 if (skip_one
&& fill
== 1)
8105 if ((address
+ fill
) >> align_pow
8106 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8115 branch_align_power (segT sec
)
8117 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8118 is aligned to at least an 8-byte boundary, then a branch target need
8119 only fit within an 8-byte aligned block of memory to avoid a stall.
8120 Otherwise, try to fit branch targets within 4-byte aligned blocks
8121 (which may be insufficient, e.g., if the section has no alignment, but
8122 it's good enough). */
8123 if (xtensa_fetch_width
== 8)
8125 if (get_recorded_alignment (sec
) >= 3)
8129 assert (xtensa_fetch_width
== 4);
8135 /* This will assert if it is not possible. */
8138 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8144 assert (fill_size
% 3 == 0);
8145 return (fill_size
/ 3);
8148 assert (fill_size
!= 1); /* Bad argument. */
8150 while (fill_size
> 1)
8153 if (fill_size
== 2 || fill_size
== 4)
8155 fill_size
-= insn_size
;
8158 assert (fill_size
!= 1); /* Bad algorithm. */
8164 get_text_align_nth_nop_size (offsetT fill_size
,
8166 bfd_boolean use_no_density
)
8173 assert (fill_size
!= 1); /* Bad argument. */
8175 while (fill_size
> 1)
8178 if (fill_size
== 2 || fill_size
== 4)
8180 fill_size
-= insn_size
;
8190 /* For the given fragment, find the appropriate address
8191 for it to begin at if we are using NOPs to align it. */
8194 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8196 /* The rule is: get next fragment's FIRST instruction. Find
8197 the smallest number of bytes that need to be added to
8198 ensure that the next fragment's FIRST instruction will fit
8201 E.G., 2 bytes : 0, 1, 2 mod 4
8204 If the FIRST instruction MIGHT be relaxed,
8205 assume that it will become a 3-byte instruction.
8207 Note again here that LOOP instructions are not bundleable,
8208 and this relaxation only applies to LOOP opcodes. */
8211 int first_insn_size
;
8213 addressT pre_opcode_bytes
;
8216 xtensa_opcode opcode
;
8217 bfd_boolean is_loop
;
8219 assert (fragP
->fr_type
== rs_machine_dependent
);
8220 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8222 /* Find the loop frag. */
8223 first_insn
= next_non_empty_frag (fragP
);
8224 /* Now find the first insn frag. */
8225 first_insn
= next_non_empty_frag (first_insn
);
8227 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8229 loop_insn_size
= xg_get_single_size (opcode
);
8231 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8232 pre_opcode_bytes
+= loop_insn_size
;
8234 /* For loops, the alignment depends on the size of the
8235 instruction following the loop, not the LOOP instruction. */
8237 if (first_insn
== NULL
)
8238 first_insn_size
= xtensa_fetch_width
;
8240 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8242 /* If it was 8, then we'll need a larger alignment for the section. */
8243 align_power
= get_text_align_power (first_insn_size
);
8244 record_alignment (now_seg
, align_power
);
8246 fill_size
= get_text_align_fill_size
8247 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8248 fragP
->tc_frag_data
.is_no_density
);
8250 return address
+ fill_size
;
8254 /* 3 mechanisms for relaxing an alignment:
8256 Align to a power of 2.
8257 Align so the next fragment's instruction does not cross a word boundary.
8258 Align the current instruction so that if the next instruction
8259 were 3 bytes, it would not cross a word boundary.
8263 zeros - This is easy; always insert zeros.
8264 nops - 3-byte and 2-byte instructions
8268 >=5 : 3-byte instruction + fn (n-3)
8269 widening - widen previous instructions. */
8272 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8274 addressT target_address
, loop_insn_offset
;
8276 xtensa_opcode loop_opcode
;
8277 bfd_boolean is_loop
;
8280 offsetT branch_align
;
8283 assert (fragP
->fr_type
== rs_machine_dependent
);
8284 switch (fragP
->fr_subtype
)
8286 case RELAX_DESIRE_ALIGN
:
8287 target_size
= next_frag_format_size (fragP
);
8288 if (target_size
== XTENSA_UNDEFINED
)
8290 align_power
= branch_align_power (now_seg
);
8291 branch_align
= 1 << align_power
;
8292 /* Don't count on the section alignment being as large as the target. */
8293 if (target_size
> branch_align
)
8294 target_size
= branch_align
;
8295 opt_diff
= get_text_align_fill_size (address
, align_power
,
8296 target_size
, FALSE
, FALSE
);
8298 *max_diff
= (opt_diff
+ branch_align
8299 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8300 assert (*max_diff
>= opt_diff
);
8303 case RELAX_ALIGN_NEXT_OPCODE
:
8304 /* The next non-empty frag after this one holds the LOOP instruction
8305 that needs to be aligned. The required alignment depends on the
8306 size of the next non-empty frag after the loop frag, i.e., the
8307 first instruction in the loop. */
8308 loop_frag
= next_non_empty_frag (fragP
);
8309 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8310 loop_insn_offset
= 0;
8311 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8314 /* If the loop has been expanded then the LOOP instruction
8315 could be at an offset from this fragment. */
8316 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8317 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8319 /* In an ideal world, which is what we are shooting for here,
8320 we wouldn't need to use any NOPs immediately prior to the
8321 LOOP instruction. If this approach fails, relax_frag_loop_align
8322 will call get_noop_aligned_address. */
8324 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8325 align_power
= get_text_align_power (target_size
);
8326 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8327 target_size
, FALSE
, FALSE
);
8329 *max_diff
= xtensa_fetch_width
8330 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8331 - target_size
+ opt_diff
;
8332 assert (*max_diff
>= opt_diff
);
8343 /* md_relax_frag Hook and Helper Functions. */
8345 static long relax_frag_loop_align (fragS
*, long);
8346 static long relax_frag_for_align (fragS
*, long);
8347 static long relax_frag_immed
8348 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8351 /* Return the number of bytes added to this fragment, given that the
8352 input has been stretched already by "stretch". */
8355 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8357 xtensa_isa isa
= xtensa_default_isa
;
8358 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8359 long new_stretch
= 0;
8363 static xtensa_insnbuf vbuf
= NULL
;
8364 int slot
, num_slots
;
8367 as_where (&file_name
, &line
);
8368 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8370 fragP
->tc_frag_data
.unreported_expansion
= 0;
8372 switch (fragP
->fr_subtype
)
8374 case RELAX_ALIGN_NEXT_OPCODE
:
8375 /* Always convert. */
8376 if (fragP
->tc_frag_data
.relax_seen
)
8377 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8380 case RELAX_LOOP_END
:
8384 case RELAX_LOOP_END_ADD_NOP
:
8385 /* Add a NOP and switch to .fill 0. */
8386 new_stretch
= relax_frag_add_nop (fragP
);
8390 case RELAX_DESIRE_ALIGN
:
8391 /* Do nothing. The narrowing before this frag will either align
8396 case RELAX_LITERAL_FINAL
:
8399 case RELAX_LITERAL_NR
:
8401 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8402 assert (unreported
== lit_size
);
8403 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8404 fragP
->fr_var
-= lit_size
;
8405 fragP
->fr_fix
+= lit_size
;
8411 vbuf
= xtensa_insnbuf_alloc (isa
);
8413 xtensa_insnbuf_from_chars
8414 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8415 fmt
= xtensa_format_decode (isa
, vbuf
);
8416 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8418 for (slot
= 0; slot
< num_slots
; slot
++)
8420 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8423 if (fragP
->tc_frag_data
.relax_seen
)
8424 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8428 case RELAX_IMMED_STEP1
:
8429 case RELAX_IMMED_STEP2
:
8430 case RELAX_IMMED_STEP3
:
8431 /* Place the immediate. */
8432 new_stretch
+= relax_frag_immed
8433 (now_seg
, fragP
, stretch
,
8434 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8435 fmt
, slot
, stretched_p
, FALSE
);
8439 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8445 case RELAX_LITERAL_POOL_BEGIN
:
8446 case RELAX_LITERAL_POOL_END
:
8447 case RELAX_MAYBE_UNREACHABLE
:
8448 case RELAX_MAYBE_DESIRE_ALIGN
:
8449 /* No relaxation required. */
8452 case RELAX_FILL_NOP
:
8453 case RELAX_UNREACHABLE
:
8454 if (fragP
->tc_frag_data
.relax_seen
)
8455 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8459 as_bad (_("bad relaxation state"));
8462 /* Tell gas we need another relaxation pass. */
8463 if (! fragP
->tc_frag_data
.relax_seen
)
8465 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8469 new_logical_line (file_name
, line
);
8475 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8477 addressT old_address
, old_next_address
, old_size
;
8478 addressT new_address
, new_next_address
, new_size
;
8481 /* All the frags with relax_frag_for_alignment prior to this one in the
8482 section have been done, hopefully eliminating the need for a NOP here.
8483 But, this will put it in if necessary. */
8485 /* Calculate the old address of this fragment and the next fragment. */
8486 old_address
= fragP
->fr_address
- stretch
;
8487 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8488 fragP
->tc_frag_data
.text_expansion
[0]);
8489 old_size
= old_next_address
- old_address
;
8491 /* Calculate the new address of this fragment and the next fragment. */
8492 new_address
= fragP
->fr_address
;
8494 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8495 new_size
= new_next_address
- new_address
;
8497 growth
= new_size
- old_size
;
8499 /* Fix up the text_expansion field and return the new growth. */
8500 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8505 /* Add a NOP instruction. */
8508 relax_frag_add_nop (fragS
*fragP
)
8510 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8511 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8512 assemble_nop (length
, nop_buf
);
8513 fragP
->tc_frag_data
.is_insn
= TRUE
;
8515 if (fragP
->fr_var
< length
)
8517 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8521 fragP
->fr_fix
+= length
;
8522 fragP
->fr_var
-= length
;
8527 static long future_alignment_required (fragS
*, long);
8530 relax_frag_for_align (fragS
*fragP
, long stretch
)
8532 /* Overview of the relaxation procedure for alignment:
8533 We can widen with NOPs or by widening instructions or by filling
8534 bytes after jump instructions. Find the opportune places and widen
8535 them if necessary. */
8540 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8541 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8542 || (fragP
->fr_subtype
== RELAX_SLOTS
8543 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8545 stretch_me
= future_alignment_required (fragP
, stretch
);
8546 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8552 /* We expanded on a previous pass. Can we shrink now? */
8553 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8554 if (shrink
<= stretch
&& stretch
> 0)
8556 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8562 /* Below here, diff > 0. */
8563 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8569 /* Return the address of the next frag that should be aligned.
8571 By "address" we mean the address it _would_ be at if there
8572 is no action taken to align it between here and the target frag.
8573 In other words, if no narrows and no fill nops are used between
8574 here and the frag to align, _even_if_ some of the frags we use
8575 to align targets have already expanded on a previous relaxation
8578 Also, count each frag that may be used to help align the target.
8580 Return 0 if there are no frags left in the chain that need to be
8584 find_address_of_next_align_frag (fragS
**fragPP
,
8588 bfd_boolean
*paddable
)
8590 fragS
*fragP
= *fragPP
;
8591 addressT address
= fragP
->fr_address
;
8593 /* Do not reset the counts to 0. */
8597 /* Limit this to a small search. */
8598 if (*widens
>= (int) xtensa_fetch_width
)
8603 address
+= fragP
->fr_fix
;
8605 if (fragP
->fr_type
== rs_fill
)
8606 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8607 else if (fragP
->fr_type
== rs_machine_dependent
)
8609 switch (fragP
->fr_subtype
)
8611 case RELAX_UNREACHABLE
:
8615 case RELAX_FILL_NOP
:
8617 if (!fragP
->tc_frag_data
.is_no_density
)
8622 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8627 address
+= total_frag_text_expansion (fragP
);;
8631 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8634 case RELAX_ALIGN_NEXT_OPCODE
:
8635 case RELAX_DESIRE_ALIGN
:
8639 case RELAX_MAYBE_UNREACHABLE
:
8640 case RELAX_MAYBE_DESIRE_ALIGN
:
8645 /* Just punt if we don't know the type. */
8652 /* Just punt if we don't know the type. */
8656 fragP
= fragP
->fr_next
;
8664 static long bytes_to_stretch (fragS
*, int, int, int, int);
8667 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8669 fragS
*this_frag
= fragP
;
8673 int narrow_nops
= 0;
8674 bfd_boolean paddable
= FALSE
;
8675 offsetT local_opt_diff
;
8678 int stretch_amount
= 0;
8679 int local_stretch_amount
;
8680 int global_stretch_amount
;
8682 address
= find_address_of_next_align_frag
8683 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8687 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8688 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8690 frag_wane (this_frag
);
8694 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8695 opt_diff
= local_opt_diff
;
8696 assert (opt_diff
>= 0);
8697 assert (max_diff
>= opt_diff
);
8702 fragP
= fragP
->fr_next
;
8704 while (fragP
&& opt_diff
< max_diff
&& address
)
8706 /* We only use these to determine if we can exit early
8707 because there will be plenty of ways to align future
8709 int glob_widens
= 0;
8712 bfd_boolean glob_pad
= 0;
8713 address
= find_address_of_next_align_frag
8714 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8715 /* If there is a padable portion, then skip. */
8716 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8721 offsetT next_m_diff
;
8722 offsetT next_o_diff
;
8724 /* Downrange frags haven't had stretch added to them yet. */
8727 /* The address also includes any text expansion from this
8728 frag in a previous pass, but we don't want that. */
8729 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8731 /* Assume we are going to move at least opt_diff. In
8732 reality, we might not be able to, but assuming that
8733 we will helps catch cases where moving opt_diff pushes
8734 the next target from aligned to unaligned. */
8735 address
+= opt_diff
;
8737 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8739 /* Now cleanup for the adjustments to address. */
8740 next_o_diff
+= opt_diff
;
8741 next_m_diff
+= opt_diff
;
8742 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8743 opt_diff
= next_o_diff
;
8744 if (next_m_diff
< max_diff
)
8745 max_diff
= next_m_diff
;
8746 fragP
= fragP
->fr_next
;
8750 /* If there are enough wideners in between, do it. */
8753 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8755 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8760 local_stretch_amount
8761 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8762 num_widens
, local_opt_diff
);
8763 global_stretch_amount
8764 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8765 num_widens
, opt_diff
);
8766 /* If the condition below is true, then the frag couldn't
8767 stretch the correct amount for the global case, so we just
8768 optimize locally. We'll rely on the subsequent frags to get
8769 the correct alignment in the global case. */
8770 if (global_stretch_amount
< local_stretch_amount
)
8771 stretch_amount
= local_stretch_amount
;
8773 stretch_amount
= global_stretch_amount
;
8775 if (this_frag
->fr_subtype
== RELAX_SLOTS
8776 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8777 assert (stretch_amount
<= 1);
8778 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8780 if (this_frag
->tc_frag_data
.is_no_density
)
8781 assert (stretch_amount
== 3 || stretch_amount
== 0);
8783 assert (stretch_amount
<= 3);
8786 return stretch_amount
;
8790 /* The idea: widen everything you can to get a target or loop aligned,
8791 then start using NOPs.
8793 When we must have a NOP, here is a table of how we decide
8794 (so you don't have to fight through the control flow below):
8796 wide_nops = the number of wide NOPs available for aligning
8797 narrow_nops = the number of narrow NOPs available for aligning
8798 (a subset of wide_nops)
8799 widens = the number of narrow instructions that should be widened
8806 b 0 1 1 (case 3a makes this case unnecessary)
8809 c 0 1 2 (case 4a makes this case unnecessary)
8812 c 0 2 1 (case 5b makes this case unnecessary)
8815 c 0 1 4 (case 6b makes this case unnecessary)
8816 d 1 1 1 (case 6a makes this case unnecessary)
8817 e 0 2 2 (case 6a makes this case unnecessary)
8818 f 0 3 0 (case 6a makes this case unnecessary)
8821 c 1 1 2 (case 7b makes this case unnecessary)
8822 d 0 1 5 (case 7a makes this case unnecessary)
8823 e 0 2 3 (case 7b makes this case unnecessary)
8824 f 0 3 1 (case 7b makes this case unnecessary)
8825 g 1 2 1 (case 7b makes this case unnecessary)
8829 bytes_to_stretch (fragS
*this_frag
,
8835 int bytes_short
= desired_diff
- num_widens
;
8837 assert (desired_diff
>= 0 && desired_diff
< 8);
8838 if (desired_diff
== 0)
8841 assert (wide_nops
> 0 || num_widens
> 0);
8843 /* Always prefer widening to NOP-filling. */
8844 if (bytes_short
< 0)
8846 /* There are enough RELAX_NARROW frags after this one
8847 to align the target without widening this frag in any way. */
8851 if (bytes_short
== 0)
8853 /* Widen every narrow between here and the align target
8854 and the align target will be properly aligned. */
8855 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8861 /* From here we will need at least one NOP to get an alignment.
8862 However, we may not be able to align at all, in which case,
8864 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8866 switch (desired_diff
)
8871 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8872 return 2; /* case 2 */
8878 return 3; /* case 3a */
8880 if (num_widens
>= 1 && wide_nops
== 1)
8881 return 3; /* case 4a */
8882 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8883 return 2; /* case 4b */
8886 if (num_widens
>= 2 && wide_nops
== 1)
8887 return 3; /* case 5a */
8888 /* We will need two nops. Are there enough nops
8889 between here and the align target? */
8890 if (wide_nops
< 2 || narrow_nops
== 0)
8892 /* Are there other nops closer that can serve instead? */
8893 if (wide_nops
> 2 && narrow_nops
> 1)
8895 /* Take the density one first, because there might not be
8896 another density one available. */
8897 if (!this_frag
->tc_frag_data
.is_no_density
)
8898 return 2; /* case 5b narrow */
8900 return 3; /* case 5b wide */
8904 return 3; /* case 6a */
8905 else if (num_widens
>= 3 && wide_nops
== 1)
8906 return 3; /* case 6b */
8909 if (wide_nops
== 1 && num_widens
>= 4)
8910 return 3; /* case 7a */
8911 else if (wide_nops
== 2 && num_widens
>= 1)
8912 return 3; /* case 7b */
8920 /* We will need a NOP no matter what, but should we widen
8921 this instruction to help?
8923 This is a RELAX_NARROW frag. */
8924 switch (desired_diff
)
8933 if (wide_nops
>= 1 && num_widens
== 1)
8934 return 1; /* case 4a */
8937 if (wide_nops
>= 1 && num_widens
== 2)
8938 return 1; /* case 5a */
8942 return 0; /* case 6a */
8943 else if (wide_nops
>= 1 && num_widens
== 3)
8944 return 1; /* case 6b */
8947 if (wide_nops
>= 1 && num_widens
== 4)
8948 return 1; /* case 7a */
8949 else if (wide_nops
>= 2 && num_widens
== 1)
8950 return 1; /* case 7b */
8963 relax_frag_immed (segT segP
,
8970 bfd_boolean estimate_only
)
8974 bfd_boolean negatable_branch
= FALSE
;
8975 bfd_boolean branch_jmp_to_next
= FALSE
;
8976 bfd_boolean from_wide_insn
= FALSE
;
8977 xtensa_isa isa
= xtensa_default_isa
;
8979 offsetT frag_offset
;
8982 int num_text_bytes
, num_literal_bytes
;
8983 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8985 assert (fragP
->fr_opcode
!= NULL
);
8987 xg_clear_vinsn (&cur_vinsn
);
8988 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8989 if (cur_vinsn
.num_slots
> 1)
8990 from_wide_insn
= TRUE
;
8992 tinsn
= cur_vinsn
.slots
[slot
];
8993 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8995 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8998 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8999 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9001 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9003 old_size
= xtensa_format_length (isa
, fmt
);
9005 /* Special case: replace a branch to the next instruction with a NOP.
9006 This is required to work around a hardware bug in T1040.0 and also
9007 serves as an optimization. */
9009 if (branch_jmp_to_next
9010 && ((old_size
== 2) || (old_size
== 3))
9011 && !next_frag_is_loop_target (fragP
))
9014 /* Here is the fun stuff: Get the immediate field from this
9015 instruction. If it fits, we are done. If not, find the next
9016 instruction sequence that fits. */
9018 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9019 istack_init (&istack
);
9020 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9021 min_steps
, stretch
);
9022 if (num_steps
< min_steps
)
9024 as_fatal (_("internal error: relaxation failed"));
9028 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
9030 as_fatal (_("internal error: relaxation requires too many steps"));
9034 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9036 /* Figure out the number of bytes needed. */
9038 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9040 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9042 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9045 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9049 num_text_bytes
+= old_size
;
9050 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9051 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9054 total_text_diff
= num_text_bytes
- old_size
;
9055 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9057 /* It MUST get larger. If not, we could get an infinite loop. */
9058 assert (num_text_bytes
>= 0);
9059 assert (literal_diff
>= 0);
9060 assert (total_text_diff
>= 0);
9062 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9063 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9064 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9065 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9067 /* Find the associated expandable literal for this. */
9068 if (literal_diff
!= 0)
9070 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9073 assert (literal_diff
== 4);
9074 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9076 /* We expect that the literal section state has NOT been
9078 assert (lit_fragP
->fr_type
== rs_machine_dependent
9079 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9080 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9082 /* We need to mark this section for another iteration
9088 if (negatable_branch
&& istack
.ninsn
> 1)
9089 update_next_frag_state (fragP
);
9091 return this_text_diff
;
9095 /* md_convert_frag Hook and Helper Functions. */
9097 static void convert_frag_align_next_opcode (fragS
*);
9098 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9099 static void convert_frag_fill_nop (fragS
*);
9100 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9103 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9105 static xtensa_insnbuf vbuf
= NULL
;
9106 xtensa_isa isa
= xtensa_default_isa
;
9113 as_where (&file_name
, &line
);
9114 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9116 switch (fragp
->fr_subtype
)
9118 case RELAX_ALIGN_NEXT_OPCODE
:
9119 /* Always convert. */
9120 convert_frag_align_next_opcode (fragp
);
9123 case RELAX_DESIRE_ALIGN
:
9124 /* Do nothing. If not aligned already, too bad. */
9128 case RELAX_LITERAL_FINAL
:
9133 vbuf
= xtensa_insnbuf_alloc (isa
);
9135 xtensa_insnbuf_from_chars
9136 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9137 fmt
= xtensa_format_decode (isa
, vbuf
);
9138 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9140 for (slot
= 0; slot
< num_slots
; slot
++)
9142 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9145 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9149 case RELAX_IMMED_STEP1
:
9150 case RELAX_IMMED_STEP2
:
9151 case RELAX_IMMED_STEP3
:
9152 /* Place the immediate. */
9155 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9160 /* This is OK because some slots could have
9161 relaxations and others have none. */
9167 case RELAX_UNREACHABLE
:
9168 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9169 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9170 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9174 case RELAX_MAYBE_UNREACHABLE
:
9175 case RELAX_MAYBE_DESIRE_ALIGN
:
9179 case RELAX_FILL_NOP
:
9180 convert_frag_fill_nop (fragp
);
9183 case RELAX_LITERAL_NR
:
9184 if (use_literal_section
)
9186 /* This should have been handled during relaxation. When
9187 relaxing a code segment, literals sometimes need to be
9188 added to the corresponding literal segment. If that
9189 literal segment has already been relaxed, then we end up
9190 in this situation. Marking the literal segments as data
9191 would make this happen less often (since GAS always relaxes
9192 code before data), but we could still get into trouble if
9193 there are instructions in a segment that is not marked as
9194 containing code. Until we can implement a better solution,
9195 cheat and adjust the addresses of all the following frags.
9196 This could break subsequent alignments, but the linker's
9197 literal coalescing will do that anyway. */
9200 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9201 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9202 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9205 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9209 as_bad (_("invalid relaxation fragment result"));
9214 new_logical_line (file_name
, line
);
9219 convert_frag_align_next_opcode (fragS
*fragp
)
9221 char *nop_buf
; /* Location for Writing. */
9222 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9223 addressT aligned_address
;
9227 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9229 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9230 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9231 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9233 for (nop
= 0; nop
< nop_count
; nop
++)
9236 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9238 assemble_nop (nop_size
, nop_buf
);
9239 nop_buf
+= nop_size
;
9242 fragp
->fr_fix
+= fill_size
;
9243 fragp
->fr_var
-= fill_size
;
9248 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9250 TInsn tinsn
, single_target
;
9251 int size
, old_size
, diff
;
9252 offsetT frag_offset
;
9255 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9257 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9259 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9260 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9261 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9266 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9268 /* No conversion. */
9273 assert (fragP
->fr_opcode
!= NULL
);
9275 /* Frags in this relaxation state should only contain
9276 single instruction bundles. */
9277 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9279 /* Just convert it to a wide form.... */
9281 old_size
= xg_get_single_size (tinsn
.opcode
);
9283 tinsn_init (&single_target
);
9284 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9286 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9288 as_bad (_("unable to widen instruction"));
9292 size
= xg_get_single_size (single_target
.opcode
);
9293 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9296 diff
= size
- old_size
;
9298 assert (diff
<= fragP
->fr_var
);
9299 fragP
->fr_var
-= diff
;
9300 fragP
->fr_fix
+= diff
;
9308 convert_frag_fill_nop (fragS
*fragP
)
9310 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9311 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9312 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9313 - fragP
->fr_address
- fragP
->fr_fix
));
9316 /* No conversion. */
9320 assemble_nop (size
, loc
);
9321 fragP
->tc_frag_data
.is_insn
= TRUE
;
9322 fragP
->fr_var
-= size
;
9323 fragP
->fr_fix
+= size
;
9328 static fixS
*fix_new_exp_in_seg
9329 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9330 bfd_reloc_code_real_type
);
9331 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9334 convert_frag_immed (segT segP
,
9340 char *immed_instr
= fragP
->fr_opcode
;
9342 bfd_boolean expanded
= FALSE
;
9343 bfd_boolean branch_jmp_to_next
= FALSE
;
9344 char *fr_opcode
= fragP
->fr_opcode
;
9345 xtensa_isa isa
= xtensa_default_isa
;
9346 bfd_boolean from_wide_insn
= FALSE
;
9348 bfd_boolean is_loop
;
9350 assert (fr_opcode
!= NULL
);
9352 xg_clear_vinsn (&cur_vinsn
);
9354 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9355 if (cur_vinsn
.num_slots
> 1)
9356 from_wide_insn
= TRUE
;
9358 orig_tinsn
= cur_vinsn
.slots
[slot
];
9359 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9361 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9363 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9364 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9366 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9368 /* Conversion just inserts a NOP and marks the fix as completed. */
9369 bytes
= xtensa_format_length (isa
, fmt
);
9372 cur_vinsn
.slots
[slot
].opcode
=
9373 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9374 cur_vinsn
.slots
[slot
].ntok
= 0;
9378 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9379 assert (bytes
== 2 || bytes
== 3);
9380 build_nop (&cur_vinsn
.slots
[0], bytes
);
9381 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9383 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9384 xtensa_insnbuf_to_chars
9385 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9390 /* Here is the fun stuff: Get the immediate field from this
9391 instruction. If it fits, we're done. If not, find the next
9392 instruction sequence that fits. */
9396 symbolS
*lit_sym
= NULL
;
9398 int target_offset
= 0;
9401 symbolS
*gen_label
= NULL
;
9402 offsetT frag_offset
;
9403 bfd_boolean first
= TRUE
;
9404 bfd_boolean last_is_jump
;
9406 /* It does not fit. Find something that does and
9407 convert immediately. */
9408 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9409 istack_init (&istack
);
9410 xg_assembly_relax (&istack
, &orig_tinsn
,
9411 segP
, fragP
, frag_offset
, min_steps
, 0);
9413 old_size
= xtensa_format_length (isa
, fmt
);
9415 /* Assemble this right inline. */
9417 /* First, create the mapping from a label name to the REAL label. */
9419 for (i
= 0; i
< istack
.ninsn
; i
++)
9421 TInsn
*tinsn
= &istack
.insn
[i
];
9424 switch (tinsn
->insn_type
)
9427 if (lit_sym
!= NULL
)
9428 as_bad (_("multiple literals in expansion"));
9429 /* First find the appropriate space in the literal pool. */
9430 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9431 if (lit_frag
== NULL
)
9432 as_bad (_("no registered fragment for literal"));
9433 if (tinsn
->ntok
!= 1)
9434 as_bad (_("number of literal tokens != 1"));
9436 /* Set the literal symbol and add a fixup. */
9437 lit_sym
= lit_frag
->fr_symbol
;
9441 if (align_targets
&& !is_loop
)
9443 fragS
*unreach
= fragP
->fr_next
;
9444 while (!(unreach
->fr_type
== rs_machine_dependent
9445 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9446 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9448 unreach
= unreach
->fr_next
;
9451 assert (unreach
->fr_type
== rs_machine_dependent
9452 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9453 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9455 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9457 assert (gen_label
== NULL
);
9458 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9459 fr_opcode
- fragP
->fr_literal
9460 + target_offset
, fragP
);
9464 if (first
&& from_wide_insn
)
9466 target_offset
+= xtensa_format_length (isa
, fmt
);
9468 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9469 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9472 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9479 last_is_jump
= FALSE
;
9480 for (i
= 0; i
< istack
.ninsn
; i
++)
9482 TInsn
*tinsn
= &istack
.insn
[i
];
9486 bfd_reloc_code_real_type reloc_type
;
9488 switch (tinsn
->insn_type
)
9491 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9492 /* Already checked. */
9493 assert (lit_frag
!= NULL
);
9494 assert (lit_sym
!= NULL
);
9495 assert (tinsn
->ntok
== 1);
9497 target_seg
= S_GET_SEGMENT (lit_sym
);
9498 assert (target_seg
);
9499 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9500 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9501 &tinsn
->tok
[0], FALSE
, reloc_type
);
9508 xg_resolve_labels (tinsn
, gen_label
);
9509 xg_resolve_literals (tinsn
, lit_sym
);
9510 if (from_wide_insn
&& first
)
9513 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9515 cur_vinsn
.slots
[slot
] = *tinsn
;
9519 cur_vinsn
.slots
[slot
].opcode
=
9520 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9521 cur_vinsn
.slots
[slot
].ntok
= 0;
9523 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9524 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9525 (unsigned char *) immed_instr
, 0);
9526 fragP
->tc_frag_data
.is_insn
= TRUE
;
9527 size
= xtensa_format_length (isa
, fmt
);
9528 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9531 (tinsn
, immed_instr
+ size
, fragP
,
9532 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9533 size
+= xg_get_single_size (tinsn
->opcode
);
9538 size
= xg_get_single_size (tinsn
->opcode
);
9539 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9540 immed_instr
- fragP
->fr_literal
, TRUE
);
9542 immed_instr
+= size
;
9548 diff
= total_size
- old_size
;
9552 assert (diff
<= fragP
->fr_var
);
9553 fragP
->fr_var
-= diff
;
9554 fragP
->fr_fix
+= diff
;
9557 /* Check for undefined immediates in LOOP instructions. */
9561 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9562 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9564 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9567 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9568 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9570 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9575 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9576 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9578 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9580 /* Add an expansion note on the expanded instruction. */
9581 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9582 &orig_tinsn
.tok
[0], TRUE
,
9583 BFD_RELOC_XTENSA_ASM_EXPAND
);
9588 /* Add a new fix expression into the desired segment. We have to
9589 switch to that segment to do this. */
9592 fix_new_exp_in_seg (segT new_seg
,
9599 bfd_reloc_code_real_type r_type
)
9603 subsegT subseg
= now_subseg
;
9605 assert (new_seg
!= 0);
9606 subseg_set (new_seg
, new_subseg
);
9608 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9609 subseg_set (seg
, subseg
);
9614 /* Relax a loop instruction so that it can span loop >256 bytes.
9620 addi as, as, lo8 (label-.L1)
9621 addmi as, as, mid8 (label-.L1)
9632 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9637 unsigned long target
;
9638 static xtensa_insnbuf insnbuf
= NULL
;
9639 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9640 xtensa_isa isa
= xtensa_default_isa
;
9641 addressT loop_offset
;
9642 addressT addi_offset
= 9;
9643 addressT addmi_offset
= 12;
9648 insnbuf
= xtensa_insnbuf_alloc (isa
);
9650 /* Get the loop offset. */
9651 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9653 /* Validate that there really is a LOOP at the loop_offset. Because
9654 loops are not bundleable, we can assume that the instruction will be
9656 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9657 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9659 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9660 addi_offset
+= loop_offset
;
9661 addmi_offset
+= loop_offset
;
9663 assert (tinsn
->ntok
== 2);
9664 if (tinsn
->tok
[1].X_op
== O_constant
)
9665 target
= tinsn
->tok
[1].X_add_number
;
9666 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9668 /* Find the fragment. */
9669 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9670 assert (S_GET_SEGMENT (sym
) == segP
9671 || S_GET_SEGMENT (sym
) == absolute_section
);
9672 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9676 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9680 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9681 loop_length_hi
= loop_length
& ~0x0ff;
9682 loop_length_lo
= loop_length
& 0x0ff;
9683 if (loop_length_lo
>= 128)
9685 loop_length_lo
-= 256;
9686 loop_length_hi
+= 256;
9689 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9690 32512. If the loop is larger than that, then we just fail. */
9691 if (loop_length_hi
> 32512)
9692 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9693 _("loop too long for LOOP instruction"));
9695 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9696 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9698 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9699 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9701 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9702 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9704 fragP
->tc_frag_data
.is_insn
= TRUE
;
9705 xtensa_insnbuf_to_chars
9706 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9708 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9709 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9710 xtensa_insnbuf_to_chars
9711 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9713 /* Walk through all of the frags from here to the loop end
9714 and mark them as no_transform to keep them from being modified
9715 by the linker. If we ever have a relocation for the
9716 addi/addmi of the difference of two symbols we can remove this. */
9719 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9720 next_fragP
= next_fragP
->fr_next
)
9722 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9723 if (next_fragP
->tc_frag_data
.is_loop_target
)
9725 if (target_count
== 2)
9731 /* A map that keeps information on a per-subsegment basis. This is
9732 maintained during initial assembly, but is invalid once the
9733 subsegments are smashed together. I.E., it cannot be used during
9736 typedef struct subseg_map_struct
9744 float total_freq
; /* fall-through + branch target frequency */
9745 float target_freq
; /* branch target frequency alone */
9747 struct subseg_map_struct
*next
;
9751 static subseg_map
*sseg_map
= NULL
;
9754 get_subseg_info (segT seg
, subsegT subseg
)
9756 subseg_map
*subseg_e
;
9758 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9760 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9768 add_subseg_info (segT seg
, subsegT subseg
)
9770 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9771 memset (subseg_e
, 0, sizeof (subseg_map
));
9772 subseg_e
->seg
= seg
;
9773 subseg_e
->subseg
= subseg
;
9774 subseg_e
->flags
= 0;
9775 /* Start off considering every branch target very important. */
9776 subseg_e
->target_freq
= 1.0;
9777 subseg_e
->total_freq
= 1.0;
9778 subseg_e
->next
= sseg_map
;
9779 sseg_map
= subseg_e
;
9785 get_last_insn_flags (segT seg
, subsegT subseg
)
9787 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9789 return subseg_e
->flags
;
9795 set_last_insn_flags (segT seg
,
9800 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9802 subseg_e
= add_subseg_info (seg
, subseg
);
9804 subseg_e
->flags
|= fl
;
9806 subseg_e
->flags
&= ~fl
;
9811 get_subseg_total_freq (segT seg
, subsegT subseg
)
9813 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9815 return subseg_e
->total_freq
;
9821 get_subseg_target_freq (segT seg
, subsegT subseg
)
9823 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9825 return subseg_e
->target_freq
;
9831 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9833 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9835 subseg_e
= add_subseg_info (seg
, subseg
);
9836 subseg_e
->total_freq
= total_f
;
9837 subseg_e
->target_freq
= target_f
;
9841 /* Segment Lists and emit_state Stuff. */
9844 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9849 segT literal_section
= head
->seg
;
9851 /* Move the literal section to the front of the section list. */
9852 assert (literal_section
);
9853 if (literal_section
!= stdoutput
->sections
)
9855 bfd_section_list_remove (stdoutput
, literal_section
);
9856 bfd_section_list_prepend (stdoutput
, literal_section
);
9863 static void mark_literal_frags (seg_list
*);
9866 xtensa_move_literals (void)
9869 frchainS
*frchain_from
, *frchain_to
;
9870 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9871 fragS
**frag_splice
;
9874 fixS
*fix
, *next_fix
, **fix_splice
;
9877 mark_literal_frags (literal_head
->next
);
9879 if (use_literal_section
)
9882 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9884 /* Keep the literals for .init and .fini in separate sections. */
9885 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9886 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9889 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9890 search_frag
= frchain_from
->frch_root
;
9891 literal_pool
= NULL
;
9893 frag_splice
= &(frchain_from
->frch_root
);
9895 while (!search_frag
->tc_frag_data
.literal_frag
)
9897 assert (search_frag
->fr_fix
== 0
9898 || search_frag
->fr_type
== rs_align
);
9899 search_frag
= search_frag
->fr_next
;
9902 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9903 == RELAX_LITERAL_POOL_BEGIN
);
9904 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9906 /* Make sure that all the frags in this series are closed, and
9907 that there is at least one left over of zero-size. This
9908 prevents us from making a segment with an frchain without any
9910 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9911 xtensa_set_frag_assembly_state (frag_now
);
9912 last_frag
= frag_now
;
9913 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9914 xtensa_set_frag_assembly_state (frag_now
);
9916 while (search_frag
!= frag_now
)
9918 next_frag
= search_frag
->fr_next
;
9920 /* First, move the frag out of the literal section and
9921 to the appropriate place. */
9922 if (search_frag
->tc_frag_data
.literal_frag
)
9924 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9925 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9926 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9927 assert (frchain_to
);
9929 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
9930 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9932 *frag_splice
= next_frag
;
9933 search_frag
->fr_next
= insert_after
->fr_next
;
9934 insert_after
->fr_next
= search_frag
;
9935 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9936 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
9938 /* Now move any fixups associated with this frag to the
9940 fix
= frchain_from
->fix_root
;
9941 fix_splice
= &(frchain_from
->fix_root
);
9944 next_fix
= fix
->fx_next
;
9945 if (fix
->fx_frag
== search_frag
)
9947 *fix_splice
= next_fix
;
9948 fix
->fx_next
= frchain_to
->fix_root
;
9949 frchain_to
->fix_root
= fix
;
9950 if (frchain_to
->fix_tail
== NULL
)
9951 frchain_to
->fix_tail
= fix
;
9954 fix_splice
= &(fix
->fx_next
);
9957 search_frag
= next_frag
;
9960 if (frchain_from
->fix_root
!= NULL
)
9962 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9963 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9965 assert (frchain_from
->fix_root
== NULL
);
9967 frchain_from
->fix_tail
= NULL
;
9968 xtensa_restore_emit_state (&state
);
9971 /* Now fix up the SEGMENT value for all the literal symbols. */
9972 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9974 symbolS
*lit_sym
= lit
->sym
;
9975 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9977 S_SET_SEGMENT (lit_sym
, dest_seg
);
9982 /* Walk over all the frags for segments in a list and mark them as
9983 containing literals. As clunky as this is, we can't rely on frag_var
9984 and frag_variant to get called in all situations. */
9987 mark_literal_frags (seg_list
*segment
)
9989 frchainS
*frchain_from
;
9994 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9995 search_frag
= frchain_from
->frch_root
;
9998 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9999 search_frag
= search_frag
->fr_next
;
10001 segment
= segment
->next
;
10007 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10009 /* Move all of the sections in the section list to come
10010 after "after" in the gnu segment list. */
10015 segT literal_section
= head
->seg
;
10017 /* Move the literal section after "after". */
10018 assert (literal_section
);
10019 if (literal_section
!= after
)
10021 bfd_section_list_remove (stdoutput
, literal_section
);
10022 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10030 /* Push all the literal segments to the end of the gnu list. */
10033 xtensa_reorder_segments (void)
10040 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10046 /* Now that we have the last section, push all the literal
10047 sections to the end. */
10048 xtensa_reorder_seg_list (literal_head
, last_sec
);
10050 /* Now perform the final error check. */
10051 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10053 assert (new_count
== old_count
);
10057 /* Change the emit state (seg, subseg, and frag related stuff) to the
10058 correct location. Return a emit_state which can be passed to
10059 xtensa_restore_emit_state to return to current fragment. */
10062 xtensa_switch_to_literal_fragment (emit_state
*result
)
10064 if (directive_state
[directive_absolute_literals
])
10066 segT lit4_seg
= cache_literal_section (TRUE
);
10067 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10070 xtensa_switch_to_non_abs_literal_fragment (result
);
10072 /* Do a 4-byte align here. */
10073 frag_align (2, 0, 0);
10074 record_alignment (now_seg
, 2);
10079 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10081 static bfd_boolean recursive
= FALSE
;
10082 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10084 bfd_boolean is_init
=
10085 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10086 bfd_boolean is_fini
=
10087 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10089 if (pool_location
== NULL
10090 && !use_literal_section
10092 && !is_init
&& ! is_fini
)
10094 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10096 /* When we mark a literal pool location, we want to put a frag in
10097 the literal pool that points to it. But to do that, we want to
10098 switch_to_literal_fragment. But literal sections don't have
10099 literal pools, so their location is always null, so we would
10100 recurse forever. This is kind of hacky, but it works. */
10103 xtensa_mark_literal_pool_location ();
10107 lit_seg
= cache_literal_section (FALSE
);
10108 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10110 if (!use_literal_section
10111 && !is_init
&& !is_fini
10112 && get_literal_pool_location (now_seg
) != pool_location
)
10114 /* Close whatever frag is there. */
10115 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10116 xtensa_set_frag_assembly_state (frag_now
);
10117 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10118 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10119 xtensa_set_frag_assembly_state (frag_now
);
10124 /* Call this function before emitting data into the literal section.
10125 This is a helper function for xtensa_switch_to_literal_fragment.
10126 This is similar to a .section new_now_seg subseg. */
10129 xtensa_switch_section_emit_state (emit_state
*state
,
10131 subsegT new_now_subseg
)
10133 state
->name
= now_seg
->name
;
10134 state
->now_seg
= now_seg
;
10135 state
->now_subseg
= now_subseg
;
10136 state
->generating_literals
= generating_literals
;
10137 generating_literals
++;
10138 subseg_set (new_now_seg
, new_now_subseg
);
10142 /* Use to restore the emitting into the normal place. */
10145 xtensa_restore_emit_state (emit_state
*state
)
10147 generating_literals
= state
->generating_literals
;
10148 subseg_set (state
->now_seg
, state
->now_subseg
);
10152 /* Predicate function used to look up a section in a particular group. */
10155 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10157 const char *gname
= inf
;
10158 const char *group_name
= elf_group_name (sec
);
10160 return (group_name
== gname
10161 || (group_name
!= NULL
10163 && strcmp (group_name
, gname
) == 0));
10167 /* Get the literal section to be used for the current text section.
10168 The result may be cached in the default_lit_sections structure. */
10171 cache_literal_section (bfd_boolean use_abs_literals
)
10173 const char *text_name
, *group_name
= 0;
10174 char *base_name
, *name
, *suffix
;
10176 segT seg
, current_section
;
10177 int current_subsec
;
10178 bfd_boolean linkonce
= FALSE
;
10180 /* Save the current section/subsection. */
10181 current_section
= now_seg
;
10182 current_subsec
= now_subseg
;
10184 /* Clear the cached values if they are no longer valid. */
10185 if (now_seg
!= default_lit_sections
.current_text_seg
)
10187 default_lit_sections
.current_text_seg
= now_seg
;
10188 default_lit_sections
.lit_seg
= NULL
;
10189 default_lit_sections
.lit4_seg
= NULL
;
10192 /* Check if the literal section is already cached. */
10193 if (use_abs_literals
)
10194 pcached
= &default_lit_sections
.lit4_seg
;
10196 pcached
= &default_lit_sections
.lit_seg
;
10201 text_name
= default_lit_sections
.lit_prefix
;
10202 if (! text_name
|| ! *text_name
)
10204 text_name
= segment_name (current_section
);
10205 group_name
= elf_group_name (current_section
);
10206 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10209 base_name
= use_abs_literals
? ".lit4" : ".literal";
10212 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10213 sprintf (name
, "%s.%s", base_name
, group_name
);
10215 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10217 suffix
= strchr (text_name
+ linkonce_len
, '.');
10219 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10220 + (suffix
? strlen (suffix
) : 0));
10221 strcpy (name
, ".gnu.linkonce");
10222 strcat (name
, base_name
);
10224 strcat (name
, suffix
);
10229 /* If the section name ends with ".text", then replace that suffix
10230 instead of appending an additional suffix. */
10231 size_t len
= strlen (text_name
);
10232 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10235 name
= xmalloc (len
+ strlen (base_name
) + 1);
10236 strcpy (name
, text_name
);
10237 strcpy (name
+ len
, base_name
);
10240 /* Canonicalize section names to allow renaming literal sections.
10241 The group name, if any, came from the current text section and
10242 has already been canonicalized. */
10243 name
= tc_canonicalize_symbol_name (name
);
10245 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10246 (void *) group_name
);
10251 seg
= subseg_force_new (name
, 0);
10253 if (! use_abs_literals
)
10255 /* Add the newly created literal segment to the list. */
10256 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10258 n
->next
= literal_head
->next
;
10259 literal_head
->next
= n
;
10262 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10263 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10264 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10266 elf_group_name (seg
) = group_name
;
10268 bfd_set_section_flags (stdoutput
, seg
, flags
);
10269 bfd_set_section_alignment (stdoutput
, seg
, 2);
10273 subseg_set (current_section
, current_subsec
);
10278 /* Property Tables Stuff. */
10280 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10281 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10282 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10284 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10285 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10287 static bfd_boolean
get_frag_is_literal (const fragS
*);
10288 static void xtensa_create_property_segments
10289 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10290 static void xtensa_create_xproperty_segments
10291 (frag_flags_fn
, const char *, xt_section_type
);
10292 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10293 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10294 static void add_xt_block_frags
10295 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10296 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10297 static void xtensa_frag_flags_init (frag_flags
*);
10298 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10299 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10300 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10302 /* Set up property tables after relaxation. */
10305 xtensa_post_relax_hook (void)
10307 xtensa_move_seg_list_to_beginning (literal_head
);
10309 xtensa_find_unmarked_state_frags ();
10310 xtensa_mark_frags_for_org ();
10311 xtensa_mark_difference_of_two_symbols ();
10313 xtensa_create_property_segments (get_frag_is_literal
,
10315 XTENSA_LIT_SEC_NAME
,
10317 xtensa_create_xproperty_segments (get_frag_property_flags
,
10318 XTENSA_PROP_SEC_NAME
,
10321 if (warn_unaligned_branch_targets
)
10322 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10323 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10327 /* This function is only meaningful after xtensa_move_literals. */
10330 get_frag_is_literal (const fragS
*fragP
)
10332 assert (fragP
!= NULL
);
10333 return fragP
->tc_frag_data
.is_literal
;
10338 xtensa_create_property_segments (frag_predicate property_function
,
10339 frag_predicate end_property_function
,
10340 const char *section_name_base
,
10341 xt_section_type sec_type
)
10345 /* Walk over all of the current segments.
10346 Walk over each fragment
10347 For each non-empty fragment,
10348 Build a property record (append where possible). */
10350 for (seclist
= &stdoutput
->sections
;
10351 seclist
&& *seclist
;
10352 seclist
= &(*seclist
)->next
)
10354 segT sec
= *seclist
;
10357 flags
= bfd_get_section_flags (stdoutput
, sec
);
10358 if (flags
& SEC_DEBUGGING
)
10360 if (!(flags
& SEC_ALLOC
))
10363 if (section_has_property (sec
, property_function
))
10365 segment_info_type
*xt_seg_info
;
10366 xtensa_block_info
**xt_blocks
;
10367 segT prop_sec
= xtensa_get_property_section (sec
, section_name_base
);
10369 prop_sec
->output_section
= prop_sec
;
10370 subseg_set (prop_sec
, 0);
10371 xt_seg_info
= seg_info (prop_sec
);
10372 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10374 /* Walk over all of the frchains here and add new sections. */
10375 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10376 end_property_function
);
10380 /* Now we fill them out.... */
10382 for (seclist
= &stdoutput
->sections
;
10383 seclist
&& *seclist
;
10384 seclist
= &(*seclist
)->next
)
10386 segment_info_type
*seginfo
;
10387 xtensa_block_info
*block
;
10388 segT sec
= *seclist
;
10390 seginfo
= seg_info (sec
);
10391 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10395 xtensa_block_info
*cur_block
;
10397 bfd_size_type rec_size
;
10399 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10402 rec_size
= num_recs
* 8;
10403 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10410 subseg_set (sec
, 0);
10411 frag_data
= frag_more (rec_size
);
10413 for (i
= 0; i
< num_recs
; i
++)
10417 /* Write the fixup. */
10418 assert (cur_block
);
10419 fix
= fix_new (frag_now
, i
* 8, 4,
10420 section_symbol (cur_block
->sec
),
10422 FALSE
, BFD_RELOC_32
);
10423 fix
->fx_file
= "<internal>";
10426 /* Write the length. */
10427 md_number_to_chars (&frag_data
[4 + i
* 8],
10428 cur_block
->size
, 4);
10429 cur_block
= cur_block
->next
;
10431 frag_wane (frag_now
);
10433 frag_wane (frag_now
);
10441 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10442 const char *section_name_base
,
10443 xt_section_type sec_type
)
10447 /* Walk over all of the current segments.
10448 Walk over each fragment.
10449 For each fragment that has instructions,
10450 build an instruction record (append where possible). */
10452 for (seclist
= &stdoutput
->sections
;
10453 seclist
&& *seclist
;
10454 seclist
= &(*seclist
)->next
)
10456 segT sec
= *seclist
;
10459 flags
= bfd_get_section_flags (stdoutput
, sec
);
10460 if ((flags
& SEC_DEBUGGING
)
10461 || !(flags
& SEC_ALLOC
)
10462 || (flags
& SEC_MERGE
))
10465 if (section_has_xproperty (sec
, flag_fn
))
10467 segment_info_type
*xt_seg_info
;
10468 xtensa_block_info
**xt_blocks
;
10469 segT prop_sec
= xtensa_get_property_section (sec
, section_name_base
);
10471 prop_sec
->output_section
= prop_sec
;
10472 subseg_set (prop_sec
, 0);
10473 xt_seg_info
= seg_info (prop_sec
);
10474 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10476 /* Walk over all of the frchains here and add new sections. */
10477 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10481 /* Now we fill them out.... */
10483 for (seclist
= &stdoutput
->sections
;
10484 seclist
&& *seclist
;
10485 seclist
= &(*seclist
)->next
)
10487 segment_info_type
*seginfo
;
10488 xtensa_block_info
*block
;
10489 segT sec
= *seclist
;
10491 seginfo
= seg_info (sec
);
10492 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10496 xtensa_block_info
*cur_block
;
10498 bfd_size_type rec_size
;
10500 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10503 rec_size
= num_recs
* (8 + 4);
10504 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10505 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10512 subseg_set (sec
, 0);
10513 frag_data
= frag_more (rec_size
);
10515 for (i
= 0; i
< num_recs
; i
++)
10519 /* Write the fixup. */
10520 assert (cur_block
);
10521 fix
= fix_new (frag_now
, i
* 12, 4,
10522 section_symbol (cur_block
->sec
),
10524 FALSE
, BFD_RELOC_32
);
10525 fix
->fx_file
= "<internal>";
10528 /* Write the length. */
10529 md_number_to_chars (&frag_data
[4 + i
* 12],
10530 cur_block
->size
, 4);
10531 md_number_to_chars (&frag_data
[8 + i
* 12],
10532 frag_flags_to_number (&cur_block
->flags
),
10534 cur_block
= cur_block
->next
;
10536 frag_wane (frag_now
);
10538 frag_wane (frag_now
);
10546 section_has_property (segT sec
, frag_predicate property_function
)
10548 segment_info_type
*seginfo
= seg_info (sec
);
10551 if (seginfo
&& seginfo
->frchainP
)
10553 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10555 if (property_function (fragP
)
10556 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10565 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10567 segment_info_type
*seginfo
= seg_info (sec
);
10570 if (seginfo
&& seginfo
->frchainP
)
10572 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10574 frag_flags prop_flags
;
10575 property_function (fragP
, &prop_flags
);
10576 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10584 /* Two types of block sections exist right now: literal and insns. */
10587 add_xt_block_frags (segT sec
,
10588 xtensa_block_info
**xt_block
,
10589 frag_predicate property_function
,
10590 frag_predicate end_property_function
)
10592 bfd_vma seg_offset
;
10595 /* Build it if needed. */
10596 while (*xt_block
!= NULL
)
10597 xt_block
= &(*xt_block
)->next
;
10598 /* We are either at NULL at the beginning or at the end. */
10600 /* Walk through the frags. */
10603 if (seg_info (sec
)->frchainP
)
10605 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10607 fragP
= fragP
->fr_next
)
10609 if (property_function (fragP
)
10610 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10612 if (*xt_block
!= NULL
)
10614 if ((*xt_block
)->offset
+ (*xt_block
)->size
10615 == fragP
->fr_address
)
10616 (*xt_block
)->size
+= fragP
->fr_fix
;
10618 xt_block
= &((*xt_block
)->next
);
10620 if (*xt_block
== NULL
)
10622 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10623 xmalloc (sizeof (xtensa_block_info
));
10624 new_block
->sec
= sec
;
10625 new_block
->offset
= fragP
->fr_address
;
10626 new_block
->size
= fragP
->fr_fix
;
10627 new_block
->next
= NULL
;
10628 xtensa_frag_flags_init (&new_block
->flags
);
10629 *xt_block
= new_block
;
10631 if (end_property_function
10632 && end_property_function (fragP
))
10634 xt_block
= &((*xt_block
)->next
);
10642 /* Break the encapsulation of add_xt_prop_frags here. */
10645 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10647 if (prop_flags
->is_literal
10648 || prop_flags
->is_insn
10649 || prop_flags
->is_data
10650 || prop_flags
->is_unreachable
)
10657 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10659 memset (prop_flags
, 0, sizeof (frag_flags
));
10664 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10666 xtensa_frag_flags_init (prop_flags
);
10667 if (fragP
->tc_frag_data
.is_literal
)
10668 prop_flags
->is_literal
= TRUE
;
10669 if (fragP
->tc_frag_data
.is_specific_opcode
10670 || fragP
->tc_frag_data
.is_no_transform
)
10671 prop_flags
->is_no_transform
= TRUE
;
10672 if (fragP
->tc_frag_data
.is_unreachable
)
10673 prop_flags
->is_unreachable
= TRUE
;
10674 else if (fragP
->tc_frag_data
.is_insn
)
10676 prop_flags
->is_insn
= TRUE
;
10677 if (fragP
->tc_frag_data
.is_loop_target
)
10678 prop_flags
->insn
.is_loop_target
= TRUE
;
10679 if (fragP
->tc_frag_data
.is_branch_target
)
10680 prop_flags
->insn
.is_branch_target
= TRUE
;
10681 if (fragP
->tc_frag_data
.is_no_density
)
10682 prop_flags
->insn
.is_no_density
= TRUE
;
10683 if (fragP
->tc_frag_data
.use_absolute_literals
)
10684 prop_flags
->insn
.is_abslit
= TRUE
;
10686 if (fragP
->tc_frag_data
.is_align
)
10688 prop_flags
->is_align
= TRUE
;
10689 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10690 if (xtensa_frag_flags_is_empty (prop_flags
))
10691 prop_flags
->is_data
= TRUE
;
10697 frag_flags_to_number (const frag_flags
*prop_flags
)
10700 if (prop_flags
->is_literal
)
10701 num
|= XTENSA_PROP_LITERAL
;
10702 if (prop_flags
->is_insn
)
10703 num
|= XTENSA_PROP_INSN
;
10704 if (prop_flags
->is_data
)
10705 num
|= XTENSA_PROP_DATA
;
10706 if (prop_flags
->is_unreachable
)
10707 num
|= XTENSA_PROP_UNREACHABLE
;
10708 if (prop_flags
->insn
.is_loop_target
)
10709 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10710 if (prop_flags
->insn
.is_branch_target
)
10712 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10713 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10716 if (prop_flags
->insn
.is_no_density
)
10717 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10718 if (prop_flags
->is_no_transform
)
10719 num
|= XTENSA_PROP_NO_TRANSFORM
;
10720 if (prop_flags
->insn
.is_no_reorder
)
10721 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10722 if (prop_flags
->insn
.is_abslit
)
10723 num
|= XTENSA_PROP_INSN_ABSLIT
;
10725 if (prop_flags
->is_align
)
10727 num
|= XTENSA_PROP_ALIGN
;
10728 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10736 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10737 const frag_flags
*prop_flags_2
)
10739 /* Cannot combine with an end marker. */
10741 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10743 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10745 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10748 if (prop_flags_1
->is_insn
)
10750 /* Properties of the beginning of the frag. */
10751 if (prop_flags_2
->insn
.is_loop_target
)
10753 if (prop_flags_2
->insn
.is_branch_target
)
10755 if (prop_flags_1
->insn
.is_no_density
!=
10756 prop_flags_2
->insn
.is_no_density
)
10758 if (prop_flags_1
->is_no_transform
!=
10759 prop_flags_2
->is_no_transform
)
10761 if (prop_flags_1
->insn
.is_no_reorder
!=
10762 prop_flags_2
->insn
.is_no_reorder
)
10764 if (prop_flags_1
->insn
.is_abslit
!=
10765 prop_flags_2
->insn
.is_abslit
)
10769 if (prop_flags_1
->is_align
)
10777 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10780 unsigned align_bits
;
10782 if (!xt_block
->flags
.is_align
)
10783 return xt_block
->size
;
10785 end_addr
= xt_block
->offset
+ xt_block
->size
;
10786 align_bits
= xt_block
->flags
.alignment
;
10787 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10788 return end_addr
- xt_block
->offset
;
10793 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10794 const xtensa_block_info
*xt_block_2
)
10796 if (xt_block
->sec
!= xt_block_2
->sec
)
10798 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10799 != xt_block_2
->offset
)
10802 if (xt_block_2
->size
== 0
10803 && (!xt_block_2
->flags
.is_unreachable
10804 || xt_block
->flags
.is_unreachable
))
10806 if (xt_block_2
->flags
.is_align
10807 && xt_block
->flags
.is_align
)
10809 /* Nothing needed. */
10810 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10815 if (xt_block_2
->flags
.is_align
)
10817 /* Push alignment to previous entry. */
10818 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10819 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10824 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10825 &xt_block_2
->flags
))
10828 xt_block
->size
+= xt_block_2
->size
;
10830 if (xt_block_2
->flags
.is_align
)
10832 xt_block
->flags
.is_align
= TRUE
;
10833 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10841 add_xt_prop_frags (segT sec
,
10842 xtensa_block_info
**xt_block
,
10843 frag_flags_fn property_function
)
10845 bfd_vma seg_offset
;
10848 /* Build it if needed. */
10849 while (*xt_block
!= NULL
)
10851 xt_block
= &(*xt_block
)->next
;
10853 /* We are either at NULL at the beginning or at the end. */
10855 /* Walk through the frags. */
10858 if (seg_info (sec
)->frchainP
)
10860 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
10861 fragP
= fragP
->fr_next
)
10863 xtensa_block_info tmp_block
;
10864 tmp_block
.sec
= sec
;
10865 tmp_block
.offset
= fragP
->fr_address
;
10866 tmp_block
.size
= fragP
->fr_fix
;
10867 tmp_block
.next
= NULL
;
10868 property_function (fragP
, &tmp_block
.flags
);
10870 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10871 /* && fragP->fr_fix != 0) */
10873 if ((*xt_block
) == NULL
10874 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10876 xtensa_block_info
*new_block
;
10877 if ((*xt_block
) != NULL
)
10878 xt_block
= &(*xt_block
)->next
;
10879 new_block
= (xtensa_block_info
*)
10880 xmalloc (sizeof (xtensa_block_info
));
10881 *new_block
= tmp_block
;
10882 *xt_block
= new_block
;
10890 /* op_placement_info_table */
10892 /* op_placement_info makes it easier to determine which
10893 ops can go in which slots. */
10896 init_op_placement_info_table (void)
10898 xtensa_isa isa
= xtensa_default_isa
;
10899 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10900 xtensa_opcode opcode
;
10903 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10905 op_placement_table
= (op_placement_info_table
)
10906 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10907 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10909 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10911 op_placement_info
*opi
= &op_placement_table
[opcode
];
10912 /* FIXME: Make tinsn allocation dynamic. */
10913 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10914 as_fatal (_("too many operands in instruction"));
10915 opi
->narrowest
= XTENSA_UNDEFINED
;
10916 opi
->narrowest_size
= 0x7F;
10917 opi
->narrowest_slot
= 0;
10919 opi
->num_formats
= 0;
10921 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10923 opi
->slots
[fmt
] = 0;
10924 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10926 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10928 int fmt_length
= xtensa_format_length (isa
, fmt
);
10930 set_bit (fmt
, opi
->formats
);
10931 set_bit (slot
, opi
->slots
[fmt
]);
10932 if (fmt_length
< opi
->narrowest_size
10933 || (fmt_length
== opi
->narrowest_size
10934 && (xtensa_format_num_slots (isa
, fmt
)
10935 < xtensa_format_num_slots (isa
,
10938 opi
->narrowest
= fmt
;
10939 opi
->narrowest_size
= fmt_length
;
10940 opi
->narrowest_slot
= slot
;
10945 opi
->num_formats
++;
10948 xtensa_insnbuf_free (isa
, ibuf
);
10953 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10955 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10959 /* If the opcode is available in a single slot format, return its size. */
10962 xg_get_single_size (xtensa_opcode opcode
)
10964 return op_placement_table
[opcode
].narrowest_size
;
10968 static xtensa_format
10969 xg_get_single_format (xtensa_opcode opcode
)
10971 return op_placement_table
[opcode
].narrowest
;
10976 xg_get_single_slot (xtensa_opcode opcode
)
10978 return op_placement_table
[opcode
].narrowest_slot
;
10982 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10985 istack_init (IStack
*stack
)
10987 memset (stack
, 0, sizeof (IStack
));
10993 istack_empty (IStack
*stack
)
10995 return (stack
->ninsn
== 0);
11000 istack_full (IStack
*stack
)
11002 return (stack
->ninsn
== MAX_ISTACK
);
11006 /* Return a pointer to the top IStack entry.
11007 It is an error to call this if istack_empty () is TRUE. */
11010 istack_top (IStack
*stack
)
11012 int rec
= stack
->ninsn
- 1;
11013 assert (!istack_empty (stack
));
11014 return &stack
->insn
[rec
];
11018 /* Add a new TInsn to an IStack.
11019 It is an error to call this if istack_full () is TRUE. */
11022 istack_push (IStack
*stack
, TInsn
*insn
)
11024 int rec
= stack
->ninsn
;
11025 assert (!istack_full (stack
));
11026 stack
->insn
[rec
] = *insn
;
11031 /* Clear space for the next TInsn on the IStack and return a pointer
11032 to it. It is an error to call this if istack_full () is TRUE. */
11035 istack_push_space (IStack
*stack
)
11037 int rec
= stack
->ninsn
;
11039 assert (!istack_full (stack
));
11040 insn
= &stack
->insn
[rec
];
11047 /* Remove the last pushed instruction. It is an error to call this if
11048 istack_empty () returns TRUE. */
11051 istack_pop (IStack
*stack
)
11053 int rec
= stack
->ninsn
- 1;
11054 assert (!istack_empty (stack
));
11056 tinsn_init (&stack
->insn
[rec
]);
11060 /* TInsn functions. */
11063 tinsn_init (TInsn
*dst
)
11065 memset (dst
, 0, sizeof (TInsn
));
11069 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11072 tinsn_has_symbolic_operands (const TInsn
*insn
)
11075 int n
= insn
->ntok
;
11077 assert (insn
->insn_type
== ITYPE_INSN
);
11079 for (i
= 0; i
< n
; ++i
)
11081 switch (insn
->tok
[i
].X_op
)
11095 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11097 xtensa_isa isa
= xtensa_default_isa
;
11099 int n
= insn
->ntok
;
11101 assert (insn
->insn_type
== ITYPE_INSN
);
11103 for (i
= 0; i
< n
; ++i
)
11105 switch (insn
->tok
[i
].X_op
)
11113 /* Errors for these types are caught later. */
11118 /* Symbolic immediates are only allowed on the last immediate
11119 operand. At this time, CONST16 is the only opcode where we
11120 support non-PC-relative relocations. */
11121 if (i
!= get_relaxable_immed (insn
->opcode
)
11122 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11123 && insn
->opcode
!= xtensa_const16_opcode
))
11125 as_bad (_("invalid symbolic operand"));
11134 /* For assembly code with complex expressions (e.g. subtraction),
11135 we have to build them in the literal pool so that
11136 their results are calculated correctly after relaxation.
11137 The relaxation only handles expressions that
11138 boil down to SYMBOL + OFFSET. */
11141 tinsn_has_complex_operands (const TInsn
*insn
)
11144 int n
= insn
->ntok
;
11145 assert (insn
->insn_type
== ITYPE_INSN
);
11146 for (i
= 0; i
< n
; ++i
)
11148 switch (insn
->tok
[i
].X_op
)
11164 /* Encode a TInsn opcode and its constant operands into slotbuf.
11165 Return TRUE if there is a symbol in the immediate field. This
11166 function assumes that:
11167 1) The number of operands are correct.
11168 2) The insn_type is ITYPE_INSN.
11169 3) The opcode can be encoded in the specified format and slot.
11170 4) Operands are either O_constant or O_symbol, and all constants fit. */
11173 tinsn_to_slotbuf (xtensa_format fmt
,
11176 xtensa_insnbuf slotbuf
)
11178 xtensa_isa isa
= xtensa_default_isa
;
11179 xtensa_opcode opcode
= tinsn
->opcode
;
11180 bfd_boolean has_fixup
= FALSE
;
11181 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11184 assert (tinsn
->insn_type
== ITYPE_INSN
);
11185 if (noperands
!= tinsn
->ntok
)
11186 as_fatal (_("operand number mismatch"));
11188 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11190 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11191 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11195 for (i
= 0; i
< noperands
; i
++)
11197 expressionS
*expr
= &tinsn
->tok
[i
];
11203 switch (expr
->X_op
)
11206 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11208 /* The register number has already been checked in
11209 expression_maybe_register, so we don't need to check here. */
11210 opnd_value
= expr
->X_add_number
;
11211 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11212 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11215 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11219 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11221 as_where (&file_name
, &line
);
11222 /* It is a constant and we called this function
11223 then we have to try to fit it. */
11224 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11225 expr
->X_add_number
, file_name
, line
);
11238 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11239 into a multi-slot instruction, fill the other slots with NOPs.
11240 Return TRUE if there is a symbol in the immediate field. See also the
11241 assumptions listed for tinsn_to_slotbuf. */
11244 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11246 static xtensa_insnbuf slotbuf
= 0;
11247 static vliw_insn vinsn
;
11248 xtensa_isa isa
= xtensa_default_isa
;
11249 bfd_boolean has_fixup
= FALSE
;
11254 slotbuf
= xtensa_insnbuf_alloc (isa
);
11255 xg_init_vinsn (&vinsn
);
11258 xg_clear_vinsn (&vinsn
);
11260 bundle_tinsn (tinsn
, &vinsn
);
11262 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11264 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11266 /* Only one slot may have a fix-up because the rest contains NOPs. */
11268 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11269 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11276 /* Check the instruction arguments. Return TRUE on failure. */
11279 tinsn_check_arguments (const TInsn
*insn
)
11281 xtensa_isa isa
= xtensa_default_isa
;
11282 xtensa_opcode opcode
= insn
->opcode
;
11284 if (opcode
== XTENSA_UNDEFINED
)
11286 as_bad (_("invalid opcode"));
11290 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11292 as_bad (_("too few operands"));
11296 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11298 as_bad (_("too many operands"));
11305 /* Load an instruction from its encoded form. */
11308 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11312 xg_init_vinsn (&vinsn
);
11313 vinsn_from_chars (&vinsn
, f
);
11315 *tinsn
= vinsn
.slots
[slot
];
11316 xg_free_vinsn (&vinsn
);
11321 tinsn_from_insnbuf (TInsn
*tinsn
,
11322 xtensa_insnbuf slotbuf
,
11327 xtensa_isa isa
= xtensa_default_isa
;
11329 /* Find the immed. */
11330 tinsn_init (tinsn
);
11331 tinsn
->insn_type
= ITYPE_INSN
;
11332 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11333 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11334 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11335 for (i
= 0; i
< tinsn
->ntok
; i
++)
11337 set_expr_const (&tinsn
->tok
[i
],
11338 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11339 tinsn
->opcode
, i
));
11344 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11347 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11349 xtensa_opcode opcode
= tinsn
->opcode
;
11352 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11354 opnum
= get_relaxable_immed (opcode
);
11355 assert (opnum
>= 0);
11356 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11357 fragP
->tc_frag_data
.slot_symbols
[slot
],
11358 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11364 get_num_stack_text_bytes (IStack
*istack
)
11367 int text_bytes
= 0;
11369 for (i
= 0; i
< istack
->ninsn
; i
++)
11371 TInsn
*tinsn
= &istack
->insn
[i
];
11372 if (tinsn
->insn_type
== ITYPE_INSN
)
11373 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11380 get_num_stack_literal_bytes (IStack
*istack
)
11385 for (i
= 0; i
< istack
->ninsn
; i
++)
11387 TInsn
*tinsn
= &istack
->insn
[i
];
11388 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11395 /* vliw_insn functions. */
11398 xg_init_vinsn (vliw_insn
*v
)
11401 xtensa_isa isa
= xtensa_default_isa
;
11403 xg_clear_vinsn (v
);
11405 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11406 if (v
->insnbuf
== NULL
)
11407 as_fatal (_("out of memory"));
11409 for (i
= 0; i
< MAX_SLOTS
; i
++)
11411 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11412 if (v
->slotbuf
[i
] == NULL
)
11413 as_fatal (_("out of memory"));
11419 xg_clear_vinsn (vliw_insn
*v
)
11423 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11425 v
->format
= XTENSA_UNDEFINED
;
11427 v
->inside_bundle
= FALSE
;
11429 if (xt_saved_debug_type
!= DEBUG_NONE
)
11430 debug_type
= xt_saved_debug_type
;
11432 for (i
= 0; i
< MAX_SLOTS
; i
++)
11433 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11438 vinsn_has_specific_opcodes (vliw_insn
*v
)
11442 for (i
= 0; i
< v
->num_slots
; i
++)
11444 if (v
->slots
[i
].is_specific_opcode
)
11452 xg_free_vinsn (vliw_insn
*v
)
11455 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11456 for (i
= 0; i
< MAX_SLOTS
; i
++)
11457 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11461 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11462 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11465 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11468 bfd_boolean record_fixup
)
11470 xtensa_isa isa
= xtensa_default_isa
;
11471 xtensa_format fmt
= vinsn
->format
;
11472 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11474 bfd_boolean has_fixup
= FALSE
;
11476 xtensa_format_encode (isa
, fmt
, insnbuf
);
11478 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11480 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11481 bfd_boolean tinsn_has_fixup
=
11482 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11483 vinsn
->slotbuf
[slot
]);
11485 xtensa_format_set_slot (isa
, fmt
, slot
,
11486 insnbuf
, vinsn
->slotbuf
[slot
]);
11487 if (tinsn_has_fixup
)
11490 xtensa_opcode opcode
= tinsn
->opcode
;
11491 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11494 for (i
= 0; i
< noperands
; i
++)
11496 expressionS
* expr
= &tinsn
->tok
[i
];
11497 switch (expr
->X_op
)
11502 if (get_relaxable_immed (opcode
) == i
)
11504 /* Add a fix record for the instruction, except if this
11505 function is being called prior to relaxation, i.e.,
11506 if record_fixup is false, and the instruction might
11507 be relaxed later. */
11509 || tinsn
->is_specific_opcode
11510 || !xg_is_relaxable_insn (tinsn
, 0))
11512 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11513 frag_offset
- fragP
->fr_literal
);
11517 if (expr
->X_op
!= O_symbol
)
11518 as_bad (_("invalid operand"));
11519 tinsn
->symbol
= expr
->X_add_symbol
;
11520 tinsn
->offset
= expr
->X_add_number
;
11524 as_bad (_("symbolic operand not allowed"));
11532 as_bad (_("expression too complex"));
11544 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11546 static xtensa_insnbuf insnbuf
= NULL
;
11547 static xtensa_insnbuf slotbuf
= NULL
;
11550 xtensa_isa isa
= xtensa_default_isa
;
11554 insnbuf
= xtensa_insnbuf_alloc (isa
);
11555 slotbuf
= xtensa_insnbuf_alloc (isa
);
11558 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11559 fmt
= xtensa_format_decode (isa
, insnbuf
);
11560 if (fmt
== XTENSA_UNDEFINED
)
11561 as_fatal (_("cannot decode instruction format"));
11562 vinsn
->format
= fmt
;
11563 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11565 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11567 TInsn
*tinsn
= &vinsn
->slots
[i
];
11568 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11569 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11574 /* Expression utilities. */
11576 /* Return TRUE if the expression is an integer constant. */
11579 expr_is_const (const expressionS
*s
)
11581 return (s
->X_op
== O_constant
);
11585 /* Get the expression constant.
11586 Calling this is illegal if expr_is_const () returns TRUE. */
11589 get_expr_const (const expressionS
*s
)
11591 assert (expr_is_const (s
));
11592 return s
->X_add_number
;
11596 /* Set the expression to a constant value. */
11599 set_expr_const (expressionS
*s
, offsetT val
)
11601 s
->X_op
= O_constant
;
11602 s
->X_add_number
= val
;
11603 s
->X_add_symbol
= NULL
;
11604 s
->X_op_symbol
= NULL
;
11609 expr_is_register (const expressionS
*s
)
11611 return (s
->X_op
== O_register
);
11615 /* Get the expression constant.
11616 Calling this is illegal if expr_is_const () returns TRUE. */
11619 get_expr_register (const expressionS
*s
)
11621 assert (expr_is_register (s
));
11622 return s
->X_add_number
;
11626 /* Set the expression to a symbol + constant offset. */
11629 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11631 s
->X_op
= O_symbol
;
11632 s
->X_add_symbol
= sym
;
11633 s
->X_op_symbol
= NULL
; /* unused */
11634 s
->X_add_number
= offset
;
11638 /* Return TRUE if the two expressions are equal. */
11641 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11643 if (s1
->X_op
!= s2
->X_op
)
11645 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11647 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11649 if (s1
->X_add_number
!= s2
->X_add_number
)
11656 copy_expr (expressionS
*dst
, const expressionS
*src
)
11658 memcpy (dst
, src
, sizeof (expressionS
));
11662 /* Support for the "--rename-section" option. */
11664 struct rename_section_struct
11668 struct rename_section_struct
*next
;
11671 static struct rename_section_struct
*section_rename
;
11674 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11675 entries to the section_rename list. Note: Specifying multiple
11676 renamings separated by colons is not documented and is retained only
11677 for backward compatibility. */
11680 build_section_rename (const char *arg
)
11682 struct rename_section_struct
*r
;
11683 char *this_arg
= NULL
;
11684 char *next_arg
= NULL
;
11686 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11688 char *old_name
, *new_name
;
11692 next_arg
= strchr (this_arg
, ':');
11700 old_name
= this_arg
;
11701 new_name
= strchr (this_arg
, '=');
11703 if (*old_name
== '\0')
11705 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11708 if (!new_name
|| new_name
[1] == '\0')
11710 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11717 /* Check for invalid section renaming. */
11718 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11720 if (strcmp (r
->old_name
, old_name
) == 0)
11721 as_bad (_("section %s renamed multiple times"), old_name
);
11722 if (strcmp (r
->new_name
, new_name
) == 0)
11723 as_bad (_("multiple sections remapped to output section %s"),
11728 r
= (struct rename_section_struct
*)
11729 xmalloc (sizeof (struct rename_section_struct
));
11730 r
->old_name
= xstrdup (old_name
);
11731 r
->new_name
= xstrdup (new_name
);
11732 r
->next
= section_rename
;
11733 section_rename
= r
;
11739 xtensa_section_rename (char *name
)
11741 struct rename_section_struct
*r
= section_rename
;
11743 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11745 if (strcmp (r
->old_name
, name
) == 0)
11746 return r
->new_name
;