1 /* tc-z80.c -- Assemble code for the Zilog Z80, Z180, EZ80 and ASCII R800
2 Copyright (C) 2005-2020 Free Software Foundation, Inc.
3 Contributed by Arnold Metselaar <arnold_m@operamail.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 /* Exported constants. */
30 const char comment_chars
[] = ";\0";
31 const char line_comment_chars
[] = "#;\0";
32 const char line_separator_chars
[] = "\0";
33 const char EXP_CHARS
[] = "eE\0";
34 const char FLT_CHARS
[] = "RrDdFfSsHh\0";
36 /* For machine specific options. */
37 const char * md_shortopts
= ""; /* None yet. */
41 OPTION_MACH_Z80
= OPTION_MD_BASE
,
56 OPTION_FP_SINGLE_FORMAT
,
57 OPTION_FP_DOUBLE_FORMAT
,
58 OPTION_COMPAT_LL_PREFIX
,
59 OPTION_COMPAT_COLONLESS
,
63 #define INS_Z80 (1 << 0)
64 #define INS_R800 (1 << 1)
65 #define INS_GBZ80 (1 << 2)
66 #define INS_Z180 (1 << 3)
67 #define INS_EZ80 (1 << 4)
68 #define INS_Z80N (1 << 5)
69 #define INS_MARCH_MASK 0xffff
71 #define INS_IDX_HALF (1 << 16)
72 #define INS_IN_F_C (1 << 17)
73 #define INS_OUT_C_0 (1 << 18)
74 #define INS_SLI (1 << 19)
75 #define INS_ROT_II_LD (1 << 20) /* instructions like SLA (ii+d),r; which is: LD r,(ii+d); SLA r; LD (ii+d),r */
76 #define INS_TUNE_MASK 0xffff0000
78 #define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80 | INS_Z80N)
81 #define INS_UNDOC (INS_IDX_HALF | INS_IN_F_C)
82 #define INS_UNPORT (INS_OUT_C_0 | INS_SLI | INS_ROT_II_LD)
84 struct option md_longopts
[] =
86 { "z80", no_argument
, NULL
, OPTION_MACH_Z80
},
87 { "r800", no_argument
, NULL
, OPTION_MACH_R800
},
88 { "z180", no_argument
, NULL
, OPTION_MACH_Z180
},
89 { "ez80", no_argument
, NULL
, OPTION_MACH_EZ80_Z80
},
90 { "ez80-adl", no_argument
, NULL
, OPTION_MACH_EZ80_ADL
},
91 { "gbz80", no_argument
, NULL
, OPTION_MACH_GBZ80
},
92 { "z80n", no_argument
, NULL
, OPTION_MACH_Z80N
},
93 { "fp-s", required_argument
, NULL
, OPTION_FP_SINGLE_FORMAT
},
94 { "fp-d", required_argument
, NULL
, OPTION_FP_DOUBLE_FORMAT
},
95 { "strict", no_argument
, NULL
, OPTION_MACH_FUD
},
96 { "full", no_argument
, NULL
, OPTION_MACH_IUP
},
97 { "with-inst", required_argument
, NULL
, OPTION_MACH_INST
},
98 { "Wnins", required_argument
, NULL
, OPTION_MACH_INST
},
99 { "without-inst", required_argument
, NULL
, OPTION_MACH_NO_INST
},
100 { "local-prefix", required_argument
, NULL
, OPTION_COMPAT_LL_PREFIX
},
101 { "colonless", no_argument
, NULL
, OPTION_COMPAT_COLONLESS
},
102 { "sdcc", no_argument
, NULL
, OPTION_COMPAT_SDCC
},
103 { "Fins", required_argument
, NULL
, OPTION_MACH_NO_INST
},
104 { "ignore-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_IUD
},
105 { "Wnud", no_argument
, NULL
, OPTION_MACH_IUD
},
106 { "warn-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_WUD
},
107 { "Wud", no_argument
, NULL
, OPTION_MACH_WUD
},
108 { "forbid-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_FUD
},
109 { "Fud", no_argument
, NULL
, OPTION_MACH_FUD
},
110 { "ignore-unportable-instructions", no_argument
, NULL
, OPTION_MACH_IUP
},
111 { "Wnup", no_argument
, NULL
, OPTION_MACH_IUP
},
112 { "warn-unportable-instructions", no_argument
, NULL
, OPTION_MACH_WUP
},
113 { "Wup", no_argument
, NULL
, OPTION_MACH_WUP
},
114 { "forbid-unportable-instructions", no_argument
, NULL
, OPTION_MACH_FUP
},
115 { "Fup", no_argument
, NULL
, OPTION_MACH_FUP
},
117 { NULL
, no_argument
, NULL
, 0 }
120 size_t md_longopts_size
= sizeof (md_longopts
);
122 extern int coff_flags
;
123 /* Instruction classes that silently assembled. */
124 static int ins_ok
= INS_Z80
| INS_UNDOC
;
125 /* Instruction classes that generate errors. */
126 static int ins_err
= ~(INS_Z80
| INS_UNDOC
);
127 /* eZ80 CPU mode (ADL or Z80) */
128 static int cpu_mode
= 0; /* 0 - Z80, 1 - ADL */
129 /* accept SDCC specific instruction encoding */
130 static int sdcc_compat
= 0;
131 /* accept colonless labels */
132 static int colonless_labels
= 0;
133 /* local label prefix (NULL - default) */
134 static const char *local_label_prefix
= NULL
;
135 /* floating point support */
136 typedef const char *(*str_to_float_t
)(char *litP
, int *sizeP
);
137 static str_to_float_t str_to_float
;
138 static str_to_float_t str_to_double
;
140 /* mode of current instruction */
141 #define INST_MODE_S 0 /* short data mode */
142 #define INST_MODE_IS 0 /* short instruction mode */
143 #define INST_MODE_L 2 /* long data mode */
144 #define INST_MODE_IL 1 /* long instruction mode */
145 #define INST_MODE_FORCED 4 /* CPU mode changed by instruction suffix*/
146 static char inst_mode
;
149 setup_instruction (const char *inst
, int *add
, int *sub
)
152 if (!strcmp (inst
, "idx-reg-halves"))
154 else if (!strcmp (inst
, "sli"))
156 else if (!strcmp (inst
, "op-ii-ld"))
158 else if (!strcmp (inst
, "in-f-c"))
160 else if (!strcmp (inst
, "out-c-0"))
170 str_to_zeda32 (char *litP
, int *sizeP
);
172 str_to_float48 (char *litP
, int *sizeP
);
174 str_to_ieee754_h (char *litP
, int *sizeP
);
176 str_to_ieee754_s (char *litP
, int *sizeP
);
178 str_to_ieee754_d (char *litP
, int *sizeP
);
180 static str_to_float_t
181 get_str_to_float (const char *arg
)
183 if (strcasecmp (arg
, "zeda32") == 0)
184 return str_to_zeda32
;
186 if (strcasecmp (arg
, "math48") == 0)
187 return str_to_float48
;
189 if (strcasecmp (arg
, "half") != 0)
190 return str_to_ieee754_h
;
192 if (strcasecmp (arg
, "single") != 0)
193 return str_to_ieee754_s
;
195 if (strcasecmp (arg
, "double") != 0)
196 return str_to_ieee754_d
;
198 if (strcasecmp (arg
, "ieee754") == 0)
199 as_fatal (_("invalid floating point numbers type `%s'"), arg
);
204 setup_instruction_list (const char *list
, int *add
, int *sub
)
211 for (b
= list
; *b
!= '\0';)
218 if (sz
== 0 || sz
>= (int)sizeof (buf
))
220 as_bad (_("invalid INST in command line: %s"), b
);
225 if (setup_instruction (buf
, add
, sub
))
229 as_bad (_("invalid INST in command line: %s"), buf
);
240 md_parse_option (int c
, const char* arg
)
246 case OPTION_MACH_Z80
:
247 ins_ok
= (ins_ok
& INS_TUNE_MASK
) | INS_Z80
;
248 ins_err
= (ins_err
& INS_MARCH_MASK
) | (~INS_Z80
& INS_MARCH_MASK
);
250 case OPTION_MACH_R800
:
251 ins_ok
= INS_R800
| INS_IDX_HALF
| INS_IN_F_C
;
252 ins_err
= INS_UNPORT
;
254 case OPTION_MACH_Z180
:
256 ins_err
= INS_UNDOC
| INS_UNPORT
;
258 case OPTION_MACH_EZ80_Z80
:
259 ins_ok
= INS_EZ80
| INS_IDX_HALF
;
260 ins_err
= (INS_UNDOC
| INS_UNPORT
) & ~INS_IDX_HALF
;
263 case OPTION_MACH_EZ80_ADL
:
264 ins_ok
= INS_EZ80
| INS_IDX_HALF
;
265 ins_err
= (INS_UNDOC
| INS_UNPORT
) & ~INS_IDX_HALF
;
268 case OPTION_MACH_GBZ80
:
270 ins_err
= INS_UNDOC
| INS_UNPORT
;
272 case OPTION_MACH_Z80N
:
273 ins_ok
= INS_Z80N
| INS_UNPORT
| INS_UNDOC
;
276 case OPTION_FP_SINGLE_FORMAT
:
277 str_to_float
= get_str_to_float (arg
);
279 case OPTION_FP_DOUBLE_FORMAT
:
280 str_to_double
= get_str_to_float (arg
);
282 case OPTION_MACH_INST
:
283 if ((ins_ok
& INS_GBZ80
) == 0)
284 return setup_instruction_list (arg
, & ins_ok
, & ins_err
);
286 case OPTION_MACH_NO_INST
:
287 if ((ins_ok
& INS_GBZ80
) == 0)
288 return setup_instruction_list (arg
, & ins_err
, & ins_ok
);
290 case OPTION_MACH_WUD
:
291 case OPTION_MACH_IUD
:
292 if ((ins_ok
& INS_GBZ80
) == 0)
295 ins_err
&= ~INS_UNDOC
;
298 case OPTION_MACH_WUP
:
299 case OPTION_MACH_IUP
:
300 if ((ins_ok
& INS_GBZ80
) == 0)
302 ins_ok
|= INS_UNDOC
| INS_UNPORT
;
303 ins_err
&= ~(INS_UNDOC
| INS_UNPORT
);
306 case OPTION_MACH_FUD
:
307 if ((ins_ok
& (INS_R800
| INS_GBZ80
)) == 0)
309 ins_ok
&= (INS_UNDOC
| INS_UNPORT
);
310 ins_err
|= INS_UNDOC
| INS_UNPORT
;
313 case OPTION_MACH_FUP
:
314 ins_ok
&= ~INS_UNPORT
;
315 ins_err
|= INS_UNPORT
;
317 case OPTION_COMPAT_LL_PREFIX
:
318 local_label_prefix
= (arg
&& *arg
) ? arg
: NULL
;
320 case OPTION_COMPAT_SDCC
:
322 local_label_prefix
= "_";
324 case OPTION_COMPAT_COLONLESS
:
325 colonless_labels
= 1;
333 md_show_usage (FILE * f
)
336 CPU model options:\n\
337 -z80\t\t\t assemble for Zilog Z80\n\
338 -r800\t\t\t assemble for Ascii R800\n\
339 -z180\t\t\t assemble for Zilog Z180\n\
340 -ez80\t\t\t assemble for Zilog eZ80 in Z80 mode by default\n\
341 -ez80-adl\t\t assemble for Zilog eZ80 in ADL mode by default\n\
342 -gbz80\t\t assemble for GameBoy Z80\n\
343 -z80n\t\t\t assemble for Z80N\n\
345 Compatibility options:\n\
346 -local-prefix=TEXT\t treat labels prefixed by TEXT as local\n\
347 -colonless\t\t permit colonless labels\n\
348 -sdcc\t\t\t accept SDCC specific instruction syntax\n\
349 -fp-s=FORMAT\t\t set single precission FP numbers format\n\
350 -fp-d=FORMAT\t\t set double precission FP numbers format\n\
351 Where FORMAT one of:\n\
352 ieee754\t\t IEEE754 compatible\n\
353 half\t\t\t IEEE754 half precision (16 bit)\n\
354 single\t\t IEEE754 single precision (32 bit)\n\
355 double\t\t IEEE754 double precision (64 bit)\n\
356 zeda32\t\t Zeda z80float library 32 bit format\n\
357 math48\t\t 48 bit format from Math48 library\n\
359 Support for known undocumented instructions:\n\
360 -strict\t\t assemble only documented instructions\n\
361 -full\t\t\t assemble all undocumented instructions\n\
362 -with-inst=INST[,...]\n\
363 -Wnins INST[,...]\t assemble specified instruction(s)\n\
364 -without-inst=INST[,...]\n\
365 -Fins INST[,...]\t do not assemble specified instruction(s)\n\
366 Where INST is one of:\n\
367 idx-reg-halves\t instructions with halves of index registers\n\
368 sli\t\t\t instruction SLI/SLL\n\
369 op-ii-ld\t\t instructions like SLA (II+dd),R (opcodes DD/FD CB dd xx)\n\
370 in-f-c\t\t instruction IN F,(C)\n\
371 out-c-0\t\t instruction OUT (C),0\n\
374 -ignore-undocumented-instructions\n\
375 -Wnud\t\t\t silently assemble undocumented Z80-instructions that work on R800\n\
376 -ignore-unportable-instructions\n\
377 -Wnup\t\t\t silently assemble all undocumented Z80-instructions\n\
378 -warn-undocumented-instructions\n\
379 -Wud\t\t\t issue warnings for undocumented Z80-instructions that work on R800\n\
380 -warn-unportable-instructions\n\
381 -Wup\t\t\t issue warnings for other undocumented Z80-instructions\n\
382 -forbid-undocumented-instructions\n\
383 -Fud\t\t\t treat all undocumented Z80-instructions as errors\n\
384 -forbid-unportable-instructions\n\
385 -Fup\t\t\t treat undocumented Z80-instructions that do not work on R800 as errors\n\
387 Default: -z80 -ignore-undocumented-instructions -warn-unportable-instructions.\n");
390 static symbolS
* zero
;
397 #define R_STACKABLE (0x80)
398 #define R_ARITH (0x40)
401 #define R_INDEX (R_IX | R_IY)
410 #define REG_F (6 | 8)
415 #define REG_AF (3 | R_STACKABLE)
416 #define REG_BC (0 | R_STACKABLE | R_ARITH)
417 #define REG_DE (1 | R_STACKABLE | R_ARITH)
418 #define REG_HL (2 | R_STACKABLE | R_ARITH)
419 #define REG_IX (REG_HL | R_IX)
420 #define REG_IY (REG_HL | R_IY)
421 #define REG_SP (3 | R_ARITH)
423 static const struct reg_entry regtable
[] =
438 {"ixh",REG_H
| R_IX
},
439 {"ixl",REG_L
| R_IX
},
441 {"iyh",REG_H
| R_IY
},
442 {"iyl",REG_L
| R_IY
},
449 #define BUFLEN 8 /* Large enough for any keyword. */
454 expressionS nul
, reg
;
456 unsigned int i
, j
, k
;
459 if (ins_ok
& INS_EZ80
) /* if select EZ80 cpu then */
460 listing_lhs_width
= 6; /* use 6 bytes per line in the listing */
462 reg
.X_op
= O_register
;
464 reg
.X_add_symbol
= reg
.X_op_symbol
= 0;
465 for ( i
= 0 ; i
< ARRAY_SIZE ( regtable
) ; ++i
)
467 reg
.X_add_number
= regtable
[i
].number
;
468 k
= strlen ( regtable
[i
].name
);
472 for ( j
= ( 1<<k
) ; j
; --j
)
474 for ( k
= 0 ; regtable
[i
].name
[k
] ; ++k
)
476 buf
[k
] = ( j
& ( 1<<k
) ) ? TOUPPER (regtable
[i
].name
[k
]) : regtable
[i
].name
[k
];
478 symbolS
* psym
= symbol_find_or_make (buf
);
479 S_SET_SEGMENT (psym
, reg_section
);
480 symbol_set_value_expression (psym
, ®
);
484 p
= input_line_pointer
;
485 input_line_pointer
= (char *) "0";
488 input_line_pointer
= p
;
489 zero
= make_expr_symbol (& nul
);
490 /* We do not use relaxation (yet). */
499 switch (ins_ok
& INS_MARCH_MASK
)
502 if (ins_ok
& INS_UNPORT
)
503 mach_type
= bfd_mach_z80full
;
504 else if (ins_ok
& INS_UNDOC
)
505 mach_type
= bfd_mach_z80
;
507 mach_type
= bfd_mach_z80strict
;
510 mach_type
= bfd_mach_r800
;
513 mach_type
= bfd_mach_z180
;
516 mach_type
= bfd_mach_gbz80
;
519 mach_type
= cpu_mode
? bfd_mach_ez80_adl
: bfd_mach_ez80_z80
;
522 mach_type
= bfd_mach_z80n
;
528 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach_type
);
531 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533 z80_elf_final_processing (void)
536 switch (ins_ok
& INS_MARCH_MASK
)
539 elf_flags
= EF_Z80_MACH_Z80
;
542 elf_flags
= EF_Z80_MACH_R800
;
545 elf_flags
= EF_Z80_MACH_Z180
;
548 elf_flags
= EF_Z80_MACH_GBZ80
;
551 elf_flags
= cpu_mode
? EF_Z80_MACH_EZ80_ADL
: EF_Z80_MACH_EZ80_Z80
;
554 elf_flags
= EF_Z80_MACH_Z80N
;
560 elf_elfheader (stdoutput
)->e_flags
= elf_flags
;
565 skip_space (const char *s
)
567 while (*s
== ' ' || *s
== '\t')
572 /* A non-zero return-value causes a continue in the
573 function read_a_source_file () in ../read.c. */
575 z80_start_line_hook (void)
580 /* Convert one character constants. */
581 for (p
= input_line_pointer
; *p
&& *p
!= '\n'; ++p
)
586 if (p
[1] != 0 && p
[1] != '\'' && p
[2] == '\'')
588 snprintf (buf
, 4, "%3d", (unsigned char)p
[1]);
596 for (quote
= *p
++; quote
!= *p
&& '\n' != *p
; ++p
)
600 as_bad (_("-- unterminated string"));
601 ignore_rest_of_line ();
607 *p
= (*skip_space (p
+ 1) == '(') ? '+' : ' ';
611 /* Check for <label>[:] [.](EQU|DEFL) <value>. */
612 if (is_name_beginner (*input_line_pointer
))
615 char c
, *rest
, *line_start
;
618 line_start
= input_line_pointer
;
622 c
= get_symbol_name (&name
);
623 rest
= input_line_pointer
+ 1;
625 if (ISSPACE (c
) && colonless_labels
)
629 bump_line_counters ();
634 if (c
== ':' && sdcc_compat
&& rest
[-2] != '$')
635 dollar_label_clear ();
638 /* remove second colon if SDCC compatibility enabled */
643 rest
= (char*)skip_space (rest
);
646 if (strncasecmp (rest
, "EQU", 3) == 0)
648 else if (strncasecmp (rest
, "DEFL", 4) == 0)
652 if (len
&& (!ISALPHA (rest
[len
])))
654 /* Handle assignment here. */
655 if (line_start
[-1] == '\n')
657 bump_line_counters ();
660 input_line_pointer
= rest
+ len
- 1;
661 /* Allow redefining with "DEFL" (len == 4), but not with "EQU". */
662 equals (name
, len
== 4);
667 /* Restore line and pointer. */
668 (void) restore_line_pointer (c
);
669 input_line_pointer
= line_start
;
676 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
682 md_atof (int type
, char *litP
, int *sizeP
)
691 return str_to_float (litP
, sizeP
);
698 return str_to_double (litP
, sizeP
);
701 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
705 md_section_align (segT seg ATTRIBUTE_UNUSED
, valueT size
)
711 md_pcrel_from (fixS
* fixp
)
713 return fixp
->fx_where
+ fixp
->fx_frag
->fr_address
;
716 typedef const char * (asfunc
)(char, char, const char*);
718 typedef struct _table_t
721 unsigned char prefix
;
722 unsigned char opcode
;
724 unsigned inss
; /*0 - all CPU types or list of supported INS_* */
727 /* Compares the key for structs that start with a char * to the key. */
729 key_cmp (const void * a
, const void * b
)
731 const char *str_a
, *str_b
;
733 str_a
= *((const char**)a
);
734 str_b
= *((const char**)b
);
735 return strcmp (str_a
, str_b
);
739 const char *key
= buf
;
741 /* Prevent an error on a line from also generating
742 a "junk at end of line" error message. */
743 static char err_flag
;
746 error (const char * message
)
751 as_bad ("%s", message
);
758 error (_("illegal operand"));
762 wrong_mach (int ins_type
)
764 if (ins_type
& ins_err
)
767 as_warn (_("undocumented instruction"));
771 check_mach (int ins_type
)
773 if ((ins_type
& ins_ok
) == 0)
774 wrong_mach (ins_type
);
777 /* Check whether an expression is indirect. */
779 is_indir (const char *s
)
785 /* Indirection is indicated with parentheses. */
788 for (p
= s
, depth
= 0; *p
&& *p
!= ','; ++p
)
794 for (quote
= *p
++; quote
!= *p
&& *p
!= '\n'; ++p
)
795 if (*p
== '\\' && p
[1])
805 p
= skip_space (p
+ 1);
811 error (_("mismatched parentheses"));
817 error (_("mismatched parentheses"));
822 /* Check whether a symbol involves a register. */
824 contains_register (symbolS
*sym
)
828 expressionS
* ex
= symbol_get_value_expression(sym
);
830 return (O_register
== ex
->X_op
)
831 || (ex
->X_add_symbol
&& contains_register(ex
->X_add_symbol
))
832 || (ex
->X_op_symbol
&& contains_register(ex
->X_op_symbol
));
838 /* Parse general expression, not looking for indexed addressing. */
840 parse_exp_not_indexed (const char *s
, expressionS
*op
)
847 if (sdcc_compat
&& (*p
== '<' || *p
== '>'))
851 case '<': /* LSB request */
854 case '>': /* MSB request */
855 make_shift
= cpu_mode
? 16 : 8;
862 op
->X_md
= indir
= is_indir (p
);
863 if (indir
&& (ins_ok
& INS_GBZ80
))
864 { /* check for instructions like ld a,(hl+), ld (hl-),a */
865 p
= skip_space (p
+1);
866 if (!strncasecmp (p
, "hl", 2))
869 if (*skip_space(p
+1) == ')' && (*p
== '+' || *p
== '-'))
872 op
->X_add_symbol
= NULL
;
873 op
->X_add_number
= (*p
== '+') ? REG_HL
: -REG_HL
;
874 input_line_pointer
= (char*)skip_space(p
+ 1) + 1;
875 return input_line_pointer
;
879 input_line_pointer
= (char*) s
;
884 error (_("missing operand"));
887 error (_("bad expression syntax"));
895 /* replace [op] by [op >> shift] */
897 op
->X_add_symbol
= make_expr_symbol (op
);
898 op
->X_add_number
= 0;
899 op
->X_op
= O_right_shift
;
900 memset (&data
, 0, sizeof (data
));
901 data
.X_op
= O_constant
;
902 data
.X_add_number
= make_shift
;
903 op
->X_op_symbol
= make_expr_symbol (&data
);
905 return input_line_pointer
;
909 unify_indexed (expressionS
*op
)
911 if (O_register
!= symbol_get_value_expression (op
->X_add_symbol
)->X_op
)
914 int rnum
= symbol_get_value_expression (op
->X_add_symbol
)->X_add_number
;
915 if ( ((REG_IX
!= rnum
) && (REG_IY
!= rnum
)) || contains_register (op
->X_op_symbol
))
921 /* Convert subtraction to addition of negative value. */
922 if (O_subtract
== op
->X_op
)
925 minus
.X_op
= O_uminus
;
926 minus
.X_add_number
= 0;
927 minus
.X_add_symbol
= op
->X_op_symbol
;
928 minus
.X_op_symbol
= 0;
929 op
->X_op_symbol
= make_expr_symbol (&minus
);
933 /* Clear X_add_number of the expression. */
934 if (op
->X_add_number
!= 0)
937 memset (&add
, 0, sizeof (add
));
939 add
.X_add_number
= op
->X_add_number
;
940 add
.X_add_symbol
= op
->X_op_symbol
;
942 op
->X_add_symbol
= make_expr_symbol (&add
);
945 op
->X_add_symbol
= op
->X_op_symbol
;
947 op
->X_add_number
= rnum
;
952 /* Parse expression, change operator to O_md1 for indexed addressing. */
954 parse_exp (const char *s
, expressionS
*op
)
956 const char* res
= parse_exp_not_indexed (s
, op
);
961 if (unify_indexed (op
) && op
->X_md
)
965 if (op
->X_md
&& ((REG_IX
== op
->X_add_number
) || (REG_IY
== op
->X_add_number
)))
967 op
->X_add_symbol
= zero
;
972 /* parse SDCC syntax where index register offset placed before parentheses */
973 if (sdcc_compat
&& is_indir (res
))
977 res
= parse_exp (res
, op
);
978 if (op
->X_op
!= O_md1
|| op
->X_add_symbol
!= zero
)
981 op
->X_add_symbol
= make_expr_symbol (&off
);
990 /* Condition codes, including some synonyms provided by HiTech zas. */
991 static const struct reg_entry cc_tab
[] =
1009 /* Parse condition code. */
1011 parse_cc (const char *s
, char * op
)
1015 struct reg_entry
* cc_p
;
1017 for (i
= 0; i
< BUFLEN
; ++i
)
1019 if (!ISALPHA (s
[i
])) /* Condition codes consist of letters only. */
1021 buf
[i
] = TOLOWER (s
[i
]);
1025 && ((s
[i
] == 0) || (s
[i
] == ',')))
1028 cc_p
= bsearch (&key
, cc_tab
, ARRAY_SIZE (cc_tab
),
1029 sizeof (cc_tab
[0]), key_cmp
);
1046 emit_insn (char prefix
, char opcode
, const char * args
)
1061 void z80_cons_fix_new (fragS
*frag_p
, int offset
, int nbytes
, expressionS
*exp
)
1063 bfd_reloc_code_real_type r
[4] =
1071 if (nbytes
< 1 || nbytes
> 4)
1073 as_bad (_("unsupported BFD relocation size %u"), nbytes
);
1077 fix_new_exp (frag_p
, offset
, nbytes
, exp
, 0, r
[nbytes
-1]);
1082 emit_data_val (expressionS
* val
, int size
)
1085 bfd_reloc_code_real_type r_type
;
1087 p
= frag_more (size
);
1088 if (val
->X_op
== O_constant
)
1091 for (i
= 0; i
< size
; ++i
)
1092 p
[i
] = (char)(val
->X_add_number
>> (i
*8));
1098 case 1: r_type
= BFD_RELOC_8
; break;
1099 case 2: r_type
= BFD_RELOC_16
; break;
1100 case 3: r_type
= BFD_RELOC_24
; break;
1101 case 4: r_type
= BFD_RELOC_32
; break;
1102 case 8: r_type
= BFD_RELOC_64
; break;
1104 as_fatal (_("invalid data size %d"), size
);
1107 if ( (val
->X_op
== O_register
)
1108 || (val
->X_op
== O_md1
)
1109 || contains_register (val
->X_add_symbol
)
1110 || contains_register (val
->X_op_symbol
))
1113 if (size
<= 2 && val
->X_op_symbol
)
1115 bfd_boolean simplify
= TRUE
;
1116 int shift
= symbol_get_value_expression (val
->X_op_symbol
)->X_add_number
;
1117 if (val
->X_op
== O_bit_and
&& shift
== (1 << (size
*8))-1)
1119 else if (val
->X_op
!= O_right_shift
)
1126 case 0: r_type
= BFD_RELOC_Z80_BYTE0
; break;
1127 case 8: r_type
= BFD_RELOC_Z80_BYTE1
; break;
1128 case 16: r_type
= BFD_RELOC_Z80_BYTE2
; break;
1129 case 24: r_type
= BFD_RELOC_Z80_BYTE3
; break;
1130 default: simplify
= FALSE
;
1133 else /* if (size == 2) */
1137 case 0: r_type
= BFD_RELOC_Z80_WORD0
; break;
1138 case 16: r_type
= BFD_RELOC_Z80_WORD1
; break;
1139 default: simplify
= FALSE
;
1145 val
->X_op
= O_symbol
;
1146 val
->X_op_symbol
= NULL
;
1147 val
->X_add_number
= 0;
1151 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
, val
, FALSE
, r_type
);
1155 emit_byte (expressionS
* val
, bfd_reloc_code_real_type r_type
)
1159 if (r_type
== BFD_RELOC_8
)
1161 emit_data_val (val
, 1);
1165 *p
= val
->X_add_number
;
1166 if ( contains_register (val
->X_add_symbol
) || contains_register (val
->X_op_symbol
) )
1170 else if ((r_type
== BFD_RELOC_8_PCREL
) && (val
->X_op
== O_constant
))
1172 as_bad (_("cannot make a relative jump to an absolute location"));
1174 else if (val
->X_op
== O_constant
)
1176 if ((val
->X_add_number
< -128) || (val
->X_add_number
>= 128))
1178 if (r_type
== BFD_RELOC_Z80_DISP8
)
1179 as_bad (_("index overflow (%+ld)"), val
->X_add_number
);
1181 as_bad (_("offset overflow (%+ld)"), val
->X_add_number
);
1186 /* For symbols only, constants are stored at begin of function */
1187 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 1, val
,
1188 (r_type
== BFD_RELOC_8_PCREL
) ? TRUE
: FALSE
, r_type
);
1193 emit_word (expressionS
* val
)
1195 emit_data_val (val
, (inst_mode
& INST_MODE_IL
) ? 3 : 2);
1199 emit_mx (char prefix
, char opcode
, int shift
, expressionS
* arg
)
1200 /* The operand m may be r, (hl), (ix+d), (iy+d),
1201 if 0 == prefix m may also be ixl, ixh, iyl, iyh. */
1206 rnum
= arg
->X_add_number
;
1222 if ((prefix
== 0) && (rnum
& R_INDEX
))
1224 prefix
= (rnum
& R_IX
) ? 0xDD : 0xFD;
1225 if (!(ins_ok
& INS_EZ80
))
1226 check_mach (INS_IDX_HALF
);
1235 q
= frag_more (prefix
? 2 : 1);
1238 * q
++ = opcode
+ (rnum
<< shift
);
1241 if (ins_ok
& INS_GBZ80
)
1247 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1248 *q
= (prefix
) ? prefix
: (opcode
+ (6 << shift
));
1250 expressionS offset
= *arg
;
1251 offset
.X_op
= O_symbol
;
1252 offset
.X_add_number
= 0;
1253 emit_byte (&offset
, BFD_RELOC_Z80_DISP8
);
1258 *q
= opcode
+(6<<shift
);
1266 /* The operand m may be r, (hl), (ix+d), (iy+d),
1267 if 0 = prefix m may also be ixl, ixh, iyl, iyh. */
1269 emit_m (char prefix
, char opcode
, const char *args
)
1274 p
= parse_exp (args
, &arg_m
);
1279 emit_mx (prefix
, opcode
, 0, &arg_m
);
1287 /* The operand m may be as above or one of the undocumented
1288 combinations (ix+d),r and (iy+d),r (if unportable instructions
1292 emit_mr (char prefix
, char opcode
, const char *args
)
1294 expressionS arg_m
, arg_r
;
1297 p
= parse_exp (args
, & arg_m
);
1304 p
= parse_exp (p
+ 1, & arg_r
);
1306 if ((arg_r
.X_md
== 0)
1307 && (arg_r
.X_op
== O_register
)
1308 && (arg_r
.X_add_number
< 8))
1309 opcode
+= arg_r
.X_add_number
- 6; /* Emit_mx () will add 6. */
1315 check_mach (INS_ROT_II_LD
);
1319 emit_mx (prefix
, opcode
, 0, & arg_m
);
1328 emit_sx (char prefix
, char opcode
, expressionS
* arg_p
)
1332 switch (arg_p
->X_op
)
1336 emit_mx (prefix
, opcode
, 0, arg_p
);
1343 q
= frag_more (prefix
? 2 : 1);
1347 emit_byte (arg_p
, BFD_RELOC_8
);
1352 /* The operand s may be r, (hl), (ix+d), (iy+d), n. */
1354 emit_s (char prefix
, char opcode
, const char *args
)
1359 p
= parse_exp (args
, & arg_s
);
1360 if (*p
== ',' && arg_s
.X_md
== 0 && arg_s
.X_op
== O_register
&& arg_s
.X_add_number
== REG_A
)
1361 { /* possible instruction in generic format op A,x */
1362 if (!(ins_ok
& INS_EZ80
) && !sdcc_compat
)
1365 p
= parse_exp (p
, & arg_s
);
1367 emit_sx (prefix
, opcode
, & arg_s
);
1372 emit_sub (char prefix
, char opcode
, const char *args
)
1377 if (!(ins_ok
& INS_GBZ80
))
1378 return emit_s (prefix
, opcode
, args
);
1379 p
= parse_exp (args
, & arg_s
);
1382 error (_("bad instruction syntax"));
1386 if (arg_s
.X_md
!= 0 || arg_s
.X_op
!= O_register
|| arg_s
.X_add_number
!= REG_A
)
1389 p
= parse_exp (p
, & arg_s
);
1391 emit_sx (prefix
, opcode
, & arg_s
);
1396 emit_swap (char prefix
, char opcode
, const char *args
)
1402 if (!(ins_ok
& INS_Z80N
))
1403 return emit_mr (prefix
, opcode
, args
);
1405 /* check for alias swap a for swapnib of Z80N */
1406 p
= parse_exp (args
, ®
);
1407 if (reg
.X_md
!= 0 || reg
.X_op
!= O_register
|| reg
.X_add_number
!= REG_A
)
1417 emit_call (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1420 const char *p
; char *q
;
1422 p
= parse_exp_not_indexed (args
, &addr
);
1434 /* Operand may be rr, r, (hl), (ix+d), (iy+d). */
1436 emit_incdec (char prefix
, char opcode
, const char * args
)
1438 expressionS operand
;
1440 const char *p
; char *q
;
1442 p
= parse_exp (args
, &operand
);
1443 rnum
= operand
.X_add_number
;
1444 if ((! operand
.X_md
)
1445 && (operand
.X_op
== O_register
)
1448 q
= frag_more ((rnum
& R_INDEX
) ? 2 : 1);
1450 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1451 *q
= prefix
+ ((rnum
& 3) << 4);
1455 if ((operand
.X_op
== O_md1
) || (operand
.X_op
== O_register
))
1456 emit_mx (0, opcode
, 3, & operand
);
1464 emit_jr (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1470 p
= parse_exp_not_indexed (args
, &addr
);
1477 addr
.X_add_number
--; /* pcrel computes after offset code */
1478 emit_byte (&addr
, BFD_RELOC_8_PCREL
);
1484 emit_jp (char prefix
, char opcode
, const char * args
)
1491 p
= parse_exp_not_indexed (args
, & addr
);
1494 rnum
= addr
.X_add_number
;
1495 if ((O_register
== addr
.X_op
) && (REG_HL
== (rnum
& ~R_INDEX
)))
1497 q
= frag_more ((rnum
& R_INDEX
) ? 2 : 1);
1499 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1502 else if (addr
.X_op
== O_register
&& rnum
== REG_C
&& (ins_ok
& INS_Z80N
))
1521 emit_im (char prefix
, char opcode
, const char * args
)
1527 p
= parse_exp (args
, & mode
);
1528 if (mode
.X_md
|| (mode
.X_op
!= O_constant
))
1531 switch (mode
.X_add_number
)
1535 ++mode
.X_add_number
;
1540 *q
= opcode
+ 8*mode
.X_add_number
;
1549 emit_pop (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1555 p
= parse_exp (args
, & regp
);
1557 && (regp
.X_op
== O_register
)
1558 && (regp
.X_add_number
& R_STACKABLE
))
1562 rnum
= regp
.X_add_number
;
1566 *q
++ = (rnum
&R_IX
)?0xDD:0xFD;
1570 *q
= opcode
+ ((rnum
& 3) << 4);
1579 emit_push (char prefix
, char opcode
, const char * args
)
1585 p
= parse_exp (args
, & arg
);
1586 if (arg
.X_op
== O_register
)
1587 return emit_pop (prefix
, opcode
, args
);
1589 if (arg
.X_md
|| arg
.X_op
== O_md1
|| !(ins_ok
& INS_Z80N
))
1597 fix_new_exp (frag_now
, q
- frag_now
->fr_literal
, 2, &arg
, FALSE
,
1598 BFD_RELOC_Z80_16_BE
);
1604 emit_retcc (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1609 p
= parse_cc (args
, &cc
);
1615 return p
? p
: args
;
1619 emit_adc (char prefix
, char opcode
, const char * args
)
1626 p
= parse_exp (args
, &term
);
1629 error (_("bad instruction syntax"));
1633 if ((term
.X_md
) || (term
.X_op
!= O_register
))
1636 switch (term
.X_add_number
)
1639 p
= emit_s (0, prefix
, p
);
1642 p
= parse_exp (p
, &term
);
1643 if ((!term
.X_md
) && (term
.X_op
== O_register
))
1645 rnum
= term
.X_add_number
;
1646 if (R_ARITH
== (rnum
& (R_ARITH
| R_INDEX
)))
1650 *q
= opcode
+ ((rnum
& 3) << 4);
1662 emit_add (char prefix
, char opcode
, const char * args
)
1669 p
= parse_exp (args
, &term
);
1672 error (_("bad instruction syntax"));
1676 if ((term
.X_md
) || (term
.X_op
!= O_register
))
1679 switch (term
.X_add_number
)
1682 p
= emit_s (0, prefix
, p
);
1685 p
= parse_exp (p
, &term
);
1686 if (!(ins_ok
& INS_GBZ80
) || term
.X_md
|| term
.X_op
== O_register
)
1690 emit_byte (&term
, BFD_RELOC_Z80_DISP8
);
1694 if (!(ins_ok
& INS_Z80N
))
1703 lhs
= term
.X_add_number
;
1704 p
= parse_exp (p
, &term
);
1705 rhs
= term
.X_add_number
;
1706 if (term
.X_md
!= 0 || term
.X_op
== O_md1
)
1708 else if ((term
.X_op
== O_register
) && (rhs
& R_ARITH
) && (rhs
== lhs
|| (rhs
& ~R_INDEX
) != REG_HL
))
1712 q
= frag_more ((lhs
& R_INDEX
) ? 2 : 1);
1714 *q
++ = (lhs
& R_IX
) ? 0xDD : 0xFD;
1715 *q
= opcode
+ ((rhs
& 3) << 4);
1719 else if (!(lhs
& R_INDEX
) && (ins_ok
& INS_Z80N
))
1721 if (term
.X_op
== O_register
&& rhs
== REG_A
)
1722 { /* ADD BC/DE/HL,A */
1725 *q
= 0x33 - (lhs
& 3);
1728 else if (term
.X_op
!= O_register
&& term
.X_op
!= O_md1
)
1729 { /* ADD BC/DE/HL,nn */
1732 *q
= 0x36 - (lhs
& 3);
1745 emit_bit (char prefix
, char opcode
, const char * args
)
1751 p
= parse_exp (args
, &b
);
1753 error (_("bad instruction syntax"));
1755 bn
= b
.X_add_number
;
1757 && (b
.X_op
== O_constant
)
1762 /* Bit : no optional third operand. */
1763 p
= emit_m (prefix
, opcode
+ (bn
<< 3), p
);
1765 /* Set, res : resulting byte can be copied to register. */
1766 p
= emit_mr (prefix
, opcode
+ (bn
<< 3), p
);
1773 /* BSLA DE,B; BSRA DE,B; BSRL DE,B; BSRF DE,B; BRLC DE,B (Z80N only) */
1775 emit_bshft (char prefix
, char opcode
, const char * args
)
1781 p
= parse_exp (args
, & r1
);
1783 error (_("bad instruction syntax"));
1784 p
= parse_exp (p
, & r2
);
1785 if (r1
.X_md
|| r1
.X_op
!= O_register
|| r1
.X_add_number
!= REG_DE
||
1786 r2
.X_md
|| r2
.X_op
!= O_register
|| r2
.X_add_number
!= REG_B
)
1795 emit_jpcc (char prefix
, char opcode
, const char * args
)
1800 p
= parse_cc (args
, & cc
);
1801 if (p
&& *p
++ == ',')
1802 p
= emit_call (0, opcode
+ cc
, p
);
1804 p
= (prefix
== (char)0xC3)
1805 ? emit_jp (0xE9, prefix
, args
)
1806 : emit_call (0, prefix
, args
);
1811 emit_jrcc (char prefix
, char opcode
, const char * args
)
1816 p
= parse_cc (args
, &cc
);
1817 if (p
&& *p
++ == ',')
1820 error (_("condition code invalid for jr"));
1822 p
= emit_jr (0, opcode
+ cc
, p
);
1825 p
= emit_jr (0, prefix
, args
);
1831 emit_ex (char prefix_in ATTRIBUTE_UNUSED
,
1832 char opcode_in ATTRIBUTE_UNUSED
, const char * args
)
1836 char prefix
, opcode
;
1838 p
= parse_exp_not_indexed (args
, &op
);
1842 error (_("bad instruction syntax"));
1846 prefix
= opcode
= 0;
1847 if (op
.X_op
== O_register
)
1848 switch (op
.X_add_number
| (op
.X_md
? 0x8000 : 0))
1851 if (TOLOWER (*p
++) == 'a' && TOLOWER (*p
++) == 'f')
1853 /* The scrubber changes '\'' to '`' in this context. */
1860 if (TOLOWER (*p
++) == 'h' && TOLOWER (*p
++) == 'l')
1864 p
= parse_exp (p
, & op
);
1865 if (op
.X_op
== O_register
1867 && (op
.X_add_number
& ~R_INDEX
) == REG_HL
)
1870 if (R_INDEX
& op
.X_add_number
)
1871 prefix
= (R_IX
& op
.X_add_number
) ? 0xDD : 0xFD;
1876 emit_insn (prefix
, opcode
, p
);
1884 emit_in (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1887 expressionS reg
, port
;
1891 p
= parse_exp (args
, ®
);
1892 if (reg
.X_md
&& reg
.X_op
== O_register
&& reg
.X_add_number
== REG_C
)
1893 { /* permit instruction in (c) as alias for in f,(c) */
1896 reg
.X_add_number
= REG_F
;
1902 error (_("bad instruction syntax"));
1905 p
= parse_exp (p
, &port
);
1908 && reg
.X_op
== O_register
1909 && (reg
.X_add_number
<= 7 || reg
.X_add_number
== REG_F
)
1912 if (port
.X_op
!= O_md1
&& port
.X_op
!= O_register
)
1914 if (REG_A
== reg
.X_add_number
)
1918 emit_byte (&port
, BFD_RELOC_8
);
1925 if (port
.X_add_number
== REG_C
|| port
.X_add_number
== REG_BC
)
1927 if (port
.X_add_number
== REG_BC
&& !(ins_ok
& INS_EZ80
))
1929 else if (reg
.X_add_number
== REG_F
&& !(ins_ok
& INS_R800
))
1930 check_mach (INS_IN_F_C
);
1933 *q
= 0x40|((reg
.X_add_number
&7)<<3);
1945 emit_in0 (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1948 expressionS reg
, port
;
1952 p
= parse_exp (args
, ®
);
1955 error (_("bad instruction syntax"));
1959 p
= parse_exp (p
, &port
);
1961 && reg
.X_op
== O_register
1962 && reg
.X_add_number
<= 7
1964 && port
.X_op
!= O_md1
1965 && port
.X_op
!= O_register
)
1969 *q
= 0x00|(reg
.X_add_number
<< 3);
1970 emit_byte (&port
, BFD_RELOC_8
);
1978 emit_out (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1981 expressionS reg
, port
;
1985 p
= parse_exp (args
, & port
);
1988 error (_("bad instruction syntax"));
1991 p
= parse_exp (p
, ®
);
1993 { ill_op (); return p
; }
1994 /* Allow "out (c), 0" as unportable instruction. */
1995 if (reg
.X_op
== O_constant
&& reg
.X_add_number
== 0)
1997 check_mach (INS_OUT_C_0
);
1998 reg
.X_op
= O_register
;
1999 reg
.X_add_number
= 6;
2002 || reg
.X_op
!= O_register
2003 || reg
.X_add_number
> 7)
2006 if (port
.X_op
!= O_register
&& port
.X_op
!= O_md1
)
2008 if (REG_A
== reg
.X_add_number
)
2012 emit_byte (&port
, BFD_RELOC_8
);
2019 if (REG_C
== port
.X_add_number
|| port
.X_add_number
== REG_BC
)
2021 if (port
.X_add_number
== REG_BC
&& !(ins_ok
& INS_EZ80
))
2025 *q
= 0x41 | (reg
.X_add_number
<< 3);
2034 emit_out0 (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2037 expressionS reg
, port
;
2041 p
= parse_exp (args
, & port
);
2044 error (_("bad instruction syntax"));
2047 p
= parse_exp (p
, ®
);
2049 && port
.X_op
!= O_register
2050 && port
.X_op
!= O_md1
2052 && reg
.X_op
== O_register
2053 && reg
.X_add_number
<= 7)
2057 *q
= 0x01 | (reg
.X_add_number
<< 3);
2058 emit_byte (&port
, BFD_RELOC_8
);
2066 emit_rst (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
2072 p
= parse_exp_not_indexed (args
, &addr
);
2073 if (addr
.X_op
!= O_constant
)
2075 error ("rst needs constant address");
2079 if (addr
.X_add_number
& ~(7 << 3))
2084 *q
= opcode
+ (addr
.X_add_number
& (7 << 3));
2089 /* For 8-bit indirect load to memory instructions like: LD (HL),n or LD (ii+d),n. */
2091 emit_ld_m_n (expressionS
*dst
, expressionS
*src
)
2095 expressionS dst_offset
;
2097 switch (dst
->X_add_number
)
2099 case REG_HL
: prefix
= 0x00; break;
2100 case REG_IX
: prefix
= 0xDD; break;
2101 case REG_IY
: prefix
= 0xFD; break;
2107 q
= frag_more (prefix
? 2 : 1);
2114 dst_offset
.X_op
= O_symbol
;
2115 dst_offset
.X_add_number
= 0;
2116 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2118 emit_byte (src
, BFD_RELOC_8
);
2121 /* For 8-bit load register to memory instructions: LD (<expression>),r. */
2123 emit_ld_m_r (expressionS
*dst
, expressionS
*src
)
2127 expressionS dst_offset
;
2132 if (ins_ok
& INS_GBZ80
)
2133 { /* LD (HL+),A or LD (HL-),A */
2134 if (src
->X_op
!= O_register
|| src
->X_add_number
!= REG_A
)
2136 *frag_more (1) = (dst
->X_add_number
== REG_HL
) ? 0x22 : 0x32;
2140 prefix
= (dst
->X_add_number
== REG_IX
) ? 0xDD : 0xFD;
2143 switch (dst
->X_add_number
)
2145 case REG_BC
: /* LD (BC),A */
2146 case REG_DE
: /* LD (DE),A */
2147 if (src
->X_add_number
== REG_A
)
2150 *q
= 0x02 | ((dst
->X_add_number
& 3) << 4);
2156 case REG_HL
: /* LD (HL),r or LD (ii+d),r */
2157 if (src
->X_add_number
<= 7)
2159 q
= frag_more (prefix
? 2 : 1);
2162 *q
= 0x70 | src
->X_add_number
;
2166 dst_offset
.X_op
= O_symbol
;
2167 dst_offset
.X_add_number
= 0;
2168 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2176 default: /* LD (nn),A */
2177 if (src
->X_add_number
== REG_A
)
2180 *q
= (ins_ok
& INS_GBZ80
) ? 0xEA : 0x32;
2189 /* For 16-bit load register to memory instructions: LD (<expression>),rr. */
2191 emit_ld_m_rr (expressionS
*dst
, expressionS
*src
)
2196 expressionS dst_offset
;
2200 case O_md1
: /* eZ80 instructions LD (ii+d),rr */
2201 case O_register
: /* eZ80 instructions LD (HL),rr */
2202 if (!(ins_ok
& INS_EZ80
)) /* 16-bit indirect load group is supported by eZ80 only */
2204 switch (dst
->X_add_number
)
2206 case REG_IX
: prefix
= 0xDD; break;
2207 case REG_IY
: prefix
= 0xFD; break;
2208 case REG_HL
: prefix
= 0xED; break;
2212 switch (src
->X_add_number
)
2214 case REG_BC
: opcode
= 0x0F; break;
2215 case REG_DE
: opcode
= 0x1F; break;
2216 case REG_HL
: opcode
= 0x2F; break;
2217 case REG_IX
: opcode
= (prefix
!= 0xFD) ? 0x3F : 0x3E; break;
2218 case REG_IY
: opcode
= (prefix
!= 0xFD) ? 0x3E : 0x3F; break;
2222 q
= frag_more (prefix
? 2 : 1);
2225 if (prefix
== 0xFD || prefix
== 0xDD)
2228 dst_offset
.X_op
= O_symbol
;
2229 dst_offset
.X_add_number
= 0;
2230 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2233 default: /* LD (nn),rr */
2234 if (ins_ok
& INS_GBZ80
)
2236 /* GBZ80 supports only LD (nn),SP */
2237 if (src
->X_add_number
== REG_SP
)
2247 switch (src
->X_add_number
)
2249 case REG_BC
: prefix
= 0xED; opcode
= 0x43; break;
2250 case REG_DE
: prefix
= 0xED; opcode
= 0x53; break;
2251 case REG_HL
: prefix
= 0x00; opcode
= 0x22; break;
2252 case REG_IX
: prefix
= 0xDD; opcode
= 0x22; break;
2253 case REG_IY
: prefix
= 0xFD; opcode
= 0x22; break;
2254 case REG_SP
: prefix
= 0xED; opcode
= 0x73; break;
2259 q
= frag_more (prefix
? 2 : 1);
2268 emit_ld_r_m (expressionS
*dst
, expressionS
*src
)
2269 { /* for 8-bit memory load to register: LD r,(xxx) */
2273 expressionS src_offset
;
2275 if (dst
->X_add_number
== REG_A
&& src
->X_op
== O_register
)
2276 { /* LD A,(BC) or LD A,(DE) */
2277 switch (src
->X_add_number
)
2279 case REG_BC
: opcode
= 0x0A; break;
2280 case REG_DE
: opcode
= 0x1A; break;
2294 if (ins_ok
& INS_GBZ80
)
2295 { /* LD A,(HL+) or LD A,(HL-) */
2296 if (dst
->X_op
== O_register
&& dst
->X_add_number
== REG_A
)
2297 *frag_more (1) = (src
->X_add_number
== REG_HL
) ? 0x2A : 0x3A;
2304 if (dst
->X_add_number
> 7)
2306 opcode
= 0x46; /* LD B,(HL) */
2307 switch (src
->X_add_number
)
2309 case REG_HL
: prefix
= 0x00; break;
2310 case REG_IX
: prefix
= 0xDD; break;
2311 case REG_IY
: prefix
= 0xFD; break;
2315 q
= frag_more (prefix
? 2 : 1);
2318 *q
= opcode
| ((dst
->X_add_number
& 7) << 3);
2322 src_offset
.X_op
= O_symbol
;
2323 src_offset
.X_add_number
= 0;
2324 emit_byte (& src_offset
, BFD_RELOC_Z80_DISP8
);
2327 default: /* LD A,(nn) */
2328 if (dst
->X_add_number
== REG_A
)
2331 *q
= (ins_ok
& INS_GBZ80
) ? 0xFA : 0x3A;
2338 emit_ld_r_n (expressionS
*dst
, expressionS
*src
)
2339 { /* for 8-bit immediate value load to register: LD r,n */
2343 switch (dst
->X_add_number
)
2366 q
= frag_more (prefix
? 2 : 1);
2369 if (ins_ok
& INS_GBZ80
)
2371 else if (!(ins_ok
& INS_EZ80
))
2372 check_mach (INS_IDX_HALF
);
2375 *q
= 0x06 | ((dst
->X_add_number
& 7) << 3);
2376 emit_byte (src
, BFD_RELOC_8
);
2380 emit_ld_r_r (expressionS
*dst
, expressionS
*src
)
2381 { /* mostly 8-bit load register from register instructions: LD r,r */
2382 /* there are some exceptions: LD SP,HL/IX/IY; LD I,HL and LD HL,I */
2388 switch (dst
->X_add_number
)
2391 switch (src
->X_add_number
)
2393 case REG_HL
: prefix
= 0x00; break;
2394 case REG_IX
: prefix
= 0xDD; break;
2395 case REG_IY
: prefix
= 0xFD; break;
2402 if (!(ins_ok
& INS_EZ80
))
2404 if (src
->X_add_number
!= REG_I
)
2407 error (_("ADL mode instruction"));
2413 if (src
->X_add_number
== REG_HL
)
2415 if (!(ins_ok
& INS_EZ80
))
2418 error (_("ADL mode instruction"));
2422 else if (src
->X_add_number
== REG_A
)
2431 if (!(ins_ok
& INS_EZ80
) || (src
->X_add_number
!= REG_A
))
2434 error (_("ADL mode instruction"));
2439 if (src
->X_add_number
== REG_A
) /* LD R,A */
2448 if (src
->X_add_number
== REG_I
) /* LD A,I */
2454 else if (src
->X_add_number
== REG_R
) /* LD A,R */
2460 else if (src
->X_add_number
== REG_MB
) /* LD A,MB */
2462 if (!(ins_ok
& INS_EZ80
))
2467 error (_("ADL mode instruction"));
2498 switch (src
->X_add_number
)
2509 ill_op (); /* LD iiH/L,H/L are not permitted */
2513 if (prefix
== 0xFD || dst
->X_add_number
== REG_H
|| dst
->X_add_number
== REG_L
)
2514 ill_op (); /* LD IYL,IXL and LD H,IXH are not permitted */
2520 if (prefix
== 0xDD || dst
->X_add_number
== REG_H
|| dst
->X_add_number
== REG_L
)
2521 ill_op (); /* LD IXH,IYH and LD L,IYL are not permitted */
2528 opcode
= 0x40 + ((dst
->X_add_number
& 7) << 3) + (src
->X_add_number
& 7);
2530 if ((ins_ok
& INS_GBZ80
) && prefix
!= 0)
2532 if (ii_halves
&& !(ins_ok
& INS_EZ80
))
2533 check_mach (INS_IDX_HALF
);
2534 if (prefix
== 0 && (ins_ok
& INS_EZ80
))
2538 case 0x40: /* SIS prefix, in Z80 it is LD B,B */
2539 case 0x49: /* LIS prefix, in Z80 it is LD C,C */
2540 case 0x52: /* SIL prefix, in Z80 it is LD D,D */
2541 case 0x5B: /* LIL prefix, in Z80 it is LD E,E */
2542 as_warn (_("unsupported instruction, assembled as NOP"));
2548 q
= frag_more (prefix
? 2 : 1);
2555 emit_ld_rr_m (expressionS
*dst
, expressionS
*src
)
2556 { /* for 16-bit indirect load from memory to register: LD rr,(xxx) */
2560 expressionS src_offset
;
2562 /* GBZ80 has no support for 16-bit load from memory instructions */
2563 if (ins_ok
& INS_GBZ80
)
2569 case O_md1
: /* LD rr,(ii+d) */
2570 prefix
= (src
->X_add_number
== REG_IX
) ? 0xDD : 0xFD;
2572 case O_register
: /* LD rr,(HL) */
2573 /* currently only EZ80 has support for 16bit indirect memory load instructions */
2574 if (!(ins_ok
& INS_EZ80
))
2576 switch (dst
->X_add_number
)
2578 case REG_BC
: opcode
= 0x07; break;
2579 case REG_DE
: opcode
= 0x17; break;
2580 case REG_HL
: opcode
= 0x27; break;
2581 case REG_IX
: opcode
= (!prefix
|| prefix
== 0xDD) ? 0x37 : 0x31; break;
2582 case REG_IY
: opcode
= prefix
? ((prefix
== 0xDD) ? 0x31 : 0x37) : 0x36; break;
2592 src_offset
.X_op
= O_symbol
;
2593 src_offset
.X_add_number
= 0;
2594 emit_byte (& src_offset
, BFD_RELOC_Z80_DISP8
);
2597 default: /* LD rr,(nn) */
2598 switch (dst
->X_add_number
)
2600 case REG_BC
: prefix
= 0xED; opcode
= 0x4B; break;
2601 case REG_DE
: prefix
= 0xED; opcode
= 0x5B; break;
2602 case REG_HL
: prefix
= 0x00; opcode
= 0x2A; break;
2603 case REG_SP
: prefix
= 0xED; opcode
= 0x7B; break;
2604 case REG_IX
: prefix
= 0xDD; opcode
= 0x2A; break;
2605 case REG_IY
: prefix
= 0xFD; opcode
= 0x2A; break;
2609 q
= frag_more (prefix
? 2 : 1);
2619 emit_ld_rr_nn (expressionS
*dst
, expressionS
*src
)
2620 { /* mostly load imediate value to multibyte register instructions: LD rr,nn */
2623 int opcode
= 0x21; /* LD HL,nn */
2624 switch (dst
->X_add_number
)
2637 opcode
= 0x01 + ((dst
->X_add_number
& 3) << 4);
2643 if (prefix
&& (ins_ok
& INS_GBZ80
))
2645 q
= frag_more (prefix
? 2 : 1);
2653 emit_ld (char prefix_in ATTRIBUTE_UNUSED
, char opcode_in ATTRIBUTE_UNUSED
,
2656 expressionS dst
, src
;
2659 p
= parse_exp (args
, & dst
);
2661 error (_("bad instruction syntax"));
2662 p
= parse_exp (p
, & src
);
2666 if (src
.X_op
== O_register
)
2668 if (src
.X_add_number
<= 7)
2669 emit_ld_m_r (& dst
, & src
); /* LD (xxx),r */
2671 emit_ld_m_rr (& dst
, & src
); /* LD (xxx),rr */
2674 emit_ld_m_n (& dst
, & src
); /* LD (hl),n or LD (ix/y+r),n */
2676 else if (dst
.X_op
== O_register
)
2680 if (dst
.X_add_number
<= 7)
2681 emit_ld_r_m (& dst
, & src
);
2683 emit_ld_rr_m (& dst
, & src
);
2685 else if (src
.X_op
== O_register
)
2686 emit_ld_r_r (& dst
, & src
);
2687 else if ((dst
.X_add_number
& ~R_INDEX
) <= 7)
2688 emit_ld_r_n (& dst
, & src
);
2690 emit_ld_rr_nn (& dst
, & src
);
2699 emit_lddldi (char prefix
, char opcode
, const char * args
)
2701 expressionS dst
, src
;
2705 if (!(ins_ok
& INS_GBZ80
))
2706 return emit_insn (prefix
, opcode
, args
);
2708 p
= parse_exp (args
, & dst
);
2710 error (_("bad instruction syntax"));
2711 p
= parse_exp (p
, & src
);
2713 if (dst
.X_op
!= O_register
|| src
.X_op
!= O_register
)
2716 /* convert opcode 0xA0 . 0x22, 0xA8 . 0x32 */
2717 opcode
= (opcode
& 0x08) * 2 + 0x22;
2720 && dst
.X_add_number
== REG_HL
2722 && src
.X_add_number
== REG_A
)
2723 opcode
|= 0x00; /* LDx (HL),A */
2724 else if (dst
.X_md
== 0
2725 && dst
.X_add_number
== REG_A
2727 && src
.X_add_number
== REG_HL
)
2728 opcode
|= 0x08; /* LDx A,(HL) */
2738 emit_ldh (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2741 expressionS dst
, src
;
2745 p
= parse_exp (args
, & dst
);
2748 error (_("bad instruction syntax"));
2752 p
= parse_exp (p
, & src
);
2754 && dst
.X_op
== O_register
2755 && dst
.X_add_number
== REG_A
2757 && src
.X_op
!= O_md1
)
2759 if (src
.X_op
!= O_register
)
2763 emit_byte (& src
, BFD_RELOC_8
);
2765 else if (src
.X_add_number
== REG_C
)
2766 *frag_more (1) = 0xF2;
2770 else if (dst
.X_md
!= 0
2771 && dst
.X_op
!= O_md1
2773 && src
.X_op
== O_register
2774 && src
.X_add_number
== REG_A
)
2776 if (dst
.X_op
== O_register
)
2778 if (dst
.X_add_number
== REG_C
)
2790 emit_byte (& dst
, BFD_RELOC_8
);
2800 emit_ldhl (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
2802 expressionS dst
, src
;
2805 p
= parse_exp (args
, & dst
);
2808 error (_("bad instruction syntax"));
2812 p
= parse_exp (p
, & src
);
2813 if (dst
.X_md
|| dst
.X_op
!= O_register
|| dst
.X_add_number
!= REG_SP
2814 || src
.X_md
|| src
.X_op
== O_register
|| src
.X_op
== O_md1
)
2818 emit_byte (& src
, BFD_RELOC_Z80_DISP8
);
2823 parse_lea_pea_args (const char * args
, expressionS
*op
)
2826 p
= parse_exp (args
, op
);
2827 if (sdcc_compat
&& *p
== ',' && op
->X_op
== O_register
)
2830 p
= parse_exp (p
+ 1, &off
);
2832 op
->X_add_symbol
= make_expr_symbol (&off
);
2838 emit_lea (char prefix
, char opcode
, const char * args
)
2840 expressionS dst
, src
;
2845 p
= parse_exp (args
, & dst
);
2846 if (dst
.X_md
!= 0 || dst
.X_op
!= O_register
)
2849 rnum
= dst
.X_add_number
;
2855 opcode
= 0x02 | ((rnum
& 0x03) << 4);
2858 opcode
= 0x32; /* lea ix,ix+d has opcode 0x32; lea ix,iy+d has opcode 0x54 */
2861 opcode
= 0x33; /* lea iy,iy+d has opcode 0x33; lea iy,ix+d has opcode 0x55 */
2868 error (_("bad instruction syntax"));
2870 p
= parse_lea_pea_args (p
, & src
);
2871 if (src
.X_md
!= 0 || src
.X_op
!= O_add
/*&& src.X_op != O_register*/)
2874 rnum
= src
.X_add_number
;
2879 case O_register
: /* permit instructions like LEA rr,IX without displacement specified */
2880 src
.X_add_symbol
= zero
;
2889 opcode
= (opcode
== (char)0x33) ? 0x55 : (opcode
|0x00);
2892 opcode
= (opcode
== (char)0x32) ? 0x54 : (opcode
|0x01);
2899 src
.X_op
= O_symbol
;
2900 src
.X_add_number
= 0;
2901 emit_byte (& src
, BFD_RELOC_Z80_DISP8
);
2907 emit_mlt (char prefix
, char opcode
, const char * args
)
2913 p
= parse_exp (args
, & arg
);
2914 if (arg
.X_md
!= 0 || arg
.X_op
!= O_register
|| !(arg
.X_add_number
& R_ARITH
))
2918 if (ins_ok
& INS_Z80N
)
2920 if (arg
.X_add_number
!= REG_DE
)
2928 *q
= opcode
| ((arg
.X_add_number
& 3) << 4);
2934 /* MUL D,E (Z80N only) */
2936 emit_mul (char prefix
, char opcode
, const char * args
)
2942 p
= parse_exp (args
, & r1
);
2944 error (_("bad instruction syntax"));
2945 p
= parse_exp (p
, & r2
);
2947 if (r1
.X_md
!= 0 || r1
.X_op
!= O_register
|| r1
.X_add_number
!= REG_D
||
2948 r2
.X_md
!= 0 || r2
.X_op
!= O_register
|| r2
.X_add_number
!= REG_E
)
2959 emit_nextreg (char prefix
, char opcode ATTRIBUTE_UNUSED
, const char * args
)
2965 p
= parse_exp (args
, & rr
);
2967 error (_("bad instruction syntax"));
2968 p
= parse_exp (p
, & nn
);
2969 if (rr
.X_md
!= 0 || rr
.X_op
== O_register
|| rr
.X_op
== O_md1
||
2970 nn
.X_md
!= 0 || nn
.X_op
== O_md1
)
2974 emit_byte (&rr
, BFD_RELOC_8
);
2975 if (nn
.X_op
== O_register
&& nn
.X_add_number
== REG_A
)
2977 else if (nn
.X_op
!= O_register
)
2980 emit_byte (&nn
, BFD_RELOC_8
);
2988 emit_pea (char prefix
, char opcode
, const char * args
)
2994 p
= parse_lea_pea_args (args
, & arg
);
2996 || (/*arg.X_op != O_register &&*/ arg
.X_op
!= O_add
)
2997 || !(arg
.X_add_number
& R_INDEX
))
2999 /* PEA ii without displacement is mostly typo,
3000 because there is PUSH instruction which is shorter and faster */
3001 /*if (arg.X_op == O_register)
3002 as_warn (_("PEA is used without displacement, use PUSH instead"));*/
3006 *q
= opcode
+ (arg
.X_add_number
== REG_IY
? 1 : 0);
3008 arg
.X_op
= O_symbol
;
3009 arg
.X_add_number
= 0;
3010 emit_byte (& arg
, BFD_RELOC_Z80_DISP8
);
3016 emit_reti (char prefix
, char opcode
, const char * args
)
3018 if (ins_ok
& INS_GBZ80
)
3019 return emit_insn (0x00, 0xD9, args
);
3021 return emit_insn (prefix
, opcode
, args
);
3025 emit_tst (char prefix
, char opcode
, const char *args
)
3032 p
= parse_exp (args
, & arg_s
);
3033 if (*p
== ',' && arg_s
.X_md
== 0 && arg_s
.X_op
== O_register
&& arg_s
.X_add_number
== REG_A
)
3035 if (!(ins_ok
& INS_EZ80
))
3038 p
= parse_exp (p
, & arg_s
);
3041 rnum
= arg_s
.X_add_number
;
3048 rnum
= arg_s
.X_add_number
;
3049 if (arg_s
.X_md
!= 0)
3058 *q
= opcode
| (rnum
<< 3);
3064 if (ins_ok
& INS_Z80N
)
3074 emit_byte (& arg_s
, BFD_RELOC_8
);
3080 emit_insn_n (char prefix
, char opcode
, const char *args
)
3086 p
= parse_exp (args
, & arg
);
3087 if (arg
.X_md
|| arg
.X_op
== O_register
|| arg
.X_op
== O_md1
)
3093 emit_byte (& arg
, BFD_RELOC_8
);
3099 emit_data (int size ATTRIBUTE_UNUSED
)
3106 if (is_it_end_of_statement ())
3108 demand_empty_rest_of_line ();
3111 p
= skip_space (input_line_pointer
);
3115 if (*p
== '\"' || *p
== '\'')
3117 for (quote
= *p
, q
= ++p
, cnt
= 0; *p
&& quote
!= *p
; ++p
, ++cnt
)
3119 u
= frag_more (cnt
);
3122 as_warn (_("unterminated string"));
3124 p
= skip_space (p
+1);
3128 p
= parse_exp (p
, &exp
);
3129 if (exp
.X_op
== O_md1
|| exp
.X_op
== O_register
)
3135 as_warn (_("parentheses ignored"));
3136 emit_byte (&exp
, BFD_RELOC_8
);
3140 while (*p
++ == ',') ;
3141 input_line_pointer
= (char *)(p
-1);
3150 if (is_it_end_of_statement ())
3152 demand_empty_rest_of_line ();
3155 p
= skip_space (input_line_pointer
);
3159 p
= parse_exp (p
, &exp
);
3160 if (exp
.X_op
== O_md1
|| exp
.X_op
== O_register
)
3166 as_warn (_("parentheses ignored"));
3167 emit_data_val (&exp
, size
);
3169 } while (*p
++ == ',') ;
3170 input_line_pointer
= (char *)(p
-1);
3173 /* next functions were commented out because it is difficult to mix
3174 both ADL and Z80 mode instructions within one COFF file:
3175 objdump cannot recognize point of mode switching.
3178 set_cpu_mode (int mode
)
3180 if (ins_ok
& INS_EZ80
)
3183 error (_("CPU mode is unsupported by target"));
3187 assume (int arg ATTRIBUTE_UNUSED
)
3193 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3194 c
= get_symbol_name (& name
);
3195 if (strncasecmp (name
, "ADL", 4) != 0)
3201 restore_line_pointer (c
);
3202 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3203 if (*input_line_pointer
++ != '=')
3205 error (_("assignment expected"));
3208 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3209 n
= get_single_number ();
3215 emit_mulub (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
3219 p
= skip_space (args
);
3220 if (TOLOWER (*p
++) != 'a' || *p
++ != ',')
3226 reg
= TOLOWER (*p
++);
3233 check_mach (INS_R800
);
3234 if (!*skip_space (p
))
3238 *q
= opcode
+ ((reg
- 'b') << 3);
3250 emit_muluw (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
3254 p
= skip_space (args
);
3255 if (TOLOWER (*p
++) != 'h' || TOLOWER (*p
++) != 'l' || *p
++ != ',')
3262 p
= parse_exp (p
, & reg
);
3264 if ((!reg
.X_md
) && reg
.X_op
== O_register
)
3265 switch (reg
.X_add_number
)
3269 check_mach (INS_R800
);
3272 *q
= opcode
+ ((reg
.X_add_number
& 3) << 4);
3282 assemble_suffix (const char **suffix
)
3285 const char sf
[8][4] =
3305 for (i
= 0; (i
< 3) && (ISALPHA (*p
)); i
++)
3306 sbuf
[i
] = TOLOWER (*p
++);
3307 if (*p
&& !ISSPACE (*p
))
3312 t
= bsearch (sbuf
, sf
, ARRAY_SIZE (sf
), sizeof (sf
[0]), (int(*)(const void*, const void*)) strcmp
);
3319 i
= cpu_mode
? 0x5B : 0x52;
3322 i
= cpu_mode
? 0x49 : 0x40;
3325 i
= cpu_mode
? 0x5B : 0x49;
3334 i
= cpu_mode
? 0x52 : 0x40;
3343 *frag_more (1) = (char)i
;
3346 case 0x40: inst_mode
= INST_MODE_FORCED
| INST_MODE_S
| INST_MODE_IS
; break;
3347 case 0x49: inst_mode
= INST_MODE_FORCED
| INST_MODE_L
| INST_MODE_IS
; break;
3348 case 0x52: inst_mode
= INST_MODE_FORCED
| INST_MODE_S
| INST_MODE_IL
; break;
3349 case 0x5B: inst_mode
= INST_MODE_FORCED
| INST_MODE_L
| INST_MODE_IL
; break;
3357 #if defined(OBJ_ELF)
3358 return obj_elf_section (arg
);
3359 #elif defined(OBJ_COFF)
3360 return obj_coff_section (arg
);
3362 #error Unknown object format
3372 as_fatal (_("Invalid directive"));
3375 ins_ok
&= INS_MARCH_MASK
;
3377 if (old_ins
!= ins_ok
)
3382 ignore (int arg ATTRIBUTE_UNUSED
)
3384 ignore_rest_of_line ();
3392 as_fatal (_("Invalid directive"));
3393 for (p
= input_line_pointer
; *p
&& *p
!= '(' && *p
!= '\n'; p
++)
3400 ignore_rest_of_line ();
3406 /* Port specific pseudo ops. */
3407 const pseudo_typeS md_pseudo_table
[] =
3409 { ".area", area
, 0},
3410 { ".assume", assume
, 0},
3411 { ".ez80", set_inss
, INS_EZ80
},
3412 { ".gbz80", set_inss
, INS_GBZ80
},
3413 { ".module", ignore
, 0},
3414 { ".optsdcc", ignore
, 0},
3415 { ".r800", set_inss
, INS_R800
},
3416 { ".set", s_set
, 0},
3417 { ".z180", set_inss
, INS_Z180
},
3418 { ".z80", set_inss
, INS_Z80
},
3419 { ".z80n", set_inss
, INS_Z80N
},
3420 { "db" , emit_data
, 1},
3421 { "d24", z80_cons
, 3},
3422 { "d32", z80_cons
, 4},
3423 { "def24", z80_cons
, 3},
3424 { "def32", z80_cons
, 4},
3425 { "defb", emit_data
, 1},
3426 { "defm", emit_data
, 1},
3427 { "defs", s_space
, 1}, /* Synonym for ds on some assemblers. */
3428 { "defw", z80_cons
, 2},
3429 { "ds", s_space
, 1}, /* Fill with bytes rather than words. */
3430 { "dw", z80_cons
, 2},
3431 { "psect", psect
, 0}, /* TODO: Translate attributes. */
3432 { "set", 0, 0}, /* Real instruction on z80. */
3436 static table_t instab
[] =
3438 { "adc", 0x88, 0x4A, emit_adc
, INS_ALL
},
3439 { "add", 0x80, 0x09, emit_add
, INS_ALL
},
3440 { "and", 0x00, 0xA0, emit_s
, INS_ALL
},
3441 { "bit", 0xCB, 0x40, emit_bit
, INS_ALL
},
3442 { "brlc", 0xED, 0x2C, emit_bshft
,INS_Z80N
},
3443 { "bsla", 0xED, 0x28, emit_bshft
,INS_Z80N
},
3444 { "bsra", 0xED, 0x29, emit_bshft
,INS_Z80N
},
3445 { "bsrf", 0xED, 0x2B, emit_bshft
,INS_Z80N
},
3446 { "bsrl", 0xED, 0x2A, emit_bshft
,INS_Z80N
},
3447 { "call", 0xCD, 0xC4, emit_jpcc
, INS_ALL
},
3448 { "ccf", 0x00, 0x3F, emit_insn
, INS_ALL
},
3449 { "cp", 0x00, 0xB8, emit_s
, INS_ALL
},
3450 { "cpd", 0xED, 0xA9, emit_insn
, INS_NOT_GBZ80
},
3451 { "cpdr", 0xED, 0xB9, emit_insn
, INS_NOT_GBZ80
},
3452 { "cpi", 0xED, 0xA1, emit_insn
, INS_NOT_GBZ80
},
3453 { "cpir", 0xED, 0xB1, emit_insn
, INS_NOT_GBZ80
},
3454 { "cpl", 0x00, 0x2F, emit_insn
, INS_ALL
},
3455 { "daa", 0x00, 0x27, emit_insn
, INS_ALL
},
3456 { "dec", 0x0B, 0x05, emit_incdec
,INS_ALL
},
3457 { "di", 0x00, 0xF3, emit_insn
, INS_ALL
},
3458 { "djnz", 0x00, 0x10, emit_jr
, INS_NOT_GBZ80
},
3459 { "ei", 0x00, 0xFB, emit_insn
, INS_ALL
},
3460 { "ex", 0x00, 0x00, emit_ex
, INS_NOT_GBZ80
},
3461 { "exx", 0x00, 0xD9, emit_insn
, INS_NOT_GBZ80
},
3462 { "halt", 0x00, 0x76, emit_insn
, INS_ALL
},
3463 { "im", 0xED, 0x46, emit_im
, INS_NOT_GBZ80
},
3464 { "in", 0x00, 0x00, emit_in
, INS_NOT_GBZ80
},
3465 { "in0", 0xED, 0x00, emit_in0
, INS_Z180
|INS_EZ80
},
3466 { "inc", 0x03, 0x04, emit_incdec
,INS_ALL
},
3467 { "ind", 0xED, 0xAA, emit_insn
, INS_NOT_GBZ80
},
3468 { "ind2", 0xED, 0x8C, emit_insn
, INS_EZ80
},
3469 { "ind2r",0xED, 0x9C, emit_insn
, INS_EZ80
},
3470 { "indm", 0xED, 0x8A, emit_insn
, INS_EZ80
},
3471 { "indmr",0xED, 0x9A, emit_insn
, INS_EZ80
},
3472 { "indr", 0xED, 0xBA, emit_insn
, INS_NOT_GBZ80
},
3473 { "indrx",0xED, 0xCA, emit_insn
, INS_EZ80
},
3474 { "ini", 0xED, 0xA2, emit_insn
, INS_NOT_GBZ80
},
3475 { "ini2", 0xED, 0x84, emit_insn
, INS_EZ80
},
3476 { "ini2r",0xED, 0x94, emit_insn
, INS_EZ80
},
3477 { "inim", 0xED, 0x82, emit_insn
, INS_EZ80
},
3478 { "inimr",0xED, 0x92, emit_insn
, INS_EZ80
},
3479 { "inir", 0xED, 0xB2, emit_insn
, INS_NOT_GBZ80
},
3480 { "inirx",0xED, 0xC2, emit_insn
, INS_EZ80
},
3481 { "jp", 0xC3, 0xC2, emit_jpcc
, INS_ALL
},
3482 { "jr", 0x18, 0x20, emit_jrcc
, INS_ALL
},
3483 { "ld", 0x00, 0x00, emit_ld
, INS_ALL
},
3484 { "ldd", 0xED, 0xA8, emit_lddldi
,INS_ALL
}, /* GBZ80 has special meaning */
3485 { "lddr", 0xED, 0xB8, emit_insn
, INS_NOT_GBZ80
},
3486 { "lddrx",0xED, 0xBC, emit_insn
, INS_Z80N
},
3487 { "lddx", 0xED, 0xAC, emit_insn
, INS_Z80N
},
3488 { "ldh", 0xE0, 0x00, emit_ldh
, INS_GBZ80
},
3489 { "ldhl", 0x00, 0xF8, emit_ldhl
, INS_GBZ80
},
3490 { "ldi", 0xED, 0xA0, emit_lddldi
,INS_ALL
}, /* GBZ80 has special meaning */
3491 { "ldir", 0xED, 0xB0, emit_insn
, INS_NOT_GBZ80
},
3492 { "ldirx",0xED, 0xB4, emit_insn
, INS_Z80N
},
3493 { "ldix", 0xED, 0xA4, emit_insn
, INS_Z80N
},
3494 { "ldpirx",0xED,0xB7, emit_insn
, INS_Z80N
},
3495 { "ldws", 0xED, 0xA5, emit_insn
, INS_Z80N
},
3496 { "lea", 0xED, 0x02, emit_lea
, INS_EZ80
},
3497 { "mirror",0xED,0x24, emit_insn
, INS_Z80N
},
3498 { "mlt", 0xED, 0x4C, emit_mlt
, INS_Z180
|INS_EZ80
|INS_Z80N
},
3499 { "mul", 0xED, 0x30, emit_mul
, INS_Z80N
},
3500 { "mulub",0xED, 0xC5, emit_mulub
,INS_R800
},
3501 { "muluw",0xED, 0xC3, emit_muluw
,INS_R800
},
3502 { "neg", 0xED, 0x44, emit_insn
, INS_NOT_GBZ80
},
3503 { "nextreg",0xED,0x91,emit_nextreg
,INS_Z80N
},
3504 { "nop", 0x00, 0x00, emit_insn
, INS_ALL
},
3505 { "or", 0x00, 0xB0, emit_s
, INS_ALL
},
3506 { "otd2r",0xED, 0xBC, emit_insn
, INS_EZ80
},
3507 { "otdm", 0xED, 0x8B, emit_insn
, INS_Z180
|INS_EZ80
},
3508 { "otdmr",0xED, 0x9B, emit_insn
, INS_Z180
|INS_EZ80
},
3509 { "otdr", 0xED, 0xBB, emit_insn
, INS_NOT_GBZ80
},
3510 { "otdrx",0xED, 0xCB, emit_insn
, INS_EZ80
},
3511 { "oti2r",0xED, 0xB4, emit_insn
, INS_EZ80
},
3512 { "otim", 0xED, 0x83, emit_insn
, INS_Z180
|INS_EZ80
},
3513 { "otimr",0xED, 0x93, emit_insn
, INS_Z180
|INS_EZ80
},
3514 { "otir", 0xED, 0xB3, emit_insn
, INS_NOT_GBZ80
},
3515 { "otirx",0xED, 0xC3, emit_insn
, INS_EZ80
},
3516 { "out", 0x00, 0x00, emit_out
, INS_NOT_GBZ80
},
3517 { "out0", 0xED, 0x01, emit_out0
, INS_Z180
|INS_EZ80
},
3518 { "outd", 0xED, 0xAB, emit_insn
, INS_NOT_GBZ80
},
3519 { "outd2",0xED, 0xAC, emit_insn
, INS_EZ80
},
3520 { "outi", 0xED, 0xA3, emit_insn
, INS_NOT_GBZ80
},
3521 { "outi2",0xED, 0xA4, emit_insn
, INS_EZ80
},
3522 { "outinb",0xED,0x90, emit_insn
, INS_Z80N
},
3523 { "pea", 0xED, 0x65, emit_pea
, INS_EZ80
},
3524 { "pixelad",0xED,0x94,emit_insn
, INS_Z80N
},
3525 { "pixeldn",0xED,0x93,emit_insn
, INS_Z80N
},
3526 { "pop", 0x00, 0xC1, emit_pop
, INS_ALL
},
3527 { "push", 0x00, 0xC5, emit_push
, INS_ALL
},
3528 { "res", 0xCB, 0x80, emit_bit
, INS_ALL
},
3529 { "ret", 0xC9, 0xC0, emit_retcc
,INS_ALL
},
3530 { "reti", 0xED, 0x4D, emit_reti
, INS_ALL
}, /*GBZ80 has its own opcode for it*/
3531 { "retn", 0xED, 0x45, emit_insn
, INS_NOT_GBZ80
},
3532 { "rl", 0xCB, 0x10, emit_mr
, INS_ALL
},
3533 { "rla", 0x00, 0x17, emit_insn
, INS_ALL
},
3534 { "rlc", 0xCB, 0x00, emit_mr
, INS_ALL
},
3535 { "rlca", 0x00, 0x07, emit_insn
, INS_ALL
},
3536 { "rld", 0xED, 0x6F, emit_insn
, INS_NOT_GBZ80
},
3537 { "rr", 0xCB, 0x18, emit_mr
, INS_ALL
},
3538 { "rra", 0x00, 0x1F, emit_insn
, INS_ALL
},
3539 { "rrc", 0xCB, 0x08, emit_mr
, INS_ALL
},
3540 { "rrca", 0x00, 0x0F, emit_insn
, INS_ALL
},
3541 { "rrd", 0xED, 0x67, emit_insn
, INS_NOT_GBZ80
},
3542 { "rsmix",0xED, 0x7E, emit_insn
, INS_EZ80
},
3543 { "rst", 0x00, 0xC7, emit_rst
, INS_ALL
},
3544 { "sbc", 0x98, 0x42, emit_adc
, INS_ALL
},
3545 { "scf", 0x00, 0x37, emit_insn
, INS_ALL
},
3546 { "set", 0xCB, 0xC0, emit_bit
, INS_ALL
},
3547 { "setae",0xED, 0x95, emit_insn
, INS_Z80N
},
3548 { "sl1", 0xCB, 0x30, emit_mr
, INS_SLI
},
3549 { "sla", 0xCB, 0x20, emit_mr
, INS_ALL
},
3550 { "sli", 0xCB, 0x30, emit_mr
, INS_SLI
},
3551 { "sll", 0xCB, 0x30, emit_mr
, INS_SLI
},
3552 { "slp", 0xED, 0x76, emit_insn
, INS_Z180
|INS_EZ80
},
3553 { "sra", 0xCB, 0x28, emit_mr
, INS_ALL
},
3554 { "srl", 0xCB, 0x38, emit_mr
, INS_ALL
},
3555 { "stmix",0xED, 0x7D, emit_insn
, INS_EZ80
},
3556 { "stop", 0x00, 0x10, emit_insn
, INS_GBZ80
},
3557 { "sub", 0x00, 0x90, emit_sub
, INS_ALL
},
3558 { "swap", 0xCB, 0x30, emit_swap
, INS_GBZ80
|INS_Z80N
},
3559 { "swapnib",0xED,0x23,emit_insn
, INS_Z80N
},
3560 { "test", 0xED, 0x27, emit_insn_n
, INS_Z80N
},
3561 { "tst", 0xED, 0x04, emit_tst
, INS_Z180
|INS_EZ80
|INS_Z80N
},
3562 { "tstio",0xED, 0x74, emit_insn_n
,INS_Z180
|INS_EZ80
},
3563 { "xor", 0x00, 0xA8, emit_s
, INS_ALL
},
3567 md_assemble (char *str
)
3575 inst_mode
= cpu_mode
? (INST_MODE_L
| INST_MODE_IL
) : (INST_MODE_S
| INST_MODE_IS
);
3576 old_ptr
= input_line_pointer
;
3577 p
= skip_space (str
);
3578 for (i
= 0; (i
< BUFLEN
) && (ISALPHA (*p
) || ISDIGIT (*p
));)
3579 buf
[i
++] = TOLOWER (*p
++);
3583 buf
[BUFLEN
-3] = buf
[BUFLEN
-2] = '.'; /* Mark opcode as abbreviated. */
3585 as_bad (_("Unknown instruction '%s'"), buf
);
3589 dwarf2_emit_insn (0);
3590 if ((*p
) && (!ISSPACE (*p
)))
3592 if (*p
!= '.' || !(ins_ok
& INS_EZ80
) || !assemble_suffix (&p
))
3594 as_bad (_("syntax error"));
3602 insp
= bsearch (&key
, instab
, ARRAY_SIZE (instab
),
3603 sizeof (instab
[0]), key_cmp
);
3604 if (!insp
|| (insp
->inss
&& !(insp
->inss
& ins_ok
)))
3607 as_bad (_("Unknown instruction `%s'"), buf
);
3611 p
= insp
->fp (insp
->prefix
, insp
->opcode
, p
);
3613 if ((!err_flag
) && *p
)
3614 as_bad (_("junk at end of line, "
3615 "first unrecognized character is `%c'"), *p
);
3619 input_line_pointer
= old_ptr
;
3623 is_overflow (long value
, unsigned bitsize
)
3625 long fieldmask
= (1 << bitsize
) - 1;
3626 long signmask
= ~fieldmask
;
3627 long a
= value
& fieldmask
;
3628 long ss
= a
& signmask
;
3629 if (ss
!= 0 && ss
!= (signmask
& fieldmask
))
3635 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
3638 char *p_lit
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3640 if (fixP
->fx_addsy
== NULL
)
3642 else if (fixP
->fx_pcrel
)
3644 segT s
= S_GET_SEGMENT (fixP
->fx_addsy
);
3645 if (s
== seg
|| s
== absolute_section
)
3647 val
+= S_GET_VALUE (fixP
->fx_addsy
);
3652 switch (fixP
->fx_r_type
)
3654 case BFD_RELOC_8_PCREL
:
3655 case BFD_RELOC_Z80_DISP8
:
3660 case BFD_RELOC_Z80_16_BE
:
3661 fixP
->fx_no_overflow
= 0;
3664 fixP
->fx_no_overflow
= 1;
3668 switch (fixP
->fx_r_type
)
3670 case BFD_RELOC_8_PCREL
:
3671 case BFD_RELOC_Z80_DISP8
:
3672 if (fixP
->fx_done
&& (val
< -0x80 || val
> 0x7f))
3673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3674 _("8-bit signed offset out of range (%+ld)"), val
);
3678 case BFD_RELOC_Z80_BYTE0
:
3682 case BFD_RELOC_Z80_BYTE1
:
3683 *p_lit
++ = (val
>> 8);
3686 case BFD_RELOC_Z80_BYTE2
:
3687 *p_lit
++ = (val
>> 16);
3690 case BFD_RELOC_Z80_BYTE3
:
3691 *p_lit
++ = (val
>> 24);
3695 if (fixP
->fx_done
&& is_overflow(val
, 8))
3696 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3697 _("8-bit overflow (%+ld)"), val
);
3701 case BFD_RELOC_Z80_WORD1
:
3702 *p_lit
++ = (val
>> 16);
3703 *p_lit
++ = (val
>> 24);
3706 case BFD_RELOC_Z80_WORD0
:
3708 *p_lit
++ = (val
>> 8);
3712 if (fixP
->fx_done
&& is_overflow(val
, 16))
3713 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3714 _("16-bit overflow (%+ld)"), val
);
3716 *p_lit
++ = (val
>> 8);
3719 case BFD_RELOC_24
: /* Def24 may produce this. */
3720 if (fixP
->fx_done
&& is_overflow(val
, 24))
3721 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3722 _("24-bit overflow (%+ld)"), val
);
3724 *p_lit
++ = (val
>> 8);
3725 *p_lit
++ = (val
>> 16);
3728 case BFD_RELOC_32
: /* Def32 and .long may produce this. */
3729 if (fixP
->fx_done
&& is_overflow(val
, 32))
3730 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3731 _("32-bit overflow (%+ld)"), val
);
3733 *p_lit
++ = (val
>> 8);
3734 *p_lit
++ = (val
>> 16);
3735 *p_lit
++ = (val
>> 24);
3738 case BFD_RELOC_Z80_16_BE
: /* Z80N PUSH nn instruction produce this. */
3739 *p_lit
++ = val
>> 8;
3744 printf (_("md_apply_fix: unknown reloc type 0x%x\n"), fixP
->fx_r_type
);
3749 /* GAS will call this to generate a reloc. GAS will pass the
3750 resulting reloc to `bfd_install_relocation'. This currently works
3751 poorly, as `bfd_install_relocation' often does the wrong thing, and
3752 instances of `tc_gen_reloc' have been written to work around the
3753 problems, which in turns makes it difficult to fix
3754 `bfd_install_relocation'. */
3756 /* If while processing a fixup, a reloc really
3757 needs to be created then it is done here. */
3760 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
3764 if (fixp
->fx_subsy
!= NULL
)
3766 as_bad_where (fixp
->fx_file
, fixp
->fx_line
, _("expression too complex"));
3770 reloc
= XNEW (arelent
);
3771 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3772 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3773 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3774 reloc
->addend
= fixp
->fx_offset
;
3775 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3776 if (reloc
->howto
== NULL
)
3778 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3779 _("reloc %d not supported by object file format"),
3780 (int) fixp
->fx_r_type
);
3784 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3785 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3786 reloc
->address
= fixp
->fx_offset
;
3792 z80_tc_label_is_local (const char *name
)
3796 if (local_label_prefix
== NULL
)
3798 for (p
= local_label_prefix
, n
= name
; *p
&& *n
&& *n
== *p
; p
++, n
++)
3803 /* Parse floating point number from string and compute mantissa and
3804 exponent. Mantissa is normalized.
3806 #define EXP_MIN -0x10000
3807 #define EXP_MAX 0x10000
3809 str_to_broken_float (bfd_boolean
*signP
, bfd_uint64_t
*mantissaP
, int *expP
)
3813 bfd_uint64_t mantissa
= 0;
3817 p
= (char*)skip_space (input_line_pointer
);
3820 if (sign
|| *p
== '+')
3822 if (strncasecmp (p
, "NaN", 3) == 0)
3826 input_line_pointer
= p
+ 3;
3829 if (strncasecmp (p
, "inf", 3) == 0)
3831 *mantissaP
= 1ull << 63;
3833 input_line_pointer
= p
+ 3;
3836 for (; ISDIGIT (*p
); ++p
)
3844 mantissa
= mantissa
* 10 + (*p
- '0');
3846 /* skip non-significant digits */
3847 for (; ISDIGIT (*p
); ++p
)
3853 if (!exponent
) /* If no precission overflow. */
3855 for (; ISDIGIT (*p
); ++p
, --exponent
)
3863 mantissa
= mantissa
* 10 + (*p
- '0');
3866 for (; ISDIGIT (*p
); ++p
)
3869 if (*p
== 'e' || *p
== 'E')
3875 if (es
|| *p
== '+')
3877 for (; ISDIGIT (*p
); ++p
)
3880 t
= t
* 10 + (*p
- '0');
3882 exponent
+= (es
) ? -t
: t
;
3884 if (ISALNUM (*p
) || *p
== '.')
3886 input_line_pointer
= p
;
3889 *mantissaP
= 1ull << 63;
3891 return 1; /* result is 0 */
3894 for (; mantissa
<= ~0ull/10; --exponent
)
3896 /* Now we have sign, mantissa, and signed decimal exponent
3897 need to recompute to binary exponent. */
3898 for (i
= 64; exponent
> 0; --exponent
)
3900 /* be sure that no integer overflow */
3901 while (mantissa
> ~0ull/10)
3908 for (; exponent
< 0; ++exponent
)
3910 while (!(mantissa
>> 63))
3918 for (; !(mantissa
>> 63); --i
)
3920 *mantissaP
= mantissa
;
3926 str_to_zeda32(char *litP
, int *sizeP
)
3928 bfd_uint64_t mantissa
;
3934 if (!str_to_broken_float (&sign
, &mantissa
, &exponent
))
3935 return _("invalid syntax");
3936 /* I do not know why decrement is needed */
3938 /* shift by 39 bits right keeping 25 bit mantissa for rounding */
3942 /* make 24 bit mantissa */
3944 /* check for overflow */
3951 if (exponent
< -127)
3956 else if (exponent
> 127)
3959 mantissa
= sign
? 0xc00000 : 0x400000;
3961 else if (mantissa
== 0)
3964 mantissa
= 0x200000;
3967 mantissa
&= (1ull << 23) - 1;
3968 for (i
= 0; i
< 24; i
+= 8)
3969 *litP
++ = (char)(mantissa
>> i
);
3970 *litP
= (char)(0x80 + exponent
);
3975 Math48 by Anders Hejlsberg support.
3976 Mantissa is 39 bits wide, exponent 8 bit wide.
3979 bit 46-8: normalized mantissa (bits 38-0, bit39 assumed to be 1)
3980 bit 7-0: exponent+128 (0 - value is null)
3981 MIN: 2.938735877e-39
3982 MAX: 1.701411835e+38
3985 str_to_float48(char *litP
, int *sizeP
)
3987 bfd_uint64_t mantissa
;
3993 if (!str_to_broken_float (&sign
, &mantissa
, &exponent
))
3994 return _("invalid syntax");
3995 /* shift by 23 bits right keeping 41 bit mantissa for rounding */
3999 /* make 40 bit mantissa */
4001 /* check for overflow */
4007 if (exponent
< -127)
4009 memset (litP
, 0, 6);
4013 return _("overflow");
4015 mantissa
&= (1ull << 39) - 1;
4016 *litP
++ = (char)(0x80 + exponent
);
4017 for (i
= 0; i
< 40; i
+= 8)
4018 *litP
++ = (char)(mantissa
>> i
);
4023 str_to_ieee754_h(char *litP
, int *sizeP
)
4025 return ieee_md_atof ('h', litP
, sizeP
, FALSE
);
4029 str_to_ieee754_s(char *litP
, int *sizeP
)
4031 return ieee_md_atof ('s', litP
, sizeP
, FALSE
);
4035 str_to_ieee754_d(char *litP
, int *sizeP
)
4037 return ieee_md_atof ('d', litP
, sizeP
, FALSE
);
4040 #ifdef TARGET_USE_CFIPOP
4041 /* Initialize the DWARF-2 unwind information for this procedure. */
4043 z80_tc_frame_initial_instructions (void)
4045 static int sp_regno
= -1;
4048 sp_regno
= z80_tc_regname_to_dw2regnum ("sp");
4050 cfi_add_CFA_def_cfa (sp_regno
, 0);
4054 z80_tc_regname_to_dw2regnum (const char *regname
)
4056 static const char *regs
[] =
4057 { /* same registers as for GDB */
4058 "af", "bc", "de", "hl",
4059 "sp", "pc", "ix", "iy",
4060 "af_", "bc_", "de_", "hl_",
4065 for (i
= 0; i
< ARRAY_SIZE(regs
); ++i
)
4066 if (!strcasecmp (regs
[i
], regname
))
4073 /* Implement DWARF2_ADDR_SIZE. */
4075 z80_dwarf2_addr_size (const bfd
*abfd
)
4077 switch (bfd_get_mach (abfd
))
4079 case bfd_mach_ez80_adl
: