gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2014 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a53},
  59 @code{cortex-a57},
  60 and
  61 @code{xgene-1}.
  62 The special name @code{all} may be used to allow the assembler to accept
  63 instructions valid for any supported processor, including all optional
  64 extensions.
  65
  66 In addition to the basic instruction set, the assembler can be told to
  67 accept, or restrict, various extension mnemonics that extend the
  68 processor.  @xref{AArch64 Extensions}.
  69
  70 If some implementations of a particular processor can have an
  71 extension, then then those extensions are automatically enabled.
  72 Consequently, you will not normally have to specify any additional
  73 extensions.
  74
  75 @cindex @option{-march=} command line option, AArch64
  76 @item -march=@var{architecture}[+@var{extension}@dots{}]
  77 This option specifies the target architecture.  The assembler will
  78 issue an error message if an attempt is made to assemble an
  79 instruction which will not execute on the target architecture.  The
  80 only value for @var{architecture} is @code{armv8-a}.
  81
  82 If both @option{-mcpu} and @option{-march} are specified, the
  83 assembler will use the setting for @option{-mcpu}.  If neither are
  84 specified, the assembler will default to @option{-mcpu=all}.
  85
  86 The architecture option can be extended with the same instruction set
  87 extension options as the @option{-mcpu} option.  Unlike
  88 @option{-mcpu}, extensions are not always enabled by default,
  89 @xref{AArch64 Extensions}.
  90
  91 @cindex @code{-mverbose-error} command line option, AArch64
  92 @item -mverbose-error
  93 This option enables verbose error messages for AArch64 gas.  This option
  94 is enabled by default.
  95
  96 @cindex @code{-mno-verbose-error} command line option, AArch64
  97 @item -mno-verbose-error
  98 This option disables verbose error messages in AArch64 gas.
  99
 100 @end table
 101 @c man end
 102
 103 @node AArch64 Extensions
 104 @section Architecture Extensions
 105
 106 The table below lists the permitted architecture extensions that are
 107 supported by the assembler and the conditions under which they are
 108 automatically enabled.
 109
 110 Multiple extensions may be specified, separated by a @code{+}.
 111 Extension mnemonics may also be removed from those the assembler
 112 accepts.  This is done by prepending @code{no} to the option that adds
 113 the extension.  Extensions that are removed must be listed after all
 114 extensions that have been added.
 115
 116 Enabling an extension that requires other extensions will
 117 automatically cause those extensions to be enabled.  Similarly,
 118 disabling an extension that is required by other extensions will
 119 automatically cause those extensions to be disabled.
 120
 121 @multitable @columnfractions .12 .17 .17 .54
 122 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 123  @tab Description
 124 @item @code{crc} @tab ARMv8-A @tab No
 125  @tab Enable CRC instructions.
 126 @item @code{crypto} @tab ARMv8-A @tab No
 127  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 128 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 129  @tab Enable floating-point extensions.
 130 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 131  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 132 @end multitable
 133
 134 @node AArch64 Syntax
 135 @section Syntax
 136 @menu
 137 * AArch64-Chars::                Special Characters
 138 * AArch64-Regs::                 Register Names
 139 * AArch64-Relocations::      Relocations
 140 @end menu
 141
 142 @node AArch64-Chars
 143 @subsection Special Characters
 144
 145 @cindex line comment character, AArch64
 146 @cindex AArch64 line comment character
 147 The presence of a @samp{//} on a line indicates the start of a comment
 148 that extends to the end of the current line.  If a @samp{#} appears as
 149 the first character of a line, the whole line is treated as a comment.
 150
 151 @cindex line separator, AArch64
 152 @cindex statement separator, AArch64
 153 @cindex AArch64 line separator
 154 The @samp{;} character can be used instead of a newline to separate
 155 statements.
 156
 157 @cindex immediate character, AArch64
 158 @cindex AArch64 immediate character
 159 The @samp{#} can be optionally used to indicate immediate operands.
 160
 161 @node AArch64-Regs
 162 @subsection Register Names
 163
 164 @cindex AArch64 register names
 165 @cindex register names, AArch64
 166 Please refer to the section @samp{4.4 Register Names} of
 167 @samp{ARMv8 Instruction Set Overview}, which is available at
 168 @uref{http://infocenter.arm.com}.
 169
 170 @node AArch64-Relocations
 171 @subsection Relocations
 172
 173 @cindex relocations, AArch64
 174 @cindex AArch64 relocations
 175 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 176 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 177 by prefixing the label with @samp{#:abs_g2:} etc.
 178 For example to load the 48-bit absolute address of @var{foo} into x0:
 179
 180 @smallexample
 181         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 182         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 183         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 184 @end smallexample
 185
 186 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 187 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 188 instructions can be generated by prefixing the label with
 189 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 190
 191 For example to use 33-bit (+/-4GB) pc-relative addressing to
 192 load the address of @var{foo} into x0:
 193
 194 @smallexample
 195         adrp x0, :pg_hi21:foo
 196         add  x0, x0, #:lo12:foo
 197 @end smallexample
 198
 199 Or to load the value of @var{foo} into x0:
 200
 201 @smallexample
 202         adrp x0, :pg_hi21:foo
 203         ldr  x0, [x0, #:lo12:foo]
 204 @end smallexample
 205
 206 Note that @samp{:pg_hi21:} is optional.
 207
 208 @smallexample
 209         adrp x0, foo
 210 @end smallexample
 211
 212 is equivalent to
 213
 214 @smallexample
 215         adrp x0, :pg_hi21:foo
 216 @end smallexample
 217
 218 @node AArch64 Floating Point
 219 @section Floating Point
 220
 221 @cindex floating point, AArch64 (@sc{ieee})
 222 @cindex AArch64 floating point (@sc{ieee})
 223 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 224
 225 @node AArch64 Directives
 226 @section AArch64 Machine Directives
 227
 228 @cindex machine directives, AArch64
 229 @cindex AArch64 machine directives
 230 @table @code
 231
 232 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 233 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 234
 235 @cindex @code{.bss} directive, AArch64
 236 @item .bss
 237 This directive switches to the @code{.bss} section.
 238
 239 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 240 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 241 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 242 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 243 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 244 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 245 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 246 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 247 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 248 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 249
 250 @cindex @code{.ltorg} directive, AArch64
 251 @item .ltorg
 252 This directive causes the current contents of the literal pool to be
 253 dumped into the current section (which is assumed to be the .text
 254 section) at the current location (aligned to a word boundary).
 255 GAS maintains a separate literal pool for each section and each
 256 sub-section.  The @code{.ltorg} directive will only affect the literal
 257 pool of the current section and sub-section.  At the end of assembly
 258 all remaining, un-empty literal pools will automatically be dumped.
 259
 260 Note - older versions of GAS would dump the current literal
 261 pool any time a section change occurred.  This is no longer done, since
 262 it prevents accurate control of the placement of literal pools.
 263
 264 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 265
 266 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 267 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 268
 269 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 270
 271 @cindex @code{.pool} directive, AArch64
 272 @item .pool
 273 This is a synonym for .ltorg.
 274
 275 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 276 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 277
 278 @cindex @code{.req} directive, AArch64
 279 @item @var{name} .req @var{register name}
 280 This creates an alias for @var{register name} called @var{name}.  For
 281 example:
 282
 283 @smallexample
 284         foo .req w0
 285 @end smallexample
 286
 287 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 288
 289 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 290
 291 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 292
 293 @cindex @code{.unreq} directive, AArch64
 294 @item .unreq @var{alias-name}
 295 This undefines a register alias which was previously defined using the
 296 @code{req} directive.  For example:
 297
 298 @smallexample
 299         foo .req w0
 300         .unreq foo
 301 @end smallexample
 302
 303 An error occurs if the name is undefined.  Note - this pseudo op can
 304 be used to delete builtin in register name aliases (eg 'w0').  This
 305 should only be done if it is really necessary.
 306
 307 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 308
 309 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 310 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 311 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 312 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 313
 314 @end table
 315
 316 @node AArch64 Opcodes
 317 @section Opcodes
 318
 319 @cindex AArch64 opcodes
 320 @cindex opcodes for AArch64
 321 GAS implements all the standard AArch64 opcodes.  It also
 322 implements several pseudo opcodes, including several synthetic load
 323 instructions.
 324
 325 @table @code
 326
 327 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 328 @item LDR =
 329 @smallexample
 330   ldr <register> , =<expression>
 331 @end smallexample
 332
 333 The constant expression will be placed into the nearest literal pool (if it not
 334 already there) and a PC-relative LDR instruction will be generated.
 335
 336 @end table
 337
 338 For more information on the AArch64 instruction set and assembly language
 339 notation, see @samp{ARMv8 Instruction Set Overview} available at
 340 @uref{http://infocenter.arm.com}.
 341
 342
 343 @node AArch64 Mapping Symbols
 344 @section Mapping Symbols
 345
 346 The AArch64 ELF specification requires that special symbols be inserted
 347 into object files to mark certain features:
 348
 349 @table @code
 350
 351 @cindex @code{$x}
 352 @item $x
 353 At the start of a region of code containing AArch64 instructions.
 354
 355 @cindex @code{$d}
 356 @item $d
 357 At the start of a region of data.
 358
 359 @end table