gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2017 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a55},
  61 @code{cortex-a57},
  62 @code{cortex-a72},
  63 @code{cortex-a73},
  64 @code{cortex-a75},
  65 @code{exynos-m1},
  66 @code{falkor},
  67 @code{qdf24xx},
  68 @code{saphira},
  69 @code{thunderx},
  70 @code{vulcan},
  71 @code{xgene1}
  72 and
  73 @code{xgene2}.
  74 The special name @code{all} may be used to allow the assembler to accept
  75 instructions valid for any supported processor, including all optional
  76 extensions.
  77
  78 In addition to the basic instruction set, the assembler can be told to
  79 accept, or restrict, various extension mnemonics that extend the
  80 processor.  @xref{AArch64 Extensions}.
  81
  82 If some implementations of a particular processor can have an
  83 extension, then then those extensions are automatically enabled.
  84 Consequently, you will not normally have to specify any additional
  85 extensions.
  86
  87 @cindex @option{-march=} command line option, AArch64
  88 @item -march=@var{architecture}[+@var{extension}@dots{}]
  89 This option specifies the target architecture.  The assembler will
  90 issue an error message if an attempt is made to assemble an
  91 instruction which will not execute on the target architecture.  The
  92 following architecture names are recognized: @code{armv8-a},
  93 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a} and @code{armv8.4-a}.
  94
  95 If both @option{-mcpu} and @option{-march} are specified, the
  96 assembler will use the setting for @option{-mcpu}.  If neither are
  97 specified, the assembler will default to @option{-mcpu=all}.
  98
  99 The architecture option can be extended with the same instruction set
 100 extension options as the @option{-mcpu} option.  Unlike
 101 @option{-mcpu}, extensions are not always enabled by default,
 102 @xref{AArch64 Extensions}.
 103
 104 @cindex @code{-mverbose-error} command line option, AArch64
 105 @item -mverbose-error
 106 This option enables verbose error messages for AArch64 gas.  This option
 107 is enabled by default.
 108
 109 @cindex @code{-mno-verbose-error} command line option, AArch64
 110 @item -mno-verbose-error
 111 This option disables verbose error messages in AArch64 gas.
 112
 113 @end table
 114 @c man end
 115
 116 @node AArch64 Extensions
 117 @section Architecture Extensions
 118
 119 The table below lists the permitted architecture extensions that are
 120 supported by the assembler and the conditions under which they are
 121 automatically enabled.
 122
 123 Multiple extensions may be specified, separated by a @code{+}.
 124 Extension mnemonics may also be removed from those the assembler
 125 accepts.  This is done by prepending @code{no} to the option that adds
 126 the extension.  Extensions that are removed must be listed after all
 127 extensions that have been added.
 128
 129 Enabling an extension that requires other extensions will
 130 automatically cause those extensions to be enabled.  Similarly,
 131 disabling an extension that is required by other extensions will
 132 automatically cause those extensions to be disabled.
 133
 134 @multitable @columnfractions .12 .17 .17 .54
 135 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 136  @tab Description
 137 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 138  @tab Enable the complex number SIMD extensions.  This implies
 139  @code{fp16} and @code{simd}.
 140 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 141  @tab Enable CRC instructions.
 142 @item @code{crypto} @tab ARMv8-A @tab No
 143  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 144 @item @code{aes} @tab ARMv8-A @tab No
 145  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 146 @item @code{sha2} @tab ARMv8-A @tab No
 147  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 148 @item @code{sha3} @tab ARMv8.2-A @tab No
 149  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 150 @item @code{sm4} @tab ARMv8.2-A @tab No
 151  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 152 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 153  @tab Enable floating-point extensions.
 154 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 155  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 156  @code{fp}.
 157 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 158  @tab Enable Limited Ordering Regions extensions.
 159 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 160  @tab Enable Large System extensions.
 161 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 162  @tab Enable Privileged Access Never support.
 163 @item @code{profile} @tab ARMv8.2-A @tab No
 164  @tab Enable statistical profiling extensions.
 165 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 166  @tab Enable the Reliability, Availability and Serviceability
 167  extension.
 168 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 169  @tab Enable the weak release consistency extension.
 170 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 171  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 172 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 173  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 174 @item @code{sve} @tab ARMv8.2-A @tab No
 175  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 176  @code{simd} and @code{compnum}.
 177 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 178  @tab Enable the Dot Product extension.  This implies @code{simd}.
 179 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 180  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 181  This implies @code{fp16}.
 182 @end multitable
 183
 184 @node AArch64 Syntax
 185 @section Syntax
 186 @menu
 187 * AArch64-Chars::                Special Characters
 188 * AArch64-Regs::                 Register Names
 189 * AArch64-Relocations::      Relocations
 190 @end menu
 191
 192 @node AArch64-Chars
 193 @subsection Special Characters
 194
 195 @cindex line comment character, AArch64
 196 @cindex AArch64 line comment character
 197 The presence of a @samp{//} on a line indicates the start of a comment
 198 that extends to the end of the current line.  If a @samp{#} appears as
 199 the first character of a line, the whole line is treated as a comment.
 200
 201 @cindex line separator, AArch64
 202 @cindex statement separator, AArch64
 203 @cindex AArch64 line separator
 204 The @samp{;} character can be used instead of a newline to separate
 205 statements.
 206
 207 @cindex immediate character, AArch64
 208 @cindex AArch64 immediate character
 209 The @samp{#} can be optionally used to indicate immediate operands.
 210
 211 @node AArch64-Regs
 212 @subsection Register Names
 213
 214 @cindex AArch64 register names
 215 @cindex register names, AArch64
 216 Please refer to the section @samp{4.4 Register Names} of
 217 @samp{ARMv8 Instruction Set Overview}, which is available at
 218 @uref{http://infocenter.arm.com}.
 219
 220 @node AArch64-Relocations
 221 @subsection Relocations
 222
 223 @cindex relocations, AArch64
 224 @cindex AArch64 relocations
 225 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 226 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 227 by prefixing the label with @samp{#:abs_g2:} etc.
 228 For example to load the 48-bit absolute address of @var{foo} into x0:
 229
 230 @smallexample
 231         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 232         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 233         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 234 @end smallexample
 235
 236 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 237 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 238 instructions can be generated by prefixing the label with
 239 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 240
 241 For example to use 33-bit (+/-4GB) pc-relative addressing to
 242 load the address of @var{foo} into x0:
 243
 244 @smallexample
 245         adrp x0, :pg_hi21:foo
 246         add  x0, x0, #:lo12:foo
 247 @end smallexample
 248
 249 Or to load the value of @var{foo} into x0:
 250
 251 @smallexample
 252         adrp x0, :pg_hi21:foo
 253         ldr  x0, [x0, #:lo12:foo]
 254 @end smallexample
 255
 256 Note that @samp{:pg_hi21:} is optional.
 257
 258 @smallexample
 259         adrp x0, foo
 260 @end smallexample
 261
 262 is equivalent to
 263
 264 @smallexample
 265         adrp x0, :pg_hi21:foo
 266 @end smallexample
 267
 268 @node AArch64 Floating Point
 269 @section Floating Point
 270
 271 @cindex floating point, AArch64 (@sc{ieee})
 272 @cindex AArch64 floating point (@sc{ieee})
 273 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 274
 275 @node AArch64 Directives
 276 @section AArch64 Machine Directives
 277
 278 @cindex machine directives, AArch64
 279 @cindex AArch64 machine directives
 280 @table @code
 281
 282 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 283
 284 @cindex @code{.arch} directive, AArch64
 285 @item .arch @var{name}
 286 Select the target architecture.  Valid values for @var{name} are the same as
 287 for the @option{-march} commandline option.
 288
 289 Specifying @code{.arch} clears any previously selected architecture
 290 extensions.
 291
 292 @cindex @code{.arch_extension} directive, AArch64
 293 @item .arch_extension @var{name}
 294 Add or remove an architecture extension to the target architecture.  Valid
 295 values for @var{name} are the same as those accepted as architectural
 296 extensions by the @option{-mcpu} commandline option.
 297
 298 @code{.arch_extension} may be used multiple times to add or remove extensions
 299 incrementally to the architecture being compiled for.
 300
 301 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 302
 303 @cindex @code{.bss} directive, AArch64
 304 @item .bss
 305 This directive switches to the @code{.bss} section.
 306
 307 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 308
 309 @cindex @code{.cpu} directive, AArch64
 310 @item .cpu @var{name}
 311 Set the target processor.  Valid values for @var{name} are the same as
 312 those accepted by the @option{-mcpu=} command line option.
 313
 314 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 315
 316 @cindex @code{.dword} directive, AArch64
 317 @item .dword @var{expressions}
 318 The @code{.dword} directive produces 64 bit values.
 319
 320 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 321
 322 @cindex @code{.even} directive, AArch64
 323 @item .even
 324 The @code{.even} directive aligns the output on the next even byte
 325 boundary.
 326
 327 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 328 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 329 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 330 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 331
 332 @cindex @code{.inst} directive, AArch64
 333 @item .inst @var{expressions}
 334 Inserts the expressions into the output as if they were instructions,
 335 rather than data.
 336
 337 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 338 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 339 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 340
 341 @cindex @code{.ltorg} directive, AArch64
 342 @item .ltorg
 343 This directive causes the current contents of the literal pool to be
 344 dumped into the current section (which is assumed to be the .text
 345 section) at the current location (aligned to a word boundary).
 346 GAS maintains a separate literal pool for each section and each
 347 sub-section.  The @code{.ltorg} directive will only affect the literal
 348 pool of the current section and sub-section.  At the end of assembly
 349 all remaining, un-empty literal pools will automatically be dumped.
 350
 351 Note - older versions of GAS would dump the current literal
 352 pool any time a section change occurred.  This is no longer done, since
 353 it prevents accurate control of the placement of literal pools.
 354
 355 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 356
 357 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 358 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 359
 360 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 361
 362 @cindex @code{.pool} directive, AArch64
 363 @item .pool
 364 This is a synonym for .ltorg.
 365
 366 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 367 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 368
 369 @cindex @code{.req} directive, AArch64
 370 @item @var{name} .req @var{register name}
 371 This creates an alias for @var{register name} called @var{name}.  For
 372 example:
 373
 374 @smallexample
 375         foo .req w0
 376 @end smallexample
 377
 378 ip0, ip1, lr and fp are automatically defined to
 379 alias to X16, X17, X30 and X29 respectively.
 380
 381 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 382
 383 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 384
 385 @cindex @code{.tlsdescadd} directive, AArch64
 386 @item   @code{.tlsdescadd}
 387 Emits a TLSDESC_ADD reloc on the next instruction.
 388
 389 @cindex @code{.tlsdesccall} directive, AArch64
 390 @item   @code{.tlsdesccall}
 391 Emits a TLSDESC_CALL reloc on the next instruction.
 392
 393 @cindex @code{.tlsdescldr} directive, AArch64
 394 @item   @code{.tlsdescldr}
 395 Emits a TLSDESC_LDR reloc on the next instruction.
 396
 397 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 398
 399 @cindex @code{.unreq} directive, AArch64
 400 @item .unreq @var{alias-name}
 401 This undefines a register alias which was previously defined using the
 402 @code{req} directive.  For example:
 403
 404 @smallexample
 405         foo .req w0
 406         .unreq foo
 407 @end smallexample
 408
 409 An error occurs if the name is undefined.  Note - this pseudo op can
 410 be used to delete builtin in register name aliases (eg 'w0').  This
 411 should only be done if it is really necessary.
 412
 413 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 414
 415 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 416 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 417
 418 @cindex @code{.xword} directive, AArch64
 419 @item .xword @var{expressions}
 420 The @code{.xword} directive produces 64 bit values.  This is the same
 421 as the @code{.dword} directive.
 422
 423 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 424 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 425
 426 @end table
 427
 428 @node AArch64 Opcodes
 429 @section Opcodes
 430
 431 @cindex AArch64 opcodes
 432 @cindex opcodes for AArch64
 433 GAS implements all the standard AArch64 opcodes.  It also
 434 implements several pseudo opcodes, including several synthetic load
 435 instructions.
 436
 437 @table @code
 438
 439 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 440 @item LDR =
 441 @smallexample
 442   ldr <register> , =<expression>
 443 @end smallexample
 444
 445 The constant expression will be placed into the nearest literal pool (if it not
 446 already there) and a PC-relative LDR instruction will be generated.
 447
 448 @end table
 449
 450 For more information on the AArch64 instruction set and assembly language
 451 notation, see @samp{ARMv8 Instruction Set Overview} available at
 452 @uref{http://infocenter.arm.com}.
 453
 454
 455 @node AArch64 Mapping Symbols
 456 @section Mapping Symbols
 457
 458 The AArch64 ELF specification requires that special symbols be inserted
 459 into object files to mark certain features:
 460
 461 @table @code
 462
 463 @cindex @code{$x}
 464 @item $x
 465 At the start of a region of code containing AArch64 instructions.
 466
 467 @cindex @code{$d}
 468 @item $d
 469 At the start of a region of data.
 470
 471 @end table