gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2016 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a57},
  61 @code{cortex-a72},
  62 @code{exynos-m1},
  63 @code{qdf24xx},
  64 @code{thunderx},
  65 @code{xgene1}
  66 and
  67 @code{xgene2}.
  68 The special name @code{all} may be used to allow the assembler to accept
  69 instructions valid for any supported processor, including all optional
  70 extensions.
  71
  72 In addition to the basic instruction set, the assembler can be told to
  73 accept, or restrict, various extension mnemonics that extend the
  74 processor.  @xref{AArch64 Extensions}.
  75
  76 If some implementations of a particular processor can have an
  77 extension, then then those extensions are automatically enabled.
  78 Consequently, you will not normally have to specify any additional
  79 extensions.
  80
  81 @cindex @option{-march=} command line option, AArch64
  82 @item -march=@var{architecture}[+@var{extension}@dots{}]
  83 This option specifies the target architecture.  The assembler will
  84 issue an error message if an attempt is made to assemble an
  85 instruction which will not execute on the target architecture.  The
  86 following architecture names are recognized: @code{armv8-a},
  87 @code{armv8.1-a} and @code{armv8.2-a}.
  88
  89 If both @option{-mcpu} and @option{-march} are specified, the
  90 assembler will use the setting for @option{-mcpu}.  If neither are
  91 specified, the assembler will default to @option{-mcpu=all}.
  92
  93 The architecture option can be extended with the same instruction set
  94 extension options as the @option{-mcpu} option.  Unlike
  95 @option{-mcpu}, extensions are not always enabled by default,
  96 @xref{AArch64 Extensions}.
  97
  98 @cindex @code{-mverbose-error} command line option, AArch64
  99 @item -mverbose-error
 100 This option enables verbose error messages for AArch64 gas.  This option
 101 is enabled by default.
 102
 103 @cindex @code{-mno-verbose-error} command line option, AArch64
 104 @item -mno-verbose-error
 105 This option disables verbose error messages in AArch64 gas.
 106
 107 @end table
 108 @c man end
 109
 110 @node AArch64 Extensions
 111 @section Architecture Extensions
 112
 113 The table below lists the permitted architecture extensions that are
 114 supported by the assembler and the conditions under which they are
 115 automatically enabled.
 116
 117 Multiple extensions may be specified, separated by a @code{+}.
 118 Extension mnemonics may also be removed from those the assembler
 119 accepts.  This is done by prepending @code{no} to the option that adds
 120 the extension.  Extensions that are removed must be listed after all
 121 extensions that have been added.
 122
 123 Enabling an extension that requires other extensions will
 124 automatically cause those extensions to be enabled.  Similarly,
 125 disabling an extension that is required by other extensions will
 126 automatically cause those extensions to be disabled.
 127
 128 @multitable @columnfractions .12 .17 .17 .54
 129 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 130  @tab Description
 131 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 132  @tab Enable CRC instructions.
 133 @item @code{crypto} @tab ARMv8-A @tab No
 134  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 135 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 136  @tab Enable floating-point extensions.
 137 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 138  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 139 @item @code{pan} @tab ARMv8-A @tab ARMv8-A or later
 140  @tab Enable Privileged Access Never support.
 141 @item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
 142  @tab Enable Limited Ordering Regions extensions.
 143 @item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later
 144  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 145 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 146  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 147  @code{fp}.
 148 @item @code{profile} @tab ARMv8.2-A @tab No
 149  @tab Enable statistical profiling extensions.
 150 @end multitable
 151
 152 @node AArch64 Syntax
 153 @section Syntax
 154 @menu
 155 * AArch64-Chars::                Special Characters
 156 * AArch64-Regs::                 Register Names
 157 * AArch64-Relocations::      Relocations
 158 @end menu
 159
 160 @node AArch64-Chars
 161 @subsection Special Characters
 162
 163 @cindex line comment character, AArch64
 164 @cindex AArch64 line comment character
 165 The presence of a @samp{//} on a line indicates the start of a comment
 166 that extends to the end of the current line.  If a @samp{#} appears as
 167 the first character of a line, the whole line is treated as a comment.
 168
 169 @cindex line separator, AArch64
 170 @cindex statement separator, AArch64
 171 @cindex AArch64 line separator
 172 The @samp{;} character can be used instead of a newline to separate
 173 statements.
 174
 175 @cindex immediate character, AArch64
 176 @cindex AArch64 immediate character
 177 The @samp{#} can be optionally used to indicate immediate operands.
 178
 179 @node AArch64-Regs
 180 @subsection Register Names
 181
 182 @cindex AArch64 register names
 183 @cindex register names, AArch64
 184 Please refer to the section @samp{4.4 Register Names} of
 185 @samp{ARMv8 Instruction Set Overview}, which is available at
 186 @uref{http://infocenter.arm.com}.
 187
 188 @node AArch64-Relocations
 189 @subsection Relocations
 190
 191 @cindex relocations, AArch64
 192 @cindex AArch64 relocations
 193 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 194 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 195 by prefixing the label with @samp{#:abs_g2:} etc.
 196 For example to load the 48-bit absolute address of @var{foo} into x0:
 197
 198 @smallexample
 199         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 200         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 201         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 202 @end smallexample
 203
 204 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 205 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 206 instructions can be generated by prefixing the label with
 207 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 208
 209 For example to use 33-bit (+/-4GB) pc-relative addressing to
 210 load the address of @var{foo} into x0:
 211
 212 @smallexample
 213         adrp x0, :pg_hi21:foo
 214         add  x0, x0, #:lo12:foo
 215 @end smallexample
 216
 217 Or to load the value of @var{foo} into x0:
 218
 219 @smallexample
 220         adrp x0, :pg_hi21:foo
 221         ldr  x0, [x0, #:lo12:foo]
 222 @end smallexample
 223
 224 Note that @samp{:pg_hi21:} is optional.
 225
 226 @smallexample
 227         adrp x0, foo
 228 @end smallexample
 229
 230 is equivalent to
 231
 232 @smallexample
 233         adrp x0, :pg_hi21:foo
 234 @end smallexample
 235
 236 @node AArch64 Floating Point
 237 @section Floating Point
 238
 239 @cindex floating point, AArch64 (@sc{ieee})
 240 @cindex AArch64 floating point (@sc{ieee})
 241 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 242
 243 @node AArch64 Directives
 244 @section AArch64 Machine Directives
 245
 246 @cindex machine directives, AArch64
 247 @cindex AArch64 machine directives
 248 @table @code
 249
 250 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 251
 252 @cindex @code{.arch} directive, AArch64
 253 @item .arch @var{name}
 254 Select the target architecture.  Valid values for @var{name} are the same as
 255 for the @option{-march} commandline option.
 256
 257 Specifying @code{.arch} clears any previously selected architecture
 258 extensions.
 259
 260 @cindex @code{.arch_extension} directive, AArch64
 261 @item .arch_extension @var{name}
 262 Add or remove an architecture extension to the target architecture.  Valid
 263 values for @var{name} are the same as those accepted as architectural
 264 extensions by the @option{-mcpu} commandline option.
 265
 266 @code{.arch_extension} may be used multiple times to add or remove extensions
 267 incrementally to the architecture being compiled for.
 268
 269 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 270
 271 @cindex @code{.bss} directive, AArch64
 272 @item .bss
 273 This directive switches to the @code{.bss} section.
 274
 275 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 276
 277 @cindex @code{.cpu} directive, AArch64
 278 @item .cpu @var{name}
 279 Set the target processor.  Valid values for @var{name} are the same as
 280 those accepted by the @option{-mcpu=} command line option.
 281
 282 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 283
 284 @cindex @code{.dword} directive, AArch64
 285 @item .dword @var{expressions}
 286 The @code{.dword} directive produces 64 bit values.
 287
 288 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 289
 290 @cindex @code{.even} directive, AArch64
 291 @item .even
 292 The @code{.even} directive aligns the output on the next even byte
 293 boundary.
 294
 295 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 296 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 297 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 298 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 299
 300 @cindex @code{.inst} directive, AArch64
 301 @item .inst @var{expressions}
 302 Inserts the expressions into the output as if they were instructions,
 303 rather than data.
 304
 305 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 306 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 307 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 308
 309 @cindex @code{.ltorg} directive, AArch64
 310 @item .ltorg
 311 This directive causes the current contents of the literal pool to be
 312 dumped into the current section (which is assumed to be the .text
 313 section) at the current location (aligned to a word boundary).
 314 GAS maintains a separate literal pool for each section and each
 315 sub-section.  The @code{.ltorg} directive will only affect the literal
 316 pool of the current section and sub-section.  At the end of assembly
 317 all remaining, un-empty literal pools will automatically be dumped.
 318
 319 Note - older versions of GAS would dump the current literal
 320 pool any time a section change occurred.  This is no longer done, since
 321 it prevents accurate control of the placement of literal pools.
 322
 323 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 324
 325 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 326 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 327
 328 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 329
 330 @cindex @code{.pool} directive, AArch64
 331 @item .pool
 332 This is a synonym for .ltorg.
 333
 334 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 335 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 336
 337 @cindex @code{.req} directive, AArch64
 338 @item @var{name} .req @var{register name}
 339 This creates an alias for @var{register name} called @var{name}.  For
 340 example:
 341
 342 @smallexample
 343         foo .req w0
 344 @end smallexample
 345
 346 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 347
 348 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 349
 350 @cindex @code{.tlsdescadd} directive, AArch64
 351 @item   @code{.tlsdescadd}
 352 Emits a TLSDESC_ADD reloc on the next instruction.
 353
 354 @cindex @code{.tlsdesccall} directive, AArch64
 355 @item   @code{.tlsdesccall}
 356 Emits a TLSDESC_CALL reloc on the next instruction.
 357
 358 @cindex @code{.tlsdescldr} directive, AArch64
 359 @item   @code{.tlsdescldr}
 360 Emits a TLSDESC_LDR reloc on the next instruction.
 361
 362 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 363
 364 @cindex @code{.unreq} directive, AArch64
 365 @item .unreq @var{alias-name}
 366 This undefines a register alias which was previously defined using the
 367 @code{req} directive.  For example:
 368
 369 @smallexample
 370         foo .req w0
 371         .unreq foo
 372 @end smallexample
 373
 374 An error occurs if the name is undefined.  Note - this pseudo op can
 375 be used to delete builtin in register name aliases (eg 'w0').  This
 376 should only be done if it is really necessary.
 377
 378 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 379
 380 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 381 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 382
 383 @cindex @code{.xword} directive, AArch64
 384 @item .xword @var{expressions}
 385 The @code{.xword} directive produces 64 bit values.  This is the same
 386 as the @code{.dword} directive.
 387
 388 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 389 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 390
 391 @end table
 392
 393 @node AArch64 Opcodes
 394 @section Opcodes
 395
 396 @cindex AArch64 opcodes
 397 @cindex opcodes for AArch64
 398 GAS implements all the standard AArch64 opcodes.  It also
 399 implements several pseudo opcodes, including several synthetic load
 400 instructions.
 401
 402 @table @code
 403
 404 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 405 @item LDR =
 406 @smallexample
 407   ldr <register> , =<expression>
 408 @end smallexample
 409
 410 The constant expression will be placed into the nearest literal pool (if it not
 411 already there) and a PC-relative LDR instruction will be generated.
 412
 413 @end table
 414
 415 For more information on the AArch64 instruction set and assembly language
 416 notation, see @samp{ARMv8 Instruction Set Overview} available at
 417 @uref{http://infocenter.arm.com}.
 418
 419
 420 @node AArch64 Mapping Symbols
 421 @section Mapping Symbols
 422
 423 The AArch64 ELF specification requires that special symbols be inserted
 424 into object files to mark certain features:
 425
 426 @table @code
 427
 428 @cindex @code{$x}
 429 @item $x
 430 At the start of a region of code containing AArch64 instructions.
 431
 432 @cindex @code{$d}
 433 @item $d
 434 At the start of a region of data.
 435
 436 @end table