gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2017 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a55},
  61 @code{cortex-a57},
  62 @code{cortex-a72},
  63 @code{cortex-a73},
  64 @code{cortex-a75},
  65 @code{exynos-m1},
  66 @code{falkor},
  67 @code{qdf24xx},
  68 @code{saphira},
  69 @code{thunderx},
  70 @code{vulcan},
  71 @code{xgene1}
  72 and
  73 @code{xgene2}.
  74 The special name @code{all} may be used to allow the assembler to accept
  75 instructions valid for any supported processor, including all optional
  76 extensions.
  77
  78 In addition to the basic instruction set, the assembler can be told to
  79 accept, or restrict, various extension mnemonics that extend the
  80 processor.  @xref{AArch64 Extensions}.
  81
  82 If some implementations of a particular processor can have an
  83 extension, then then those extensions are automatically enabled.
  84 Consequently, you will not normally have to specify any additional
  85 extensions.
  86
  87 @cindex @option{-march=} command line option, AArch64
  88 @item -march=@var{architecture}[+@var{extension}@dots{}]
  89 This option specifies the target architecture.  The assembler will
  90 issue an error message if an attempt is made to assemble an
  91 instruction which will not execute on the target architecture.  The
  92 following architecture names are recognized: @code{armv8-a},
  93 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a} and @code{armv8.4-a}.
  94
  95 If both @option{-mcpu} and @option{-march} are specified, the
  96 assembler will use the setting for @option{-mcpu}.  If neither are
  97 specified, the assembler will default to @option{-mcpu=all}.
  98
  99 The architecture option can be extended with the same instruction set
 100 extension options as the @option{-mcpu} option.  Unlike
 101 @option{-mcpu}, extensions are not always enabled by default,
 102 @xref{AArch64 Extensions}.
 103
 104 @cindex @code{-mverbose-error} command line option, AArch64
 105 @item -mverbose-error
 106 This option enables verbose error messages for AArch64 gas.  This option
 107 is enabled by default.
 108
 109 @cindex @code{-mno-verbose-error} command line option, AArch64
 110 @item -mno-verbose-error
 111 This option disables verbose error messages in AArch64 gas.
 112
 113 @end table
 114 @c man end
 115
 116 @node AArch64 Extensions
 117 @section Architecture Extensions
 118
 119 The table below lists the permitted architecture extensions that are
 120 supported by the assembler and the conditions under which they are
 121 automatically enabled.
 122
 123 Multiple extensions may be specified, separated by a @code{+}.
 124 Extension mnemonics may also be removed from those the assembler
 125 accepts.  This is done by prepending @code{no} to the option that adds
 126 the extension.  Extensions that are removed must be listed after all
 127 extensions that have been added.
 128
 129 Enabling an extension that requires other extensions will
 130 automatically cause those extensions to be enabled.  Similarly,
 131 disabling an extension that is required by other extensions will
 132 automatically cause those extensions to be disabled.
 133
 134 @multitable @columnfractions .12 .17 .17 .54
 135 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 136  @tab Description
 137 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 138  @tab Enable the complex number SIMD extensions.  This implies
 139  @code{fp16} and @code{simd}.
 140 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 141  @tab Enable CRC instructions.
 142 @item @code{crypto} @tab ARMv8-A @tab No
 143  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 144 @item @code{aes} @tab ARMv8-A @tab No
 145  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 146 @item @code{sha2} @tab ARMv8-A @tab No
 147  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 148 @item @code{sha3} @tab ARMv8.2-A @tab No
 149  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 150 @item @code{sm4} @tab ARMv8.2-A @tab No
 151  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 152 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 153  @tab Enable floating-point extensions.
 154 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 155  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 156  @code{fp}.
 157 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 158  @tab Enable Limited Ordering Regions extensions.
 159 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 160  @tab Enable Large System extensions.
 161 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 162  @tab Enable Privileged Access Never support.
 163 @item @code{profile} @tab ARMv8.2-A @tab No
 164  @tab Enable statistical profiling extensions.
 165 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 166  @tab Enable the Reliability, Availability and Serviceability
 167  extension.
 168 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 169  @tab Enable the weak release consistency extension.
 170 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 171  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 172 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 173  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 174 @item @code{sve} @tab ARMv8.2-A @tab No
 175  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 176  @code{simd} and @code{compnum}.
 177 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 178  @tab Enable the Dot Product extension.  This implies @code{simd}.
 179 @end multitable
 180
 181 @node AArch64 Syntax
 182 @section Syntax
 183 @menu
 184 * AArch64-Chars::                Special Characters
 185 * AArch64-Regs::                 Register Names
 186 * AArch64-Relocations::      Relocations
 187 @end menu
 188
 189 @node AArch64-Chars
 190 @subsection Special Characters
 191
 192 @cindex line comment character, AArch64
 193 @cindex AArch64 line comment character
 194 The presence of a @samp{//} on a line indicates the start of a comment
 195 that extends to the end of the current line.  If a @samp{#} appears as
 196 the first character of a line, the whole line is treated as a comment.
 197
 198 @cindex line separator, AArch64
 199 @cindex statement separator, AArch64
 200 @cindex AArch64 line separator
 201 The @samp{;} character can be used instead of a newline to separate
 202 statements.
 203
 204 @cindex immediate character, AArch64
 205 @cindex AArch64 immediate character
 206 The @samp{#} can be optionally used to indicate immediate operands.
 207
 208 @node AArch64-Regs
 209 @subsection Register Names
 210
 211 @cindex AArch64 register names
 212 @cindex register names, AArch64
 213 Please refer to the section @samp{4.4 Register Names} of
 214 @samp{ARMv8 Instruction Set Overview}, which is available at
 215 @uref{http://infocenter.arm.com}.
 216
 217 @node AArch64-Relocations
 218 @subsection Relocations
 219
 220 @cindex relocations, AArch64
 221 @cindex AArch64 relocations
 222 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 223 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 224 by prefixing the label with @samp{#:abs_g2:} etc.
 225 For example to load the 48-bit absolute address of @var{foo} into x0:
 226
 227 @smallexample
 228         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 229         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 230         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 231 @end smallexample
 232
 233 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 234 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 235 instructions can be generated by prefixing the label with
 236 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 237
 238 For example to use 33-bit (+/-4GB) pc-relative addressing to
 239 load the address of @var{foo} into x0:
 240
 241 @smallexample
 242         adrp x0, :pg_hi21:foo
 243         add  x0, x0, #:lo12:foo
 244 @end smallexample
 245
 246 Or to load the value of @var{foo} into x0:
 247
 248 @smallexample
 249         adrp x0, :pg_hi21:foo
 250         ldr  x0, [x0, #:lo12:foo]
 251 @end smallexample
 252
 253 Note that @samp{:pg_hi21:} is optional.
 254
 255 @smallexample
 256         adrp x0, foo
 257 @end smallexample
 258
 259 is equivalent to
 260
 261 @smallexample
 262         adrp x0, :pg_hi21:foo
 263 @end smallexample
 264
 265 @node AArch64 Floating Point
 266 @section Floating Point
 267
 268 @cindex floating point, AArch64 (@sc{ieee})
 269 @cindex AArch64 floating point (@sc{ieee})
 270 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 271
 272 @node AArch64 Directives
 273 @section AArch64 Machine Directives
 274
 275 @cindex machine directives, AArch64
 276 @cindex AArch64 machine directives
 277 @table @code
 278
 279 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 280
 281 @cindex @code{.arch} directive, AArch64
 282 @item .arch @var{name}
 283 Select the target architecture.  Valid values for @var{name} are the same as
 284 for the @option{-march} commandline option.
 285
 286 Specifying @code{.arch} clears any previously selected architecture
 287 extensions.
 288
 289 @cindex @code{.arch_extension} directive, AArch64
 290 @item .arch_extension @var{name}
 291 Add or remove an architecture extension to the target architecture.  Valid
 292 values for @var{name} are the same as those accepted as architectural
 293 extensions by the @option{-mcpu} commandline option.
 294
 295 @code{.arch_extension} may be used multiple times to add or remove extensions
 296 incrementally to the architecture being compiled for.
 297
 298 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 299
 300 @cindex @code{.bss} directive, AArch64
 301 @item .bss
 302 This directive switches to the @code{.bss} section.
 303
 304 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 305
 306 @cindex @code{.cpu} directive, AArch64
 307 @item .cpu @var{name}
 308 Set the target processor.  Valid values for @var{name} are the same as
 309 those accepted by the @option{-mcpu=} command line option.
 310
 311 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 312
 313 @cindex @code{.dword} directive, AArch64
 314 @item .dword @var{expressions}
 315 The @code{.dword} directive produces 64 bit values.
 316
 317 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 318
 319 @cindex @code{.even} directive, AArch64
 320 @item .even
 321 The @code{.even} directive aligns the output on the next even byte
 322 boundary.
 323
 324 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 325 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 326 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 327 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 328
 329 @cindex @code{.inst} directive, AArch64
 330 @item .inst @var{expressions}
 331 Inserts the expressions into the output as if they were instructions,
 332 rather than data.
 333
 334 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 335 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 336 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 337
 338 @cindex @code{.ltorg} directive, AArch64
 339 @item .ltorg
 340 This directive causes the current contents of the literal pool to be
 341 dumped into the current section (which is assumed to be the .text
 342 section) at the current location (aligned to a word boundary).
 343 GAS maintains a separate literal pool for each section and each
 344 sub-section.  The @code{.ltorg} directive will only affect the literal
 345 pool of the current section and sub-section.  At the end of assembly
 346 all remaining, un-empty literal pools will automatically be dumped.
 347
 348 Note - older versions of GAS would dump the current literal
 349 pool any time a section change occurred.  This is no longer done, since
 350 it prevents accurate control of the placement of literal pools.
 351
 352 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 353
 354 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 355 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 356
 357 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 358
 359 @cindex @code{.pool} directive, AArch64
 360 @item .pool
 361 This is a synonym for .ltorg.
 362
 363 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 364 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 365
 366 @cindex @code{.req} directive, AArch64
 367 @item @var{name} .req @var{register name}
 368 This creates an alias for @var{register name} called @var{name}.  For
 369 example:
 370
 371 @smallexample
 372         foo .req w0
 373 @end smallexample
 374
 375 ip0, ip1, lr and fp are automatically defined to
 376 alias to X16, X17, X30 and X29 respectively.
 377
 378 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 379
 380 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 381
 382 @cindex @code{.tlsdescadd} directive, AArch64
 383 @item   @code{.tlsdescadd}
 384 Emits a TLSDESC_ADD reloc on the next instruction.
 385
 386 @cindex @code{.tlsdesccall} directive, AArch64
 387 @item   @code{.tlsdesccall}
 388 Emits a TLSDESC_CALL reloc on the next instruction.
 389
 390 @cindex @code{.tlsdescldr} directive, AArch64
 391 @item   @code{.tlsdescldr}
 392 Emits a TLSDESC_LDR reloc on the next instruction.
 393
 394 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 395
 396 @cindex @code{.unreq} directive, AArch64
 397 @item .unreq @var{alias-name}
 398 This undefines a register alias which was previously defined using the
 399 @code{req} directive.  For example:
 400
 401 @smallexample
 402         foo .req w0
 403         .unreq foo
 404 @end smallexample
 405
 406 An error occurs if the name is undefined.  Note - this pseudo op can
 407 be used to delete builtin in register name aliases (eg 'w0').  This
 408 should only be done if it is really necessary.
 409
 410 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 411
 412 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 413 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 414
 415 @cindex @code{.xword} directive, AArch64
 416 @item .xword @var{expressions}
 417 The @code{.xword} directive produces 64 bit values.  This is the same
 418 as the @code{.dword} directive.
 419
 420 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 421 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 422
 423 @end table
 424
 425 @node AArch64 Opcodes
 426 @section Opcodes
 427
 428 @cindex AArch64 opcodes
 429 @cindex opcodes for AArch64
 430 GAS implements all the standard AArch64 opcodes.  It also
 431 implements several pseudo opcodes, including several synthetic load
 432 instructions.
 433
 434 @table @code
 435
 436 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 437 @item LDR =
 438 @smallexample
 439   ldr <register> , =<expression>
 440 @end smallexample
 441
 442 The constant expression will be placed into the nearest literal pool (if it not
 443 already there) and a PC-relative LDR instruction will be generated.
 444
 445 @end table
 446
 447 For more information on the AArch64 instruction set and assembly language
 448 notation, see @samp{ARMv8 Instruction Set Overview} available at
 449 @uref{http://infocenter.arm.com}.
 450
 451
 452 @node AArch64 Mapping Symbols
 453 @section Mapping Symbols
 454
 455 The AArch64 ELF specification requires that special symbols be inserted
 456 into object files to mark certain features:
 457
 458 @table @code
 459
 460 @cindex @code{$x}
 461 @item $x
 462 At the start of a region of code containing AArch64 instructions.
 463
 464 @cindex @code{$d}
 465 @item $d
 466 At the start of a region of data.
 467
 468 @end table