gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2016 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a57},
  61 @code{cortex-a72},
  62 @code{exynos-m1},
  63 @code{qdf24xx},
  64 @code{thunderx},
  65 @code{xgene1}
  66 and
  67 @code{xgene2}.
  68 The special name @code{all} may be used to allow the assembler to accept
  69 instructions valid for any supported processor, including all optional
  70 extensions.
  71
  72 In addition to the basic instruction set, the assembler can be told to
  73 accept, or restrict, various extension mnemonics that extend the
  74 processor.  @xref{AArch64 Extensions}.
  75
  76 If some implementations of a particular processor can have an
  77 extension, then then those extensions are automatically enabled.
  78 Consequently, you will not normally have to specify any additional
  79 extensions.
  80
  81 @cindex @option{-march=} command line option, AArch64
  82 @item -march=@var{architecture}[+@var{extension}@dots{}]
  83 This option specifies the target architecture.  The assembler will
  84 issue an error message if an attempt is made to assemble an
  85 instruction which will not execute on the target architecture.  The
  86 following architecture names are recognized: @code{armv8-a},
  87 @code{armv8.1-a} and @code{armv8.2-a}.
  88
  89 If both @option{-mcpu} and @option{-march} are specified, the
  90 assembler will use the setting for @option{-mcpu}.  If neither are
  91 specified, the assembler will default to @option{-mcpu=all}.
  92
  93 The architecture option can be extended with the same instruction set
  94 extension options as the @option{-mcpu} option.  Unlike
  95 @option{-mcpu}, extensions are not always enabled by default,
  96 @xref{AArch64 Extensions}.
  97
  98 @cindex @code{-mverbose-error} command line option, AArch64
  99 @item -mverbose-error
 100 This option enables verbose error messages for AArch64 gas.  This option
 101 is enabled by default.
 102
 103 @cindex @code{-mno-verbose-error} command line option, AArch64
 104 @item -mno-verbose-error
 105 This option disables verbose error messages in AArch64 gas.
 106
 107 @end table
 108 @c man end
 109
 110 @node AArch64 Extensions
 111 @section Architecture Extensions
 112
 113 The table below lists the permitted architecture extensions that are
 114 supported by the assembler and the conditions under which they are
 115 automatically enabled.
 116
 117 Multiple extensions may be specified, separated by a @code{+}.
 118 Extension mnemonics may also be removed from those the assembler
 119 accepts.  This is done by prepending @code{no} to the option that adds
 120 the extension.  Extensions that are removed must be listed after all
 121 extensions that have been added.
 122
 123 Enabling an extension that requires other extensions will
 124 automatically cause those extensions to be enabled.  Similarly,
 125 disabling an extension that is required by other extensions will
 126 automatically cause those extensions to be disabled.
 127
 128 @multitable @columnfractions .12 .17 .17 .54
 129 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 130  @tab Description
 131 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 132  @tab Enable CRC instructions.
 133 @item @code{crypto} @tab ARMv8-A @tab No
 134  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 135 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 136  @tab Enable floating-point extensions.
 137 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 138  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 139  @code{fp}.
 140 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 141  @tab Enable Limited Ordering Regions extensions.
 142 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 143  @tab Enable Large System extensions.
 144 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 145  @tab Enable Privileged Access Never support.
 146 @item @code{profile} @tab ARMv8.2-A @tab No
 147  @tab Enable statistical profiling extensions.
 148 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 149  @tab Enable the Reliability, Availability and Serviceability
 150  extension.
 151 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 152  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 153 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 154  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 155 @end multitable
 156
 157 @node AArch64 Syntax
 158 @section Syntax
 159 @menu
 160 * AArch64-Chars::                Special Characters
 161 * AArch64-Regs::                 Register Names
 162 * AArch64-Relocations::      Relocations
 163 @end menu
 164
 165 @node AArch64-Chars
 166 @subsection Special Characters
 167
 168 @cindex line comment character, AArch64
 169 @cindex AArch64 line comment character
 170 The presence of a @samp{//} on a line indicates the start of a comment
 171 that extends to the end of the current line.  If a @samp{#} appears as
 172 the first character of a line, the whole line is treated as a comment.
 173
 174 @cindex line separator, AArch64
 175 @cindex statement separator, AArch64
 176 @cindex AArch64 line separator
 177 The @samp{;} character can be used instead of a newline to separate
 178 statements.
 179
 180 @cindex immediate character, AArch64
 181 @cindex AArch64 immediate character
 182 The @samp{#} can be optionally used to indicate immediate operands.
 183
 184 @node AArch64-Regs
 185 @subsection Register Names
 186
 187 @cindex AArch64 register names
 188 @cindex register names, AArch64
 189 Please refer to the section @samp{4.4 Register Names} of
 190 @samp{ARMv8 Instruction Set Overview}, which is available at
 191 @uref{http://infocenter.arm.com}.
 192
 193 @node AArch64-Relocations
 194 @subsection Relocations
 195
 196 @cindex relocations, AArch64
 197 @cindex AArch64 relocations
 198 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 199 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 200 by prefixing the label with @samp{#:abs_g2:} etc.
 201 For example to load the 48-bit absolute address of @var{foo} into x0:
 202
 203 @smallexample
 204         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 205         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 206         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 207 @end smallexample
 208
 209 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 210 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 211 instructions can be generated by prefixing the label with
 212 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 213
 214 For example to use 33-bit (+/-4GB) pc-relative addressing to
 215 load the address of @var{foo} into x0:
 216
 217 @smallexample
 218         adrp x0, :pg_hi21:foo
 219         add  x0, x0, #:lo12:foo
 220 @end smallexample
 221
 222 Or to load the value of @var{foo} into x0:
 223
 224 @smallexample
 225         adrp x0, :pg_hi21:foo
 226         ldr  x0, [x0, #:lo12:foo]
 227 @end smallexample
 228
 229 Note that @samp{:pg_hi21:} is optional.
 230
 231 @smallexample
 232         adrp x0, foo
 233 @end smallexample
 234
 235 is equivalent to
 236
 237 @smallexample
 238         adrp x0, :pg_hi21:foo
 239 @end smallexample
 240
 241 @node AArch64 Floating Point
 242 @section Floating Point
 243
 244 @cindex floating point, AArch64 (@sc{ieee})
 245 @cindex AArch64 floating point (@sc{ieee})
 246 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 247
 248 @node AArch64 Directives
 249 @section AArch64 Machine Directives
 250
 251 @cindex machine directives, AArch64
 252 @cindex AArch64 machine directives
 253 @table @code
 254
 255 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 256
 257 @cindex @code{.arch} directive, AArch64
 258 @item .arch @var{name}
 259 Select the target architecture.  Valid values for @var{name} are the same as
 260 for the @option{-march} commandline option.
 261
 262 Specifying @code{.arch} clears any previously selected architecture
 263 extensions.
 264
 265 @cindex @code{.arch_extension} directive, AArch64
 266 @item .arch_extension @var{name}
 267 Add or remove an architecture extension to the target architecture.  Valid
 268 values for @var{name} are the same as those accepted as architectural
 269 extensions by the @option{-mcpu} commandline option.
 270
 271 @code{.arch_extension} may be used multiple times to add or remove extensions
 272 incrementally to the architecture being compiled for.
 273
 274 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 275
 276 @cindex @code{.bss} directive, AArch64
 277 @item .bss
 278 This directive switches to the @code{.bss} section.
 279
 280 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 281
 282 @cindex @code{.cpu} directive, AArch64
 283 @item .cpu @var{name}
 284 Set the target processor.  Valid values for @var{name} are the same as
 285 those accepted by the @option{-mcpu=} command line option.
 286
 287 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 288
 289 @cindex @code{.dword} directive, AArch64
 290 @item .dword @var{expressions}
 291 The @code{.dword} directive produces 64 bit values.
 292
 293 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 294
 295 @cindex @code{.even} directive, AArch64
 296 @item .even
 297 The @code{.even} directive aligns the output on the next even byte
 298 boundary.
 299
 300 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 301 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 302 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 303 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 304
 305 @cindex @code{.inst} directive, AArch64
 306 @item .inst @var{expressions}
 307 Inserts the expressions into the output as if they were instructions,
 308 rather than data.
 309
 310 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 311 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 312 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 313
 314 @cindex @code{.ltorg} directive, AArch64
 315 @item .ltorg
 316 This directive causes the current contents of the literal pool to be
 317 dumped into the current section (which is assumed to be the .text
 318 section) at the current location (aligned to a word boundary).
 319 GAS maintains a separate literal pool for each section and each
 320 sub-section.  The @code{.ltorg} directive will only affect the literal
 321 pool of the current section and sub-section.  At the end of assembly
 322 all remaining, un-empty literal pools will automatically be dumped.
 323
 324 Note - older versions of GAS would dump the current literal
 325 pool any time a section change occurred.  This is no longer done, since
 326 it prevents accurate control of the placement of literal pools.
 327
 328 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 329
 330 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 331 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 332
 333 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 334
 335 @cindex @code{.pool} directive, AArch64
 336 @item .pool
 337 This is a synonym for .ltorg.
 338
 339 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 340 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 341
 342 @cindex @code{.req} directive, AArch64
 343 @item @var{name} .req @var{register name}
 344 This creates an alias for @var{register name} called @var{name}.  For
 345 example:
 346
 347 @smallexample
 348         foo .req w0
 349 @end smallexample
 350
 351 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 352
 353 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 354
 355 @cindex @code{.tlsdescadd} directive, AArch64
 356 @item   @code{.tlsdescadd}
 357 Emits a TLSDESC_ADD reloc on the next instruction.
 358
 359 @cindex @code{.tlsdesccall} directive, AArch64
 360 @item   @code{.tlsdesccall}
 361 Emits a TLSDESC_CALL reloc on the next instruction.
 362
 363 @cindex @code{.tlsdescldr} directive, AArch64
 364 @item   @code{.tlsdescldr}
 365 Emits a TLSDESC_LDR reloc on the next instruction.
 366
 367 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 368
 369 @cindex @code{.unreq} directive, AArch64
 370 @item .unreq @var{alias-name}
 371 This undefines a register alias which was previously defined using the
 372 @code{req} directive.  For example:
 373
 374 @smallexample
 375         foo .req w0
 376         .unreq foo
 377 @end smallexample
 378
 379 An error occurs if the name is undefined.  Note - this pseudo op can
 380 be used to delete builtin in register name aliases (eg 'w0').  This
 381 should only be done if it is really necessary.
 382
 383 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 384
 385 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 386 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 387
 388 @cindex @code{.xword} directive, AArch64
 389 @item .xword @var{expressions}
 390 The @code{.xword} directive produces 64 bit values.  This is the same
 391 as the @code{.dword} directive.
 392
 393 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 394 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 395
 396 @end table
 397
 398 @node AArch64 Opcodes
 399 @section Opcodes
 400
 401 @cindex AArch64 opcodes
 402 @cindex opcodes for AArch64
 403 GAS implements all the standard AArch64 opcodes.  It also
 404 implements several pseudo opcodes, including several synthetic load
 405 instructions.
 406
 407 @table @code
 408
 409 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 410 @item LDR =
 411 @smallexample
 412   ldr <register> , =<expression>
 413 @end smallexample
 414
 415 The constant expression will be placed into the nearest literal pool (if it not
 416 already there) and a PC-relative LDR instruction will be generated.
 417
 418 @end table
 419
 420 For more information on the AArch64 instruction set and assembly language
 421 notation, see @samp{ARMv8 Instruction Set Overview} available at
 422 @uref{http://infocenter.arm.com}.
 423
 424
 425 @node AArch64 Mapping Symbols
 426 @section Mapping Symbols
 427
 428 The AArch64 ELF specification requires that special symbols be inserted
 429 into object files to mark certain features:
 430
 431 @table @code
 432
 433 @cindex @code{$x}
 434 @item $x
 435 At the start of a region of code containing AArch64 instructions.
 436
 437 @cindex @code{$d}
 438 @item $d
 439 At the start of a region of data.
 440
 441 @end table