gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2015 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a53},
  59 @code{cortex-a57},
  60 @code{cortex-a72},
  61 @code{thunderx},
  62 @code{xgene1}
  63 and
  64 @code{xgene2}.
  65 The special name @code{all} may be used to allow the assembler to accept
  66 instructions valid for any supported processor, including all optional
  67 extensions.
  68
  69 In addition to the basic instruction set, the assembler can be told to
  70 accept, or restrict, various extension mnemonics that extend the
  71 processor.  @xref{AArch64 Extensions}.
  72
  73 If some implementations of a particular processor can have an
  74 extension, then then those extensions are automatically enabled.
  75 Consequently, you will not normally have to specify any additional
  76 extensions.
  77
  78 @cindex @option{-march=} command line option, AArch64
  79 @item -march=@var{architecture}[+@var{extension}@dots{}]
  80 This option specifies the target architecture.  The assembler will
  81 issue an error message if an attempt is made to assemble an
  82 instruction which will not execute on the target architecture.  The
  83 only value for @var{architecture} is @code{armv8-a}.
  84
  85 If both @option{-mcpu} and @option{-march} are specified, the
  86 assembler will use the setting for @option{-mcpu}.  If neither are
  87 specified, the assembler will default to @option{-mcpu=all}.
  88
  89 The architecture option can be extended with the same instruction set
  90 extension options as the @option{-mcpu} option.  Unlike
  91 @option{-mcpu}, extensions are not always enabled by default,
  92 @xref{AArch64 Extensions}.
  93
  94 @cindex @code{-mverbose-error} command line option, AArch64
  95 @item -mverbose-error
  96 This option enables verbose error messages for AArch64 gas.  This option
  97 is enabled by default.
  98
  99 @cindex @code{-mno-verbose-error} command line option, AArch64
 100 @item -mno-verbose-error
 101 This option disables verbose error messages in AArch64 gas.
 102
 103 @end table
 104 @c man end
 105
 106 @node AArch64 Extensions
 107 @section Architecture Extensions
 108
 109 The table below lists the permitted architecture extensions that are
 110 supported by the assembler and the conditions under which they are
 111 automatically enabled.
 112
 113 Multiple extensions may be specified, separated by a @code{+}.
 114 Extension mnemonics may also be removed from those the assembler
 115 accepts.  This is done by prepending @code{no} to the option that adds
 116 the extension.  Extensions that are removed must be listed after all
 117 extensions that have been added.
 118
 119 Enabling an extension that requires other extensions will
 120 automatically cause those extensions to be enabled.  Similarly,
 121 disabling an extension that is required by other extensions will
 122 automatically cause those extensions to be disabled.
 123
 124 @multitable @columnfractions .12 .17 .17 .54
 125 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 126  @tab Description
 127 @item @code{crc} @tab ARMv8-A @tab No
 128  @tab Enable CRC instructions.
 129 @item @code{crypto} @tab ARMv8-A @tab No
 130  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 131 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 132  @tab Enable floating-point extensions.
 133 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 134  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 135 @end multitable
 136
 137 @node AArch64 Syntax
 138 @section Syntax
 139 @menu
 140 * AArch64-Chars::                Special Characters
 141 * AArch64-Regs::                 Register Names
 142 * AArch64-Relocations::      Relocations
 143 @end menu
 144
 145 @node AArch64-Chars
 146 @subsection Special Characters
 147
 148 @cindex line comment character, AArch64
 149 @cindex AArch64 line comment character
 150 The presence of a @samp{//} on a line indicates the start of a comment
 151 that extends to the end of the current line.  If a @samp{#} appears as
 152 the first character of a line, the whole line is treated as a comment.
 153
 154 @cindex line separator, AArch64
 155 @cindex statement separator, AArch64
 156 @cindex AArch64 line separator
 157 The @samp{;} character can be used instead of a newline to separate
 158 statements.
 159
 160 @cindex immediate character, AArch64
 161 @cindex AArch64 immediate character
 162 The @samp{#} can be optionally used to indicate immediate operands.
 163
 164 @node AArch64-Regs
 165 @subsection Register Names
 166
 167 @cindex AArch64 register names
 168 @cindex register names, AArch64
 169 Please refer to the section @samp{4.4 Register Names} of
 170 @samp{ARMv8 Instruction Set Overview}, which is available at
 171 @uref{http://infocenter.arm.com}.
 172
 173 @node AArch64-Relocations
 174 @subsection Relocations
 175
 176 @cindex relocations, AArch64
 177 @cindex AArch64 relocations
 178 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 179 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 180 by prefixing the label with @samp{#:abs_g2:} etc.
 181 For example to load the 48-bit absolute address of @var{foo} into x0:
 182
 183 @smallexample
 184         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 185         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 186         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 187 @end smallexample
 188
 189 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 190 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 191 instructions can be generated by prefixing the label with
 192 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 193
 194 For example to use 33-bit (+/-4GB) pc-relative addressing to
 195 load the address of @var{foo} into x0:
 196
 197 @smallexample
 198         adrp x0, :pg_hi21:foo
 199         add  x0, x0, #:lo12:foo
 200 @end smallexample
 201
 202 Or to load the value of @var{foo} into x0:
 203
 204 @smallexample
 205         adrp x0, :pg_hi21:foo
 206         ldr  x0, [x0, #:lo12:foo]
 207 @end smallexample
 208
 209 Note that @samp{:pg_hi21:} is optional.
 210
 211 @smallexample
 212         adrp x0, foo
 213 @end smallexample
 214
 215 is equivalent to
 216
 217 @smallexample
 218         adrp x0, :pg_hi21:foo
 219 @end smallexample
 220
 221 @node AArch64 Floating Point
 222 @section Floating Point
 223
 224 @cindex floating point, AArch64 (@sc{ieee})
 225 @cindex AArch64 floating point (@sc{ieee})
 226 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 227
 228 @node AArch64 Directives
 229 @section AArch64 Machine Directives
 230
 231 @cindex machine directives, AArch64
 232 @cindex AArch64 machine directives
 233 @table @code
 234
 235 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 236
 237 @cindex @code{.arch} directive, AArch64
 238 @item .arch @var{name}
 239 Select the target architecture.  Valid values for @var{name} are the same as
 240 for the @option{-march} commandline option.
 241
 242 Specifying @code{.arch} clears any previously selected architecture
 243 extensions.
 244
 245 @cindex @code{.arch_extension} directive, AArch64
 246 @item .arch_extension @var{name}
 247 Add or remove an architecture extension to the target architecture.  Valid
 248 values for @var{name} are the same as those accepted as architectural
 249 extensions by the @option{-mcpu} commandline option.
 250
 251 @code{.arch_extension} may be used multiple times to add or remove extensions
 252 incrementally to the architecture being compiled for.
 253
 254 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 255
 256 @cindex @code{.bss} directive, AArch64
 257 @item .bss
 258 This directive switches to the @code{.bss} section.
 259
 260 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 261 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 262 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 263 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 264 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 265 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 266 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 267 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 268 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 269 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 270
 271 @cindex @code{.ltorg} directive, AArch64
 272 @item .ltorg
 273 This directive causes the current contents of the literal pool to be
 274 dumped into the current section (which is assumed to be the .text
 275 section) at the current location (aligned to a word boundary).
 276 GAS maintains a separate literal pool for each section and each
 277 sub-section.  The @code{.ltorg} directive will only affect the literal
 278 pool of the current section and sub-section.  At the end of assembly
 279 all remaining, un-empty literal pools will automatically be dumped.
 280
 281 Note - older versions of GAS would dump the current literal
 282 pool any time a section change occurred.  This is no longer done, since
 283 it prevents accurate control of the placement of literal pools.
 284
 285 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 286
 287 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 288 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 289
 290 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 291
 292 @cindex @code{.pool} directive, AArch64
 293 @item .pool
 294 This is a synonym for .ltorg.
 295
 296 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 297 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 298
 299 @cindex @code{.req} directive, AArch64
 300 @item @var{name} .req @var{register name}
 301 This creates an alias for @var{register name} called @var{name}.  For
 302 example:
 303
 304 @smallexample
 305         foo .req w0
 306 @end smallexample
 307
 308 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 309
 310 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 311
 312 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 313
 314 @cindex @code{.unreq} directive, AArch64
 315 @item .unreq @var{alias-name}
 316 This undefines a register alias which was previously defined using the
 317 @code{req} directive.  For example:
 318
 319 @smallexample
 320         foo .req w0
 321         .unreq foo
 322 @end smallexample
 323
 324 An error occurs if the name is undefined.  Note - this pseudo op can
 325 be used to delete builtin in register name aliases (eg 'w0').  This
 326 should only be done if it is really necessary.
 327
 328 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 329
 330 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 331 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 332 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 333 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 334
 335 @end table
 336
 337 @node AArch64 Opcodes
 338 @section Opcodes
 339
 340 @cindex AArch64 opcodes
 341 @cindex opcodes for AArch64
 342 GAS implements all the standard AArch64 opcodes.  It also
 343 implements several pseudo opcodes, including several synthetic load
 344 instructions.
 345
 346 @table @code
 347
 348 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 349 @item LDR =
 350 @smallexample
 351   ldr <register> , =<expression>
 352 @end smallexample
 353
 354 The constant expression will be placed into the nearest literal pool (if it not
 355 already there) and a PC-relative LDR instruction will be generated.
 356
 357 @end table
 358
 359 For more information on the AArch64 instruction set and assembly language
 360 notation, see @samp{ARMv8 Instruction Set Overview} available at
 361 @uref{http://infocenter.arm.com}.
 362
 363
 364 @node AArch64 Mapping Symbols
 365 @section Mapping Symbols
 366
 367 The AArch64 ELF specification requires that special symbols be inserted
 368 into object files to mark certain features:
 369
 370 @table @code
 371
 372 @cindex @code{$x}
 373 @item $x
 374 At the start of a region of code containing AArch64 instructions.
 375
 376 @cindex @code{$d}
 377 @item $d
 378 At the start of a region of data.
 379
 380 @end table