gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2016 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a57},
  61 @code{cortex-a72},
  62 @code{cortex-a73},
  63 @code{exynos-m1},
  64 @code{qdf24xx},
  65 @code{thunderx},
  66 @code{xgene1}
  67 and
  68 @code{xgene2}.
  69 The special name @code{all} may be used to allow the assembler to accept
  70 instructions valid for any supported processor, including all optional
  71 extensions.
  72
  73 In addition to the basic instruction set, the assembler can be told to
  74 accept, or restrict, various extension mnemonics that extend the
  75 processor.  @xref{AArch64 Extensions}.
  76
  77 If some implementations of a particular processor can have an
  78 extension, then then those extensions are automatically enabled.
  79 Consequently, you will not normally have to specify any additional
  80 extensions.
  81
  82 @cindex @option{-march=} command line option, AArch64
  83 @item -march=@var{architecture}[+@var{extension}@dots{}]
  84 This option specifies the target architecture.  The assembler will
  85 issue an error message if an attempt is made to assemble an
  86 instruction which will not execute on the target architecture.  The
  87 following architecture names are recognized: @code{armv8-a},
  88 @code{armv8.1-a} and @code{armv8.2-a}.
  89
  90 If both @option{-mcpu} and @option{-march} are specified, the
  91 assembler will use the setting for @option{-mcpu}.  If neither are
  92 specified, the assembler will default to @option{-mcpu=all}.
  93
  94 The architecture option can be extended with the same instruction set
  95 extension options as the @option{-mcpu} option.  Unlike
  96 @option{-mcpu}, extensions are not always enabled by default,
  97 @xref{AArch64 Extensions}.
  98
  99 @cindex @code{-mverbose-error} command line option, AArch64
 100 @item -mverbose-error
 101 This option enables verbose error messages for AArch64 gas.  This option
 102 is enabled by default.
 103
 104 @cindex @code{-mno-verbose-error} command line option, AArch64
 105 @item -mno-verbose-error
 106 This option disables verbose error messages in AArch64 gas.
 107
 108 @end table
 109 @c man end
 110
 111 @node AArch64 Extensions
 112 @section Architecture Extensions
 113
 114 The table below lists the permitted architecture extensions that are
 115 supported by the assembler and the conditions under which they are
 116 automatically enabled.
 117
 118 Multiple extensions may be specified, separated by a @code{+}.
 119 Extension mnemonics may also be removed from those the assembler
 120 accepts.  This is done by prepending @code{no} to the option that adds
 121 the extension.  Extensions that are removed must be listed after all
 122 extensions that have been added.
 123
 124 Enabling an extension that requires other extensions will
 125 automatically cause those extensions to be enabled.  Similarly,
 126 disabling an extension that is required by other extensions will
 127 automatically cause those extensions to be disabled.
 128
 129 @multitable @columnfractions .12 .17 .17 .54
 130 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 131  @tab Description
 132 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 133  @tab Enable CRC instructions.
 134 @item @code{crypto} @tab ARMv8-A @tab No
 135  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 136 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 137  @tab Enable floating-point extensions.
 138 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 139  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 140  @code{fp}.
 141 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 142  @tab Enable Limited Ordering Regions extensions.
 143 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 144  @tab Enable Large System extensions.
 145 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 146  @tab Enable Privileged Access Never support.
 147 @item @code{profile} @tab ARMv8.2-A @tab No
 148  @tab Enable statistical profiling extensions.
 149 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 150  @tab Enable the Reliability, Availability and Serviceability
 151  extension.
 152 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 153  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 154 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 155  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 156 @end multitable
 157
 158 @node AArch64 Syntax
 159 @section Syntax
 160 @menu
 161 * AArch64-Chars::                Special Characters
 162 * AArch64-Regs::                 Register Names
 163 * AArch64-Relocations::      Relocations
 164 @end menu
 165
 166 @node AArch64-Chars
 167 @subsection Special Characters
 168
 169 @cindex line comment character, AArch64
 170 @cindex AArch64 line comment character
 171 The presence of a @samp{//} on a line indicates the start of a comment
 172 that extends to the end of the current line.  If a @samp{#} appears as
 173 the first character of a line, the whole line is treated as a comment.
 174
 175 @cindex line separator, AArch64
 176 @cindex statement separator, AArch64
 177 @cindex AArch64 line separator
 178 The @samp{;} character can be used instead of a newline to separate
 179 statements.
 180
 181 @cindex immediate character, AArch64
 182 @cindex AArch64 immediate character
 183 The @samp{#} can be optionally used to indicate immediate operands.
 184
 185 @node AArch64-Regs
 186 @subsection Register Names
 187
 188 @cindex AArch64 register names
 189 @cindex register names, AArch64
 190 Please refer to the section @samp{4.4 Register Names} of
 191 @samp{ARMv8 Instruction Set Overview}, which is available at
 192 @uref{http://infocenter.arm.com}.
 193
 194 @node AArch64-Relocations
 195 @subsection Relocations
 196
 197 @cindex relocations, AArch64
 198 @cindex AArch64 relocations
 199 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 200 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 201 by prefixing the label with @samp{#:abs_g2:} etc.
 202 For example to load the 48-bit absolute address of @var{foo} into x0:
 203
 204 @smallexample
 205         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 206         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 207         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 208 @end smallexample
 209
 210 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 211 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 212 instructions can be generated by prefixing the label with
 213 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 214
 215 For example to use 33-bit (+/-4GB) pc-relative addressing to
 216 load the address of @var{foo} into x0:
 217
 218 @smallexample
 219         adrp x0, :pg_hi21:foo
 220         add  x0, x0, #:lo12:foo
 221 @end smallexample
 222
 223 Or to load the value of @var{foo} into x0:
 224
 225 @smallexample
 226         adrp x0, :pg_hi21:foo
 227         ldr  x0, [x0, #:lo12:foo]
 228 @end smallexample
 229
 230 Note that @samp{:pg_hi21:} is optional.
 231
 232 @smallexample
 233         adrp x0, foo
 234 @end smallexample
 235
 236 is equivalent to
 237
 238 @smallexample
 239         adrp x0, :pg_hi21:foo
 240 @end smallexample
 241
 242 @node AArch64 Floating Point
 243 @section Floating Point
 244
 245 @cindex floating point, AArch64 (@sc{ieee})
 246 @cindex AArch64 floating point (@sc{ieee})
 247 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 248
 249 @node AArch64 Directives
 250 @section AArch64 Machine Directives
 251
 252 @cindex machine directives, AArch64
 253 @cindex AArch64 machine directives
 254 @table @code
 255
 256 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 257
 258 @cindex @code{.arch} directive, AArch64
 259 @item .arch @var{name}
 260 Select the target architecture.  Valid values for @var{name} are the same as
 261 for the @option{-march} commandline option.
 262
 263 Specifying @code{.arch} clears any previously selected architecture
 264 extensions.
 265
 266 @cindex @code{.arch_extension} directive, AArch64
 267 @item .arch_extension @var{name}
 268 Add or remove an architecture extension to the target architecture.  Valid
 269 values for @var{name} are the same as those accepted as architectural
 270 extensions by the @option{-mcpu} commandline option.
 271
 272 @code{.arch_extension} may be used multiple times to add or remove extensions
 273 incrementally to the architecture being compiled for.
 274
 275 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 276
 277 @cindex @code{.bss} directive, AArch64
 278 @item .bss
 279 This directive switches to the @code{.bss} section.
 280
 281 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 282
 283 @cindex @code{.cpu} directive, AArch64
 284 @item .cpu @var{name}
 285 Set the target processor.  Valid values for @var{name} are the same as
 286 those accepted by the @option{-mcpu=} command line option.
 287
 288 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 289
 290 @cindex @code{.dword} directive, AArch64
 291 @item .dword @var{expressions}
 292 The @code{.dword} directive produces 64 bit values.
 293
 294 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 295
 296 @cindex @code{.even} directive, AArch64
 297 @item .even
 298 The @code{.even} directive aligns the output on the next even byte
 299 boundary.
 300
 301 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 302 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 303 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 304 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 305
 306 @cindex @code{.inst} directive, AArch64
 307 @item .inst @var{expressions}
 308 Inserts the expressions into the output as if they were instructions,
 309 rather than data.
 310
 311 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 312 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 313 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 314
 315 @cindex @code{.ltorg} directive, AArch64
 316 @item .ltorg
 317 This directive causes the current contents of the literal pool to be
 318 dumped into the current section (which is assumed to be the .text
 319 section) at the current location (aligned to a word boundary).
 320 GAS maintains a separate literal pool for each section and each
 321 sub-section.  The @code{.ltorg} directive will only affect the literal
 322 pool of the current section and sub-section.  At the end of assembly
 323 all remaining, un-empty literal pools will automatically be dumped.
 324
 325 Note - older versions of GAS would dump the current literal
 326 pool any time a section change occurred.  This is no longer done, since
 327 it prevents accurate control of the placement of literal pools.
 328
 329 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 330
 331 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 332 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 333
 334 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 335
 336 @cindex @code{.pool} directive, AArch64
 337 @item .pool
 338 This is a synonym for .ltorg.
 339
 340 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 341 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 342
 343 @cindex @code{.req} directive, AArch64
 344 @item @var{name} .req @var{register name}
 345 This creates an alias for @var{register name} called @var{name}.  For
 346 example:
 347
 348 @smallexample
 349         foo .req w0
 350 @end smallexample
 351
 352 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 353
 354 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 355
 356 @cindex @code{.tlsdescadd} directive, AArch64
 357 @item   @code{.tlsdescadd}
 358 Emits a TLSDESC_ADD reloc on the next instruction.
 359
 360 @cindex @code{.tlsdesccall} directive, AArch64
 361 @item   @code{.tlsdesccall}
 362 Emits a TLSDESC_CALL reloc on the next instruction.
 363
 364 @cindex @code{.tlsdescldr} directive, AArch64
 365 @item   @code{.tlsdescldr}
 366 Emits a TLSDESC_LDR reloc on the next instruction.
 367
 368 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 369
 370 @cindex @code{.unreq} directive, AArch64
 371 @item .unreq @var{alias-name}
 372 This undefines a register alias which was previously defined using the
 373 @code{req} directive.  For example:
 374
 375 @smallexample
 376         foo .req w0
 377         .unreq foo
 378 @end smallexample
 379
 380 An error occurs if the name is undefined.  Note - this pseudo op can
 381 be used to delete builtin in register name aliases (eg 'w0').  This
 382 should only be done if it is really necessary.
 383
 384 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 385
 386 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 387 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 388
 389 @cindex @code{.xword} directive, AArch64
 390 @item .xword @var{expressions}
 391 The @code{.xword} directive produces 64 bit values.  This is the same
 392 as the @code{.dword} directive.
 393
 394 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 395 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 396
 397 @end table
 398
 399 @node AArch64 Opcodes
 400 @section Opcodes
 401
 402 @cindex AArch64 opcodes
 403 @cindex opcodes for AArch64
 404 GAS implements all the standard AArch64 opcodes.  It also
 405 implements several pseudo opcodes, including several synthetic load
 406 instructions.
 407
 408 @table @code
 409
 410 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 411 @item LDR =
 412 @smallexample
 413   ldr <register> , =<expression>
 414 @end smallexample
 415
 416 The constant expression will be placed into the nearest literal pool (if it not
 417 already there) and a PC-relative LDR instruction will be generated.
 418
 419 @end table
 420
 421 For more information on the AArch64 instruction set and assembly language
 422 notation, see @samp{ARMv8 Instruction Set Overview} available at
 423 @uref{http://infocenter.arm.com}.
 424
 425
 426 @node AArch64 Mapping Symbols
 427 @section Mapping Symbols
 428
 429 The AArch64 ELF specification requires that special symbols be inserted
 430 into object files to mark certain features:
 431
 432 @table @code
 433
 434 @cindex @code{$x}
 435 @item $x
 436 At the start of a region of code containing AArch64 instructions.
 437
 438 @cindex @code{$d}
 439 @item $d
 440 At the start of a region of data.
 441
 442 @end table