gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2018 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a55},
  61 @code{cortex-a57},
  62 @code{cortex-a72},
  63 @code{cortex-a73},
  64 @code{cortex-a75},
  65 @code{cortex-a76},
  66 @code{exynos-m1},
  67 @code{falkor},
  68 @code{qdf24xx},
  69 @code{saphira},
  70 @code{thunderx},
  71 @code{vulcan},
  72 @code{xgene1}
  73 and
  74 @code{xgene2}.
  75 The special name @code{all} may be used to allow the assembler to accept
  76 instructions valid for any supported processor, including all optional
  77 extensions.
  78
  79 In addition to the basic instruction set, the assembler can be told to
  80 accept, or restrict, various extension mnemonics that extend the
  81 processor.  @xref{AArch64 Extensions}.
  82
  83 If some implementations of a particular processor can have an
  84 extension, then then those extensions are automatically enabled.
  85 Consequently, you will not normally have to specify any additional
  86 extensions.
  87
  88 @cindex @option{-march=} command-line option, AArch64
  89 @item -march=@var{architecture}[+@var{extension}@dots{}]
  90 This option specifies the target architecture.  The assembler will
  91 issue an error message if an attempt is made to assemble an
  92 instruction which will not execute on the target architecture.  The
  93 following architecture names are recognized: @code{armv8-a},
  94 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
  95 and @code{armv8.5-a}.
  96
  97 If both @option{-mcpu} and @option{-march} are specified, the
  98 assembler will use the setting for @option{-mcpu}.  If neither are
  99 specified, the assembler will default to @option{-mcpu=all}.
 100
 101 The architecture option can be extended with the same instruction set
 102 extension options as the @option{-mcpu} option.  Unlike
 103 @option{-mcpu}, extensions are not always enabled by default,
 104 @xref{AArch64 Extensions}.
 105
 106 @cindex @code{-mverbose-error} command-line option, AArch64
 107 @item -mverbose-error
 108 This option enables verbose error messages for AArch64 gas.  This option
 109 is enabled by default.
 110
 111 @cindex @code{-mno-verbose-error} command-line option, AArch64
 112 @item -mno-verbose-error
 113 This option disables verbose error messages in AArch64 gas.
 114
 115 @end table
 116 @c man end
 117
 118 @node AArch64 Extensions
 119 @section Architecture Extensions
 120
 121 The table below lists the permitted architecture extensions that are
 122 supported by the assembler and the conditions under which they are
 123 automatically enabled.
 124
 125 Multiple extensions may be specified, separated by a @code{+}.
 126 Extension mnemonics may also be removed from those the assembler
 127 accepts.  This is done by prepending @code{no} to the option that adds
 128 the extension.  Extensions that are removed must be listed after all
 129 extensions that have been added.
 130
 131 Enabling an extension that requires other extensions will
 132 automatically cause those extensions to be enabled.  Similarly,
 133 disabling an extension that is required by other extensions will
 134 automatically cause those extensions to be disabled.
 135
 136 @multitable @columnfractions .12 .17 .17 .54
 137 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 138  @tab Description
 139 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 140  @tab Enable the complex number SIMD extensions.  This implies
 141  @code{fp16} and @code{simd}.
 142 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 143  @tab Enable CRC instructions.
 144 @item @code{crypto} @tab ARMv8-A @tab No
 145  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 146 @item @code{aes} @tab ARMv8-A @tab No
 147  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 148 @item @code{sha2} @tab ARMv8-A @tab No
 149  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 150 @item @code{sha3} @tab ARMv8.2-A @tab No
 151  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 152 @item @code{sm4} @tab ARMv8.2-A @tab No
 153  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 154 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 155  @tab Enable floating-point extensions.
 156 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 157  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 158  @code{fp}.
 159 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 160  @tab Enable Limited Ordering Regions extensions.
 161 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 162  @tab Enable Large System extensions.
 163 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 164  @tab Enable Privileged Access Never support.
 165 @item @code{profile} @tab ARMv8.2-A @tab No
 166  @tab Enable statistical profiling extensions.
 167 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 168  @tab Enable the Reliability, Availability and Serviceability
 169  extension.
 170 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 171  @tab Enable the weak release consistency extension.
 172 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 173  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 174 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 175  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 176 @item @code{sve} @tab ARMv8.2-A @tab No
 177  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 178  @code{simd} and @code{compnum}.
 179 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 180  @tab Enable the Dot Product extension.  This implies @code{simd}.
 181 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 182  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 183  This implies @code{fp16}.
 184 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 185  @tab Enable the speculation barrier instruction sb.
 186 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 187  @tab Enable the Execution and Data and Prediction instructions.
 188 @end multitable
 189
 190 @node AArch64 Syntax
 191 @section Syntax
 192 @menu
 193 * AArch64-Chars::                Special Characters
 194 * AArch64-Regs::                 Register Names
 195 * AArch64-Relocations::      Relocations
 196 @end menu
 197
 198 @node AArch64-Chars
 199 @subsection Special Characters
 200
 201 @cindex line comment character, AArch64
 202 @cindex AArch64 line comment character
 203 The presence of a @samp{//} on a line indicates the start of a comment
 204 that extends to the end of the current line.  If a @samp{#} appears as
 205 the first character of a line, the whole line is treated as a comment.
 206
 207 @cindex line separator, AArch64
 208 @cindex statement separator, AArch64
 209 @cindex AArch64 line separator
 210 The @samp{;} character can be used instead of a newline to separate
 211 statements.
 212
 213 @cindex immediate character, AArch64
 214 @cindex AArch64 immediate character
 215 The @samp{#} can be optionally used to indicate immediate operands.
 216
 217 @node AArch64-Regs
 218 @subsection Register Names
 219
 220 @cindex AArch64 register names
 221 @cindex register names, AArch64
 222 Please refer to the section @samp{4.4 Register Names} of
 223 @samp{ARMv8 Instruction Set Overview}, which is available at
 224 @uref{http://infocenter.arm.com}.
 225
 226 @node AArch64-Relocations
 227 @subsection Relocations
 228
 229 @cindex relocations, AArch64
 230 @cindex AArch64 relocations
 231 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 232 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 233 by prefixing the label with @samp{#:abs_g2:} etc.
 234 For example to load the 48-bit absolute address of @var{foo} into x0:
 235
 236 @smallexample
 237         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 238         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 239         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 240 @end smallexample
 241
 242 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 243 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 244 instructions can be generated by prefixing the label with
 245 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 246
 247 For example to use 33-bit (+/-4GB) pc-relative addressing to
 248 load the address of @var{foo} into x0:
 249
 250 @smallexample
 251         adrp x0, :pg_hi21:foo
 252         add  x0, x0, #:lo12:foo
 253 @end smallexample
 254
 255 Or to load the value of @var{foo} into x0:
 256
 257 @smallexample
 258         adrp x0, :pg_hi21:foo
 259         ldr  x0, [x0, #:lo12:foo]
 260 @end smallexample
 261
 262 Note that @samp{:pg_hi21:} is optional.
 263
 264 @smallexample
 265         adrp x0, foo
 266 @end smallexample
 267
 268 is equivalent to
 269
 270 @smallexample
 271         adrp x0, :pg_hi21:foo
 272 @end smallexample
 273
 274 @node AArch64 Floating Point
 275 @section Floating Point
 276
 277 @cindex floating point, AArch64 (@sc{ieee})
 278 @cindex AArch64 floating point (@sc{ieee})
 279 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 280
 281 @node AArch64 Directives
 282 @section AArch64 Machine Directives
 283
 284 @cindex machine directives, AArch64
 285 @cindex AArch64 machine directives
 286 @table @code
 287
 288 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 289
 290 @cindex @code{.arch} directive, AArch64
 291 @item .arch @var{name}
 292 Select the target architecture.  Valid values for @var{name} are the same as
 293 for the @option{-march} command-line option.
 294
 295 Specifying @code{.arch} clears any previously selected architecture
 296 extensions.
 297
 298 @cindex @code{.arch_extension} directive, AArch64
 299 @item .arch_extension @var{name}
 300 Add or remove an architecture extension to the target architecture.  Valid
 301 values for @var{name} are the same as those accepted as architectural
 302 extensions by the @option{-mcpu} command-line option.
 303
 304 @code{.arch_extension} may be used multiple times to add or remove extensions
 305 incrementally to the architecture being compiled for.
 306
 307 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 308
 309 @cindex @code{.bss} directive, AArch64
 310 @item .bss
 311 This directive switches to the @code{.bss} section.
 312
 313 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 314
 315 @cindex @code{.cpu} directive, AArch64
 316 @item .cpu @var{name}
 317 Set the target processor.  Valid values for @var{name} are the same as
 318 those accepted by the @option{-mcpu=} command-line option.
 319
 320 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 321
 322 @cindex @code{.dword} directive, AArch64
 323 @item .dword @var{expressions}
 324 The @code{.dword} directive produces 64 bit values.
 325
 326 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 327
 328 @cindex @code{.even} directive, AArch64
 329 @item .even
 330 The @code{.even} directive aligns the output on the next even byte
 331 boundary.
 332
 333 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 334 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 335 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 336 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 337
 338 @cindex @code{.inst} directive, AArch64
 339 @item .inst @var{expressions}
 340 Inserts the expressions into the output as if they were instructions,
 341 rather than data.
 342
 343 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 344 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 345 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 346
 347 @cindex @code{.ltorg} directive, AArch64
 348 @item .ltorg
 349 This directive causes the current contents of the literal pool to be
 350 dumped into the current section (which is assumed to be the .text
 351 section) at the current location (aligned to a word boundary).
 352 GAS maintains a separate literal pool for each section and each
 353 sub-section.  The @code{.ltorg} directive will only affect the literal
 354 pool of the current section and sub-section.  At the end of assembly
 355 all remaining, un-empty literal pools will automatically be dumped.
 356
 357 Note - older versions of GAS would dump the current literal
 358 pool any time a section change occurred.  This is no longer done, since
 359 it prevents accurate control of the placement of literal pools.
 360
 361 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 362
 363 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 364 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 365
 366 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 367
 368 @cindex @code{.pool} directive, AArch64
 369 @item .pool
 370 This is a synonym for .ltorg.
 371
 372 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 373 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 374
 375 @cindex @code{.req} directive, AArch64
 376 @item @var{name} .req @var{register name}
 377 This creates an alias for @var{register name} called @var{name}.  For
 378 example:
 379
 380 @smallexample
 381         foo .req w0
 382 @end smallexample
 383
 384 ip0, ip1, lr and fp are automatically defined to
 385 alias to X16, X17, X30 and X29 respectively.
 386
 387 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 388
 389 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 390
 391 @cindex @code{.tlsdescadd} directive, AArch64
 392 @item   @code{.tlsdescadd}
 393 Emits a TLSDESC_ADD reloc on the next instruction.
 394
 395 @cindex @code{.tlsdesccall} directive, AArch64
 396 @item   @code{.tlsdesccall}
 397 Emits a TLSDESC_CALL reloc on the next instruction.
 398
 399 @cindex @code{.tlsdescldr} directive, AArch64
 400 @item   @code{.tlsdescldr}
 401 Emits a TLSDESC_LDR reloc on the next instruction.
 402
 403 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 404
 405 @cindex @code{.unreq} directive, AArch64
 406 @item .unreq @var{alias-name}
 407 This undefines a register alias which was previously defined using the
 408 @code{req} directive.  For example:
 409
 410 @smallexample
 411         foo .req w0
 412         .unreq foo
 413 @end smallexample
 414
 415 An error occurs if the name is undefined.  Note - this pseudo op can
 416 be used to delete builtin in register name aliases (eg 'w0').  This
 417 should only be done if it is really necessary.
 418
 419 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 420
 421 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 422 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 423
 424 @cindex @code{.xword} directive, AArch64
 425 @item .xword @var{expressions}
 426 The @code{.xword} directive produces 64 bit values.  This is the same
 427 as the @code{.dword} directive.
 428
 429 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 430 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 431
 432 @end table
 433
 434 @node AArch64 Opcodes
 435 @section Opcodes
 436
 437 @cindex AArch64 opcodes
 438 @cindex opcodes for AArch64
 439 GAS implements all the standard AArch64 opcodes.  It also
 440 implements several pseudo opcodes, including several synthetic load
 441 instructions.
 442
 443 @table @code
 444
 445 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 446 @item LDR =
 447 @smallexample
 448   ldr <register> , =<expression>
 449 @end smallexample
 450
 451 The constant expression will be placed into the nearest literal pool (if it not
 452 already there) and a PC-relative LDR instruction will be generated.
 453
 454 @end table
 455
 456 For more information on the AArch64 instruction set and assembly language
 457 notation, see @samp{ARMv8 Instruction Set Overview} available at
 458 @uref{http://infocenter.arm.com}.
 459
 460
 461 @node AArch64 Mapping Symbols
 462 @section Mapping Symbols
 463
 464 The AArch64 ELF specification requires that special symbols be inserted
 465 into object files to mark certain features:
 466
 467 @table @code
 468
 469 @cindex @code{$x}
 470 @item $x
 471 At the start of a region of code containing AArch64 instructions.
 472
 473 @cindex @code{$d}
 474 @item $d
 475 At the start of a region of data.
 476
 477 @end table