1 @c Copyright (C) 2009-2016 Free Software Foundation, Inc.
2 @c Contributed by ARM Ltd.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @node AArch64-Dependent
10 @chapter AArch64 Dependent Features
14 @node Machine Dependencies
15 @chapter AArch64 Dependent Features
18 @cindex AArch64 support
20 * AArch64 Options:: Options
21 * AArch64 Extensions:: Extensions
22 * AArch64 Syntax:: Syntax
23 * AArch64 Floating Point:: Floating Point
24 * AArch64 Directives:: AArch64 Machine Directives
25 * AArch64 Opcodes:: Opcodes
26 * AArch64 Mapping Symbols:: Mapping Symbols
31 @cindex AArch64 options (none)
32 @cindex options for AArch64 (none)
37 @cindex @option{-EB} command line option, AArch64
39 This option specifies that the output generated by the assembler should
40 be marked as being encoded for a big-endian processor.
42 @cindex @option{-EL} command line option, AArch64
44 This option specifies that the output generated by the assembler should
45 be marked as being encoded for a little-endian processor.
47 @cindex @option{-mabi=} command line option, AArch64
49 Specify which ABI the source code uses. The recognized arguments
50 are: @code{ilp32} and @code{lp64}, which decides the generated object
51 file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
53 @cindex @option{-mcpu=} command line option, AArch64
54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
55 This option specifies the target processor. The assembler will issue an error
56 message if an attempt is made to assemble an instruction which will not execute
57 on the target processor. The following processor names are recognized:
68 The special name @code{all} may be used to allow the assembler to accept
69 instructions valid for any supported processor, including all optional
72 In addition to the basic instruction set, the assembler can be told to
73 accept, or restrict, various extension mnemonics that extend the
74 processor. @xref{AArch64 Extensions}.
76 If some implementations of a particular processor can have an
77 extension, then then those extensions are automatically enabled.
78 Consequently, you will not normally have to specify any additional
81 @cindex @option{-march=} command line option, AArch64
82 @item -march=@var{architecture}[+@var{extension}@dots{}]
83 This option specifies the target architecture. The assembler will
84 issue an error message if an attempt is made to assemble an
85 instruction which will not execute on the target architecture. The
86 following architecture names are recognized: @code{armv8-a},
87 @code{armv8.1-a} and @code{armv8.2-a}.
89 If both @option{-mcpu} and @option{-march} are specified, the
90 assembler will use the setting for @option{-mcpu}. If neither are
91 specified, the assembler will default to @option{-mcpu=all}.
93 The architecture option can be extended with the same instruction set
94 extension options as the @option{-mcpu} option. Unlike
95 @option{-mcpu}, extensions are not always enabled by default,
96 @xref{AArch64 Extensions}.
98 @cindex @code{-mverbose-error} command line option, AArch64
100 This option enables verbose error messages for AArch64 gas. This option
101 is enabled by default.
103 @cindex @code{-mno-verbose-error} command line option, AArch64
104 @item -mno-verbose-error
105 This option disables verbose error messages in AArch64 gas.
110 @node AArch64 Extensions
111 @section Architecture Extensions
113 The table below lists the permitted architecture extensions that are
114 supported by the assembler and the conditions under which they are
115 automatically enabled.
117 Multiple extensions may be specified, separated by a @code{+}.
118 Extension mnemonics may also be removed from those the assembler
119 accepts. This is done by prepending @code{no} to the option that adds
120 the extension. Extensions that are removed must be listed after all
121 extensions that have been added.
123 Enabling an extension that requires other extensions will
124 automatically cause those extensions to be enabled. Similarly,
125 disabling an extension that is required by other extensions will
126 automatically cause those extensions to be disabled.
128 @multitable @columnfractions .12 .17 .17 .54
129 @headitem Extension @tab Minimum Architecture @tab Enabled by default
131 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
132 @tab Enable CRC instructions.
133 @item @code{crypto} @tab ARMv8-A @tab No
134 @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}.
135 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
136 @tab Enable floating-point extensions.
137 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
138 @tab Enable ARMv8.2 16-bit floating-point support. This implies
140 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
141 @tab Enable Limited Ordering Regions extensions.
142 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
143 @tab Enable Large System extensions.
144 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
145 @tab Enable Privileged Access Never support.
146 @item @code{profile} @tab ARMv8.2-A @tab No
147 @tab Enable statistical profiling extensions.
148 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
149 @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
150 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
151 @tab Enable Advanced SIMD extensions. This implies @code{fp}.
157 * AArch64-Chars:: Special Characters
158 * AArch64-Regs:: Register Names
159 * AArch64-Relocations:: Relocations
163 @subsection Special Characters
165 @cindex line comment character, AArch64
166 @cindex AArch64 line comment character
167 The presence of a @samp{//} on a line indicates the start of a comment
168 that extends to the end of the current line. If a @samp{#} appears as
169 the first character of a line, the whole line is treated as a comment.
171 @cindex line separator, AArch64
172 @cindex statement separator, AArch64
173 @cindex AArch64 line separator
174 The @samp{;} character can be used instead of a newline to separate
177 @cindex immediate character, AArch64
178 @cindex AArch64 immediate character
179 The @samp{#} can be optionally used to indicate immediate operands.
182 @subsection Register Names
184 @cindex AArch64 register names
185 @cindex register names, AArch64
186 Please refer to the section @samp{4.4 Register Names} of
187 @samp{ARMv8 Instruction Set Overview}, which is available at
188 @uref{http://infocenter.arm.com}.
190 @node AArch64-Relocations
191 @subsection Relocations
193 @cindex relocations, AArch64
194 @cindex AArch64 relocations
195 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
196 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
197 by prefixing the label with @samp{#:abs_g2:} etc.
198 For example to load the 48-bit absolute address of @var{foo} into x0:
201 movz x0, #:abs_g2:foo // bits 32-47, overflow check
202 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
203 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
206 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
207 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
208 instructions can be generated by prefixing the label with
209 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
211 For example to use 33-bit (+/-4GB) pc-relative addressing to
212 load the address of @var{foo} into x0:
215 adrp x0, :pg_hi21:foo
216 add x0, x0, #:lo12:foo
219 Or to load the value of @var{foo} into x0:
222 adrp x0, :pg_hi21:foo
223 ldr x0, [x0, #:lo12:foo]
226 Note that @samp{:pg_hi21:} is optional.
235 adrp x0, :pg_hi21:foo
238 @node AArch64 Floating Point
239 @section Floating Point
241 @cindex floating point, AArch64 (@sc{ieee})
242 @cindex AArch64 floating point (@sc{ieee})
243 The AArch64 architecture uses @sc{ieee} floating-point numbers.
245 @node AArch64 Directives
246 @section AArch64 Machine Directives
248 @cindex machine directives, AArch64
249 @cindex AArch64 machine directives
252 @c AAAAAAAAAAAAAAAAAAAAAAAAA
254 @cindex @code{.arch} directive, AArch64
255 @item .arch @var{name}
256 Select the target architecture. Valid values for @var{name} are the same as
257 for the @option{-march} commandline option.
259 Specifying @code{.arch} clears any previously selected architecture
262 @cindex @code{.arch_extension} directive, AArch64
263 @item .arch_extension @var{name}
264 Add or remove an architecture extension to the target architecture. Valid
265 values for @var{name} are the same as those accepted as architectural
266 extensions by the @option{-mcpu} commandline option.
268 @code{.arch_extension} may be used multiple times to add or remove extensions
269 incrementally to the architecture being compiled for.
271 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
273 @cindex @code{.bss} directive, AArch64
275 This directive switches to the @code{.bss} section.
277 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
279 @cindex @code{.cpu} directive, AArch64
280 @item .cpu @var{name}
281 Set the target processor. Valid values for @var{name} are the same as
282 those accepted by the @option{-mcpu=} command line option.
284 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
286 @cindex @code{.dword} directive, AArch64
287 @item .dword @var{expressions}
288 The @code{.dword} directive produces 64 bit values.
290 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
292 @cindex @code{.even} directive, AArch64
294 The @code{.even} directive aligns the output on the next even byte
297 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
298 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
299 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
300 @c IIIIIIIIIIIIIIIIIIIIIIIIII
302 @cindex @code{.inst} directive, AArch64
303 @item .inst @var{expressions}
304 Inserts the expressions into the output as if they were instructions,
307 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
308 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
309 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
311 @cindex @code{.ltorg} directive, AArch64
313 This directive causes the current contents of the literal pool to be
314 dumped into the current section (which is assumed to be the .text
315 section) at the current location (aligned to a word boundary).
316 GAS maintains a separate literal pool for each section and each
317 sub-section. The @code{.ltorg} directive will only affect the literal
318 pool of the current section and sub-section. At the end of assembly
319 all remaining, un-empty literal pools will automatically be dumped.
321 Note - older versions of GAS would dump the current literal
322 pool any time a section change occurred. This is no longer done, since
323 it prevents accurate control of the placement of literal pools.
325 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
327 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
328 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
330 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
332 @cindex @code{.pool} directive, AArch64
334 This is a synonym for .ltorg.
336 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
337 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
339 @cindex @code{.req} directive, AArch64
340 @item @var{name} .req @var{register name}
341 This creates an alias for @var{register name} called @var{name}. For
348 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
350 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
352 @cindex @code{.tlsdescadd} directive, AArch64
353 @item @code{.tlsdescadd}
354 Emits a TLSDESC_ADD reloc on the next instruction.
356 @cindex @code{.tlsdesccall} directive, AArch64
357 @item @code{.tlsdesccall}
358 Emits a TLSDESC_CALL reloc on the next instruction.
360 @cindex @code{.tlsdescldr} directive, AArch64
361 @item @code{.tlsdescldr}
362 Emits a TLSDESC_LDR reloc on the next instruction.
364 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
366 @cindex @code{.unreq} directive, AArch64
367 @item .unreq @var{alias-name}
368 This undefines a register alias which was previously defined using the
369 @code{req} directive. For example:
376 An error occurs if the name is undefined. Note - this pseudo op can
377 be used to delete builtin in register name aliases (eg 'w0'). This
378 should only be done if it is really necessary.
380 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
382 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
383 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
385 @cindex @code{.xword} directive, AArch64
386 @item .xword @var{expressions}
387 The @code{.xword} directive produces 64 bit values. This is the same
388 as the @code{.dword} directive.
390 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
391 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
395 @node AArch64 Opcodes
398 @cindex AArch64 opcodes
399 @cindex opcodes for AArch64
400 GAS implements all the standard AArch64 opcodes. It also
401 implements several pseudo opcodes, including several synthetic load
406 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
409 ldr <register> , =<expression>
412 The constant expression will be placed into the nearest literal pool (if it not
413 already there) and a PC-relative LDR instruction will be generated.
417 For more information on the AArch64 instruction set and assembly language
418 notation, see @samp{ARMv8 Instruction Set Overview} available at
419 @uref{http://infocenter.arm.com}.
422 @node AArch64 Mapping Symbols
423 @section Mapping Symbols
425 The AArch64 ELF specification requires that special symbols be inserted
426 into object files to mark certain features:
432 At the start of a region of code containing AArch64 instructions.
436 At the start of a region of data.