1 @c Copyright (C) 1996-2020 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
149 @code{cortex-m0plus},
152 @code{marvell-whitney},
158 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
159 @code{i80200} (Intel XScale processor)
160 @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
163 The special name @code{all} may be used to allow the
164 assembler to accept instructions valid for any ARM processor.
166 In addition to the basic instruction set, the assembler can be told to
167 accept various extension mnemonics that extend the processor using the
168 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
169 is equivalent to specifying @code{-mcpu=ep9312}.
171 Multiple extensions may be specified, separated by a @code{+}. The
172 extensions should be specified in ascending alphabetical order.
174 Some extensions may be restricted to particular architectures; this is
175 documented in the list of extensions below.
177 Extension mnemonics may also be removed from those the assembler accepts.
178 This is done be prepending @code{no} to the option that adds the extension.
179 Extensions that are removed should be listed after all extensions which have
180 been added, again in ascending alphabetical order. For example,
181 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
184 The following extensions are currently supported:
185 @code{bf16} (BFloat16 extensions for v8.6-A architecture),
186 @code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
188 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
189 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
190 @code{fp} (Floating Point Extensions for v8-A architecture),
191 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
192 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
193 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
198 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
200 @code{os} (Operating System for v6M architecture),
201 @code{predres} (Execution and Data Prediction Restriction Instruction for
202 v8-A architectures, added by default from v8.5-A),
203 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
204 default from v8.5-A),
205 @code{sec} (Security Extensions for v6K and v7-A architectures),
206 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
207 @code{virt} (Virtualization Extensions for v7-A architecture, implies
209 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
210 @code{ras} (Reliability, Availability and Serviceability extensions
211 for v8-A architecture),
212 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
217 @cindex @code{-march=} command-line option, ARM
218 @item -march=@var{architecture}[+@var{extension}@dots{}]
219 This option specifies the target architecture. The assembler will issue
220 an error message if an attempt is made to assemble an instruction which
221 will not execute on the target architecture. The following architecture
222 names are recognized:
260 @code{armv8.1-m.main},
266 If both @code{-mcpu} and
267 @code{-march} are specified, the assembler will use
268 the setting for @code{-mcpu}.
270 The architecture option can be extended with a set extension options. These
271 extensions are context sensitive, i.e. the same extension may mean different
272 things when used with different architectures. When used together with a
273 @code{-mfpu} option, the union of both feature enablement is taken.
274 See their availability and meaning below:
276 For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
278 @code{+fp}: Enables VFPv2 instructions.
279 @code{+nofp}: Disables all FPU instrunctions.
283 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
284 @code{+nofp}: Disables all FPU instructions.
288 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
289 @code{+vfpv3-d16}: Alias for @code{+fp}.
290 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
291 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
292 conversion instructions and 16 double-word registers.
293 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
294 instructions and 32 double-word registers.
295 @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
296 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
297 @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
299 @code{+neon}: Alias for @code{+simd}.
300 @code{+neon-vfpv3}: Alias for @code{+simd}.
301 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
302 NEONv1 instructions with 32 double-word registers.
303 @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
304 double-word registers.
305 @code{+mp}: Enables Multiprocessing Extensions.
306 @code{+sec}: Enables Security Extensions.
307 @code{+nofp}: Disables all FPU and NEON instructions.
308 @code{+nosimd}: Disables all NEON instructions.
312 @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
313 @code{+vfpv4-d16}: Alias for @code{+fp}.
314 @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
315 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
316 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
317 conversion instructions and 16 double-word registers.
318 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
319 instructions and 32 double-word registers.
320 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
321 @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
322 double-word registers.
323 @code{+neon-vfpv4}: Alias for @code{+simd}.
324 @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
326 @code{+neon-vfpv3}: Alias for @code{+neon}.
327 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
328 NEONv1 instructions with 32 double-word registers.
329 double-word registers.
330 @code{+nofp}: Disables all FPU and NEON instructions.
331 @code{+nosimd}: Disables all NEON instructions.
335 @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
336 double-word registers.
337 @code{+vfpv3xd}: Alias for @code{+fp.sp}.
338 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
339 @code{+vfpv3-d16}: Alias for @code{+fp}.
340 @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
341 floating-point conversion instructions with 16 double-word registers.
342 @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
343 conversion instructions with 16 double-word registers.
344 @code{+idiv}: Enables integer division instructions in ARM mode.
345 @code{+nofp}: Disables all FPU instructions.
349 @code{+fp}: Enables single-precision only VFPv4 instructions with 16
350 double-word registers.
351 @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
352 @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
353 double-word registers.
354 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
355 @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
356 @code{+nofp}: Disables all FPU instructions.
358 For @code{armv8-m.main}:
360 @code{+dsp}: Enables DSP Extension.
361 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
362 double-word registers.
363 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
364 @code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
365 @code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
366 @code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
367 @code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
368 @code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
369 @code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
370 @code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
371 @code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
372 @code{+nofp}: Disables all FPU instructions.
373 @code{+nodsp}: Disables DSP Extension.
375 For @code{armv8.1-m.main}:
377 @code{+dsp}: Enables DSP Extension.
378 @code{+fp}: Enables single and half precision scalar Floating Point Extensions
379 for Armv8.1-M Mainline with 16 double-word registers.
380 @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
381 Armv8.1-M Mainline, implies @code{+fp}.
382 @code{+mve}: Enables integer only M-profile Vector Extension for
383 Armv8.1-M Mainline, implies @code{+dsp}.
384 @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
385 Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
386 @code{+nofp}: Disables all FPU instructions.
387 @code{+nodsp}: Disables DSP Extension.
388 @code{+nomve}: Disables all M-profile Vector Extensions.
392 @code{+crc}: Enables CRC32 Extension.
393 @code{+simd}: Enables VFP and NEON for Armv8-A.
394 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
396 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
397 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
399 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
400 @code{+nocrypto}: Disables Cryptography Extensions.
402 For @code{armv8.1-a}:
404 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
405 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
407 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
408 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
410 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
411 @code{+nocrypto}: Disables Cryptography Extensions.
413 For @code{armv8.2-a} and @code{armv8.3-a}:
415 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
416 @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
417 @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
418 for Armv8.2-A, implies @code{+fp16}.
419 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
421 @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
423 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
424 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
426 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
427 @code{+nocrypto}: Disables Cryptography Extensions.
429 For @code{armv8.4-a}:
431 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
433 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
434 Variant Extensions for Armv8.2-A, implies @code{+simd}.
435 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
437 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
438 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
440 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
441 @code{+nocryptp}: Disables Cryptography Extensions.
443 For @code{armv8.5-a}:
445 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
447 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
448 Variant Extensions for Armv8.2-A, implies @code{+simd}.
449 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
451 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
452 @code{+nocryptp}: Disables Cryptography Extensions.
455 @cindex @code{-mfpu=} command-line option, ARM
456 @item -mfpu=@var{floating-point-format}
458 This option specifies the floating point format to assemble for. The
459 assembler will issue an error message if an attempt is made to assemble
460 an instruction which will not execute on the target floating point unit.
461 The following format options are recognized:
481 @code{vfpv3-d16-fp16},
498 @code{neon-fp-armv8},
499 @code{crypto-neon-fp-armv8},
500 @code{neon-fp-armv8.1}
502 @code{crypto-neon-fp-armv8.1}.
504 In addition to determining which instructions are assembled, this option
505 also affects the way in which the @code{.double} assembler directive behaves
506 when assembling little-endian code.
508 The default is dependent on the processor selected. For Architecture 5 or
509 later, the default is to assemble for VFP instructions; for earlier
510 architectures the default is to assemble for FPA instructions.
512 @cindex @code{-mfp16-format=} command-line option
513 @item -mfp16-format=@var{format}
514 This option specifies the half-precision floating point format to use
515 when assembling floating point numbers emitted by the @code{.float16}
517 The following format options are recognized:
520 If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
521 point format is used, if @code{alternative} is specified then the Arm
522 alternative half-precision format is used. If this option is set on the
523 command line then the format is fixed and cannot be changed with
524 the @code{float16_format} directive. If this value is not set then
525 the IEEE 754-2008 format is used until the format is explicitly set with
526 the @code{float16_format} directive.
528 @cindex @code{-mthumb} command-line option, ARM
530 This option specifies that the assembler should start assembling Thumb
531 instructions; that is, it should behave as though the file starts with a
532 @code{.code 16} directive.
534 @cindex @code{-mthumb-interwork} command-line option, ARM
535 @item -mthumb-interwork
536 This option specifies that the output generated by the assembler should
537 be marked as supporting interworking. It also affects the behaviour
538 of the @code{ADR} and @code{ADRL} pseudo opcodes.
540 @cindex @code{-mimplicit-it} command-line option, ARM
541 @item -mimplicit-it=never
542 @itemx -mimplicit-it=always
543 @itemx -mimplicit-it=arm
544 @itemx -mimplicit-it=thumb
545 The @code{-mimplicit-it} option controls the behavior of the assembler when
546 conditional instructions are not enclosed in IT blocks.
547 There are four possible behaviors.
548 If @code{never} is specified, such constructs cause a warning in ARM
549 code and an error in Thumb-2 code.
550 If @code{always} is specified, such constructs are accepted in both
551 ARM and Thumb-2 code, where the IT instruction is added implicitly.
552 If @code{arm} is specified, such constructs are accepted in ARM code
553 and cause an error in Thumb-2 code.
554 If @code{thumb} is specified, such constructs cause a warning in ARM
555 code and are accepted in Thumb-2 code. If you omit this option, the
556 behavior is equivalent to @code{-mimplicit-it=arm}.
558 @cindex @code{-mapcs-26} command-line option, ARM
559 @cindex @code{-mapcs-32} command-line option, ARM
562 These options specify that the output generated by the assembler should
563 be marked as supporting the indicated version of the Arm Procedure.
566 @cindex @code{-matpcs} command-line option, ARM
568 This option specifies that the output generated by the assembler should
569 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
570 enabled this option will cause the assembler to create an empty
571 debugging section in the object file called .arm.atpcs. Debuggers can
572 use this to determine the ABI being used by.
574 @cindex @code{-mapcs-float} command-line option, ARM
576 This indicates the floating point variant of the APCS should be
577 used. In this variant floating point arguments are passed in FP
578 registers rather than integer registers.
580 @cindex @code{-mapcs-reentrant} command-line option, ARM
581 @item -mapcs-reentrant
582 This indicates that the reentrant variant of the APCS should be used.
583 This variant supports position independent code.
585 @cindex @code{-mfloat-abi=} command-line option, ARM
586 @item -mfloat-abi=@var{abi}
587 This option specifies that the output generated by the assembler should be
588 marked as using specified floating point ABI.
589 The following values are recognized:
595 @cindex @code{-eabi=} command-line option, ARM
596 @item -meabi=@var{ver}
597 This option specifies which EABI version the produced object files should
599 The following values are recognized:
605 @cindex @code{-EB} command-line option, ARM
607 This option specifies that the output generated by the assembler should
608 be marked as being encoded for a big-endian processor.
610 Note: If a program is being built for a system with big-endian data
611 and little-endian instructions then it should be assembled with the
612 @option{-EB} option, (all of it, code and data) and then linked with
613 the @option{--be8} option. This will reverse the endianness of the
614 instructions back to little-endian, but leave the data as big-endian.
616 @cindex @code{-EL} command-line option, ARM
618 This option specifies that the output generated by the assembler should
619 be marked as being encoded for a little-endian processor.
621 @cindex @code{-k} command-line option, ARM
622 @cindex PIC code generation for ARM
624 This option specifies that the output of the assembler should be marked
625 as position-independent code (PIC).
627 @cindex @code{--fix-v4bx} command-line option, ARM
629 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
630 the linker option of the same name.
632 @cindex @code{-mwarn-deprecated} command-line option, ARM
633 @item -mwarn-deprecated
634 @itemx -mno-warn-deprecated
635 Enable or disable warnings about using deprecated options or
636 features. The default is to warn.
638 @cindex @code{-mccs} command-line option, ARM
640 Turns on CodeComposer Studio assembly syntax compatibility mode.
642 @cindex @code{-mwarn-syms} command-line option, ARM
644 @itemx -mno-warn-syms
645 Enable or disable warnings about symbols that match the names of ARM
646 instructions. The default is to warn.
654 * ARM-Instruction-Set:: Instruction Set
655 * ARM-Chars:: Special Characters
656 * ARM-Regs:: Register Names
657 * ARM-Relocations:: Relocations
658 * ARM-Neon-Alignment:: NEON Alignment Specifiers
661 @node ARM-Instruction-Set
662 @subsection Instruction Set Syntax
663 Two slightly different syntaxes are support for ARM and THUMB
664 instructions. The default, @code{divided}, uses the old style where
665 ARM and THUMB instructions had their own, separate syntaxes. The new,
666 @code{unified} syntax, which can be selected via the @code{.syntax}
667 directive, and has the following main features:
671 Immediate operands do not require a @code{#} prefix.
674 The @code{IT} instruction may appear, and if it does it is validated
675 against subsequent conditional affixes. In ARM mode it does not
676 generate machine code, in THUMB mode it does.
679 For ARM instructions the conditional affixes always appear at the end
680 of the instruction. For THUMB instructions conditional affixes can be
681 used, but only inside the scope of an @code{IT} instruction.
684 All of the instructions new to the V6T2 architecture (and later) are
685 available. (Only a few such instructions can be written in the
686 @code{divided} syntax).
689 The @code{.N} and @code{.W} suffixes are recognized and honored.
692 All instructions set the flags if and only if they have an @code{s}
697 @subsection Special Characters
699 @cindex line comment character, ARM
700 @cindex ARM line comment character
701 The presence of a @samp{@@} anywhere on a line indicates the start of
702 a comment that extends to the end of that line.
704 If a @samp{#} appears as the first character of a line then the whole
705 line is treated as a comment, but in this case the line could also be
706 a logical line number directive (@pxref{Comments}) or a preprocessor
707 control command (@pxref{Preprocessing}).
709 @cindex line separator, ARM
710 @cindex statement separator, ARM
711 @cindex ARM line separator
712 The @samp{;} character can be used instead of a newline to separate
715 @cindex immediate character, ARM
716 @cindex ARM immediate character
717 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
719 @cindex identifiers, ARM
720 @cindex ARM identifiers
721 *TODO* Explain about /data modifier on symbols.
724 @subsection Register Names
726 @cindex ARM register names
727 @cindex register names, ARM
728 *TODO* Explain about ARM register naming, and the predefined names.
730 @node ARM-Relocations
731 @subsection ARM relocation generation
733 @cindex data relocations, ARM
734 @cindex ARM data relocations
735 Specific data relocations can be generated by putting the relocation name
736 in parentheses after the symbol name. For example:
742 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
744 The following relocations are supported:
760 For compatibility with older toolchains the assembler also accepts
761 @code{(PLT)} after branch targets. On legacy targets this will
762 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
763 targets it will encode either the @samp{R_ARM_CALL} or
764 @samp{R_ARM_JUMP24} relocation, as appropriate.
766 @cindex MOVW and MOVT relocations, ARM
767 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
768 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
769 respectively. For example to load the 32-bit address of foo into r0:
772 MOVW r0, #:lower16:foo
773 MOVT r0, #:upper16:foo
776 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
777 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
778 generated by prefixing the value with @samp{#:lower0_7:#},
779 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
780 respectively. For example to load the 32-bit address of foo into r0:
783 MOVS r0, #:upper8_15:#foo
785 ADDS r0, #:upper0_7:#foo
787 ADDS r0, #:lower8_15:#foo
789 ADDS r0, #:lower0_7:#foo
792 @node ARM-Neon-Alignment
793 @subsection NEON Alignment Specifiers
795 @cindex alignment for NEON instructions
796 Some NEON load/store instructions allow an optional address
798 The ARM documentation specifies that this is indicated by
799 @samp{@@ @var{align}}. However GAS already interprets
800 the @samp{@@} character as a "line comment" start,
801 so @samp{: @var{align}} is used instead. For example:
804 vld1.8 @{q0@}, [r0, :128]
807 @node ARM Floating Point
808 @section Floating Point
810 @cindex floating point, ARM (@sc{ieee})
811 @cindex ARM floating point (@sc{ieee})
812 The ARM family uses @sc{ieee} floating-point numbers.
815 @section ARM Machine Directives
817 @cindex machine directives, ARM
818 @cindex ARM machine directives
821 @c AAAAAAAAAAAAAAAAAAAAAAAAA
824 @cindex @code{.2byte} directive, ARM
825 @cindex @code{.4byte} directive, ARM
826 @cindex @code{.8byte} directive, ARM
827 @item .2byte @var{expression} [, @var{expression}]*
828 @itemx .4byte @var{expression} [, @var{expression}]*
829 @itemx .8byte @var{expression} [, @var{expression}]*
830 These directives write 2, 4 or 8 byte values to the output section.
833 @cindex @code{.align} directive, ARM
834 @item .align @var{expression} [, @var{expression}]
835 This is the generic @var{.align} directive. For the ARM however if the
836 first argument is zero (ie no alignment is needed) the assembler will
837 behave as if the argument had been 2 (ie pad to the next four byte
838 boundary). This is for compatibility with ARM's own assembler.
840 @cindex @code{.arch} directive, ARM
841 @item .arch @var{name}
842 Select the target architecture. Valid values for @var{name} are the same as
843 for the @option{-march} command-line option without the instruction set
846 Specifying @code{.arch} clears any previously selected architecture
849 @cindex @code{.arch_extension} directive, ARM
850 @item .arch_extension @var{name}
851 Add or remove an architecture extension to the target architecture. Valid
852 values for @var{name} are the same as those accepted as architectural
853 extensions by the @option{-mcpu} and @option{-march} command-line options.
855 @code{.arch_extension} may be used multiple times to add or remove extensions
856 incrementally to the architecture being compiled for.
858 @cindex @code{.arm} directive, ARM
860 This performs the same action as @var{.code 32}.
862 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
864 @cindex @code{.bss} directive, ARM
866 This directive switches to the @code{.bss} section.
868 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
870 @cindex @code{.cantunwind} directive, ARM
872 Prevents unwinding through the current function. No personality routine
873 or exception table data is required or permitted.
875 @cindex @code{.code} directive, ARM
876 @item .code @code{[16|32]}
877 This directive selects the instruction set being generated. The value 16
878 selects Thumb, with the value 32 selecting ARM.
880 @cindex @code{.cpu} directive, ARM
881 @item .cpu @var{name}
882 Select the target processor. Valid values for @var{name} are the same as
883 for the @option{-mcpu} command-line option without the instruction set
886 Specifying @code{.cpu} clears any previously selected architecture
889 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
891 @cindex @code{.dn} and @code{.qn} directives, ARM
892 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
893 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
895 The @code{dn} and @code{qn} directives are used to create typed
896 and/or indexed register aliases for use in Advanced SIMD Extension
897 (Neon) instructions. The former should be used to create aliases
898 of double-precision registers, and the latter to create aliases of
899 quad-precision registers.
901 If these directives are used to create typed aliases, those aliases can
902 be used in Neon instructions instead of writing types after the mnemonic
903 or after each operand. For example:
912 This is equivalent to writing the following:
918 Aliases created using @code{dn} or @code{qn} can be destroyed using
921 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
923 @cindex @code{.eabi_attribute} directive, ARM
924 @item .eabi_attribute @var{tag}, @var{value}
925 Set the EABI object attribute @var{tag} to @var{value}.
927 The @var{tag} is either an attribute number, or one of the following:
928 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
929 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
930 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
931 @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
932 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
933 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
934 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
935 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
936 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
937 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
938 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
939 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
940 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
941 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
942 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
943 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
944 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
945 @code{Tag_conformance}, @code{Tag_T2EE_use},
946 @code{Tag_Virtualization_use}
948 The @var{value} is either a @code{number}, @code{"string"}, or
949 @code{number, "string"} depending on the tag.
951 Note - the following legacy values are also accepted by @var{tag}:
952 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
953 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
955 @cindex @code{.even} directive, ARM
957 This directive aligns to an even-numbered address.
959 @cindex @code{.extend} directive, ARM
960 @cindex @code{.ldouble} directive, ARM
961 @item .extend @var{expression} [, @var{expression}]*
962 @itemx .ldouble @var{expression} [, @var{expression}]*
963 These directives write 12byte long double floating-point values to the
964 output section. These are not compatible with current ARM processors
967 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
969 @cindex @code{.float16} directive, ARM
970 @item .float16 @var{value [,...,value_n]}
971 Place the half precision floating point representation of one or more
972 floating-point values into the current section. The exact format of the
973 encoding is specified by @code{.float16_format}. If the format has not
974 been explicitly set yet (either via the @code{.float16_format} directive or
975 the command line option) then the IEEE 754-2008 format is used.
977 @cindex @code{.float16_format} directive, ARM
978 @item .float16_format @var{format}
979 Set the format to use when encoding float16 values emitted by
980 the @code{.float16} directive.
981 Once the format has been set it cannot be changed.
982 @code{format} should be one of the following: @code{ieee} (encode in
983 the IEEE 754-2008 half precision format) or @code{alternative} (encode in
984 the Arm alternative half precision format).
987 @cindex @code{.fnend} directive, ARM
989 Marks the end of a function with an unwind table entry. The unwind index
990 table entry is created when this directive is processed.
992 If no personality routine has been specified then standard personality
993 routine 0 or 1 will be used, depending on the number of unwind opcodes
997 @cindex @code{.fnstart} directive, ARM
999 Marks the start of a function with an unwind table entry.
1001 @cindex @code{.force_thumb} directive, ARM
1003 This directive forces the selection of Thumb instructions, even if the
1004 target processor does not support those instructions
1006 @cindex @code{.fpu} directive, ARM
1007 @item .fpu @var{name}
1008 Select the floating-point unit to assemble for. Valid values for @var{name}
1009 are the same as for the @option{-mfpu} command-line option.
1011 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
1012 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
1014 @cindex @code{.handlerdata} directive, ARM
1016 Marks the end of the current function, and the start of the exception table
1017 entry for that function. Anything between this directive and the
1018 @code{.fnend} directive will be added to the exception table entry.
1020 Must be preceded by a @code{.personality} or @code{.personalityindex}
1023 @c IIIIIIIIIIIIIIIIIIIIIIIIII
1025 @cindex @code{.inst} directive, ARM
1026 @item .inst @var{opcode} [ , @dots{} ]
1027 @itemx .inst.n @var{opcode} [ , @dots{} ]
1028 @itemx .inst.w @var{opcode} [ , @dots{} ]
1029 Generates the instruction corresponding to the numerical value @var{opcode}.
1030 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
1031 specified explicitly, overriding the normal encoding rules.
1033 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
1034 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
1035 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
1037 @item .ldouble @var{expression} [, @var{expression}]*
1040 @cindex @code{.ltorg} directive, ARM
1042 This directive causes the current contents of the literal pool to be
1043 dumped into the current section (which is assumed to be the .text
1044 section) at the current location (aligned to a word boundary).
1045 @code{GAS} maintains a separate literal pool for each section and each
1046 sub-section. The @code{.ltorg} directive will only affect the literal
1047 pool of the current section and sub-section. At the end of assembly
1048 all remaining, un-empty literal pools will automatically be dumped.
1050 Note - older versions of @code{GAS} would dump the current literal
1051 pool any time a section change occurred. This is no longer done, since
1052 it prevents accurate control of the placement of literal pools.
1054 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
1056 @cindex @code{.movsp} directive, ARM
1057 @item .movsp @var{reg} [, #@var{offset}]
1058 Tell the unwinder that @var{reg} contains an offset from the current
1059 stack pointer. If @var{offset} is not specified then it is assumed to be
1062 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
1063 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
1065 @cindex @code{.object_arch} directive, ARM
1066 @item .object_arch @var{name}
1067 Override the architecture recorded in the EABI object attribute section.
1068 Valid values for @var{name} are the same as for the @code{.arch} directive.
1069 Typically this is useful when code uses runtime detection of CPU features.
1071 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
1073 @cindex @code{.packed} directive, ARM
1074 @item .packed @var{expression} [, @var{expression}]*
1075 This directive writes 12-byte packed floating-point values to the
1076 output section. These are not compatible with current ARM processors
1080 @cindex @code{.pad} directive, ARM
1081 @item .pad #@var{count}
1082 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
1083 A positive value indicates the function prologue allocated stack space by
1084 decrementing the stack pointer.
1086 @cindex @code{.personality} directive, ARM
1087 @item .personality @var{name}
1088 Sets the personality routine for the current function to @var{name}.
1090 @cindex @code{.personalityindex} directive, ARM
1091 @item .personalityindex @var{index}
1092 Sets the personality routine for the current function to the EABI standard
1093 routine number @var{index}
1095 @cindex @code{.pool} directive, ARM
1097 This is a synonym for .ltorg.
1099 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
1100 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
1102 @cindex @code{.req} directive, ARM
1103 @item @var{name} .req @var{register name}
1104 This creates an alias for @var{register name} called @var{name}. For
1111 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
1114 @cindex @code{.save} directive, ARM
1115 @item .save @var{reglist}
1116 Generate unwinder annotations to restore the registers in @var{reglist}.
1117 The format of @var{reglist} is the same as the corresponding store-multiple
1121 @exdent @emph{core registers}
1122 .save @{r4, r5, r6, lr@}
1123 stmfd sp!, @{r4, r5, r6, lr@}
1124 @exdent @emph{FPA registers}
1127 @exdent @emph{VFP registers}
1128 .save @{d8, d9, d10@}
1129 fstmdx sp!, @{d8, d9, d10@}
1130 @exdent @emph{iWMMXt registers}
1131 .save @{wr10, wr11@}
1132 wstrd wr11, [sp, #-8]!
1133 wstrd wr10, [sp, #-8]!
1136 wstrd wr11, [sp, #-8]!
1138 wstrd wr10, [sp, #-8]!
1142 @cindex @code{.setfp} directive, ARM
1143 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
1144 Make all unwinder annotations relative to a frame pointer. Without this
1145 the unwinder will use offsets from the stack pointer.
1147 The syntax of this directive is the same as the @code{add} or @code{mov}
1148 instruction used to set the frame pointer. @var{spreg} must be either
1149 @code{sp} or mentioned in a previous @code{.movsp} directive.
1159 @cindex @code{.secrel32} directive, ARM
1160 @item .secrel32 @var{expression} [, @var{expression}]*
1161 This directive emits relocations that evaluate to the section-relative
1162 offset of each expression's symbol. This directive is only supported
1165 @cindex @code{.syntax} directive, ARM
1166 @item .syntax [@code{unified} | @code{divided}]
1167 This directive sets the Instruction Set Syntax as described in the
1168 @ref{ARM-Instruction-Set} section.
1170 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
1172 @cindex @code{.thumb} directive, ARM
1174 This performs the same action as @var{.code 16}.
1176 @cindex @code{.thumb_func} directive, ARM
1178 This directive specifies that the following symbol is the name of a
1179 Thumb encoded function. This information is necessary in order to allow
1180 the assembler and linker to generate correct code for interworking
1181 between Arm and Thumb instructions and should be used even if
1182 interworking is not going to be performed. The presence of this
1183 directive also implies @code{.thumb}
1185 This directive is not necessary when generating EABI objects. On these
1186 targets the encoding is implicit when generating Thumb code.
1188 @cindex @code{.thumb_set} directive, ARM
1190 This performs the equivalent of a @code{.set} directive in that it
1191 creates a symbol which is an alias for another symbol (possibly not yet
1192 defined). This directive also has the added property in that it marks
1193 the aliased symbol as being a thumb function entry point, in the same
1194 way that the @code{.thumb_func} directive does.
1196 @cindex @code{.tlsdescseq} directive, ARM
1197 @item .tlsdescseq @var{tls-variable}
1198 This directive is used to annotate parts of an inlined TLS descriptor
1199 trampoline. Normally the trampoline is provided by the linker, and
1200 this directive is not needed.
1202 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
1204 @cindex @code{.unreq} directive, ARM
1205 @item .unreq @var{alias-name}
1206 This undefines a register alias which was previously defined using the
1207 @code{req}, @code{dn} or @code{qn} directives. For example:
1214 An error occurs if the name is undefined. Note - this pseudo op can
1215 be used to delete builtin in register name aliases (eg 'r0'). This
1216 should only be done if it is really necessary.
1218 @cindex @code{.unwind_raw} directive, ARM
1219 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
1220 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
1221 the stack pointer by @var{offset} bytes.
1223 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1226 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1228 @cindex @code{.vsave} directive, ARM
1229 @item .vsave @var{vfp-reglist}
1230 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1231 using FLDMD. Also works for VFPv3 registers
1232 that are to be restored using VLDM.
1233 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1237 @exdent @emph{VFP registers}
1238 .vsave @{d8, d9, d10@}
1239 fstmdd sp!, @{d8, d9, d10@}
1240 @exdent @emph{VFPv3 registers}
1241 .vsave @{d15, d16, d17@}
1242 vstm sp!, @{d15, d16, d17@}
1245 Since FLDMX and FSTMX are now deprecated, this directive should be
1246 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1248 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1249 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1250 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1251 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1259 @cindex opcodes for ARM
1260 @code{@value{AS}} implements all the standard ARM opcodes. It also
1261 implements several pseudo opcodes, including several synthetic load
1266 @cindex @code{NOP} pseudo op, ARM
1272 This pseudo op will always evaluate to a legal ARM instruction that does
1273 nothing. Currently it will evaluate to MOV r0, r0.
1275 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1278 ldr <register> , = <expression>
1281 If expression evaluates to a numeric constant then a MOV or MVN
1282 instruction will be used in place of the LDR instruction, if the
1283 constant can be generated by either of these instructions. Otherwise
1284 the constant will be placed into the nearest literal pool (if it not
1285 already there) and a PC relative LDR instruction will be generated.
1287 @cindex @code{ADR reg,<label>} pseudo op, ARM
1290 adr <register> <label>
1293 This instruction will load the address of @var{label} into the indicated
1294 register. The instruction will evaluate to a PC relative ADD or SUB
1295 instruction depending upon where the label is located. If the label is
1296 out of range, or if it is not defined in the same file (and section) as
1297 the ADR instruction, then an error will be generated. This instruction
1298 will not make use of the literal pool.
1300 If @var{label} is a thumb function symbol, and thumb interworking has
1301 been enabled via the @option{-mthumb-interwork} option then the bottom
1302 bit of the value stored into @var{register} will be set. This allows
1303 the following sequence to work as expected:
1306 adr r0, thumb_function
1310 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1313 adrl <register> <label>
1316 This instruction will load the address of @var{label} into the indicated
1317 register. The instruction will evaluate to one or two PC relative ADD
1318 or SUB instructions depending upon where the label is located. If a
1319 second instruction is not needed a NOP instruction will be generated in
1320 its place, so that this instruction is always 8 bytes long.
1322 If the label is out of range, or if it is not defined in the same file
1323 (and section) as the ADRL instruction, then an error will be generated.
1324 This instruction will not make use of the literal pool.
1326 If @var{label} is a thumb function symbol, and thumb interworking has
1327 been enabled via the @option{-mthumb-interwork} option then the bottom
1328 bit of the value stored into @var{register} will be set.
1332 For information on the ARM or Thumb instruction sets, see @cite{ARM
1333 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1336 @node ARM Mapping Symbols
1337 @section Mapping Symbols
1339 The ARM ELF specification requires that special symbols be inserted
1340 into object files to mark certain features:
1346 At the start of a region of code containing ARM instructions.
1350 At the start of a region of code containing THUMB instructions.
1354 At the start of a region of data.
1358 The assembler will automatically insert these symbols for you - there
1359 is no need to code them yourself. Support for tagging symbols ($b,
1360 $f, $p and $m) which is also mentioned in the current ARM ELF
1361 specification is not implemented. This is because they have been
1362 dropped from the new EABI and so tools cannot rely upon their
1365 @node ARM Unwinding Tutorial
1368 The ABI for the ARM Architecture specifies a standard format for
1369 exception unwind information. This information is used when an
1370 exception is thrown to determine where control should be transferred.
1371 In particular, the unwind information is used to determine which
1372 function called the function that threw the exception, and which
1373 function called that one, and so forth. This information is also used
1374 to restore the values of callee-saved registers in the function
1375 catching the exception.
1377 If you are writing functions in assembly code, and those functions
1378 call other functions that throw exceptions, you must use assembly
1379 pseudo ops to ensure that appropriate exception unwind information is
1380 generated. Otherwise, if one of the functions called by your assembly
1381 code throws an exception, the run-time library will be unable to
1382 unwind the stack through your assembly code and your program will not
1385 To illustrate the use of these pseudo ops, we will examine the code
1386 that G++ generates for the following C++ input:
1389 void callee (int *);
1400 This example does not show how to throw or catch an exception from
1401 assembly code. That is a much more complex operation and should
1402 always be done in a high-level language, such as C++, that directly
1403 supports exceptions.
1405 The code generated by one particular version of G++ when compiling the
1412 @ Function supports interworking.
1413 @ args = 0, pretend = 0, frame = 8
1414 @ frame_needed = 1, uses_anonymous_args = 0
1436 Of course, the sequence of instructions varies based on the options
1437 you pass to GCC and on the version of GCC in use. The exact
1438 instructions are not important since we are focusing on the pseudo ops
1439 that are used to generate unwind information.
1441 An important assumption made by the unwinder is that the stack frame
1442 does not change during the body of the function. In particular, since
1443 we assume that the assembly code does not itself throw an exception,
1444 the only point where an exception can be thrown is from a call, such
1445 as the @code{bl} instruction above. At each call site, the same saved
1446 registers (including @code{lr}, which indicates the return address)
1447 must be located in the same locations relative to the frame pointer.
1449 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1450 op appears immediately before the first instruction of the function
1451 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1452 op appears immediately after the last instruction of the function.
1453 These pseudo ops specify the range of the function.
1455 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1456 @code{.pad}) matters; their exact locations are irrelevant. In the
1457 example above, the compiler emits the pseudo ops with particular
1458 instructions. That makes it easier to understand the code, but it is
1459 not required for correctness. It would work just as well to emit all
1460 of the pseudo ops other than @code{.fnend} in the same order, but
1461 immediately after @code{.fnstart}.
1463 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1464 indicates registers that have been saved to the stack so that they can
1465 be restored before the function returns. The argument to the
1466 @code{.save} pseudo op is a list of registers to save. If a register
1467 is ``callee-saved'' (as specified by the ABI) and is modified by the
1468 function you are writing, then your code must save the value before it
1469 is modified and restore the original value before the function
1470 returns. If an exception is thrown, the run-time library restores the
1471 values of these registers from their locations on the stack before
1472 returning control to the exception handler. (Of course, if an
1473 exception is not thrown, the function that contains the @code{.save}
1474 pseudo op restores these registers in the function epilogue, as is
1475 done with the @code{ldmfd} instruction above.)
1477 You do not have to save callee-saved registers at the very beginning
1478 of the function and you do not need to use the @code{.save} pseudo op
1479 immediately following the point at which the registers are saved.
1480 However, if you modify a callee-saved register, you must save it on
1481 the stack before modifying it and before calling any functions which
1482 might throw an exception. And, you must use the @code{.save} pseudo
1483 op to indicate that you have done so.
1485 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1486 modification of the stack pointer that does not save any registers.
1487 The argument is the number of bytes (in decimal) that are subtracted
1488 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1489 subtracting from the stack pointer increases the size of the stack.)
1491 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1492 indicates the register that contains the frame pointer. The first
1493 argument is the register that is set, which is typically @code{fp}.
1494 The second argument indicates the register from which the frame
1495 pointer takes its value. The third argument, if present, is the value
1496 (in decimal) added to the register specified by the second argument to
1497 compute the value of the frame pointer. You should not modify the
1498 frame pointer in the body of the function.
1500 If you do not use a frame pointer, then you should not use the
1501 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1502 should avoid modifying the stack pointer outside of the function
1503 prologue. Otherwise, the run-time library will be unable to find
1504 saved registers when it is unwinding the stack.
1506 The pseudo ops described above are sufficient for writing assembly
1507 code that calls functions which may throw exceptions. If you need to
1508 know more about the object-file format used to represent unwind
1509 information, you may consult the @cite{Exception Handling ABI for the
1510 ARM Architecture} available from @uref{http://infocenter.arm.com}.
projects / deliverable / binutils-gdb.git / blob