1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
122 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
123 @code{i80200} (Intel XScale processor)
124 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
127 The special name @code{all} may be used to allow the
128 assembler to accept instructions valid for any ARM processor.
130 In addition to the basic instruction set, the assembler can be told to
131 accept various extension mnemonics that extend the processor using the
132 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
133 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
134 are currently supported:
140 @cindex @code{-march=} command line option, ARM
141 @item -march=@var{architecture}[+@var{extension}@dots{}]
142 This option specifies the target architecture. The assembler will issue
143 an error message if an attempt is made to assemble an instruction which
144 will not execute on the target architecture. The following architecture
145 names are recognized:
173 If both @code{-mcpu} and
174 @code{-march} are specified, the assembler will use
175 the setting for @code{-mcpu}.
177 The architecture option can be extended with the same instruction set
178 extension options as the @code{-mcpu} option.
180 @cindex @code{-mfpu=} command line option, ARM
181 @item -mfpu=@var{floating-point-format}
183 This option specifies the floating point format to assemble for. The
184 assembler will issue an error message if an attempt is made to assemble
185 an instruction which will not execute on the target floating point unit.
186 The following format options are recognized:
212 In addition to determining which instructions are assembled, this option
213 also affects the way in which the @code{.double} assembler directive behaves
214 when assembling little-endian code.
216 The default is dependent on the processor selected. For Architecture 5 or
217 later, the default is to assembler for VFP instructions; for earlier
218 architectures the default is to assemble for FPA instructions.
220 @cindex @code{-mthumb} command line option, ARM
222 This option specifies that the assembler should start assembling Thumb
223 instructions; that is, it should behave as though the file starts with a
224 @code{.code 16} directive.
226 @cindex @code{-mthumb-interwork} command line option, ARM
227 @item -mthumb-interwork
228 This option specifies that the output generated by the assembler should
229 be marked as supporting interworking.
231 @cindex @code{-mimplicit-it} command line option, ARM
232 @item -mimplicit-it=never
233 @itemx -mimplicit-it=always
234 @itemx -mimplicit-it=arm
235 @itemx -mimplicit-it=thumb
236 The @code{-mimplicit-it} option controls the behavior of the assembler when
237 conditional instructions are not enclosed in IT blocks.
238 There are four possible behaviors.
239 If @code{never} is specified, such constructs cause a warning in ARM
240 code and an error in Thumb-2 code.
241 If @code{always} is specified, such constructs are accepted in both
242 ARM and Thumb-2 code, where the IT instruction is added implicitly.
243 If @code{arm} is specified, such constructs are accepted in ARM code
244 and cause an error in Thumb-2 code.
245 If @code{thumb} is specified, such constructs cause a warning in ARM
246 code and are accepted in Thumb-2 code. If you omit this option, the
247 behavior is equivalent to @code{-mimplicit-it=arm}.
249 @cindex @code{-mapcs-26} command line option, ARM
250 @cindex @code{-mapcs-32} command line option, ARM
253 These options specify that the output generated by the assembler should
254 be marked as supporting the indicated version of the Arm Procedure.
257 @cindex @code{-matpcs} command line option, ARM
259 This option specifies that the output generated by the assembler should
260 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
261 enabled this option will cause the assembler to create an empty
262 debugging section in the object file called .arm.atpcs. Debuggers can
263 use this to determine the ABI being used by.
265 @cindex @code{-mapcs-float} command line option, ARM
267 This indicates the floating point variant of the APCS should be
268 used. In this variant floating point arguments are passed in FP
269 registers rather than integer registers.
271 @cindex @code{-mapcs-reentrant} command line option, ARM
272 @item -mapcs-reentrant
273 This indicates that the reentrant variant of the APCS should be used.
274 This variant supports position independent code.
276 @cindex @code{-mfloat-abi=} command line option, ARM
277 @item -mfloat-abi=@var{abi}
278 This option specifies that the output generated by the assembler should be
279 marked as using specified floating point ABI.
280 The following values are recognized:
286 @cindex @code{-eabi=} command line option, ARM
287 @item -meabi=@var{ver}
288 This option specifies which EABI version the produced object files should
290 The following values are recognized:
296 @cindex @code{-EB} command line option, ARM
298 This option specifies that the output generated by the assembler should
299 be marked as being encoded for a big-endian processor.
301 @cindex @code{-EL} command line option, ARM
303 This option specifies that the output generated by the assembler should
304 be marked as being encoded for a little-endian processor.
306 @cindex @code{-k} command line option, ARM
307 @cindex PIC code generation for ARM
309 This option specifies that the output of the assembler should be marked
310 as position-independent code (PIC).
312 @cindex @code{--fix-v4bx} command line option, ARM
314 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
315 the linker option of the same name.
317 @cindex @code{-mwarn-deprecated} command line option, ARM
318 @item -mwarn-deprecated
319 @itemx -mno-warn-deprecated
320 Enable or disable warnings about using deprecated options or
321 features. The default is to warn.
329 * ARM-Instruction-Set:: Instruction Set
330 * ARM-Chars:: Special Characters
331 * ARM-Regs:: Register Names
332 * ARM-Relocations:: Relocations
335 @node ARM-Instruction-Set
336 @subsection Instruction Set Syntax
337 Two slightly different syntaxes are support for ARM and THUMB
338 instructions. The default, @code{divided}, uses the old style where
339 ARM and THUMB instructions had their own, separate syntaxes. The new,
340 @code{unified} syntax, which can be selected via the @code{.syntax}
341 directive, and has the following main features:
345 Immediate operands do not require a @code{#} prefix.
348 The @code{IT} instruction may appear, and if it does it is validated
349 against subsequent conditional affixes. In ARM mode it does not
350 generate machine code, in THUMB mode it does.
353 For ARM instructions the conditional affixes always appear at the end
354 of the instruction. For THUMB instructions conditional affixes can be
355 used, but only inside the scope of an @code{IT} instruction.
358 All of the instructions new to the V6T2 architecture (and later) are
359 available. (Only a few such instructions can be written in the
360 @code{divided} syntax).
363 The @code{.N} and @code{.W} suffixes are recognized and honored.
366 All instructions set the flags if and only if they have an @code{s}
371 @subsection Special Characters
373 @cindex line comment character, ARM
374 @cindex ARM line comment character
375 The presence of a @samp{@@} on a line indicates the start of a comment
376 that extends to the end of the current line. If a @samp{#} appears as
377 the first character of a line, the whole line is treated as a comment.
379 @cindex line separator, ARM
380 @cindex statement separator, ARM
381 @cindex ARM line separator
382 The @samp{;} character can be used instead of a newline to separate
385 @cindex immediate character, ARM
386 @cindex ARM immediate character
387 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
389 @cindex identifiers, ARM
390 @cindex ARM identifiers
391 *TODO* Explain about /data modifier on symbols.
394 @subsection Register Names
396 @cindex ARM register names
397 @cindex register names, ARM
398 *TODO* Explain about ARM register naming, and the predefined names.
400 @node ARM Floating Point
401 @section Floating Point
403 @cindex floating point, ARM (@sc{ieee})
404 @cindex ARM floating point (@sc{ieee})
405 The ARM family uses @sc{ieee} floating-point numbers.
407 @node ARM-Relocations
408 @subsection ARM relocation generation
410 @cindex data relocations, ARM
411 @cindex ARM data relocations
412 Specific data relocations can be generated by putting the relocation name
413 in parentheses after the symbol name. For example:
419 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
421 The following relocations are supported:
434 For compatibility with older toolchains the assembler also accepts
435 @code{(PLT)} after branch targets. This will generate the deprecated
436 @samp{R_ARM_PLT32} relocation.
438 @cindex MOVW and MOVT relocations, ARM
439 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
440 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
441 respectively. For example to load the 32-bit address of foo into r0:
444 MOVW r0, #:lower16:foo
445 MOVT r0, #:upper16:foo
449 @section ARM Machine Directives
451 @cindex machine directives, ARM
452 @cindex ARM machine directives
455 @c AAAAAAAAAAAAAAAAAAAAAAAAA
457 @cindex @code{.2byte} directive, ARM
458 @cindex @code{.4byte} directive, ARM
459 @cindex @code{.8byte} directive, ARM
460 @item .2byte @var{expression} [, @var{expression}]*
461 @itemx .4byte @var{expression} [, @var{expression}]*
462 @itemx .8byte @var{expression} [, @var{expression}]*
463 These directives write 2, 4 or 8 byte values to the output section.
465 @cindex @code{.align} directive, ARM
466 @item .align @var{expression} [, @var{expression}]
467 This is the generic @var{.align} directive. For the ARM however if the
468 first argument is zero (ie no alignment is needed) the assembler will
469 behave as if the argument had been 2 (ie pad to the next four byte
470 boundary). This is for compatibility with ARM's own assembler.
472 @cindex @code{.arch} directive, ARM
473 @item .arch @var{name}
474 Select the target architecture. Valid values for @var{name} are the same as
475 for the @option{-march} commandline option.
477 @cindex @code{.arm} directive, ARM
479 This performs the same action as @var{.code 32}.
482 @cindex @code{.pad} directive, ARM
483 @item .pad #@var{count}
484 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
485 A positive value indicates the function prologue allocated stack space by
486 decrementing the stack pointer.
488 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
490 @cindex @code{.bss} directive, ARM
492 This directive switches to the @code{.bss} section.
494 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
496 @cindex @code{.cantunwind} directive, ARM
498 Prevents unwinding through the current function. No personality routine
499 or exception table data is required or permitted.
501 @cindex @code{.code} directive, ARM
502 @item .code @code{[16|32]}
503 This directive selects the instruction set being generated. The value 16
504 selects Thumb, with the value 32 selecting ARM.
506 @cindex @code{.cpu} directive, ARM
507 @item .cpu @var{name}
508 Select the target processor. Valid values for @var{name} are the same as
509 for the @option{-mcpu} commandline option.
511 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
513 @cindex @code{.dn} and @code{.qn} directives, ARM
514 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
515 @item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
517 The @code{dn} and @code{qn} directives are used to create typed
518 and/or indexed register aliases for use in Advanced SIMD Extension
519 (Neon) instructions. The former should be used to create aliases
520 of double-precision registers, and the latter to create aliases of
521 quad-precision registers.
523 If these directives are used to create typed aliases, those aliases can
524 be used in Neon instructions instead of writing types after the mnemonic
525 or after each operand. For example:
534 This is equivalent to writing the following:
540 Aliases created using @code{dn} or @code{qn} can be destroyed using
543 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
545 @cindex @code{.eabi_attribute} directive, ARM
546 @item .eabi_attribute @var{tag}, @var{value}
547 Set the EABI object attribute @var{tag} to @var{value}.
549 The @var{tag} is either an attribute number, or one of the following:
550 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
551 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
552 @code{Tag_THUMB_ISA_use}, @code{Tag_VFP_arch}, @code{Tag_WMMX_arch},
553 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
554 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
555 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
556 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
557 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
558 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
559 @code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved},
560 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
561 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
562 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
563 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
564 @code{Tag_VFP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
565 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
566 @code{Tag_conformance}, @code{Tag_T2EE_use},
567 @code{Tag_Virtualization_use}, @code{Tag_MPextension_use}
569 The @var{value} is either a @code{number}, @code{"string"}, or
570 @code{number, "string"} depending on the tag.
572 @cindex @code{.even} directive, ARM
574 This directive aligns to an even-numbered address.
576 @cindex @code{.extend} directive, ARM
577 @cindex @code{.ldouble} directive, ARM
578 @item .extend @var{expression} [, @var{expression}]*
579 @itemx .ldouble @var{expression} [, @var{expression}]*
580 These directives write 12byte long double floating-point values to the
581 output section. These are not compatible with current ARM processors
584 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
587 @cindex @code{.fnend} directive, ARM
589 Marks the end of a function with an unwind table entry. The unwind index
590 table entry is created when this directive is processed.
592 If no personality routine has been specified then standard personality
593 routine 0 or 1 will be used, depending on the number of unwind opcodes
597 @cindex @code{.fnstart} directive, ARM
599 Marks the start of a function with an unwind table entry.
601 @cindex @code{.force_thumb} directive, ARM
603 This directive forces the selection of Thumb instructions, even if the
604 target processor does not support those instructions
606 @cindex @code{.fpu} directive, ARM
607 @item .fpu @var{name}
608 Select the floating-point unit to assemble for. Valid values for @var{name}
609 are the same as for the @option{-mfpu} commandline option.
611 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
612 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
614 @cindex @code{.handlerdata} directive, ARM
616 Marks the end of the current function, and the start of the exception table
617 entry for that function. Anything between this directive and the
618 @code{.fnend} directive will be added to the exception table entry.
620 Must be preceded by a @code{.personality} or @code{.personalityindex}
623 @c IIIIIIIIIIIIIIIIIIIIIIIIII
625 @cindex @code{.inst} directive, ARM
626 @item .inst @var{opcode} [ , @dots{} ]
627 @item .inst.n @var{opcode} [ , @dots{} ]
628 @item .inst.w @var{opcode} [ , @dots{} ]
629 Generates the instruction corresponding to the numerical value @var{opcode}.
630 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
631 specified explicitly, overriding the normal encoding rules.
633 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
634 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
635 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
637 @item .ldouble @var{expression} [, @var{expression}]*
640 @cindex @code{.ltorg} directive, ARM
642 This directive causes the current contents of the literal pool to be
643 dumped into the current section (which is assumed to be the .text
644 section) at the current location (aligned to a word boundary).
645 @code{GAS} maintains a separate literal pool for each section and each
646 sub-section. The @code{.ltorg} directive will only affect the literal
647 pool of the current section and sub-section. At the end of assembly
648 all remaining, un-empty literal pools will automatically be dumped.
650 Note - older versions of @code{GAS} would dump the current literal
651 pool any time a section change occurred. This is no longer done, since
652 it prevents accurate control of the placement of literal pools.
654 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
656 @cindex @code{.movsp} directive, ARM
657 @item .movsp @var{reg} [, #@var{offset}]
658 Tell the unwinder that @var{reg} contains an offset from the current
659 stack pointer. If @var{offset} is not specified then it is assumed to be
662 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
663 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
665 @cindex @code{.object_arch} directive, ARM
666 @item .object_arch @var{name}
667 Override the architecture recorded in the EABI object attribute section.
668 Valid values for @var{name} are the same as for the @code{.arch} directive.
669 Typically this is useful when code uses runtime detection of CPU features.
671 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
673 @cindex @code{.packed} directive, ARM
674 @item .packed @var{expression} [, @var{expression}]*
675 This directive writes 12-byte packed floating-point values to the
676 output section. These are not compatible with current ARM processors
679 @cindex @code{.pad} directive, ARM
680 @item .pad #@var{count}
681 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
682 A positive value indicates the function prologue allocated stack space by
683 decrementing the stack pointer.
685 @cindex @code{.personality} directive, ARM
686 @item .personality @var{name}
687 Sets the personality routine for the current function to @var{name}.
689 @cindex @code{.personalityindex} directive, ARM
690 @item .personalityindex @var{index}
691 Sets the personality routine for the current function to the EABI standard
692 routine number @var{index}
694 @cindex @code{.pool} directive, ARM
696 This is a synonym for .ltorg.
698 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
699 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
701 @cindex @code{.req} directive, ARM
702 @item @var{name} .req @var{register name}
703 This creates an alias for @var{register name} called @var{name}. For
710 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
713 @cindex @code{.save} directive, ARM
714 @item .save @var{reglist}
715 Generate unwinder annotations to restore the registers in @var{reglist}.
716 The format of @var{reglist} is the same as the corresponding store-multiple
720 @exdent @emph{core registers}
721 .save @{r4, r5, r6, lr@}
722 stmfd sp!, @{r4, r5, r6, lr@}
723 @exdent @emph{FPA registers}
726 @exdent @emph{VFP registers}
727 .save @{d8, d9, d10@}
728 fstmdx sp!, @{d8, d9, d10@}
729 @exdent @emph{iWMMXt registers}
731 wstrd wr11, [sp, #-8]!
732 wstrd wr10, [sp, #-8]!
735 wstrd wr11, [sp, #-8]!
737 wstrd wr10, [sp, #-8]!
741 @cindex @code{.setfp} directive, ARM
742 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
743 Make all unwinder annotations relative to a frame pointer. Without this
744 the unwinder will use offsets from the stack pointer.
746 The syntax of this directive is the same as the @code{sub} or @code{mov}
747 instruction used to set the frame pointer. @var{spreg} must be either
748 @code{sp} or mentioned in a previous @code{.movsp} directive.
758 @cindex @code{.secrel32} directive, ARM
759 @item .secrel32 @var{expression} [, @var{expression}]*
760 This directive emits relocations that evaluate to the section-relative
761 offset of each expression's symbol. This directive is only supported
764 @cindex @code{.syntax} directive, ARM
765 @item .syntax [@code{unified} | @code{divided}]
766 This directive sets the Instruction Set Syntax as described in the
767 @ref{ARM-Instruction-Set} section.
769 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
771 @cindex @code{.thumb} directive, ARM
773 This performs the same action as @var{.code 16}.
775 @cindex @code{.thumb_func} directive, ARM
777 This directive specifies that the following symbol is the name of a
778 Thumb encoded function. This information is necessary in order to allow
779 the assembler and linker to generate correct code for interworking
780 between Arm and Thumb instructions and should be used even if
781 interworking is not going to be performed. The presence of this
782 directive also implies @code{.thumb}
784 This directive is not neccessary when generating EABI objects. On these
785 targets the encoding is implicit when generating Thumb code.
787 @cindex @code{.thumb_set} directive, ARM
789 This performs the equivalent of a @code{.set} directive in that it
790 creates a symbol which is an alias for another symbol (possibly not yet
791 defined). This directive also has the added property in that it marks
792 the aliased symbol as being a thumb function entry point, in the same
793 way that the @code{.thumb_func} directive does.
795 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
797 @cindex @code{.unreq} directive, ARM
798 @item .unreq @var{alias-name}
799 This undefines a register alias which was previously defined using the
800 @code{req}, @code{dn} or @code{qn} directives. For example:
807 An error occurs if the name is undefined. Note - this pseudo op can
808 be used to delete builtin in register name aliases (eg 'r0'). This
809 should only be done if it is really necessary.
811 @cindex @code{.unwind_raw} directive, ARM
812 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
813 Insert one of more arbitary unwind opcode bytes, which are known to adjust
814 the stack pointer by @var{offset} bytes.
816 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
819 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
821 @cindex @code{.vsave} directive, ARM
822 @item .vsave @var{vfp-reglist}
823 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
824 using FLDMD. Also works for VFPv3 registers
825 that are to be restored using VLDM.
826 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
830 @exdent @emph{VFP registers}
831 .vsave @{d8, d9, d10@}
832 fstmdd sp!, @{d8, d9, d10@}
833 @exdent @emph{VFPv3 registers}
834 .vsave @{d15, d16, d17@}
835 vstm sp!, @{d15, d16, d17@}
838 Since FLDMX and FSTMX are now deprecated, this directive should be
839 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
841 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
842 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
843 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
844 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
852 @cindex opcodes for ARM
853 @code{@value{AS}} implements all the standard ARM opcodes. It also
854 implements several pseudo opcodes, including several synthetic load
859 @cindex @code{NOP} pseudo op, ARM
865 This pseudo op will always evaluate to a legal ARM instruction that does
866 nothing. Currently it will evaluate to MOV r0, r0.
868 @cindex @code{LDR reg,=<label>} pseudo op, ARM
871 ldr <register> , = <expression>
874 If expression evaluates to a numeric constant then a MOV or MVN
875 instruction will be used in place of the LDR instruction, if the
876 constant can be generated by either of these instructions. Otherwise
877 the constant will be placed into the nearest literal pool (if it not
878 already there) and a PC relative LDR instruction will be generated.
880 @cindex @code{ADR reg,<label>} pseudo op, ARM
883 adr <register> <label>
886 This instruction will load the address of @var{label} into the indicated
887 register. The instruction will evaluate to a PC relative ADD or SUB
888 instruction depending upon where the label is located. If the label is
889 out of range, or if it is not defined in the same file (and section) as
890 the ADR instruction, then an error will be generated. This instruction
891 will not make use of the literal pool.
893 @cindex @code{ADRL reg,<label>} pseudo op, ARM
896 adrl <register> <label>
899 This instruction will load the address of @var{label} into the indicated
900 register. The instruction will evaluate to one or two PC relative ADD
901 or SUB instructions depending upon where the label is located. If a
902 second instruction is not needed a NOP instruction will be generated in
903 its place, so that this instruction is always 8 bytes long.
905 If the label is out of range, or if it is not defined in the same file
906 (and section) as the ADRL instruction, then an error will be generated.
907 This instruction will not make use of the literal pool.
911 For information on the ARM or Thumb instruction sets, see @cite{ARM
912 Software Development Toolkit Reference Manual}, Advanced RISC Machines
915 @node ARM Mapping Symbols
916 @section Mapping Symbols
918 The ARM ELF specification requires that special symbols be inserted
919 into object files to mark certain features:
925 At the start of a region of code containing ARM instructions.
929 At the start of a region of code containing THUMB instructions.
933 At the start of a region of data.
937 The assembler will automatically insert these symbols for you - there
938 is no need to code them yourself. Support for tagging symbols ($b,
939 $f, $p and $m) which is also mentioned in the current ARM ELF
940 specification is not implemented. This is because they have been
941 dropped from the new EABI and so tools cannot rely upon their
944 @node ARM Unwinding Tutorial
947 The ABI for the ARM Architecture specifies a standard format for
948 exception unwind information. This information is used when an
949 exception is thrown to determine where control should be transferred.
950 In particular, the unwind information is used to determine which
951 function called the function that threw the exception, and which
952 function called that one, and so forth. This information is also used
953 to restore the values of callee-saved registers in the function
954 catching the exception.
956 If you are writing functions in assembly code, and those functions
957 call other functions that throw exceptions, you must use assembly
958 pseudo ops to ensure that appropriate exception unwind information is
959 generated. Otherwise, if one of the functions called by your assembly
960 code throws an exception, the run-time library will be unable to
961 unwind the stack through your assembly code and your program will not
964 To illustrate the use of these pseudo ops, we will examine the code
965 that G++ generates for the following C++ input:
979 This example does not show how to throw or catch an exception from
980 assembly code. That is a much more complex operation and should
981 always be done in a high-level language, such as C++, that directly
984 The code generated by one particular version of G++ when compiling the
991 @ Function supports interworking.
992 @ args = 0, pretend = 0, frame = 8
993 @ frame_needed = 1, uses_anonymous_args = 0
1015 Of course, the sequence of instructions varies based on the options
1016 you pass to GCC and on the version of GCC in use. The exact
1017 instructions are not important since we are focusing on the pseudo ops
1018 that are used to generate unwind information.
1020 An important assumption made by the unwinder is that the stack frame
1021 does not change during the body of the function. In particular, since
1022 we assume that the assembly code does not itself throw an exception,
1023 the only point where an exception can be thrown is from a call, such
1024 as the @code{bl} instruction above. At each call site, the same saved
1025 registers (including @code{lr}, which indicates the return address)
1026 must be located in the same locations relative to the frame pointer.
1028 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1029 op appears immediately before the first instruction of the function
1030 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1031 op appears immediately after the last instruction of the function.
1032 These pseudo ops specify the range of the function.
1034 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1035 @code{.pad}) matters; their exact locations are irrelevant. In the
1036 example above, the compiler emits the pseudo ops with particular
1037 instructions. That makes it easier to understand the code, but it is
1038 not required for correctness. It would work just as well to emit all
1039 of the pseudo ops other than @code{.fnend} in the same order, but
1040 immediately after @code{.fnstart}.
1042 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1043 indicates registers that have been saved to the stack so that they can
1044 be restored before the function returns. The argument to the
1045 @code{.save} pseudo op is a list of registers to save. If a register
1046 is ``callee-saved'' (as specified by the ABI) and is modified by the
1047 function you are writing, then your code must save the value before it
1048 is modified and restore the original value before the function
1049 returns. If an exception is thrown, the run-time library restores the
1050 values of these registers from their locations on the stack before
1051 returning control to the exception handler. (Of course, if an
1052 exception is not thrown, the function that contains the @code{.save}
1053 pseudo op restores these registers in the function epilogue, as is
1054 done with the @code{ldmfd} instruction above.)
1056 You do not have to save callee-saved registers at the very beginning
1057 of the function and you do not need to use the @code{.save} pseudo op
1058 immediately following the point at which the registers are saved.
1059 However, if you modify a callee-saved register, you must save it on
1060 the stack before modifying it and before calling any functions which
1061 might throw an exception. And, you must use the @code{.save} pseudo
1062 op to indicate that you have done so.
1064 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1065 modification of the stack pointer that does not save any registers.
1066 The argument is the number of bytes (in decimal) that are subtracted
1067 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1068 subtracting from the stack pointer increases the size of the stack.)
1070 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1071 indicates the register that contains the frame pointer. The first
1072 argument is the register that is set, which is typically @code{fp}.
1073 The second argument indicates the register from which the frame
1074 pointer takes its value. The third argument, if present, is the value
1075 (in decimal) added to the register specified by the second argument to
1076 compute the value of the frame pointer. You should not modify the
1077 frame pointer in the body of the function.
1079 If you do not use a frame pointer, then you should not use the
1080 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1081 should avoid modifying the stack pointer outside of the function
1082 prologue. Otherwise, the run-time library will be unable to find
1083 saved registers when it is unwinding the stack.
1085 The pseudo ops described above are sufficient for writing assembly
1086 code that calls functions which may throw exceptions. If you need to
1087 know more about the object-file format used to represent unwind
1088 information, you may consult the @cite{Exception Handling ABI for the
1089 ARM Architecture} available from @uref{http://infocenter.arm.com}.