1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
123 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
124 @code{i80200} (Intel XScale processor)
125 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
128 The special name @code{all} may be used to allow the
129 assembler to accept instructions valid for any ARM processor.
131 In addition to the basic instruction set, the assembler can be told to
132 accept various extension mnemonics that extend the processor using the
133 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
134 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
135 are currently supported:
141 @cindex @code{-march=} command line option, ARM
142 @item -march=@var{architecture}[+@var{extension}@dots{}]
143 This option specifies the target architecture. The assembler will issue
144 an error message if an attempt is made to assemble an instruction which
145 will not execute on the target architecture. The following architecture
146 names are recognized:
174 If both @code{-mcpu} and
175 @code{-march} are specified, the assembler will use
176 the setting for @code{-mcpu}.
178 The architecture option can be extended with the same instruction set
179 extension options as the @code{-mcpu} option.
181 @cindex @code{-mfpu=} command line option, ARM
182 @item -mfpu=@var{floating-point-format}
184 This option specifies the floating point format to assemble for. The
185 assembler will issue an error message if an attempt is made to assemble
186 an instruction which will not execute on the target floating point unit.
187 The following format options are recognized:
213 In addition to determining which instructions are assembled, this option
214 also affects the way in which the @code{.double} assembler directive behaves
215 when assembling little-endian code.
217 The default is dependent on the processor selected. For Architecture 5 or
218 later, the default is to assembler for VFP instructions; for earlier
219 architectures the default is to assemble for FPA instructions.
221 @cindex @code{-mthumb} command line option, ARM
223 This option specifies that the assembler should start assembling Thumb
224 instructions; that is, it should behave as though the file starts with a
225 @code{.code 16} directive.
227 @cindex @code{-mthumb-interwork} command line option, ARM
228 @item -mthumb-interwork
229 This option specifies that the output generated by the assembler should
230 be marked as supporting interworking.
232 @cindex @code{-mimplicit-it} command line option, ARM
233 @item -mimplicit-it=never
234 @itemx -mimplicit-it=always
235 @itemx -mimplicit-it=arm
236 @itemx -mimplicit-it=thumb
237 The @code{-mimplicit-it} option controls the behavior of the assembler when
238 conditional instructions are not enclosed in IT blocks.
239 There are four possible behaviors.
240 If @code{never} is specified, such constructs cause a warning in ARM
241 code and an error in Thumb-2 code.
242 If @code{always} is specified, such constructs are accepted in both
243 ARM and Thumb-2 code, where the IT instruction is added implicitly.
244 If @code{arm} is specified, such constructs are accepted in ARM code
245 and cause an error in Thumb-2 code.
246 If @code{thumb} is specified, such constructs cause a warning in ARM
247 code and are accepted in Thumb-2 code. If you omit this option, the
248 behavior is equivalent to @code{-mimplicit-it=arm}.
250 @cindex @code{-mapcs-26} command line option, ARM
251 @cindex @code{-mapcs-32} command line option, ARM
254 These options specify that the output generated by the assembler should
255 be marked as supporting the indicated version of the Arm Procedure.
258 @cindex @code{-matpcs} command line option, ARM
260 This option specifies that the output generated by the assembler should
261 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
262 enabled this option will cause the assembler to create an empty
263 debugging section in the object file called .arm.atpcs. Debuggers can
264 use this to determine the ABI being used by.
266 @cindex @code{-mapcs-float} command line option, ARM
268 This indicates the floating point variant of the APCS should be
269 used. In this variant floating point arguments are passed in FP
270 registers rather than integer registers.
272 @cindex @code{-mapcs-reentrant} command line option, ARM
273 @item -mapcs-reentrant
274 This indicates that the reentrant variant of the APCS should be used.
275 This variant supports position independent code.
277 @cindex @code{-mfloat-abi=} command line option, ARM
278 @item -mfloat-abi=@var{abi}
279 This option specifies that the output generated by the assembler should be
280 marked as using specified floating point ABI.
281 The following values are recognized:
287 @cindex @code{-eabi=} command line option, ARM
288 @item -meabi=@var{ver}
289 This option specifies which EABI version the produced object files should
291 The following values are recognized:
297 @cindex @code{-EB} command line option, ARM
299 This option specifies that the output generated by the assembler should
300 be marked as being encoded for a big-endian processor.
302 @cindex @code{-EL} command line option, ARM
304 This option specifies that the output generated by the assembler should
305 be marked as being encoded for a little-endian processor.
307 @cindex @code{-k} command line option, ARM
308 @cindex PIC code generation for ARM
310 This option specifies that the output of the assembler should be marked
311 as position-independent code (PIC).
313 @cindex @code{--fix-v4bx} command line option, ARM
315 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
316 the linker option of the same name.
318 @cindex @code{-mwarn-deprecated} command line option, ARM
319 @item -mwarn-deprecated
320 @itemx -mno-warn-deprecated
321 Enable or disable warnings about using deprecated options or
322 features. The default is to warn.
330 * ARM-Instruction-Set:: Instruction Set
331 * ARM-Chars:: Special Characters
332 * ARM-Regs:: Register Names
333 * ARM-Relocations:: Relocations
336 @node ARM-Instruction-Set
337 @subsection Instruction Set Syntax
338 Two slightly different syntaxes are support for ARM and THUMB
339 instructions. The default, @code{divided}, uses the old style where
340 ARM and THUMB instructions had their own, separate syntaxes. The new,
341 @code{unified} syntax, which can be selected via the @code{.syntax}
342 directive, and has the following main features:
346 Immediate operands do not require a @code{#} prefix.
349 The @code{IT} instruction may appear, and if it does it is validated
350 against subsequent conditional affixes. In ARM mode it does not
351 generate machine code, in THUMB mode it does.
354 For ARM instructions the conditional affixes always appear at the end
355 of the instruction. For THUMB instructions conditional affixes can be
356 used, but only inside the scope of an @code{IT} instruction.
359 All of the instructions new to the V6T2 architecture (and later) are
360 available. (Only a few such instructions can be written in the
361 @code{divided} syntax).
364 The @code{.N} and @code{.W} suffixes are recognized and honored.
367 All instructions set the flags if and only if they have an @code{s}
372 @subsection Special Characters
374 @cindex line comment character, ARM
375 @cindex ARM line comment character
376 The presence of a @samp{@@} on a line indicates the start of a comment
377 that extends to the end of the current line. If a @samp{#} appears as
378 the first character of a line, the whole line is treated as a comment.
380 @cindex line separator, ARM
381 @cindex statement separator, ARM
382 @cindex ARM line separator
383 The @samp{;} character can be used instead of a newline to separate
386 @cindex immediate character, ARM
387 @cindex ARM immediate character
388 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
390 @cindex identifiers, ARM
391 @cindex ARM identifiers
392 *TODO* Explain about /data modifier on symbols.
395 @subsection Register Names
397 @cindex ARM register names
398 @cindex register names, ARM
399 *TODO* Explain about ARM register naming, and the predefined names.
401 @node ARM Floating Point
402 @section Floating Point
404 @cindex floating point, ARM (@sc{ieee})
405 @cindex ARM floating point (@sc{ieee})
406 The ARM family uses @sc{ieee} floating-point numbers.
408 @node ARM-Relocations
409 @subsection ARM relocation generation
411 @cindex data relocations, ARM
412 @cindex ARM data relocations
413 Specific data relocations can be generated by putting the relocation name
414 in parentheses after the symbol name. For example:
420 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
422 The following relocations are supported:
435 For compatibility with older toolchains the assembler also accepts
436 @code{(PLT)} after branch targets. This will generate the deprecated
437 @samp{R_ARM_PLT32} relocation.
439 @cindex MOVW and MOVT relocations, ARM
440 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
441 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
442 respectively. For example to load the 32-bit address of foo into r0:
445 MOVW r0, #:lower16:foo
446 MOVT r0, #:upper16:foo
450 @section ARM Machine Directives
452 @cindex machine directives, ARM
453 @cindex ARM machine directives
456 @c AAAAAAAAAAAAAAAAAAAAAAAAA
458 @cindex @code{.2byte} directive, ARM
459 @cindex @code{.4byte} directive, ARM
460 @cindex @code{.8byte} directive, ARM
461 @item .2byte @var{expression} [, @var{expression}]*
462 @itemx .4byte @var{expression} [, @var{expression}]*
463 @itemx .8byte @var{expression} [, @var{expression}]*
464 These directives write 2, 4 or 8 byte values to the output section.
466 @cindex @code{.align} directive, ARM
467 @item .align @var{expression} [, @var{expression}]
468 This is the generic @var{.align} directive. For the ARM however if the
469 first argument is zero (ie no alignment is needed) the assembler will
470 behave as if the argument had been 2 (ie pad to the next four byte
471 boundary). This is for compatibility with ARM's own assembler.
473 @cindex @code{.arch} directive, ARM
474 @item .arch @var{name}
475 Select the target architecture. Valid values for @var{name} are the same as
476 for the @option{-march} commandline option.
478 @cindex @code{.arm} directive, ARM
480 This performs the same action as @var{.code 32}.
483 @cindex @code{.pad} directive, ARM
484 @item .pad #@var{count}
485 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
486 A positive value indicates the function prologue allocated stack space by
487 decrementing the stack pointer.
489 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
491 @cindex @code{.bss} directive, ARM
493 This directive switches to the @code{.bss} section.
495 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
497 @cindex @code{.cantunwind} directive, ARM
499 Prevents unwinding through the current function. No personality routine
500 or exception table data is required or permitted.
502 @cindex @code{.code} directive, ARM
503 @item .code @code{[16|32]}
504 This directive selects the instruction set being generated. The value 16
505 selects Thumb, with the value 32 selecting ARM.
507 @cindex @code{.cpu} directive, ARM
508 @item .cpu @var{name}
509 Select the target processor. Valid values for @var{name} are the same as
510 for the @option{-mcpu} commandline option.
512 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
514 @cindex @code{.dn} and @code{.qn} directives, ARM
515 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
516 @item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
518 The @code{dn} and @code{qn} directives are used to create typed
519 and/or indexed register aliases for use in Advanced SIMD Extension
520 (Neon) instructions. The former should be used to create aliases
521 of double-precision registers, and the latter to create aliases of
522 quad-precision registers.
524 If these directives are used to create typed aliases, those aliases can
525 be used in Neon instructions instead of writing types after the mnemonic
526 or after each operand. For example:
535 This is equivalent to writing the following:
541 Aliases created using @code{dn} or @code{qn} can be destroyed using
544 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
546 @cindex @code{.eabi_attribute} directive, ARM
547 @item .eabi_attribute @var{tag}, @var{value}
548 Set the EABI object attribute @var{tag} to @var{value}.
550 The @var{tag} is either an attribute number, or one of the following:
551 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
552 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
553 @code{Tag_THUMB_ISA_use}, @code{Tag_VFP_arch}, @code{Tag_WMMX_arch},
554 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
555 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
556 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
557 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
558 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
559 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
560 @code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved},
561 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
562 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
563 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
564 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
565 @code{Tag_VFP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
566 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
567 @code{Tag_conformance}, @code{Tag_T2EE_use},
568 @code{Tag_Virtualization_use}, @code{Tag_MPextension_use}
570 The @var{value} is either a @code{number}, @code{"string"}, or
571 @code{number, "string"} depending on the tag.
573 @cindex @code{.even} directive, ARM
575 This directive aligns to an even-numbered address.
577 @cindex @code{.extend} directive, ARM
578 @cindex @code{.ldouble} directive, ARM
579 @item .extend @var{expression} [, @var{expression}]*
580 @itemx .ldouble @var{expression} [, @var{expression}]*
581 These directives write 12byte long double floating-point values to the
582 output section. These are not compatible with current ARM processors
585 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
588 @cindex @code{.fnend} directive, ARM
590 Marks the end of a function with an unwind table entry. The unwind index
591 table entry is created when this directive is processed.
593 If no personality routine has been specified then standard personality
594 routine 0 or 1 will be used, depending on the number of unwind opcodes
598 @cindex @code{.fnstart} directive, ARM
600 Marks the start of a function with an unwind table entry.
602 @cindex @code{.force_thumb} directive, ARM
604 This directive forces the selection of Thumb instructions, even if the
605 target processor does not support those instructions
607 @cindex @code{.fpu} directive, ARM
608 @item .fpu @var{name}
609 Select the floating-point unit to assemble for. Valid values for @var{name}
610 are the same as for the @option{-mfpu} commandline option.
612 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
613 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
615 @cindex @code{.handlerdata} directive, ARM
617 Marks the end of the current function, and the start of the exception table
618 entry for that function. Anything between this directive and the
619 @code{.fnend} directive will be added to the exception table entry.
621 Must be preceded by a @code{.personality} or @code{.personalityindex}
624 @c IIIIIIIIIIIIIIIIIIIIIIIIII
626 @cindex @code{.inst} directive, ARM
627 @item .inst @var{opcode} [ , @dots{} ]
628 @item .inst.n @var{opcode} [ , @dots{} ]
629 @item .inst.w @var{opcode} [ , @dots{} ]
630 Generates the instruction corresponding to the numerical value @var{opcode}.
631 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
632 specified explicitly, overriding the normal encoding rules.
634 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
635 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
636 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
638 @item .ldouble @var{expression} [, @var{expression}]*
641 @cindex @code{.ltorg} directive, ARM
643 This directive causes the current contents of the literal pool to be
644 dumped into the current section (which is assumed to be the .text
645 section) at the current location (aligned to a word boundary).
646 @code{GAS} maintains a separate literal pool for each section and each
647 sub-section. The @code{.ltorg} directive will only affect the literal
648 pool of the current section and sub-section. At the end of assembly
649 all remaining, un-empty literal pools will automatically be dumped.
651 Note - older versions of @code{GAS} would dump the current literal
652 pool any time a section change occurred. This is no longer done, since
653 it prevents accurate control of the placement of literal pools.
655 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
657 @cindex @code{.movsp} directive, ARM
658 @item .movsp @var{reg} [, #@var{offset}]
659 Tell the unwinder that @var{reg} contains an offset from the current
660 stack pointer. If @var{offset} is not specified then it is assumed to be
663 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
664 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
666 @cindex @code{.object_arch} directive, ARM
667 @item .object_arch @var{name}
668 Override the architecture recorded in the EABI object attribute section.
669 Valid values for @var{name} are the same as for the @code{.arch} directive.
670 Typically this is useful when code uses runtime detection of CPU features.
672 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
674 @cindex @code{.packed} directive, ARM
675 @item .packed @var{expression} [, @var{expression}]*
676 This directive writes 12-byte packed floating-point values to the
677 output section. These are not compatible with current ARM processors
680 @cindex @code{.pad} directive, ARM
681 @item .pad #@var{count}
682 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
683 A positive value indicates the function prologue allocated stack space by
684 decrementing the stack pointer.
686 @cindex @code{.personality} directive, ARM
687 @item .personality @var{name}
688 Sets the personality routine for the current function to @var{name}.
690 @cindex @code{.personalityindex} directive, ARM
691 @item .personalityindex @var{index}
692 Sets the personality routine for the current function to the EABI standard
693 routine number @var{index}
695 @cindex @code{.pool} directive, ARM
697 This is a synonym for .ltorg.
699 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
700 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
702 @cindex @code{.req} directive, ARM
703 @item @var{name} .req @var{register name}
704 This creates an alias for @var{register name} called @var{name}. For
711 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
714 @cindex @code{.save} directive, ARM
715 @item .save @var{reglist}
716 Generate unwinder annotations to restore the registers in @var{reglist}.
717 The format of @var{reglist} is the same as the corresponding store-multiple
721 @exdent @emph{core registers}
722 .save @{r4, r5, r6, lr@}
723 stmfd sp!, @{r4, r5, r6, lr@}
724 @exdent @emph{FPA registers}
727 @exdent @emph{VFP registers}
728 .save @{d8, d9, d10@}
729 fstmdx sp!, @{d8, d9, d10@}
730 @exdent @emph{iWMMXt registers}
732 wstrd wr11, [sp, #-8]!
733 wstrd wr10, [sp, #-8]!
736 wstrd wr11, [sp, #-8]!
738 wstrd wr10, [sp, #-8]!
742 @cindex @code{.setfp} directive, ARM
743 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
744 Make all unwinder annotations relative to a frame pointer. Without this
745 the unwinder will use offsets from the stack pointer.
747 The syntax of this directive is the same as the @code{sub} or @code{mov}
748 instruction used to set the frame pointer. @var{spreg} must be either
749 @code{sp} or mentioned in a previous @code{.movsp} directive.
759 @cindex @code{.secrel32} directive, ARM
760 @item .secrel32 @var{expression} [, @var{expression}]*
761 This directive emits relocations that evaluate to the section-relative
762 offset of each expression's symbol. This directive is only supported
765 @cindex @code{.syntax} directive, ARM
766 @item .syntax [@code{unified} | @code{divided}]
767 This directive sets the Instruction Set Syntax as described in the
768 @ref{ARM-Instruction-Set} section.
770 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
772 @cindex @code{.thumb} directive, ARM
774 This performs the same action as @var{.code 16}.
776 @cindex @code{.thumb_func} directive, ARM
778 This directive specifies that the following symbol is the name of a
779 Thumb encoded function. This information is necessary in order to allow
780 the assembler and linker to generate correct code for interworking
781 between Arm and Thumb instructions and should be used even if
782 interworking is not going to be performed. The presence of this
783 directive also implies @code{.thumb}
785 This directive is not neccessary when generating EABI objects. On these
786 targets the encoding is implicit when generating Thumb code.
788 @cindex @code{.thumb_set} directive, ARM
790 This performs the equivalent of a @code{.set} directive in that it
791 creates a symbol which is an alias for another symbol (possibly not yet
792 defined). This directive also has the added property in that it marks
793 the aliased symbol as being a thumb function entry point, in the same
794 way that the @code{.thumb_func} directive does.
796 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
798 @cindex @code{.unreq} directive, ARM
799 @item .unreq @var{alias-name}
800 This undefines a register alias which was previously defined using the
801 @code{req}, @code{dn} or @code{qn} directives. For example:
808 An error occurs if the name is undefined. Note - this pseudo op can
809 be used to delete builtin in register name aliases (eg 'r0'). This
810 should only be done if it is really necessary.
812 @cindex @code{.unwind_raw} directive, ARM
813 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
814 Insert one of more arbitary unwind opcode bytes, which are known to adjust
815 the stack pointer by @var{offset} bytes.
817 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
820 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
822 @cindex @code{.vsave} directive, ARM
823 @item .vsave @var{vfp-reglist}
824 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
825 using FLDMD. Also works for VFPv3 registers
826 that are to be restored using VLDM.
827 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
831 @exdent @emph{VFP registers}
832 .vsave @{d8, d9, d10@}
833 fstmdd sp!, @{d8, d9, d10@}
834 @exdent @emph{VFPv3 registers}
835 .vsave @{d15, d16, d17@}
836 vstm sp!, @{d15, d16, d17@}
839 Since FLDMX and FSTMX are now deprecated, this directive should be
840 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
842 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
843 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
844 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
845 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
853 @cindex opcodes for ARM
854 @code{@value{AS}} implements all the standard ARM opcodes. It also
855 implements several pseudo opcodes, including several synthetic load
860 @cindex @code{NOP} pseudo op, ARM
866 This pseudo op will always evaluate to a legal ARM instruction that does
867 nothing. Currently it will evaluate to MOV r0, r0.
869 @cindex @code{LDR reg,=<label>} pseudo op, ARM
872 ldr <register> , = <expression>
875 If expression evaluates to a numeric constant then a MOV or MVN
876 instruction will be used in place of the LDR instruction, if the
877 constant can be generated by either of these instructions. Otherwise
878 the constant will be placed into the nearest literal pool (if it not
879 already there) and a PC relative LDR instruction will be generated.
881 @cindex @code{ADR reg,<label>} pseudo op, ARM
884 adr <register> <label>
887 This instruction will load the address of @var{label} into the indicated
888 register. The instruction will evaluate to a PC relative ADD or SUB
889 instruction depending upon where the label is located. If the label is
890 out of range, or if it is not defined in the same file (and section) as
891 the ADR instruction, then an error will be generated. This instruction
892 will not make use of the literal pool.
894 @cindex @code{ADRL reg,<label>} pseudo op, ARM
897 adrl <register> <label>
900 This instruction will load the address of @var{label} into the indicated
901 register. The instruction will evaluate to one or two PC relative ADD
902 or SUB instructions depending upon where the label is located. If a
903 second instruction is not needed a NOP instruction will be generated in
904 its place, so that this instruction is always 8 bytes long.
906 If the label is out of range, or if it is not defined in the same file
907 (and section) as the ADRL instruction, then an error will be generated.
908 This instruction will not make use of the literal pool.
912 For information on the ARM or Thumb instruction sets, see @cite{ARM
913 Software Development Toolkit Reference Manual}, Advanced RISC Machines
916 @node ARM Mapping Symbols
917 @section Mapping Symbols
919 The ARM ELF specification requires that special symbols be inserted
920 into object files to mark certain features:
926 At the start of a region of code containing ARM instructions.
930 At the start of a region of code containing THUMB instructions.
934 At the start of a region of data.
938 The assembler will automatically insert these symbols for you - there
939 is no need to code them yourself. Support for tagging symbols ($b,
940 $f, $p and $m) which is also mentioned in the current ARM ELF
941 specification is not implemented. This is because they have been
942 dropped from the new EABI and so tools cannot rely upon their
945 @node ARM Unwinding Tutorial
948 The ABI for the ARM Architecture specifies a standard format for
949 exception unwind information. This information is used when an
950 exception is thrown to determine where control should be transferred.
951 In particular, the unwind information is used to determine which
952 function called the function that threw the exception, and which
953 function called that one, and so forth. This information is also used
954 to restore the values of callee-saved registers in the function
955 catching the exception.
957 If you are writing functions in assembly code, and those functions
958 call other functions that throw exceptions, you must use assembly
959 pseudo ops to ensure that appropriate exception unwind information is
960 generated. Otherwise, if one of the functions called by your assembly
961 code throws an exception, the run-time library will be unable to
962 unwind the stack through your assembly code and your program will not
965 To illustrate the use of these pseudo ops, we will examine the code
966 that G++ generates for the following C++ input:
980 This example does not show how to throw or catch an exception from
981 assembly code. That is a much more complex operation and should
982 always be done in a high-level language, such as C++, that directly
985 The code generated by one particular version of G++ when compiling the
992 @ Function supports interworking.
993 @ args = 0, pretend = 0, frame = 8
994 @ frame_needed = 1, uses_anonymous_args = 0
1016 Of course, the sequence of instructions varies based on the options
1017 you pass to GCC and on the version of GCC in use. The exact
1018 instructions are not important since we are focusing on the pseudo ops
1019 that are used to generate unwind information.
1021 An important assumption made by the unwinder is that the stack frame
1022 does not change during the body of the function. In particular, since
1023 we assume that the assembly code does not itself throw an exception,
1024 the only point where an exception can be thrown is from a call, such
1025 as the @code{bl} instruction above. At each call site, the same saved
1026 registers (including @code{lr}, which indicates the return address)
1027 must be located in the same locations relative to the frame pointer.
1029 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1030 op appears immediately before the first instruction of the function
1031 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1032 op appears immediately after the last instruction of the function.
1033 These pseudo ops specify the range of the function.
1035 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1036 @code{.pad}) matters; their exact locations are irrelevant. In the
1037 example above, the compiler emits the pseudo ops with particular
1038 instructions. That makes it easier to understand the code, but it is
1039 not required for correctness. It would work just as well to emit all
1040 of the pseudo ops other than @code{.fnend} in the same order, but
1041 immediately after @code{.fnstart}.
1043 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1044 indicates registers that have been saved to the stack so that they can
1045 be restored before the function returns. The argument to the
1046 @code{.save} pseudo op is a list of registers to save. If a register
1047 is ``callee-saved'' (as specified by the ABI) and is modified by the
1048 function you are writing, then your code must save the value before it
1049 is modified and restore the original value before the function
1050 returns. If an exception is thrown, the run-time library restores the
1051 values of these registers from their locations on the stack before
1052 returning control to the exception handler. (Of course, if an
1053 exception is not thrown, the function that contains the @code{.save}
1054 pseudo op restores these registers in the function epilogue, as is
1055 done with the @code{ldmfd} instruction above.)
1057 You do not have to save callee-saved registers at the very beginning
1058 of the function and you do not need to use the @code{.save} pseudo op
1059 immediately following the point at which the registers are saved.
1060 However, if you modify a callee-saved register, you must save it on
1061 the stack before modifying it and before calling any functions which
1062 might throw an exception. And, you must use the @code{.save} pseudo
1063 op to indicate that you have done so.
1065 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1066 modification of the stack pointer that does not save any registers.
1067 The argument is the number of bytes (in decimal) that are subtracted
1068 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1069 subtracting from the stack pointer increases the size of the stack.)
1071 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1072 indicates the register that contains the frame pointer. The first
1073 argument is the register that is set, which is typically @code{fp}.
1074 The second argument indicates the register from which the frame
1075 pointer takes its value. The third argument, if present, is the value
1076 (in decimal) added to the register specified by the second argument to
1077 compute the value of the frame pointer. You should not modify the
1078 frame pointer in the body of the function.
1080 If you do not use a frame pointer, then you should not use the
1081 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1082 should avoid modifying the stack pointer outside of the function
1083 prologue. Otherwise, the run-time library will be unable to find
1084 saved registers when it is unwinding the stack.
1086 The pseudo ops described above are sufficient for writing assembly
1087 code that calls functions which may throw exceptions. If you need to
1088 know more about the object-file format used to represent unwind
1089 information, you may consult the @cite{Exception Handling ABI for the
1090 ARM Architecture} available from @uref{http://infocenter.arm.com}.