1 @c Copyright (C) 1996-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
146 @code{cortex-m0plus},
149 @code{marvell-whitney},
153 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
154 @code{i80200} (Intel XScale processor)
155 @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
158 The special name @code{all} may be used to allow the
159 assembler to accept instructions valid for any ARM processor.
161 In addition to the basic instruction set, the assembler can be told to
162 accept various extension mnemonics that extend the processor using the
163 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
164 is equivalent to specifying @code{-mcpu=ep9312}.
166 Multiple extensions may be specified, separated by a @code{+}. The
167 extensions should be specified in ascending alphabetical order.
169 Some extensions may be restricted to particular architectures; this is
170 documented in the list of extensions below.
172 Extension mnemonics may also be removed from those the assembler accepts.
173 This is done be prepending @code{no} to the option that adds the extension.
174 Extensions that are removed should be listed after all extensions which have
175 been added, again in ascending alphabetical order. For example,
176 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
179 The following extensions are currently supported:
181 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
182 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
183 @code{fp} (Floating Point Extensions for v8-A architecture),
184 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
185 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
186 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
191 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
193 @code{os} (Operating System for v6M architecture),
194 @code{predres} (Execution and Data Prediction Restriction Instruction for
195 v8-A architectures, added by default from v8.5-A),
196 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
197 default from v8.5-A),
198 @code{sec} (Security Extensions for v6K and v7-A architectures),
199 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
200 @code{virt} (Virtualization Extensions for v7-A architecture, implies
202 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
203 @code{ras} (Reliability, Availability and Serviceability extensions
204 for v8-A architecture),
205 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
210 @cindex @code{-march=} command-line option, ARM
211 @item -march=@var{architecture}[+@var{extension}@dots{}]
212 This option specifies the target architecture. The assembler will issue
213 an error message if an attempt is made to assemble an instruction which
214 will not execute on the target architecture. The following architecture
215 names are recognized:
253 @code{armv8.1-m.main},
258 If both @code{-mcpu} and
259 @code{-march} are specified, the assembler will use
260 the setting for @code{-mcpu}.
262 The architecture option can be extended with a set extension options. These
263 extensions are context sensitive, i.e. the same extension may mean different
264 things when used with different architectures. When used together with a
265 @code{-mfpu} option, the union of both feature enablement is taken.
266 See their availability and meaning below:
268 For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
270 @code{+fp}: Enables VFPv2 instructions.
271 @code{+nofp}: Disables all FPU instrunctions.
275 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
276 @code{+nofp}: Disables all FPU instructions.
280 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
281 @code{+vfpv3-d16}: Alias for @code{+fp}.
282 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
283 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
284 conversion instructions and 16 double-word registers.
285 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
286 instructions and 32 double-word registers.
287 @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
288 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
289 @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
291 @code{+neon}: Alias for @code{+simd}.
292 @code{+neon-vfpv3}: Alias for @code{+simd}.
293 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
294 NEONv1 instructions with 32 double-word registers.
295 @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
296 double-word registers.
297 @code{+mp}: Enables Multiprocessing Extensions.
298 @code{+sec}: Enables Security Extensions.
299 @code{+nofp}: Disables all FPU and NEON instructions.
300 @code{+nosimd}: Disables all NEON instructions.
304 @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
305 @code{+vfpv4-d16}: Alias for @code{+fp}.
306 @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
307 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
308 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
309 conversion instructions and 16 double-word registers.
310 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
311 instructions and 32 double-word registers.
312 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
313 @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
314 double-word registers.
315 @code{+neon-vfpv4}: Alias for @code{+simd}.
316 @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
318 @code{+neon-vfpv3}: Alias for @code{+neon}.
319 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
320 NEONv1 instructions with 32 double-word registers.
321 double-word registers.
322 @code{+nofp}: Disables all FPU and NEON instructions.
323 @code{+nosimd}: Disables all NEON instructions.
327 @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
328 double-word registers.
329 @code{+vfpv3xd}: Alias for @code{+fp.sp}.
330 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
331 @code{+vfpv3-d16}: Alias for @code{+fp}.
332 @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
333 floating-point conversion instructions with 16 double-word registers.
334 @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
335 conversion instructions with 16 double-word registers.
336 @code{+idiv}: Enables integer division instructions in ARM mode.
337 @code{+nofp}: Disables all FPU instructions.
341 @code{+fp}: Enables single-precision only VFPv4 instructions with 16
342 double-word registers.
343 @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
344 @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
345 double-word registers.
346 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
347 @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
348 @code{+nofp}: Disables all FPU instructions.
350 For @code{armv8-m.main}:
352 @code{+dsp}: Enables DSP Extension.
353 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
354 double-word registers.
355 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
356 @code{+nofp}: Disables all FPU instructions.
357 @code{+nodsp}: Disables DSP Extension.
359 For @code{armv8.1-m.main}:
361 @code{+dsp}: Enables DSP Extension.
362 @code{+fp}: Enables single and half precision scalar Floating Point Extensions
363 for Armv8.1-M Mainline with 16 double-word registers.
364 @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
365 Armv8.1-M Mainline, implies @code{+fp}.
366 @code{+mve}: Enables integer only M-profile Vector Extension for
367 Armv8.1-M Mainline, implies @code{+dsp}.
368 @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
369 Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
370 @code{+nofp}: Disables all FPU instructions.
371 @code{+nodsp}: Disables DSP Extension.
372 @code{+nomve}: Disables all M-profile Vector Extensions.
376 @code{+crc}: Enables CRC32 Extension.
377 @code{+simd}: Enables VFP and NEON for Armv8-A.
378 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
380 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
381 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
383 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
384 @code{+nocrypto}: Disables Cryptography Extensions.
386 For @code{armv8.1-a}:
388 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
389 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
391 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
392 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
394 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
395 @code{+nocrypto}: Disables Cryptography Extensions.
397 For @code{armv8.2-a} and @code{armv8.3-a}:
399 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
400 @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
401 @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
402 for Armv8.2-A, implies @code{+fp16}.
403 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
405 @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
407 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
408 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
410 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
411 @code{+nocrypto}: Disables Cryptography Extensions.
413 For @code{armv8.4-a}:
415 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
417 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
418 Variant Extensions for Armv8.2-A, implies @code{+simd}.
419 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
421 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
422 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
424 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
425 @code{+nocryptp}: Disables Cryptography Extensions.
427 For @code{armv8.5-a}:
429 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
431 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
432 Variant Extensions for Armv8.2-A, implies @code{+simd}.
433 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
435 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
436 @code{+nocryptp}: Disables Cryptography Extensions.
439 @cindex @code{-mfpu=} command-line option, ARM
440 @item -mfpu=@var{floating-point-format}
442 This option specifies the floating point format to assemble for. The
443 assembler will issue an error message if an attempt is made to assemble
444 an instruction which will not execute on the target floating point unit.
445 The following format options are recognized:
465 @code{vfpv3-d16-fp16},
482 @code{neon-fp-armv8},
483 @code{crypto-neon-fp-armv8},
484 @code{neon-fp-armv8.1}
486 @code{crypto-neon-fp-armv8.1}.
488 In addition to determining which instructions are assembled, this option
489 also affects the way in which the @code{.double} assembler directive behaves
490 when assembling little-endian code.
492 The default is dependent on the processor selected. For Architecture 5 or
493 later, the default is to assemble for VFP instructions; for earlier
494 architectures the default is to assemble for FPA instructions.
496 @cindex @code{-mfp16-format=} command-line option
497 @item -mfp16-format=@var{format}
498 This option specifies the half-precision floating point format to use
499 when assembling floating point numbers emitted by the @code{.float16}
501 The following format options are recognized:
504 If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
505 point format is used, if @code{alternative} is specified then the Arm
506 alternative half-precision format is used. If this option is set on the
507 command line then the format is fixed and cannot be changed with
508 the @code{float16_format} directive. If this value is not set then
509 the IEEE 754-2008 format is used until the format is explicitly set with
510 the @code{float16_format} directive.
512 @cindex @code{-mthumb} command-line option, ARM
514 This option specifies that the assembler should start assembling Thumb
515 instructions; that is, it should behave as though the file starts with a
516 @code{.code 16} directive.
518 @cindex @code{-mthumb-interwork} command-line option, ARM
519 @item -mthumb-interwork
520 This option specifies that the output generated by the assembler should
521 be marked as supporting interworking. It also affects the behaviour
522 of the @code{ADR} and @code{ADRL} pseudo opcodes.
524 @cindex @code{-mimplicit-it} command-line option, ARM
525 @item -mimplicit-it=never
526 @itemx -mimplicit-it=always
527 @itemx -mimplicit-it=arm
528 @itemx -mimplicit-it=thumb
529 The @code{-mimplicit-it} option controls the behavior of the assembler when
530 conditional instructions are not enclosed in IT blocks.
531 There are four possible behaviors.
532 If @code{never} is specified, such constructs cause a warning in ARM
533 code and an error in Thumb-2 code.
534 If @code{always} is specified, such constructs are accepted in both
535 ARM and Thumb-2 code, where the IT instruction is added implicitly.
536 If @code{arm} is specified, such constructs are accepted in ARM code
537 and cause an error in Thumb-2 code.
538 If @code{thumb} is specified, such constructs cause a warning in ARM
539 code and are accepted in Thumb-2 code. If you omit this option, the
540 behavior is equivalent to @code{-mimplicit-it=arm}.
542 @cindex @code{-mapcs-26} command-line option, ARM
543 @cindex @code{-mapcs-32} command-line option, ARM
546 These options specify that the output generated by the assembler should
547 be marked as supporting the indicated version of the Arm Procedure.
550 @cindex @code{-matpcs} command-line option, ARM
552 This option specifies that the output generated by the assembler should
553 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
554 enabled this option will cause the assembler to create an empty
555 debugging section in the object file called .arm.atpcs. Debuggers can
556 use this to determine the ABI being used by.
558 @cindex @code{-mapcs-float} command-line option, ARM
560 This indicates the floating point variant of the APCS should be
561 used. In this variant floating point arguments are passed in FP
562 registers rather than integer registers.
564 @cindex @code{-mapcs-reentrant} command-line option, ARM
565 @item -mapcs-reentrant
566 This indicates that the reentrant variant of the APCS should be used.
567 This variant supports position independent code.
569 @cindex @code{-mfloat-abi=} command-line option, ARM
570 @item -mfloat-abi=@var{abi}
571 This option specifies that the output generated by the assembler should be
572 marked as using specified floating point ABI.
573 The following values are recognized:
579 @cindex @code{-eabi=} command-line option, ARM
580 @item -meabi=@var{ver}
581 This option specifies which EABI version the produced object files should
583 The following values are recognized:
589 @cindex @code{-EB} command-line option, ARM
591 This option specifies that the output generated by the assembler should
592 be marked as being encoded for a big-endian processor.
594 Note: If a program is being built for a system with big-endian data
595 and little-endian instructions then it should be assembled with the
596 @option{-EB} option, (all of it, code and data) and then linked with
597 the @option{--be8} option. This will reverse the endianness of the
598 instructions back to little-endian, but leave the data as big-endian.
600 @cindex @code{-EL} command-line option, ARM
602 This option specifies that the output generated by the assembler should
603 be marked as being encoded for a little-endian processor.
605 @cindex @code{-k} command-line option, ARM
606 @cindex PIC code generation for ARM
608 This option specifies that the output of the assembler should be marked
609 as position-independent code (PIC).
611 @cindex @code{--fix-v4bx} command-line option, ARM
613 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
614 the linker option of the same name.
616 @cindex @code{-mwarn-deprecated} command-line option, ARM
617 @item -mwarn-deprecated
618 @itemx -mno-warn-deprecated
619 Enable or disable warnings about using deprecated options or
620 features. The default is to warn.
622 @cindex @code{-mccs} command-line option, ARM
624 Turns on CodeComposer Studio assembly syntax compatibility mode.
626 @cindex @code{-mwarn-syms} command-line option, ARM
628 @itemx -mno-warn-syms
629 Enable or disable warnings about symbols that match the names of ARM
630 instructions. The default is to warn.
638 * ARM-Instruction-Set:: Instruction Set
639 * ARM-Chars:: Special Characters
640 * ARM-Regs:: Register Names
641 * ARM-Relocations:: Relocations
642 * ARM-Neon-Alignment:: NEON Alignment Specifiers
645 @node ARM-Instruction-Set
646 @subsection Instruction Set Syntax
647 Two slightly different syntaxes are support for ARM and THUMB
648 instructions. The default, @code{divided}, uses the old style where
649 ARM and THUMB instructions had their own, separate syntaxes. The new,
650 @code{unified} syntax, which can be selected via the @code{.syntax}
651 directive, and has the following main features:
655 Immediate operands do not require a @code{#} prefix.
658 The @code{IT} instruction may appear, and if it does it is validated
659 against subsequent conditional affixes. In ARM mode it does not
660 generate machine code, in THUMB mode it does.
663 For ARM instructions the conditional affixes always appear at the end
664 of the instruction. For THUMB instructions conditional affixes can be
665 used, but only inside the scope of an @code{IT} instruction.
668 All of the instructions new to the V6T2 architecture (and later) are
669 available. (Only a few such instructions can be written in the
670 @code{divided} syntax).
673 The @code{.N} and @code{.W} suffixes are recognized and honored.
676 All instructions set the flags if and only if they have an @code{s}
681 @subsection Special Characters
683 @cindex line comment character, ARM
684 @cindex ARM line comment character
685 The presence of a @samp{@@} anywhere on a line indicates the start of
686 a comment that extends to the end of that line.
688 If a @samp{#} appears as the first character of a line then the whole
689 line is treated as a comment, but in this case the line could also be
690 a logical line number directive (@pxref{Comments}) or a preprocessor
691 control command (@pxref{Preprocessing}).
693 @cindex line separator, ARM
694 @cindex statement separator, ARM
695 @cindex ARM line separator
696 The @samp{;} character can be used instead of a newline to separate
699 @cindex immediate character, ARM
700 @cindex ARM immediate character
701 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
703 @cindex identifiers, ARM
704 @cindex ARM identifiers
705 *TODO* Explain about /data modifier on symbols.
708 @subsection Register Names
710 @cindex ARM register names
711 @cindex register names, ARM
712 *TODO* Explain about ARM register naming, and the predefined names.
714 @node ARM-Relocations
715 @subsection ARM relocation generation
717 @cindex data relocations, ARM
718 @cindex ARM data relocations
719 Specific data relocations can be generated by putting the relocation name
720 in parentheses after the symbol name. For example:
726 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
728 The following relocations are supported:
744 For compatibility with older toolchains the assembler also accepts
745 @code{(PLT)} after branch targets. On legacy targets this will
746 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
747 targets it will encode either the @samp{R_ARM_CALL} or
748 @samp{R_ARM_JUMP24} relocation, as appropriate.
750 @cindex MOVW and MOVT relocations, ARM
751 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
752 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
753 respectively. For example to load the 32-bit address of foo into r0:
756 MOVW r0, #:lower16:foo
757 MOVT r0, #:upper16:foo
760 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
761 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
762 generated by prefixing the value with @samp{#:lower0_7:#},
763 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
764 respectively. For example to load the 32-bit address of foo into r0:
767 MOVS r0, #:upper8_15:#foo
769 ADDS r0, #:upper0_7:#foo
771 ADDS r0, #:lower8_15:#foo
773 ADDS r0, #:lower0_7:#foo
776 @node ARM-Neon-Alignment
777 @subsection NEON Alignment Specifiers
779 @cindex alignment for NEON instructions
780 Some NEON load/store instructions allow an optional address
782 The ARM documentation specifies that this is indicated by
783 @samp{@@ @var{align}}. However GAS already interprets
784 the @samp{@@} character as a "line comment" start,
785 so @samp{: @var{align}} is used instead. For example:
788 vld1.8 @{q0@}, [r0, :128]
791 @node ARM Floating Point
792 @section Floating Point
794 @cindex floating point, ARM (@sc{ieee})
795 @cindex ARM floating point (@sc{ieee})
796 The ARM family uses @sc{ieee} floating-point numbers.
799 @section ARM Machine Directives
801 @cindex machine directives, ARM
802 @cindex ARM machine directives
805 @c AAAAAAAAAAAAAAAAAAAAAAAAA
808 @cindex @code{.2byte} directive, ARM
809 @cindex @code{.4byte} directive, ARM
810 @cindex @code{.8byte} directive, ARM
811 @item .2byte @var{expression} [, @var{expression}]*
812 @itemx .4byte @var{expression} [, @var{expression}]*
813 @itemx .8byte @var{expression} [, @var{expression}]*
814 These directives write 2, 4 or 8 byte values to the output section.
817 @cindex @code{.align} directive, ARM
818 @item .align @var{expression} [, @var{expression}]
819 This is the generic @var{.align} directive. For the ARM however if the
820 first argument is zero (ie no alignment is needed) the assembler will
821 behave as if the argument had been 2 (ie pad to the next four byte
822 boundary). This is for compatibility with ARM's own assembler.
824 @cindex @code{.arch} directive, ARM
825 @item .arch @var{name}
826 Select the target architecture. Valid values for @var{name} are the same as
827 for the @option{-march} command-line option without the instruction set
830 Specifying @code{.arch} clears any previously selected architecture
833 @cindex @code{.arch_extension} directive, ARM
834 @item .arch_extension @var{name}
835 Add or remove an architecture extension to the target architecture. Valid
836 values for @var{name} are the same as those accepted as architectural
837 extensions by the @option{-mcpu} and @option{-march} command-line options.
839 @code{.arch_extension} may be used multiple times to add or remove extensions
840 incrementally to the architecture being compiled for.
842 @cindex @code{.arm} directive, ARM
844 This performs the same action as @var{.code 32}.
846 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
848 @cindex @code{.bss} directive, ARM
850 This directive switches to the @code{.bss} section.
852 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
854 @cindex @code{.cantunwind} directive, ARM
856 Prevents unwinding through the current function. No personality routine
857 or exception table data is required or permitted.
859 @cindex @code{.code} directive, ARM
860 @item .code @code{[16|32]}
861 This directive selects the instruction set being generated. The value 16
862 selects Thumb, with the value 32 selecting ARM.
864 @cindex @code{.cpu} directive, ARM
865 @item .cpu @var{name}
866 Select the target processor. Valid values for @var{name} are the same as
867 for the @option{-mcpu} command-line option without the instruction set
870 Specifying @code{.cpu} clears any previously selected architecture
873 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
875 @cindex @code{.dn} and @code{.qn} directives, ARM
876 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
877 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
879 The @code{dn} and @code{qn} directives are used to create typed
880 and/or indexed register aliases for use in Advanced SIMD Extension
881 (Neon) instructions. The former should be used to create aliases
882 of double-precision registers, and the latter to create aliases of
883 quad-precision registers.
885 If these directives are used to create typed aliases, those aliases can
886 be used in Neon instructions instead of writing types after the mnemonic
887 or after each operand. For example:
896 This is equivalent to writing the following:
902 Aliases created using @code{dn} or @code{qn} can be destroyed using
905 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
907 @cindex @code{.eabi_attribute} directive, ARM
908 @item .eabi_attribute @var{tag}, @var{value}
909 Set the EABI object attribute @var{tag} to @var{value}.
911 The @var{tag} is either an attribute number, or one of the following:
912 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
913 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
914 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
915 @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
916 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
917 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
918 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
919 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
920 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
921 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
922 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
923 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
924 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
925 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
926 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
927 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
928 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
929 @code{Tag_conformance}, @code{Tag_T2EE_use},
930 @code{Tag_Virtualization_use}
932 The @var{value} is either a @code{number}, @code{"string"}, or
933 @code{number, "string"} depending on the tag.
935 Note - the following legacy values are also accepted by @var{tag}:
936 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
937 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
939 @cindex @code{.even} directive, ARM
941 This directive aligns to an even-numbered address.
943 @cindex @code{.extend} directive, ARM
944 @cindex @code{.ldouble} directive, ARM
945 @item .extend @var{expression} [, @var{expression}]*
946 @itemx .ldouble @var{expression} [, @var{expression}]*
947 These directives write 12byte long double floating-point values to the
948 output section. These are not compatible with current ARM processors
951 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
953 @cindex @code{.float16} directive, ARM
954 @item .float16 @var{value [,...,value_n]}
955 Place the half precision floating point representation of one or more
956 floating-point values into the current section. The exact format of the
957 encoding is specified by @code{.float16_format}. If the format has not
958 been explicitly set yet (either via the @code{.float16_format} directive or
959 the command line option) then the IEEE 754-2008 format is used.
961 @cindex @code{.float16_format} directive, ARM
962 @item .float16_format @var{format}
963 Set the format to use when encoding float16 values emitted by
964 the @code{.float16} directive.
965 Once the format has been set it cannot be changed.
966 @code{format} should be one of the following: @code{ieee} (encode in
967 the IEEE 754-2008 half precision format) or @code{alternative} (encode in
968 the Arm alternative half precision format).
971 @cindex @code{.fnend} directive, ARM
973 Marks the end of a function with an unwind table entry. The unwind index
974 table entry is created when this directive is processed.
976 If no personality routine has been specified then standard personality
977 routine 0 or 1 will be used, depending on the number of unwind opcodes
981 @cindex @code{.fnstart} directive, ARM
983 Marks the start of a function with an unwind table entry.
985 @cindex @code{.force_thumb} directive, ARM
987 This directive forces the selection of Thumb instructions, even if the
988 target processor does not support those instructions
990 @cindex @code{.fpu} directive, ARM
991 @item .fpu @var{name}
992 Select the floating-point unit to assemble for. Valid values for @var{name}
993 are the same as for the @option{-mfpu} command-line option.
995 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
996 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
998 @cindex @code{.handlerdata} directive, ARM
1000 Marks the end of the current function, and the start of the exception table
1001 entry for that function. Anything between this directive and the
1002 @code{.fnend} directive will be added to the exception table entry.
1004 Must be preceded by a @code{.personality} or @code{.personalityindex}
1007 @c IIIIIIIIIIIIIIIIIIIIIIIIII
1009 @cindex @code{.inst} directive, ARM
1010 @item .inst @var{opcode} [ , @dots{} ]
1011 @itemx .inst.n @var{opcode} [ , @dots{} ]
1012 @itemx .inst.w @var{opcode} [ , @dots{} ]
1013 Generates the instruction corresponding to the numerical value @var{opcode}.
1014 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
1015 specified explicitly, overriding the normal encoding rules.
1017 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
1018 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
1019 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
1021 @item .ldouble @var{expression} [, @var{expression}]*
1024 @cindex @code{.ltorg} directive, ARM
1026 This directive causes the current contents of the literal pool to be
1027 dumped into the current section (which is assumed to be the .text
1028 section) at the current location (aligned to a word boundary).
1029 @code{GAS} maintains a separate literal pool for each section and each
1030 sub-section. The @code{.ltorg} directive will only affect the literal
1031 pool of the current section and sub-section. At the end of assembly
1032 all remaining, un-empty literal pools will automatically be dumped.
1034 Note - older versions of @code{GAS} would dump the current literal
1035 pool any time a section change occurred. This is no longer done, since
1036 it prevents accurate control of the placement of literal pools.
1038 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
1040 @cindex @code{.movsp} directive, ARM
1041 @item .movsp @var{reg} [, #@var{offset}]
1042 Tell the unwinder that @var{reg} contains an offset from the current
1043 stack pointer. If @var{offset} is not specified then it is assumed to be
1046 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
1047 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
1049 @cindex @code{.object_arch} directive, ARM
1050 @item .object_arch @var{name}
1051 Override the architecture recorded in the EABI object attribute section.
1052 Valid values for @var{name} are the same as for the @code{.arch} directive.
1053 Typically this is useful when code uses runtime detection of CPU features.
1055 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
1057 @cindex @code{.packed} directive, ARM
1058 @item .packed @var{expression} [, @var{expression}]*
1059 This directive writes 12-byte packed floating-point values to the
1060 output section. These are not compatible with current ARM processors
1064 @cindex @code{.pad} directive, ARM
1065 @item .pad #@var{count}
1066 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
1067 A positive value indicates the function prologue allocated stack space by
1068 decrementing the stack pointer.
1070 @cindex @code{.personality} directive, ARM
1071 @item .personality @var{name}
1072 Sets the personality routine for the current function to @var{name}.
1074 @cindex @code{.personalityindex} directive, ARM
1075 @item .personalityindex @var{index}
1076 Sets the personality routine for the current function to the EABI standard
1077 routine number @var{index}
1079 @cindex @code{.pool} directive, ARM
1081 This is a synonym for .ltorg.
1083 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
1084 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
1086 @cindex @code{.req} directive, ARM
1087 @item @var{name} .req @var{register name}
1088 This creates an alias for @var{register name} called @var{name}. For
1095 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
1098 @cindex @code{.save} directive, ARM
1099 @item .save @var{reglist}
1100 Generate unwinder annotations to restore the registers in @var{reglist}.
1101 The format of @var{reglist} is the same as the corresponding store-multiple
1105 @exdent @emph{core registers}
1106 .save @{r4, r5, r6, lr@}
1107 stmfd sp!, @{r4, r5, r6, lr@}
1108 @exdent @emph{FPA registers}
1111 @exdent @emph{VFP registers}
1112 .save @{d8, d9, d10@}
1113 fstmdx sp!, @{d8, d9, d10@}
1114 @exdent @emph{iWMMXt registers}
1115 .save @{wr10, wr11@}
1116 wstrd wr11, [sp, #-8]!
1117 wstrd wr10, [sp, #-8]!
1120 wstrd wr11, [sp, #-8]!
1122 wstrd wr10, [sp, #-8]!
1126 @cindex @code{.setfp} directive, ARM
1127 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
1128 Make all unwinder annotations relative to a frame pointer. Without this
1129 the unwinder will use offsets from the stack pointer.
1131 The syntax of this directive is the same as the @code{add} or @code{mov}
1132 instruction used to set the frame pointer. @var{spreg} must be either
1133 @code{sp} or mentioned in a previous @code{.movsp} directive.
1143 @cindex @code{.secrel32} directive, ARM
1144 @item .secrel32 @var{expression} [, @var{expression}]*
1145 This directive emits relocations that evaluate to the section-relative
1146 offset of each expression's symbol. This directive is only supported
1149 @cindex @code{.syntax} directive, ARM
1150 @item .syntax [@code{unified} | @code{divided}]
1151 This directive sets the Instruction Set Syntax as described in the
1152 @ref{ARM-Instruction-Set} section.
1154 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
1156 @cindex @code{.thumb} directive, ARM
1158 This performs the same action as @var{.code 16}.
1160 @cindex @code{.thumb_func} directive, ARM
1162 This directive specifies that the following symbol is the name of a
1163 Thumb encoded function. This information is necessary in order to allow
1164 the assembler and linker to generate correct code for interworking
1165 between Arm and Thumb instructions and should be used even if
1166 interworking is not going to be performed. The presence of this
1167 directive also implies @code{.thumb}
1169 This directive is not necessary when generating EABI objects. On these
1170 targets the encoding is implicit when generating Thumb code.
1172 @cindex @code{.thumb_set} directive, ARM
1174 This performs the equivalent of a @code{.set} directive in that it
1175 creates a symbol which is an alias for another symbol (possibly not yet
1176 defined). This directive also has the added property in that it marks
1177 the aliased symbol as being a thumb function entry point, in the same
1178 way that the @code{.thumb_func} directive does.
1180 @cindex @code{.tlsdescseq} directive, ARM
1181 @item .tlsdescseq @var{tls-variable}
1182 This directive is used to annotate parts of an inlined TLS descriptor
1183 trampoline. Normally the trampoline is provided by the linker, and
1184 this directive is not needed.
1186 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
1188 @cindex @code{.unreq} directive, ARM
1189 @item .unreq @var{alias-name}
1190 This undefines a register alias which was previously defined using the
1191 @code{req}, @code{dn} or @code{qn} directives. For example:
1198 An error occurs if the name is undefined. Note - this pseudo op can
1199 be used to delete builtin in register name aliases (eg 'r0'). This
1200 should only be done if it is really necessary.
1202 @cindex @code{.unwind_raw} directive, ARM
1203 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
1204 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
1205 the stack pointer by @var{offset} bytes.
1207 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1210 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1212 @cindex @code{.vsave} directive, ARM
1213 @item .vsave @var{vfp-reglist}
1214 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1215 using FLDMD. Also works for VFPv3 registers
1216 that are to be restored using VLDM.
1217 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1221 @exdent @emph{VFP registers}
1222 .vsave @{d8, d9, d10@}
1223 fstmdd sp!, @{d8, d9, d10@}
1224 @exdent @emph{VFPv3 registers}
1225 .vsave @{d15, d16, d17@}
1226 vstm sp!, @{d15, d16, d17@}
1229 Since FLDMX and FSTMX are now deprecated, this directive should be
1230 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1232 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1233 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1234 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1235 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1243 @cindex opcodes for ARM
1244 @code{@value{AS}} implements all the standard ARM opcodes. It also
1245 implements several pseudo opcodes, including several synthetic load
1250 @cindex @code{NOP} pseudo op, ARM
1256 This pseudo op will always evaluate to a legal ARM instruction that does
1257 nothing. Currently it will evaluate to MOV r0, r0.
1259 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1262 ldr <register> , = <expression>
1265 If expression evaluates to a numeric constant then a MOV or MVN
1266 instruction will be used in place of the LDR instruction, if the
1267 constant can be generated by either of these instructions. Otherwise
1268 the constant will be placed into the nearest literal pool (if it not
1269 already there) and a PC relative LDR instruction will be generated.
1271 @cindex @code{ADR reg,<label>} pseudo op, ARM
1274 adr <register> <label>
1277 This instruction will load the address of @var{label} into the indicated
1278 register. The instruction will evaluate to a PC relative ADD or SUB
1279 instruction depending upon where the label is located. If the label is
1280 out of range, or if it is not defined in the same file (and section) as
1281 the ADR instruction, then an error will be generated. This instruction
1282 will not make use of the literal pool.
1284 If @var{label} is a thumb function symbol, and thumb interworking has
1285 been enabled via the @option{-mthumb-interwork} option then the bottom
1286 bit of the value stored into @var{register} will be set. This allows
1287 the following sequence to work as expected:
1290 adr r0, thumb_function
1294 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1297 adrl <register> <label>
1300 This instruction will load the address of @var{label} into the indicated
1301 register. The instruction will evaluate to one or two PC relative ADD
1302 or SUB instructions depending upon where the label is located. If a
1303 second instruction is not needed a NOP instruction will be generated in
1304 its place, so that this instruction is always 8 bytes long.
1306 If the label is out of range, or if it is not defined in the same file
1307 (and section) as the ADRL instruction, then an error will be generated.
1308 This instruction will not make use of the literal pool.
1310 If @var{label} is a thumb function symbol, and thumb interworking has
1311 been enabled via the @option{-mthumb-interwork} option then the bottom
1312 bit of the value stored into @var{register} will be set.
1316 For information on the ARM or Thumb instruction sets, see @cite{ARM
1317 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1320 @node ARM Mapping Symbols
1321 @section Mapping Symbols
1323 The ARM ELF specification requires that special symbols be inserted
1324 into object files to mark certain features:
1330 At the start of a region of code containing ARM instructions.
1334 At the start of a region of code containing THUMB instructions.
1338 At the start of a region of data.
1342 The assembler will automatically insert these symbols for you - there
1343 is no need to code them yourself. Support for tagging symbols ($b,
1344 $f, $p and $m) which is also mentioned in the current ARM ELF
1345 specification is not implemented. This is because they have been
1346 dropped from the new EABI and so tools cannot rely upon their
1349 @node ARM Unwinding Tutorial
1352 The ABI for the ARM Architecture specifies a standard format for
1353 exception unwind information. This information is used when an
1354 exception is thrown to determine where control should be transferred.
1355 In particular, the unwind information is used to determine which
1356 function called the function that threw the exception, and which
1357 function called that one, and so forth. This information is also used
1358 to restore the values of callee-saved registers in the function
1359 catching the exception.
1361 If you are writing functions in assembly code, and those functions
1362 call other functions that throw exceptions, you must use assembly
1363 pseudo ops to ensure that appropriate exception unwind information is
1364 generated. Otherwise, if one of the functions called by your assembly
1365 code throws an exception, the run-time library will be unable to
1366 unwind the stack through your assembly code and your program will not
1369 To illustrate the use of these pseudo ops, we will examine the code
1370 that G++ generates for the following C++ input:
1373 void callee (int *);
1384 This example does not show how to throw or catch an exception from
1385 assembly code. That is a much more complex operation and should
1386 always be done in a high-level language, such as C++, that directly
1387 supports exceptions.
1389 The code generated by one particular version of G++ when compiling the
1396 @ Function supports interworking.
1397 @ args = 0, pretend = 0, frame = 8
1398 @ frame_needed = 1, uses_anonymous_args = 0
1420 Of course, the sequence of instructions varies based on the options
1421 you pass to GCC and on the version of GCC in use. The exact
1422 instructions are not important since we are focusing on the pseudo ops
1423 that are used to generate unwind information.
1425 An important assumption made by the unwinder is that the stack frame
1426 does not change during the body of the function. In particular, since
1427 we assume that the assembly code does not itself throw an exception,
1428 the only point where an exception can be thrown is from a call, such
1429 as the @code{bl} instruction above. At each call site, the same saved
1430 registers (including @code{lr}, which indicates the return address)
1431 must be located in the same locations relative to the frame pointer.
1433 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1434 op appears immediately before the first instruction of the function
1435 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1436 op appears immediately after the last instruction of the function.
1437 These pseudo ops specify the range of the function.
1439 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1440 @code{.pad}) matters; their exact locations are irrelevant. In the
1441 example above, the compiler emits the pseudo ops with particular
1442 instructions. That makes it easier to understand the code, but it is
1443 not required for correctness. It would work just as well to emit all
1444 of the pseudo ops other than @code{.fnend} in the same order, but
1445 immediately after @code{.fnstart}.
1447 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1448 indicates registers that have been saved to the stack so that they can
1449 be restored before the function returns. The argument to the
1450 @code{.save} pseudo op is a list of registers to save. If a register
1451 is ``callee-saved'' (as specified by the ABI) and is modified by the
1452 function you are writing, then your code must save the value before it
1453 is modified and restore the original value before the function
1454 returns. If an exception is thrown, the run-time library restores the
1455 values of these registers from their locations on the stack before
1456 returning control to the exception handler. (Of course, if an
1457 exception is not thrown, the function that contains the @code{.save}
1458 pseudo op restores these registers in the function epilogue, as is
1459 done with the @code{ldmfd} instruction above.)
1461 You do not have to save callee-saved registers at the very beginning
1462 of the function and you do not need to use the @code{.save} pseudo op
1463 immediately following the point at which the registers are saved.
1464 However, if you modify a callee-saved register, you must save it on
1465 the stack before modifying it and before calling any functions which
1466 might throw an exception. And, you must use the @code{.save} pseudo
1467 op to indicate that you have done so.
1469 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1470 modification of the stack pointer that does not save any registers.
1471 The argument is the number of bytes (in decimal) that are subtracted
1472 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1473 subtracting from the stack pointer increases the size of the stack.)
1475 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1476 indicates the register that contains the frame pointer. The first
1477 argument is the register that is set, which is typically @code{fp}.
1478 The second argument indicates the register from which the frame
1479 pointer takes its value. The third argument, if present, is the value
1480 (in decimal) added to the register specified by the second argument to
1481 compute the value of the frame pointer. You should not modify the
1482 frame pointer in the body of the function.
1484 If you do not use a frame pointer, then you should not use the
1485 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1486 should avoid modifying the stack pointer outside of the function
1487 prologue. Otherwise, the run-time library will be unable to find
1488 saved registers when it is unwinding the stack.
1490 The pseudo ops described above are sufficient for writing assembly
1491 code that calls functions which may throw exceptions. If you need to
1492 know more about the object-file format used to represent unwind
1493 information, you may consult the @cite{Exception Handling ABI for the
1494 ARM Architecture} available from @uref{http://infocenter.arm.com}.