1 @c Copyright (C) 1996-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
146 @code{cortex-m0plus},
149 @code{marvell-whitney},
153 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
154 @code{i80200} (Intel XScale processor)
155 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
158 The special name @code{all} may be used to allow the
159 assembler to accept instructions valid for any ARM processor.
161 In addition to the basic instruction set, the assembler can be told to
162 accept various extension mnemonics that extend the processor using the
163 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
164 is equivalent to specifying @code{-mcpu=ep9312}.
166 Multiple extensions may be specified, separated by a @code{+}. The
167 extensions should be specified in ascending alphabetical order.
169 Some extensions may be restricted to particular architectures; this is
170 documented in the list of extensions below.
172 Extension mnemonics may also be removed from those the assembler accepts.
173 This is done be prepending @code{no} to the option that adds the extension.
174 Extensions that are removed should be listed after all extensions which have
175 been added, again in ascending alphabetical order. For example,
176 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
179 The following extensions are currently supported:
181 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
182 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
183 @code{fp} (Floating Point Extensions for v8-A architecture),
184 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
185 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
186 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
191 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
193 @code{os} (Operating System for v6M architecture),
194 @code{predres} (Execution and Data Prediction Restriction Instruction for
195 v8-A architectures, added by default from v8.5-A),
196 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
197 default from v8.5-A),
198 @code{sec} (Security Extensions for v6K and v7-A architectures),
199 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
200 @code{virt} (Virtualization Extensions for v7-A architecture, implies
202 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
203 @code{ras} (Reliability, Availability and Serviceability extensions
204 for v8-A architecture),
205 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
210 @cindex @code{-march=} command-line option, ARM
211 @item -march=@var{architecture}[+@var{extension}@dots{}]
212 This option specifies the target architecture. The assembler will issue
213 an error message if an attempt is made to assemble an instruction which
214 will not execute on the target architecture. The following architecture
215 names are recognized:
253 @code{armv8.1-m.main},
258 If both @code{-mcpu} and
259 @code{-march} are specified, the assembler will use
260 the setting for @code{-mcpu}.
262 The architecture option can be extended with a set extension options. These
263 extensions are context sensitive, i.e. the same extension may mean different
264 things when used with different architectures. When used together with a
265 @code{-mfpu} option, the union of both feature enablement is taken.
266 See their availability and meaning below:
268 For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
270 @code{+fp}: Enables VFPv2 instructions.
271 @code{+nofp}: Disables all FPU instrunctions.
275 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
276 @code{+nofp}: Disables all FPU instructions.
280 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
281 @code{+vfpv3-d16}: Alias for @code{+fp}.
282 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
283 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
284 conversion instructions and 16 double-word registers.
285 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
286 instructions and 32 double-word registers.
287 @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
288 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
289 @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
291 @code{+neon}: Alias for @code{+simd}.
292 @code{+neon-vfpv3}: Alias for @code{+simd}.
293 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
294 NEONv1 instructions with 32 double-word registers.
295 @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
296 double-word registers.
297 @code{+mp}: Enables Multiprocessing Extensions.
298 @code{+sec}: Enables Security Extensions.
299 @code{+nofp}: Disables all FPU and NEON instructions.
300 @code{+nosimd}: Disables all NEON instructions.
304 @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
305 @code{+vfpv4-d16}: Alias for @code{+fp}.
306 @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
307 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
308 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
309 conversion instructions and 16 double-word registers.
310 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
311 instructions and 32 double-word registers.
312 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
313 @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
314 double-word registers.
315 @code{+neon-vfpv4}: Alias for @code{+simd}.
316 @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
318 @code{+neon-vfpv3}: Alias for @code{+neon}.
319 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
320 NEONv1 instructions with 32 double-word registers.
321 double-word registers.
322 @code{+nofp}: Disables all FPU and NEON instructions.
323 @code{+nosimd}: Disables all NEON instructions.
327 @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
328 double-word registers.
329 @code{+vfpv3xd}: Alias for @code{+fp.sp}.
330 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
331 @code{+vfpv3-d16}: Alias for @code{+fp}.
332 @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
333 floating-point conversion instructions with 16 double-word registers.
334 @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
335 conversion instructions with 16 double-word registers.
336 @code{+idiv}: Enables integer division instructions in ARM mode.
337 @code{+nofp}: Disables all FPU instructions.
341 @code{+fp}: Enables single-precision only VFPv4 instructions with 16
342 double-word registers.
343 @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
344 @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
345 double-word registers.
346 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
347 @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
348 @code{+nofp}: Disables all FPU instructions.
350 For @code{armv8-m.main}:
352 @code{+dsp}: Enables DSP Extension.
353 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
354 double-word registers.
355 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
356 @code{+nofp}: Disables all FPU instructions.
357 @code{+nodsp}: Disables DSP Extension.
359 For @code{armv8.1-m.main}:
361 @code{+dsp}: Enables DSP Extension.
362 @code{+fp}: Enables single and half precision scalar Floating Point Extensions
363 for Armv8.1-M Mainline with 16 double-word registers.
364 @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
365 Armv8.1-M Mainline, implies @code{+fp}.
366 @code{+nofp}: Disables all FPU instructions.
367 @code{+nodsp}: Disables DSP Extension.
371 @code{+crc}: Enables CRC32 Extension.
372 @code{+simd}: Enables VFP and NEON for Armv8-A.
373 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
375 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
376 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
378 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
379 @code{+nocrypto}: Disables Cryptography Extensions.
381 For @code{armv8.1-a}:
383 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
384 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
386 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
387 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
389 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
390 @code{+nocrypto}: Disables Cryptography Extensions.
392 For @code{armv8.2-a} and @code{armv8.3-a}:
394 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
395 @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
396 @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
397 for Armv8.2-A, implies @code{+fp16}.
398 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
400 @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
402 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
403 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
405 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
406 @code{+nocrypto}: Disables Cryptography Extensions.
408 For @code{armv8.4-a}:
410 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
412 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
413 Variant Extensions for Armv8.2-A, implies @code{+simd}.
414 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
416 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
417 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
419 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
420 @code{+nocryptp}: Disables Cryptography Extensions.
422 For @code{armv8.5-a}:
424 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
426 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
427 Variant Extensions for Armv8.2-A, implies @code{+simd}.
428 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
430 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
431 @code{+nocryptp}: Disables Cryptography Extensions.
434 @cindex @code{-mfpu=} command-line option, ARM
435 @item -mfpu=@var{floating-point-format}
437 This option specifies the floating point format to assemble for. The
438 assembler will issue an error message if an attempt is made to assemble
439 an instruction which will not execute on the target floating point unit.
440 The following format options are recognized:
460 @code{vfpv3-d16-fp16},
477 @code{neon-fp-armv8},
478 @code{crypto-neon-fp-armv8},
479 @code{neon-fp-armv8.1}
481 @code{crypto-neon-fp-armv8.1}.
483 In addition to determining which instructions are assembled, this option
484 also affects the way in which the @code{.double} assembler directive behaves
485 when assembling little-endian code.
487 The default is dependent on the processor selected. For Architecture 5 or
488 later, the default is to assemble for VFP instructions; for earlier
489 architectures the default is to assemble for FPA instructions.
491 @cindex @code{-mthumb} command-line option, ARM
493 This option specifies that the assembler should start assembling Thumb
494 instructions; that is, it should behave as though the file starts with a
495 @code{.code 16} directive.
497 @cindex @code{-mthumb-interwork} command-line option, ARM
498 @item -mthumb-interwork
499 This option specifies that the output generated by the assembler should
500 be marked as supporting interworking. It also affects the behaviour
501 of the @code{ADR} and @code{ADRL} pseudo opcodes.
503 @cindex @code{-mimplicit-it} command-line option, ARM
504 @item -mimplicit-it=never
505 @itemx -mimplicit-it=always
506 @itemx -mimplicit-it=arm
507 @itemx -mimplicit-it=thumb
508 The @code{-mimplicit-it} option controls the behavior of the assembler when
509 conditional instructions are not enclosed in IT blocks.
510 There are four possible behaviors.
511 If @code{never} is specified, such constructs cause a warning in ARM
512 code and an error in Thumb-2 code.
513 If @code{always} is specified, such constructs are accepted in both
514 ARM and Thumb-2 code, where the IT instruction is added implicitly.
515 If @code{arm} is specified, such constructs are accepted in ARM code
516 and cause an error in Thumb-2 code.
517 If @code{thumb} is specified, such constructs cause a warning in ARM
518 code and are accepted in Thumb-2 code. If you omit this option, the
519 behavior is equivalent to @code{-mimplicit-it=arm}.
521 @cindex @code{-mapcs-26} command-line option, ARM
522 @cindex @code{-mapcs-32} command-line option, ARM
525 These options specify that the output generated by the assembler should
526 be marked as supporting the indicated version of the Arm Procedure.
529 @cindex @code{-matpcs} command-line option, ARM
531 This option specifies that the output generated by the assembler should
532 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
533 enabled this option will cause the assembler to create an empty
534 debugging section in the object file called .arm.atpcs. Debuggers can
535 use this to determine the ABI being used by.
537 @cindex @code{-mapcs-float} command-line option, ARM
539 This indicates the floating point variant of the APCS should be
540 used. In this variant floating point arguments are passed in FP
541 registers rather than integer registers.
543 @cindex @code{-mapcs-reentrant} command-line option, ARM
544 @item -mapcs-reentrant
545 This indicates that the reentrant variant of the APCS should be used.
546 This variant supports position independent code.
548 @cindex @code{-mfloat-abi=} command-line option, ARM
549 @item -mfloat-abi=@var{abi}
550 This option specifies that the output generated by the assembler should be
551 marked as using specified floating point ABI.
552 The following values are recognized:
558 @cindex @code{-eabi=} command-line option, ARM
559 @item -meabi=@var{ver}
560 This option specifies which EABI version the produced object files should
562 The following values are recognized:
568 @cindex @code{-EB} command-line option, ARM
570 This option specifies that the output generated by the assembler should
571 be marked as being encoded for a big-endian processor.
573 Note: If a program is being built for a system with big-endian data
574 and little-endian instructions then it should be assembled with the
575 @option{-EB} option, (all of it, code and data) and then linked with
576 the @option{--be8} option. This will reverse the endianness of the
577 instructions back to little-endian, but leave the data as big-endian.
579 @cindex @code{-EL} command-line option, ARM
581 This option specifies that the output generated by the assembler should
582 be marked as being encoded for a little-endian processor.
584 @cindex @code{-k} command-line option, ARM
585 @cindex PIC code generation for ARM
587 This option specifies that the output of the assembler should be marked
588 as position-independent code (PIC).
590 @cindex @code{--fix-v4bx} command-line option, ARM
592 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
593 the linker option of the same name.
595 @cindex @code{-mwarn-deprecated} command-line option, ARM
596 @item -mwarn-deprecated
597 @itemx -mno-warn-deprecated
598 Enable or disable warnings about using deprecated options or
599 features. The default is to warn.
601 @cindex @code{-mccs} command-line option, ARM
603 Turns on CodeComposer Studio assembly syntax compatibility mode.
605 @cindex @code{-mwarn-syms} command-line option, ARM
607 @itemx -mno-warn-syms
608 Enable or disable warnings about symbols that match the names of ARM
609 instructions. The default is to warn.
617 * ARM-Instruction-Set:: Instruction Set
618 * ARM-Chars:: Special Characters
619 * ARM-Regs:: Register Names
620 * ARM-Relocations:: Relocations
621 * ARM-Neon-Alignment:: NEON Alignment Specifiers
624 @node ARM-Instruction-Set
625 @subsection Instruction Set Syntax
626 Two slightly different syntaxes are support for ARM and THUMB
627 instructions. The default, @code{divided}, uses the old style where
628 ARM and THUMB instructions had their own, separate syntaxes. The new,
629 @code{unified} syntax, which can be selected via the @code{.syntax}
630 directive, and has the following main features:
634 Immediate operands do not require a @code{#} prefix.
637 The @code{IT} instruction may appear, and if it does it is validated
638 against subsequent conditional affixes. In ARM mode it does not
639 generate machine code, in THUMB mode it does.
642 For ARM instructions the conditional affixes always appear at the end
643 of the instruction. For THUMB instructions conditional affixes can be
644 used, but only inside the scope of an @code{IT} instruction.
647 All of the instructions new to the V6T2 architecture (and later) are
648 available. (Only a few such instructions can be written in the
649 @code{divided} syntax).
652 The @code{.N} and @code{.W} suffixes are recognized and honored.
655 All instructions set the flags if and only if they have an @code{s}
660 @subsection Special Characters
662 @cindex line comment character, ARM
663 @cindex ARM line comment character
664 The presence of a @samp{@@} anywhere on a line indicates the start of
665 a comment that extends to the end of that line.
667 If a @samp{#} appears as the first character of a line then the whole
668 line is treated as a comment, but in this case the line could also be
669 a logical line number directive (@pxref{Comments}) or a preprocessor
670 control command (@pxref{Preprocessing}).
672 @cindex line separator, ARM
673 @cindex statement separator, ARM
674 @cindex ARM line separator
675 The @samp{;} character can be used instead of a newline to separate
678 @cindex immediate character, ARM
679 @cindex ARM immediate character
680 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
682 @cindex identifiers, ARM
683 @cindex ARM identifiers
684 *TODO* Explain about /data modifier on symbols.
687 @subsection Register Names
689 @cindex ARM register names
690 @cindex register names, ARM
691 *TODO* Explain about ARM register naming, and the predefined names.
693 @node ARM-Relocations
694 @subsection ARM relocation generation
696 @cindex data relocations, ARM
697 @cindex ARM data relocations
698 Specific data relocations can be generated by putting the relocation name
699 in parentheses after the symbol name. For example:
705 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
707 The following relocations are supported:
723 For compatibility with older toolchains the assembler also accepts
724 @code{(PLT)} after branch targets. On legacy targets this will
725 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
726 targets it will encode either the @samp{R_ARM_CALL} or
727 @samp{R_ARM_JUMP24} relocation, as appropriate.
729 @cindex MOVW and MOVT relocations, ARM
730 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
731 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
732 respectively. For example to load the 32-bit address of foo into r0:
735 MOVW r0, #:lower16:foo
736 MOVT r0, #:upper16:foo
739 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
740 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
741 generated by prefixing the value with @samp{#:lower0_7:#},
742 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
743 respectively. For example to load the 32-bit address of foo into r0:
746 MOVS r0, #:upper8_15:#foo
748 ADDS r0, #:upper0_7:#foo
750 ADDS r0, #:lower8_15:#foo
752 ADDS r0, #:lower0_7:#foo
755 @node ARM-Neon-Alignment
756 @subsection NEON Alignment Specifiers
758 @cindex alignment for NEON instructions
759 Some NEON load/store instructions allow an optional address
761 The ARM documentation specifies that this is indicated by
762 @samp{@@ @var{align}}. However GAS already interprets
763 the @samp{@@} character as a "line comment" start,
764 so @samp{: @var{align}} is used instead. For example:
767 vld1.8 @{q0@}, [r0, :128]
770 @node ARM Floating Point
771 @section Floating Point
773 @cindex floating point, ARM (@sc{ieee})
774 @cindex ARM floating point (@sc{ieee})
775 The ARM family uses @sc{ieee} floating-point numbers.
778 @section ARM Machine Directives
780 @cindex machine directives, ARM
781 @cindex ARM machine directives
784 @c AAAAAAAAAAAAAAAAAAAAAAAAA
787 @cindex @code{.2byte} directive, ARM
788 @cindex @code{.4byte} directive, ARM
789 @cindex @code{.8byte} directive, ARM
790 @item .2byte @var{expression} [, @var{expression}]*
791 @itemx .4byte @var{expression} [, @var{expression}]*
792 @itemx .8byte @var{expression} [, @var{expression}]*
793 These directives write 2, 4 or 8 byte values to the output section.
796 @cindex @code{.align} directive, ARM
797 @item .align @var{expression} [, @var{expression}]
798 This is the generic @var{.align} directive. For the ARM however if the
799 first argument is zero (ie no alignment is needed) the assembler will
800 behave as if the argument had been 2 (ie pad to the next four byte
801 boundary). This is for compatibility with ARM's own assembler.
803 @cindex @code{.arch} directive, ARM
804 @item .arch @var{name}
805 Select the target architecture. Valid values for @var{name} are the same as
806 for the @option{-march} command-line option without the instruction set
809 Specifying @code{.arch} clears any previously selected architecture
812 @cindex @code{.arch_extension} directive, ARM
813 @item .arch_extension @var{name}
814 Add or remove an architecture extension to the target architecture. Valid
815 values for @var{name} are the same as those accepted as architectural
816 extensions by the @option{-mcpu} and @option{-march} command-line options.
818 @code{.arch_extension} may be used multiple times to add or remove extensions
819 incrementally to the architecture being compiled for.
821 @cindex @code{.arm} directive, ARM
823 This performs the same action as @var{.code 32}.
825 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
827 @cindex @code{.bss} directive, ARM
829 This directive switches to the @code{.bss} section.
831 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
833 @cindex @code{.cantunwind} directive, ARM
835 Prevents unwinding through the current function. No personality routine
836 or exception table data is required or permitted.
838 @cindex @code{.code} directive, ARM
839 @item .code @code{[16|32]}
840 This directive selects the instruction set being generated. The value 16
841 selects Thumb, with the value 32 selecting ARM.
843 @cindex @code{.cpu} directive, ARM
844 @item .cpu @var{name}
845 Select the target processor. Valid values for @var{name} are the same as
846 for the @option{-mcpu} command-line option without the instruction set
849 Specifying @code{.cpu} clears any previously selected architecture
852 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
854 @cindex @code{.dn} and @code{.qn} directives, ARM
855 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
856 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
858 The @code{dn} and @code{qn} directives are used to create typed
859 and/or indexed register aliases for use in Advanced SIMD Extension
860 (Neon) instructions. The former should be used to create aliases
861 of double-precision registers, and the latter to create aliases of
862 quad-precision registers.
864 If these directives are used to create typed aliases, those aliases can
865 be used in Neon instructions instead of writing types after the mnemonic
866 or after each operand. For example:
875 This is equivalent to writing the following:
881 Aliases created using @code{dn} or @code{qn} can be destroyed using
884 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
886 @cindex @code{.eabi_attribute} directive, ARM
887 @item .eabi_attribute @var{tag}, @var{value}
888 Set the EABI object attribute @var{tag} to @var{value}.
890 The @var{tag} is either an attribute number, or one of the following:
891 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
892 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
893 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
894 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
895 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
896 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
897 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
898 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
899 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
900 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
901 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
902 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
903 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
904 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
905 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
906 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
907 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
908 @code{Tag_conformance}, @code{Tag_T2EE_use},
909 @code{Tag_Virtualization_use}
911 The @var{value} is either a @code{number}, @code{"string"}, or
912 @code{number, "string"} depending on the tag.
914 Note - the following legacy values are also accepted by @var{tag}:
915 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
916 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
918 @cindex @code{.even} directive, ARM
920 This directive aligns to an even-numbered address.
922 @cindex @code{.extend} directive, ARM
923 @cindex @code{.ldouble} directive, ARM
924 @item .extend @var{expression} [, @var{expression}]*
925 @itemx .ldouble @var{expression} [, @var{expression}]*
926 These directives write 12byte long double floating-point values to the
927 output section. These are not compatible with current ARM processors
930 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
933 @cindex @code{.fnend} directive, ARM
935 Marks the end of a function with an unwind table entry. The unwind index
936 table entry is created when this directive is processed.
938 If no personality routine has been specified then standard personality
939 routine 0 or 1 will be used, depending on the number of unwind opcodes
943 @cindex @code{.fnstart} directive, ARM
945 Marks the start of a function with an unwind table entry.
947 @cindex @code{.force_thumb} directive, ARM
949 This directive forces the selection of Thumb instructions, even if the
950 target processor does not support those instructions
952 @cindex @code{.fpu} directive, ARM
953 @item .fpu @var{name}
954 Select the floating-point unit to assemble for. Valid values for @var{name}
955 are the same as for the @option{-mfpu} command-line option.
957 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
958 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
960 @cindex @code{.handlerdata} directive, ARM
962 Marks the end of the current function, and the start of the exception table
963 entry for that function. Anything between this directive and the
964 @code{.fnend} directive will be added to the exception table entry.
966 Must be preceded by a @code{.personality} or @code{.personalityindex}
969 @c IIIIIIIIIIIIIIIIIIIIIIIIII
971 @cindex @code{.inst} directive, ARM
972 @item .inst @var{opcode} [ , @dots{} ]
973 @itemx .inst.n @var{opcode} [ , @dots{} ]
974 @itemx .inst.w @var{opcode} [ , @dots{} ]
975 Generates the instruction corresponding to the numerical value @var{opcode}.
976 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
977 specified explicitly, overriding the normal encoding rules.
979 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
980 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
981 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
983 @item .ldouble @var{expression} [, @var{expression}]*
986 @cindex @code{.ltorg} directive, ARM
988 This directive causes the current contents of the literal pool to be
989 dumped into the current section (which is assumed to be the .text
990 section) at the current location (aligned to a word boundary).
991 @code{GAS} maintains a separate literal pool for each section and each
992 sub-section. The @code{.ltorg} directive will only affect the literal
993 pool of the current section and sub-section. At the end of assembly
994 all remaining, un-empty literal pools will automatically be dumped.
996 Note - older versions of @code{GAS} would dump the current literal
997 pool any time a section change occurred. This is no longer done, since
998 it prevents accurate control of the placement of literal pools.
1000 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
1002 @cindex @code{.movsp} directive, ARM
1003 @item .movsp @var{reg} [, #@var{offset}]
1004 Tell the unwinder that @var{reg} contains an offset from the current
1005 stack pointer. If @var{offset} is not specified then it is assumed to be
1008 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
1009 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
1011 @cindex @code{.object_arch} directive, ARM
1012 @item .object_arch @var{name}
1013 Override the architecture recorded in the EABI object attribute section.
1014 Valid values for @var{name} are the same as for the @code{.arch} directive.
1015 Typically this is useful when code uses runtime detection of CPU features.
1017 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
1019 @cindex @code{.packed} directive, ARM
1020 @item .packed @var{expression} [, @var{expression}]*
1021 This directive writes 12-byte packed floating-point values to the
1022 output section. These are not compatible with current ARM processors
1026 @cindex @code{.pad} directive, ARM
1027 @item .pad #@var{count}
1028 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
1029 A positive value indicates the function prologue allocated stack space by
1030 decrementing the stack pointer.
1032 @cindex @code{.personality} directive, ARM
1033 @item .personality @var{name}
1034 Sets the personality routine for the current function to @var{name}.
1036 @cindex @code{.personalityindex} directive, ARM
1037 @item .personalityindex @var{index}
1038 Sets the personality routine for the current function to the EABI standard
1039 routine number @var{index}
1041 @cindex @code{.pool} directive, ARM
1043 This is a synonym for .ltorg.
1045 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
1046 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
1048 @cindex @code{.req} directive, ARM
1049 @item @var{name} .req @var{register name}
1050 This creates an alias for @var{register name} called @var{name}. For
1057 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
1060 @cindex @code{.save} directive, ARM
1061 @item .save @var{reglist}
1062 Generate unwinder annotations to restore the registers in @var{reglist}.
1063 The format of @var{reglist} is the same as the corresponding store-multiple
1067 @exdent @emph{core registers}
1068 .save @{r4, r5, r6, lr@}
1069 stmfd sp!, @{r4, r5, r6, lr@}
1070 @exdent @emph{FPA registers}
1073 @exdent @emph{VFP registers}
1074 .save @{d8, d9, d10@}
1075 fstmdx sp!, @{d8, d9, d10@}
1076 @exdent @emph{iWMMXt registers}
1077 .save @{wr10, wr11@}
1078 wstrd wr11, [sp, #-8]!
1079 wstrd wr10, [sp, #-8]!
1082 wstrd wr11, [sp, #-8]!
1084 wstrd wr10, [sp, #-8]!
1088 @cindex @code{.setfp} directive, ARM
1089 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
1090 Make all unwinder annotations relative to a frame pointer. Without this
1091 the unwinder will use offsets from the stack pointer.
1093 The syntax of this directive is the same as the @code{add} or @code{mov}
1094 instruction used to set the frame pointer. @var{spreg} must be either
1095 @code{sp} or mentioned in a previous @code{.movsp} directive.
1105 @cindex @code{.secrel32} directive, ARM
1106 @item .secrel32 @var{expression} [, @var{expression}]*
1107 This directive emits relocations that evaluate to the section-relative
1108 offset of each expression's symbol. This directive is only supported
1111 @cindex @code{.syntax} directive, ARM
1112 @item .syntax [@code{unified} | @code{divided}]
1113 This directive sets the Instruction Set Syntax as described in the
1114 @ref{ARM-Instruction-Set} section.
1116 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
1118 @cindex @code{.thumb} directive, ARM
1120 This performs the same action as @var{.code 16}.
1122 @cindex @code{.thumb_func} directive, ARM
1124 This directive specifies that the following symbol is the name of a
1125 Thumb encoded function. This information is necessary in order to allow
1126 the assembler and linker to generate correct code for interworking
1127 between Arm and Thumb instructions and should be used even if
1128 interworking is not going to be performed. The presence of this
1129 directive also implies @code{.thumb}
1131 This directive is not necessary when generating EABI objects. On these
1132 targets the encoding is implicit when generating Thumb code.
1134 @cindex @code{.thumb_set} directive, ARM
1136 This performs the equivalent of a @code{.set} directive in that it
1137 creates a symbol which is an alias for another symbol (possibly not yet
1138 defined). This directive also has the added property in that it marks
1139 the aliased symbol as being a thumb function entry point, in the same
1140 way that the @code{.thumb_func} directive does.
1142 @cindex @code{.tlsdescseq} directive, ARM
1143 @item .tlsdescseq @var{tls-variable}
1144 This directive is used to annotate parts of an inlined TLS descriptor
1145 trampoline. Normally the trampoline is provided by the linker, and
1146 this directive is not needed.
1148 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
1150 @cindex @code{.unreq} directive, ARM
1151 @item .unreq @var{alias-name}
1152 This undefines a register alias which was previously defined using the
1153 @code{req}, @code{dn} or @code{qn} directives. For example:
1160 An error occurs if the name is undefined. Note - this pseudo op can
1161 be used to delete builtin in register name aliases (eg 'r0'). This
1162 should only be done if it is really necessary.
1164 @cindex @code{.unwind_raw} directive, ARM
1165 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
1166 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
1167 the stack pointer by @var{offset} bytes.
1169 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1172 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1174 @cindex @code{.vsave} directive, ARM
1175 @item .vsave @var{vfp-reglist}
1176 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1177 using FLDMD. Also works for VFPv3 registers
1178 that are to be restored using VLDM.
1179 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1183 @exdent @emph{VFP registers}
1184 .vsave @{d8, d9, d10@}
1185 fstmdd sp!, @{d8, d9, d10@}
1186 @exdent @emph{VFPv3 registers}
1187 .vsave @{d15, d16, d17@}
1188 vstm sp!, @{d15, d16, d17@}
1191 Since FLDMX and FSTMX are now deprecated, this directive should be
1192 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1194 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1195 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1196 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1197 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1205 @cindex opcodes for ARM
1206 @code{@value{AS}} implements all the standard ARM opcodes. It also
1207 implements several pseudo opcodes, including several synthetic load
1212 @cindex @code{NOP} pseudo op, ARM
1218 This pseudo op will always evaluate to a legal ARM instruction that does
1219 nothing. Currently it will evaluate to MOV r0, r0.
1221 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1224 ldr <register> , = <expression>
1227 If expression evaluates to a numeric constant then a MOV or MVN
1228 instruction will be used in place of the LDR instruction, if the
1229 constant can be generated by either of these instructions. Otherwise
1230 the constant will be placed into the nearest literal pool (if it not
1231 already there) and a PC relative LDR instruction will be generated.
1233 @cindex @code{ADR reg,<label>} pseudo op, ARM
1236 adr <register> <label>
1239 This instruction will load the address of @var{label} into the indicated
1240 register. The instruction will evaluate to a PC relative ADD or SUB
1241 instruction depending upon where the label is located. If the label is
1242 out of range, or if it is not defined in the same file (and section) as
1243 the ADR instruction, then an error will be generated. This instruction
1244 will not make use of the literal pool.
1246 If @var{label} is a thumb function symbol, and thumb interworking has
1247 been enabled via the @option{-mthumb-interwork} option then the bottom
1248 bit of the value stored into @var{register} will be set. This allows
1249 the following sequence to work as expected:
1252 adr r0, thumb_function
1256 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1259 adrl <register> <label>
1262 This instruction will load the address of @var{label} into the indicated
1263 register. The instruction will evaluate to one or two PC relative ADD
1264 or SUB instructions depending upon where the label is located. If a
1265 second instruction is not needed a NOP instruction will be generated in
1266 its place, so that this instruction is always 8 bytes long.
1268 If the label is out of range, or if it is not defined in the same file
1269 (and section) as the ADRL instruction, then an error will be generated.
1270 This instruction will not make use of the literal pool.
1272 If @var{label} is a thumb function symbol, and thumb interworking has
1273 been enabled via the @option{-mthumb-interwork} option then the bottom
1274 bit of the value stored into @var{register} will be set.
1278 For information on the ARM or Thumb instruction sets, see @cite{ARM
1279 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1282 @node ARM Mapping Symbols
1283 @section Mapping Symbols
1285 The ARM ELF specification requires that special symbols be inserted
1286 into object files to mark certain features:
1292 At the start of a region of code containing ARM instructions.
1296 At the start of a region of code containing THUMB instructions.
1300 At the start of a region of data.
1304 The assembler will automatically insert these symbols for you - there
1305 is no need to code them yourself. Support for tagging symbols ($b,
1306 $f, $p and $m) which is also mentioned in the current ARM ELF
1307 specification is not implemented. This is because they have been
1308 dropped from the new EABI and so tools cannot rely upon their
1311 @node ARM Unwinding Tutorial
1314 The ABI for the ARM Architecture specifies a standard format for
1315 exception unwind information. This information is used when an
1316 exception is thrown to determine where control should be transferred.
1317 In particular, the unwind information is used to determine which
1318 function called the function that threw the exception, and which
1319 function called that one, and so forth. This information is also used
1320 to restore the values of callee-saved registers in the function
1321 catching the exception.
1323 If you are writing functions in assembly code, and those functions
1324 call other functions that throw exceptions, you must use assembly
1325 pseudo ops to ensure that appropriate exception unwind information is
1326 generated. Otherwise, if one of the functions called by your assembly
1327 code throws an exception, the run-time library will be unable to
1328 unwind the stack through your assembly code and your program will not
1331 To illustrate the use of these pseudo ops, we will examine the code
1332 that G++ generates for the following C++ input:
1335 void callee (int *);
1346 This example does not show how to throw or catch an exception from
1347 assembly code. That is a much more complex operation and should
1348 always be done in a high-level language, such as C++, that directly
1349 supports exceptions.
1351 The code generated by one particular version of G++ when compiling the
1358 @ Function supports interworking.
1359 @ args = 0, pretend = 0, frame = 8
1360 @ frame_needed = 1, uses_anonymous_args = 0
1382 Of course, the sequence of instructions varies based on the options
1383 you pass to GCC and on the version of GCC in use. The exact
1384 instructions are not important since we are focusing on the pseudo ops
1385 that are used to generate unwind information.
1387 An important assumption made by the unwinder is that the stack frame
1388 does not change during the body of the function. In particular, since
1389 we assume that the assembly code does not itself throw an exception,
1390 the only point where an exception can be thrown is from a call, such
1391 as the @code{bl} instruction above. At each call site, the same saved
1392 registers (including @code{lr}, which indicates the return address)
1393 must be located in the same locations relative to the frame pointer.
1395 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1396 op appears immediately before the first instruction of the function
1397 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1398 op appears immediately after the last instruction of the function.
1399 These pseudo ops specify the range of the function.
1401 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1402 @code{.pad}) matters; their exact locations are irrelevant. In the
1403 example above, the compiler emits the pseudo ops with particular
1404 instructions. That makes it easier to understand the code, but it is
1405 not required for correctness. It would work just as well to emit all
1406 of the pseudo ops other than @code{.fnend} in the same order, but
1407 immediately after @code{.fnstart}.
1409 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1410 indicates registers that have been saved to the stack so that they can
1411 be restored before the function returns. The argument to the
1412 @code{.save} pseudo op is a list of registers to save. If a register
1413 is ``callee-saved'' (as specified by the ABI) and is modified by the
1414 function you are writing, then your code must save the value before it
1415 is modified and restore the original value before the function
1416 returns. If an exception is thrown, the run-time library restores the
1417 values of these registers from their locations on the stack before
1418 returning control to the exception handler. (Of course, if an
1419 exception is not thrown, the function that contains the @code{.save}
1420 pseudo op restores these registers in the function epilogue, as is
1421 done with the @code{ldmfd} instruction above.)
1423 You do not have to save callee-saved registers at the very beginning
1424 of the function and you do not need to use the @code{.save} pseudo op
1425 immediately following the point at which the registers are saved.
1426 However, if you modify a callee-saved register, you must save it on
1427 the stack before modifying it and before calling any functions which
1428 might throw an exception. And, you must use the @code{.save} pseudo
1429 op to indicate that you have done so.
1431 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1432 modification of the stack pointer that does not save any registers.
1433 The argument is the number of bytes (in decimal) that are subtracted
1434 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1435 subtracting from the stack pointer increases the size of the stack.)
1437 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1438 indicates the register that contains the frame pointer. The first
1439 argument is the register that is set, which is typically @code{fp}.
1440 The second argument indicates the register from which the frame
1441 pointer takes its value. The third argument, if present, is the value
1442 (in decimal) added to the register specified by the second argument to
1443 compute the value of the frame pointer. You should not modify the
1444 frame pointer in the body of the function.
1446 If you do not use a frame pointer, then you should not use the
1447 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1448 should avoid modifying the stack pointer outside of the function
1449 prologue. Otherwise, the run-time library will be unable to find
1450 saved registers when it is unwinding the stack.
1452 The pseudo ops described above are sufficient for writing assembly
1453 code that calls functions which may throw exceptions. If you need to
1454 know more about the object-file format used to represent unwind
1455 information, you may consult the @cite{Exception Handling ABI for the
1456 ARM Architecture} available from @uref{http://infocenter.arm.com}.