gas/doc/c-arm.texi

   1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5
   6 @ifset GENERIC
   7 @page
   8 @node ARM-Dependent
   9 @chapter ARM Dependent Features
  10 @end ifset
  11
  12 @ifclear GENERIC
  13 @node Machine Dependencies
  14 @chapter ARM Dependent Features
  15 @end ifclear
  16
  17 @cindex ARM support
  18 @cindex Thumb support
  19 @menu
  20 * ARM Options::              Options
  21 * ARM Syntax::               Syntax
  22 * ARM Floating Point::       Floating Point
  23 * ARM Directives::           ARM Machine Directives
  24 * ARM Opcodes::              Opcodes
  25 * ARM Mapping Symbols::      Mapping Symbols
  26 @end menu
  27
  28 @node ARM Options
  29 @section Options
  30 @cindex ARM options (none)
  31 @cindex options for ARM (none)
  32
  33 @table @code
  34
  35 @cindex @code{-mcpu=} command line option, ARM
  36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  37 This option specifies the target processor.  The assembler will issue an
  38 error message if an attempt is made to assemble an instruction which
  39 will not execute on the target processor.  The following processor names are
  40 recognized:
  41 @code{arm1},
  42 @code{arm2},
  43 @code{arm250},
  44 @code{arm3},
  45 @code{arm6},
  46 @code{arm60},
  47 @code{arm600},
  48 @code{arm610},
  49 @code{arm620},
  50 @code{arm7},
  51 @code{arm7m},
  52 @code{arm7d},
  53 @code{arm7dm},
  54 @code{arm7di},
  55 @code{arm7dmi},
  56 @code{arm70},
  57 @code{arm700},
  58 @code{arm700i},
  59 @code{arm710},
  60 @code{arm710t},
  61 @code{arm720},
  62 @code{arm720t},
  63 @code{arm740t},
  64 @code{arm710c},
  65 @code{arm7100},
  66 @code{arm7500},
  67 @code{arm7500fe},
  68 @code{arm7t},
  69 @code{arm7tdmi},
  70 @code{arm7tdmi-s},
  71 @code{arm8},
  72 @code{arm810},
  73 @code{strongarm},
  74 @code{strongarm1},
  75 @code{strongarm110},
  76 @code{strongarm1100},
  77 @code{strongarm1110},
  78 @code{arm9},
  79 @code{arm920},
  80 @code{arm920t},
  81 @code{arm922t},
  82 @code{arm940t},
  83 @code{arm9tdmi},
  84 @code{arm9e},
  85 @code{arm926e},
  86 @code{arm926ej-s},
  87 @code{arm946e-r0},
  88 @code{arm946e},
  89 @code{arm946e-s},
  90 @code{arm966e-r0},
  91 @code{arm966e},
  92 @code{arm966e-s},
  93 @code{arm968e-s},
  94 @code{arm10t},
  95 @code{arm10tdmi},
  96 @code{arm10e},
  97 @code{arm1020},
  98 @code{arm1020t},
  99 @code{arm1020e},
 100 @code{arm1022e},
 101 @code{arm1026ej-s},
 102 @code{arm1136j-s},
 103 @code{arm1136jf-s},
 104 @code{arm1156t2-s},
 105 @code{arm1156t2f-s},
 106 @code{arm1176jz-s},
 107 @code{arm1176jzf-s},
 108 @code{mpcore},
 109 @code{mpcorenovfp},
 110 @code{cortex-a8},
 111 @code{cortex-r4},
 112 @code{cortex-m3},
 113 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
 114 @code{i80200} (Intel XScale processor)
 115 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
 116 and
 117 @code{xscale}.
 118 The special name @code{all} may be used to allow the
 119 assembler to accept instructions valid for any ARM processor.
 120
 121 In addition to the basic instruction set, the assembler can be told to
 122 accept various extension mnemonics that extend the processor using the
 123 co-processor instruction space.  For example, @code{-mcpu=arm920+maverick}
 124 is equivalent to specifying @code{-mcpu=ep9312}.  The following extensions
 125 are currently supported:
 126 @code{+maverick}
 127 @code{+iwmmxt}
 128 and
 129 @code{+xscale}.
 130
 131 @cindex @code{-march=} command line option, ARM
 132 @item -march=@var{architecture}[+@var{extension}@dots{}]
 133 This option specifies the target architecture.  The assembler will issue
 134 an error message if an attempt is made to assemble an instruction which
 135 will not execute on the target architecture.  The following architecture
 136 names are recognized:
 137 @code{armv1},
 138 @code{armv2},
 139 @code{armv2a},
 140 @code{armv2s},
 141 @code{armv3},
 142 @code{armv3m},
 143 @code{armv4},
 144 @code{armv4xm},
 145 @code{armv4t},
 146 @code{armv4txm},
 147 @code{armv5},
 148 @code{armv5t},
 149 @code{armv5txm},
 150 @code{armv5te},
 151 @code{armv5texp},
 152 @code{armv6},
 153 @code{armv6j},
 154 @code{armv6k},
 155 @code{armv6z},
 156 @code{armv6zk},
 157 @code{armv7},
 158 @code{armv7-a},
 159 @code{armv7-r},
 160 @code{armv7-m},
 161 @code{iwmmxt}
 162 and
 163 @code{xscale}.
 164 If both @code{-mcpu} and
 165 @code{-march} are specified, the assembler will use
 166 the setting for @code{-mcpu}.
 167
 168 The architecture option can be extended with the same instruction set
 169 extension options as the @code{-mcpu} option.
 170
 171 @cindex @code{-mfpu=} command line option, ARM
 172 @item -mfpu=@var{floating-point-format}
 173
 174 This option specifies the floating point format to assemble for.  The
 175 assembler will issue an error message if an attempt is made to assemble
 176 an instruction which will not execute on the target floating point unit.
 177 The following format options are recognized:
 178 @code{softfpa},
 179 @code{fpe},
 180 @code{fpe2},
 181 @code{fpe3},
 182 @code{fpa},
 183 @code{fpa10},
 184 @code{fpa11},
 185 @code{arm7500fe},
 186 @code{softvfp},
 187 @code{softvfp+vfp},
 188 @code{vfp},
 189 @code{vfp10},
 190 @code{vfp10-r0},
 191 @code{vfp9},
 192 @code{vfpxd},
 193 @code{arm1020t},
 194 @code{arm1020e},
 195 @code{arm1136jf-s}
 196 and
 197 @code{maverick}.
 198
 199 In addition to determining which instructions are assembled, this option
 200 also affects the way in which the @code{.double} assembler directive behaves
 201 when assembling little-endian code.
 202
 203 The default is dependent on the processor selected.  For Architecture 5 or
 204 later, the default is to assembler for VFP instructions; for earlier
 205 architectures the default is to assemble for FPA instructions.
 206
 207 @cindex @code{-mthumb} command line option, ARM
 208 @item -mthumb
 209 This option specifies that the assembler should start assembling Thumb
 210 instructions; that is, it should behave as though the file starts with a
 211 @code{.code 16} directive.
 212
 213 @cindex @code{-mthumb-interwork} command line option, ARM
 214 @item -mthumb-interwork
 215 This option specifies that the output generated by the assembler should
 216 be marked as supporting interworking.
 217
 218 @cindex @code{-mapcs} command line option, ARM
 219 @item -mapcs @code{[26|32]}
 220 This option specifies that the output generated by the assembler should
 221 be marked as supporting the indicated version of the Arm Procedure.
 222 Calling Standard.
 223
 224 @cindex @code{-matpcs} command line option, ARM
 225 @item -matpcs
 226 This option specifies that the output generated by the assembler should
 227 be marked as supporting the Arm/Thumb Procedure Calling Standard.  If
 228 enabled this option will cause the assembler to create an empty
 229 debugging section in the object file called .arm.atpcs.  Debuggers can
 230 use this to determine the ABI being used by.
 231
 232 @cindex @code{-mapcs-float} command line option, ARM
 233 @item -mapcs-float
 234 This indicates the floating point variant of the APCS should be
 235 used.  In this variant floating point arguments are passed in FP
 236 registers rather than integer registers.
 237
 238 @cindex @code{-mapcs-reentrant} command line option, ARM
 239 @item -mapcs-reentrant
 240 This indicates that the reentrant variant of the APCS should be used.
 241 This variant supports position independent code.
 242
 243 @cindex @code{-mfloat-abi=} command line option, ARM
 244 @item -mfloat-abi=@var{abi}
 245 This option specifies that the output generated by the assembler should be
 246 marked as using specified floating point ABI.
 247 The following values are recognized:
 248 @code{soft},
 249 @code{softfp}
 250 and
 251 @code{hard}.
 252
 253 @cindex @code{-eabi=} command line option, ARM
 254 @item -meabi=@var{ver}
 255 This option specifies which EABI version the produced object files should
 256 conform to.
 257 The following values are recognized:
 258 @code{gnu},
 259 @code{4}
 260 and
 261 @code{5}.
 262
 263 @cindex @code{-EB} command line option, ARM
 264 @item -EB
 265 This option specifies that the output generated by the assembler should
 266 be marked as being encoded for a big-endian processor.
 267
 268 @cindex @code{-EL} command line option, ARM
 269 @item -EL
 270 This option specifies that the output generated by the assembler should
 271 be marked as being encoded for a little-endian processor.
 272
 273 @cindex @code{-k} command line option, ARM
 274 @cindex PIC code generation for ARM
 275 @item -k
 276 This option specifies that the output of the assembler should be marked
 277 as position-independent code (PIC).
 278
 279 @end table
 280
 281
 282 @node ARM Syntax
 283 @section Syntax
 284 @menu
 285 * ARM-Chars::                Special Characters
 286 * ARM-Regs::                 Register Names
 287 * ARM-Relocations::          Relocations
 288 @end menu
 289
 290 @node ARM-Chars
 291 @subsection Special Characters
 292
 293 @cindex line comment character, ARM
 294 @cindex ARM line comment character
 295 The presence of a @samp{@@} on a line indicates the start of a comment
 296 that extends to the end of the current line.  If a @samp{#} appears as
 297 the first character of a line, the whole line is treated as a comment.
 298
 299 @cindex line separator, ARM
 300 @cindex statement separator, ARM
 301 @cindex ARM line separator
 302 The @samp{;} character can be used instead of a newline to separate
 303 statements.
 304
 305 @cindex immediate character, ARM
 306 @cindex ARM immediate character
 307 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 308
 309 @cindex identifiers, ARM
 310 @cindex ARM identifiers
 311 *TODO* Explain about /data modifier on symbols.
 312
 313 @node ARM-Regs
 314 @subsection Register Names
 315
 316 @cindex ARM register names
 317 @cindex register names, ARM
 318 *TODO* Explain about ARM register naming, and the predefined names.
 319
 320 @node ARM Floating Point
 321 @section Floating Point
 322
 323 @cindex floating point, ARM (@sc{ieee})
 324 @cindex ARM floating point (@sc{ieee})
 325 The ARM family uses @sc{ieee} floating-point numbers.
 326
 327 @node ARM-Relocations
 328 @subsection ARM relocation generation
 329
 330 @cindex data relocations, ARM
 331 @cindex ARM data relocations
 332 Specific data relocations can be generated by putting the relocation name
 333 in parentheses after the symbol name.  For example:
 334
 335 @smallexample
 336         .word foo(TARGET1)
 337 @end smallexample
 338
 339 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
 340 @var{foo}.
 341 The following relocations are supported:
 342 @code{GOT},
 343 @code{GOTOFF},
 344 @code{TARGET1},
 345 @code{TARGET2},
 346 @code{SBREL},
 347 @code{TLSGD},
 348 @code{TLSLDM},
 349 @code{TLSLDO},
 350 @code{GOTTPOFF}
 351 and
 352 @code{TPOFF}.
 353
 354 For compatibility with older toolchains the assembler also accepts
 355 @code{(PLT)} after branch targets.  This will generate the deprecated
 356 @samp{R_ARM_PLT32} relocation.
 357
 358 @cindex MOVW and MOVT relocations, ARM
 359 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
 360 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
 361 respectively.  For example to load the 32-bit address of foo into r0:
 362
 363 @smallexample
 364         MOVW r0, #:lower16:foo
 365         MOVT r0, #:upper16:foo
 366 @end smallexample
 367
 368 @node ARM Directives
 369 @section ARM Machine Directives
 370
 371 @cindex machine directives, ARM
 372 @cindex ARM machine directives
 373 @table @code
 374
 375 @cindex @code{align} directive, ARM
 376 @item .align @var{expression} [, @var{expression}]
 377 This is the generic @var{.align} directive.  For the ARM however if the
 378 first argument is zero (ie no alignment is needed) the assembler will
 379 behave as if the argument had been 2 (ie pad to the next four byte
 380 boundary).  This is for compatibility with ARM's own assembler.
 381
 382 @cindex @code{req} directive, ARM
 383 @item @var{name} .req @var{register name}
 384 This creates an alias for @var{register name} called @var{name}.  For
 385 example:
 386
 387 @smallexample
 388         foo .req r0
 389 @end smallexample
 390
 391 @cindex @code{unreq} directive, ARM
 392 @item .unreq @var{alias-name}
 393 This undefines a register alias which was previously defined using the
 394 @code{req} directive.  For example:
 395
 396 @smallexample
 397         foo .req r0
 398         .unreq foo
 399 @end smallexample
 400
 401 An error occurs if the name is undefined.  Note - this pseudo op can
 402 be used to delete builtin in register name aliases (eg 'r0').  This
 403 should only be done if it is really necessary.
 404
 405 @cindex @code{code} directive, ARM
 406 @item .code @code{[16|32]}
 407 This directive selects the instruction set being generated. The value 16
 408 selects Thumb, with the value 32 selecting ARM.
 409
 410 @cindex @code{thumb} directive, ARM
 411 @item .thumb
 412 This performs the same action as @var{.code 16}.
 413
 414 @cindex @code{arm} directive, ARM
 415 @item .arm
 416 This performs the same action as @var{.code 32}.
 417
 418 @cindex @code{force_thumb} directive, ARM
 419 @item .force_thumb
 420 This directive forces the selection of Thumb instructions, even if the
 421 target processor does not support those instructions
 422
 423 @cindex @code{thumb_func} directive, ARM
 424 @item .thumb_func
 425 This directive specifies that the following symbol is the name of a
 426 Thumb encoded function.  This information is necessary in order to allow
 427 the assembler and linker to generate correct code for interworking
 428 between Arm and Thumb instructions and should be used even if
 429 interworking is not going to be performed.  The presence of this
 430 directive also implies @code{.thumb}
 431
 432 This directive is not neccessary when generating EABI objects.  On these
 433 targets the encoding is implicit when generating Thumb code.
 434
 435 @cindex @code{thumb_set} directive, ARM
 436 @item .thumb_set
 437 This performs the equivalent of a @code{.set} directive in that it
 438 creates a symbol which is an alias for another symbol (possibly not yet
 439 defined).  This directive also has the added property in that it marks
 440 the aliased symbol as being a thumb function entry point, in the same
 441 way that the @code{.thumb_func} directive does.
 442
 443 @cindex @code{.ltorg} directive, ARM
 444 @item .ltorg
 445 This directive causes the current contents of the literal pool to be
 446 dumped into the current section (which is assumed to be the .text
 447 section) at the current location (aligned to a word boundary).
 448 @code{GAS} maintains a separate literal pool for each section and each
 449 sub-section.  The @code{.ltorg} directive will only affect the literal
 450 pool of the current section and sub-section.  At the end of assembly
 451 all remaining, un-empty literal pools will automatically be dumped.
 452
 453 Note - older versions of @code{GAS} would dump the current literal
 454 pool any time a section change occurred.  This is no longer done, since
 455 it prevents accurate control of the placement of literal pools.
 456
 457 @cindex @code{.pool} directive, ARM
 458 @item .pool
 459 This is a synonym for .ltorg.
 460
 461 @cindex @code{.fnstart} directive, ARM
 462 @item .unwind_fnstart
 463 Marks the start of a function with an unwind table entry.
 464
 465 @cindex @code{.fnend} directive, ARM
 466 @item .unwind_fnend
 467 Marks the end of a function with an unwind table entry.  The unwind index
 468 table entry is created when this directive is processed.
 469
 470 If no personality routine has been specified then standard personality
 471 routine 0 or 1 will be used, depending on the number of unwind opcodes
 472 required.
 473
 474 @cindex @code{.cantunwind} directive, ARM
 475 @item .cantunwind
 476 Prevents unwinding through the current function.  No personality routine
 477 or exception table data is required or permitted.
 478
 479 @cindex @code{.personality} directive, ARM
 480 @item .personality @var{name}
 481 Sets the personality routine for the current function to @var{name}.
 482
 483 @cindex @code{.personalityindex} directive, ARM
 484 @item .personalityindex @var{index}
 485 Sets the personality routine for the current function to the EABI standard
 486 routine number @var{index}
 487
 488 @cindex @code{.handlerdata} directive, ARM
 489 @item .handlerdata
 490 Marks the end of the current function, and the start of the exception table
 491 entry for that function.  Anything between this directive and the
 492 @code{.fnend} directive will be added to the exception table entry.
 493
 494 Must be preceded by a @code{.personality} or @code{.personalityindex}
 495 directive.
 496
 497 @cindex @code{.save} directive, ARM
 498 @item .save @var{reglist}
 499 Generate unwinder annotations to restore the registers in @var{reglist}.
 500 The format of @var{reglist} is the same as the corresponding store-multiple
 501 instruction.
 502
 503 @smallexample
 504 @exdent @emph{core registers}
 505   .save @{r4, r5, r6, lr@}
 506   stmfd sp!, @{r4, r5, r6, lr@}
 507 @exdent @emph{FPA registers}
 508   .save f4, 2
 509   sfmfd f4, 2, [sp]!
 510 @exdent @emph{VFP registers}
 511   .save @{d8, d9, d10@}
 512   fstmdx sp!, @{d8, d9, d10@}
 513 @exdent @emph{iWMMXt registers}
 514   .save @{wr10, wr11@}
 515   wstrd wr11, [sp, #-8]!
 516   wstrd wr10, [sp, #-8]!
 517 or
 518   .save wr11
 519   wstrd wr11, [sp, #-8]!
 520   .save wr10
 521   wstrd wr10, [sp, #-8]!
 522 @end smallexample
 523
 524 @cindex @code{.vsave} directive, ARM
 525 @item .vsave @var{vfp-reglist}
 526 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
 527 using FLDMD.  Also works for VFPv3 registers
 528 that are to be restored using VLDM.
 529 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
 530 instruction.
 531
 532 @smallexample
 533 @exdent @emph{VFP registers}
 534   .vsave @{d8, d9, d10@}
 535   fstmdd sp!, @{d8, d9, d10@}
 536 @exdent @emph{VFPv3 registers}
 537   .vsave @{d15, d16, d17@}
 538   vstm sp!, @{d15, d16, d17@}
 539 @end smallexample
 540
 541 Since FLDMX and FSTMX are now deprecated, this directive should be
 542 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
 543
 544 @cindex @code{.pad} directive, ARM
 545 @item .pad #@var{count}
 546 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
 547 A positive value indicates the function prologue allocated stack space by
 548 decrementing the stack pointer.
 549
 550 @cindex @code{.movsp} directive, ARM
 551 @item .movsp @var{reg} [, #@var{offset}]
 552 Tell the unwinder that @var{reg} contains an offset from the current
 553 stack pointer.  If @var{offset} is not specified then it is assumed to be
 554 zero.
 555
 556 @cindex @code{.setfp} directive, ARM
 557 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
 558 Make all unwinder annotations relaive to a frame pointer.  Without this
 559 the unwinder will use offsets from the stack pointer.
 560
 561 The syntax of this directive is the same as the @code{sub} or @code{mov}
 562 instruction used to set the frame pointer.  @var{spreg} must be either
 563 @code{sp} or mentioned in a previous @code{.movsp} directive.
 564
 565 @smallexample
 566 .movsp ip
 567 mov ip, sp
 568 @dots{}
 569 .setfp fp, ip, #4
 570 sub fp, ip, #4
 571 @end smallexample
 572
 573 @cindex @code{.unwind_raw} directive, ARM
 574 @item .raw @var{offset}, @var{byte1}, @dots{}
 575 Insert one of more arbitary unwind opcode bytes, which are known to adjust
 576 the stack pointer by @var{offset} bytes.
 577
 578 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
 579 @code{.save @{r0@}}
 580
 581 @cindex @code{.cpu} directive, ARM
 582 @item .cpu @var{name}
 583 Select the target processor.  Valid values for @var{name} are the same as
 584 for the @option{-mcpu} commandline option.
 585
 586 @cindex @code{.arch} directive, ARM
 587 @item .arch @var{name}
 588 Select the target architecture.  Valid values for @var{name} are the same as
 589 for the @option{-march} commandline option.
 590
 591 @cindex @code{.object_arch} directive, ARM
 592 @item .object_arch @var{name}
 593 Override the architecture recorded in the EABI object attribute section.
 594 Valid values for @var{name} are the same as for the @code{.arch} directive.
 595 Typically this is useful when code uses runtime detection of CPU features.
 596
 597 @cindex @code{.fpu} directive, ARM
 598 @item .fpu @var{name}
 599 Select the floating point unit to assemble for.  Valid values for @var{name}
 600 are the same as for the @option{-mfpu} commandline option.
 601
 602 @cindex @code{.eabi_attribute} directive, ARM
 603 @item .eabi_attribute @var{tag}, @var{value}
 604 Set the EABI object attribute number @var{tag} to @var{value}.  The value
 605 is either a @code{number}, @code{"string"}, or @code{number, "string"}
 606 depending on the tag.
 607
 608 @end table
 609
 610 @node ARM Opcodes
 611 @section Opcodes
 612
 613 @cindex ARM opcodes
 614 @cindex opcodes for ARM
 615 @code{@value{AS}} implements all the standard ARM opcodes.  It also
 616 implements several pseudo opcodes, including several synthetic load
 617 instructions.
 618
 619 @table @code
 620
 621 @cindex @code{NOP} pseudo op, ARM
 622 @item NOP
 623 @smallexample
 624   nop
 625 @end smallexample
 626
 627 This pseudo op will always evaluate to a legal ARM instruction that does
 628 nothing.  Currently it will evaluate to MOV r0, r0.
 629
 630 @cindex @code{LDR reg,=<label>} pseudo op, ARM
 631 @item LDR
 632 @smallexample
 633   ldr <register> , = <expression>
 634 @end smallexample
 635
 636 If expression evaluates to a numeric constant then a MOV or MVN
 637 instruction will be used in place of the LDR instruction, if the
 638 constant can be generated by either of these instructions.  Otherwise
 639 the constant will be placed into the nearest literal pool (if it not
 640 already there) and a PC relative LDR instruction will be generated.
 641
 642 @cindex @code{ADR reg,<label>} pseudo op, ARM
 643 @item ADR
 644 @smallexample
 645   adr <register> <label>
 646 @end smallexample
 647
 648 This instruction will load the address of @var{label} into the indicated
 649 register.  The instruction will evaluate to a PC relative ADD or SUB
 650 instruction depending upon where the label is located.  If the label is
 651 out of range, or if it is not defined in the same file (and section) as
 652 the ADR instruction, then an error will be generated.  This instruction
 653 will not make use of the literal pool.
 654
 655 @cindex @code{ADRL reg,<label>} pseudo op, ARM
 656 @item ADRL
 657 @smallexample
 658   adrl <register> <label>
 659 @end smallexample
 660
 661 This instruction will load the address of @var{label} into the indicated
 662 register.  The instruction will evaluate to one or two PC relative ADD
 663 or SUB instructions depending upon where the label is located.  If a
 664 second instruction is not needed a NOP instruction will be generated in
 665 its place, so that this instruction is always 8 bytes long.
 666
 667 If the label is out of range, or if it is not defined in the same file
 668 (and section) as the ADRL instruction, then an error will be generated.
 669 This instruction will not make use of the literal pool.
 670
 671 @end table
 672
 673 For information on the ARM or Thumb instruction sets, see @cite{ARM
 674 Software Development Toolkit Reference Manual}, Advanced RISC Machines
 675 Ltd.
 676
 677 @node ARM Mapping Symbols
 678 @section Mapping Symbols
 679
 680 The ARM ELF specification requires that special symbols be inserted
 681 into object files to mark certain features:
 682
 683 @table @code
 684
 685 @cindex @code{$a}
 686 @item $a
 687 At the start of a region of code containing ARM instructions.
 688
 689 @cindex @code{$t}
 690 @item $t
 691 At the start of a region of code containing THUMB instructions.
 692
 693 @cindex @code{$d}
 694 @item $d
 695 At the start of a region of data.
 696
 697 @end table
 698
 699 The assembler will automatically insert these symbols for you - there
 700 is no need to code them yourself.  Support for tagging symbols ($b,
 701 $f, $p and $m) which is also mentioned in the current ARM ELF
 702 specification is not implemented.  This is because they have been
 703 dropped from the new EABI and so tools cannot rely upon their
 704 presence.
 705