1 @c Copyright (C) 1996-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
138 @code{cortex-m0plus},
141 @code{marvell-whitney},
145 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
146 @code{i80200} (Intel XScale processor)
147 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
150 The special name @code{all} may be used to allow the
151 assembler to accept instructions valid for any ARM processor.
153 In addition to the basic instruction set, the assembler can be told to
154 accept various extension mnemonics that extend the processor using the
155 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
156 is equivalent to specifying @code{-mcpu=ep9312}.
158 Multiple extensions may be specified, separated by a @code{+}. The
159 extensions should be specified in ascending alphabetical order.
161 Some extensions may be restricted to particular architectures; this is
162 documented in the list of extensions below.
164 Extension mnemonics may also be removed from those the assembler accepts.
165 This is done be prepending @code{no} to the option that adds the extension.
166 Extensions that are removed should be listed after all extensions which have
167 been added, again in ascending alphabetical order. For example,
168 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
171 The following extensions are currently supported:
173 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
174 @code{fp} (Floating Point Extensions for v8-A architecture),
175 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
180 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
182 @code{os} (Operating System for v6M architecture),
183 @code{sec} (Security Extensions for v6K and v7-A architectures),
184 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
185 @code{virt} (Virtualization Extensions for v7-A architecture, implies
187 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
188 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
193 @cindex @code{-march=} command line option, ARM
194 @item -march=@var{architecture}[+@var{extension}@dots{}]
195 This option specifies the target architecture. The assembler will issue
196 an error message if an attempt is made to assemble an instruction which
197 will not execute on the target architecture. The following architecture
198 names are recognized:
234 If both @code{-mcpu} and
235 @code{-march} are specified, the assembler will use
236 the setting for @code{-mcpu}.
238 The architecture option can be extended with the same instruction set
239 extension options as the @code{-mcpu} option.
241 @cindex @code{-mfpu=} command line option, ARM
242 @item -mfpu=@var{floating-point-format}
244 This option specifies the floating point format to assemble for. The
245 assembler will issue an error message if an attempt is made to assemble
246 an instruction which will not execute on the target floating point unit.
247 The following format options are recognized:
267 @code{vfpv3-d16-fp16},
282 @code{neon-fp-armv8},
283 @code{crypto-neon-fp-armv8},
284 @code{neon-fp-armv8.1}
286 @code{crypto-neon-fp-armv8.1}.
288 In addition to determining which instructions are assembled, this option
289 also affects the way in which the @code{.double} assembler directive behaves
290 when assembling little-endian code.
292 The default is dependent on the processor selected. For Architecture 5 or
293 later, the default is to assembler for VFP instructions; for earlier
294 architectures the default is to assemble for FPA instructions.
296 @cindex @code{-mthumb} command line option, ARM
298 This option specifies that the assembler should start assembling Thumb
299 instructions; that is, it should behave as though the file starts with a
300 @code{.code 16} directive.
302 @cindex @code{-mthumb-interwork} command line option, ARM
303 @item -mthumb-interwork
304 This option specifies that the output generated by the assembler should
305 be marked as supporting interworking.
307 @cindex @code{-mimplicit-it} command line option, ARM
308 @item -mimplicit-it=never
309 @itemx -mimplicit-it=always
310 @itemx -mimplicit-it=arm
311 @itemx -mimplicit-it=thumb
312 The @code{-mimplicit-it} option controls the behavior of the assembler when
313 conditional instructions are not enclosed in IT blocks.
314 There are four possible behaviors.
315 If @code{never} is specified, such constructs cause a warning in ARM
316 code and an error in Thumb-2 code.
317 If @code{always} is specified, such constructs are accepted in both
318 ARM and Thumb-2 code, where the IT instruction is added implicitly.
319 If @code{arm} is specified, such constructs are accepted in ARM code
320 and cause an error in Thumb-2 code.
321 If @code{thumb} is specified, such constructs cause a warning in ARM
322 code and are accepted in Thumb-2 code. If you omit this option, the
323 behavior is equivalent to @code{-mimplicit-it=arm}.
325 @cindex @code{-mapcs-26} command line option, ARM
326 @cindex @code{-mapcs-32} command line option, ARM
329 These options specify that the output generated by the assembler should
330 be marked as supporting the indicated version of the Arm Procedure.
333 @cindex @code{-matpcs} command line option, ARM
335 This option specifies that the output generated by the assembler should
336 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
337 enabled this option will cause the assembler to create an empty
338 debugging section in the object file called .arm.atpcs. Debuggers can
339 use this to determine the ABI being used by.
341 @cindex @code{-mapcs-float} command line option, ARM
343 This indicates the floating point variant of the APCS should be
344 used. In this variant floating point arguments are passed in FP
345 registers rather than integer registers.
347 @cindex @code{-mapcs-reentrant} command line option, ARM
348 @item -mapcs-reentrant
349 This indicates that the reentrant variant of the APCS should be used.
350 This variant supports position independent code.
352 @cindex @code{-mfloat-abi=} command line option, ARM
353 @item -mfloat-abi=@var{abi}
354 This option specifies that the output generated by the assembler should be
355 marked as using specified floating point ABI.
356 The following values are recognized:
362 @cindex @code{-eabi=} command line option, ARM
363 @item -meabi=@var{ver}
364 This option specifies which EABI version the produced object files should
366 The following values are recognized:
372 @cindex @code{-EB} command line option, ARM
374 This option specifies that the output generated by the assembler should
375 be marked as being encoded for a big-endian processor.
377 Note: If a program is being built for a system with big-endian data
378 and little-endian instructions then it should be assembled with the
379 @option{-EB} option, (all of it, code and data) and then linked with
380 the @option{--be8} option. This will reverse the endianness of the
381 instructions back to little-endian, but leave the data as big-endian.
383 @cindex @code{-EL} command line option, ARM
385 This option specifies that the output generated by the assembler should
386 be marked as being encoded for a little-endian processor.
388 @cindex @code{-k} command line option, ARM
389 @cindex PIC code generation for ARM
391 This option specifies that the output of the assembler should be marked
392 as position-independent code (PIC).
394 @cindex @code{--fix-v4bx} command line option, ARM
396 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
397 the linker option of the same name.
399 @cindex @code{-mwarn-deprecated} command line option, ARM
400 @item -mwarn-deprecated
401 @itemx -mno-warn-deprecated
402 Enable or disable warnings about using deprecated options or
403 features. The default is to warn.
405 @cindex @code{-mccs} command line option, ARM
407 Turns on CodeComposer Studio assembly syntax compatibility mode.
409 @cindex @code{-mwarn-syms} command line option, ARM
411 @itemx -mno-warn-syms
412 Enable or disable warnings about symbols that match the names of ARM
413 instructions. The default is to warn.
421 * ARM-Instruction-Set:: Instruction Set
422 * ARM-Chars:: Special Characters
423 * ARM-Regs:: Register Names
424 * ARM-Relocations:: Relocations
425 * ARM-Neon-Alignment:: NEON Alignment Specifiers
428 @node ARM-Instruction-Set
429 @subsection Instruction Set Syntax
430 Two slightly different syntaxes are support for ARM and THUMB
431 instructions. The default, @code{divided}, uses the old style where
432 ARM and THUMB instructions had their own, separate syntaxes. The new,
433 @code{unified} syntax, which can be selected via the @code{.syntax}
434 directive, and has the following main features:
438 Immediate operands do not require a @code{#} prefix.
441 The @code{IT} instruction may appear, and if it does it is validated
442 against subsequent conditional affixes. In ARM mode it does not
443 generate machine code, in THUMB mode it does.
446 For ARM instructions the conditional affixes always appear at the end
447 of the instruction. For THUMB instructions conditional affixes can be
448 used, but only inside the scope of an @code{IT} instruction.
451 All of the instructions new to the V6T2 architecture (and later) are
452 available. (Only a few such instructions can be written in the
453 @code{divided} syntax).
456 The @code{.N} and @code{.W} suffixes are recognized and honored.
459 All instructions set the flags if and only if they have an @code{s}
464 @subsection Special Characters
466 @cindex line comment character, ARM
467 @cindex ARM line comment character
468 The presence of a @samp{@@} anywhere on a line indicates the start of
469 a comment that extends to the end of that line.
471 If a @samp{#} appears as the first character of a line then the whole
472 line is treated as a comment, but in this case the line could also be
473 a logical line number directive (@pxref{Comments}) or a preprocessor
474 control command (@pxref{Preprocessing}).
476 @cindex line separator, ARM
477 @cindex statement separator, ARM
478 @cindex ARM line separator
479 The @samp{;} character can be used instead of a newline to separate
482 @cindex immediate character, ARM
483 @cindex ARM immediate character
484 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
486 @cindex identifiers, ARM
487 @cindex ARM identifiers
488 *TODO* Explain about /data modifier on symbols.
491 @subsection Register Names
493 @cindex ARM register names
494 @cindex register names, ARM
495 *TODO* Explain about ARM register naming, and the predefined names.
497 @node ARM-Relocations
498 @subsection ARM relocation generation
500 @cindex data relocations, ARM
501 @cindex ARM data relocations
502 Specific data relocations can be generated by putting the relocation name
503 in parentheses after the symbol name. For example:
509 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
511 The following relocations are supported:
527 For compatibility with older toolchains the assembler also accepts
528 @code{(PLT)} after branch targets. On legacy targets this will
529 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
530 targets it will encode either the @samp{R_ARM_CALL} or
531 @samp{R_ARM_JUMP24} relocation, as appropriate.
533 @cindex MOVW and MOVT relocations, ARM
534 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
535 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
536 respectively. For example to load the 32-bit address of foo into r0:
539 MOVW r0, #:lower16:foo
540 MOVT r0, #:upper16:foo
543 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
544 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
545 generated by prefixing the value with @samp{#:lower0_7:#},
546 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
547 respectively. For example to load the 32-bit address of foo into r0:
550 MOVS r0, #:upper8_15:#foo
552 ADDS r0, #:upper0_7:#foo
554 ADDS r0, #:lower8_15:#foo
556 ADDS r0, #:lower0_7:#foo
559 @node ARM-Neon-Alignment
560 @subsection NEON Alignment Specifiers
562 @cindex alignment for NEON instructions
563 Some NEON load/store instructions allow an optional address
565 The ARM documentation specifies that this is indicated by
566 @samp{@@ @var{align}}. However GAS already interprets
567 the @samp{@@} character as a "line comment" start,
568 so @samp{: @var{align}} is used instead. For example:
571 vld1.8 @{q0@}, [r0, :128]
574 @node ARM Floating Point
575 @section Floating Point
577 @cindex floating point, ARM (@sc{ieee})
578 @cindex ARM floating point (@sc{ieee})
579 The ARM family uses @sc{ieee} floating-point numbers.
582 @section ARM Machine Directives
584 @cindex machine directives, ARM
585 @cindex ARM machine directives
588 @c AAAAAAAAAAAAAAAAAAAAAAAAA
590 @cindex @code{.2byte} directive, ARM
591 @cindex @code{.4byte} directive, ARM
592 @cindex @code{.8byte} directive, ARM
593 @item .2byte @var{expression} [, @var{expression}]*
594 @itemx .4byte @var{expression} [, @var{expression}]*
595 @itemx .8byte @var{expression} [, @var{expression}]*
596 These directives write 2, 4 or 8 byte values to the output section.
598 @cindex @code{.align} directive, ARM
599 @item .align @var{expression} [, @var{expression}]
600 This is the generic @var{.align} directive. For the ARM however if the
601 first argument is zero (ie no alignment is needed) the assembler will
602 behave as if the argument had been 2 (ie pad to the next four byte
603 boundary). This is for compatibility with ARM's own assembler.
605 @cindex @code{.arch} directive, ARM
606 @item .arch @var{name}
607 Select the target architecture. Valid values for @var{name} are the same as
608 for the @option{-march} commandline option.
610 Specifying @code{.arch} clears any previously selected architecture
613 @cindex @code{.arch_extension} directive, ARM
614 @item .arch_extension @var{name}
615 Add or remove an architecture extension to the target architecture. Valid
616 values for @var{name} are the same as those accepted as architectural
617 extensions by the @option{-mcpu} commandline option.
619 @code{.arch_extension} may be used multiple times to add or remove extensions
620 incrementally to the architecture being compiled for.
622 @cindex @code{.arm} directive, ARM
624 This performs the same action as @var{.code 32}.
626 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
628 @cindex @code{.bss} directive, ARM
630 This directive switches to the @code{.bss} section.
632 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
634 @cindex @code{.cantunwind} directive, ARM
636 Prevents unwinding through the current function. No personality routine
637 or exception table data is required or permitted.
639 @cindex @code{.code} directive, ARM
640 @item .code @code{[16|32]}
641 This directive selects the instruction set being generated. The value 16
642 selects Thumb, with the value 32 selecting ARM.
644 @cindex @code{.cpu} directive, ARM
645 @item .cpu @var{name}
646 Select the target processor. Valid values for @var{name} are the same as
647 for the @option{-mcpu} commandline option.
649 Specifying @code{.cpu} clears any previously selected architecture
652 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
654 @cindex @code{.dn} and @code{.qn} directives, ARM
655 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
656 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
658 The @code{dn} and @code{qn} directives are used to create typed
659 and/or indexed register aliases for use in Advanced SIMD Extension
660 (Neon) instructions. The former should be used to create aliases
661 of double-precision registers, and the latter to create aliases of
662 quad-precision registers.
664 If these directives are used to create typed aliases, those aliases can
665 be used in Neon instructions instead of writing types after the mnemonic
666 or after each operand. For example:
675 This is equivalent to writing the following:
681 Aliases created using @code{dn} or @code{qn} can be destroyed using
684 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
686 @cindex @code{.eabi_attribute} directive, ARM
687 @item .eabi_attribute @var{tag}, @var{value}
688 Set the EABI object attribute @var{tag} to @var{value}.
690 The @var{tag} is either an attribute number, or one of the following:
691 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
692 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
693 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
694 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
695 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
696 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
697 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
698 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
699 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
700 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
701 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
702 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
703 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
704 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
705 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
706 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
707 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
708 @code{Tag_conformance}, @code{Tag_T2EE_use},
709 @code{Tag_Virtualization_use}
711 The @var{value} is either a @code{number}, @code{"string"}, or
712 @code{number, "string"} depending on the tag.
714 Note - the following legacy values are also accepted by @var{tag}:
715 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
716 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
718 @cindex @code{.even} directive, ARM
720 This directive aligns to an even-numbered address.
722 @cindex @code{.extend} directive, ARM
723 @cindex @code{.ldouble} directive, ARM
724 @item .extend @var{expression} [, @var{expression}]*
725 @itemx .ldouble @var{expression} [, @var{expression}]*
726 These directives write 12byte long double floating-point values to the
727 output section. These are not compatible with current ARM processors
730 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
733 @cindex @code{.fnend} directive, ARM
735 Marks the end of a function with an unwind table entry. The unwind index
736 table entry is created when this directive is processed.
738 If no personality routine has been specified then standard personality
739 routine 0 or 1 will be used, depending on the number of unwind opcodes
743 @cindex @code{.fnstart} directive, ARM
745 Marks the start of a function with an unwind table entry.
747 @cindex @code{.force_thumb} directive, ARM
749 This directive forces the selection of Thumb instructions, even if the
750 target processor does not support those instructions
752 @cindex @code{.fpu} directive, ARM
753 @item .fpu @var{name}
754 Select the floating-point unit to assemble for. Valid values for @var{name}
755 are the same as for the @option{-mfpu} commandline option.
757 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
758 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
760 @cindex @code{.handlerdata} directive, ARM
762 Marks the end of the current function, and the start of the exception table
763 entry for that function. Anything between this directive and the
764 @code{.fnend} directive will be added to the exception table entry.
766 Must be preceded by a @code{.personality} or @code{.personalityindex}
769 @c IIIIIIIIIIIIIIIIIIIIIIIIII
771 @cindex @code{.inst} directive, ARM
772 @item .inst @var{opcode} [ , @dots{} ]
773 @itemx .inst.n @var{opcode} [ , @dots{} ]
774 @itemx .inst.w @var{opcode} [ , @dots{} ]
775 Generates the instruction corresponding to the numerical value @var{opcode}.
776 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
777 specified explicitly, overriding the normal encoding rules.
779 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
780 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
781 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
783 @item .ldouble @var{expression} [, @var{expression}]*
786 @cindex @code{.ltorg} directive, ARM
788 This directive causes the current contents of the literal pool to be
789 dumped into the current section (which is assumed to be the .text
790 section) at the current location (aligned to a word boundary).
791 @code{GAS} maintains a separate literal pool for each section and each
792 sub-section. The @code{.ltorg} directive will only affect the literal
793 pool of the current section and sub-section. At the end of assembly
794 all remaining, un-empty literal pools will automatically be dumped.
796 Note - older versions of @code{GAS} would dump the current literal
797 pool any time a section change occurred. This is no longer done, since
798 it prevents accurate control of the placement of literal pools.
800 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
802 @cindex @code{.movsp} directive, ARM
803 @item .movsp @var{reg} [, #@var{offset}]
804 Tell the unwinder that @var{reg} contains an offset from the current
805 stack pointer. If @var{offset} is not specified then it is assumed to be
808 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
809 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
811 @cindex @code{.object_arch} directive, ARM
812 @item .object_arch @var{name}
813 Override the architecture recorded in the EABI object attribute section.
814 Valid values for @var{name} are the same as for the @code{.arch} directive.
815 Typically this is useful when code uses runtime detection of CPU features.
817 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
819 @cindex @code{.packed} directive, ARM
820 @item .packed @var{expression} [, @var{expression}]*
821 This directive writes 12-byte packed floating-point values to the
822 output section. These are not compatible with current ARM processors
826 @cindex @code{.pad} directive, ARM
827 @item .pad #@var{count}
828 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
829 A positive value indicates the function prologue allocated stack space by
830 decrementing the stack pointer.
832 @cindex @code{.personality} directive, ARM
833 @item .personality @var{name}
834 Sets the personality routine for the current function to @var{name}.
836 @cindex @code{.personalityindex} directive, ARM
837 @item .personalityindex @var{index}
838 Sets the personality routine for the current function to the EABI standard
839 routine number @var{index}
841 @cindex @code{.pool} directive, ARM
843 This is a synonym for .ltorg.
845 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
846 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
848 @cindex @code{.req} directive, ARM
849 @item @var{name} .req @var{register name}
850 This creates an alias for @var{register name} called @var{name}. For
857 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
860 @cindex @code{.save} directive, ARM
861 @item .save @var{reglist}
862 Generate unwinder annotations to restore the registers in @var{reglist}.
863 The format of @var{reglist} is the same as the corresponding store-multiple
867 @exdent @emph{core registers}
868 .save @{r4, r5, r6, lr@}
869 stmfd sp!, @{r4, r5, r6, lr@}
870 @exdent @emph{FPA registers}
873 @exdent @emph{VFP registers}
874 .save @{d8, d9, d10@}
875 fstmdx sp!, @{d8, d9, d10@}
876 @exdent @emph{iWMMXt registers}
878 wstrd wr11, [sp, #-8]!
879 wstrd wr10, [sp, #-8]!
882 wstrd wr11, [sp, #-8]!
884 wstrd wr10, [sp, #-8]!
888 @cindex @code{.setfp} directive, ARM
889 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
890 Make all unwinder annotations relative to a frame pointer. Without this
891 the unwinder will use offsets from the stack pointer.
893 The syntax of this directive is the same as the @code{add} or @code{mov}
894 instruction used to set the frame pointer. @var{spreg} must be either
895 @code{sp} or mentioned in a previous @code{.movsp} directive.
905 @cindex @code{.secrel32} directive, ARM
906 @item .secrel32 @var{expression} [, @var{expression}]*
907 This directive emits relocations that evaluate to the section-relative
908 offset of each expression's symbol. This directive is only supported
911 @cindex @code{.syntax} directive, ARM
912 @item .syntax [@code{unified} | @code{divided}]
913 This directive sets the Instruction Set Syntax as described in the
914 @ref{ARM-Instruction-Set} section.
916 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
918 @cindex @code{.thumb} directive, ARM
920 This performs the same action as @var{.code 16}.
922 @cindex @code{.thumb_func} directive, ARM
924 This directive specifies that the following symbol is the name of a
925 Thumb encoded function. This information is necessary in order to allow
926 the assembler and linker to generate correct code for interworking
927 between Arm and Thumb instructions and should be used even if
928 interworking is not going to be performed. The presence of this
929 directive also implies @code{.thumb}
931 This directive is not neccessary when generating EABI objects. On these
932 targets the encoding is implicit when generating Thumb code.
934 @cindex @code{.thumb_set} directive, ARM
936 This performs the equivalent of a @code{.set} directive in that it
937 creates a symbol which is an alias for another symbol (possibly not yet
938 defined). This directive also has the added property in that it marks
939 the aliased symbol as being a thumb function entry point, in the same
940 way that the @code{.thumb_func} directive does.
942 @cindex @code{.tlsdescseq} directive, ARM
943 @item .tlsdescseq @var{tls-variable}
944 This directive is used to annotate parts of an inlined TLS descriptor
945 trampoline. Normally the trampoline is provided by the linker, and
946 this directive is not needed.
948 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
950 @cindex @code{.unreq} directive, ARM
951 @item .unreq @var{alias-name}
952 This undefines a register alias which was previously defined using the
953 @code{req}, @code{dn} or @code{qn} directives. For example:
960 An error occurs if the name is undefined. Note - this pseudo op can
961 be used to delete builtin in register name aliases (eg 'r0'). This
962 should only be done if it is really necessary.
964 @cindex @code{.unwind_raw} directive, ARM
965 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
966 Insert one of more arbitary unwind opcode bytes, which are known to adjust
967 the stack pointer by @var{offset} bytes.
969 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
972 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
974 @cindex @code{.vsave} directive, ARM
975 @item .vsave @var{vfp-reglist}
976 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
977 using FLDMD. Also works for VFPv3 registers
978 that are to be restored using VLDM.
979 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
983 @exdent @emph{VFP registers}
984 .vsave @{d8, d9, d10@}
985 fstmdd sp!, @{d8, d9, d10@}
986 @exdent @emph{VFPv3 registers}
987 .vsave @{d15, d16, d17@}
988 vstm sp!, @{d15, d16, d17@}
991 Since FLDMX and FSTMX are now deprecated, this directive should be
992 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
994 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
995 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
996 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
997 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1005 @cindex opcodes for ARM
1006 @code{@value{AS}} implements all the standard ARM opcodes. It also
1007 implements several pseudo opcodes, including several synthetic load
1012 @cindex @code{NOP} pseudo op, ARM
1018 This pseudo op will always evaluate to a legal ARM instruction that does
1019 nothing. Currently it will evaluate to MOV r0, r0.
1021 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1024 ldr <register> , = <expression>
1027 If expression evaluates to a numeric constant then a MOV or MVN
1028 instruction will be used in place of the LDR instruction, if the
1029 constant can be generated by either of these instructions. Otherwise
1030 the constant will be placed into the nearest literal pool (if it not
1031 already there) and a PC relative LDR instruction will be generated.
1033 @cindex @code{ADR reg,<label>} pseudo op, ARM
1036 adr <register> <label>
1039 This instruction will load the address of @var{label} into the indicated
1040 register. The instruction will evaluate to a PC relative ADD or SUB
1041 instruction depending upon where the label is located. If the label is
1042 out of range, or if it is not defined in the same file (and section) as
1043 the ADR instruction, then an error will be generated. This instruction
1044 will not make use of the literal pool.
1046 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1049 adrl <register> <label>
1052 This instruction will load the address of @var{label} into the indicated
1053 register. The instruction will evaluate to one or two PC relative ADD
1054 or SUB instructions depending upon where the label is located. If a
1055 second instruction is not needed a NOP instruction will be generated in
1056 its place, so that this instruction is always 8 bytes long.
1058 If the label is out of range, or if it is not defined in the same file
1059 (and section) as the ADRL instruction, then an error will be generated.
1060 This instruction will not make use of the literal pool.
1064 For information on the ARM or Thumb instruction sets, see @cite{ARM
1065 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1068 @node ARM Mapping Symbols
1069 @section Mapping Symbols
1071 The ARM ELF specification requires that special symbols be inserted
1072 into object files to mark certain features:
1078 At the start of a region of code containing ARM instructions.
1082 At the start of a region of code containing THUMB instructions.
1086 At the start of a region of data.
1090 The assembler will automatically insert these symbols for you - there
1091 is no need to code them yourself. Support for tagging symbols ($b,
1092 $f, $p and $m) which is also mentioned in the current ARM ELF
1093 specification is not implemented. This is because they have been
1094 dropped from the new EABI and so tools cannot rely upon their
1097 @node ARM Unwinding Tutorial
1100 The ABI for the ARM Architecture specifies a standard format for
1101 exception unwind information. This information is used when an
1102 exception is thrown to determine where control should be transferred.
1103 In particular, the unwind information is used to determine which
1104 function called the function that threw the exception, and which
1105 function called that one, and so forth. This information is also used
1106 to restore the values of callee-saved registers in the function
1107 catching the exception.
1109 If you are writing functions in assembly code, and those functions
1110 call other functions that throw exceptions, you must use assembly
1111 pseudo ops to ensure that appropriate exception unwind information is
1112 generated. Otherwise, if one of the functions called by your assembly
1113 code throws an exception, the run-time library will be unable to
1114 unwind the stack through your assembly code and your program will not
1117 To illustrate the use of these pseudo ops, we will examine the code
1118 that G++ generates for the following C++ input:
1121 void callee (int *);
1132 This example does not show how to throw or catch an exception from
1133 assembly code. That is a much more complex operation and should
1134 always be done in a high-level language, such as C++, that directly
1135 supports exceptions.
1137 The code generated by one particular version of G++ when compiling the
1144 @ Function supports interworking.
1145 @ args = 0, pretend = 0, frame = 8
1146 @ frame_needed = 1, uses_anonymous_args = 0
1168 Of course, the sequence of instructions varies based on the options
1169 you pass to GCC and on the version of GCC in use. The exact
1170 instructions are not important since we are focusing on the pseudo ops
1171 that are used to generate unwind information.
1173 An important assumption made by the unwinder is that the stack frame
1174 does not change during the body of the function. In particular, since
1175 we assume that the assembly code does not itself throw an exception,
1176 the only point where an exception can be thrown is from a call, such
1177 as the @code{bl} instruction above. At each call site, the same saved
1178 registers (including @code{lr}, which indicates the return address)
1179 must be located in the same locations relative to the frame pointer.
1181 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1182 op appears immediately before the first instruction of the function
1183 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1184 op appears immediately after the last instruction of the function.
1185 These pseudo ops specify the range of the function.
1187 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1188 @code{.pad}) matters; their exact locations are irrelevant. In the
1189 example above, the compiler emits the pseudo ops with particular
1190 instructions. That makes it easier to understand the code, but it is
1191 not required for correctness. It would work just as well to emit all
1192 of the pseudo ops other than @code{.fnend} in the same order, but
1193 immediately after @code{.fnstart}.
1195 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1196 indicates registers that have been saved to the stack so that they can
1197 be restored before the function returns. The argument to the
1198 @code{.save} pseudo op is a list of registers to save. If a register
1199 is ``callee-saved'' (as specified by the ABI) and is modified by the
1200 function you are writing, then your code must save the value before it
1201 is modified and restore the original value before the function
1202 returns. If an exception is thrown, the run-time library restores the
1203 values of these registers from their locations on the stack before
1204 returning control to the exception handler. (Of course, if an
1205 exception is not thrown, the function that contains the @code{.save}
1206 pseudo op restores these registers in the function epilogue, as is
1207 done with the @code{ldmfd} instruction above.)
1209 You do not have to save callee-saved registers at the very beginning
1210 of the function and you do not need to use the @code{.save} pseudo op
1211 immediately following the point at which the registers are saved.
1212 However, if you modify a callee-saved register, you must save it on
1213 the stack before modifying it and before calling any functions which
1214 might throw an exception. And, you must use the @code{.save} pseudo
1215 op to indicate that you have done so.
1217 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1218 modification of the stack pointer that does not save any registers.
1219 The argument is the number of bytes (in decimal) that are subtracted
1220 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1221 subtracting from the stack pointer increases the size of the stack.)
1223 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1224 indicates the register that contains the frame pointer. The first
1225 argument is the register that is set, which is typically @code{fp}.
1226 The second argument indicates the register from which the frame
1227 pointer takes its value. The third argument, if present, is the value
1228 (in decimal) added to the register specified by the second argument to
1229 compute the value of the frame pointer. You should not modify the
1230 frame pointer in the body of the function.
1232 If you do not use a frame pointer, then you should not use the
1233 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1234 should avoid modifying the stack pointer outside of the function
1235 prologue. Otherwise, the run-time library will be unable to find
1236 saved registers when it is unwinding the stack.
1238 The pseudo ops described above are sufficient for writing assembly
1239 code that calls functions which may throw exceptions. If you need to
1240 know more about the object-file format used to represent unwind
1241 information, you may consult the @cite{Exception Handling ABI for the
1242 ARM Architecture} available from @uref{http://infocenter.arm.com}.