1 @c Copyright (C) 1996-2020 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
149 @code{cortex-m0plus},
153 @code{marvell-whitney},
159 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
160 @code{i80200} (Intel XScale processor)
161 @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
164 The special name @code{all} may be used to allow the
165 assembler to accept instructions valid for any ARM processor.
167 In addition to the basic instruction set, the assembler can be told to
168 accept various extension mnemonics that extend the processor using the
169 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
170 is equivalent to specifying @code{-mcpu=ep9312}.
172 Multiple extensions may be specified, separated by a @code{+}. The
173 extensions should be specified in ascending alphabetical order.
175 Some extensions may be restricted to particular architectures; this is
176 documented in the list of extensions below.
178 Extension mnemonics may also be removed from those the assembler accepts.
179 This is done be prepending @code{no} to the option that adds the extension.
180 Extensions that are removed should be listed after all extensions which have
181 been added, again in ascending alphabetical order. For example,
182 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
185 The following extensions are currently supported:
186 @code{bf16} (BFloat16 extensions for v8.6-A architecture),
187 @code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
189 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
190 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
191 @code{fp} (Floating Point Extensions for v8-A architecture),
192 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
193 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
194 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
199 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
201 @code{os} (Operating System for v6M architecture),
202 @code{predres} (Execution and Data Prediction Restriction Instruction for
203 v8-A architectures, added by default from v8.5-A),
204 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
205 default from v8.5-A),
206 @code{sec} (Security Extensions for v6K and v7-A architectures),
207 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
208 @code{virt} (Virtualization Extensions for v7-A architecture, implies
210 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
211 @code{ras} (Reliability, Availability and Serviceability extensions
212 for v8-A architecture),
213 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
218 @cindex @code{-march=} command-line option, ARM
219 @item -march=@var{architecture}[+@var{extension}@dots{}]
220 This option specifies the target architecture. The assembler will issue
221 an error message if an attempt is made to assemble an instruction which
222 will not execute on the target architecture. The following architecture
223 names are recognized:
261 @code{armv8.1-m.main},
267 If both @code{-mcpu} and
268 @code{-march} are specified, the assembler will use
269 the setting for @code{-mcpu}.
271 The architecture option can be extended with a set extension options. These
272 extensions are context sensitive, i.e. the same extension may mean different
273 things when used with different architectures. When used together with a
274 @code{-mfpu} option, the union of both feature enablement is taken.
275 See their availability and meaning below:
277 For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
279 @code{+fp}: Enables VFPv2 instructions.
280 @code{+nofp}: Disables all FPU instrunctions.
284 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
285 @code{+nofp}: Disables all FPU instructions.
289 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
290 @code{+vfpv3-d16}: Alias for @code{+fp}.
291 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
292 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
293 conversion instructions and 16 double-word registers.
294 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
295 instructions and 32 double-word registers.
296 @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
297 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
298 @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
300 @code{+neon}: Alias for @code{+simd}.
301 @code{+neon-vfpv3}: Alias for @code{+simd}.
302 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
303 NEONv1 instructions with 32 double-word registers.
304 @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
305 double-word registers.
306 @code{+mp}: Enables Multiprocessing Extensions.
307 @code{+sec}: Enables Security Extensions.
308 @code{+nofp}: Disables all FPU and NEON instructions.
309 @code{+nosimd}: Disables all NEON instructions.
313 @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
314 @code{+vfpv4-d16}: Alias for @code{+fp}.
315 @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
316 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
317 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
318 conversion instructions and 16 double-word registers.
319 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
320 instructions and 32 double-word registers.
321 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
322 @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
323 double-word registers.
324 @code{+neon-vfpv4}: Alias for @code{+simd}.
325 @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
327 @code{+neon-vfpv3}: Alias for @code{+neon}.
328 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
329 NEONv1 instructions with 32 double-word registers.
330 double-word registers.
331 @code{+nofp}: Disables all FPU and NEON instructions.
332 @code{+nosimd}: Disables all NEON instructions.
336 @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
337 double-word registers.
338 @code{+vfpv3xd}: Alias for @code{+fp.sp}.
339 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
340 @code{+vfpv3-d16}: Alias for @code{+fp}.
341 @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
342 floating-point conversion instructions with 16 double-word registers.
343 @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
344 conversion instructions with 16 double-word registers.
345 @code{+idiv}: Enables integer division instructions in ARM mode.
346 @code{+nofp}: Disables all FPU instructions.
350 @code{+fp}: Enables single-precision only VFPv4 instructions with 16
351 double-word registers.
352 @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
353 @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
354 double-word registers.
355 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
356 @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
357 @code{+nofp}: Disables all FPU instructions.
359 For @code{armv8-m.main}:
361 @code{+dsp}: Enables DSP Extension.
362 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
363 double-word registers.
364 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
365 @code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
366 @code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
367 @code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
368 @code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
369 @code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
370 @code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
371 @code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
372 @code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
373 @code{+nofp}: Disables all FPU instructions.
374 @code{+nodsp}: Disables DSP Extension.
376 For @code{armv8.1-m.main}:
378 @code{+dsp}: Enables DSP Extension.
379 @code{+fp}: Enables single and half precision scalar Floating Point Extensions
380 for Armv8.1-M Mainline with 16 double-word registers.
381 @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
382 Armv8.1-M Mainline, implies @code{+fp}.
383 @code{+mve}: Enables integer only M-profile Vector Extension for
384 Armv8.1-M Mainline, implies @code{+dsp}.
385 @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
386 Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
387 @code{+nofp}: Disables all FPU instructions.
388 @code{+nodsp}: Disables DSP Extension.
389 @code{+nomve}: Disables all M-profile Vector Extensions.
393 @code{+crc}: Enables CRC32 Extension.
394 @code{+simd}: Enables VFP and NEON for Armv8-A.
395 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
397 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
398 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
400 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
401 @code{+nocrypto}: Disables Cryptography Extensions.
403 For @code{armv8.1-a}:
405 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
406 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
408 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
409 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
411 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
412 @code{+nocrypto}: Disables Cryptography Extensions.
414 For @code{armv8.2-a} and @code{armv8.3-a}:
416 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
417 @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
418 @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
419 for Armv8.2-A, implies @code{+fp16}.
420 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
422 @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
424 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
425 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
427 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
428 @code{+nocrypto}: Disables Cryptography Extensions.
430 For @code{armv8.4-a}:
432 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
434 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
435 Variant Extensions for Armv8.2-A, implies @code{+simd}.
436 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
438 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
439 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
441 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
442 @code{+nocryptp}: Disables Cryptography Extensions.
444 For @code{armv8.5-a}:
446 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
448 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
449 Variant Extensions for Armv8.2-A, implies @code{+simd}.
450 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
452 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
453 @code{+nocryptp}: Disables Cryptography Extensions.
456 @cindex @code{-mfpu=} command-line option, ARM
457 @item -mfpu=@var{floating-point-format}
459 This option specifies the floating point format to assemble for. The
460 assembler will issue an error message if an attempt is made to assemble
461 an instruction which will not execute on the target floating point unit.
462 The following format options are recognized:
482 @code{vfpv3-d16-fp16},
499 @code{neon-fp-armv8},
500 @code{crypto-neon-fp-armv8},
501 @code{neon-fp-armv8.1}
503 @code{crypto-neon-fp-armv8.1}.
505 In addition to determining which instructions are assembled, this option
506 also affects the way in which the @code{.double} assembler directive behaves
507 when assembling little-endian code.
509 The default is dependent on the processor selected. For Architecture 5 or
510 later, the default is to assemble for VFP instructions; for earlier
511 architectures the default is to assemble for FPA instructions.
513 @cindex @code{-mfp16-format=} command-line option
514 @item -mfp16-format=@var{format}
515 This option specifies the half-precision floating point format to use
516 when assembling floating point numbers emitted by the @code{.float16}
518 The following format options are recognized:
521 If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
522 point format is used, if @code{alternative} is specified then the Arm
523 alternative half-precision format is used. If this option is set on the
524 command line then the format is fixed and cannot be changed with
525 the @code{float16_format} directive. If this value is not set then
526 the IEEE 754-2008 format is used until the format is explicitly set with
527 the @code{float16_format} directive.
529 @cindex @code{-mthumb} command-line option, ARM
531 This option specifies that the assembler should start assembling Thumb
532 instructions; that is, it should behave as though the file starts with a
533 @code{.code 16} directive.
535 @cindex @code{-mthumb-interwork} command-line option, ARM
536 @item -mthumb-interwork
537 This option specifies that the output generated by the assembler should
538 be marked as supporting interworking. It also affects the behaviour
539 of the @code{ADR} and @code{ADRL} pseudo opcodes.
541 @cindex @code{-mimplicit-it} command-line option, ARM
542 @item -mimplicit-it=never
543 @itemx -mimplicit-it=always
544 @itemx -mimplicit-it=arm
545 @itemx -mimplicit-it=thumb
546 The @code{-mimplicit-it} option controls the behavior of the assembler when
547 conditional instructions are not enclosed in IT blocks.
548 There are four possible behaviors.
549 If @code{never} is specified, such constructs cause a warning in ARM
550 code and an error in Thumb-2 code.
551 If @code{always} is specified, such constructs are accepted in both
552 ARM and Thumb-2 code, where the IT instruction is added implicitly.
553 If @code{arm} is specified, such constructs are accepted in ARM code
554 and cause an error in Thumb-2 code.
555 If @code{thumb} is specified, such constructs cause a warning in ARM
556 code and are accepted in Thumb-2 code. If you omit this option, the
557 behavior is equivalent to @code{-mimplicit-it=arm}.
559 @cindex @code{-mapcs-26} command-line option, ARM
560 @cindex @code{-mapcs-32} command-line option, ARM
563 These options specify that the output generated by the assembler should
564 be marked as supporting the indicated version of the Arm Procedure.
567 @cindex @code{-matpcs} command-line option, ARM
569 This option specifies that the output generated by the assembler should
570 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
571 enabled this option will cause the assembler to create an empty
572 debugging section in the object file called .arm.atpcs. Debuggers can
573 use this to determine the ABI being used by.
575 @cindex @code{-mapcs-float} command-line option, ARM
577 This indicates the floating point variant of the APCS should be
578 used. In this variant floating point arguments are passed in FP
579 registers rather than integer registers.
581 @cindex @code{-mapcs-reentrant} command-line option, ARM
582 @item -mapcs-reentrant
583 This indicates that the reentrant variant of the APCS should be used.
584 This variant supports position independent code.
586 @cindex @code{-mfloat-abi=} command-line option, ARM
587 @item -mfloat-abi=@var{abi}
588 This option specifies that the output generated by the assembler should be
589 marked as using specified floating point ABI.
590 The following values are recognized:
596 @cindex @code{-eabi=} command-line option, ARM
597 @item -meabi=@var{ver}
598 This option specifies which EABI version the produced object files should
600 The following values are recognized:
606 @cindex @code{-EB} command-line option, ARM
608 This option specifies that the output generated by the assembler should
609 be marked as being encoded for a big-endian processor.
611 Note: If a program is being built for a system with big-endian data
612 and little-endian instructions then it should be assembled with the
613 @option{-EB} option, (all of it, code and data) and then linked with
614 the @option{--be8} option. This will reverse the endianness of the
615 instructions back to little-endian, but leave the data as big-endian.
617 @cindex @code{-EL} command-line option, ARM
619 This option specifies that the output generated by the assembler should
620 be marked as being encoded for a little-endian processor.
622 @cindex @code{-k} command-line option, ARM
623 @cindex PIC code generation for ARM
625 This option specifies that the output of the assembler should be marked
626 as position-independent code (PIC).
628 @cindex @code{--fix-v4bx} command-line option, ARM
630 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
631 the linker option of the same name.
633 @cindex @code{-mwarn-deprecated} command-line option, ARM
634 @item -mwarn-deprecated
635 @itemx -mno-warn-deprecated
636 Enable or disable warnings about using deprecated options or
637 features. The default is to warn.
639 @cindex @code{-mccs} command-line option, ARM
641 Turns on CodeComposer Studio assembly syntax compatibility mode.
643 @cindex @code{-mwarn-syms} command-line option, ARM
645 @itemx -mno-warn-syms
646 Enable or disable warnings about symbols that match the names of ARM
647 instructions. The default is to warn.
655 * ARM-Instruction-Set:: Instruction Set
656 * ARM-Chars:: Special Characters
657 * ARM-Regs:: Register Names
658 * ARM-Relocations:: Relocations
659 * ARM-Neon-Alignment:: NEON Alignment Specifiers
662 @node ARM-Instruction-Set
663 @subsection Instruction Set Syntax
664 Two slightly different syntaxes are support for ARM and THUMB
665 instructions. The default, @code{divided}, uses the old style where
666 ARM and THUMB instructions had their own, separate syntaxes. The new,
667 @code{unified} syntax, which can be selected via the @code{.syntax}
668 directive, and has the following main features:
672 Immediate operands do not require a @code{#} prefix.
675 The @code{IT} instruction may appear, and if it does it is validated
676 against subsequent conditional affixes. In ARM mode it does not
677 generate machine code, in THUMB mode it does.
680 For ARM instructions the conditional affixes always appear at the end
681 of the instruction. For THUMB instructions conditional affixes can be
682 used, but only inside the scope of an @code{IT} instruction.
685 All of the instructions new to the V6T2 architecture (and later) are
686 available. (Only a few such instructions can be written in the
687 @code{divided} syntax).
690 The @code{.N} and @code{.W} suffixes are recognized and honored.
693 All instructions set the flags if and only if they have an @code{s}
698 @subsection Special Characters
700 @cindex line comment character, ARM
701 @cindex ARM line comment character
702 The presence of a @samp{@@} anywhere on a line indicates the start of
703 a comment that extends to the end of that line.
705 If a @samp{#} appears as the first character of a line then the whole
706 line is treated as a comment, but in this case the line could also be
707 a logical line number directive (@pxref{Comments}) or a preprocessor
708 control command (@pxref{Preprocessing}).
710 @cindex line separator, ARM
711 @cindex statement separator, ARM
712 @cindex ARM line separator
713 The @samp{;} character can be used instead of a newline to separate
716 @cindex immediate character, ARM
717 @cindex ARM immediate character
718 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
720 @cindex identifiers, ARM
721 @cindex ARM identifiers
722 *TODO* Explain about /data modifier on symbols.
725 @subsection Register Names
727 @cindex ARM register names
728 @cindex register names, ARM
729 *TODO* Explain about ARM register naming, and the predefined names.
731 @node ARM-Relocations
732 @subsection ARM relocation generation
734 @cindex data relocations, ARM
735 @cindex ARM data relocations
736 Specific data relocations can be generated by putting the relocation name
737 in parentheses after the symbol name. For example:
743 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
745 The following relocations are supported:
761 For compatibility with older toolchains the assembler also accepts
762 @code{(PLT)} after branch targets. On legacy targets this will
763 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
764 targets it will encode either the @samp{R_ARM_CALL} or
765 @samp{R_ARM_JUMP24} relocation, as appropriate.
767 @cindex MOVW and MOVT relocations, ARM
768 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
769 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
770 respectively. For example to load the 32-bit address of foo into r0:
773 MOVW r0, #:lower16:foo
774 MOVT r0, #:upper16:foo
777 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
778 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
779 generated by prefixing the value with @samp{#:lower0_7:#},
780 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
781 respectively. For example to load the 32-bit address of foo into r0:
784 MOVS r0, #:upper8_15:#foo
786 ADDS r0, #:upper0_7:#foo
788 ADDS r0, #:lower8_15:#foo
790 ADDS r0, #:lower0_7:#foo
793 @node ARM-Neon-Alignment
794 @subsection NEON Alignment Specifiers
796 @cindex alignment for NEON instructions
797 Some NEON load/store instructions allow an optional address
799 The ARM documentation specifies that this is indicated by
800 @samp{@@ @var{align}}. However GAS already interprets
801 the @samp{@@} character as a "line comment" start,
802 so @samp{: @var{align}} is used instead. For example:
805 vld1.8 @{q0@}, [r0, :128]
808 @node ARM Floating Point
809 @section Floating Point
811 @cindex floating point, ARM (@sc{ieee})
812 @cindex ARM floating point (@sc{ieee})
813 The ARM family uses @sc{ieee} floating-point numbers.
816 @section ARM Machine Directives
818 @cindex machine directives, ARM
819 @cindex ARM machine directives
822 @c AAAAAAAAAAAAAAAAAAAAAAAAA
825 @cindex @code{.2byte} directive, ARM
826 @cindex @code{.4byte} directive, ARM
827 @cindex @code{.8byte} directive, ARM
828 @item .2byte @var{expression} [, @var{expression}]*
829 @itemx .4byte @var{expression} [, @var{expression}]*
830 @itemx .8byte @var{expression} [, @var{expression}]*
831 These directives write 2, 4 or 8 byte values to the output section.
834 @cindex @code{.align} directive, ARM
835 @item .align @var{expression} [, @var{expression}]
836 This is the generic @var{.align} directive. For the ARM however if the
837 first argument is zero (ie no alignment is needed) the assembler will
838 behave as if the argument had been 2 (ie pad to the next four byte
839 boundary). This is for compatibility with ARM's own assembler.
841 @cindex @code{.arch} directive, ARM
842 @item .arch @var{name}
843 Select the target architecture. Valid values for @var{name} are the same as
844 for the @option{-march} command-line option without the instruction set
847 Specifying @code{.arch} clears any previously selected architecture
850 @cindex @code{.arch_extension} directive, ARM
851 @item .arch_extension @var{name}
852 Add or remove an architecture extension to the target architecture. Valid
853 values for @var{name} are the same as those accepted as architectural
854 extensions by the @option{-mcpu} and @option{-march} command-line options.
856 @code{.arch_extension} may be used multiple times to add or remove extensions
857 incrementally to the architecture being compiled for.
859 @cindex @code{.arm} directive, ARM
861 This performs the same action as @var{.code 32}.
863 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
865 @cindex @code{.bss} directive, ARM
867 This directive switches to the @code{.bss} section.
869 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
871 @cindex @code{.cantunwind} directive, ARM
873 Prevents unwinding through the current function. No personality routine
874 or exception table data is required or permitted.
876 @cindex @code{.code} directive, ARM
877 @item .code @code{[16|32]}
878 This directive selects the instruction set being generated. The value 16
879 selects Thumb, with the value 32 selecting ARM.
881 @cindex @code{.cpu} directive, ARM
882 @item .cpu @var{name}
883 Select the target processor. Valid values for @var{name} are the same as
884 for the @option{-mcpu} command-line option without the instruction set
887 Specifying @code{.cpu} clears any previously selected architecture
890 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
892 @cindex @code{.dn} and @code{.qn} directives, ARM
893 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
894 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
896 The @code{dn} and @code{qn} directives are used to create typed
897 and/or indexed register aliases for use in Advanced SIMD Extension
898 (Neon) instructions. The former should be used to create aliases
899 of double-precision registers, and the latter to create aliases of
900 quad-precision registers.
902 If these directives are used to create typed aliases, those aliases can
903 be used in Neon instructions instead of writing types after the mnemonic
904 or after each operand. For example:
913 This is equivalent to writing the following:
919 Aliases created using @code{dn} or @code{qn} can be destroyed using
922 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
924 @cindex @code{.eabi_attribute} directive, ARM
925 @item .eabi_attribute @var{tag}, @var{value}
926 Set the EABI object attribute @var{tag} to @var{value}.
928 The @var{tag} is either an attribute number, or one of the following:
929 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
930 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
931 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
932 @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
933 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
934 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
935 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
936 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
937 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
938 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
939 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
940 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
941 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
942 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
943 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
944 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
945 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
946 @code{Tag_conformance}, @code{Tag_T2EE_use},
947 @code{Tag_Virtualization_use}
949 The @var{value} is either a @code{number}, @code{"string"}, or
950 @code{number, "string"} depending on the tag.
952 Note - the following legacy values are also accepted by @var{tag}:
953 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
954 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
956 @cindex @code{.even} directive, ARM
958 This directive aligns to an even-numbered address.
960 @cindex @code{.extend} directive, ARM
961 @cindex @code{.ldouble} directive, ARM
962 @item .extend @var{expression} [, @var{expression}]*
963 @itemx .ldouble @var{expression} [, @var{expression}]*
964 These directives write 12byte long double floating-point values to the
965 output section. These are not compatible with current ARM processors
968 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
970 @cindex @code{.float16} directive, ARM
971 @item .float16 @var{value [,...,value_n]}
972 Place the half precision floating point representation of one or more
973 floating-point values into the current section. The exact format of the
974 encoding is specified by @code{.float16_format}. If the format has not
975 been explicitly set yet (either via the @code{.float16_format} directive or
976 the command line option) then the IEEE 754-2008 format is used.
978 @cindex @code{.float16_format} directive, ARM
979 @item .float16_format @var{format}
980 Set the format to use when encoding float16 values emitted by
981 the @code{.float16} directive.
982 Once the format has been set it cannot be changed.
983 @code{format} should be one of the following: @code{ieee} (encode in
984 the IEEE 754-2008 half precision format) or @code{alternative} (encode in
985 the Arm alternative half precision format).
988 @cindex @code{.fnend} directive, ARM
990 Marks the end of a function with an unwind table entry. The unwind index
991 table entry is created when this directive is processed.
993 If no personality routine has been specified then standard personality
994 routine 0 or 1 will be used, depending on the number of unwind opcodes
998 @cindex @code{.fnstart} directive, ARM
1000 Marks the start of a function with an unwind table entry.
1002 @cindex @code{.force_thumb} directive, ARM
1004 This directive forces the selection of Thumb instructions, even if the
1005 target processor does not support those instructions
1007 @cindex @code{.fpu} directive, ARM
1008 @item .fpu @var{name}
1009 Select the floating-point unit to assemble for. Valid values for @var{name}
1010 are the same as for the @option{-mfpu} command-line option.
1012 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
1013 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
1015 @cindex @code{.handlerdata} directive, ARM
1017 Marks the end of the current function, and the start of the exception table
1018 entry for that function. Anything between this directive and the
1019 @code{.fnend} directive will be added to the exception table entry.
1021 Must be preceded by a @code{.personality} or @code{.personalityindex}
1024 @c IIIIIIIIIIIIIIIIIIIIIIIIII
1026 @cindex @code{.inst} directive, ARM
1027 @item .inst @var{opcode} [ , @dots{} ]
1028 @itemx .inst.n @var{opcode} [ , @dots{} ]
1029 @itemx .inst.w @var{opcode} [ , @dots{} ]
1030 Generates the instruction corresponding to the numerical value @var{opcode}.
1031 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
1032 specified explicitly, overriding the normal encoding rules.
1034 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
1035 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
1036 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
1038 @item .ldouble @var{expression} [, @var{expression}]*
1041 @cindex @code{.ltorg} directive, ARM
1043 This directive causes the current contents of the literal pool to be
1044 dumped into the current section (which is assumed to be the .text
1045 section) at the current location (aligned to a word boundary).
1046 @code{GAS} maintains a separate literal pool for each section and each
1047 sub-section. The @code{.ltorg} directive will only affect the literal
1048 pool of the current section and sub-section. At the end of assembly
1049 all remaining, un-empty literal pools will automatically be dumped.
1051 Note - older versions of @code{GAS} would dump the current literal
1052 pool any time a section change occurred. This is no longer done, since
1053 it prevents accurate control of the placement of literal pools.
1055 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
1057 @cindex @code{.movsp} directive, ARM
1058 @item .movsp @var{reg} [, #@var{offset}]
1059 Tell the unwinder that @var{reg} contains an offset from the current
1060 stack pointer. If @var{offset} is not specified then it is assumed to be
1063 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
1064 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
1066 @cindex @code{.object_arch} directive, ARM
1067 @item .object_arch @var{name}
1068 Override the architecture recorded in the EABI object attribute section.
1069 Valid values for @var{name} are the same as for the @code{.arch} directive.
1070 Typically this is useful when code uses runtime detection of CPU features.
1072 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
1074 @cindex @code{.packed} directive, ARM
1075 @item .packed @var{expression} [, @var{expression}]*
1076 This directive writes 12-byte packed floating-point values to the
1077 output section. These are not compatible with current ARM processors
1081 @cindex @code{.pad} directive, ARM
1082 @item .pad #@var{count}
1083 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
1084 A positive value indicates the function prologue allocated stack space by
1085 decrementing the stack pointer.
1087 @cindex @code{.personality} directive, ARM
1088 @item .personality @var{name}
1089 Sets the personality routine for the current function to @var{name}.
1091 @cindex @code{.personalityindex} directive, ARM
1092 @item .personalityindex @var{index}
1093 Sets the personality routine for the current function to the EABI standard
1094 routine number @var{index}
1096 @cindex @code{.pool} directive, ARM
1098 This is a synonym for .ltorg.
1100 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
1101 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
1103 @cindex @code{.req} directive, ARM
1104 @item @var{name} .req @var{register name}
1105 This creates an alias for @var{register name} called @var{name}. For
1112 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
1115 @cindex @code{.save} directive, ARM
1116 @item .save @var{reglist}
1117 Generate unwinder annotations to restore the registers in @var{reglist}.
1118 The format of @var{reglist} is the same as the corresponding store-multiple
1122 @exdent @emph{core registers}
1123 .save @{r4, r5, r6, lr@}
1124 stmfd sp!, @{r4, r5, r6, lr@}
1125 @exdent @emph{FPA registers}
1128 @exdent @emph{VFP registers}
1129 .save @{d8, d9, d10@}
1130 fstmdx sp!, @{d8, d9, d10@}
1131 @exdent @emph{iWMMXt registers}
1132 .save @{wr10, wr11@}
1133 wstrd wr11, [sp, #-8]!
1134 wstrd wr10, [sp, #-8]!
1137 wstrd wr11, [sp, #-8]!
1139 wstrd wr10, [sp, #-8]!
1143 @cindex @code{.setfp} directive, ARM
1144 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
1145 Make all unwinder annotations relative to a frame pointer. Without this
1146 the unwinder will use offsets from the stack pointer.
1148 The syntax of this directive is the same as the @code{add} or @code{mov}
1149 instruction used to set the frame pointer. @var{spreg} must be either
1150 @code{sp} or mentioned in a previous @code{.movsp} directive.
1160 @cindex @code{.secrel32} directive, ARM
1161 @item .secrel32 @var{expression} [, @var{expression}]*
1162 This directive emits relocations that evaluate to the section-relative
1163 offset of each expression's symbol. This directive is only supported
1166 @cindex @code{.syntax} directive, ARM
1167 @item .syntax [@code{unified} | @code{divided}]
1168 This directive sets the Instruction Set Syntax as described in the
1169 @ref{ARM-Instruction-Set} section.
1171 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
1173 @cindex @code{.thumb} directive, ARM
1175 This performs the same action as @var{.code 16}.
1177 @cindex @code{.thumb_func} directive, ARM
1179 This directive specifies that the following symbol is the name of a
1180 Thumb encoded function. This information is necessary in order to allow
1181 the assembler and linker to generate correct code for interworking
1182 between Arm and Thumb instructions and should be used even if
1183 interworking is not going to be performed. The presence of this
1184 directive also implies @code{.thumb}
1186 This directive is not necessary when generating EABI objects. On these
1187 targets the encoding is implicit when generating Thumb code.
1189 @cindex @code{.thumb_set} directive, ARM
1191 This performs the equivalent of a @code{.set} directive in that it
1192 creates a symbol which is an alias for another symbol (possibly not yet
1193 defined). This directive also has the added property in that it marks
1194 the aliased symbol as being a thumb function entry point, in the same
1195 way that the @code{.thumb_func} directive does.
1197 @cindex @code{.tlsdescseq} directive, ARM
1198 @item .tlsdescseq @var{tls-variable}
1199 This directive is used to annotate parts of an inlined TLS descriptor
1200 trampoline. Normally the trampoline is provided by the linker, and
1201 this directive is not needed.
1203 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
1205 @cindex @code{.unreq} directive, ARM
1206 @item .unreq @var{alias-name}
1207 This undefines a register alias which was previously defined using the
1208 @code{req}, @code{dn} or @code{qn} directives. For example:
1215 An error occurs if the name is undefined. Note - this pseudo op can
1216 be used to delete builtin in register name aliases (eg 'r0'). This
1217 should only be done if it is really necessary.
1219 @cindex @code{.unwind_raw} directive, ARM
1220 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
1221 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
1222 the stack pointer by @var{offset} bytes.
1224 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1227 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1229 @cindex @code{.vsave} directive, ARM
1230 @item .vsave @var{vfp-reglist}
1231 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1232 using FLDMD. Also works for VFPv3 registers
1233 that are to be restored using VLDM.
1234 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1238 @exdent @emph{VFP registers}
1239 .vsave @{d8, d9, d10@}
1240 fstmdd sp!, @{d8, d9, d10@}
1241 @exdent @emph{VFPv3 registers}
1242 .vsave @{d15, d16, d17@}
1243 vstm sp!, @{d15, d16, d17@}
1246 Since FLDMX and FSTMX are now deprecated, this directive should be
1247 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1249 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1250 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1251 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1252 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1260 @cindex opcodes for ARM
1261 @code{@value{AS}} implements all the standard ARM opcodes. It also
1262 implements several pseudo opcodes, including several synthetic load
1267 @cindex @code{NOP} pseudo op, ARM
1273 This pseudo op will always evaluate to a legal ARM instruction that does
1274 nothing. Currently it will evaluate to MOV r0, r0.
1276 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1279 ldr <register> , = <expression>
1282 If expression evaluates to a numeric constant then a MOV or MVN
1283 instruction will be used in place of the LDR instruction, if the
1284 constant can be generated by either of these instructions. Otherwise
1285 the constant will be placed into the nearest literal pool (if it not
1286 already there) and a PC relative LDR instruction will be generated.
1288 @cindex @code{ADR reg,<label>} pseudo op, ARM
1291 adr <register> <label>
1294 This instruction will load the address of @var{label} into the indicated
1295 register. The instruction will evaluate to a PC relative ADD or SUB
1296 instruction depending upon where the label is located. If the label is
1297 out of range, or if it is not defined in the same file (and section) as
1298 the ADR instruction, then an error will be generated. This instruction
1299 will not make use of the literal pool.
1301 If @var{label} is a thumb function symbol, and thumb interworking has
1302 been enabled via the @option{-mthumb-interwork} option then the bottom
1303 bit of the value stored into @var{register} will be set. This allows
1304 the following sequence to work as expected:
1307 adr r0, thumb_function
1311 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1314 adrl <register> <label>
1317 This instruction will load the address of @var{label} into the indicated
1318 register. The instruction will evaluate to one or two PC relative ADD
1319 or SUB instructions depending upon where the label is located. If a
1320 second instruction is not needed a NOP instruction will be generated in
1321 its place, so that this instruction is always 8 bytes long.
1323 If the label is out of range, or if it is not defined in the same file
1324 (and section) as the ADRL instruction, then an error will be generated.
1325 This instruction will not make use of the literal pool.
1327 If @var{label} is a thumb function symbol, and thumb interworking has
1328 been enabled via the @option{-mthumb-interwork} option then the bottom
1329 bit of the value stored into @var{register} will be set.
1333 For information on the ARM or Thumb instruction sets, see @cite{ARM
1334 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1337 @node ARM Mapping Symbols
1338 @section Mapping Symbols
1340 The ARM ELF specification requires that special symbols be inserted
1341 into object files to mark certain features:
1347 At the start of a region of code containing ARM instructions.
1351 At the start of a region of code containing THUMB instructions.
1355 At the start of a region of data.
1359 The assembler will automatically insert these symbols for you - there
1360 is no need to code them yourself. Support for tagging symbols ($b,
1361 $f, $p and $m) which is also mentioned in the current ARM ELF
1362 specification is not implemented. This is because they have been
1363 dropped from the new EABI and so tools cannot rely upon their
1366 @node ARM Unwinding Tutorial
1369 The ABI for the ARM Architecture specifies a standard format for
1370 exception unwind information. This information is used when an
1371 exception is thrown to determine where control should be transferred.
1372 In particular, the unwind information is used to determine which
1373 function called the function that threw the exception, and which
1374 function called that one, and so forth. This information is also used
1375 to restore the values of callee-saved registers in the function
1376 catching the exception.
1378 If you are writing functions in assembly code, and those functions
1379 call other functions that throw exceptions, you must use assembly
1380 pseudo ops to ensure that appropriate exception unwind information is
1381 generated. Otherwise, if one of the functions called by your assembly
1382 code throws an exception, the run-time library will be unable to
1383 unwind the stack through your assembly code and your program will not
1386 To illustrate the use of these pseudo ops, we will examine the code
1387 that G++ generates for the following C++ input:
1390 void callee (int *);
1401 This example does not show how to throw or catch an exception from
1402 assembly code. That is a much more complex operation and should
1403 always be done in a high-level language, such as C++, that directly
1404 supports exceptions.
1406 The code generated by one particular version of G++ when compiling the
1413 @ Function supports interworking.
1414 @ args = 0, pretend = 0, frame = 8
1415 @ frame_needed = 1, uses_anonymous_args = 0
1437 Of course, the sequence of instructions varies based on the options
1438 you pass to GCC and on the version of GCC in use. The exact
1439 instructions are not important since we are focusing on the pseudo ops
1440 that are used to generate unwind information.
1442 An important assumption made by the unwinder is that the stack frame
1443 does not change during the body of the function. In particular, since
1444 we assume that the assembly code does not itself throw an exception,
1445 the only point where an exception can be thrown is from a call, such
1446 as the @code{bl} instruction above. At each call site, the same saved
1447 registers (including @code{lr}, which indicates the return address)
1448 must be located in the same locations relative to the frame pointer.
1450 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1451 op appears immediately before the first instruction of the function
1452 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1453 op appears immediately after the last instruction of the function.
1454 These pseudo ops specify the range of the function.
1456 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1457 @code{.pad}) matters; their exact locations are irrelevant. In the
1458 example above, the compiler emits the pseudo ops with particular
1459 instructions. That makes it easier to understand the code, but it is
1460 not required for correctness. It would work just as well to emit all
1461 of the pseudo ops other than @code{.fnend} in the same order, but
1462 immediately after @code{.fnstart}.
1464 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1465 indicates registers that have been saved to the stack so that they can
1466 be restored before the function returns. The argument to the
1467 @code{.save} pseudo op is a list of registers to save. If a register
1468 is ``callee-saved'' (as specified by the ABI) and is modified by the
1469 function you are writing, then your code must save the value before it
1470 is modified and restore the original value before the function
1471 returns. If an exception is thrown, the run-time library restores the
1472 values of these registers from their locations on the stack before
1473 returning control to the exception handler. (Of course, if an
1474 exception is not thrown, the function that contains the @code{.save}
1475 pseudo op restores these registers in the function epilogue, as is
1476 done with the @code{ldmfd} instruction above.)
1478 You do not have to save callee-saved registers at the very beginning
1479 of the function and you do not need to use the @code{.save} pseudo op
1480 immediately following the point at which the registers are saved.
1481 However, if you modify a callee-saved register, you must save it on
1482 the stack before modifying it and before calling any functions which
1483 might throw an exception. And, you must use the @code{.save} pseudo
1484 op to indicate that you have done so.
1486 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1487 modification of the stack pointer that does not save any registers.
1488 The argument is the number of bytes (in decimal) that are subtracted
1489 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1490 subtracting from the stack pointer increases the size of the stack.)
1492 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1493 indicates the register that contains the frame pointer. The first
1494 argument is the register that is set, which is typically @code{fp}.
1495 The second argument indicates the register from which the frame
1496 pointer takes its value. The third argument, if present, is the value
1497 (in decimal) added to the register specified by the second argument to
1498 compute the value of the frame pointer. You should not modify the
1499 frame pointer in the body of the function.
1501 If you do not use a frame pointer, then you should not use the
1502 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1503 should avoid modifying the stack pointer outside of the function
1504 prologue. Otherwise, the run-time library will be unable to find
1505 saved registers when it is unwinding the stack.
1507 The pseudo ops described above are sufficient for writing assembly
1508 code that calls functions which may throw exceptions. If you need to
1509 know more about the object-file format used to represent unwind
1510 information, you may consult the @cite{Exception Handling ABI for the
1511 ARM Architecture} available from @uref{http://infocenter.arm.com}.
projects / deliverable / binutils-gdb.git / blob