gas/doc/c-arm.texi

   1 @c Copyright (C) 1996, 1998, 1999, 2000 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4
   5 @ifset GENERIC
   6 @page
   7 @node ARM-Dependent
   8 @chapter ARM Dependent Features
   9 @end ifset
  10
  11 @ifclear GENERIC
  12 @node Machine Dependencies
  13 @chapter ARM Dependent Features
  14 @end ifclear
  15
  16 @cindex ARM support
  17 @cindex Thumb support
  18 @menu
  19 * ARM Options::              Options
  20 * ARM Syntax::               Syntax
  21 * ARM Floating Point::       Floating Point
  22 * ARM Directives::           ARM Machine Directives
  23 * ARM Opcodes::              Opcodes
  24 @end menu
  25
  26 @node ARM Options
  27 @section Options
  28 @cindex ARM options (none)
  29 @cindex options for ARM (none)
  30
  31 @table @code
  32
  33 @cindex @code{-marm} command line option, ARM
  34 @item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]}
  35 @itemx -mxscale
  36 This option specifies the target processor.  The assembler will issue an
  37 error message if an attempt is made to assemble an instruction which
  38 will not execute on the target processor.
  39
  40 @cindex @code{-marmv} command line option, ARM
  41 @item -marmv@code{[2|2a|3|3m|4|4t|5|5t|5te]}
  42 This option specifies the target architecture.  The assembler will issue
  43 an error message if an attempt is made to assemble an instruction which
  44 will not execute on the target architecture.
  45 The option @code{-marmv5te} specifies that v5t architecture should be
  46 used with the El Segundo extensions enabled.
  47
  48 @cindex @code{-mthumb} command line option, ARM
  49 @item -mthumb
  50 This option specifies that only Thumb instructions should be assembled.
  51
  52 @cindex @code{-mall} command line option, ARM
  53 @item -mall
  54 This option specifies that any Arm or Thumb instruction should be assembled.
  55
  56 @cindex @code{-mfpa} command line option, ARM
  57 @item -mfpa @code{[10|11]}
  58 This option specifies the floating point architecture in use on the
  59 target processor.
  60
  61 @cindex @code{-mfpe-old} command line option, ARM
  62 @item -mfpe-old
  63 Do not allow the assemble of floating point multiple instructions.
  64
  65 @cindex @code{-mno-fpu} command line option, ARM
  66 @item -mno-fpu
  67 Do not allow the assembly of any floating point instructions.
  68
  69 @cindex @code{-mthumb-interwork} command line option, ARM
  70 @item -mthumb-interwork
  71 This option specifies that the output generated by the assembler should
  72 be marked as supporting interworking.
  73
  74 @cindex @code{-mapcs} command line option, ARM
  75 @item -mapcs @code{[26|32]}
  76 This option specifies that the output generated by the assembler should
  77 be marked as supporting the indicated version of the Arm Procedure.
  78 Calling Standard.
  79
  80 @cindex @code{-matpcs} command line option, ARM
  81 @item -matpcs
  82 This option specifies that the output generated by the assembler should
  83 be marked as supporting the Arm/Thumb Procedure Calling Standard.  If
  84 enabled this option will cause the assembler to create an empty
  85 debugging section in the object file called .arm.atpcs.  Debuggers can
  86 use this to determine the ABI being used by.
  87
  88 @cindex @code{-mapcs-float} command line option, ARM
  89 @item -mapcs-float
  90 This indicates the the floating point variant of the APCS should be
  91 used.  In this variant floating point arguments are passed in FP
  92 registers rather than integer registers.
  93
  94 @cindex @code{-mapcs-reentrant} command line option, ARM
  95 @item -mapcs-reentrant
  96 This indicates that the reentrant variant of the APCS should be used.
  97 This variant supports position independent code.
  98
  99 @cindex @code{-EB} command line option, ARM
 100 @item -EB
 101 This option specifies that the output generated by the assembler should
 102 be marked as being encoded for a big-endian processor.
 103
 104 @cindex @code{-EL} command line option, ARM
 105 @item -EL
 106 This option specifies that the output generated by the assembler should
 107 be marked as being encoded for a little-endian processor.
 108
 109 @cindex @code{-k} command line option, ARM
 110 @cindex PIC code generation for ARM
 111 @item -k
 112 This option enables the generation of PIC (position independent code).
 113
 114 @cindex @code{-moabi} command line option, ARM
 115 @item -moabi
 116 This indicates that the code should be assembled using the old ARM ELF
 117 conventions, based on a beta release release of the ARM-ELF
 118 specifications, rather than the default conventions which are based on
 119 the final release of the ARM-ELF specifications.
 120
 121 @end table
 122
 123
 124 @node ARM Syntax
 125 @section Syntax
 126 @menu
 127 * ARM-Chars::                Special Characters
 128 * ARM-Regs::                 Register Names
 129 @end menu
 130
 131 @node ARM-Chars
 132 @subsection Special Characters
 133
 134 @cindex line comment character, ARM
 135 @cindex ARM line comment character
 136 The presence of a @samp{@@} on a line indicates the start of a comment
 137 that extends to the end of the current line.  If a @samp{#} appears as
 138 the first character of a line, the whole line is treated as a comment.
 139
 140 @cindex line separator, ARM
 141 @cindex statement separator, ARM
 142 @cindex ARM line separator
 143 On ARM systems running the GNU/Linux operating system, @samp{;} can be
 144 used instead of a newline to separate statements.
 145
 146 @cindex immediate character, ARM
 147 @cindex ARM immediate character
 148 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 149
 150 @cindex identifiers, ARM
 151 @cindex ARM identifiers
 152 *TODO* Explain about /data modifier on symbols.
 153
 154 @node ARM-Regs
 155 @subsection Register Names
 156
 157 @cindex ARM register names
 158 @cindex register names, ARM
 159 *TODO* Explain about ARM register naming, and the predefined names.
 160
 161 @node ARM Floating Point
 162 @section Floating Point
 163
 164 @cindex floating point, ARM (@sc{ieee})
 165 @cindex ARM floating point (@sc{ieee})
 166 The ARM family uses @sc{ieee} floating-point numbers.
 167
 168
 169
 170 @node ARM Directives
 171 @section ARM Machine Directives
 172
 173 @cindex machine directives, ARM
 174 @cindex ARM machine directives
 175 @table @code
 176
 177 @cindex @code{align} directive, ARM
 178 @item .align @var{expression} [, @var{expression}]
 179 This is the generic @var{.align} directive.  For the ARM however if the
 180 first argument is zero (ie no alignment is needed) the assembler will
 181 behave as if the argument had been 2 (ie pad to the next four byte
 182 boundary).  This is for compatability with ARM's own assembler.
 183
 184 @cindex @code{req} directive, ARM
 185 @item @var{name} .req @var{register name}
 186 This creates an alias for @var{register name} called @var{name}.  For
 187 example:
 188
 189 @smallexample
 190         foo .req r0
 191 @end smallexample
 192
 193 @cindex @code{code} directive, ARM
 194 @item .code @code{[16|32]}
 195 This directive selects the instruction set being generated. The value 16
 196 selects Thumb, with the value 32 selecting ARM.
 197
 198 @cindex @code{thumb} directive, ARM
 199 @item .thumb
 200 This performs the same action as @var{.code 16}.
 201
 202 @cindex @code{arm} directive, ARM
 203 @item .arm
 204 This performs the same action as @var{.code 32}.
 205
 206 @cindex @code{force_thumb} directive, ARM
 207 @item .force_thumb
 208 This directive forces the selection of Thumb instructions, even if the
 209 target processor does not support those instructions
 210
 211 @cindex @code{thumb_func} directive, ARM
 212 @item .thumb_func
 213 This directive specifies that the following symbol is the name of a
 214 Thumb encoded function.  This information is necessary in order to allow
 215 the assembler and linker to generate correct code for interworking
 216 between Arm and Thumb instructions and should be used even if
 217 interworking is not going to be performed.  The presence of this
 218 directive also implies @code{.thumb}
 219
 220 @cindex @code{thumb_set} directive, ARM
 221 @item .thumb_set
 222 This performs the equivalent of a @code{.set} directive in that it
 223 creates a symbol which is an alias for another symbol (possibly not yet
 224 defined).  This directive also has the added property in that it marks
 225 the aliased symbol as being a thumb function entry point, in the same
 226 way that the @code{.thumb_func} directive does.
 227
 228 @cindex @code{.ltorg} directive, ARM
 229 @item .ltorg
 230 This directive causes the current contents of the literal pool to be
 231 dumped into the current section (which is assumed to be the .text
 232 section) at the current location (aligned to a word boundary).
 233
 234 @cindex @code{.pool} directive, ARM
 235 @item .pool
 236 This is a synonym for .ltorg.
 237
 238 @end table
 239
 240 @node ARM Opcodes
 241 @section Opcodes
 242
 243 @cindex ARM opcodes
 244 @cindex opcodes for ARM
 245 @code{@value{AS}} implements all the standard ARM opcodes.  It also
 246 implements several pseudo opcodes, including several synthetic load
 247 instructions.
 248
 249 @table @code
 250
 251 @cindex @code{NOP} pseudo op, ARM
 252 @item NOP
 253 @smallexample
 254   nop
 255 @end smallexample
 256
 257 This pseudo op will always evaluate to a legal ARM instruction that does
 258 nothing.  Currently it will evaluate to MOV r0, r0.
 259
 260 @cindex @code{LDR reg,=<label>} pseudo op, ARM
 261 @item LDR
 262 @smallexample
 263   ldr <register> , = <expression>
 264 @end smallexample
 265
 266 If expression evaluates to a numeric constant then a MOV or MVN
 267 instruction will be used in place of the LDR instruction, if the
 268 constant can be generated by either of these instructions.  Otherwise
 269 the constant will be placed into the nearest literal pool (if it not
 270 already there) and a PC relative LDR instruction will be generated.
 271
 272 @cindex @code{ADR reg,<label>} pseudo op, ARM
 273 @item ADR
 274 @smallexample
 275   adr <register> <label>
 276 @end smallexample
 277
 278 This instruction will load the address of @var{label} into the indicated
 279 register.  The instruction will evaluate to a PC relative ADD or SUB
 280 instruction depending upon where the label is located.  If the label is
 281 out of range, or if it is not defined in the same file (and section) as
 282 the ADR instruction, then an error will be generated.  This instruction
 283 will not make use of the literal pool.
 284
 285 @cindex @code{ADRL reg,<label>} pseudo op, ARM
 286 @item ADRL
 287 @smallexample
 288   adrl <register> <label>
 289 @end smallexample
 290
 291 This instruction will load the address of @var{label} into the indicated
 292 register.  The instruction will evaluate to one or two a PC relative ADD
 293 or SUB instructions depending upon where the label is located.  If a
 294 second instruction is not needed a NOP instruction will be generated in
 295 its place, so that this instruction is always 8 bytes long.
 296
 297 If the label is out of range, or if it is not defined in the same file
 298 (and section) as the ADRL instruction, then an error will be generated.
 299 This instruction will not make use of the literal pool.
 300
 301 @end table
 302
 303 For information on the ARM or Thumb instruction sets, see @cite{ARM
 304 Software Development Toolkit Reference Manual}, Advanced RISC Machines
 305 Ltd.
 306