gas/doc/c-arm.texi

   1 @c Copyright (C) 1996, 1998, 1999, 2000 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4
   5 @ifset GENERIC
   6 @page
   7 @node ARM-Dependent
   8 @chapter ARM Dependent Features
   9 @end ifset
  10
  11 @ifclear GENERIC
  12 @node Machine Dependencies
  13 @chapter ARM Dependent Features
  14 @end ifclear
  15
  16 @cindex ARM support
  17 @cindex Thumb support
  18 @menu
  19 * ARM Options::              Options
  20 * ARM Syntax::               Syntax
  21 * ARM Floating Point::       Floating Point
  22 * ARM Directives::           ARM Machine Directives
  23 * ARM Opcodes::              Opcodes
  24 @end menu
  25
  26 @node ARM Options
  27 @section Options
  28 @cindex ARM options (none)
  29 @cindex options for ARM (none)
  30
  31 @table @code
  32
  33 @cindex @code{-marm} command line option, ARM
  34 @item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]}
  35 This option specifies the target processor.  The assembler will issue an
  36 error message if an attempt is made to assemble an instruction which
  37 will not execute on the target processor.
  38
  39 @cindex @code{-marmv} command line option, ARM
  40 @item -marmv@code{[2|2a|3|3m|4|4t|5|5t]}
  41 This option specifies the target architecture.  The assembler will issue
  42 an error message if an attempt is made to assemble an instruction which
  43 will not execute on the target architecture.
  44
  45 @cindex @code{-mthumb} command line option, ARM
  46 @item -mthumb
  47 This option specifies that only Thumb instructions should be assembled.
  48
  49 @cindex @code{-mall} command line option, ARM
  50 @item -mall
  51 This option specifies that any Arm or Thumb instruction should be assembled.
  52
  53 @cindex @code{-mfpa} command line option, ARM
  54 @item -mfpa @var{[10|11]}
  55 This option specifies the floating point architecture in use on the
  56 target processor.
  57
  58 @cindex @code{-mfpe-old} command line option, ARM
  59 @item -mfpe-old
  60 Do not allow the assemble of floating point multiple instructions.
  61
  62 @cindex @code{-mno-fpu} command line option, ARM
  63 @item -mno-fpu
  64 Do not allow the assembly of any floating point instructions.
  65
  66 @cindex @code{-mthumb-interwork} command line option, ARM
  67 @item -mthumb-interwork
  68 This option specifies that the output generated by the assembler should
  69 be marked as supporting interworking.
  70
  71 @cindex @code{-mapcs} command line option, ARM
  72 @item -mapcs @var{[26|32]}
  73 This option specifies that the output generated by the assembler should
  74 be marked as supporting the indicated version of the Arm Procedure.
  75 Calling Standard.
  76
  77 @cindex @code{-mapcs-float} command line option, ARM
  78 @item -mapcs-float
  79 This indicates the the floating point variant of the APCS should be
  80 used.  In this variant floating point arguments are passed in FP
  81 registers rather than integer registers.
  82
  83 @cindex @code{-mapcs-reentrant} command line option, ARM
  84 @item -mapcs-reentrant
  85 This indicates that the reentrant variant of the APCS should be used.
  86 This variant supports position independent code.
  87
  88 @cindex @code{-EB} command line option, ARM
  89 @item -EB
  90 This option specifies that the output generated by the assembler should
  91 be marked as being encoded for a big-endian processor.
  92
  93 @cindex @code{-EL} command line option, ARM
  94 @item -EL
  95 This option specifies that the output generated by the assembler should
  96 be marked as being encoded for a little-endian processor.
  97
  98 @cindex @code{-k} command line option, ARM
  99 @cindex PIC code generation for ARM
 100 @item -k
 101 This option enables the generation of PIC (position independent code).
 102
 103 @cindex @code{-moabi} command line option, ARM
 104 @item -moabi
 105 This indicates that the code should be assembled using the old ARM ELF
 106 conventions, based on a beta release release of the ARM-ELF
 107 specifications, rather than the default conventions which are based on
 108 the final release of the ARM-ELF specifications.
 109
 110 @end table
 111
 112
 113 @node ARM Syntax
 114 @section Syntax
 115 @menu
 116 * ARM-Chars::                Special Characters
 117 * ARM-Regs::                 Register Names
 118 @end menu
 119
 120 @node ARM-Chars
 121 @subsection Special Characters
 122
 123 @cindex line comment character, ARM
 124 @cindex ARM line comment character
 125 The presence of a @samp{@@} on a line indicates the start of a comment
 126 that extends to the end of the current line.  If a @samp{#} appears as
 127 the first character of a line, the whole line is treated as a comment.
 128
 129 @cindex line separator, ARM
 130 @cindex statement separator, ARM
 131 @cindex ARM line separator
 132 On ARM systems running the GNU/Linux operating system, @samp{;} can be
 133 used instead of a newline to separate statements.
 134
 135 @cindex immediate character, ARM
 136 @cindex ARM immediate character
 137 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 138
 139 @cindex identifiers, ARM
 140 @cindex ARM identifiers
 141 *TODO* Explain about /data modifier on symbols.
 142
 143 @node ARM-Regs
 144 @subsection Register Names
 145
 146 @cindex ARM register names
 147 @cindex register names, ARM
 148 *TODO* Explain about ARM register naming, and the predefined names.
 149
 150 @node ARM Floating Point
 151 @section Floating Point
 152
 153 @cindex floating point, ARM (@sc{ieee})
 154 @cindex ARM floating point (@sc{ieee})
 155 The ARM family uses @sc{ieee} floating-point numbers.
 156
 157
 158
 159 @node ARM Directives
 160 @section ARM Machine Directives
 161
 162 @cindex machine directives, ARM
 163 @cindex ARM machine directives
 164 @table @code
 165
 166 @cindex @code{align} directive, ARM
 167 @item .align @var{expression} [, @var{expression}]
 168 This is the generic @var{.align} directive.  For the ARM however if the
 169 first argument is zero (ie no alignment is needed) the assembler will
 170 behave as if the argument had been 2 (ie pad to the next four byte
 171 boundary).  This is for compatability with ARM's own assembler.
 172
 173 @cindex @code{req} directive, ARM
 174 @item @var{name} .req @var{register name}
 175 This creates an alias for @var{register name} called @var{name}.  For
 176 example:
 177
 178 @smallexample
 179         foo .req r0
 180 @end smallexample
 181
 182 @cindex @code{code} directive, ARM
 183 @item .code @var{[16|32]}
 184 This directive selects the instruction set being generated. The value 16
 185 selects Thumb, with the value 32 selecting ARM.
 186
 187 @cindex @code{thumb} directive, ARM
 188 @item .thumb
 189 This performs the same action as @var{.code 16}.
 190
 191 @cindex @code{arm} directive, ARM
 192 @item .arm
 193 This performs the same action as @var{.code 32}.
 194
 195 @cindex @code{force_thumb} directive, ARM
 196 @item .force_thumb
 197 This directive forces the selection of Thumb instructions, even if the
 198 target processor does not support those instructions
 199
 200 @cindex @code{thumb_func} directive, ARM
 201 @item .thumb_func
 202 This directive specifies that the following symbol is the name of a
 203 Thumb encoded function.  This information is necessary in order to allow
 204 the assembler and linker to generate correct code for interworking
 205 between Arm and Thumb instructions and should be used even if
 206 interworking is not going to be performed.  The presence of this
 207 directive also implies @code{.thumb}
 208
 209 @cindex @code{thumb_set} directive, ARM
 210 @item .thumb_set
 211 This performs the equivalent of a @code{.set} directive in that it
 212 creates a symbol which is an alias for another symbol (possibly not yet
 213 defined).  This directive also has the added property in that it marks
 214 the aliased symbol as being a thumb function entry point, in the same
 215 way that the @code{.thumb_func} directive does.
 216
 217 @cindex @code{.ltorg} directive, ARM
 218 @item .ltorg
 219 This directive causes the current contents of the literal pool to be
 220 dumped into the current section (which is assumed to be the .text
 221 section) at the current location (aligned to a word boundary).
 222
 223 @cindex @code{.pool} directive, ARM
 224 @item .pool
 225 This is a synonym for .ltorg.
 226
 227 @end table
 228
 229 @node ARM Opcodes
 230 @section Opcodes
 231
 232 @cindex ARM opcodes
 233 @cindex opcodes for ARM
 234 @code{@value{AS}} implements all the standard ARM opcodes.  It also
 235 implements several pseudo opcodes, including several synthetic load
 236 instructions.
 237
 238 @table @code
 239
 240 @cindex @code{NOP} pseudo op, ARM
 241 @item NOP
 242 @smallexample
 243   nop
 244 @end smallexample
 245
 246 This pseudo op will always evaluate to a legal ARM instruction that does
 247 nothing.  Currently it will evaluate to MOV r0, r0.
 248
 249 @cindex @code{LDR reg,=<label>} pseudo op, ARM
 250 @item LDR
 251 @smallexample
 252   ldr <register> , = <expression>
 253 @end smallexample
 254
 255 If expression evaluates to a numeric constant then a MOV or MVN
 256 instruction will be used in place of the LDR instruction, if the
 257 constant can be generated by either of these instructions.  Otherwise
 258 the constant will be placed into the nearest literal pool (if it not
 259 already there) and a PC relative LDR instruction will be generated.
 260
 261 @cindex @code{ADR reg,<label>} pseudo op, ARM
 262 @item ADR
 263 @smallexample
 264   adr <register> <label>
 265 @end smallexample
 266
 267 This instruction will load the address of @var{label} into the indicated
 268 register.  The instruction will evaluate to a PC relative ADD or SUB
 269 instruction depending upon where the label is located.  If the label is
 270 out of range, or if it is not defined in the same file (and section) as
 271 the ADR instruction, then an error will be generated.  This instruction
 272 will not make use of the literal pool.
 273
 274 @cindex @code{ADRL reg,<label>} pseudo op, ARM
 275 @item ADRL
 276 @smallexample
 277   adrl <register> <label>
 278 @end smallexample
 279
 280 This instruction will load the address of @var{label} into the indicated
 281 register.  The instruction will evaluate to one or two a PC relative ADD
 282 or SUB instructions depending upon where the label is located.  If a
 283 second instruction is not needed a NOP instruction will be generated in
 284 its place, so that this instruction is always 8 bytes long.
 285
 286 If the label is out of range, or if it is not defined in the same file
 287 (and section) as the ADRL instruction, then an error will be generated.
 288 This instruction will not make use of the literal pool.
 289
 290 @end table
 291
 292 For information on the ARM or Thumb instruction sets, see @cite{ARM
 293 Software Development Toolkit Reference Manual}, Advanced RISC Machines
 294 Ltd.
 295