gas/doc/c-arm.texi

   1 @c Copyright (C) 1996, 1998, 1999 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4
   5 @ifset GENERIC
   6 @page
   7 @node ARM-Dependent
   8 @chapter ARM Dependent Features
   9 @end ifset
  10
  11 @ifclear GENERIC
  12 @node Machine Dependencies
  13 @chapter ARM Dependent Features
  14 @end ifclear
  15
  16 @cindex ARM support
  17 @cindex Thumb support
  18 @menu
  19 * ARM Options::              Options
  20 * ARM Syntax::               Syntax
  21 * ARM Floating Point::       Floating Point
  22 * ARM Directives::           ARM Machine Directives
  23 * ARM Opcodes::              Opcodes
  24 @end menu
  25
  26 @node ARM Options
  27 @section Options
  28 @cindex ARM options (none)
  29 @cindex options for ARM (none)
  30 @table @code
  31 @cindex @code{-marm} command line option, ARM
  32 @item -marm @var{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920||strongarm|strongarm110|strongarm1100]}
  33 This option specifies the target processor.  The assembler will issue an
  34 error message if an attempt is made to assemble an instruction which
  35 will not execute on the target processor.
  36 @cindex @code{-marmv} command line option, ARM
  37 @item -marmv @var{[2|2a|3|3m|4|4t|5|5t]}
  38 This option specifies the target architecture.  The assembler will issue
  39 an error message if an attempt is made to assemble an instruction which
  40 will not execute on the target architecture.
  41 @cindex @code{-mthumb} command line option, ARM
  42 @item -mthumb
  43 This option specifies that only Thumb instructions should be assembled.
  44 @cindex @code{-mall} command line option, ARM
  45 @item -mall
  46 This option specifies that any Arm or Thumb instruction should be assembled.
  47 @cindex @code{-mfpa} command line option, ARM
  48 @item -mfpa @var{[10|11]}
  49 This option specifies the floating point architecture in use on the
  50 target processor.
  51 @cindex @code{-mfpe-old} command line option, ARM
  52 @item -mfpe-old
  53 Do not allow the assemble of floating point multiple instructions.
  54 @cindex @code{-mno-fpu} command line option, ARM
  55 @item -mno-fpu
  56 Do not allow the assembly of any floating point instructions.
  57 @cindex @code{-mthumb-interwork} command line option, ARM
  58 @item -mthumb-interwork
  59 This option specifies that the output generated by the assembler should
  60 be marked as supporting interworking.
  61 @cindex @code{-mapcs} command line option, ARM
  62 @item -mapcs @var{[26|32]}
  63 This option specifies that the output generated by the assembler should
  64 be marked as supporting the indicated version of the Arm Procedure.
  65 Calling Standard.
  66 @item -mapcs-float
  67 This indicates the the floating point variant of the APCS should be
  68 used.  In this variant floating point arguments are passed in FP
  69 registers ratehr than integer registers.
  70 @item -mapcs-reentrant
  71 This indicates that the reentrant variant of the APCS should be used.
  72 This variant supports position independent code.
  73 @cindex @code{-EB} command line option, ARM
  74 @item -EB
  75 This option specifies that the output generated by the assembler should
  76 be marked as being encoded for a big-endian processor.
  77 @cindex @code{-EL} command line option, ARM
  78 @item -EL
  79 This option specifies that the output generated by the assembler should
  80 be marked as being encoded for a little-endian processor.
  81 @cindex @code{-k} command line option, ARM
  82 @cindex PIC code generation for ARM
  83 @item -k
  84 This option enables the generation of PIC (position independent code).
  85 @item -moabi
  86 This indicates that the code should be assembled using the old ARM ELF
  87 conventions, based on a beta release release of the ARM-ELF
  88 specifications, rather than the default conventions which are based on
  89 the final release of the ARM-ELF specifications.
  90 @end table
  91
  92
  93 @node ARM Syntax
  94 @section Syntax
  95 @menu
  96 * ARM-Chars::                Special Characters
  97 * ARM-Regs::                 Register Names
  98 @end menu
  99
 100 @node ARM-Chars
 101 @subsection Special Characters
 102
 103 @cindex line comment character, ARM
 104 @cindex ARM line comment character
 105 The presence of a @samp{#} and @samp{@@} on a line indicates the start of
 106 a comment that extends to the end of the current line.
 107
 108 @cindex identifiers, ARM
 109 @cindex ARM identifiers
 110 *TODO* Explain about /data modifier on symbols.
 111
 112 @node ARM-Regs
 113 @subsection Register Names
 114
 115 @cindex ARM register names
 116 @cindex register names, ARM
 117 *TODO* Explain about ARM register naming, and the predefined names.
 118
 119 @node ARM Floating Point
 120 @section Floating Point
 121
 122 @cindex floating point, ARM (@sc{ieee})
 123 @cindex ARM floating point (@sc{ieee})
 124 The ARM family uses @sc{ieee} floating-point numbers.
 125
 126
 127
 128 @node ARM Directives
 129 @section ARM Machine Directives
 130
 131 @cindex machine directives, ARM
 132 @cindex ARM machine directives
 133 @table @code
 134
 135 @cindex @code{req} directive, ARM
 136 @item @var{name} .req @var{register name}
 137 This creates an alias for @var{register name} called @var{name}.  For
 138 example:
 139
 140 @smallexample
 141         foo .req r0
 142 @end smallexample
 143
 144 @cindex @code{code} directive, ARM
 145 @item .code @var{[16|32]}
 146 This directive selects the instruction set being generated. The value 16
 147 selects Thumb, with the value 32 selecting ARM.
 148
 149 @cindex @code{thumb} directive, ARM
 150 @item .thumb
 151 This performs the same action as @var{.code 16}.
 152
 153 @cindex @code{arm} directive, ARM
 154 @item .arm
 155 This performs the same action as @var{.code 32}.
 156
 157 @cindex @code{force_thumb} directive, ARM
 158 @item .force_thumb
 159 This directive forces the selection of Thumb instructions, even if the
 160 target processor does not support those instructions
 161
 162 @cindex @code{thumb_func} directive, ARM
 163 @item .thumb_func
 164 This directive specifies that the following symbol is the name of a
 165 Thumb encoded function.  This information is necessary in order to allow
 166 the assembler and linker to generate correct code for interworking
 167 between Arm and Thumb instructions and should be used even if
 168 interworking is not going to be performed.
 169
 170 @cindex @code{.ltorg} directive, ARM
 171 @item .ltorg
 172 This directive causes the current contents of the literal pool to be
 173 dumped into the current section (which is assumed to be the .text
 174 section) at the current location (aligned to a word boundary).
 175
 176 @cindex @code{.pool} directive, ARM
 177 @item .pool
 178 This is a synonym for .ltorg.
 179
 180 @end table
 181
 182 @node ARM Opcodes
 183 @section Opcodes
 184
 185 @cindex ARM opcodes
 186 @cindex opcodes for ARM
 187 @code{@value{AS}} implements all the standard ARM opcodes.  It also
 188 implements several pseudo opcodes, including several synthetic load
 189 instructions.
 190
 191 @table @code
 192
 193 @cindex @code{NOP} pseudo op, ARM
 194 @item NOP
 195 @smallexample
 196   nop
 197 @end smallexample
 198
 199 This pseudo op will always evaluate to a legal ARM instruction that does
 200 nothing.  Currently it will evaluate to MOV r0, r0.
 201
 202 @cindex @code{LDR reg,=<label>} pseudo op, ARM
 203 @item LDR
 204 @smallexample
 205   ldr <register> , = <expression>
 206 @end smallexample
 207
 208 If expression evaluates to a numeric constant then a MOV or MVN
 209 instruction will be used in place of the LDR instruction, if the
 210 constant can be generated by either of these instructions.  Otherwise
 211 the constant will be placed into the nearest literal pool (if it not
 212 already there) and a PC relative LDR instruction will be generated.
 213
 214 @cindex @code{ADR reg,<label>} pseudo op, ARM
 215 @item ADR
 216 @smallexample
 217   adr <register> <label>
 218 @end smallexample
 219
 220 This instruction will load the address of @var{label} into the indicated
 221 register.  The instruction will evaluate to a PC relative ADD or SUB
 222 instruction depending upon where the label is located.  If the label is
 223 out of range, or if it is not defined in the same file (and section) as
 224 the ADR instruction, then an error will be generated.  This instruction
 225 will not make use of the literal pool.
 226
 227 @cindex @code{ADRL reg,<label>} pseudo op, ARM
 228 @item ADRL
 229 @smallexample
 230   adrl <register> <label>
 231 @end smallexample
 232
 233 This instruction will load the address of @var{label} into the indicated
 234 register.  The instruction will evaluate to one or two a PC relative ADD
 235 or SUB instructions depending upon where the label is located.  If a
 236 second instruction is not needed a NOP instruction will be generated in
 237 its place, so that this instruction is always 8 bytes long.
 238
 239 If the label is out of range, or if it is not defined in the same file
 240 (and section) as the ADRL instruction, then an error will be generated.
 241 This instruction will not make use of the literal pool.
 242
 243 @end table
 244
 245 For information on the ARM or Thumb instruction sets, see @cite{ARM
 246 Software Development Toolkit Reference Manual}, Advanced RISC Machines
 247 Ltd.
 248