1 @c Copyright (C) 1996-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
146 @code{cortex-m0plus},
149 @code{marvell-whitney},
152 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
153 @code{i80200} (Intel XScale processor)
154 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
157 The special name @code{all} may be used to allow the
158 assembler to accept instructions valid for any ARM processor.
160 In addition to the basic instruction set, the assembler can be told to
161 accept various extension mnemonics that extend the processor using the
162 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
163 is equivalent to specifying @code{-mcpu=ep9312}.
165 Multiple extensions may be specified, separated by a @code{+}. The
166 extensions should be specified in ascending alphabetical order.
168 Some extensions may be restricted to particular architectures; this is
169 documented in the list of extensions below.
171 Extension mnemonics may also be removed from those the assembler accepts.
172 This is done be prepending @code{no} to the option that adds the extension.
173 Extensions that are removed should be listed after all extensions which have
174 been added, again in ascending alphabetical order. For example,
175 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
178 The following extensions are currently supported:
180 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
181 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
182 @code{fp} (Floating Point Extensions for v8-A architecture),
183 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
184 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
185 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
190 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
192 @code{os} (Operating System for v6M architecture),
193 @code{predres} (Execution and Data Prediction Restriction Instruction for
194 v8-A architectures, added by default from v8.5-A),
195 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
196 default from v8.5-A),
197 @code{sec} (Security Extensions for v6K and v7-A architectures),
198 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
199 @code{virt} (Virtualization Extensions for v7-A architecture, implies
201 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
202 @code{ras} (Reliability, Availability and Serviceability extensions
203 for v8-A architecture),
204 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
209 @cindex @code{-march=} command-line option, ARM
210 @item -march=@var{architecture}[+@var{extension}@dots{}]
211 This option specifies the target architecture. The assembler will issue
212 an error message if an attempt is made to assemble an instruction which
213 will not execute on the target architecture. The following architecture
214 names are recognized:
254 If both @code{-mcpu} and
255 @code{-march} are specified, the assembler will use
256 the setting for @code{-mcpu}.
258 The architecture option can be extended with the same instruction set
259 extension options as the @code{-mcpu} option.
261 @cindex @code{-mfpu=} command-line option, ARM
262 @item -mfpu=@var{floating-point-format}
264 This option specifies the floating point format to assemble for. The
265 assembler will issue an error message if an attempt is made to assemble
266 an instruction which will not execute on the target floating point unit.
267 The following format options are recognized:
287 @code{vfpv3-d16-fp16},
304 @code{neon-fp-armv8},
305 @code{crypto-neon-fp-armv8},
306 @code{neon-fp-armv8.1}
308 @code{crypto-neon-fp-armv8.1}.
310 In addition to determining which instructions are assembled, this option
311 also affects the way in which the @code{.double} assembler directive behaves
312 when assembling little-endian code.
314 The default is dependent on the processor selected. For Architecture 5 or
315 later, the default is to assemble for VFP instructions; for earlier
316 architectures the default is to assemble for FPA instructions.
318 @cindex @code{-mthumb} command-line option, ARM
320 This option specifies that the assembler should start assembling Thumb
321 instructions; that is, it should behave as though the file starts with a
322 @code{.code 16} directive.
324 @cindex @code{-mthumb-interwork} command-line option, ARM
325 @item -mthumb-interwork
326 This option specifies that the output generated by the assembler should
327 be marked as supporting interworking. It also affects the behaviour
328 of the @code{ADR} and @code{ADRL} pseudo opcodes.
330 @cindex @code{-mimplicit-it} command-line option, ARM
331 @item -mimplicit-it=never
332 @itemx -mimplicit-it=always
333 @itemx -mimplicit-it=arm
334 @itemx -mimplicit-it=thumb
335 The @code{-mimplicit-it} option controls the behavior of the assembler when
336 conditional instructions are not enclosed in IT blocks.
337 There are four possible behaviors.
338 If @code{never} is specified, such constructs cause a warning in ARM
339 code and an error in Thumb-2 code.
340 If @code{always} is specified, such constructs are accepted in both
341 ARM and Thumb-2 code, where the IT instruction is added implicitly.
342 If @code{arm} is specified, such constructs are accepted in ARM code
343 and cause an error in Thumb-2 code.
344 If @code{thumb} is specified, such constructs cause a warning in ARM
345 code and are accepted in Thumb-2 code. If you omit this option, the
346 behavior is equivalent to @code{-mimplicit-it=arm}.
348 @cindex @code{-mapcs-26} command-line option, ARM
349 @cindex @code{-mapcs-32} command-line option, ARM
352 These options specify that the output generated by the assembler should
353 be marked as supporting the indicated version of the Arm Procedure.
356 @cindex @code{-matpcs} command-line option, ARM
358 This option specifies that the output generated by the assembler should
359 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
360 enabled this option will cause the assembler to create an empty
361 debugging section in the object file called .arm.atpcs. Debuggers can
362 use this to determine the ABI being used by.
364 @cindex @code{-mapcs-float} command-line option, ARM
366 This indicates the floating point variant of the APCS should be
367 used. In this variant floating point arguments are passed in FP
368 registers rather than integer registers.
370 @cindex @code{-mapcs-reentrant} command-line option, ARM
371 @item -mapcs-reentrant
372 This indicates that the reentrant variant of the APCS should be used.
373 This variant supports position independent code.
375 @cindex @code{-mfloat-abi=} command-line option, ARM
376 @item -mfloat-abi=@var{abi}
377 This option specifies that the output generated by the assembler should be
378 marked as using specified floating point ABI.
379 The following values are recognized:
385 @cindex @code{-eabi=} command-line option, ARM
386 @item -meabi=@var{ver}
387 This option specifies which EABI version the produced object files should
389 The following values are recognized:
395 @cindex @code{-EB} command-line option, ARM
397 This option specifies that the output generated by the assembler should
398 be marked as being encoded for a big-endian processor.
400 Note: If a program is being built for a system with big-endian data
401 and little-endian instructions then it should be assembled with the
402 @option{-EB} option, (all of it, code and data) and then linked with
403 the @option{--be8} option. This will reverse the endianness of the
404 instructions back to little-endian, but leave the data as big-endian.
406 @cindex @code{-EL} command-line option, ARM
408 This option specifies that the output generated by the assembler should
409 be marked as being encoded for a little-endian processor.
411 @cindex @code{-k} command-line option, ARM
412 @cindex PIC code generation for ARM
414 This option specifies that the output of the assembler should be marked
415 as position-independent code (PIC).
417 @cindex @code{--fix-v4bx} command-line option, ARM
419 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
420 the linker option of the same name.
422 @cindex @code{-mwarn-deprecated} command-line option, ARM
423 @item -mwarn-deprecated
424 @itemx -mno-warn-deprecated
425 Enable or disable warnings about using deprecated options or
426 features. The default is to warn.
428 @cindex @code{-mccs} command-line option, ARM
430 Turns on CodeComposer Studio assembly syntax compatibility mode.
432 @cindex @code{-mwarn-syms} command-line option, ARM
434 @itemx -mno-warn-syms
435 Enable or disable warnings about symbols that match the names of ARM
436 instructions. The default is to warn.
444 * ARM-Instruction-Set:: Instruction Set
445 * ARM-Chars:: Special Characters
446 * ARM-Regs:: Register Names
447 * ARM-Relocations:: Relocations
448 * ARM-Neon-Alignment:: NEON Alignment Specifiers
451 @node ARM-Instruction-Set
452 @subsection Instruction Set Syntax
453 Two slightly different syntaxes are support for ARM and THUMB
454 instructions. The default, @code{divided}, uses the old style where
455 ARM and THUMB instructions had their own, separate syntaxes. The new,
456 @code{unified} syntax, which can be selected via the @code{.syntax}
457 directive, and has the following main features:
461 Immediate operands do not require a @code{#} prefix.
464 The @code{IT} instruction may appear, and if it does it is validated
465 against subsequent conditional affixes. In ARM mode it does not
466 generate machine code, in THUMB mode it does.
469 For ARM instructions the conditional affixes always appear at the end
470 of the instruction. For THUMB instructions conditional affixes can be
471 used, but only inside the scope of an @code{IT} instruction.
474 All of the instructions new to the V6T2 architecture (and later) are
475 available. (Only a few such instructions can be written in the
476 @code{divided} syntax).
479 The @code{.N} and @code{.W} suffixes are recognized and honored.
482 All instructions set the flags if and only if they have an @code{s}
487 @subsection Special Characters
489 @cindex line comment character, ARM
490 @cindex ARM line comment character
491 The presence of a @samp{@@} anywhere on a line indicates the start of
492 a comment that extends to the end of that line.
494 If a @samp{#} appears as the first character of a line then the whole
495 line is treated as a comment, but in this case the line could also be
496 a logical line number directive (@pxref{Comments}) or a preprocessor
497 control command (@pxref{Preprocessing}).
499 @cindex line separator, ARM
500 @cindex statement separator, ARM
501 @cindex ARM line separator
502 The @samp{;} character can be used instead of a newline to separate
505 @cindex immediate character, ARM
506 @cindex ARM immediate character
507 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
509 @cindex identifiers, ARM
510 @cindex ARM identifiers
511 *TODO* Explain about /data modifier on symbols.
514 @subsection Register Names
516 @cindex ARM register names
517 @cindex register names, ARM
518 *TODO* Explain about ARM register naming, and the predefined names.
520 @node ARM-Relocations
521 @subsection ARM relocation generation
523 @cindex data relocations, ARM
524 @cindex ARM data relocations
525 Specific data relocations can be generated by putting the relocation name
526 in parentheses after the symbol name. For example:
532 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
534 The following relocations are supported:
550 For compatibility with older toolchains the assembler also accepts
551 @code{(PLT)} after branch targets. On legacy targets this will
552 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
553 targets it will encode either the @samp{R_ARM_CALL} or
554 @samp{R_ARM_JUMP24} relocation, as appropriate.
556 @cindex MOVW and MOVT relocations, ARM
557 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
558 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
559 respectively. For example to load the 32-bit address of foo into r0:
562 MOVW r0, #:lower16:foo
563 MOVT r0, #:upper16:foo
566 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
567 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
568 generated by prefixing the value with @samp{#:lower0_7:#},
569 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
570 respectively. For example to load the 32-bit address of foo into r0:
573 MOVS r0, #:upper8_15:#foo
575 ADDS r0, #:upper0_7:#foo
577 ADDS r0, #:lower8_15:#foo
579 ADDS r0, #:lower0_7:#foo
582 @node ARM-Neon-Alignment
583 @subsection NEON Alignment Specifiers
585 @cindex alignment for NEON instructions
586 Some NEON load/store instructions allow an optional address
588 The ARM documentation specifies that this is indicated by
589 @samp{@@ @var{align}}. However GAS already interprets
590 the @samp{@@} character as a "line comment" start,
591 so @samp{: @var{align}} is used instead. For example:
594 vld1.8 @{q0@}, [r0, :128]
597 @node ARM Floating Point
598 @section Floating Point
600 @cindex floating point, ARM (@sc{ieee})
601 @cindex ARM floating point (@sc{ieee})
602 The ARM family uses @sc{ieee} floating-point numbers.
605 @section ARM Machine Directives
607 @cindex machine directives, ARM
608 @cindex ARM machine directives
611 @c AAAAAAAAAAAAAAAAAAAAAAAAA
614 @cindex @code{.2byte} directive, ARM
615 @cindex @code{.4byte} directive, ARM
616 @cindex @code{.8byte} directive, ARM
617 @item .2byte @var{expression} [, @var{expression}]*
618 @itemx .4byte @var{expression} [, @var{expression}]*
619 @itemx .8byte @var{expression} [, @var{expression}]*
620 These directives write 2, 4 or 8 byte values to the output section.
623 @cindex @code{.align} directive, ARM
624 @item .align @var{expression} [, @var{expression}]
625 This is the generic @var{.align} directive. For the ARM however if the
626 first argument is zero (ie no alignment is needed) the assembler will
627 behave as if the argument had been 2 (ie pad to the next four byte
628 boundary). This is for compatibility with ARM's own assembler.
630 @cindex @code{.arch} directive, ARM
631 @item .arch @var{name}
632 Select the target architecture. Valid values for @var{name} are the same as
633 for the @option{-march} command-line option without the instruction set
636 Specifying @code{.arch} clears any previously selected architecture
639 @cindex @code{.arch_extension} directive, ARM
640 @item .arch_extension @var{name}
641 Add or remove an architecture extension to the target architecture. Valid
642 values for @var{name} are the same as those accepted as architectural
643 extensions by the @option{-mcpu} and @option{-march} command-line options.
645 @code{.arch_extension} may be used multiple times to add or remove extensions
646 incrementally to the architecture being compiled for.
648 @cindex @code{.arm} directive, ARM
650 This performs the same action as @var{.code 32}.
652 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
654 @cindex @code{.bss} directive, ARM
656 This directive switches to the @code{.bss} section.
658 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
660 @cindex @code{.cantunwind} directive, ARM
662 Prevents unwinding through the current function. No personality routine
663 or exception table data is required or permitted.
665 @cindex @code{.code} directive, ARM
666 @item .code @code{[16|32]}
667 This directive selects the instruction set being generated. The value 16
668 selects Thumb, with the value 32 selecting ARM.
670 @cindex @code{.cpu} directive, ARM
671 @item .cpu @var{name}
672 Select the target processor. Valid values for @var{name} are the same as
673 for the @option{-mcpu} command-line option without the instruction set
676 Specifying @code{.cpu} clears any previously selected architecture
679 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
681 @cindex @code{.dn} and @code{.qn} directives, ARM
682 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
683 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
685 The @code{dn} and @code{qn} directives are used to create typed
686 and/or indexed register aliases for use in Advanced SIMD Extension
687 (Neon) instructions. The former should be used to create aliases
688 of double-precision registers, and the latter to create aliases of
689 quad-precision registers.
691 If these directives are used to create typed aliases, those aliases can
692 be used in Neon instructions instead of writing types after the mnemonic
693 or after each operand. For example:
702 This is equivalent to writing the following:
708 Aliases created using @code{dn} or @code{qn} can be destroyed using
711 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
713 @cindex @code{.eabi_attribute} directive, ARM
714 @item .eabi_attribute @var{tag}, @var{value}
715 Set the EABI object attribute @var{tag} to @var{value}.
717 The @var{tag} is either an attribute number, or one of the following:
718 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
719 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
720 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
721 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
722 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
723 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
724 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
725 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
726 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
727 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
728 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
729 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
730 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
731 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
732 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
733 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
734 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
735 @code{Tag_conformance}, @code{Tag_T2EE_use},
736 @code{Tag_Virtualization_use}
738 The @var{value} is either a @code{number}, @code{"string"}, or
739 @code{number, "string"} depending on the tag.
741 Note - the following legacy values are also accepted by @var{tag}:
742 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
743 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
745 @cindex @code{.even} directive, ARM
747 This directive aligns to an even-numbered address.
749 @cindex @code{.extend} directive, ARM
750 @cindex @code{.ldouble} directive, ARM
751 @item .extend @var{expression} [, @var{expression}]*
752 @itemx .ldouble @var{expression} [, @var{expression}]*
753 These directives write 12byte long double floating-point values to the
754 output section. These are not compatible with current ARM processors
757 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
760 @cindex @code{.fnend} directive, ARM
762 Marks the end of a function with an unwind table entry. The unwind index
763 table entry is created when this directive is processed.
765 If no personality routine has been specified then standard personality
766 routine 0 or 1 will be used, depending on the number of unwind opcodes
770 @cindex @code{.fnstart} directive, ARM
772 Marks the start of a function with an unwind table entry.
774 @cindex @code{.force_thumb} directive, ARM
776 This directive forces the selection of Thumb instructions, even if the
777 target processor does not support those instructions
779 @cindex @code{.fpu} directive, ARM
780 @item .fpu @var{name}
781 Select the floating-point unit to assemble for. Valid values for @var{name}
782 are the same as for the @option{-mfpu} command-line option.
784 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
785 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
787 @cindex @code{.handlerdata} directive, ARM
789 Marks the end of the current function, and the start of the exception table
790 entry for that function. Anything between this directive and the
791 @code{.fnend} directive will be added to the exception table entry.
793 Must be preceded by a @code{.personality} or @code{.personalityindex}
796 @c IIIIIIIIIIIIIIIIIIIIIIIIII
798 @cindex @code{.inst} directive, ARM
799 @item .inst @var{opcode} [ , @dots{} ]
800 @itemx .inst.n @var{opcode} [ , @dots{} ]
801 @itemx .inst.w @var{opcode} [ , @dots{} ]
802 Generates the instruction corresponding to the numerical value @var{opcode}.
803 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
804 specified explicitly, overriding the normal encoding rules.
806 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
807 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
808 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
810 @item .ldouble @var{expression} [, @var{expression}]*
813 @cindex @code{.ltorg} directive, ARM
815 This directive causes the current contents of the literal pool to be
816 dumped into the current section (which is assumed to be the .text
817 section) at the current location (aligned to a word boundary).
818 @code{GAS} maintains a separate literal pool for each section and each
819 sub-section. The @code{.ltorg} directive will only affect the literal
820 pool of the current section and sub-section. At the end of assembly
821 all remaining, un-empty literal pools will automatically be dumped.
823 Note - older versions of @code{GAS} would dump the current literal
824 pool any time a section change occurred. This is no longer done, since
825 it prevents accurate control of the placement of literal pools.
827 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
829 @cindex @code{.movsp} directive, ARM
830 @item .movsp @var{reg} [, #@var{offset}]
831 Tell the unwinder that @var{reg} contains an offset from the current
832 stack pointer. If @var{offset} is not specified then it is assumed to be
835 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
836 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
838 @cindex @code{.object_arch} directive, ARM
839 @item .object_arch @var{name}
840 Override the architecture recorded in the EABI object attribute section.
841 Valid values for @var{name} are the same as for the @code{.arch} directive.
842 Typically this is useful when code uses runtime detection of CPU features.
844 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
846 @cindex @code{.packed} directive, ARM
847 @item .packed @var{expression} [, @var{expression}]*
848 This directive writes 12-byte packed floating-point values to the
849 output section. These are not compatible with current ARM processors
853 @cindex @code{.pad} directive, ARM
854 @item .pad #@var{count}
855 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
856 A positive value indicates the function prologue allocated stack space by
857 decrementing the stack pointer.
859 @cindex @code{.personality} directive, ARM
860 @item .personality @var{name}
861 Sets the personality routine for the current function to @var{name}.
863 @cindex @code{.personalityindex} directive, ARM
864 @item .personalityindex @var{index}
865 Sets the personality routine for the current function to the EABI standard
866 routine number @var{index}
868 @cindex @code{.pool} directive, ARM
870 This is a synonym for .ltorg.
872 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
873 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
875 @cindex @code{.req} directive, ARM
876 @item @var{name} .req @var{register name}
877 This creates an alias for @var{register name} called @var{name}. For
884 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
887 @cindex @code{.save} directive, ARM
888 @item .save @var{reglist}
889 Generate unwinder annotations to restore the registers in @var{reglist}.
890 The format of @var{reglist} is the same as the corresponding store-multiple
894 @exdent @emph{core registers}
895 .save @{r4, r5, r6, lr@}
896 stmfd sp!, @{r4, r5, r6, lr@}
897 @exdent @emph{FPA registers}
900 @exdent @emph{VFP registers}
901 .save @{d8, d9, d10@}
902 fstmdx sp!, @{d8, d9, d10@}
903 @exdent @emph{iWMMXt registers}
905 wstrd wr11, [sp, #-8]!
906 wstrd wr10, [sp, #-8]!
909 wstrd wr11, [sp, #-8]!
911 wstrd wr10, [sp, #-8]!
915 @cindex @code{.setfp} directive, ARM
916 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
917 Make all unwinder annotations relative to a frame pointer. Without this
918 the unwinder will use offsets from the stack pointer.
920 The syntax of this directive is the same as the @code{add} or @code{mov}
921 instruction used to set the frame pointer. @var{spreg} must be either
922 @code{sp} or mentioned in a previous @code{.movsp} directive.
932 @cindex @code{.secrel32} directive, ARM
933 @item .secrel32 @var{expression} [, @var{expression}]*
934 This directive emits relocations that evaluate to the section-relative
935 offset of each expression's symbol. This directive is only supported
938 @cindex @code{.syntax} directive, ARM
939 @item .syntax [@code{unified} | @code{divided}]
940 This directive sets the Instruction Set Syntax as described in the
941 @ref{ARM-Instruction-Set} section.
943 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
945 @cindex @code{.thumb} directive, ARM
947 This performs the same action as @var{.code 16}.
949 @cindex @code{.thumb_func} directive, ARM
951 This directive specifies that the following symbol is the name of a
952 Thumb encoded function. This information is necessary in order to allow
953 the assembler and linker to generate correct code for interworking
954 between Arm and Thumb instructions and should be used even if
955 interworking is not going to be performed. The presence of this
956 directive also implies @code{.thumb}
958 This directive is not necessary when generating EABI objects. On these
959 targets the encoding is implicit when generating Thumb code.
961 @cindex @code{.thumb_set} directive, ARM
963 This performs the equivalent of a @code{.set} directive in that it
964 creates a symbol which is an alias for another symbol (possibly not yet
965 defined). This directive also has the added property in that it marks
966 the aliased symbol as being a thumb function entry point, in the same
967 way that the @code{.thumb_func} directive does.
969 @cindex @code{.tlsdescseq} directive, ARM
970 @item .tlsdescseq @var{tls-variable}
971 This directive is used to annotate parts of an inlined TLS descriptor
972 trampoline. Normally the trampoline is provided by the linker, and
973 this directive is not needed.
975 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
977 @cindex @code{.unreq} directive, ARM
978 @item .unreq @var{alias-name}
979 This undefines a register alias which was previously defined using the
980 @code{req}, @code{dn} or @code{qn} directives. For example:
987 An error occurs if the name is undefined. Note - this pseudo op can
988 be used to delete builtin in register name aliases (eg 'r0'). This
989 should only be done if it is really necessary.
991 @cindex @code{.unwind_raw} directive, ARM
992 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
993 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
994 the stack pointer by @var{offset} bytes.
996 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
999 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1001 @cindex @code{.vsave} directive, ARM
1002 @item .vsave @var{vfp-reglist}
1003 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1004 using FLDMD. Also works for VFPv3 registers
1005 that are to be restored using VLDM.
1006 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1010 @exdent @emph{VFP registers}
1011 .vsave @{d8, d9, d10@}
1012 fstmdd sp!, @{d8, d9, d10@}
1013 @exdent @emph{VFPv3 registers}
1014 .vsave @{d15, d16, d17@}
1015 vstm sp!, @{d15, d16, d17@}
1018 Since FLDMX and FSTMX are now deprecated, this directive should be
1019 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1021 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1022 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1023 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1024 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1032 @cindex opcodes for ARM
1033 @code{@value{AS}} implements all the standard ARM opcodes. It also
1034 implements several pseudo opcodes, including several synthetic load
1039 @cindex @code{NOP} pseudo op, ARM
1045 This pseudo op will always evaluate to a legal ARM instruction that does
1046 nothing. Currently it will evaluate to MOV r0, r0.
1048 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1051 ldr <register> , = <expression>
1054 If expression evaluates to a numeric constant then a MOV or MVN
1055 instruction will be used in place of the LDR instruction, if the
1056 constant can be generated by either of these instructions. Otherwise
1057 the constant will be placed into the nearest literal pool (if it not
1058 already there) and a PC relative LDR instruction will be generated.
1060 @cindex @code{ADR reg,<label>} pseudo op, ARM
1063 adr <register> <label>
1066 This instruction will load the address of @var{label} into the indicated
1067 register. The instruction will evaluate to a PC relative ADD or SUB
1068 instruction depending upon where the label is located. If the label is
1069 out of range, or if it is not defined in the same file (and section) as
1070 the ADR instruction, then an error will be generated. This instruction
1071 will not make use of the literal pool.
1073 If @var{label} is a thumb function symbol, and thumb interworking has
1074 been enabled via the @option{-mthumb-interwork} option then the bottom
1075 bit of the value stored into @var{register} will be set. This allows
1076 the following sequence to work as expected:
1079 adr r0, thumb_function
1083 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1086 adrl <register> <label>
1089 This instruction will load the address of @var{label} into the indicated
1090 register. The instruction will evaluate to one or two PC relative ADD
1091 or SUB instructions depending upon where the label is located. If a
1092 second instruction is not needed a NOP instruction will be generated in
1093 its place, so that this instruction is always 8 bytes long.
1095 If the label is out of range, or if it is not defined in the same file
1096 (and section) as the ADRL instruction, then an error will be generated.
1097 This instruction will not make use of the literal pool.
1099 If @var{label} is a thumb function symbol, and thumb interworking has
1100 been enabled via the @option{-mthumb-interwork} option then the bottom
1101 bit of the value stored into @var{register} will be set.
1105 For information on the ARM or Thumb instruction sets, see @cite{ARM
1106 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1109 @node ARM Mapping Symbols
1110 @section Mapping Symbols
1112 The ARM ELF specification requires that special symbols be inserted
1113 into object files to mark certain features:
1119 At the start of a region of code containing ARM instructions.
1123 At the start of a region of code containing THUMB instructions.
1127 At the start of a region of data.
1131 The assembler will automatically insert these symbols for you - there
1132 is no need to code them yourself. Support for tagging symbols ($b,
1133 $f, $p and $m) which is also mentioned in the current ARM ELF
1134 specification is not implemented. This is because they have been
1135 dropped from the new EABI and so tools cannot rely upon their
1138 @node ARM Unwinding Tutorial
1141 The ABI for the ARM Architecture specifies a standard format for
1142 exception unwind information. This information is used when an
1143 exception is thrown to determine where control should be transferred.
1144 In particular, the unwind information is used to determine which
1145 function called the function that threw the exception, and which
1146 function called that one, and so forth. This information is also used
1147 to restore the values of callee-saved registers in the function
1148 catching the exception.
1150 If you are writing functions in assembly code, and those functions
1151 call other functions that throw exceptions, you must use assembly
1152 pseudo ops to ensure that appropriate exception unwind information is
1153 generated. Otherwise, if one of the functions called by your assembly
1154 code throws an exception, the run-time library will be unable to
1155 unwind the stack through your assembly code and your program will not
1158 To illustrate the use of these pseudo ops, we will examine the code
1159 that G++ generates for the following C++ input:
1162 void callee (int *);
1173 This example does not show how to throw or catch an exception from
1174 assembly code. That is a much more complex operation and should
1175 always be done in a high-level language, such as C++, that directly
1176 supports exceptions.
1178 The code generated by one particular version of G++ when compiling the
1185 @ Function supports interworking.
1186 @ args = 0, pretend = 0, frame = 8
1187 @ frame_needed = 1, uses_anonymous_args = 0
1209 Of course, the sequence of instructions varies based on the options
1210 you pass to GCC and on the version of GCC in use. The exact
1211 instructions are not important since we are focusing on the pseudo ops
1212 that are used to generate unwind information.
1214 An important assumption made by the unwinder is that the stack frame
1215 does not change during the body of the function. In particular, since
1216 we assume that the assembly code does not itself throw an exception,
1217 the only point where an exception can be thrown is from a call, such
1218 as the @code{bl} instruction above. At each call site, the same saved
1219 registers (including @code{lr}, which indicates the return address)
1220 must be located in the same locations relative to the frame pointer.
1222 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1223 op appears immediately before the first instruction of the function
1224 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1225 op appears immediately after the last instruction of the function.
1226 These pseudo ops specify the range of the function.
1228 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1229 @code{.pad}) matters; their exact locations are irrelevant. In the
1230 example above, the compiler emits the pseudo ops with particular
1231 instructions. That makes it easier to understand the code, but it is
1232 not required for correctness. It would work just as well to emit all
1233 of the pseudo ops other than @code{.fnend} in the same order, but
1234 immediately after @code{.fnstart}.
1236 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1237 indicates registers that have been saved to the stack so that they can
1238 be restored before the function returns. The argument to the
1239 @code{.save} pseudo op is a list of registers to save. If a register
1240 is ``callee-saved'' (as specified by the ABI) and is modified by the
1241 function you are writing, then your code must save the value before it
1242 is modified and restore the original value before the function
1243 returns. If an exception is thrown, the run-time library restores the
1244 values of these registers from their locations on the stack before
1245 returning control to the exception handler. (Of course, if an
1246 exception is not thrown, the function that contains the @code{.save}
1247 pseudo op restores these registers in the function epilogue, as is
1248 done with the @code{ldmfd} instruction above.)
1250 You do not have to save callee-saved registers at the very beginning
1251 of the function and you do not need to use the @code{.save} pseudo op
1252 immediately following the point at which the registers are saved.
1253 However, if you modify a callee-saved register, you must save it on
1254 the stack before modifying it and before calling any functions which
1255 might throw an exception. And, you must use the @code{.save} pseudo
1256 op to indicate that you have done so.
1258 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1259 modification of the stack pointer that does not save any registers.
1260 The argument is the number of bytes (in decimal) that are subtracted
1261 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1262 subtracting from the stack pointer increases the size of the stack.)
1264 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1265 indicates the register that contains the frame pointer. The first
1266 argument is the register that is set, which is typically @code{fp}.
1267 The second argument indicates the register from which the frame
1268 pointer takes its value. The third argument, if present, is the value
1269 (in decimal) added to the register specified by the second argument to
1270 compute the value of the frame pointer. You should not modify the
1271 frame pointer in the body of the function.
1273 If you do not use a frame pointer, then you should not use the
1274 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1275 should avoid modifying the stack pointer outside of the function
1276 prologue. Otherwise, the run-time library will be unable to find
1277 saved registers when it is unwinding the stack.
1279 The pseudo ops described above are sufficient for writing assembly
1280 code that calls functions which may throw exceptions. If you need to
1281 know more about the object-file format used to represent unwind
1282 information, you may consult the @cite{Exception Handling ABI for the
1283 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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