gas/doc/c-d10v.texi

   1 @c Copyright (C) 1996 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4 @ifset GENERIC
   5 @page
   6 @node D10V-Dependent
   7 @chapter D10V Dependent Features
   8 @end ifset
   9 @ifclear GENERIC
  10 @node Machine Dependencies
  11 @chapter D10V Dependent Features
  12 @end ifclear
  13
  14 @cindex D10V support
  15 @menu
  16 * D10V-Opts::                   D10V Options
  17 * D10V-Syntax::                 Syntax
  18 * D10V-Float::                  Floating Point
  19 * D10V-opcodes::                Opcodes
  20 @end menu
  21
  22 @node D10V-Opts
  23 @section D10V Options
  24 @cindex options, D10V
  25 @cindex D10V options
  26 The Mitsubishi D10V version of @code{@value{AS}} has a few machine
  27 dependent options.
  28
  29 @table @samp
  30 @item -O
  31 The D10V can often execute two sub-instructions in parallel. When this option
  32 is used, @code{@value{AS}} will attempt to optimize its output by detecting when
  33 instructions can be executed in parallel.
  34 @end table
  35
  36 @node D10V-Syntax
  37 @section Syntax
  38 @cindex D10V syntax
  39 @cindex syntax, D10V
  40
  41 The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual.
  42 The differences are detailed below.
  43
  44 @menu
  45 * D10V-Regs::                 Register Names
  46 * D10V-Size::                 Size Modifiers
  47 * D10V-Chars::                Special Characters
  48 * D10V-Addressing::           Addressing Modes
  49 @end menu
  50
  51 @node D10V-Regs
  52 @subsection Register Names
  53 @cindex D10V registers
  54 @cindex registers, D10V
  55 You can use the predefined symbols @samp{r0} through @samp{r15} to refer to the D10V
  56 registers.  You can also use @samp{sp} as an alias for @samp{r15}.  The accumulators
  57 are @samp{a0} and @samp{a1}.  Register names are not case sensitive.
  58
  59 The D10V also has predefined symbols for these control registers and status bits:
  60 @table @code
  61 @item psw
  62 Processor Status Word
  63 @item bpsw
  64 Backup Processor Status Word
  65 @item pc
  66 Program Counter
  67 @item bpc
  68 Backup Program Counter
  69 @item rpt_c
  70 Repeat Count
  71 @item rpt_s
  72 Repeat Start address
  73 @item rpt_e
  74 Repeat End address
  75 @item mod_s
  76 Modulo Start address
  77 @item mod_e
  78 Modulo End address
  79 @item iba
  80 Instruction Break Address
  81 @item f0
  82 Flag 0
  83 @item f1
  84 Flag 1
  85 @item c
  86 Carry flag
  87 @end table
  88
  89 @node D10V-Size
  90 @subsection Size Modifiers
  91 @cindex D10V size modifiers
  92 @cindex size modifiers, D10V
  93 The D10V version of @code{@value{AS}} uses the instruction names in the D10V
  94 Architecture Manual.  However, the names in the manual are sometimes ambiguous.
  95 There are instruction names that can assemble to a short or long form opcode.
  96 How does the assembler pick the correct form?  @code{@value{AS}} will always pick the
  97 smallest form if it can.  When dealing with a symbol that is not defined yet when a
  98 line is being assembled, it will always use the long form.  If you need to force the
  99 assembler to use either the short or long form of the instruction, you can append
 100 either @samp{.s} (short) or @samp{.l} (long) to it.  For example, if you are writing
 101 an assembly program and you want to do a branch to a symbol that is defined later
 102 in your program, you can write @samp{bra.s   foo}.
 103 Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
 104 have both short and long forms.
 105
 106 @node D10V-Chars
 107 @subsection Special Characters
 108 @cindex line comment character, D10V
 109 @cindex D10V line comment character
 110 @samp{;} and @samp{#} are the line comment characters.
 111 @cindex sub-instruction ordering, D10V
 112 @cindex D10V sub-instruction ordering
 113 Sub-instructions may be executed in order, in reverse-order, or in parallel.
 114 Instructions listed in the standard one-per-line format will be executed sequentially.
 115 To specify the executing order, use the following symbols:
 116 @table @samp
 117 @item ->
 118 Sequential with instruction on the left first.
 119 @item <-
 120 Sequential with instruction on the right first.
 121 @item ||
 122 Parallel
 123 @end table
 124 The D10V syntax allows either one instruction per line, one instruction per line with
 125 the execution symbol, or two instructions per line.  For example
 126 @table @code
 127 @item abs       a1      ->      abs     r0
 128 Execute these sequentially.  The instruction on the right is in the right
 129 container and is executed second.
 130 @item abs       r0      <-      abs     a1
 131 Execute these reverse-sequentially.  The instruction on the right is in the right
 132 container, and is executed first.
 133 @item ld2w    r2,@r8+         ||      mac     a0,r0,r7
 134 Execute these in parallel.
 135 @item ld2w    r2,@r8+         ||
 136 @itemx mac     a0,r0,r7
 137 Two-line format. Execute these in parallel.
 138 @item ld2w    r2,@r8+
 139 @itemx mac     a0,r0,r7
 140 Two-line format. Execute these sequentially.  Assembler will
 141 put them in the proper containers.
 142 @item ld2w    r2,@r8+         ->
 143 @itemx mac     a0,r0,r7
 144 Two-line format. Execute these sequentially.  Same as above but
 145 second instruction will always go into right container.
 146 @end table
 147 @cindex symbol names, @samp{$} in
 148 @cindex @code{$} in symbol names
 149 Since @samp{$} has no special meaning, you may use it in symbol names.
 150
 151 @node D10V-Addressing
 152 @subsection Addressing Modes
 153 @cindex addressing modes, D10V
 154 @cindex D10V addressing modes
 155 @code{@value{AS}} understands the following addressing modes for the D10V.
 156 @code{R@var{n}} in the following refers to any of the numbered
 157 registers, but @emph{not} the control registers.
 158 @table @code
 159 @item R@var{n}
 160 Register direct
 161 @item @@R@var{n}
 162 Register indirect
 163 @item @@R@var{n}+
 164 Register indirect with post-increment
 165 @item @@R@var{n}-
 166 Register indirect with post-decrement
 167 @item @@-SP
 168 Register indirect with pre-decrement
 169 @item @@(@var{disp}, R@var{n})
 170 Register indirect with displacement
 171 @item @@(R0, GBR)
 172 GBR indexed
 173 @item @var{addr}
 174 PC relative address (for branch or rep).
 175 @item #@var{imm}
 176 Immediate data
 177 @end table
 178
 179 @node D10V-Float
 180 @section Floating Point
 181 @cindex floating point, D10V
 182 @cindex D10V floating point
 183 The D10V has no hardware floating point, but the @code{.float} and @code{.double}
 184 directives generates @sc{ieee} floating-point numbers for compatibility
 185 with other development tools.
 186
 187 @node D10V Opcodes
 188 @section Opcodes
 189 @cindex D10V opcode summary
 190 @cindex opcode summary, D10V
 191 @cindex mnemonics, D10V
 192 @cindex instruction summary, D10V
 193 For detailed information on the D10V machine instruction set, see
 194 @cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications}
 195 (Mitsubishi Electric Corp.).
 196 @code{@value{AS}} implements all the standard D10V opcodes.  The only changes are those
 197 described in the section on size modifiers
 198