1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
128 In addition to the basic instruction set, the assembler can be told to
129 accept various extension mnemonics. For example,
130 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
131 @var{vmx}. The following extensions are currently supported:
194 Note that rather than extending a basic instruction set, the extension
195 mnemonics starting with @code{no} revoke the respective functionality.
197 When the @code{.arch} directive is used with @option{-march}, the
198 @code{.arch} directive will take precedent.
200 @cindex @samp{-mtune=} option, i386
201 @cindex @samp{-mtune=} option, x86-64
202 @item -mtune=@var{CPU}
203 This option specifies a processor to optimize for. When used in
204 conjunction with the @option{-march} option, only instructions
205 of the processor specified by the @option{-march} option will be
208 Valid @var{CPU} values are identical to the processor list of
209 @option{-march=@var{CPU}}.
211 @cindex @samp{-msse2avx} option, i386
212 @cindex @samp{-msse2avx} option, x86-64
214 This option specifies that the assembler should encode SSE instructions
217 @cindex @samp{-msse-check=} option, i386
218 @cindex @samp{-msse-check=} option, x86-64
219 @item -msse-check=@var{none}
220 @itemx -msse-check=@var{warning}
221 @itemx -msse-check=@var{error}
222 These options control if the assembler should check SSE instructions.
223 @option{-msse-check=@var{none}} will make the assembler not to check SSE
224 instructions, which is the default. @option{-msse-check=@var{warning}}
225 will make the assembler issue a warning for any SSE instruction.
226 @option{-msse-check=@var{error}} will make the assembler issue an error
227 for any SSE instruction.
229 @cindex @samp{-mavxscalar=} option, i386
230 @cindex @samp{-mavxscalar=} option, x86-64
231 @item -mavxscalar=@var{128}
232 @itemx -mavxscalar=@var{256}
233 These options control how the assembler should encode scalar AVX
234 instructions. @option{-mavxscalar=@var{128}} will encode scalar
235 AVX instructions with 128bit vector length, which is the default.
236 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
237 with 256bit vector length.
239 @cindex @samp{-mevexlig=} option, i386
240 @cindex @samp{-mevexlig=} option, x86-64
241 @item -mevexlig=@var{128}
242 @itemx -mevexlig=@var{256}
243 @itemx -mevexlig=@var{512}
244 These options control how the assembler should encode length-ignored
245 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
246 EVEX instructions with 128bit vector length, which is the default.
247 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
248 encode LIG EVEX instructions with 256bit and 512bit vector length,
251 @cindex @samp{-mevexwig=} option, i386
252 @cindex @samp{-mevexwig=} option, x86-64
253 @item -mevexwig=@var{0}
254 @itemx -mevexwig=@var{1}
255 These options control how the assembler should encode w-ignored (WIG)
256 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
257 EVEX instructions with evex.w = 0, which is the default.
258 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
261 @cindex @samp{-mmnemonic=} option, i386
262 @cindex @samp{-mmnemonic=} option, x86-64
263 @item -mmnemonic=@var{att}
264 @itemx -mmnemonic=@var{intel}
265 This option specifies instruction mnemonic for matching instructions.
266 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
269 @cindex @samp{-msyntax=} option, i386
270 @cindex @samp{-msyntax=} option, x86-64
271 @item -msyntax=@var{att}
272 @itemx -msyntax=@var{intel}
273 This option specifies instruction syntax when processing instructions.
274 The @code{.att_syntax} and @code{.intel_syntax} directives will
277 @cindex @samp{-mnaked-reg} option, i386
278 @cindex @samp{-mnaked-reg} option, x86-64
280 This opetion specifies that registers don't require a @samp{%} prefix.
281 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
283 @cindex @samp{-madd-bnd-prefix} option, i386
284 @cindex @samp{-madd-bnd-prefix} option, x86-64
285 @item -madd-bnd-prefix
286 This option forces the assembler to add BND prefix to all branches, even
287 if such prefix was not explicitly specified in the source code.
289 @cindex @samp{-mbig-obj} option, x86-64
291 On x86-64 PE/COFF target this option forces the use of big object file
292 format, which allows more than 32768 sections.
294 @cindex @samp{-momit-lock-prefix=} option, i386
295 @cindex @samp{-momit-lock-prefix=} option, x86-64
296 @item -momit-lock-prefix=@var{no}
297 @itemx -momit-lock-prefix=@var{yes}
298 These options control how the assembler should encode lock prefix.
299 This option is intended as a workaround for processors, that fail on
300 lock prefix. This option can only be safely used with single-core,
301 single-thread computers
302 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
303 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
304 which is the default.
309 @node i386-Directives
310 @section x86 specific Directives
312 @cindex machine directives, x86
313 @cindex x86 machine directives
316 @cindex @code{lcomm} directive, COFF
317 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
318 Reserve @var{length} (an absolute expression) bytes for a local common
319 denoted by @var{symbol}. The section and value of @var{symbol} are
320 those of the new local common. The addresses are allocated in the bss
321 section, so that at run-time the bytes start off zeroed. Since
322 @var{symbol} is not declared global, it is normally not visible to
323 @code{@value{LD}}. The optional third parameter, @var{alignment},
324 specifies the desired alignment of the symbol in the bss section.
326 This directive is only available for COFF based x86 targets.
328 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
334 @section i386 Syntactical Considerations
336 * i386-Variations:: AT&T Syntax versus Intel Syntax
337 * i386-Chars:: Special Characters
340 @node i386-Variations
341 @subsection AT&T Syntax versus Intel Syntax
343 @cindex i386 intel_syntax pseudo op
344 @cindex intel_syntax pseudo op, i386
345 @cindex i386 att_syntax pseudo op
346 @cindex att_syntax pseudo op, i386
347 @cindex i386 syntax compatibility
348 @cindex syntax compatibility, i386
349 @cindex x86-64 intel_syntax pseudo op
350 @cindex intel_syntax pseudo op, x86-64
351 @cindex x86-64 att_syntax pseudo op
352 @cindex att_syntax pseudo op, x86-64
353 @cindex x86-64 syntax compatibility
354 @cindex syntax compatibility, x86-64
356 @code{@value{AS}} now supports assembly using Intel assembler syntax.
357 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
358 back to the usual AT&T mode for compatibility with the output of
359 @code{@value{GCC}}. Either of these directives may have an optional
360 argument, @code{prefix}, or @code{noprefix} specifying whether registers
361 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
362 different from Intel syntax. We mention these differences because
363 almost all 80386 documents use Intel syntax. Notable differences
364 between the two syntaxes are:
366 @cindex immediate operands, i386
367 @cindex i386 immediate operands
368 @cindex register operands, i386
369 @cindex i386 register operands
370 @cindex jump/call operands, i386
371 @cindex i386 jump/call operands
372 @cindex operand delimiters, i386
374 @cindex immediate operands, x86-64
375 @cindex x86-64 immediate operands
376 @cindex register operands, x86-64
377 @cindex x86-64 register operands
378 @cindex jump/call operands, x86-64
379 @cindex x86-64 jump/call operands
380 @cindex operand delimiters, x86-64
383 AT&T immediate operands are preceded by @samp{$}; Intel immediate
384 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
385 AT&T register operands are preceded by @samp{%}; Intel register operands
386 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
387 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
389 @cindex i386 source, destination operands
390 @cindex source, destination operands; i386
391 @cindex x86-64 source, destination operands
392 @cindex source, destination operands; x86-64
394 AT&T and Intel syntax use the opposite order for source and destination
395 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
396 @samp{source, dest} convention is maintained for compatibility with
397 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
398 instructions with 2 immediate operands, such as the @samp{enter}
399 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
401 @cindex mnemonic suffixes, i386
402 @cindex sizes operands, i386
403 @cindex i386 size suffixes
404 @cindex mnemonic suffixes, x86-64
405 @cindex sizes operands, x86-64
406 @cindex x86-64 size suffixes
408 In AT&T syntax the size of memory operands is determined from the last
409 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
410 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
411 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
412 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
413 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
414 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
417 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
418 instruction with the 64-bit displacement or immediate operand.
420 @cindex return instructions, i386
421 @cindex i386 jump, call, return
422 @cindex return instructions, x86-64
423 @cindex x86-64 jump, call, return
425 Immediate form long jumps and calls are
426 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
428 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
430 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
431 @samp{ret far @var{stack-adjust}}.
433 @cindex sections, i386
434 @cindex i386 sections
435 @cindex sections, x86-64
436 @cindex x86-64 sections
438 The AT&T assembler does not provide support for multiple section
439 programs. Unix style systems expect all programs to be single sections.
443 @subsection Special Characters
445 @cindex line comment character, i386
446 @cindex i386 line comment character
447 The presence of a @samp{#} appearing anywhere on a line indicates the
448 start of a comment that extends to the end of that line.
450 If a @samp{#} appears as the first character of a line then the whole
451 line is treated as a comment, but in this case the line can also be a
452 logical line number directive (@pxref{Comments}) or a preprocessor
453 control command (@pxref{Preprocessing}).
455 If the @option{--divide} command line option has not been specified
456 then the @samp{/} character appearing anywhere on a line also
457 introduces a line comment.
459 @cindex line separator, i386
460 @cindex statement separator, i386
461 @cindex i386 line separator
462 The @samp{;} character can be used to separate statements on the same
466 @section Instruction Naming
468 @cindex i386 instruction naming
469 @cindex instruction naming, i386
470 @cindex x86-64 instruction naming
471 @cindex instruction naming, x86-64
473 Instruction mnemonics are suffixed with one character modifiers which
474 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
475 and @samp{q} specify byte, word, long and quadruple word operands. If
476 no suffix is specified by an instruction then @code{@value{AS}} tries to
477 fill in the missing suffix based on the destination register operand
478 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
479 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
480 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
481 assembler which assumes that a missing mnemonic suffix implies long
482 operand size. (This incompatibility does not affect compiler output
483 since compilers always explicitly specify the mnemonic suffix.)
485 Almost all instructions have the same names in AT&T and Intel format.
486 There are a few exceptions. The sign extend and zero extend
487 instructions need two sizes to specify them. They need a size to
488 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
489 is accomplished by using two instruction mnemonic suffixes in AT&T
490 syntax. Base names for sign extend and zero extend are
491 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
492 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
493 are tacked on to this base name, the @emph{from} suffix before the
494 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
495 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
496 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
497 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
498 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
501 @cindex encoding options, i386
502 @cindex encoding options, x86-64
504 Different encoding options can be specified via optional mnemonic
505 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
506 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
507 prefers 8bit or 32bit displacement in encoding.
509 @cindex conversion instructions, i386
510 @cindex i386 conversion instructions
511 @cindex conversion instructions, x86-64
512 @cindex x86-64 conversion instructions
513 The Intel-syntax conversion instructions
517 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
520 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
523 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
526 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
529 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
533 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
534 @samp{%rdx:%rax} (x86-64 only),
538 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
539 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
542 @cindex jump instructions, i386
543 @cindex call instructions, i386
544 @cindex jump instructions, x86-64
545 @cindex call instructions, x86-64
546 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
547 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
550 @section AT&T Mnemonic versus Intel Mnemonic
552 @cindex i386 mnemonic compatibility
553 @cindex mnemonic compatibility, i386
555 @code{@value{AS}} supports assembly using Intel mnemonic.
556 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
557 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
558 syntax for compatibility with the output of @code{@value{GCC}}.
559 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
560 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
561 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
562 assembler with different mnemonics from those in Intel IA32 specification.
563 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
566 @section Register Naming
568 @cindex i386 registers
569 @cindex registers, i386
570 @cindex x86-64 registers
571 @cindex registers, x86-64
572 Register operands are always prefixed with @samp{%}. The 80386 registers
577 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
578 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
579 frame pointer), and @samp{%esp} (the stack pointer).
582 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
583 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
586 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
587 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
588 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
589 @samp{%cx}, and @samp{%dx})
592 the 6 section registers @samp{%cs} (code section), @samp{%ds}
593 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
597 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
601 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
602 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
605 the 2 test registers @samp{%tr6} and @samp{%tr7}.
608 the 8 floating point register stack @samp{%st} or equivalently
609 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
610 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
611 These registers are overloaded by 8 MMX registers @samp{%mm0},
612 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
613 @samp{%mm6} and @samp{%mm7}.
616 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
617 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
620 The AMD x86-64 architecture extends the register set by:
624 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
625 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
626 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
630 the 8 extended registers @samp{%r8}--@samp{%r15}.
633 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
636 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
639 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
642 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
645 the 8 debug registers: @samp{%db8}--@samp{%db15}.
648 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
652 @section Instruction Prefixes
654 @cindex i386 instruction prefixes
655 @cindex instruction prefixes, i386
656 @cindex prefixes, i386
657 Instruction prefixes are used to modify the following instruction. They
658 are used to repeat string instructions, to provide section overrides, to
659 perform bus lock operations, and to change operand and address sizes.
660 (Most instructions that normally operate on 32-bit operands will use
661 16-bit operands if the instruction has an ``operand size'' prefix.)
662 Instruction prefixes are best written on the same line as the instruction
663 they act upon. For example, the @samp{scas} (scan string) instruction is
667 repne scas %es:(%edi),%al
670 You may also place prefixes on the lines immediately preceding the
671 instruction, but this circumvents checks that @code{@value{AS}} does
672 with prefixes, and will not work with all prefixes.
674 Here is a list of instruction prefixes:
676 @cindex section override prefixes, i386
679 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
680 @samp{fs}, @samp{gs}. These are automatically added by specifying
681 using the @var{section}:@var{memory-operand} form for memory references.
683 @cindex size prefixes, i386
685 Operand/Address size prefixes @samp{data16} and @samp{addr16}
686 change 32-bit operands/addresses into 16-bit operands/addresses,
687 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
688 @code{.code16} section) into 32-bit operands/addresses. These prefixes
689 @emph{must} appear on the same line of code as the instruction they
690 modify. For example, in a 16-bit @code{.code16} section, you might
697 @cindex bus lock prefixes, i386
698 @cindex inhibiting interrupts, i386
700 The bus lock prefix @samp{lock} inhibits interrupts during execution of
701 the instruction it precedes. (This is only valid with certain
702 instructions; see a 80386 manual for details).
704 @cindex coprocessor wait, i386
706 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
707 complete the current instruction. This should never be needed for the
708 80386/80387 combination.
710 @cindex repeat prefixes, i386
712 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
713 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
714 times if the current address size is 16-bits).
715 @cindex REX prefixes, i386
717 The @samp{rex} family of prefixes is used by x86-64 to encode
718 extensions to i386 instruction set. The @samp{rex} prefix has four
719 bits --- an operand size overwrite (@code{64}) used to change operand size
720 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
723 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
724 instruction emits @samp{rex} prefix with all the bits set. By omitting
725 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
726 prefixes as well. Normally, there is no need to write the prefixes
727 explicitly, since gas will automatically generate them based on the
728 instruction operands.
732 @section Memory References
734 @cindex i386 memory references
735 @cindex memory references, i386
736 @cindex x86-64 memory references
737 @cindex memory references, x86-64
738 An Intel syntax indirect memory reference of the form
741 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
745 is translated into the AT&T syntax
748 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
752 where @var{base} and @var{index} are the optional 32-bit base and
753 index registers, @var{disp} is the optional displacement, and
754 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
755 to calculate the address of the operand. If no @var{scale} is
756 specified, @var{scale} is taken to be 1. @var{section} specifies the
757 optional section register for the memory operand, and may override the
758 default section register (see a 80386 manual for section register
759 defaults). Note that section overrides in AT&T syntax @emph{must}
760 be preceded by a @samp{%}. If you specify a section override which
761 coincides with the default section register, @code{@value{AS}} does @emph{not}
762 output any section register override prefixes to assemble the given
763 instruction. Thus, section overrides can be specified to emphasize which
764 section register is used for a given memory operand.
766 Here are some examples of Intel and AT&T style memory references:
769 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
770 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
771 missing, and the default section is used (@samp{%ss} for addressing with
772 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
774 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
775 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
776 @samp{foo}. All other fields are missing. The section register here
777 defaults to @samp{%ds}.
779 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
780 This uses the value pointed to by @samp{foo} as a memory operand.
781 Note that @var{base} and @var{index} are both missing, but there is only
782 @emph{one} @samp{,}. This is a syntactic exception.
784 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
785 This selects the contents of the variable @samp{foo} with section
786 register @var{section} being @samp{%gs}.
789 Absolute (as opposed to PC relative) call and jump operands must be
790 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
791 always chooses PC relative addressing for jump/call labels.
793 Any instruction that has a memory operand, but no register operand,
794 @emph{must} specify its size (byte, word, long, or quadruple) with an
795 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
798 The x86-64 architecture adds an RIP (instruction pointer relative)
799 addressing. This addressing mode is specified by using @samp{rip} as a
800 base register. Only constant offsets are valid. For example:
803 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
804 Points to the address 1234 bytes past the end of the current
807 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
808 Points to the @code{symbol} in RIP relative way, this is shorter than
809 the default absolute addressing.
812 Other addressing modes remain unchanged in x86-64 architecture, except
813 registers used are 64-bit instead of 32-bit.
816 @section Handling of Jump Instructions
818 @cindex jump optimization, i386
819 @cindex i386 jump optimization
820 @cindex jump optimization, x86-64
821 @cindex x86-64 jump optimization
822 Jump instructions are always optimized to use the smallest possible
823 displacements. This is accomplished by using byte (8-bit) displacement
824 jumps whenever the target is sufficiently close. If a byte displacement
825 is insufficient a long displacement is used. We do not support
826 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
827 instruction with the @samp{data16} instruction prefix), since the 80386
828 insists upon masking @samp{%eip} to 16 bits after the word displacement
829 is added. (See also @pxref{i386-Arch})
831 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
832 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
833 displacements, so that if you use these instructions (@code{@value{GCC}} does
834 not use them) you may get an error message (and incorrect code). The AT&T
835 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
846 @section Floating Point
848 @cindex i386 floating point
849 @cindex floating point, i386
850 @cindex x86-64 floating point
851 @cindex floating point, x86-64
852 All 80387 floating point types except packed BCD are supported.
853 (BCD support may be added without much difficulty). These data
854 types are 16-, 32-, and 64- bit integers, and single (32-bit),
855 double (64-bit), and extended (80-bit) precision floating point.
856 Each supported type has an instruction mnemonic suffix and a constructor
857 associated with it. Instruction mnemonic suffixes specify the operand's
858 data type. Constructors build these data types into memory.
860 @cindex @code{float} directive, i386
861 @cindex @code{single} directive, i386
862 @cindex @code{double} directive, i386
863 @cindex @code{tfloat} directive, i386
864 @cindex @code{float} directive, x86-64
865 @cindex @code{single} directive, x86-64
866 @cindex @code{double} directive, x86-64
867 @cindex @code{tfloat} directive, x86-64
870 Floating point constructors are @samp{.float} or @samp{.single},
871 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
872 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
873 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
874 only supports this format via the @samp{fldt} (load 80-bit real to stack
875 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
877 @cindex @code{word} directive, i386
878 @cindex @code{long} directive, i386
879 @cindex @code{int} directive, i386
880 @cindex @code{quad} directive, i386
881 @cindex @code{word} directive, x86-64
882 @cindex @code{long} directive, x86-64
883 @cindex @code{int} directive, x86-64
884 @cindex @code{quad} directive, x86-64
886 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
887 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
888 corresponding instruction mnemonic suffixes are @samp{s} (single),
889 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
890 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
891 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
895 Register to register operations should not use instruction mnemonic suffixes.
896 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
897 wrote @samp{fst %st, %st(1)}, since all register to register operations
898 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
899 which converts @samp{%st} from 80-bit to 64-bit floating point format,
900 then stores the result in the 4 byte location @samp{mem})
903 @section Intel's MMX and AMD's 3DNow! SIMD Operations
909 @cindex 3DNow!, x86-64
912 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
913 instructions for integer data), available on Intel's Pentium MMX
914 processors and Pentium II processors, AMD's K6 and K6-2 processors,
915 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
916 instruction set (SIMD instructions for 32-bit floating point data)
917 available on AMD's K6-2 processor and possibly others in the future.
919 Currently, @code{@value{AS}} does not support Intel's floating point
922 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
923 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
924 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
925 floating point values. The MMX registers cannot be used at the same time
926 as the floating point stack.
928 See Intel and AMD documentation, keeping in mind that the operand order in
929 instructions is reversed from the Intel syntax.
932 @section AMD's Lightweight Profiling Instructions
937 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
938 instruction set, available on AMD's Family 15h (Orochi) processors.
940 LWP enables applications to collect and manage performance data, and
941 react to performance events. The collection of performance data
942 requires no context switches. LWP runs in the context of a thread and
943 so several counters can be used independently across multiple threads.
944 LWP can be used in both 64-bit and legacy 32-bit modes.
946 For detailed information on the LWP instruction set, see the
947 @cite{AMD Lightweight Profiling Specification} available at
948 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
951 @section Bit Manipulation Instructions
956 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
958 BMI instructions provide several instructions implementing individual
959 bit manipulation operations such as isolation, masking, setting, or
962 @c Need to add a specification citation here when available.
965 @section AMD's Trailing Bit Manipulation Instructions
970 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
971 instruction set, available on AMD's BDVER2 processors (Trinity and
974 TBM instructions provide instructions implementing individual bit
975 manipulation operations such as isolating, masking, setting, resetting,
976 complementing, and operations on trailing zeros and ones.
978 @c Need to add a specification citation here when available.
981 @section Writing 16-bit Code
983 @cindex i386 16-bit code
984 @cindex 16-bit code, i386
985 @cindex real-mode code, i386
986 @cindex @code{code16gcc} directive, i386
987 @cindex @code{code16} directive, i386
988 @cindex @code{code32} directive, i386
989 @cindex @code{code64} directive, i386
990 @cindex @code{code64} directive, x86-64
991 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
992 or 64-bit x86-64 code depending on the default configuration,
993 it also supports writing code to run in real mode or in 16-bit protected
994 mode code segments. To do this, put a @samp{.code16} or
995 @samp{.code16gcc} directive before the assembly language instructions to
996 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
997 32-bit code with the @samp{.code32} directive or 64-bit code with the
998 @samp{.code64} directive.
1000 @samp{.code16gcc} provides experimental support for generating 16-bit
1001 code from gcc, and differs from @samp{.code16} in that @samp{call},
1002 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1003 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1004 default to 32-bit size. This is so that the stack pointer is
1005 manipulated in the same way over function calls, allowing access to
1006 function parameters at the same stack offsets as in 32-bit mode.
1007 @samp{.code16gcc} also automatically adds address size prefixes where
1008 necessary to use the 32-bit addressing modes that gcc generates.
1010 The code which @code{@value{AS}} generates in 16-bit mode will not
1011 necessarily run on a 16-bit pre-80386 processor. To write code that
1012 runs on such a processor, you must refrain from using @emph{any} 32-bit
1013 constructs which require @code{@value{AS}} to output address or operand
1016 Note that writing 16-bit code instructions by explicitly specifying a
1017 prefix or an instruction mnemonic suffix within a 32-bit code section
1018 generates different machine instructions than those generated for a
1019 16-bit code segment. In a 32-bit code section, the following code
1020 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1021 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1027 The same code in a 16-bit code section would generate the machine
1028 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1029 is correct since the processor default operand size is assumed to be 16
1030 bits in a 16-bit code section.
1033 @section AT&T Syntax bugs
1035 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1036 assemblers, generate floating point instructions with reversed source
1037 and destination registers in certain cases. Unfortunately, gcc and
1038 possibly many other programs use this reversed syntax, so we're stuck
1047 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1048 than the expected @samp{%st(3) - %st}. This happens with all the
1049 non-commutative arithmetic floating point operations with two register
1050 operands where the source register is @samp{%st} and the destination
1051 register is @samp{%st(i)}.
1054 @section Specifying CPU Architecture
1056 @cindex arch directive, i386
1057 @cindex i386 arch directive
1058 @cindex arch directive, x86-64
1059 @cindex x86-64 arch directive
1061 @code{@value{AS}} may be told to assemble for a particular CPU
1062 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1063 directive enables a warning when gas detects an instruction that is not
1064 supported on the CPU specified. The choices for @var{cpu_type} are:
1066 @multitable @columnfractions .20 .20 .20 .20
1067 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1068 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1069 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1070 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1071 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1072 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1073 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1074 @item @samp{bdver4} @tab @samp{btver1} @tab @samp{btver2}
1075 @item @samp{generic32} @tab @samp{generic64}
1076 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1077 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1078 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1079 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1080 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1081 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1082 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1083 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1084 @item @samp{.smap} @tab @samp{.mpx}
1085 @item @samp{.smap} @tab @samp{.sha}
1086 @item @samp{.smap} @tab @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves}
1087 @item @samp{.smap} @tab @samp{.prefetchwt1}
1088 @item @samp{.smap} @tab @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq}
1089 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1090 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1091 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1092 @item @samp{.padlock}
1093 @item @samp{.smap} @tab @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er}
1094 @item @samp{.avx512pf} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a}
1095 @item @samp{.sse5} @tab @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1096 @item @samp{.abm} @tab @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
1097 @item @samp{.cx16} @tab @samp{.padlock}
1100 Apart from the warning, there are only two other effects on
1101 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1102 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1103 will automatically use a two byte opcode sequence. The larger three
1104 byte opcode sequence is used on the 486 (and when no architecture is
1105 specified) because it executes faster on the 486. Note that you can
1106 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1107 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1108 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1109 conditional jumps will be promoted when necessary to a two instruction
1110 sequence consisting of a conditional jump of the opposite sense around
1111 an unconditional jump to the target.
1113 Following the CPU architecture (but not a sub-architecture, which are those
1114 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1115 control automatic promotion of conditional jumps. @samp{jumps} is the
1116 default, and enables jump promotion; All external jumps will be of the long
1117 variety, and file-local jumps will be promoted as necessary.
1118 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1119 byte offset jumps, and warns about file-local conditional jumps that
1120 @code{@value{AS}} promotes.
1121 Unconditional jumps are treated as for @samp{jumps}.
1132 @cindex i386 @code{mul}, @code{imul} instructions
1133 @cindex @code{mul} instruction, i386
1134 @cindex @code{imul} instruction, i386
1135 @cindex @code{mul} instruction, x86-64
1136 @cindex @code{imul} instruction, x86-64
1137 There is some trickery concerning the @samp{mul} and @samp{imul}
1138 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1139 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1140 for @samp{imul}) can be output only in the one operand form. Thus,
1141 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1142 the expanding multiply would clobber the @samp{%edx} register, and this
1143 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1144 64-bit product in @samp{%edx:%eax}.
1146 We have added a two operand form of @samp{imul} when the first operand
1147 is an immediate mode expression and the second operand is a register.
1148 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1149 example, can be done with @samp{imul $69, %eax} rather than @samp{imul