1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: AT&T Syntax versus Intel Syntax
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-16bit:: Writing 16-bit Code
36 * i386-Arch:: Specifying an x86 CPU architecture
37 * i386-Bugs:: AT&T Syntax bugs
44 @cindex options for i386
45 @cindex options for x86-64
47 @cindex x86-64 options
49 The i386 version of @code{@value{AS}} has a few machine
53 @cindex @samp{--32} option, i386
54 @cindex @samp{--32} option, x86-64
55 @cindex @samp{--64} option, i386
56 @cindex @samp{--64} option, x86-64
58 Select the word size, either 32 bits or 64 bits. Selecting 32-bit
59 implies Intel i386 architecture, while 64-bit implies AMD x86-64
62 These options are only available with the ELF object file format, and
63 require that the necessary BFD support has been included (on a 32-bit
64 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
65 usage and use x86-64 as target platform).
68 By default, x86 GAS replaces multiple nop instructions used for
69 alignment within code sections with multi-byte nop instructions such
70 as leal 0(%esi,1),%esi. This switch disables the optimization.
72 @cindex @samp{--divide} option, i386
74 On SVR4-derived platforms, the character @samp{/} is treated as a comment
75 character, which means that it cannot be used in expressions. The
76 @samp{--divide} option turns @samp{/} into a normal character. This does
77 not disable @samp{/} at the beginning of a line starting a comment, or
78 affect using @samp{#} for starting a comment.
80 @cindex @samp{-march=} option, i386
81 @cindex @samp{-march=} option, x86-64
82 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
83 This option specifies the target processor. The assembler will
84 issue an error message if an attempt is made to assemble an instruction
85 which will not execute on the target processor. The following
86 processor names are recognized:
112 In addition to the basic instruction set, the assembler can be told to
113 accept various extension mnemonics. For example,
114 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
115 @var{vmx}. The following extensions are currently supported:
141 When the @code{.arch} directive is used with @option{-march}, the
142 @code{.arch} directive will take precedent.
144 @cindex @samp{-mtune=} option, i386
145 @cindex @samp{-mtune=} option, x86-64
146 @item -mtune=@var{CPU}
147 This option specifies a processor to optimize for. When used in
148 conjunction with the @option{-march} option, only instructions
149 of the processor specified by the @option{-march} option will be
152 Valid @var{CPU} values are identical to the processor list of
153 @option{-march=@var{CPU}}.
155 @cindex @samp{-msse2avx} option, i386
156 @cindex @samp{-msse2avx} option, x86-64
158 This option specifies that the assembler should encode SSE instructions
161 @cindex @samp{-msse-check=} option, i386
162 @cindex @samp{-msse-check=} option, x86-64
163 @item -msse-check=@var{none}
164 @item -msse-check=@var{warning}
165 @item -msse-check=@var{error}
166 These options control if the assembler should check SSE intructions.
167 @option{-msse-check=@var{none}} will make the assembler not to check SSE
168 instructions, which is the default. @option{-msse-check=@var{warning}}
169 will make the assembler issue a warning for any SSE intruction.
170 @option{-msse-check=@var{error}} will make the assembler issue an error
171 for any SSE intruction.
173 @cindex @samp{-mmnemonic=} option, i386
174 @cindex @samp{-mmnemonic=} option, x86-64
175 @item -mmnemonic=@var{att}
176 @item -mmnemonic=@var{intel}
177 This option specifies instruction mnemonic for matching instructions.
178 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
181 @cindex @samp{-msyntax=} option, i386
182 @cindex @samp{-msyntax=} option, x86-64
183 @item -msyntax=@var{att}
184 @item -msyntax=@var{intel}
185 This option specifies instruction syntax when processing instructions.
186 The @code{.att_syntax} and @code{.intel_syntax} directives will
189 @cindex @samp{-mnaked-reg} option, i386
190 @cindex @samp{-mnaked-reg} option, x86-64
192 This opetion specifies that registers don't require a @samp{%} prefix.
193 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
197 @node i386-Directives
198 @section x86 specific Directives
200 @cindex machine directives, x86
201 @cindex x86 machine directives
204 @cindex @code{lcomm} directive, COFF
205 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
206 Reserve @var{length} (an absolute expression) bytes for a local common
207 denoted by @var{symbol}. The section and value of @var{symbol} are
208 those of the new local common. The addresses are allocated in the bss
209 section, so that at run-time the bytes start off zeroed. Since
210 @var{symbol} is not declared global, it is normally not visible to
211 @code{@value{LD}}. The optional third parameter, @var{alignment},
212 specifies the desired alignment of the symbol in the bss section.
214 This directive is only available for COFF based x86 targets.
216 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
222 @section AT&T Syntax versus Intel Syntax
224 @cindex i386 intel_syntax pseudo op
225 @cindex intel_syntax pseudo op, i386
226 @cindex i386 att_syntax pseudo op
227 @cindex att_syntax pseudo op, i386
228 @cindex i386 syntax compatibility
229 @cindex syntax compatibility, i386
230 @cindex x86-64 intel_syntax pseudo op
231 @cindex intel_syntax pseudo op, x86-64
232 @cindex x86-64 att_syntax pseudo op
233 @cindex att_syntax pseudo op, x86-64
234 @cindex x86-64 syntax compatibility
235 @cindex syntax compatibility, x86-64
237 @code{@value{AS}} now supports assembly using Intel assembler syntax.
238 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
239 back to the usual AT&T mode for compatibility with the output of
240 @code{@value{GCC}}. Either of these directives may have an optional
241 argument, @code{prefix}, or @code{noprefix} specifying whether registers
242 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
243 different from Intel syntax. We mention these differences because
244 almost all 80386 documents use Intel syntax. Notable differences
245 between the two syntaxes are:
247 @cindex immediate operands, i386
248 @cindex i386 immediate operands
249 @cindex register operands, i386
250 @cindex i386 register operands
251 @cindex jump/call operands, i386
252 @cindex i386 jump/call operands
253 @cindex operand delimiters, i386
255 @cindex immediate operands, x86-64
256 @cindex x86-64 immediate operands
257 @cindex register operands, x86-64
258 @cindex x86-64 register operands
259 @cindex jump/call operands, x86-64
260 @cindex x86-64 jump/call operands
261 @cindex operand delimiters, x86-64
264 AT&T immediate operands are preceded by @samp{$}; Intel immediate
265 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
266 AT&T register operands are preceded by @samp{%}; Intel register operands
267 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
268 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
270 @cindex i386 source, destination operands
271 @cindex source, destination operands; i386
272 @cindex x86-64 source, destination operands
273 @cindex source, destination operands; x86-64
275 AT&T and Intel syntax use the opposite order for source and destination
276 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
277 @samp{source, dest} convention is maintained for compatibility with
278 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
279 instructions with 2 immediate operands, such as the @samp{enter}
280 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
282 @cindex mnemonic suffixes, i386
283 @cindex sizes operands, i386
284 @cindex i386 size suffixes
285 @cindex mnemonic suffixes, x86-64
286 @cindex sizes operands, x86-64
287 @cindex x86-64 size suffixes
289 In AT&T syntax the size of memory operands is determined from the last
290 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
291 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
292 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
293 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
294 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
295 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
298 @cindex return instructions, i386
299 @cindex i386 jump, call, return
300 @cindex return instructions, x86-64
301 @cindex x86-64 jump, call, return
303 Immediate form long jumps and calls are
304 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
306 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
308 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
309 @samp{ret far @var{stack-adjust}}.
311 @cindex sections, i386
312 @cindex i386 sections
313 @cindex sections, x86-64
314 @cindex x86-64 sections
316 The AT&T assembler does not provide support for multiple section
317 programs. Unix style systems expect all programs to be single sections.
321 @section Instruction Naming
323 @cindex i386 instruction naming
324 @cindex instruction naming, i386
325 @cindex x86-64 instruction naming
326 @cindex instruction naming, x86-64
328 Instruction mnemonics are suffixed with one character modifiers which
329 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
330 and @samp{q} specify byte, word, long and quadruple word operands. If
331 no suffix is specified by an instruction then @code{@value{AS}} tries to
332 fill in the missing suffix based on the destination register operand
333 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
334 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
335 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
336 assembler which assumes that a missing mnemonic suffix implies long
337 operand size. (This incompatibility does not affect compiler output
338 since compilers always explicitly specify the mnemonic suffix.)
340 Almost all instructions have the same names in AT&T and Intel format.
341 There are a few exceptions. The sign extend and zero extend
342 instructions need two sizes to specify them. They need a size to
343 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
344 is accomplished by using two instruction mnemonic suffixes in AT&T
345 syntax. Base names for sign extend and zero extend are
346 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
347 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
348 are tacked on to this base name, the @emph{from} suffix before the
349 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
350 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
351 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
352 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
353 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
356 @cindex encoding options, i386
357 @cindex encoding options, x86-64
359 Different encoding options can be specified via optional mnemonic
360 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
361 moving from one register to another.
363 @cindex conversion instructions, i386
364 @cindex i386 conversion instructions
365 @cindex conversion instructions, x86-64
366 @cindex x86-64 conversion instructions
367 The Intel-syntax conversion instructions
371 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
374 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
377 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
380 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
383 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
387 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
388 @samp{%rdx:%rax} (x86-64 only),
392 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
393 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
396 @cindex jump instructions, i386
397 @cindex call instructions, i386
398 @cindex jump instructions, x86-64
399 @cindex call instructions, x86-64
400 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
401 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
404 @section AT&T Mnemonic versus Intel Mnemonic
406 @cindex i386 mnemonic compatibility
407 @cindex mnemonic compatibility, i386
409 @code{@value{AS}} supports assembly using Intel mnemonic.
410 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
411 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
412 syntax for compatibility with the output of @code{@value{GCC}}.
413 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
414 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
415 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
416 assembler with different mnemonics from those in Intel IA32 specification.
417 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
420 @section Register Naming
422 @cindex i386 registers
423 @cindex registers, i386
424 @cindex x86-64 registers
425 @cindex registers, x86-64
426 Register operands are always prefixed with @samp{%}. The 80386 registers
431 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
432 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
433 frame pointer), and @samp{%esp} (the stack pointer).
436 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
437 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
440 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
441 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
442 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
443 @samp{%cx}, and @samp{%dx})
446 the 6 section registers @samp{%cs} (code section), @samp{%ds}
447 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
451 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
455 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
456 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
459 the 2 test registers @samp{%tr6} and @samp{%tr7}.
462 the 8 floating point register stack @samp{%st} or equivalently
463 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
464 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
465 These registers are overloaded by 8 MMX registers @samp{%mm0},
466 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
467 @samp{%mm6} and @samp{%mm7}.
470 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
471 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
474 The AMD x86-64 architecture extends the register set by:
478 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
479 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
480 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
484 the 8 extended registers @samp{%r8}--@samp{%r15}.
487 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
490 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
493 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
496 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
499 the 8 debug registers: @samp{%db8}--@samp{%db15}.
502 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
506 @section Instruction Prefixes
508 @cindex i386 instruction prefixes
509 @cindex instruction prefixes, i386
510 @cindex prefixes, i386
511 Instruction prefixes are used to modify the following instruction. They
512 are used to repeat string instructions, to provide section overrides, to
513 perform bus lock operations, and to change operand and address sizes.
514 (Most instructions that normally operate on 32-bit operands will use
515 16-bit operands if the instruction has an ``operand size'' prefix.)
516 Instruction prefixes are best written on the same line as the instruction
517 they act upon. For example, the @samp{scas} (scan string) instruction is
521 repne scas %es:(%edi),%al
524 You may also place prefixes on the lines immediately preceding the
525 instruction, but this circumvents checks that @code{@value{AS}} does
526 with prefixes, and will not work with all prefixes.
528 Here is a list of instruction prefixes:
530 @cindex section override prefixes, i386
533 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
534 @samp{fs}, @samp{gs}. These are automatically added by specifying
535 using the @var{section}:@var{memory-operand} form for memory references.
537 @cindex size prefixes, i386
539 Operand/Address size prefixes @samp{data16} and @samp{addr16}
540 change 32-bit operands/addresses into 16-bit operands/addresses,
541 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
542 @code{.code16} section) into 32-bit operands/addresses. These prefixes
543 @emph{must} appear on the same line of code as the instruction they
544 modify. For example, in a 16-bit @code{.code16} section, you might
551 @cindex bus lock prefixes, i386
552 @cindex inhibiting interrupts, i386
554 The bus lock prefix @samp{lock} inhibits interrupts during execution of
555 the instruction it precedes. (This is only valid with certain
556 instructions; see a 80386 manual for details).
558 @cindex coprocessor wait, i386
560 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
561 complete the current instruction. This should never be needed for the
562 80386/80387 combination.
564 @cindex repeat prefixes, i386
566 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
567 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
568 times if the current address size is 16-bits).
569 @cindex REX prefixes, i386
571 The @samp{rex} family of prefixes is used by x86-64 to encode
572 extensions to i386 instruction set. The @samp{rex} prefix has four
573 bits --- an operand size overwrite (@code{64}) used to change operand size
574 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
577 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
578 instruction emits @samp{rex} prefix with all the bits set. By omitting
579 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
580 prefixes as well. Normally, there is no need to write the prefixes
581 explicitly, since gas will automatically generate them based on the
582 instruction operands.
586 @section Memory References
588 @cindex i386 memory references
589 @cindex memory references, i386
590 @cindex x86-64 memory references
591 @cindex memory references, x86-64
592 An Intel syntax indirect memory reference of the form
595 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
599 is translated into the AT&T syntax
602 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
606 where @var{base} and @var{index} are the optional 32-bit base and
607 index registers, @var{disp} is the optional displacement, and
608 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
609 to calculate the address of the operand. If no @var{scale} is
610 specified, @var{scale} is taken to be 1. @var{section} specifies the
611 optional section register for the memory operand, and may override the
612 default section register (see a 80386 manual for section register
613 defaults). Note that section overrides in AT&T syntax @emph{must}
614 be preceded by a @samp{%}. If you specify a section override which
615 coincides with the default section register, @code{@value{AS}} does @emph{not}
616 output any section register override prefixes to assemble the given
617 instruction. Thus, section overrides can be specified to emphasize which
618 section register is used for a given memory operand.
620 Here are some examples of Intel and AT&T style memory references:
623 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
624 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
625 missing, and the default section is used (@samp{%ss} for addressing with
626 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
628 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
629 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
630 @samp{foo}. All other fields are missing. The section register here
631 defaults to @samp{%ds}.
633 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
634 This uses the value pointed to by @samp{foo} as a memory operand.
635 Note that @var{base} and @var{index} are both missing, but there is only
636 @emph{one} @samp{,}. This is a syntactic exception.
638 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
639 This selects the contents of the variable @samp{foo} with section
640 register @var{section} being @samp{%gs}.
643 Absolute (as opposed to PC relative) call and jump operands must be
644 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
645 always chooses PC relative addressing for jump/call labels.
647 Any instruction that has a memory operand, but no register operand,
648 @emph{must} specify its size (byte, word, long, or quadruple) with an
649 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
652 The x86-64 architecture adds an RIP (instruction pointer relative)
653 addressing. This addressing mode is specified by using @samp{rip} as a
654 base register. Only constant offsets are valid. For example:
657 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
658 Points to the address 1234 bytes past the end of the current
661 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
662 Points to the @code{symbol} in RIP relative way, this is shorter than
663 the default absolute addressing.
666 Other addressing modes remain unchanged in x86-64 architecture, except
667 registers used are 64-bit instead of 32-bit.
670 @section Handling of Jump Instructions
672 @cindex jump optimization, i386
673 @cindex i386 jump optimization
674 @cindex jump optimization, x86-64
675 @cindex x86-64 jump optimization
676 Jump instructions are always optimized to use the smallest possible
677 displacements. This is accomplished by using byte (8-bit) displacement
678 jumps whenever the target is sufficiently close. If a byte displacement
679 is insufficient a long displacement is used. We do not support
680 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
681 instruction with the @samp{data16} instruction prefix), since the 80386
682 insists upon masking @samp{%eip} to 16 bits after the word displacement
683 is added. (See also @pxref{i386-Arch})
685 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
686 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
687 displacements, so that if you use these instructions (@code{@value{GCC}} does
688 not use them) you may get an error message (and incorrect code). The AT&T
689 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
700 @section Floating Point
702 @cindex i386 floating point
703 @cindex floating point, i386
704 @cindex x86-64 floating point
705 @cindex floating point, x86-64
706 All 80387 floating point types except packed BCD are supported.
707 (BCD support may be added without much difficulty). These data
708 types are 16-, 32-, and 64- bit integers, and single (32-bit),
709 double (64-bit), and extended (80-bit) precision floating point.
710 Each supported type has an instruction mnemonic suffix and a constructor
711 associated with it. Instruction mnemonic suffixes specify the operand's
712 data type. Constructors build these data types into memory.
714 @cindex @code{float} directive, i386
715 @cindex @code{single} directive, i386
716 @cindex @code{double} directive, i386
717 @cindex @code{tfloat} directive, i386
718 @cindex @code{float} directive, x86-64
719 @cindex @code{single} directive, x86-64
720 @cindex @code{double} directive, x86-64
721 @cindex @code{tfloat} directive, x86-64
724 Floating point constructors are @samp{.float} or @samp{.single},
725 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
726 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
727 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
728 only supports this format via the @samp{fldt} (load 80-bit real to stack
729 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
731 @cindex @code{word} directive, i386
732 @cindex @code{long} directive, i386
733 @cindex @code{int} directive, i386
734 @cindex @code{quad} directive, i386
735 @cindex @code{word} directive, x86-64
736 @cindex @code{long} directive, x86-64
737 @cindex @code{int} directive, x86-64
738 @cindex @code{quad} directive, x86-64
740 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
741 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
742 corresponding instruction mnemonic suffixes are @samp{s} (single),
743 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
744 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
745 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
749 Register to register operations should not use instruction mnemonic suffixes.
750 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
751 wrote @samp{fst %st, %st(1)}, since all register to register operations
752 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
753 which converts @samp{%st} from 80-bit to 64-bit floating point format,
754 then stores the result in the 4 byte location @samp{mem})
757 @section Intel's MMX and AMD's 3DNow! SIMD Operations
763 @cindex 3DNow!, x86-64
766 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
767 instructions for integer data), available on Intel's Pentium MMX
768 processors and Pentium II processors, AMD's K6 and K6-2 processors,
769 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
770 instruction set (SIMD instructions for 32-bit floating point data)
771 available on AMD's K6-2 processor and possibly others in the future.
773 Currently, @code{@value{AS}} does not support Intel's floating point
776 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
777 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
778 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
779 floating point values. The MMX registers cannot be used at the same time
780 as the floating point stack.
782 See Intel and AMD documentation, keeping in mind that the operand order in
783 instructions is reversed from the Intel syntax.
786 @section Writing 16-bit Code
788 @cindex i386 16-bit code
789 @cindex 16-bit code, i386
790 @cindex real-mode code, i386
791 @cindex @code{code16gcc} directive, i386
792 @cindex @code{code16} directive, i386
793 @cindex @code{code32} directive, i386
794 @cindex @code{code64} directive, i386
795 @cindex @code{code64} directive, x86-64
796 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
797 or 64-bit x86-64 code depending on the default configuration,
798 it also supports writing code to run in real mode or in 16-bit protected
799 mode code segments. To do this, put a @samp{.code16} or
800 @samp{.code16gcc} directive before the assembly language instructions to
801 be run in 16-bit mode. You can switch @code{@value{AS}} back to writing
802 normal 32-bit code with the @samp{.code32} directive.
804 @samp{.code16gcc} provides experimental support for generating 16-bit
805 code from gcc, and differs from @samp{.code16} in that @samp{call},
806 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
807 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
808 default to 32-bit size. This is so that the stack pointer is
809 manipulated in the same way over function calls, allowing access to
810 function parameters at the same stack offsets as in 32-bit mode.
811 @samp{.code16gcc} also automatically adds address size prefixes where
812 necessary to use the 32-bit addressing modes that gcc generates.
814 The code which @code{@value{AS}} generates in 16-bit mode will not
815 necessarily run on a 16-bit pre-80386 processor. To write code that
816 runs on such a processor, you must refrain from using @emph{any} 32-bit
817 constructs which require @code{@value{AS}} to output address or operand
820 Note that writing 16-bit code instructions by explicitly specifying a
821 prefix or an instruction mnemonic suffix within a 32-bit code section
822 generates different machine instructions than those generated for a
823 16-bit code segment. In a 32-bit code section, the following code
824 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
825 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
831 The same code in a 16-bit code section would generate the machine
832 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
833 is correct since the processor default operand size is assumed to be 16
834 bits in a 16-bit code section.
837 @section AT&T Syntax bugs
839 The UnixWare assembler, and probably other AT&T derived ix86 Unix
840 assemblers, generate floating point instructions with reversed source
841 and destination registers in certain cases. Unfortunately, gcc and
842 possibly many other programs use this reversed syntax, so we're stuck
851 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
852 than the expected @samp{%st(3) - %st}. This happens with all the
853 non-commutative arithmetic floating point operations with two register
854 operands where the source register is @samp{%st} and the destination
855 register is @samp{%st(i)}.
858 @section Specifying CPU Architecture
860 @cindex arch directive, i386
861 @cindex i386 arch directive
862 @cindex arch directive, x86-64
863 @cindex x86-64 arch directive
865 @code{@value{AS}} may be told to assemble for a particular CPU
866 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
867 directive enables a warning when gas detects an instruction that is not
868 supported on the CPU specified. The choices for @var{cpu_type} are:
870 @multitable @columnfractions .20 .20 .20 .20
871 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
872 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
873 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
874 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
875 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
876 @item @samp{amdfam10}
877 @item @samp{generic32} @tab @samp{generic64}
878 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
879 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
880 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
881 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe}
883 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
884 @item @samp{.svme} @tab @samp{.abm}
885 @item @samp{.padlock}
888 Apart from the warning, there are only two other effects on
889 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
890 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
891 will automatically use a two byte opcode sequence. The larger three
892 byte opcode sequence is used on the 486 (and when no architecture is
893 specified) because it executes faster on the 486. Note that you can
894 explicitly request the two byte opcode by writing @samp{sarl %eax}.
895 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
896 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
897 conditional jumps will be promoted when necessary to a two instruction
898 sequence consisting of a conditional jump of the opposite sense around
899 an unconditional jump to the target.
901 Following the CPU architecture (but not a sub-architecture, which are those
902 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
903 control automatic promotion of conditional jumps. @samp{jumps} is the
904 default, and enables jump promotion; All external jumps will be of the long
905 variety, and file-local jumps will be promoted as necessary.
906 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
907 byte offset jumps, and warns about file-local conditional jumps that
908 @code{@value{AS}} promotes.
909 Unconditional jumps are treated as for @samp{jumps}.
920 @cindex i386 @code{mul}, @code{imul} instructions
921 @cindex @code{mul} instruction, i386
922 @cindex @code{imul} instruction, i386
923 @cindex @code{mul} instruction, x86-64
924 @cindex @code{imul} instruction, x86-64
925 There is some trickery concerning the @samp{mul} and @samp{imul}
926 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
927 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
928 for @samp{imul}) can be output only in the one operand form. Thus,
929 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
930 the expanding multiply would clobber the @samp{%edx} register, and this
931 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
932 64-bit product in @samp{%edx:%eax}.
934 We have added a two operand form of @samp{imul} when the first operand
935 is an immediate mode expression and the second operand is a register.
936 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
937 example, can be done with @samp{imul $69, %eax} rather than @samp{imul