1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
128 In addition to the basic instruction set, the assembler can be told to
129 accept various extension mnemonics. For example,
130 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
131 @var{vmx}. The following extensions are currently supported:
193 Note that rather than extending a basic instruction set, the extension
194 mnemonics starting with @code{no} revoke the respective functionality.
196 When the @code{.arch} directive is used with @option{-march}, the
197 @code{.arch} directive will take precedent.
199 @cindex @samp{-mtune=} option, i386
200 @cindex @samp{-mtune=} option, x86-64
201 @item -mtune=@var{CPU}
202 This option specifies a processor to optimize for. When used in
203 conjunction with the @option{-march} option, only instructions
204 of the processor specified by the @option{-march} option will be
207 Valid @var{CPU} values are identical to the processor list of
208 @option{-march=@var{CPU}}.
210 @cindex @samp{-msse2avx} option, i386
211 @cindex @samp{-msse2avx} option, x86-64
213 This option specifies that the assembler should encode SSE instructions
216 @cindex @samp{-msse-check=} option, i386
217 @cindex @samp{-msse-check=} option, x86-64
218 @item -msse-check=@var{none}
219 @itemx -msse-check=@var{warning}
220 @itemx -msse-check=@var{error}
221 These options control if the assembler should check SSE instructions.
222 @option{-msse-check=@var{none}} will make the assembler not to check SSE
223 instructions, which is the default. @option{-msse-check=@var{warning}}
224 will make the assembler issue a warning for any SSE instruction.
225 @option{-msse-check=@var{error}} will make the assembler issue an error
226 for any SSE instruction.
228 @cindex @samp{-mavxscalar=} option, i386
229 @cindex @samp{-mavxscalar=} option, x86-64
230 @item -mavxscalar=@var{128}
231 @itemx -mavxscalar=@var{256}
232 These options control how the assembler should encode scalar AVX
233 instructions. @option{-mavxscalar=@var{128}} will encode scalar
234 AVX instructions with 128bit vector length, which is the default.
235 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
236 with 256bit vector length.
238 @cindex @samp{-mevexlig=} option, i386
239 @cindex @samp{-mevexlig=} option, x86-64
240 @item -mevexlig=@var{128}
241 @itemx -mevexlig=@var{256}
242 @itemx -mevexlig=@var{512}
243 These options control how the assembler should encode length-ignored
244 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
245 EVEX instructions with 128bit vector length, which is the default.
246 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
247 encode LIG EVEX instructions with 256bit and 512bit vector length,
250 @cindex @samp{-mevexwig=} option, i386
251 @cindex @samp{-mevexwig=} option, x86-64
252 @item -mevexwig=@var{0}
253 @itemx -mevexwig=@var{1}
254 These options control how the assembler should encode w-ignored (WIG)
255 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
256 EVEX instructions with evex.w = 0, which is the default.
257 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
260 @cindex @samp{-mmnemonic=} option, i386
261 @cindex @samp{-mmnemonic=} option, x86-64
262 @item -mmnemonic=@var{att}
263 @itemx -mmnemonic=@var{intel}
264 This option specifies instruction mnemonic for matching instructions.
265 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
268 @cindex @samp{-msyntax=} option, i386
269 @cindex @samp{-msyntax=} option, x86-64
270 @item -msyntax=@var{att}
271 @itemx -msyntax=@var{intel}
272 This option specifies instruction syntax when processing instructions.
273 The @code{.att_syntax} and @code{.intel_syntax} directives will
276 @cindex @samp{-mnaked-reg} option, i386
277 @cindex @samp{-mnaked-reg} option, x86-64
279 This opetion specifies that registers don't require a @samp{%} prefix.
280 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
282 @cindex @samp{-madd-bnd-prefix} option, i386
283 @cindex @samp{-madd-bnd-prefix} option, x86-64
284 @item -madd-bnd-prefix
285 This option forces the assembler to add BND prefix to all branches, even
286 if such prefix was not explicitly specified in the source code.
288 @cindex @samp{-mbig-obj} option, x86-64
290 On x86-64 PE/COFF target this option forces the use of big object file
291 format, which allows more than 32768 sections.
296 @node i386-Directives
297 @section x86 specific Directives
299 @cindex machine directives, x86
300 @cindex x86 machine directives
303 @cindex @code{lcomm} directive, COFF
304 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
305 Reserve @var{length} (an absolute expression) bytes for a local common
306 denoted by @var{symbol}. The section and value of @var{symbol} are
307 those of the new local common. The addresses are allocated in the bss
308 section, so that at run-time the bytes start off zeroed. Since
309 @var{symbol} is not declared global, it is normally not visible to
310 @code{@value{LD}}. The optional third parameter, @var{alignment},
311 specifies the desired alignment of the symbol in the bss section.
313 This directive is only available for COFF based x86 targets.
315 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
321 @section i386 Syntactical Considerations
323 * i386-Variations:: AT&T Syntax versus Intel Syntax
324 * i386-Chars:: Special Characters
327 @node i386-Variations
328 @subsection AT&T Syntax versus Intel Syntax
330 @cindex i386 intel_syntax pseudo op
331 @cindex intel_syntax pseudo op, i386
332 @cindex i386 att_syntax pseudo op
333 @cindex att_syntax pseudo op, i386
334 @cindex i386 syntax compatibility
335 @cindex syntax compatibility, i386
336 @cindex x86-64 intel_syntax pseudo op
337 @cindex intel_syntax pseudo op, x86-64
338 @cindex x86-64 att_syntax pseudo op
339 @cindex att_syntax pseudo op, x86-64
340 @cindex x86-64 syntax compatibility
341 @cindex syntax compatibility, x86-64
343 @code{@value{AS}} now supports assembly using Intel assembler syntax.
344 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
345 back to the usual AT&T mode for compatibility with the output of
346 @code{@value{GCC}}. Either of these directives may have an optional
347 argument, @code{prefix}, or @code{noprefix} specifying whether registers
348 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
349 different from Intel syntax. We mention these differences because
350 almost all 80386 documents use Intel syntax. Notable differences
351 between the two syntaxes are:
353 @cindex immediate operands, i386
354 @cindex i386 immediate operands
355 @cindex register operands, i386
356 @cindex i386 register operands
357 @cindex jump/call operands, i386
358 @cindex i386 jump/call operands
359 @cindex operand delimiters, i386
361 @cindex immediate operands, x86-64
362 @cindex x86-64 immediate operands
363 @cindex register operands, x86-64
364 @cindex x86-64 register operands
365 @cindex jump/call operands, x86-64
366 @cindex x86-64 jump/call operands
367 @cindex operand delimiters, x86-64
370 AT&T immediate operands are preceded by @samp{$}; Intel immediate
371 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
372 AT&T register operands are preceded by @samp{%}; Intel register operands
373 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
374 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
376 @cindex i386 source, destination operands
377 @cindex source, destination operands; i386
378 @cindex x86-64 source, destination operands
379 @cindex source, destination operands; x86-64
381 AT&T and Intel syntax use the opposite order for source and destination
382 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
383 @samp{source, dest} convention is maintained for compatibility with
384 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
385 instructions with 2 immediate operands, such as the @samp{enter}
386 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
388 @cindex mnemonic suffixes, i386
389 @cindex sizes operands, i386
390 @cindex i386 size suffixes
391 @cindex mnemonic suffixes, x86-64
392 @cindex sizes operands, x86-64
393 @cindex x86-64 size suffixes
395 In AT&T syntax the size of memory operands is determined from the last
396 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
397 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
398 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
399 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
400 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
401 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
404 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
405 instruction with the 64-bit displacement or immediate operand.
407 @cindex return instructions, i386
408 @cindex i386 jump, call, return
409 @cindex return instructions, x86-64
410 @cindex x86-64 jump, call, return
412 Immediate form long jumps and calls are
413 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
415 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
417 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
418 @samp{ret far @var{stack-adjust}}.
420 @cindex sections, i386
421 @cindex i386 sections
422 @cindex sections, x86-64
423 @cindex x86-64 sections
425 The AT&T assembler does not provide support for multiple section
426 programs. Unix style systems expect all programs to be single sections.
430 @subsection Special Characters
432 @cindex line comment character, i386
433 @cindex i386 line comment character
434 The presence of a @samp{#} appearing anywhere on a line indicates the
435 start of a comment that extends to the end of that line.
437 If a @samp{#} appears as the first character of a line then the whole
438 line is treated as a comment, but in this case the line can also be a
439 logical line number directive (@pxref{Comments}) or a preprocessor
440 control command (@pxref{Preprocessing}).
442 If the @option{--divide} command line option has not been specified
443 then the @samp{/} character appearing anywhere on a line also
444 introduces a line comment.
446 @cindex line separator, i386
447 @cindex statement separator, i386
448 @cindex i386 line separator
449 The @samp{;} character can be used to separate statements on the same
453 @section Instruction Naming
455 @cindex i386 instruction naming
456 @cindex instruction naming, i386
457 @cindex x86-64 instruction naming
458 @cindex instruction naming, x86-64
460 Instruction mnemonics are suffixed with one character modifiers which
461 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
462 and @samp{q} specify byte, word, long and quadruple word operands. If
463 no suffix is specified by an instruction then @code{@value{AS}} tries to
464 fill in the missing suffix based on the destination register operand
465 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
466 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
467 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
468 assembler which assumes that a missing mnemonic suffix implies long
469 operand size. (This incompatibility does not affect compiler output
470 since compilers always explicitly specify the mnemonic suffix.)
472 Almost all instructions have the same names in AT&T and Intel format.
473 There are a few exceptions. The sign extend and zero extend
474 instructions need two sizes to specify them. They need a size to
475 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
476 is accomplished by using two instruction mnemonic suffixes in AT&T
477 syntax. Base names for sign extend and zero extend are
478 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
479 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
480 are tacked on to this base name, the @emph{from} suffix before the
481 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
482 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
483 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
484 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
485 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
488 @cindex encoding options, i386
489 @cindex encoding options, x86-64
491 Different encoding options can be specified via optional mnemonic
492 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
493 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
494 prefers 8bit or 32bit displacement in encoding.
496 @cindex conversion instructions, i386
497 @cindex i386 conversion instructions
498 @cindex conversion instructions, x86-64
499 @cindex x86-64 conversion instructions
500 The Intel-syntax conversion instructions
504 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
507 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
510 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
513 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
516 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
520 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
521 @samp{%rdx:%rax} (x86-64 only),
525 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
526 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
529 @cindex jump instructions, i386
530 @cindex call instructions, i386
531 @cindex jump instructions, x86-64
532 @cindex call instructions, x86-64
533 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
534 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
537 @section AT&T Mnemonic versus Intel Mnemonic
539 @cindex i386 mnemonic compatibility
540 @cindex mnemonic compatibility, i386
542 @code{@value{AS}} supports assembly using Intel mnemonic.
543 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
544 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
545 syntax for compatibility with the output of @code{@value{GCC}}.
546 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
547 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
548 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
549 assembler with different mnemonics from those in Intel IA32 specification.
550 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
553 @section Register Naming
555 @cindex i386 registers
556 @cindex registers, i386
557 @cindex x86-64 registers
558 @cindex registers, x86-64
559 Register operands are always prefixed with @samp{%}. The 80386 registers
564 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
565 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
566 frame pointer), and @samp{%esp} (the stack pointer).
569 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
570 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
573 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
574 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
575 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
576 @samp{%cx}, and @samp{%dx})
579 the 6 section registers @samp{%cs} (code section), @samp{%ds}
580 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
584 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
588 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
589 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
592 the 2 test registers @samp{%tr6} and @samp{%tr7}.
595 the 8 floating point register stack @samp{%st} or equivalently
596 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
597 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
598 These registers are overloaded by 8 MMX registers @samp{%mm0},
599 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
600 @samp{%mm6} and @samp{%mm7}.
603 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
604 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
607 The AMD x86-64 architecture extends the register set by:
611 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
612 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
613 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
617 the 8 extended registers @samp{%r8}--@samp{%r15}.
620 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
623 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
626 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
629 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
632 the 8 debug registers: @samp{%db8}--@samp{%db15}.
635 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
639 @section Instruction Prefixes
641 @cindex i386 instruction prefixes
642 @cindex instruction prefixes, i386
643 @cindex prefixes, i386
644 Instruction prefixes are used to modify the following instruction. They
645 are used to repeat string instructions, to provide section overrides, to
646 perform bus lock operations, and to change operand and address sizes.
647 (Most instructions that normally operate on 32-bit operands will use
648 16-bit operands if the instruction has an ``operand size'' prefix.)
649 Instruction prefixes are best written on the same line as the instruction
650 they act upon. For example, the @samp{scas} (scan string) instruction is
654 repne scas %es:(%edi),%al
657 You may also place prefixes on the lines immediately preceding the
658 instruction, but this circumvents checks that @code{@value{AS}} does
659 with prefixes, and will not work with all prefixes.
661 Here is a list of instruction prefixes:
663 @cindex section override prefixes, i386
666 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
667 @samp{fs}, @samp{gs}. These are automatically added by specifying
668 using the @var{section}:@var{memory-operand} form for memory references.
670 @cindex size prefixes, i386
672 Operand/Address size prefixes @samp{data16} and @samp{addr16}
673 change 32-bit operands/addresses into 16-bit operands/addresses,
674 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
675 @code{.code16} section) into 32-bit operands/addresses. These prefixes
676 @emph{must} appear on the same line of code as the instruction they
677 modify. For example, in a 16-bit @code{.code16} section, you might
684 @cindex bus lock prefixes, i386
685 @cindex inhibiting interrupts, i386
687 The bus lock prefix @samp{lock} inhibits interrupts during execution of
688 the instruction it precedes. (This is only valid with certain
689 instructions; see a 80386 manual for details).
691 @cindex coprocessor wait, i386
693 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
694 complete the current instruction. This should never be needed for the
695 80386/80387 combination.
697 @cindex repeat prefixes, i386
699 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
700 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
701 times if the current address size is 16-bits).
702 @cindex REX prefixes, i386
704 The @samp{rex} family of prefixes is used by x86-64 to encode
705 extensions to i386 instruction set. The @samp{rex} prefix has four
706 bits --- an operand size overwrite (@code{64}) used to change operand size
707 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
710 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
711 instruction emits @samp{rex} prefix with all the bits set. By omitting
712 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
713 prefixes as well. Normally, there is no need to write the prefixes
714 explicitly, since gas will automatically generate them based on the
715 instruction operands.
719 @section Memory References
721 @cindex i386 memory references
722 @cindex memory references, i386
723 @cindex x86-64 memory references
724 @cindex memory references, x86-64
725 An Intel syntax indirect memory reference of the form
728 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
732 is translated into the AT&T syntax
735 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
739 where @var{base} and @var{index} are the optional 32-bit base and
740 index registers, @var{disp} is the optional displacement, and
741 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
742 to calculate the address of the operand. If no @var{scale} is
743 specified, @var{scale} is taken to be 1. @var{section} specifies the
744 optional section register for the memory operand, and may override the
745 default section register (see a 80386 manual for section register
746 defaults). Note that section overrides in AT&T syntax @emph{must}
747 be preceded by a @samp{%}. If you specify a section override which
748 coincides with the default section register, @code{@value{AS}} does @emph{not}
749 output any section register override prefixes to assemble the given
750 instruction. Thus, section overrides can be specified to emphasize which
751 section register is used for a given memory operand.
753 Here are some examples of Intel and AT&T style memory references:
756 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
757 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
758 missing, and the default section is used (@samp{%ss} for addressing with
759 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
761 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
762 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
763 @samp{foo}. All other fields are missing. The section register here
764 defaults to @samp{%ds}.
766 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
767 This uses the value pointed to by @samp{foo} as a memory operand.
768 Note that @var{base} and @var{index} are both missing, but there is only
769 @emph{one} @samp{,}. This is a syntactic exception.
771 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
772 This selects the contents of the variable @samp{foo} with section
773 register @var{section} being @samp{%gs}.
776 Absolute (as opposed to PC relative) call and jump operands must be
777 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
778 always chooses PC relative addressing for jump/call labels.
780 Any instruction that has a memory operand, but no register operand,
781 @emph{must} specify its size (byte, word, long, or quadruple) with an
782 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
785 The x86-64 architecture adds an RIP (instruction pointer relative)
786 addressing. This addressing mode is specified by using @samp{rip} as a
787 base register. Only constant offsets are valid. For example:
790 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
791 Points to the address 1234 bytes past the end of the current
794 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
795 Points to the @code{symbol} in RIP relative way, this is shorter than
796 the default absolute addressing.
799 Other addressing modes remain unchanged in x86-64 architecture, except
800 registers used are 64-bit instead of 32-bit.
803 @section Handling of Jump Instructions
805 @cindex jump optimization, i386
806 @cindex i386 jump optimization
807 @cindex jump optimization, x86-64
808 @cindex x86-64 jump optimization
809 Jump instructions are always optimized to use the smallest possible
810 displacements. This is accomplished by using byte (8-bit) displacement
811 jumps whenever the target is sufficiently close. If a byte displacement
812 is insufficient a long displacement is used. We do not support
813 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
814 instruction with the @samp{data16} instruction prefix), since the 80386
815 insists upon masking @samp{%eip} to 16 bits after the word displacement
816 is added. (See also @pxref{i386-Arch})
818 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
819 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
820 displacements, so that if you use these instructions (@code{@value{GCC}} does
821 not use them) you may get an error message (and incorrect code). The AT&T
822 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
833 @section Floating Point
835 @cindex i386 floating point
836 @cindex floating point, i386
837 @cindex x86-64 floating point
838 @cindex floating point, x86-64
839 All 80387 floating point types except packed BCD are supported.
840 (BCD support may be added without much difficulty). These data
841 types are 16-, 32-, and 64- bit integers, and single (32-bit),
842 double (64-bit), and extended (80-bit) precision floating point.
843 Each supported type has an instruction mnemonic suffix and a constructor
844 associated with it. Instruction mnemonic suffixes specify the operand's
845 data type. Constructors build these data types into memory.
847 @cindex @code{float} directive, i386
848 @cindex @code{single} directive, i386
849 @cindex @code{double} directive, i386
850 @cindex @code{tfloat} directive, i386
851 @cindex @code{float} directive, x86-64
852 @cindex @code{single} directive, x86-64
853 @cindex @code{double} directive, x86-64
854 @cindex @code{tfloat} directive, x86-64
857 Floating point constructors are @samp{.float} or @samp{.single},
858 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
859 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
860 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
861 only supports this format via the @samp{fldt} (load 80-bit real to stack
862 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
864 @cindex @code{word} directive, i386
865 @cindex @code{long} directive, i386
866 @cindex @code{int} directive, i386
867 @cindex @code{quad} directive, i386
868 @cindex @code{word} directive, x86-64
869 @cindex @code{long} directive, x86-64
870 @cindex @code{int} directive, x86-64
871 @cindex @code{quad} directive, x86-64
873 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
874 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
875 corresponding instruction mnemonic suffixes are @samp{s} (single),
876 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
877 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
878 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
882 Register to register operations should not use instruction mnemonic suffixes.
883 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
884 wrote @samp{fst %st, %st(1)}, since all register to register operations
885 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
886 which converts @samp{%st} from 80-bit to 64-bit floating point format,
887 then stores the result in the 4 byte location @samp{mem})
890 @section Intel's MMX and AMD's 3DNow! SIMD Operations
896 @cindex 3DNow!, x86-64
899 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
900 instructions for integer data), available on Intel's Pentium MMX
901 processors and Pentium II processors, AMD's K6 and K6-2 processors,
902 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
903 instruction set (SIMD instructions for 32-bit floating point data)
904 available on AMD's K6-2 processor and possibly others in the future.
906 Currently, @code{@value{AS}} does not support Intel's floating point
909 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
910 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
911 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
912 floating point values. The MMX registers cannot be used at the same time
913 as the floating point stack.
915 See Intel and AMD documentation, keeping in mind that the operand order in
916 instructions is reversed from the Intel syntax.
919 @section AMD's Lightweight Profiling Instructions
924 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
925 instruction set, available on AMD's Family 15h (Orochi) processors.
927 LWP enables applications to collect and manage performance data, and
928 react to performance events. The collection of performance data
929 requires no context switches. LWP runs in the context of a thread and
930 so several counters can be used independently across multiple threads.
931 LWP can be used in both 64-bit and legacy 32-bit modes.
933 For detailed information on the LWP instruction set, see the
934 @cite{AMD Lightweight Profiling Specification} available at
935 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
938 @section Bit Manipulation Instructions
943 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
945 BMI instructions provide several instructions implementing individual
946 bit manipulation operations such as isolation, masking, setting, or
949 @c Need to add a specification citation here when available.
952 @section AMD's Trailing Bit Manipulation Instructions
957 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
958 instruction set, available on AMD's BDVER2 processors (Trinity and
961 TBM instructions provide instructions implementing individual bit
962 manipulation operations such as isolating, masking, setting, resetting,
963 complementing, and operations on trailing zeros and ones.
965 @c Need to add a specification citation here when available.
968 @section Writing 16-bit Code
970 @cindex i386 16-bit code
971 @cindex 16-bit code, i386
972 @cindex real-mode code, i386
973 @cindex @code{code16gcc} directive, i386
974 @cindex @code{code16} directive, i386
975 @cindex @code{code32} directive, i386
976 @cindex @code{code64} directive, i386
977 @cindex @code{code64} directive, x86-64
978 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
979 or 64-bit x86-64 code depending on the default configuration,
980 it also supports writing code to run in real mode or in 16-bit protected
981 mode code segments. To do this, put a @samp{.code16} or
982 @samp{.code16gcc} directive before the assembly language instructions to
983 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
984 32-bit code with the @samp{.code32} directive or 64-bit code with the
985 @samp{.code64} directive.
987 @samp{.code16gcc} provides experimental support for generating 16-bit
988 code from gcc, and differs from @samp{.code16} in that @samp{call},
989 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
990 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
991 default to 32-bit size. This is so that the stack pointer is
992 manipulated in the same way over function calls, allowing access to
993 function parameters at the same stack offsets as in 32-bit mode.
994 @samp{.code16gcc} also automatically adds address size prefixes where
995 necessary to use the 32-bit addressing modes that gcc generates.
997 The code which @code{@value{AS}} generates in 16-bit mode will not
998 necessarily run on a 16-bit pre-80386 processor. To write code that
999 runs on such a processor, you must refrain from using @emph{any} 32-bit
1000 constructs which require @code{@value{AS}} to output address or operand
1003 Note that writing 16-bit code instructions by explicitly specifying a
1004 prefix or an instruction mnemonic suffix within a 32-bit code section
1005 generates different machine instructions than those generated for a
1006 16-bit code segment. In a 32-bit code section, the following code
1007 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1008 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1014 The same code in a 16-bit code section would generate the machine
1015 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1016 is correct since the processor default operand size is assumed to be 16
1017 bits in a 16-bit code section.
1020 @section AT&T Syntax bugs
1022 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1023 assemblers, generate floating point instructions with reversed source
1024 and destination registers in certain cases. Unfortunately, gcc and
1025 possibly many other programs use this reversed syntax, so we're stuck
1034 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1035 than the expected @samp{%st(3) - %st}. This happens with all the
1036 non-commutative arithmetic floating point operations with two register
1037 operands where the source register is @samp{%st} and the destination
1038 register is @samp{%st(i)}.
1041 @section Specifying CPU Architecture
1043 @cindex arch directive, i386
1044 @cindex i386 arch directive
1045 @cindex arch directive, x86-64
1046 @cindex x86-64 arch directive
1048 @code{@value{AS}} may be told to assemble for a particular CPU
1049 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1050 directive enables a warning when gas detects an instruction that is not
1051 supported on the CPU specified. The choices for @var{cpu_type} are:
1053 @multitable @columnfractions .20 .20 .20 .20
1054 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1055 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1056 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1057 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1058 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1059 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1060 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1061 @item @samp{bdver4} @tab @samp{btver1} @tab @samp{btver2}
1062 @item @samp{generic32} @tab @samp{generic64}
1063 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1064 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1065 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1066 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1067 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1068 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1069 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1070 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1071 @item @samp{.smap} @tab @samp{.mpx}
1072 @item @samp{.smap} @tab @samp{.sha}
1073 @item @samp{.smap} @tab @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves}
1074 @item @samp{.smap} @tab @samp{.prefetchwt1}
1075 @item @samp{.smap} @tab @samp{.avx512vl} @tab @samp{.avx512bw}
1076 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1077 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1078 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1079 @item @samp{.padlock}
1080 @item @samp{.smap} @tab @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er}
1081 @item @samp{.avx512pf} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a}
1082 @item @samp{.sse5} @tab @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1083 @item @samp{.abm} @tab @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
1084 @item @samp{.cx16} @tab @samp{.padlock}
1087 Apart from the warning, there are only two other effects on
1088 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1089 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1090 will automatically use a two byte opcode sequence. The larger three
1091 byte opcode sequence is used on the 486 (and when no architecture is
1092 specified) because it executes faster on the 486. Note that you can
1093 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1094 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1095 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1096 conditional jumps will be promoted when necessary to a two instruction
1097 sequence consisting of a conditional jump of the opposite sense around
1098 an unconditional jump to the target.
1100 Following the CPU architecture (but not a sub-architecture, which are those
1101 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1102 control automatic promotion of conditional jumps. @samp{jumps} is the
1103 default, and enables jump promotion; All external jumps will be of the long
1104 variety, and file-local jumps will be promoted as necessary.
1105 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1106 byte offset jumps, and warns about file-local conditional jumps that
1107 @code{@value{AS}} promotes.
1108 Unconditional jumps are treated as for @samp{jumps}.
1119 @cindex i386 @code{mul}, @code{imul} instructions
1120 @cindex @code{mul} instruction, i386
1121 @cindex @code{imul} instruction, i386
1122 @cindex @code{mul} instruction, x86-64
1123 @cindex @code{imul} instruction, x86-64
1124 There is some trickery concerning the @samp{mul} and @samp{imul}
1125 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1126 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1127 for @samp{imul}) can be output only in the one operand form. Thus,
1128 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1129 the expanding multiply would clobber the @samp{%edx} register, and this
1130 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1131 64-bit product in @samp{%edx:%eax}.
1133 We have added a two operand form of @samp{imul} when the first operand
1134 is an immediate mode expression and the second operand is a register.
1135 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1136 example, can be done with @samp{imul $69, %eax} rather than @samp{imul