1 @c Copyright (C) 1991-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
130 In addition to the basic instruction set, the assembler can be told to
131 accept various extension mnemonics. For example,
132 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
133 @var{vmx}. The following extensions are currently supported:
183 @code{avx512_4fmaps},
184 @code{avx512_4vnniw},
194 @code{noavx512_4fmaps},
195 @code{noavx512_4vnniw},
232 Note that rather than extending a basic instruction set, the extension
233 mnemonics starting with @code{no} revoke the respective functionality.
235 When the @code{.arch} directive is used with @option{-march}, the
236 @code{.arch} directive will take precedent.
238 @cindex @samp{-mtune=} option, i386
239 @cindex @samp{-mtune=} option, x86-64
240 @item -mtune=@var{CPU}
241 This option specifies a processor to optimize for. When used in
242 conjunction with the @option{-march} option, only instructions
243 of the processor specified by the @option{-march} option will be
246 Valid @var{CPU} values are identical to the processor list of
247 @option{-march=@var{CPU}}.
249 @cindex @samp{-msse2avx} option, i386
250 @cindex @samp{-msse2avx} option, x86-64
252 This option specifies that the assembler should encode SSE instructions
255 @cindex @samp{-msse-check=} option, i386
256 @cindex @samp{-msse-check=} option, x86-64
257 @item -msse-check=@var{none}
258 @itemx -msse-check=@var{warning}
259 @itemx -msse-check=@var{error}
260 These options control if the assembler should check SSE instructions.
261 @option{-msse-check=@var{none}} will make the assembler not to check SSE
262 instructions, which is the default. @option{-msse-check=@var{warning}}
263 will make the assembler issue a warning for any SSE instruction.
264 @option{-msse-check=@var{error}} will make the assembler issue an error
265 for any SSE instruction.
267 @cindex @samp{-mavxscalar=} option, i386
268 @cindex @samp{-mavxscalar=} option, x86-64
269 @item -mavxscalar=@var{128}
270 @itemx -mavxscalar=@var{256}
271 These options control how the assembler should encode scalar AVX
272 instructions. @option{-mavxscalar=@var{128}} will encode scalar
273 AVX instructions with 128bit vector length, which is the default.
274 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
275 with 256bit vector length.
277 @cindex @samp{-mevexlig=} option, i386
278 @cindex @samp{-mevexlig=} option, x86-64
279 @item -mevexlig=@var{128}
280 @itemx -mevexlig=@var{256}
281 @itemx -mevexlig=@var{512}
282 These options control how the assembler should encode length-ignored
283 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
284 EVEX instructions with 128bit vector length, which is the default.
285 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
286 encode LIG EVEX instructions with 256bit and 512bit vector length,
289 @cindex @samp{-mevexwig=} option, i386
290 @cindex @samp{-mevexwig=} option, x86-64
291 @item -mevexwig=@var{0}
292 @itemx -mevexwig=@var{1}
293 These options control how the assembler should encode w-ignored (WIG)
294 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
295 EVEX instructions with evex.w = 0, which is the default.
296 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
299 @cindex @samp{-mmnemonic=} option, i386
300 @cindex @samp{-mmnemonic=} option, x86-64
301 @item -mmnemonic=@var{att}
302 @itemx -mmnemonic=@var{intel}
303 This option specifies instruction mnemonic for matching instructions.
304 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
307 @cindex @samp{-msyntax=} option, i386
308 @cindex @samp{-msyntax=} option, x86-64
309 @item -msyntax=@var{att}
310 @itemx -msyntax=@var{intel}
311 This option specifies instruction syntax when processing instructions.
312 The @code{.att_syntax} and @code{.intel_syntax} directives will
315 @cindex @samp{-mnaked-reg} option, i386
316 @cindex @samp{-mnaked-reg} option, x86-64
318 This opetion specifies that registers don't require a @samp{%} prefix.
319 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
321 @cindex @samp{-madd-bnd-prefix} option, i386
322 @cindex @samp{-madd-bnd-prefix} option, x86-64
323 @item -madd-bnd-prefix
324 This option forces the assembler to add BND prefix to all branches, even
325 if such prefix was not explicitly specified in the source code.
327 @cindex @samp{-mshared} option, i386
328 @cindex @samp{-mshared} option, x86-64
330 On ELF target, the assembler normally optimizes out non-PLT relocations
331 against defined non-weak global branch targets with default visibility.
332 The @samp{-mshared} option tells the assembler to generate code which
333 may go into a shared library where all non-weak global branch targets
334 with default visibility can be preempted. The resulting code is
335 slightly bigger. This option only affects the handling of branch
338 @cindex @samp{-mbig-obj} option, x86-64
340 On x86-64 PE/COFF target this option forces the use of big object file
341 format, which allows more than 32768 sections.
343 @cindex @samp{-momit-lock-prefix=} option, i386
344 @cindex @samp{-momit-lock-prefix=} option, x86-64
345 @item -momit-lock-prefix=@var{no}
346 @itemx -momit-lock-prefix=@var{yes}
347 These options control how the assembler should encode lock prefix.
348 This option is intended as a workaround for processors, that fail on
349 lock prefix. This option can only be safely used with single-core,
350 single-thread computers
351 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
352 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
353 which is the default.
355 @cindex @samp{-mfence-as-lock-add=} option, i386
356 @cindex @samp{-mfence-as-lock-add=} option, x86-64
357 @item -mfence-as-lock-add=@var{no}
358 @itemx -mfence-as-lock-add=@var{yes}
359 These options control how the assembler should encode lfence, mfence and
361 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
362 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
363 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
364 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
365 sfence as usual, which is the default.
367 @cindex @samp{-mrelax-relocations=} option, i386
368 @cindex @samp{-mrelax-relocations=} option, x86-64
369 @item -mrelax-relocations=@var{no}
370 @itemx -mrelax-relocations=@var{yes}
371 These options control whether the assembler should generate relax
372 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
373 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
374 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
375 @option{-mrelax-relocations=@var{no}} will not generate relax
376 relocations. The default can be controlled by a configure option
377 @option{--enable-x86-relax-relocations}.
379 @cindex @samp{-mevexrcig=} option, i386
380 @cindex @samp{-mevexrcig=} option, x86-64
381 @item -mevexrcig=@var{rne}
382 @itemx -mevexrcig=@var{rd}
383 @itemx -mevexrcig=@var{ru}
384 @itemx -mevexrcig=@var{rz}
385 These options control how the assembler should encode SAE-only
386 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
387 of EVEX instruction with 00, which is the default.
388 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
389 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
390 with 01, 10 and 11 RC bits, respectively.
392 @cindex @samp{-mamd64} option, x86-64
393 @cindex @samp{-mintel64} option, x86-64
396 This option specifies that the assembler should accept only AMD64 or
397 Intel64 ISA in 64-bit mode. The default is to accept both.
402 @node i386-Directives
403 @section x86 specific Directives
405 @cindex machine directives, x86
406 @cindex x86 machine directives
409 @cindex @code{lcomm} directive, COFF
410 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
411 Reserve @var{length} (an absolute expression) bytes for a local common
412 denoted by @var{symbol}. The section and value of @var{symbol} are
413 those of the new local common. The addresses are allocated in the bss
414 section, so that at run-time the bytes start off zeroed. Since
415 @var{symbol} is not declared global, it is normally not visible to
416 @code{@value{LD}}. The optional third parameter, @var{alignment},
417 specifies the desired alignment of the symbol in the bss section.
419 This directive is only available for COFF based x86 targets.
421 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
427 @section i386 Syntactical Considerations
429 * i386-Variations:: AT&T Syntax versus Intel Syntax
430 * i386-Chars:: Special Characters
433 @node i386-Variations
434 @subsection AT&T Syntax versus Intel Syntax
436 @cindex i386 intel_syntax pseudo op
437 @cindex intel_syntax pseudo op, i386
438 @cindex i386 att_syntax pseudo op
439 @cindex att_syntax pseudo op, i386
440 @cindex i386 syntax compatibility
441 @cindex syntax compatibility, i386
442 @cindex x86-64 intel_syntax pseudo op
443 @cindex intel_syntax pseudo op, x86-64
444 @cindex x86-64 att_syntax pseudo op
445 @cindex att_syntax pseudo op, x86-64
446 @cindex x86-64 syntax compatibility
447 @cindex syntax compatibility, x86-64
449 @code{@value{AS}} now supports assembly using Intel assembler syntax.
450 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
451 back to the usual AT&T mode for compatibility with the output of
452 @code{@value{GCC}}. Either of these directives may have an optional
453 argument, @code{prefix}, or @code{noprefix} specifying whether registers
454 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
455 different from Intel syntax. We mention these differences because
456 almost all 80386 documents use Intel syntax. Notable differences
457 between the two syntaxes are:
459 @cindex immediate operands, i386
460 @cindex i386 immediate operands
461 @cindex register operands, i386
462 @cindex i386 register operands
463 @cindex jump/call operands, i386
464 @cindex i386 jump/call operands
465 @cindex operand delimiters, i386
467 @cindex immediate operands, x86-64
468 @cindex x86-64 immediate operands
469 @cindex register operands, x86-64
470 @cindex x86-64 register operands
471 @cindex jump/call operands, x86-64
472 @cindex x86-64 jump/call operands
473 @cindex operand delimiters, x86-64
476 AT&T immediate operands are preceded by @samp{$}; Intel immediate
477 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
478 AT&T register operands are preceded by @samp{%}; Intel register operands
479 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
480 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
482 @cindex i386 source, destination operands
483 @cindex source, destination operands; i386
484 @cindex x86-64 source, destination operands
485 @cindex source, destination operands; x86-64
487 AT&T and Intel syntax use the opposite order for source and destination
488 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
489 @samp{source, dest} convention is maintained for compatibility with
490 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
491 instructions with 2 immediate operands, such as the @samp{enter}
492 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
494 @cindex mnemonic suffixes, i386
495 @cindex sizes operands, i386
496 @cindex i386 size suffixes
497 @cindex mnemonic suffixes, x86-64
498 @cindex sizes operands, x86-64
499 @cindex x86-64 size suffixes
501 In AT&T syntax the size of memory operands is determined from the last
502 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
503 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
504 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
505 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
506 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
507 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
510 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
511 instruction with the 64-bit displacement or immediate operand.
513 @cindex return instructions, i386
514 @cindex i386 jump, call, return
515 @cindex return instructions, x86-64
516 @cindex x86-64 jump, call, return
518 Immediate form long jumps and calls are
519 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
521 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
523 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
524 @samp{ret far @var{stack-adjust}}.
526 @cindex sections, i386
527 @cindex i386 sections
528 @cindex sections, x86-64
529 @cindex x86-64 sections
531 The AT&T assembler does not provide support for multiple section
532 programs. Unix style systems expect all programs to be single sections.
536 @subsection Special Characters
538 @cindex line comment character, i386
539 @cindex i386 line comment character
540 The presence of a @samp{#} appearing anywhere on a line indicates the
541 start of a comment that extends to the end of that line.
543 If a @samp{#} appears as the first character of a line then the whole
544 line is treated as a comment, but in this case the line can also be a
545 logical line number directive (@pxref{Comments}) or a preprocessor
546 control command (@pxref{Preprocessing}).
548 If the @option{--divide} command line option has not been specified
549 then the @samp{/} character appearing anywhere on a line also
550 introduces a line comment.
552 @cindex line separator, i386
553 @cindex statement separator, i386
554 @cindex i386 line separator
555 The @samp{;} character can be used to separate statements on the same
559 @section i386-Mnemonics
560 @subsection Instruction Naming
562 @cindex i386 instruction naming
563 @cindex instruction naming, i386
564 @cindex x86-64 instruction naming
565 @cindex instruction naming, x86-64
567 Instruction mnemonics are suffixed with one character modifiers which
568 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
569 and @samp{q} specify byte, word, long and quadruple word operands. If
570 no suffix is specified by an instruction then @code{@value{AS}} tries to
571 fill in the missing suffix based on the destination register operand
572 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
573 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
574 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
575 assembler which assumes that a missing mnemonic suffix implies long
576 operand size. (This incompatibility does not affect compiler output
577 since compilers always explicitly specify the mnemonic suffix.)
579 Almost all instructions have the same names in AT&T and Intel format.
580 There are a few exceptions. The sign extend and zero extend
581 instructions need two sizes to specify them. They need a size to
582 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
583 is accomplished by using two instruction mnemonic suffixes in AT&T
584 syntax. Base names for sign extend and zero extend are
585 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
586 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
587 are tacked on to this base name, the @emph{from} suffix before the
588 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
589 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
590 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
591 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
592 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
595 @cindex encoding options, i386
596 @cindex encoding options, x86-64
598 Different encoding options can be specified via optional mnemonic
599 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
600 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
601 prefers 8bit or 32bit displacement in encoding.
603 @cindex conversion instructions, i386
604 @cindex i386 conversion instructions
605 @cindex conversion instructions, x86-64
606 @cindex x86-64 conversion instructions
607 The Intel-syntax conversion instructions
611 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
614 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
617 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
620 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
623 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
627 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
628 @samp{%rdx:%rax} (x86-64 only),
632 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
633 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
636 @cindex jump instructions, i386
637 @cindex call instructions, i386
638 @cindex jump instructions, x86-64
639 @cindex call instructions, x86-64
640 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
641 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
644 @subsection AT&T Mnemonic versus Intel Mnemonic
646 @cindex i386 mnemonic compatibility
647 @cindex mnemonic compatibility, i386
649 @code{@value{AS}} supports assembly using Intel mnemonic.
650 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
651 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
652 syntax for compatibility with the output of @code{@value{GCC}}.
653 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
654 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
655 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
656 assembler with different mnemonics from those in Intel IA32 specification.
657 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
660 @section Register Naming
662 @cindex i386 registers
663 @cindex registers, i386
664 @cindex x86-64 registers
665 @cindex registers, x86-64
666 Register operands are always prefixed with @samp{%}. The 80386 registers
671 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
672 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
673 frame pointer), and @samp{%esp} (the stack pointer).
676 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
677 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
680 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
681 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
682 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
683 @samp{%cx}, and @samp{%dx})
686 the 6 section registers @samp{%cs} (code section), @samp{%ds}
687 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
691 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
692 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
695 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
696 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
699 the 2 test registers @samp{%tr6} and @samp{%tr7}.
702 the 8 floating point register stack @samp{%st} or equivalently
703 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
704 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
705 These registers are overloaded by 8 MMX registers @samp{%mm0},
706 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
707 @samp{%mm6} and @samp{%mm7}.
710 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
711 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
714 The AMD x86-64 architecture extends the register set by:
718 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
719 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
720 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
724 the 8 extended registers @samp{%r8}--@samp{%r15}.
727 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
730 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
733 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
736 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
739 the 8 debug registers: @samp{%db8}--@samp{%db15}.
742 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
745 With the AVX extensions more registers were made available:
750 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
751 available in 32-bit mode). The bottom 128 bits are overlaid with the
752 @samp{xmm0}--@samp{xmm15} registers.
756 The AVX2 extensions made in 64-bit mode more registers available:
761 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
762 registers @samp{%ymm16}--@samp{%ymm31}.
766 The AVX512 extensions added the following registers:
771 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
772 available in 32-bit mode). The bottom 128 bits are overlaid with the
773 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
774 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
777 the 8 mask registers @samp{%k0}--@samp{%k7}.
782 @section Instruction Prefixes
784 @cindex i386 instruction prefixes
785 @cindex instruction prefixes, i386
786 @cindex prefixes, i386
787 Instruction prefixes are used to modify the following instruction. They
788 are used to repeat string instructions, to provide section overrides, to
789 perform bus lock operations, and to change operand and address sizes.
790 (Most instructions that normally operate on 32-bit operands will use
791 16-bit operands if the instruction has an ``operand size'' prefix.)
792 Instruction prefixes are best written on the same line as the instruction
793 they act upon. For example, the @samp{scas} (scan string) instruction is
797 repne scas %es:(%edi),%al
800 You may also place prefixes on the lines immediately preceding the
801 instruction, but this circumvents checks that @code{@value{AS}} does
802 with prefixes, and will not work with all prefixes.
804 Here is a list of instruction prefixes:
806 @cindex section override prefixes, i386
809 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
810 @samp{fs}, @samp{gs}. These are automatically added by specifying
811 using the @var{section}:@var{memory-operand} form for memory references.
813 @cindex size prefixes, i386
815 Operand/Address size prefixes @samp{data16} and @samp{addr16}
816 change 32-bit operands/addresses into 16-bit operands/addresses,
817 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
818 @code{.code16} section) into 32-bit operands/addresses. These prefixes
819 @emph{must} appear on the same line of code as the instruction they
820 modify. For example, in a 16-bit @code{.code16} section, you might
827 @cindex bus lock prefixes, i386
828 @cindex inhibiting interrupts, i386
830 The bus lock prefix @samp{lock} inhibits interrupts during execution of
831 the instruction it precedes. (This is only valid with certain
832 instructions; see a 80386 manual for details).
834 @cindex coprocessor wait, i386
836 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
837 complete the current instruction. This should never be needed for the
838 80386/80387 combination.
840 @cindex repeat prefixes, i386
842 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
843 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
844 times if the current address size is 16-bits).
845 @cindex REX prefixes, i386
847 The @samp{rex} family of prefixes is used by x86-64 to encode
848 extensions to i386 instruction set. The @samp{rex} prefix has four
849 bits --- an operand size overwrite (@code{64}) used to change operand size
850 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
853 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
854 instruction emits @samp{rex} prefix with all the bits set. By omitting
855 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
856 prefixes as well. Normally, there is no need to write the prefixes
857 explicitly, since gas will automatically generate them based on the
858 instruction operands.
862 @section Memory References
864 @cindex i386 memory references
865 @cindex memory references, i386
866 @cindex x86-64 memory references
867 @cindex memory references, x86-64
868 An Intel syntax indirect memory reference of the form
871 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
875 is translated into the AT&T syntax
878 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
882 where @var{base} and @var{index} are the optional 32-bit base and
883 index registers, @var{disp} is the optional displacement, and
884 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
885 to calculate the address of the operand. If no @var{scale} is
886 specified, @var{scale} is taken to be 1. @var{section} specifies the
887 optional section register for the memory operand, and may override the
888 default section register (see a 80386 manual for section register
889 defaults). Note that section overrides in AT&T syntax @emph{must}
890 be preceded by a @samp{%}. If you specify a section override which
891 coincides with the default section register, @code{@value{AS}} does @emph{not}
892 output any section register override prefixes to assemble the given
893 instruction. Thus, section overrides can be specified to emphasize which
894 section register is used for a given memory operand.
896 Here are some examples of Intel and AT&T style memory references:
899 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
900 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
901 missing, and the default section is used (@samp{%ss} for addressing with
902 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
904 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
905 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
906 @samp{foo}. All other fields are missing. The section register here
907 defaults to @samp{%ds}.
909 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
910 This uses the value pointed to by @samp{foo} as a memory operand.
911 Note that @var{base} and @var{index} are both missing, but there is only
912 @emph{one} @samp{,}. This is a syntactic exception.
914 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
915 This selects the contents of the variable @samp{foo} with section
916 register @var{section} being @samp{%gs}.
919 Absolute (as opposed to PC relative) call and jump operands must be
920 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
921 always chooses PC relative addressing for jump/call labels.
923 Any instruction that has a memory operand, but no register operand,
924 @emph{must} specify its size (byte, word, long, or quadruple) with an
925 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
928 The x86-64 architecture adds an RIP (instruction pointer relative)
929 addressing. This addressing mode is specified by using @samp{rip} as a
930 base register. Only constant offsets are valid. For example:
933 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
934 Points to the address 1234 bytes past the end of the current
937 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
938 Points to the @code{symbol} in RIP relative way, this is shorter than
939 the default absolute addressing.
942 Other addressing modes remain unchanged in x86-64 architecture, except
943 registers used are 64-bit instead of 32-bit.
946 @section Handling of Jump Instructions
948 @cindex jump optimization, i386
949 @cindex i386 jump optimization
950 @cindex jump optimization, x86-64
951 @cindex x86-64 jump optimization
952 Jump instructions are always optimized to use the smallest possible
953 displacements. This is accomplished by using byte (8-bit) displacement
954 jumps whenever the target is sufficiently close. If a byte displacement
955 is insufficient a long displacement is used. We do not support
956 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
957 instruction with the @samp{data16} instruction prefix), since the 80386
958 insists upon masking @samp{%eip} to 16 bits after the word displacement
959 is added. (See also @pxref{i386-Arch})
961 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
962 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
963 displacements, so that if you use these instructions (@code{@value{GCC}} does
964 not use them) you may get an error message (and incorrect code). The AT&T
965 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
976 @section Floating Point
978 @cindex i386 floating point
979 @cindex floating point, i386
980 @cindex x86-64 floating point
981 @cindex floating point, x86-64
982 All 80387 floating point types except packed BCD are supported.
983 (BCD support may be added without much difficulty). These data
984 types are 16-, 32-, and 64- bit integers, and single (32-bit),
985 double (64-bit), and extended (80-bit) precision floating point.
986 Each supported type has an instruction mnemonic suffix and a constructor
987 associated with it. Instruction mnemonic suffixes specify the operand's
988 data type. Constructors build these data types into memory.
990 @cindex @code{float} directive, i386
991 @cindex @code{single} directive, i386
992 @cindex @code{double} directive, i386
993 @cindex @code{tfloat} directive, i386
994 @cindex @code{float} directive, x86-64
995 @cindex @code{single} directive, x86-64
996 @cindex @code{double} directive, x86-64
997 @cindex @code{tfloat} directive, x86-64
1000 Floating point constructors are @samp{.float} or @samp{.single},
1001 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1002 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1003 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1004 only supports this format via the @samp{fldt} (load 80-bit real to stack
1005 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1007 @cindex @code{word} directive, i386
1008 @cindex @code{long} directive, i386
1009 @cindex @code{int} directive, i386
1010 @cindex @code{quad} directive, i386
1011 @cindex @code{word} directive, x86-64
1012 @cindex @code{long} directive, x86-64
1013 @cindex @code{int} directive, x86-64
1014 @cindex @code{quad} directive, x86-64
1016 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1017 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1018 corresponding instruction mnemonic suffixes are @samp{s} (single),
1019 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1020 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1021 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1022 stack) instructions.
1025 Register to register operations should not use instruction mnemonic suffixes.
1026 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1027 wrote @samp{fst %st, %st(1)}, since all register to register operations
1028 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1029 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1030 then stores the result in the 4 byte location @samp{mem})
1033 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1036 @cindex 3DNow!, i386
1039 @cindex 3DNow!, x86-64
1040 @cindex SIMD, x86-64
1042 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1043 instructions for integer data), available on Intel's Pentium MMX
1044 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1045 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1046 instruction set (SIMD instructions for 32-bit floating point data)
1047 available on AMD's K6-2 processor and possibly others in the future.
1049 Currently, @code{@value{AS}} does not support Intel's floating point
1052 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1053 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1054 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1055 floating point values. The MMX registers cannot be used at the same time
1056 as the floating point stack.
1058 See Intel and AMD documentation, keeping in mind that the operand order in
1059 instructions is reversed from the Intel syntax.
1062 @section AMD's Lightweight Profiling Instructions
1067 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1068 instruction set, available on AMD's Family 15h (Orochi) processors.
1070 LWP enables applications to collect and manage performance data, and
1071 react to performance events. The collection of performance data
1072 requires no context switches. LWP runs in the context of a thread and
1073 so several counters can be used independently across multiple threads.
1074 LWP can be used in both 64-bit and legacy 32-bit modes.
1076 For detailed information on the LWP instruction set, see the
1077 @cite{AMD Lightweight Profiling Specification} available at
1078 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1081 @section Bit Manipulation Instructions
1086 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1088 BMI instructions provide several instructions implementing individual
1089 bit manipulation operations such as isolation, masking, setting, or
1092 @c Need to add a specification citation here when available.
1095 @section AMD's Trailing Bit Manipulation Instructions
1100 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1101 instruction set, available on AMD's BDVER2 processors (Trinity and
1104 TBM instructions provide instructions implementing individual bit
1105 manipulation operations such as isolating, masking, setting, resetting,
1106 complementing, and operations on trailing zeros and ones.
1108 @c Need to add a specification citation here when available.
1111 @section Writing 16-bit Code
1113 @cindex i386 16-bit code
1114 @cindex 16-bit code, i386
1115 @cindex real-mode code, i386
1116 @cindex @code{code16gcc} directive, i386
1117 @cindex @code{code16} directive, i386
1118 @cindex @code{code32} directive, i386
1119 @cindex @code{code64} directive, i386
1120 @cindex @code{code64} directive, x86-64
1121 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1122 or 64-bit x86-64 code depending on the default configuration,
1123 it also supports writing code to run in real mode or in 16-bit protected
1124 mode code segments. To do this, put a @samp{.code16} or
1125 @samp{.code16gcc} directive before the assembly language instructions to
1126 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1127 32-bit code with the @samp{.code32} directive or 64-bit code with the
1128 @samp{.code64} directive.
1130 @samp{.code16gcc} provides experimental support for generating 16-bit
1131 code from gcc, and differs from @samp{.code16} in that @samp{call},
1132 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1133 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1134 default to 32-bit size. This is so that the stack pointer is
1135 manipulated in the same way over function calls, allowing access to
1136 function parameters at the same stack offsets as in 32-bit mode.
1137 @samp{.code16gcc} also automatically adds address size prefixes where
1138 necessary to use the 32-bit addressing modes that gcc generates.
1140 The code which @code{@value{AS}} generates in 16-bit mode will not
1141 necessarily run on a 16-bit pre-80386 processor. To write code that
1142 runs on such a processor, you must refrain from using @emph{any} 32-bit
1143 constructs which require @code{@value{AS}} to output address or operand
1146 Note that writing 16-bit code instructions by explicitly specifying a
1147 prefix or an instruction mnemonic suffix within a 32-bit code section
1148 generates different machine instructions than those generated for a
1149 16-bit code segment. In a 32-bit code section, the following code
1150 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1151 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1157 The same code in a 16-bit code section would generate the machine
1158 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1159 is correct since the processor default operand size is assumed to be 16
1160 bits in a 16-bit code section.
1163 @section Specifying CPU Architecture
1165 @cindex arch directive, i386
1166 @cindex i386 arch directive
1167 @cindex arch directive, x86-64
1168 @cindex x86-64 arch directive
1170 @code{@value{AS}} may be told to assemble for a particular CPU
1171 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1172 directive enables a warning when gas detects an instruction that is not
1173 supported on the CPU specified. The choices for @var{cpu_type} are:
1175 @multitable @columnfractions .20 .20 .20 .20
1176 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1177 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1178 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1179 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1180 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1181 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1182 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1183 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1184 @item @samp{generic32} @tab @samp{generic64}
1185 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1186 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1187 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1188 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1189 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1190 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1191 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1192 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1193 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1194 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1195 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1196 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1197 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1198 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite}
1199 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1200 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1201 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1202 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1205 Apart from the warning, there are only two other effects on
1206 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1207 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1208 will automatically use a two byte opcode sequence. The larger three
1209 byte opcode sequence is used on the 486 (and when no architecture is
1210 specified) because it executes faster on the 486. Note that you can
1211 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1212 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1213 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1214 conditional jumps will be promoted when necessary to a two instruction
1215 sequence consisting of a conditional jump of the opposite sense around
1216 an unconditional jump to the target.
1218 Following the CPU architecture (but not a sub-architecture, which are those
1219 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1220 control automatic promotion of conditional jumps. @samp{jumps} is the
1221 default, and enables jump promotion; All external jumps will be of the long
1222 variety, and file-local jumps will be promoted as necessary.
1223 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1224 byte offset jumps, and warns about file-local conditional jumps that
1225 @code{@value{AS}} promotes.
1226 Unconditional jumps are treated as for @samp{jumps}.
1235 @section AT&T Syntax bugs
1237 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1238 assemblers, generate floating point instructions with reversed source
1239 and destination registers in certain cases. Unfortunately, gcc and
1240 possibly many other programs use this reversed syntax, so we're stuck
1249 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1250 than the expected @samp{%st(3) - %st}. This happens with all the
1251 non-commutative arithmetic floating point operations with two register
1252 operands where the source register is @samp{%st} and the destination
1253 register is @samp{%st(i)}.
1258 @cindex i386 @code{mul}, @code{imul} instructions
1259 @cindex @code{mul} instruction, i386
1260 @cindex @code{imul} instruction, i386
1261 @cindex @code{mul} instruction, x86-64
1262 @cindex @code{imul} instruction, x86-64
1263 There is some trickery concerning the @samp{mul} and @samp{imul}
1264 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1265 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1266 for @samp{imul}) can be output only in the one operand form. Thus,
1267 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1268 the expanding multiply would clobber the @samp{%edx} register, and this
1269 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1270 64-bit product in @samp{%edx:%eax}.
1272 We have added a two operand form of @samp{imul} when the first operand
1273 is an immediate mode expression and the second operand is a register.
1274 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1275 example, can be done with @samp{imul $69, %eax} rather than @samp{imul