1 @c Copyright (C) 1991-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
130 In addition to the basic instruction set, the assembler can be told to
131 accept various extension mnemonics. For example,
132 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
133 @var{vmx}. The following extensions are currently supported:
185 @code{avx512_4fmaps},
186 @code{avx512_4vnniw},
187 @code{avx512_vpopcntdq},
198 @code{noavx512_4fmaps},
199 @code{noavx512_4vnniw},
200 @code{noavx512_vpopcntdq},
201 @code{noavx512_vbmi2},
238 Note that rather than extending a basic instruction set, the extension
239 mnemonics starting with @code{no} revoke the respective functionality.
241 When the @code{.arch} directive is used with @option{-march}, the
242 @code{.arch} directive will take precedent.
244 @cindex @samp{-mtune=} option, i386
245 @cindex @samp{-mtune=} option, x86-64
246 @item -mtune=@var{CPU}
247 This option specifies a processor to optimize for. When used in
248 conjunction with the @option{-march} option, only instructions
249 of the processor specified by the @option{-march} option will be
252 Valid @var{CPU} values are identical to the processor list of
253 @option{-march=@var{CPU}}.
255 @cindex @samp{-msse2avx} option, i386
256 @cindex @samp{-msse2avx} option, x86-64
258 This option specifies that the assembler should encode SSE instructions
261 @cindex @samp{-msse-check=} option, i386
262 @cindex @samp{-msse-check=} option, x86-64
263 @item -msse-check=@var{none}
264 @itemx -msse-check=@var{warning}
265 @itemx -msse-check=@var{error}
266 These options control if the assembler should check SSE instructions.
267 @option{-msse-check=@var{none}} will make the assembler not to check SSE
268 instructions, which is the default. @option{-msse-check=@var{warning}}
269 will make the assembler issue a warning for any SSE instruction.
270 @option{-msse-check=@var{error}} will make the assembler issue an error
271 for any SSE instruction.
273 @cindex @samp{-mavxscalar=} option, i386
274 @cindex @samp{-mavxscalar=} option, x86-64
275 @item -mavxscalar=@var{128}
276 @itemx -mavxscalar=@var{256}
277 These options control how the assembler should encode scalar AVX
278 instructions. @option{-mavxscalar=@var{128}} will encode scalar
279 AVX instructions with 128bit vector length, which is the default.
280 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
281 with 256bit vector length.
283 @cindex @samp{-mevexlig=} option, i386
284 @cindex @samp{-mevexlig=} option, x86-64
285 @item -mevexlig=@var{128}
286 @itemx -mevexlig=@var{256}
287 @itemx -mevexlig=@var{512}
288 These options control how the assembler should encode length-ignored
289 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
290 EVEX instructions with 128bit vector length, which is the default.
291 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
292 encode LIG EVEX instructions with 256bit and 512bit vector length,
295 @cindex @samp{-mevexwig=} option, i386
296 @cindex @samp{-mevexwig=} option, x86-64
297 @item -mevexwig=@var{0}
298 @itemx -mevexwig=@var{1}
299 These options control how the assembler should encode w-ignored (WIG)
300 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
301 EVEX instructions with evex.w = 0, which is the default.
302 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
305 @cindex @samp{-mmnemonic=} option, i386
306 @cindex @samp{-mmnemonic=} option, x86-64
307 @item -mmnemonic=@var{att}
308 @itemx -mmnemonic=@var{intel}
309 This option specifies instruction mnemonic for matching instructions.
310 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
313 @cindex @samp{-msyntax=} option, i386
314 @cindex @samp{-msyntax=} option, x86-64
315 @item -msyntax=@var{att}
316 @itemx -msyntax=@var{intel}
317 This option specifies instruction syntax when processing instructions.
318 The @code{.att_syntax} and @code{.intel_syntax} directives will
321 @cindex @samp{-mnaked-reg} option, i386
322 @cindex @samp{-mnaked-reg} option, x86-64
324 This option specifies that registers don't require a @samp{%} prefix.
325 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
327 @cindex @samp{-madd-bnd-prefix} option, i386
328 @cindex @samp{-madd-bnd-prefix} option, x86-64
329 @item -madd-bnd-prefix
330 This option forces the assembler to add BND prefix to all branches, even
331 if such prefix was not explicitly specified in the source code.
333 @cindex @samp{-mshared} option, i386
334 @cindex @samp{-mshared} option, x86-64
336 On ELF target, the assembler normally optimizes out non-PLT relocations
337 against defined non-weak global branch targets with default visibility.
338 The @samp{-mshared} option tells the assembler to generate code which
339 may go into a shared library where all non-weak global branch targets
340 with default visibility can be preempted. The resulting code is
341 slightly bigger. This option only affects the handling of branch
344 @cindex @samp{-mbig-obj} option, x86-64
346 On x86-64 PE/COFF target this option forces the use of big object file
347 format, which allows more than 32768 sections.
349 @cindex @samp{-momit-lock-prefix=} option, i386
350 @cindex @samp{-momit-lock-prefix=} option, x86-64
351 @item -momit-lock-prefix=@var{no}
352 @itemx -momit-lock-prefix=@var{yes}
353 These options control how the assembler should encode lock prefix.
354 This option is intended as a workaround for processors, that fail on
355 lock prefix. This option can only be safely used with single-core,
356 single-thread computers
357 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
358 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
359 which is the default.
361 @cindex @samp{-mfence-as-lock-add=} option, i386
362 @cindex @samp{-mfence-as-lock-add=} option, x86-64
363 @item -mfence-as-lock-add=@var{no}
364 @itemx -mfence-as-lock-add=@var{yes}
365 These options control how the assembler should encode lfence, mfence and
367 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
368 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
369 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
370 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
371 sfence as usual, which is the default.
373 @cindex @samp{-mrelax-relocations=} option, i386
374 @cindex @samp{-mrelax-relocations=} option, x86-64
375 @item -mrelax-relocations=@var{no}
376 @itemx -mrelax-relocations=@var{yes}
377 These options control whether the assembler should generate relax
378 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
379 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
380 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
381 @option{-mrelax-relocations=@var{no}} will not generate relax
382 relocations. The default can be controlled by a configure option
383 @option{--enable-x86-relax-relocations}.
385 @cindex @samp{-mevexrcig=} option, i386
386 @cindex @samp{-mevexrcig=} option, x86-64
387 @item -mevexrcig=@var{rne}
388 @itemx -mevexrcig=@var{rd}
389 @itemx -mevexrcig=@var{ru}
390 @itemx -mevexrcig=@var{rz}
391 These options control how the assembler should encode SAE-only
392 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
393 of EVEX instruction with 00, which is the default.
394 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
395 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
396 with 01, 10 and 11 RC bits, respectively.
398 @cindex @samp{-mamd64} option, x86-64
399 @cindex @samp{-mintel64} option, x86-64
402 This option specifies that the assembler should accept only AMD64 or
403 Intel64 ISA in 64-bit mode. The default is to accept both.
408 @node i386-Directives
409 @section x86 specific Directives
411 @cindex machine directives, x86
412 @cindex x86 machine directives
415 @cindex @code{lcomm} directive, COFF
416 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
417 Reserve @var{length} (an absolute expression) bytes for a local common
418 denoted by @var{symbol}. The section and value of @var{symbol} are
419 those of the new local common. The addresses are allocated in the bss
420 section, so that at run-time the bytes start off zeroed. Since
421 @var{symbol} is not declared global, it is normally not visible to
422 @code{@value{LD}}. The optional third parameter, @var{alignment},
423 specifies the desired alignment of the symbol in the bss section.
425 This directive is only available for COFF based x86 targets.
427 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
433 @section i386 Syntactical Considerations
435 * i386-Variations:: AT&T Syntax versus Intel Syntax
436 * i386-Chars:: Special Characters
439 @node i386-Variations
440 @subsection AT&T Syntax versus Intel Syntax
442 @cindex i386 intel_syntax pseudo op
443 @cindex intel_syntax pseudo op, i386
444 @cindex i386 att_syntax pseudo op
445 @cindex att_syntax pseudo op, i386
446 @cindex i386 syntax compatibility
447 @cindex syntax compatibility, i386
448 @cindex x86-64 intel_syntax pseudo op
449 @cindex intel_syntax pseudo op, x86-64
450 @cindex x86-64 att_syntax pseudo op
451 @cindex att_syntax pseudo op, x86-64
452 @cindex x86-64 syntax compatibility
453 @cindex syntax compatibility, x86-64
455 @code{@value{AS}} now supports assembly using Intel assembler syntax.
456 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
457 back to the usual AT&T mode for compatibility with the output of
458 @code{@value{GCC}}. Either of these directives may have an optional
459 argument, @code{prefix}, or @code{noprefix} specifying whether registers
460 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
461 different from Intel syntax. We mention these differences because
462 almost all 80386 documents use Intel syntax. Notable differences
463 between the two syntaxes are:
465 @cindex immediate operands, i386
466 @cindex i386 immediate operands
467 @cindex register operands, i386
468 @cindex i386 register operands
469 @cindex jump/call operands, i386
470 @cindex i386 jump/call operands
471 @cindex operand delimiters, i386
473 @cindex immediate operands, x86-64
474 @cindex x86-64 immediate operands
475 @cindex register operands, x86-64
476 @cindex x86-64 register operands
477 @cindex jump/call operands, x86-64
478 @cindex x86-64 jump/call operands
479 @cindex operand delimiters, x86-64
482 AT&T immediate operands are preceded by @samp{$}; Intel immediate
483 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
484 AT&T register operands are preceded by @samp{%}; Intel register operands
485 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
486 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
488 @cindex i386 source, destination operands
489 @cindex source, destination operands; i386
490 @cindex x86-64 source, destination operands
491 @cindex source, destination operands; x86-64
493 AT&T and Intel syntax use the opposite order for source and destination
494 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
495 @samp{source, dest} convention is maintained for compatibility with
496 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
497 instructions with 2 immediate operands, such as the @samp{enter}
498 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
500 @cindex mnemonic suffixes, i386
501 @cindex sizes operands, i386
502 @cindex i386 size suffixes
503 @cindex mnemonic suffixes, x86-64
504 @cindex sizes operands, x86-64
505 @cindex x86-64 size suffixes
507 In AT&T syntax the size of memory operands is determined from the last
508 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
509 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
510 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
511 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
512 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
513 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
516 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
517 instruction with the 64-bit displacement or immediate operand.
519 @cindex return instructions, i386
520 @cindex i386 jump, call, return
521 @cindex return instructions, x86-64
522 @cindex x86-64 jump, call, return
524 Immediate form long jumps and calls are
525 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
527 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
529 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
530 @samp{ret far @var{stack-adjust}}.
532 @cindex sections, i386
533 @cindex i386 sections
534 @cindex sections, x86-64
535 @cindex x86-64 sections
537 The AT&T assembler does not provide support for multiple section
538 programs. Unix style systems expect all programs to be single sections.
542 @subsection Special Characters
544 @cindex line comment character, i386
545 @cindex i386 line comment character
546 The presence of a @samp{#} appearing anywhere on a line indicates the
547 start of a comment that extends to the end of that line.
549 If a @samp{#} appears as the first character of a line then the whole
550 line is treated as a comment, but in this case the line can also be a
551 logical line number directive (@pxref{Comments}) or a preprocessor
552 control command (@pxref{Preprocessing}).
554 If the @option{--divide} command line option has not been specified
555 then the @samp{/} character appearing anywhere on a line also
556 introduces a line comment.
558 @cindex line separator, i386
559 @cindex statement separator, i386
560 @cindex i386 line separator
561 The @samp{;} character can be used to separate statements on the same
565 @section i386-Mnemonics
566 @subsection Instruction Naming
568 @cindex i386 instruction naming
569 @cindex instruction naming, i386
570 @cindex x86-64 instruction naming
571 @cindex instruction naming, x86-64
573 Instruction mnemonics are suffixed with one character modifiers which
574 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
575 and @samp{q} specify byte, word, long and quadruple word operands. If
576 no suffix is specified by an instruction then @code{@value{AS}} tries to
577 fill in the missing suffix based on the destination register operand
578 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
579 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
580 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
581 assembler which assumes that a missing mnemonic suffix implies long
582 operand size. (This incompatibility does not affect compiler output
583 since compilers always explicitly specify the mnemonic suffix.)
585 Almost all instructions have the same names in AT&T and Intel format.
586 There are a few exceptions. The sign extend and zero extend
587 instructions need two sizes to specify them. They need a size to
588 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
589 is accomplished by using two instruction mnemonic suffixes in AT&T
590 syntax. Base names for sign extend and zero extend are
591 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
592 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
593 are tacked on to this base name, the @emph{from} suffix before the
594 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
595 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
596 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
597 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
598 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
601 @cindex encoding options, i386
602 @cindex encoding options, x86-64
604 Different encoding options can be specified via pseudo prefixes:
608 @samp{@{disp8@}} -- prefer 8-bit displacement.
611 @samp{@{disp32@}} -- prefer 32-bit displacement.
614 @samp{@{load@}} -- prefer load-form instruction.
617 @samp{@{store@}} -- prefer store-form instruction.
620 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
623 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
626 @samp{@{evex@}} -- encode with EVEX prefix.
629 @cindex conversion instructions, i386
630 @cindex i386 conversion instructions
631 @cindex conversion instructions, x86-64
632 @cindex x86-64 conversion instructions
633 The Intel-syntax conversion instructions
637 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
640 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
643 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
646 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
649 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
653 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
654 @samp{%rdx:%rax} (x86-64 only),
658 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
659 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
662 @cindex jump instructions, i386
663 @cindex call instructions, i386
664 @cindex jump instructions, x86-64
665 @cindex call instructions, x86-64
666 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
667 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
670 @subsection AT&T Mnemonic versus Intel Mnemonic
672 @cindex i386 mnemonic compatibility
673 @cindex mnemonic compatibility, i386
675 @code{@value{AS}} supports assembly using Intel mnemonic.
676 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
677 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
678 syntax for compatibility with the output of @code{@value{GCC}}.
679 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
680 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
681 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
682 assembler with different mnemonics from those in Intel IA32 specification.
683 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
686 @section Register Naming
688 @cindex i386 registers
689 @cindex registers, i386
690 @cindex x86-64 registers
691 @cindex registers, x86-64
692 Register operands are always prefixed with @samp{%}. The 80386 registers
697 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
698 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
699 frame pointer), and @samp{%esp} (the stack pointer).
702 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
703 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
706 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
707 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
708 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
709 @samp{%cx}, and @samp{%dx})
712 the 6 section registers @samp{%cs} (code section), @samp{%ds}
713 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
717 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
718 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
721 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
722 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
725 the 2 test registers @samp{%tr6} and @samp{%tr7}.
728 the 8 floating point register stack @samp{%st} or equivalently
729 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
730 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
731 These registers are overloaded by 8 MMX registers @samp{%mm0},
732 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
733 @samp{%mm6} and @samp{%mm7}.
736 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
737 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
740 The AMD x86-64 architecture extends the register set by:
744 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
745 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
746 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
750 the 8 extended registers @samp{%r8}--@samp{%r15}.
753 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
756 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
759 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
762 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
765 the 8 debug registers: @samp{%db8}--@samp{%db15}.
768 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
771 With the AVX extensions more registers were made available:
776 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
777 available in 32-bit mode). The bottom 128 bits are overlaid with the
778 @samp{xmm0}--@samp{xmm15} registers.
782 The AVX2 extensions made in 64-bit mode more registers available:
787 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
788 registers @samp{%ymm16}--@samp{%ymm31}.
792 The AVX512 extensions added the following registers:
797 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
798 available in 32-bit mode). The bottom 128 bits are overlaid with the
799 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
800 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
803 the 8 mask registers @samp{%k0}--@samp{%k7}.
808 @section Instruction Prefixes
810 @cindex i386 instruction prefixes
811 @cindex instruction prefixes, i386
812 @cindex prefixes, i386
813 Instruction prefixes are used to modify the following instruction. They
814 are used to repeat string instructions, to provide section overrides, to
815 perform bus lock operations, and to change operand and address sizes.
816 (Most instructions that normally operate on 32-bit operands will use
817 16-bit operands if the instruction has an ``operand size'' prefix.)
818 Instruction prefixes are best written on the same line as the instruction
819 they act upon. For example, the @samp{scas} (scan string) instruction is
823 repne scas %es:(%edi),%al
826 You may also place prefixes on the lines immediately preceding the
827 instruction, but this circumvents checks that @code{@value{AS}} does
828 with prefixes, and will not work with all prefixes.
830 Here is a list of instruction prefixes:
832 @cindex section override prefixes, i386
835 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
836 @samp{fs}, @samp{gs}. These are automatically added by specifying
837 using the @var{section}:@var{memory-operand} form for memory references.
839 @cindex size prefixes, i386
841 Operand/Address size prefixes @samp{data16} and @samp{addr16}
842 change 32-bit operands/addresses into 16-bit operands/addresses,
843 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
844 @code{.code16} section) into 32-bit operands/addresses. These prefixes
845 @emph{must} appear on the same line of code as the instruction they
846 modify. For example, in a 16-bit @code{.code16} section, you might
853 @cindex bus lock prefixes, i386
854 @cindex inhibiting interrupts, i386
856 The bus lock prefix @samp{lock} inhibits interrupts during execution of
857 the instruction it precedes. (This is only valid with certain
858 instructions; see a 80386 manual for details).
860 @cindex coprocessor wait, i386
862 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
863 complete the current instruction. This should never be needed for the
864 80386/80387 combination.
866 @cindex repeat prefixes, i386
868 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
869 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
870 times if the current address size is 16-bits).
871 @cindex REX prefixes, i386
873 The @samp{rex} family of prefixes is used by x86-64 to encode
874 extensions to i386 instruction set. The @samp{rex} prefix has four
875 bits --- an operand size overwrite (@code{64}) used to change operand size
876 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
879 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
880 instruction emits @samp{rex} prefix with all the bits set. By omitting
881 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
882 prefixes as well. Normally, there is no need to write the prefixes
883 explicitly, since gas will automatically generate them based on the
884 instruction operands.
888 @section Memory References
890 @cindex i386 memory references
891 @cindex memory references, i386
892 @cindex x86-64 memory references
893 @cindex memory references, x86-64
894 An Intel syntax indirect memory reference of the form
897 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
901 is translated into the AT&T syntax
904 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
908 where @var{base} and @var{index} are the optional 32-bit base and
909 index registers, @var{disp} is the optional displacement, and
910 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
911 to calculate the address of the operand. If no @var{scale} is
912 specified, @var{scale} is taken to be 1. @var{section} specifies the
913 optional section register for the memory operand, and may override the
914 default section register (see a 80386 manual for section register
915 defaults). Note that section overrides in AT&T syntax @emph{must}
916 be preceded by a @samp{%}. If you specify a section override which
917 coincides with the default section register, @code{@value{AS}} does @emph{not}
918 output any section register override prefixes to assemble the given
919 instruction. Thus, section overrides can be specified to emphasize which
920 section register is used for a given memory operand.
922 Here are some examples of Intel and AT&T style memory references:
925 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
926 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
927 missing, and the default section is used (@samp{%ss} for addressing with
928 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
930 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
931 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
932 @samp{foo}. All other fields are missing. The section register here
933 defaults to @samp{%ds}.
935 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
936 This uses the value pointed to by @samp{foo} as a memory operand.
937 Note that @var{base} and @var{index} are both missing, but there is only
938 @emph{one} @samp{,}. This is a syntactic exception.
940 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
941 This selects the contents of the variable @samp{foo} with section
942 register @var{section} being @samp{%gs}.
945 Absolute (as opposed to PC relative) call and jump operands must be
946 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
947 always chooses PC relative addressing for jump/call labels.
949 Any instruction that has a memory operand, but no register operand,
950 @emph{must} specify its size (byte, word, long, or quadruple) with an
951 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
954 The x86-64 architecture adds an RIP (instruction pointer relative)
955 addressing. This addressing mode is specified by using @samp{rip} as a
956 base register. Only constant offsets are valid. For example:
959 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
960 Points to the address 1234 bytes past the end of the current
963 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
964 Points to the @code{symbol} in RIP relative way, this is shorter than
965 the default absolute addressing.
968 Other addressing modes remain unchanged in x86-64 architecture, except
969 registers used are 64-bit instead of 32-bit.
972 @section Handling of Jump Instructions
974 @cindex jump optimization, i386
975 @cindex i386 jump optimization
976 @cindex jump optimization, x86-64
977 @cindex x86-64 jump optimization
978 Jump instructions are always optimized to use the smallest possible
979 displacements. This is accomplished by using byte (8-bit) displacement
980 jumps whenever the target is sufficiently close. If a byte displacement
981 is insufficient a long displacement is used. We do not support
982 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
983 instruction with the @samp{data16} instruction prefix), since the 80386
984 insists upon masking @samp{%eip} to 16 bits after the word displacement
985 is added. (See also @pxref{i386-Arch})
987 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
988 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
989 displacements, so that if you use these instructions (@code{@value{GCC}} does
990 not use them) you may get an error message (and incorrect code). The AT&T
991 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1002 @section Floating Point
1004 @cindex i386 floating point
1005 @cindex floating point, i386
1006 @cindex x86-64 floating point
1007 @cindex floating point, x86-64
1008 All 80387 floating point types except packed BCD are supported.
1009 (BCD support may be added without much difficulty). These data
1010 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1011 double (64-bit), and extended (80-bit) precision floating point.
1012 Each supported type has an instruction mnemonic suffix and a constructor
1013 associated with it. Instruction mnemonic suffixes specify the operand's
1014 data type. Constructors build these data types into memory.
1016 @cindex @code{float} directive, i386
1017 @cindex @code{single} directive, i386
1018 @cindex @code{double} directive, i386
1019 @cindex @code{tfloat} directive, i386
1020 @cindex @code{float} directive, x86-64
1021 @cindex @code{single} directive, x86-64
1022 @cindex @code{double} directive, x86-64
1023 @cindex @code{tfloat} directive, x86-64
1026 Floating point constructors are @samp{.float} or @samp{.single},
1027 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1028 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1029 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1030 only supports this format via the @samp{fldt} (load 80-bit real to stack
1031 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1033 @cindex @code{word} directive, i386
1034 @cindex @code{long} directive, i386
1035 @cindex @code{int} directive, i386
1036 @cindex @code{quad} directive, i386
1037 @cindex @code{word} directive, x86-64
1038 @cindex @code{long} directive, x86-64
1039 @cindex @code{int} directive, x86-64
1040 @cindex @code{quad} directive, x86-64
1042 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1043 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1044 corresponding instruction mnemonic suffixes are @samp{s} (single),
1045 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1046 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1047 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1048 stack) instructions.
1051 Register to register operations should not use instruction mnemonic suffixes.
1052 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1053 wrote @samp{fst %st, %st(1)}, since all register to register operations
1054 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1055 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1056 then stores the result in the 4 byte location @samp{mem})
1059 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1062 @cindex 3DNow!, i386
1065 @cindex 3DNow!, x86-64
1066 @cindex SIMD, x86-64
1068 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1069 instructions for integer data), available on Intel's Pentium MMX
1070 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1071 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1072 instruction set (SIMD instructions for 32-bit floating point data)
1073 available on AMD's K6-2 processor and possibly others in the future.
1075 Currently, @code{@value{AS}} does not support Intel's floating point
1078 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1079 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1080 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1081 floating point values. The MMX registers cannot be used at the same time
1082 as the floating point stack.
1084 See Intel and AMD documentation, keeping in mind that the operand order in
1085 instructions is reversed from the Intel syntax.
1088 @section AMD's Lightweight Profiling Instructions
1093 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1094 instruction set, available on AMD's Family 15h (Orochi) processors.
1096 LWP enables applications to collect and manage performance data, and
1097 react to performance events. The collection of performance data
1098 requires no context switches. LWP runs in the context of a thread and
1099 so several counters can be used independently across multiple threads.
1100 LWP can be used in both 64-bit and legacy 32-bit modes.
1102 For detailed information on the LWP instruction set, see the
1103 @cite{AMD Lightweight Profiling Specification} available at
1104 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1107 @section Bit Manipulation Instructions
1112 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1114 BMI instructions provide several instructions implementing individual
1115 bit manipulation operations such as isolation, masking, setting, or
1118 @c Need to add a specification citation here when available.
1121 @section AMD's Trailing Bit Manipulation Instructions
1126 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1127 instruction set, available on AMD's BDVER2 processors (Trinity and
1130 TBM instructions provide instructions implementing individual bit
1131 manipulation operations such as isolating, masking, setting, resetting,
1132 complementing, and operations on trailing zeros and ones.
1134 @c Need to add a specification citation here when available.
1137 @section Writing 16-bit Code
1139 @cindex i386 16-bit code
1140 @cindex 16-bit code, i386
1141 @cindex real-mode code, i386
1142 @cindex @code{code16gcc} directive, i386
1143 @cindex @code{code16} directive, i386
1144 @cindex @code{code32} directive, i386
1145 @cindex @code{code64} directive, i386
1146 @cindex @code{code64} directive, x86-64
1147 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1148 or 64-bit x86-64 code depending on the default configuration,
1149 it also supports writing code to run in real mode or in 16-bit protected
1150 mode code segments. To do this, put a @samp{.code16} or
1151 @samp{.code16gcc} directive before the assembly language instructions to
1152 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1153 32-bit code with the @samp{.code32} directive or 64-bit code with the
1154 @samp{.code64} directive.
1156 @samp{.code16gcc} provides experimental support for generating 16-bit
1157 code from gcc, and differs from @samp{.code16} in that @samp{call},
1158 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1159 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1160 default to 32-bit size. This is so that the stack pointer is
1161 manipulated in the same way over function calls, allowing access to
1162 function parameters at the same stack offsets as in 32-bit mode.
1163 @samp{.code16gcc} also automatically adds address size prefixes where
1164 necessary to use the 32-bit addressing modes that gcc generates.
1166 The code which @code{@value{AS}} generates in 16-bit mode will not
1167 necessarily run on a 16-bit pre-80386 processor. To write code that
1168 runs on such a processor, you must refrain from using @emph{any} 32-bit
1169 constructs which require @code{@value{AS}} to output address or operand
1172 Note that writing 16-bit code instructions by explicitly specifying a
1173 prefix or an instruction mnemonic suffix within a 32-bit code section
1174 generates different machine instructions than those generated for a
1175 16-bit code segment. In a 32-bit code section, the following code
1176 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1177 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1183 The same code in a 16-bit code section would generate the machine
1184 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1185 is correct since the processor default operand size is assumed to be 16
1186 bits in a 16-bit code section.
1189 @section Specifying CPU Architecture
1191 @cindex arch directive, i386
1192 @cindex i386 arch directive
1193 @cindex arch directive, x86-64
1194 @cindex x86-64 arch directive
1196 @code{@value{AS}} may be told to assemble for a particular CPU
1197 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1198 directive enables a warning when gas detects an instruction that is not
1199 supported on the CPU specified. The choices for @var{cpu_type} are:
1201 @multitable @columnfractions .20 .20 .20 .20
1202 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1203 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1204 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1205 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1206 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1207 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1208 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1209 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1210 @item @samp{generic32} @tab @samp{generic64}
1211 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1212 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1213 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1214 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1215 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1216 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1217 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1218 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1219 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1220 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1221 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1222 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1223 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1224 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2}
1225 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.cet}
1226 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1227 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1228 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1229 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.gfni}
1232 Apart from the warning, there are only two other effects on
1233 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1234 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1235 will automatically use a two byte opcode sequence. The larger three
1236 byte opcode sequence is used on the 486 (and when no architecture is
1237 specified) because it executes faster on the 486. Note that you can
1238 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1239 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1240 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1241 conditional jumps will be promoted when necessary to a two instruction
1242 sequence consisting of a conditional jump of the opposite sense around
1243 an unconditional jump to the target.
1245 Following the CPU architecture (but not a sub-architecture, which are those
1246 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1247 control automatic promotion of conditional jumps. @samp{jumps} is the
1248 default, and enables jump promotion; All external jumps will be of the long
1249 variety, and file-local jumps will be promoted as necessary.
1250 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1251 byte offset jumps, and warns about file-local conditional jumps that
1252 @code{@value{AS}} promotes.
1253 Unconditional jumps are treated as for @samp{jumps}.
1262 @section AT&T Syntax bugs
1264 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1265 assemblers, generate floating point instructions with reversed source
1266 and destination registers in certain cases. Unfortunately, gcc and
1267 possibly many other programs use this reversed syntax, so we're stuck
1276 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1277 than the expected @samp{%st(3) - %st}. This happens with all the
1278 non-commutative arithmetic floating point operations with two register
1279 operands where the source register is @samp{%st} and the destination
1280 register is @samp{%st(i)}.
1285 @cindex i386 @code{mul}, @code{imul} instructions
1286 @cindex @code{mul} instruction, i386
1287 @cindex @code{imul} instruction, i386
1288 @cindex @code{mul} instruction, x86-64
1289 @cindex @code{imul} instruction, x86-64
1290 There is some trickery concerning the @samp{mul} and @samp{imul}
1291 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1292 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1293 for @samp{imul}) can be output only in the one operand form. Thus,
1294 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1295 the expanding multiply would clobber the @samp{%edx} register, and this
1296 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1297 64-bit product in @samp{%edx:%eax}.
1299 We have added a two operand form of @samp{imul} when the first operand
1300 is an immediate mode expression and the second operand is a register.
1301 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1302 example, can be done with @samp{imul $69, %eax} rather than @samp{imul