1 @c Copyright (C) 1991-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
78 byte nop (0x90) is explicitly specified as the fill byte for alignment.
80 @cindex @samp{--divide} option, i386
82 On SVR4-derived platforms, the character @samp{/} is treated as a comment
83 character, which means that it cannot be used in expressions. The
84 @samp{--divide} option turns @samp{/} into a normal character. This does
85 not disable @samp{/} at the beginning of a line starting a comment, or
86 affect using @samp{#} for starting a comment.
88 @cindex @samp{-march=} option, i386
89 @cindex @samp{-march=} option, x86-64
90 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
91 This option specifies the target processor. The assembler will
92 issue an error message if an attempt is made to assemble an instruction
93 which will not execute on the target processor. The following
94 processor names are recognized:
132 In addition to the basic instruction set, the assembler can be told to
133 accept various extension mnemonics. For example,
134 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
135 @var{vmx}. The following extensions are currently supported:
196 @code{avx512_4fmaps},
197 @code{avx512_4vnniw},
198 @code{avx512_vpopcntdq},
201 @code{avx512_bitalg},
212 @code{noavx512_4fmaps},
213 @code{noavx512_4vnniw},
214 @code{noavx512_vpopcntdq},
215 @code{noavx512_vbmi2},
216 @code{noavx512_vnni},
217 @code{noavx512_bitalg},
218 @code{noavx512_vp2intersect},
219 @code{noavx512_bf16},
263 Note that rather than extending a basic instruction set, the extension
264 mnemonics starting with @code{no} revoke the respective functionality.
266 When the @code{.arch} directive is used with @option{-march}, the
267 @code{.arch} directive will take precedent.
269 @cindex @samp{-mtune=} option, i386
270 @cindex @samp{-mtune=} option, x86-64
271 @item -mtune=@var{CPU}
272 This option specifies a processor to optimize for. When used in
273 conjunction with the @option{-march} option, only instructions
274 of the processor specified by the @option{-march} option will be
277 Valid @var{CPU} values are identical to the processor list of
278 @option{-march=@var{CPU}}.
280 @cindex @samp{-msse2avx} option, i386
281 @cindex @samp{-msse2avx} option, x86-64
283 This option specifies that the assembler should encode SSE instructions
286 @cindex @samp{-msse-check=} option, i386
287 @cindex @samp{-msse-check=} option, x86-64
288 @item -msse-check=@var{none}
289 @itemx -msse-check=@var{warning}
290 @itemx -msse-check=@var{error}
291 These options control if the assembler should check SSE instructions.
292 @option{-msse-check=@var{none}} will make the assembler not to check SSE
293 instructions, which is the default. @option{-msse-check=@var{warning}}
294 will make the assembler issue a warning for any SSE instruction.
295 @option{-msse-check=@var{error}} will make the assembler issue an error
296 for any SSE instruction.
298 @cindex @samp{-mavxscalar=} option, i386
299 @cindex @samp{-mavxscalar=} option, x86-64
300 @item -mavxscalar=@var{128}
301 @itemx -mavxscalar=@var{256}
302 These options control how the assembler should encode scalar AVX
303 instructions. @option{-mavxscalar=@var{128}} will encode scalar
304 AVX instructions with 128bit vector length, which is the default.
305 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
306 with 256bit vector length.
308 WARNING: Don't use this for production code - due to CPU errata the
309 resulting code may not work on certain models.
311 @cindex @samp{-mvexwig=} option, i386
312 @cindex @samp{-mvexwig=} option, x86-64
313 @item -mvexwig=@var{0}
314 @itemx -mvexwig=@var{1}
315 These options control how the assembler should encode VEX.W-ignored (WIG)
316 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
317 instructions with vex.w = 0, which is the default.
318 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
321 WARNING: Don't use this for production code - due to CPU errata the
322 resulting code may not work on certain models.
324 @cindex @samp{-mevexlig=} option, i386
325 @cindex @samp{-mevexlig=} option, x86-64
326 @item -mevexlig=@var{128}
327 @itemx -mevexlig=@var{256}
328 @itemx -mevexlig=@var{512}
329 These options control how the assembler should encode length-ignored
330 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
331 EVEX instructions with 128bit vector length, which is the default.
332 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
333 encode LIG EVEX instructions with 256bit and 512bit vector length,
336 @cindex @samp{-mevexwig=} option, i386
337 @cindex @samp{-mevexwig=} option, x86-64
338 @item -mevexwig=@var{0}
339 @itemx -mevexwig=@var{1}
340 These options control how the assembler should encode w-ignored (WIG)
341 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
342 EVEX instructions with evex.w = 0, which is the default.
343 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
346 @cindex @samp{-mmnemonic=} option, i386
347 @cindex @samp{-mmnemonic=} option, x86-64
348 @item -mmnemonic=@var{att}
349 @itemx -mmnemonic=@var{intel}
350 This option specifies instruction mnemonic for matching instructions.
351 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
354 @cindex @samp{-msyntax=} option, i386
355 @cindex @samp{-msyntax=} option, x86-64
356 @item -msyntax=@var{att}
357 @itemx -msyntax=@var{intel}
358 This option specifies instruction syntax when processing instructions.
359 The @code{.att_syntax} and @code{.intel_syntax} directives will
362 @cindex @samp{-mnaked-reg} option, i386
363 @cindex @samp{-mnaked-reg} option, x86-64
365 This option specifies that registers don't require a @samp{%} prefix.
366 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
368 @cindex @samp{-madd-bnd-prefix} option, i386
369 @cindex @samp{-madd-bnd-prefix} option, x86-64
370 @item -madd-bnd-prefix
371 This option forces the assembler to add BND prefix to all branches, even
372 if such prefix was not explicitly specified in the source code.
374 @cindex @samp{-mshared} option, i386
375 @cindex @samp{-mshared} option, x86-64
377 On ELF target, the assembler normally optimizes out non-PLT relocations
378 against defined non-weak global branch targets with default visibility.
379 The @samp{-mshared} option tells the assembler to generate code which
380 may go into a shared library where all non-weak global branch targets
381 with default visibility can be preempted. The resulting code is
382 slightly bigger. This option only affects the handling of branch
385 @cindex @samp{-mbig-obj} option, x86-64
387 On x86-64 PE/COFF target this option forces the use of big object file
388 format, which allows more than 32768 sections.
390 @cindex @samp{-momit-lock-prefix=} option, i386
391 @cindex @samp{-momit-lock-prefix=} option, x86-64
392 @item -momit-lock-prefix=@var{no}
393 @itemx -momit-lock-prefix=@var{yes}
394 These options control how the assembler should encode lock prefix.
395 This option is intended as a workaround for processors, that fail on
396 lock prefix. This option can only be safely used with single-core,
397 single-thread computers
398 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
399 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
400 which is the default.
402 @cindex @samp{-mfence-as-lock-add=} option, i386
403 @cindex @samp{-mfence-as-lock-add=} option, x86-64
404 @item -mfence-as-lock-add=@var{no}
405 @itemx -mfence-as-lock-add=@var{yes}
406 These options control how the assembler should encode lfence, mfence and
408 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
409 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
410 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
411 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
412 sfence as usual, which is the default.
414 @cindex @samp{-mrelax-relocations=} option, i386
415 @cindex @samp{-mrelax-relocations=} option, x86-64
416 @item -mrelax-relocations=@var{no}
417 @itemx -mrelax-relocations=@var{yes}
418 These options control whether the assembler should generate relax
419 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
420 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
421 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
422 @option{-mrelax-relocations=@var{no}} will not generate relax
423 relocations. The default can be controlled by a configure option
424 @option{--enable-x86-relax-relocations}.
426 @cindex @samp{-mx86-used-note=} option, i386
427 @cindex @samp{-mx86-used-note=} option, x86-64
428 @item -mx86-used-note=@var{no}
429 @itemx -mx86-used-note=@var{yes}
430 These options control whether the assembler should generate
431 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
432 GNU property notes. The default can be controlled by the
433 @option{--enable-x86-used-note} configure option.
435 @cindex @samp{-mevexrcig=} option, i386
436 @cindex @samp{-mevexrcig=} option, x86-64
437 @item -mevexrcig=@var{rne}
438 @itemx -mevexrcig=@var{rd}
439 @itemx -mevexrcig=@var{ru}
440 @itemx -mevexrcig=@var{rz}
441 These options control how the assembler should encode SAE-only
442 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
443 of EVEX instruction with 00, which is the default.
444 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
445 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
446 with 01, 10 and 11 RC bits, respectively.
448 @cindex @samp{-mamd64} option, x86-64
449 @cindex @samp{-mintel64} option, x86-64
452 This option specifies that the assembler should accept only AMD64 or
453 Intel64 ISA in 64-bit mode. The default is to accept both.
455 @cindex @samp{-O0} option, i386
456 @cindex @samp{-O0} option, x86-64
457 @cindex @samp{-O} option, i386
458 @cindex @samp{-O} option, x86-64
459 @cindex @samp{-O1} option, i386
460 @cindex @samp{-O1} option, x86-64
461 @cindex @samp{-O2} option, i386
462 @cindex @samp{-O2} option, x86-64
463 @cindex @samp{-Os} option, i386
464 @cindex @samp{-Os} option, x86-64
465 @item -O0 | -O | -O1 | -O2 | -Os
466 Optimize instruction encoding with smaller instruction size. @samp{-O}
467 and @samp{-O1} encode 64-bit register load instructions with 64-bit
468 immediate as 32-bit register load instructions with 31-bit or 32-bits
469 immediates, encode 64-bit register clearing instructions with 32-bit
470 register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
471 register clearing instructions with 128-bit VEX vector register
472 clearing instructions, encode 128-bit/256-bit EVEX vector
473 register load/store instructions with VEX vector register load/store
474 instructions, and encode 128-bit/256-bit EVEX packed integer logical
475 instructions with 128-bit/256-bit VEX packed integer logical.
477 @samp{-O2} includes @samp{-O1} optimization plus encodes
478 256-bit/512-bit EVEX vector register clearing instructions with 128-bit
479 EVEX vector register clearing instructions. In 64-bit mode VEX encoded
480 instructions with commutative source operands will also have their
481 source operands swapped if this allows using the 2-byte VEX prefix form
482 instead of the 3-byte one. Certain forms of AND as well as OR with the
483 same (register) operand specified twice will also be changed to TEST.
485 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
486 and 64-bit register tests with immediate as 8-bit register test with
487 immediate. @samp{-O0} turns off this optimization.
492 @node i386-Directives
493 @section x86 specific Directives
495 @cindex machine directives, x86
496 @cindex x86 machine directives
499 @cindex @code{lcomm} directive, COFF
500 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
501 Reserve @var{length} (an absolute expression) bytes for a local common
502 denoted by @var{symbol}. The section and value of @var{symbol} are
503 those of the new local common. The addresses are allocated in the bss
504 section, so that at run-time the bytes start off zeroed. Since
505 @var{symbol} is not declared global, it is normally not visible to
506 @code{@value{LD}}. The optional third parameter, @var{alignment},
507 specifies the desired alignment of the symbol in the bss section.
509 This directive is only available for COFF based x86 targets.
511 @cindex @code{largecomm} directive, ELF
512 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
513 This directive behaves in the same way as the @code{comm} directive
514 except that the data is placed into the @var{.lbss} section instead of
515 the @var{.bss} section @ref{Comm}.
517 The directive is intended to be used for data which requires a large
518 amount of space, and it is only available for ELF based x86_64
521 @cindex @code{value} directive
522 @item .value @var{expression} [, @var{expression}]
523 This directive behaves in the same way as the @code{.short} directive,
524 taking a series of comma separated expressions and storing them as
525 two-byte wide values into the current section.
527 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
532 @section i386 Syntactical Considerations
534 * i386-Variations:: AT&T Syntax versus Intel Syntax
535 * i386-Chars:: Special Characters
538 @node i386-Variations
539 @subsection AT&T Syntax versus Intel Syntax
541 @cindex i386 intel_syntax pseudo op
542 @cindex intel_syntax pseudo op, i386
543 @cindex i386 att_syntax pseudo op
544 @cindex att_syntax pseudo op, i386
545 @cindex i386 syntax compatibility
546 @cindex syntax compatibility, i386
547 @cindex x86-64 intel_syntax pseudo op
548 @cindex intel_syntax pseudo op, x86-64
549 @cindex x86-64 att_syntax pseudo op
550 @cindex att_syntax pseudo op, x86-64
551 @cindex x86-64 syntax compatibility
552 @cindex syntax compatibility, x86-64
554 @code{@value{AS}} now supports assembly using Intel assembler syntax.
555 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
556 back to the usual AT&T mode for compatibility with the output of
557 @code{@value{GCC}}. Either of these directives may have an optional
558 argument, @code{prefix}, or @code{noprefix} specifying whether registers
559 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
560 different from Intel syntax. We mention these differences because
561 almost all 80386 documents use Intel syntax. Notable differences
562 between the two syntaxes are:
564 @cindex immediate operands, i386
565 @cindex i386 immediate operands
566 @cindex register operands, i386
567 @cindex i386 register operands
568 @cindex jump/call operands, i386
569 @cindex i386 jump/call operands
570 @cindex operand delimiters, i386
572 @cindex immediate operands, x86-64
573 @cindex x86-64 immediate operands
574 @cindex register operands, x86-64
575 @cindex x86-64 register operands
576 @cindex jump/call operands, x86-64
577 @cindex x86-64 jump/call operands
578 @cindex operand delimiters, x86-64
581 AT&T immediate operands are preceded by @samp{$}; Intel immediate
582 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
583 AT&T register operands are preceded by @samp{%}; Intel register operands
584 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
585 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
587 @cindex i386 source, destination operands
588 @cindex source, destination operands; i386
589 @cindex x86-64 source, destination operands
590 @cindex source, destination operands; x86-64
592 AT&T and Intel syntax use the opposite order for source and destination
593 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
594 @samp{source, dest} convention is maintained for compatibility with
595 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
596 instructions with 2 immediate operands, such as the @samp{enter}
597 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
599 @cindex mnemonic suffixes, i386
600 @cindex sizes operands, i386
601 @cindex i386 size suffixes
602 @cindex mnemonic suffixes, x86-64
603 @cindex sizes operands, x86-64
604 @cindex x86-64 size suffixes
606 In AT&T syntax the size of memory operands is determined from the last
607 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
608 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
609 (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes
610 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
611 (256-bit vector) and zmm (512-bit vector) memory references, only when there's
612 no other way to disambiguate an instruction. Intel syntax accomplishes this by
613 prefixing memory operands (@emph{not} the instruction mnemonics) with
614 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
615 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
616 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
617 syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
618 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
620 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
621 instruction with the 64-bit displacement or immediate operand.
623 @cindex return instructions, i386
624 @cindex i386 jump, call, return
625 @cindex return instructions, x86-64
626 @cindex x86-64 jump, call, return
628 Immediate form long jumps and calls are
629 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
631 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
633 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
634 @samp{ret far @var{stack-adjust}}.
636 @cindex sections, i386
637 @cindex i386 sections
638 @cindex sections, x86-64
639 @cindex x86-64 sections
641 The AT&T assembler does not provide support for multiple section
642 programs. Unix style systems expect all programs to be single sections.
646 @subsection Special Characters
648 @cindex line comment character, i386
649 @cindex i386 line comment character
650 The presence of a @samp{#} appearing anywhere on a line indicates the
651 start of a comment that extends to the end of that line.
653 If a @samp{#} appears as the first character of a line then the whole
654 line is treated as a comment, but in this case the line can also be a
655 logical line number directive (@pxref{Comments}) or a preprocessor
656 control command (@pxref{Preprocessing}).
658 If the @option{--divide} command-line option has not been specified
659 then the @samp{/} character appearing anywhere on a line also
660 introduces a line comment.
662 @cindex line separator, i386
663 @cindex statement separator, i386
664 @cindex i386 line separator
665 The @samp{;} character can be used to separate statements on the same
669 @section i386-Mnemonics
670 @subsection Instruction Naming
672 @cindex i386 instruction naming
673 @cindex instruction naming, i386
674 @cindex x86-64 instruction naming
675 @cindex instruction naming, x86-64
677 Instruction mnemonics are suffixed with one character modifiers which
678 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
679 and @samp{q} specify byte, word, long and quadruple word operands. If
680 no suffix is specified by an instruction then @code{@value{AS}} tries to
681 fill in the missing suffix based on the destination register operand
682 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
683 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
684 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
685 assembler which assumes that a missing mnemonic suffix implies long
686 operand size. (This incompatibility does not affect compiler output
687 since compilers always explicitly specify the mnemonic suffix.)
689 Almost all instructions have the same names in AT&T and Intel format.
690 There are a few exceptions. The sign extend and zero extend
691 instructions need two sizes to specify them. They need a size to
692 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
693 is accomplished by using two instruction mnemonic suffixes in AT&T
694 syntax. Base names for sign extend and zero extend are
695 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
696 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
697 are tacked on to this base name, the @emph{from} suffix before the
698 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
699 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
700 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
701 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
702 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
705 @cindex encoding options, i386
706 @cindex encoding options, x86-64
708 Different encoding options can be specified via pseudo prefixes:
712 @samp{@{disp8@}} -- prefer 8-bit displacement.
715 @samp{@{disp32@}} -- prefer 32-bit displacement.
718 @samp{@{load@}} -- prefer load-form instruction.
721 @samp{@{store@}} -- prefer store-form instruction.
724 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
727 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
730 @samp{@{evex@}} -- encode with EVEX prefix.
733 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
734 instructions (x86-64 only). Note that this differs from the @samp{rex}
735 prefix which generates REX prefix unconditionally.
738 @samp{@{nooptimize@}} -- disable instruction size optimization.
741 @cindex conversion instructions, i386
742 @cindex i386 conversion instructions
743 @cindex conversion instructions, x86-64
744 @cindex x86-64 conversion instructions
745 The Intel-syntax conversion instructions
749 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
752 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
755 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
758 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
761 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
765 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
766 @samp{%rdx:%rax} (x86-64 only),
770 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
771 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
774 @cindex jump instructions, i386
775 @cindex call instructions, i386
776 @cindex jump instructions, x86-64
777 @cindex call instructions, x86-64
778 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
779 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
782 @subsection AT&T Mnemonic versus Intel Mnemonic
784 @cindex i386 mnemonic compatibility
785 @cindex mnemonic compatibility, i386
787 @code{@value{AS}} supports assembly using Intel mnemonic.
788 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
789 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
790 syntax for compatibility with the output of @code{@value{GCC}}.
791 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
792 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
793 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
794 assembler with different mnemonics from those in Intel IA32 specification.
795 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
798 @section Register Naming
800 @cindex i386 registers
801 @cindex registers, i386
802 @cindex x86-64 registers
803 @cindex registers, x86-64
804 Register operands are always prefixed with @samp{%}. The 80386 registers
809 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
810 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
811 frame pointer), and @samp{%esp} (the stack pointer).
814 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
815 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
818 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
819 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
820 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
821 @samp{%cx}, and @samp{%dx})
824 the 6 section registers @samp{%cs} (code section), @samp{%ds}
825 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
829 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
830 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
833 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
834 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
837 the 2 test registers @samp{%tr6} and @samp{%tr7}.
840 the 8 floating point register stack @samp{%st} or equivalently
841 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
842 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
843 These registers are overloaded by 8 MMX registers @samp{%mm0},
844 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
845 @samp{%mm6} and @samp{%mm7}.
848 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
849 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
852 The AMD x86-64 architecture extends the register set by:
856 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
857 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
858 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
862 the 8 extended registers @samp{%r8}--@samp{%r15}.
865 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
868 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
871 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
874 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
877 the 8 debug registers: @samp{%db8}--@samp{%db15}.
880 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
883 With the AVX extensions more registers were made available:
888 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
889 available in 32-bit mode). The bottom 128 bits are overlaid with the
890 @samp{xmm0}--@samp{xmm15} registers.
894 The AVX2 extensions made in 64-bit mode more registers available:
899 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
900 registers @samp{%ymm16}--@samp{%ymm31}.
904 The AVX512 extensions added the following registers:
909 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
910 available in 32-bit mode). The bottom 128 bits are overlaid with the
911 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
912 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
915 the 8 mask registers @samp{%k0}--@samp{%k7}.
920 @section Instruction Prefixes
922 @cindex i386 instruction prefixes
923 @cindex instruction prefixes, i386
924 @cindex prefixes, i386
925 Instruction prefixes are used to modify the following instruction. They
926 are used to repeat string instructions, to provide section overrides, to
927 perform bus lock operations, and to change operand and address sizes.
928 (Most instructions that normally operate on 32-bit operands will use
929 16-bit operands if the instruction has an ``operand size'' prefix.)
930 Instruction prefixes are best written on the same line as the instruction
931 they act upon. For example, the @samp{scas} (scan string) instruction is
935 repne scas %es:(%edi),%al
938 You may also place prefixes on the lines immediately preceding the
939 instruction, but this circumvents checks that @code{@value{AS}} does
940 with prefixes, and will not work with all prefixes.
942 Here is a list of instruction prefixes:
944 @cindex section override prefixes, i386
947 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
948 @samp{fs}, @samp{gs}. These are automatically added by specifying
949 using the @var{section}:@var{memory-operand} form for memory references.
951 @cindex size prefixes, i386
953 Operand/Address size prefixes @samp{data16} and @samp{addr16}
954 change 32-bit operands/addresses into 16-bit operands/addresses,
955 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
956 @code{.code16} section) into 32-bit operands/addresses. These prefixes
957 @emph{must} appear on the same line of code as the instruction they
958 modify. For example, in a 16-bit @code{.code16} section, you might
965 @cindex bus lock prefixes, i386
966 @cindex inhibiting interrupts, i386
968 The bus lock prefix @samp{lock} inhibits interrupts during execution of
969 the instruction it precedes. (This is only valid with certain
970 instructions; see a 80386 manual for details).
972 @cindex coprocessor wait, i386
974 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
975 complete the current instruction. This should never be needed for the
976 80386/80387 combination.
978 @cindex repeat prefixes, i386
980 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
981 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
982 times if the current address size is 16-bits).
983 @cindex REX prefixes, i386
985 The @samp{rex} family of prefixes is used by x86-64 to encode
986 extensions to i386 instruction set. The @samp{rex} prefix has four
987 bits --- an operand size overwrite (@code{64}) used to change operand size
988 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
991 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
992 instruction emits @samp{rex} prefix with all the bits set. By omitting
993 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
994 prefixes as well. Normally, there is no need to write the prefixes
995 explicitly, since gas will automatically generate them based on the
996 instruction operands.
1000 @section Memory References
1002 @cindex i386 memory references
1003 @cindex memory references, i386
1004 @cindex x86-64 memory references
1005 @cindex memory references, x86-64
1006 An Intel syntax indirect memory reference of the form
1009 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
1013 is translated into the AT&T syntax
1016 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
1020 where @var{base} and @var{index} are the optional 32-bit base and
1021 index registers, @var{disp} is the optional displacement, and
1022 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
1023 to calculate the address of the operand. If no @var{scale} is
1024 specified, @var{scale} is taken to be 1. @var{section} specifies the
1025 optional section register for the memory operand, and may override the
1026 default section register (see a 80386 manual for section register
1027 defaults). Note that section overrides in AT&T syntax @emph{must}
1028 be preceded by a @samp{%}. If you specify a section override which
1029 coincides with the default section register, @code{@value{AS}} does @emph{not}
1030 output any section register override prefixes to assemble the given
1031 instruction. Thus, section overrides can be specified to emphasize which
1032 section register is used for a given memory operand.
1034 Here are some examples of Intel and AT&T style memory references:
1037 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1038 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1039 missing, and the default section is used (@samp{%ss} for addressing with
1040 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1042 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1043 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1044 @samp{foo}. All other fields are missing. The section register here
1045 defaults to @samp{%ds}.
1047 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1048 This uses the value pointed to by @samp{foo} as a memory operand.
1049 Note that @var{base} and @var{index} are both missing, but there is only
1050 @emph{one} @samp{,}. This is a syntactic exception.
1052 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1053 This selects the contents of the variable @samp{foo} with section
1054 register @var{section} being @samp{%gs}.
1057 Absolute (as opposed to PC relative) call and jump operands must be
1058 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1059 always chooses PC relative addressing for jump/call labels.
1061 Any instruction that has a memory operand, but no register operand,
1062 @emph{must} specify its size (byte, word, long, or quadruple) with an
1063 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1066 The x86-64 architecture adds an RIP (instruction pointer relative)
1067 addressing. This addressing mode is specified by using @samp{rip} as a
1068 base register. Only constant offsets are valid. For example:
1071 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1072 Points to the address 1234 bytes past the end of the current
1075 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1076 Points to the @code{symbol} in RIP relative way, this is shorter than
1077 the default absolute addressing.
1080 Other addressing modes remain unchanged in x86-64 architecture, except
1081 registers used are 64-bit instead of 32-bit.
1084 @section Handling of Jump Instructions
1086 @cindex jump optimization, i386
1087 @cindex i386 jump optimization
1088 @cindex jump optimization, x86-64
1089 @cindex x86-64 jump optimization
1090 Jump instructions are always optimized to use the smallest possible
1091 displacements. This is accomplished by using byte (8-bit) displacement
1092 jumps whenever the target is sufficiently close. If a byte displacement
1093 is insufficient a long displacement is used. We do not support
1094 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1095 instruction with the @samp{data16} instruction prefix), since the 80386
1096 insists upon masking @samp{%eip} to 16 bits after the word displacement
1097 is added. (See also @pxref{i386-Arch})
1099 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1100 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1101 displacements, so that if you use these instructions (@code{@value{GCC}} does
1102 not use them) you may get an error message (and incorrect code). The AT&T
1103 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1114 @section Floating Point
1116 @cindex i386 floating point
1117 @cindex floating point, i386
1118 @cindex x86-64 floating point
1119 @cindex floating point, x86-64
1120 All 80387 floating point types except packed BCD are supported.
1121 (BCD support may be added without much difficulty). These data
1122 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1123 double (64-bit), and extended (80-bit) precision floating point.
1124 Each supported type has an instruction mnemonic suffix and a constructor
1125 associated with it. Instruction mnemonic suffixes specify the operand's
1126 data type. Constructors build these data types into memory.
1128 @cindex @code{float} directive, i386
1129 @cindex @code{single} directive, i386
1130 @cindex @code{double} directive, i386
1131 @cindex @code{tfloat} directive, i386
1132 @cindex @code{float} directive, x86-64
1133 @cindex @code{single} directive, x86-64
1134 @cindex @code{double} directive, x86-64
1135 @cindex @code{tfloat} directive, x86-64
1138 Floating point constructors are @samp{.float} or @samp{.single},
1139 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1140 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1141 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1142 only supports this format via the @samp{fldt} (load 80-bit real to stack
1143 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1145 @cindex @code{word} directive, i386
1146 @cindex @code{long} directive, i386
1147 @cindex @code{int} directive, i386
1148 @cindex @code{quad} directive, i386
1149 @cindex @code{word} directive, x86-64
1150 @cindex @code{long} directive, x86-64
1151 @cindex @code{int} directive, x86-64
1152 @cindex @code{quad} directive, x86-64
1154 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1155 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1156 corresponding instruction mnemonic suffixes are @samp{s} (single),
1157 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1158 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1159 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1160 stack) instructions.
1163 Register to register operations should not use instruction mnemonic suffixes.
1164 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1165 wrote @samp{fst %st, %st(1)}, since all register to register operations
1166 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1167 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1168 then stores the result in the 4 byte location @samp{mem})
1171 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1174 @cindex 3DNow!, i386
1177 @cindex 3DNow!, x86-64
1178 @cindex SIMD, x86-64
1180 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1181 instructions for integer data), available on Intel's Pentium MMX
1182 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1183 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1184 instruction set (SIMD instructions for 32-bit floating point data)
1185 available on AMD's K6-2 processor and possibly others in the future.
1187 Currently, @code{@value{AS}} does not support Intel's floating point
1190 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1191 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1192 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1193 floating point values. The MMX registers cannot be used at the same time
1194 as the floating point stack.
1196 See Intel and AMD documentation, keeping in mind that the operand order in
1197 instructions is reversed from the Intel syntax.
1200 @section AMD's Lightweight Profiling Instructions
1205 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1206 instruction set, available on AMD's Family 15h (Orochi) processors.
1208 LWP enables applications to collect and manage performance data, and
1209 react to performance events. The collection of performance data
1210 requires no context switches. LWP runs in the context of a thread and
1211 so several counters can be used independently across multiple threads.
1212 LWP can be used in both 64-bit and legacy 32-bit modes.
1214 For detailed information on the LWP instruction set, see the
1215 @cite{AMD Lightweight Profiling Specification} available at
1216 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1219 @section Bit Manipulation Instructions
1224 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1226 BMI instructions provide several instructions implementing individual
1227 bit manipulation operations such as isolation, masking, setting, or
1230 @c Need to add a specification citation here when available.
1233 @section AMD's Trailing Bit Manipulation Instructions
1238 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1239 instruction set, available on AMD's BDVER2 processors (Trinity and
1242 TBM instructions provide instructions implementing individual bit
1243 manipulation operations such as isolating, masking, setting, resetting,
1244 complementing, and operations on trailing zeros and ones.
1246 @c Need to add a specification citation here when available.
1249 @section Writing 16-bit Code
1251 @cindex i386 16-bit code
1252 @cindex 16-bit code, i386
1253 @cindex real-mode code, i386
1254 @cindex @code{code16gcc} directive, i386
1255 @cindex @code{code16} directive, i386
1256 @cindex @code{code32} directive, i386
1257 @cindex @code{code64} directive, i386
1258 @cindex @code{code64} directive, x86-64
1259 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1260 or 64-bit x86-64 code depending on the default configuration,
1261 it also supports writing code to run in real mode or in 16-bit protected
1262 mode code segments. To do this, put a @samp{.code16} or
1263 @samp{.code16gcc} directive before the assembly language instructions to
1264 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1265 32-bit code with the @samp{.code32} directive or 64-bit code with the
1266 @samp{.code64} directive.
1268 @samp{.code16gcc} provides experimental support for generating 16-bit
1269 code from gcc, and differs from @samp{.code16} in that @samp{call},
1270 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1271 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1272 default to 32-bit size. This is so that the stack pointer is
1273 manipulated in the same way over function calls, allowing access to
1274 function parameters at the same stack offsets as in 32-bit mode.
1275 @samp{.code16gcc} also automatically adds address size prefixes where
1276 necessary to use the 32-bit addressing modes that gcc generates.
1278 The code which @code{@value{AS}} generates in 16-bit mode will not
1279 necessarily run on a 16-bit pre-80386 processor. To write code that
1280 runs on such a processor, you must refrain from using @emph{any} 32-bit
1281 constructs which require @code{@value{AS}} to output address or operand
1284 Note that writing 16-bit code instructions by explicitly specifying a
1285 prefix or an instruction mnemonic suffix within a 32-bit code section
1286 generates different machine instructions than those generated for a
1287 16-bit code segment. In a 32-bit code section, the following code
1288 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1289 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1295 The same code in a 16-bit code section would generate the machine
1296 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1297 is correct since the processor default operand size is assumed to be 16
1298 bits in a 16-bit code section.
1301 @section Specifying CPU Architecture
1303 @cindex arch directive, i386
1304 @cindex i386 arch directive
1305 @cindex arch directive, x86-64
1306 @cindex x86-64 arch directive
1308 @code{@value{AS}} may be told to assemble for a particular CPU
1309 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1310 directive enables a warning when gas detects an instruction that is not
1311 supported on the CPU specified. The choices for @var{cpu_type} are:
1313 @multitable @columnfractions .20 .20 .20 .20
1314 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1315 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1316 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1317 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1318 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
1319 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1320 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1321 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1322 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1323 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1324 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1325 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1326 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1327 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1328 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1329 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1330 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1331 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1332 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1333 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1334 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1335 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1336 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1337 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1338 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1339 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1340 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1341 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1342 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd}
1343 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1344 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1345 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1346 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
1347 @item @samp{.mcommit}
1350 Apart from the warning, there are only two other effects on
1351 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1352 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1353 will automatically use a two byte opcode sequence. The larger three
1354 byte opcode sequence is used on the 486 (and when no architecture is
1355 specified) because it executes faster on the 486. Note that you can
1356 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1357 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1358 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1359 conditional jumps will be promoted when necessary to a two instruction
1360 sequence consisting of a conditional jump of the opposite sense around
1361 an unconditional jump to the target.
1363 Following the CPU architecture (but not a sub-architecture, which are those
1364 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1365 control automatic promotion of conditional jumps. @samp{jumps} is the
1366 default, and enables jump promotion; All external jumps will be of the long
1367 variety, and file-local jumps will be promoted as necessary.
1368 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1369 byte offset jumps, and warns about file-local conditional jumps that
1370 @code{@value{AS}} promotes.
1371 Unconditional jumps are treated as for @samp{jumps}.
1380 @section AT&T Syntax bugs
1382 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1383 assemblers, generate floating point instructions with reversed source
1384 and destination registers in certain cases. Unfortunately, gcc and
1385 possibly many other programs use this reversed syntax, so we're stuck
1394 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1395 than the expected @samp{%st(3) - %st}. This happens with all the
1396 non-commutative arithmetic floating point operations with two register
1397 operands where the source register is @samp{%st} and the destination
1398 register is @samp{%st(i)}.
1403 @cindex i386 @code{mul}, @code{imul} instructions
1404 @cindex @code{mul} instruction, i386
1405 @cindex @code{imul} instruction, i386
1406 @cindex @code{mul} instruction, x86-64
1407 @cindex @code{imul} instruction, x86-64
1408 There is some trickery concerning the @samp{mul} and @samp{imul}
1409 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1410 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1411 for @samp{imul}) can be output only in the one operand form. Thus,
1412 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1413 the expanding multiply would clobber the @samp{%edx} register, and this
1414 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1415 64-bit product in @samp{%edx:%eax}.
1417 We have added a two operand form of @samp{imul} when the first operand
1418 is an immediate mode expression and the second operand is a register.
1419 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1420 example, can be done with @samp{imul $69, %eax} rather than @samp{imul