1 @c Copyright (C) 1991-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
130 In addition to the basic instruction set, the assembler can be told to
131 accept various extension mnemonics. For example,
132 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
133 @var{vmx}. The following extensions are currently supported:
206 Note that rather than extending a basic instruction set, the extension
207 mnemonics starting with @code{no} revoke the respective functionality.
209 When the @code{.arch} directive is used with @option{-march}, the
210 @code{.arch} directive will take precedent.
212 @cindex @samp{-mtune=} option, i386
213 @cindex @samp{-mtune=} option, x86-64
214 @item -mtune=@var{CPU}
215 This option specifies a processor to optimize for. When used in
216 conjunction with the @option{-march} option, only instructions
217 of the processor specified by the @option{-march} option will be
220 Valid @var{CPU} values are identical to the processor list of
221 @option{-march=@var{CPU}}.
223 @cindex @samp{-msse2avx} option, i386
224 @cindex @samp{-msse2avx} option, x86-64
226 This option specifies that the assembler should encode SSE instructions
229 @cindex @samp{-msse-check=} option, i386
230 @cindex @samp{-msse-check=} option, x86-64
231 @item -msse-check=@var{none}
232 @itemx -msse-check=@var{warning}
233 @itemx -msse-check=@var{error}
234 These options control if the assembler should check SSE instructions.
235 @option{-msse-check=@var{none}} will make the assembler not to check SSE
236 instructions, which is the default. @option{-msse-check=@var{warning}}
237 will make the assembler issue a warning for any SSE instruction.
238 @option{-msse-check=@var{error}} will make the assembler issue an error
239 for any SSE instruction.
241 @cindex @samp{-mavxscalar=} option, i386
242 @cindex @samp{-mavxscalar=} option, x86-64
243 @item -mavxscalar=@var{128}
244 @itemx -mavxscalar=@var{256}
245 These options control how the assembler should encode scalar AVX
246 instructions. @option{-mavxscalar=@var{128}} will encode scalar
247 AVX instructions with 128bit vector length, which is the default.
248 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
249 with 256bit vector length.
251 @cindex @samp{-mevexlig=} option, i386
252 @cindex @samp{-mevexlig=} option, x86-64
253 @item -mevexlig=@var{128}
254 @itemx -mevexlig=@var{256}
255 @itemx -mevexlig=@var{512}
256 These options control how the assembler should encode length-ignored
257 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
258 EVEX instructions with 128bit vector length, which is the default.
259 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
260 encode LIG EVEX instructions with 256bit and 512bit vector length,
263 @cindex @samp{-mevexwig=} option, i386
264 @cindex @samp{-mevexwig=} option, x86-64
265 @item -mevexwig=@var{0}
266 @itemx -mevexwig=@var{1}
267 These options control how the assembler should encode w-ignored (WIG)
268 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
269 EVEX instructions with evex.w = 0, which is the default.
270 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
273 @cindex @samp{-mmnemonic=} option, i386
274 @cindex @samp{-mmnemonic=} option, x86-64
275 @item -mmnemonic=@var{att}
276 @itemx -mmnemonic=@var{intel}
277 This option specifies instruction mnemonic for matching instructions.
278 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
281 @cindex @samp{-msyntax=} option, i386
282 @cindex @samp{-msyntax=} option, x86-64
283 @item -msyntax=@var{att}
284 @itemx -msyntax=@var{intel}
285 This option specifies instruction syntax when processing instructions.
286 The @code{.att_syntax} and @code{.intel_syntax} directives will
289 @cindex @samp{-mnaked-reg} option, i386
290 @cindex @samp{-mnaked-reg} option, x86-64
292 This opetion specifies that registers don't require a @samp{%} prefix.
293 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
295 @cindex @samp{-madd-bnd-prefix} option, i386
296 @cindex @samp{-madd-bnd-prefix} option, x86-64
297 @item -madd-bnd-prefix
298 This option forces the assembler to add BND prefix to all branches, even
299 if such prefix was not explicitly specified in the source code.
301 @cindex @samp{-mshared} option, i386
302 @cindex @samp{-mshared} option, x86-64
304 On ELF target, the assembler normally optimizes out non-PLT relocations
305 against defined non-weak global branch targets with default visibility.
306 The @samp{-mshared} option tells the assembler to generate code which
307 may go into a shared library where all non-weak global branch targets
308 with default visibility can be preempted. The resulting code is
309 slightly bigger. This option only affects the handling of branch
312 @cindex @samp{-mbig-obj} option, x86-64
314 On x86-64 PE/COFF target this option forces the use of big object file
315 format, which allows more than 32768 sections.
317 @cindex @samp{-momit-lock-prefix=} option, i386
318 @cindex @samp{-momit-lock-prefix=} option, x86-64
319 @item -momit-lock-prefix=@var{no}
320 @itemx -momit-lock-prefix=@var{yes}
321 These options control how the assembler should encode lock prefix.
322 This option is intended as a workaround for processors, that fail on
323 lock prefix. This option can only be safely used with single-core,
324 single-thread computers
325 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
326 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
327 which is the default.
329 @cindex @samp{-mevexrcig=} option, i386
330 @cindex @samp{-mevexrcig=} option, x86-64
331 @item -mevexrcig=@var{rne}
332 @itemx -mevexrcig=@var{rd}
333 @itemx -mevexrcig=@var{ru}
334 @itemx -mevexrcig=@var{rz}
335 These options control how the assembler should encode SAE-only
336 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
337 of EVEX instruction with 00, which is the default.
338 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
339 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
340 with 01, 10 and 11 RC bits, respectively.
342 @cindex @samp{-mamd64} option, x86-64
343 @cindex @samp{-mintel64} option, x86-64
346 This option specifies that the assembler should accept only AMD64 or
347 Intel64 ISA in 64-bit mode. The default is to accept both.
352 @node i386-Directives
353 @section x86 specific Directives
355 @cindex machine directives, x86
356 @cindex x86 machine directives
359 @cindex @code{lcomm} directive, COFF
360 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
361 Reserve @var{length} (an absolute expression) bytes for a local common
362 denoted by @var{symbol}. The section and value of @var{symbol} are
363 those of the new local common. The addresses are allocated in the bss
364 section, so that at run-time the bytes start off zeroed. Since
365 @var{symbol} is not declared global, it is normally not visible to
366 @code{@value{LD}}. The optional third parameter, @var{alignment},
367 specifies the desired alignment of the symbol in the bss section.
369 This directive is only available for COFF based x86 targets.
371 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
377 @section i386 Syntactical Considerations
379 * i386-Variations:: AT&T Syntax versus Intel Syntax
380 * i386-Chars:: Special Characters
383 @node i386-Variations
384 @subsection AT&T Syntax versus Intel Syntax
386 @cindex i386 intel_syntax pseudo op
387 @cindex intel_syntax pseudo op, i386
388 @cindex i386 att_syntax pseudo op
389 @cindex att_syntax pseudo op, i386
390 @cindex i386 syntax compatibility
391 @cindex syntax compatibility, i386
392 @cindex x86-64 intel_syntax pseudo op
393 @cindex intel_syntax pseudo op, x86-64
394 @cindex x86-64 att_syntax pseudo op
395 @cindex att_syntax pseudo op, x86-64
396 @cindex x86-64 syntax compatibility
397 @cindex syntax compatibility, x86-64
399 @code{@value{AS}} now supports assembly using Intel assembler syntax.
400 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
401 back to the usual AT&T mode for compatibility with the output of
402 @code{@value{GCC}}. Either of these directives may have an optional
403 argument, @code{prefix}, or @code{noprefix} specifying whether registers
404 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
405 different from Intel syntax. We mention these differences because
406 almost all 80386 documents use Intel syntax. Notable differences
407 between the two syntaxes are:
409 @cindex immediate operands, i386
410 @cindex i386 immediate operands
411 @cindex register operands, i386
412 @cindex i386 register operands
413 @cindex jump/call operands, i386
414 @cindex i386 jump/call operands
415 @cindex operand delimiters, i386
417 @cindex immediate operands, x86-64
418 @cindex x86-64 immediate operands
419 @cindex register operands, x86-64
420 @cindex x86-64 register operands
421 @cindex jump/call operands, x86-64
422 @cindex x86-64 jump/call operands
423 @cindex operand delimiters, x86-64
426 AT&T immediate operands are preceded by @samp{$}; Intel immediate
427 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
428 AT&T register operands are preceded by @samp{%}; Intel register operands
429 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
430 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
432 @cindex i386 source, destination operands
433 @cindex source, destination operands; i386
434 @cindex x86-64 source, destination operands
435 @cindex source, destination operands; x86-64
437 AT&T and Intel syntax use the opposite order for source and destination
438 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
439 @samp{source, dest} convention is maintained for compatibility with
440 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
441 instructions with 2 immediate operands, such as the @samp{enter}
442 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
444 @cindex mnemonic suffixes, i386
445 @cindex sizes operands, i386
446 @cindex i386 size suffixes
447 @cindex mnemonic suffixes, x86-64
448 @cindex sizes operands, x86-64
449 @cindex x86-64 size suffixes
451 In AT&T syntax the size of memory operands is determined from the last
452 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
453 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
454 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
455 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
456 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
457 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
460 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
461 instruction with the 64-bit displacement or immediate operand.
463 @cindex return instructions, i386
464 @cindex i386 jump, call, return
465 @cindex return instructions, x86-64
466 @cindex x86-64 jump, call, return
468 Immediate form long jumps and calls are
469 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
471 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
473 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
474 @samp{ret far @var{stack-adjust}}.
476 @cindex sections, i386
477 @cindex i386 sections
478 @cindex sections, x86-64
479 @cindex x86-64 sections
481 The AT&T assembler does not provide support for multiple section
482 programs. Unix style systems expect all programs to be single sections.
486 @subsection Special Characters
488 @cindex line comment character, i386
489 @cindex i386 line comment character
490 The presence of a @samp{#} appearing anywhere on a line indicates the
491 start of a comment that extends to the end of that line.
493 If a @samp{#} appears as the first character of a line then the whole
494 line is treated as a comment, but in this case the line can also be a
495 logical line number directive (@pxref{Comments}) or a preprocessor
496 control command (@pxref{Preprocessing}).
498 If the @option{--divide} command line option has not been specified
499 then the @samp{/} character appearing anywhere on a line also
500 introduces a line comment.
502 @cindex line separator, i386
503 @cindex statement separator, i386
504 @cindex i386 line separator
505 The @samp{;} character can be used to separate statements on the same
509 @section i386-Mnemonics
510 @subsection Instruction Naming
512 @cindex i386 instruction naming
513 @cindex instruction naming, i386
514 @cindex x86-64 instruction naming
515 @cindex instruction naming, x86-64
517 Instruction mnemonics are suffixed with one character modifiers which
518 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
519 and @samp{q} specify byte, word, long and quadruple word operands. If
520 no suffix is specified by an instruction then @code{@value{AS}} tries to
521 fill in the missing suffix based on the destination register operand
522 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
523 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
524 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
525 assembler which assumes that a missing mnemonic suffix implies long
526 operand size. (This incompatibility does not affect compiler output
527 since compilers always explicitly specify the mnemonic suffix.)
529 Almost all instructions have the same names in AT&T and Intel format.
530 There are a few exceptions. The sign extend and zero extend
531 instructions need two sizes to specify them. They need a size to
532 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
533 is accomplished by using two instruction mnemonic suffixes in AT&T
534 syntax. Base names for sign extend and zero extend are
535 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
536 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
537 are tacked on to this base name, the @emph{from} suffix before the
538 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
539 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
540 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
541 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
542 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
545 @cindex encoding options, i386
546 @cindex encoding options, x86-64
548 Different encoding options can be specified via optional mnemonic
549 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
550 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
551 prefers 8bit or 32bit displacement in encoding.
553 @cindex conversion instructions, i386
554 @cindex i386 conversion instructions
555 @cindex conversion instructions, x86-64
556 @cindex x86-64 conversion instructions
557 The Intel-syntax conversion instructions
561 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
564 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
567 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
570 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
573 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
577 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
578 @samp{%rdx:%rax} (x86-64 only),
582 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
583 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
586 @cindex jump instructions, i386
587 @cindex call instructions, i386
588 @cindex jump instructions, x86-64
589 @cindex call instructions, x86-64
590 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
591 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
594 @subsection AT&T Mnemonic versus Intel Mnemonic
596 @cindex i386 mnemonic compatibility
597 @cindex mnemonic compatibility, i386
599 @code{@value{AS}} supports assembly using Intel mnemonic.
600 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
601 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
602 syntax for compatibility with the output of @code{@value{GCC}}.
603 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
604 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
605 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
606 assembler with different mnemonics from those in Intel IA32 specification.
607 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
610 @section Register Naming
612 @cindex i386 registers
613 @cindex registers, i386
614 @cindex x86-64 registers
615 @cindex registers, x86-64
616 Register operands are always prefixed with @samp{%}. The 80386 registers
621 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
622 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
623 frame pointer), and @samp{%esp} (the stack pointer).
626 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
627 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
630 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
631 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
632 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
633 @samp{%cx}, and @samp{%dx})
636 the 6 section registers @samp{%cs} (code section), @samp{%ds}
637 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
641 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
645 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
646 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
649 the 2 test registers @samp{%tr6} and @samp{%tr7}.
652 the 8 floating point register stack @samp{%st} or equivalently
653 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
654 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
655 These registers are overloaded by 8 MMX registers @samp{%mm0},
656 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
657 @samp{%mm6} and @samp{%mm7}.
660 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
661 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
664 The AMD x86-64 architecture extends the register set by:
668 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
669 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
670 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
674 the 8 extended registers @samp{%r8}--@samp{%r15}.
677 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
680 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
683 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
686 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
689 the 8 debug registers: @samp{%db8}--@samp{%db15}.
692 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
696 @section Instruction Prefixes
698 @cindex i386 instruction prefixes
699 @cindex instruction prefixes, i386
700 @cindex prefixes, i386
701 Instruction prefixes are used to modify the following instruction. They
702 are used to repeat string instructions, to provide section overrides, to
703 perform bus lock operations, and to change operand and address sizes.
704 (Most instructions that normally operate on 32-bit operands will use
705 16-bit operands if the instruction has an ``operand size'' prefix.)
706 Instruction prefixes are best written on the same line as the instruction
707 they act upon. For example, the @samp{scas} (scan string) instruction is
711 repne scas %es:(%edi),%al
714 You may also place prefixes on the lines immediately preceding the
715 instruction, but this circumvents checks that @code{@value{AS}} does
716 with prefixes, and will not work with all prefixes.
718 Here is a list of instruction prefixes:
720 @cindex section override prefixes, i386
723 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
724 @samp{fs}, @samp{gs}. These are automatically added by specifying
725 using the @var{section}:@var{memory-operand} form for memory references.
727 @cindex size prefixes, i386
729 Operand/Address size prefixes @samp{data16} and @samp{addr16}
730 change 32-bit operands/addresses into 16-bit operands/addresses,
731 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
732 @code{.code16} section) into 32-bit operands/addresses. These prefixes
733 @emph{must} appear on the same line of code as the instruction they
734 modify. For example, in a 16-bit @code{.code16} section, you might
741 @cindex bus lock prefixes, i386
742 @cindex inhibiting interrupts, i386
744 The bus lock prefix @samp{lock} inhibits interrupts during execution of
745 the instruction it precedes. (This is only valid with certain
746 instructions; see a 80386 manual for details).
748 @cindex coprocessor wait, i386
750 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
751 complete the current instruction. This should never be needed for the
752 80386/80387 combination.
754 @cindex repeat prefixes, i386
756 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
757 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
758 times if the current address size is 16-bits).
759 @cindex REX prefixes, i386
761 The @samp{rex} family of prefixes is used by x86-64 to encode
762 extensions to i386 instruction set. The @samp{rex} prefix has four
763 bits --- an operand size overwrite (@code{64}) used to change operand size
764 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
767 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
768 instruction emits @samp{rex} prefix with all the bits set. By omitting
769 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
770 prefixes as well. Normally, there is no need to write the prefixes
771 explicitly, since gas will automatically generate them based on the
772 instruction operands.
776 @section Memory References
778 @cindex i386 memory references
779 @cindex memory references, i386
780 @cindex x86-64 memory references
781 @cindex memory references, x86-64
782 An Intel syntax indirect memory reference of the form
785 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
789 is translated into the AT&T syntax
792 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
796 where @var{base} and @var{index} are the optional 32-bit base and
797 index registers, @var{disp} is the optional displacement, and
798 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
799 to calculate the address of the operand. If no @var{scale} is
800 specified, @var{scale} is taken to be 1. @var{section} specifies the
801 optional section register for the memory operand, and may override the
802 default section register (see a 80386 manual for section register
803 defaults). Note that section overrides in AT&T syntax @emph{must}
804 be preceded by a @samp{%}. If you specify a section override which
805 coincides with the default section register, @code{@value{AS}} does @emph{not}
806 output any section register override prefixes to assemble the given
807 instruction. Thus, section overrides can be specified to emphasize which
808 section register is used for a given memory operand.
810 Here are some examples of Intel and AT&T style memory references:
813 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
814 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
815 missing, and the default section is used (@samp{%ss} for addressing with
816 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
818 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
819 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
820 @samp{foo}. All other fields are missing. The section register here
821 defaults to @samp{%ds}.
823 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
824 This uses the value pointed to by @samp{foo} as a memory operand.
825 Note that @var{base} and @var{index} are both missing, but there is only
826 @emph{one} @samp{,}. This is a syntactic exception.
828 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
829 This selects the contents of the variable @samp{foo} with section
830 register @var{section} being @samp{%gs}.
833 Absolute (as opposed to PC relative) call and jump operands must be
834 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
835 always chooses PC relative addressing for jump/call labels.
837 Any instruction that has a memory operand, but no register operand,
838 @emph{must} specify its size (byte, word, long, or quadruple) with an
839 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
842 The x86-64 architecture adds an RIP (instruction pointer relative)
843 addressing. This addressing mode is specified by using @samp{rip} as a
844 base register. Only constant offsets are valid. For example:
847 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
848 Points to the address 1234 bytes past the end of the current
851 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
852 Points to the @code{symbol} in RIP relative way, this is shorter than
853 the default absolute addressing.
856 Other addressing modes remain unchanged in x86-64 architecture, except
857 registers used are 64-bit instead of 32-bit.
860 @section Handling of Jump Instructions
862 @cindex jump optimization, i386
863 @cindex i386 jump optimization
864 @cindex jump optimization, x86-64
865 @cindex x86-64 jump optimization
866 Jump instructions are always optimized to use the smallest possible
867 displacements. This is accomplished by using byte (8-bit) displacement
868 jumps whenever the target is sufficiently close. If a byte displacement
869 is insufficient a long displacement is used. We do not support
870 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
871 instruction with the @samp{data16} instruction prefix), since the 80386
872 insists upon masking @samp{%eip} to 16 bits after the word displacement
873 is added. (See also @pxref{i386-Arch})
875 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
876 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
877 displacements, so that if you use these instructions (@code{@value{GCC}} does
878 not use them) you may get an error message (and incorrect code). The AT&T
879 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
890 @section Floating Point
892 @cindex i386 floating point
893 @cindex floating point, i386
894 @cindex x86-64 floating point
895 @cindex floating point, x86-64
896 All 80387 floating point types except packed BCD are supported.
897 (BCD support may be added without much difficulty). These data
898 types are 16-, 32-, and 64- bit integers, and single (32-bit),
899 double (64-bit), and extended (80-bit) precision floating point.
900 Each supported type has an instruction mnemonic suffix and a constructor
901 associated with it. Instruction mnemonic suffixes specify the operand's
902 data type. Constructors build these data types into memory.
904 @cindex @code{float} directive, i386
905 @cindex @code{single} directive, i386
906 @cindex @code{double} directive, i386
907 @cindex @code{tfloat} directive, i386
908 @cindex @code{float} directive, x86-64
909 @cindex @code{single} directive, x86-64
910 @cindex @code{double} directive, x86-64
911 @cindex @code{tfloat} directive, x86-64
914 Floating point constructors are @samp{.float} or @samp{.single},
915 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
916 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
917 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
918 only supports this format via the @samp{fldt} (load 80-bit real to stack
919 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
921 @cindex @code{word} directive, i386
922 @cindex @code{long} directive, i386
923 @cindex @code{int} directive, i386
924 @cindex @code{quad} directive, i386
925 @cindex @code{word} directive, x86-64
926 @cindex @code{long} directive, x86-64
927 @cindex @code{int} directive, x86-64
928 @cindex @code{quad} directive, x86-64
930 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
931 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
932 corresponding instruction mnemonic suffixes are @samp{s} (single),
933 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
934 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
935 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
939 Register to register operations should not use instruction mnemonic suffixes.
940 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
941 wrote @samp{fst %st, %st(1)}, since all register to register operations
942 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
943 which converts @samp{%st} from 80-bit to 64-bit floating point format,
944 then stores the result in the 4 byte location @samp{mem})
947 @section Intel's MMX and AMD's 3DNow! SIMD Operations
953 @cindex 3DNow!, x86-64
956 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
957 instructions for integer data), available on Intel's Pentium MMX
958 processors and Pentium II processors, AMD's K6 and K6-2 processors,
959 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
960 instruction set (SIMD instructions for 32-bit floating point data)
961 available on AMD's K6-2 processor and possibly others in the future.
963 Currently, @code{@value{AS}} does not support Intel's floating point
966 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
967 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
968 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
969 floating point values. The MMX registers cannot be used at the same time
970 as the floating point stack.
972 See Intel and AMD documentation, keeping in mind that the operand order in
973 instructions is reversed from the Intel syntax.
976 @section AMD's Lightweight Profiling Instructions
981 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
982 instruction set, available on AMD's Family 15h (Orochi) processors.
984 LWP enables applications to collect and manage performance data, and
985 react to performance events. The collection of performance data
986 requires no context switches. LWP runs in the context of a thread and
987 so several counters can be used independently across multiple threads.
988 LWP can be used in both 64-bit and legacy 32-bit modes.
990 For detailed information on the LWP instruction set, see the
991 @cite{AMD Lightweight Profiling Specification} available at
992 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
995 @section Bit Manipulation Instructions
1000 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1002 BMI instructions provide several instructions implementing individual
1003 bit manipulation operations such as isolation, masking, setting, or
1006 @c Need to add a specification citation here when available.
1009 @section AMD's Trailing Bit Manipulation Instructions
1014 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1015 instruction set, available on AMD's BDVER2 processors (Trinity and
1018 TBM instructions provide instructions implementing individual bit
1019 manipulation operations such as isolating, masking, setting, resetting,
1020 complementing, and operations on trailing zeros and ones.
1022 @c Need to add a specification citation here when available.
1025 @section Writing 16-bit Code
1027 @cindex i386 16-bit code
1028 @cindex 16-bit code, i386
1029 @cindex real-mode code, i386
1030 @cindex @code{code16gcc} directive, i386
1031 @cindex @code{code16} directive, i386
1032 @cindex @code{code32} directive, i386
1033 @cindex @code{code64} directive, i386
1034 @cindex @code{code64} directive, x86-64
1035 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1036 or 64-bit x86-64 code depending on the default configuration,
1037 it also supports writing code to run in real mode or in 16-bit protected
1038 mode code segments. To do this, put a @samp{.code16} or
1039 @samp{.code16gcc} directive before the assembly language instructions to
1040 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1041 32-bit code with the @samp{.code32} directive or 64-bit code with the
1042 @samp{.code64} directive.
1044 @samp{.code16gcc} provides experimental support for generating 16-bit
1045 code from gcc, and differs from @samp{.code16} in that @samp{call},
1046 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1047 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1048 default to 32-bit size. This is so that the stack pointer is
1049 manipulated in the same way over function calls, allowing access to
1050 function parameters at the same stack offsets as in 32-bit mode.
1051 @samp{.code16gcc} also automatically adds address size prefixes where
1052 necessary to use the 32-bit addressing modes that gcc generates.
1054 The code which @code{@value{AS}} generates in 16-bit mode will not
1055 necessarily run on a 16-bit pre-80386 processor. To write code that
1056 runs on such a processor, you must refrain from using @emph{any} 32-bit
1057 constructs which require @code{@value{AS}} to output address or operand
1060 Note that writing 16-bit code instructions by explicitly specifying a
1061 prefix or an instruction mnemonic suffix within a 32-bit code section
1062 generates different machine instructions than those generated for a
1063 16-bit code segment. In a 32-bit code section, the following code
1064 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1065 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1071 The same code in a 16-bit code section would generate the machine
1072 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1073 is correct since the processor default operand size is assumed to be 16
1074 bits in a 16-bit code section.
1077 @section Specifying CPU Architecture
1079 @cindex arch directive, i386
1080 @cindex i386 arch directive
1081 @cindex arch directive, x86-64
1082 @cindex x86-64 arch directive
1084 @code{@value{AS}} may be told to assemble for a particular CPU
1085 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1086 directive enables a warning when gas detects an instruction that is not
1087 supported on the CPU specified. The choices for @var{cpu_type} are:
1089 @multitable @columnfractions .20 .20 .20 .20
1090 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1091 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1092 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1093 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1094 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1095 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1096 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1097 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1098 @item @samp{generic32} @tab @samp{generic64}
1099 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1100 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1101 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1102 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1103 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1104 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1105 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1106 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1107 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1108 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1109 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1110 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1111 @item @samp{.avx512vbmi} @tab @samp{.clwb} @tab @samp{.pcommit}
1112 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1113 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1114 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1115 @item @samp{.padlock} @tab @samp{.clzero}
1118 Apart from the warning, there are only two other effects on
1119 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1120 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1121 will automatically use a two byte opcode sequence. The larger three
1122 byte opcode sequence is used on the 486 (and when no architecture is
1123 specified) because it executes faster on the 486. Note that you can
1124 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1125 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1126 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1127 conditional jumps will be promoted when necessary to a two instruction
1128 sequence consisting of a conditional jump of the opposite sense around
1129 an unconditional jump to the target.
1131 Following the CPU architecture (but not a sub-architecture, which are those
1132 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1133 control automatic promotion of conditional jumps. @samp{jumps} is the
1134 default, and enables jump promotion; All external jumps will be of the long
1135 variety, and file-local jumps will be promoted as necessary.
1136 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1137 byte offset jumps, and warns about file-local conditional jumps that
1138 @code{@value{AS}} promotes.
1139 Unconditional jumps are treated as for @samp{jumps}.
1148 @section AT&T Syntax bugs
1150 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1151 assemblers, generate floating point instructions with reversed source
1152 and destination registers in certain cases. Unfortunately, gcc and
1153 possibly many other programs use this reversed syntax, so we're stuck
1162 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1163 than the expected @samp{%st(3) - %st}. This happens with all the
1164 non-commutative arithmetic floating point operations with two register
1165 operands where the source register is @samp{%st} and the destination
1166 register is @samp{%st(i)}.
1171 @cindex i386 @code{mul}, @code{imul} instructions
1172 @cindex @code{mul} instruction, i386
1173 @cindex @code{imul} instruction, i386
1174 @cindex @code{mul} instruction, x86-64
1175 @cindex @code{imul} instruction, x86-64
1176 There is some trickery concerning the @samp{mul} and @samp{imul}
1177 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1178 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1179 for @samp{imul}) can be output only in the one operand form. Thus,
1180 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1181 the expanding multiply would clobber the @samp{%edx} register, and this
1182 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1183 64-bit product in @samp{%edx:%eax}.
1185 We have added a two operand form of @samp{imul} when the first operand
1186 is an immediate mode expression and the second operand is a register.
1187 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1188 example, can be done with @samp{imul $69, %eax} rather than @samp{imul