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1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
2 @c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
6 @c man end
7
8 @ifset GENERIC
9 @page
10 @node i386-Dependent
11 @chapter 80386 Dependent Features
12 @end ifset
13 @ifclear GENERIC
14 @node Machine Dependencies
15 @chapter 80386 Dependent Features
16 @end ifclear
17
18 @cindex i386 support
19 @cindex i80386 support
20 @cindex x86-64 support
21
22 The i386 version @code{@value{AS}} supports both the original Intel 386
23 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
24 extending the Intel architecture to 64-bits.
25
26 @menu
27 * i386-Options:: Options
28 * i386-Directives:: X86 specific directives
29 * i386-Syntax:: Syntactical considerations
30 * i386-Mnemonics:: Instruction Naming
31 * i386-Regs:: Register Naming
32 * i386-Prefixes:: Instruction Prefixes
33 * i386-Memory:: Memory References
34 * i386-Jumps:: Handling of Jump Instructions
35 * i386-Float:: Floating Point
36 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
37 * i386-LWP:: AMD's Lightweight Profiling Instructions
38 * i386-BMI:: Bit Manipulation Instruction
39 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
40 * i386-16bit:: Writing 16-bit Code
41 * i386-Arch:: Specifying an x86 CPU architecture
42 * i386-Bugs:: AT&T Syntax bugs
43 * i386-Notes:: Notes
44 @end menu
45
46 @node i386-Options
47 @section Options
48
49 @cindex options for i386
50 @cindex options for x86-64
51 @cindex i386 options
52 @cindex x86-64 options
53
54 The i386 version of @code{@value{AS}} has a few machine
55 dependent options:
56
57 @c man begin OPTIONS
58 @table @gcctabopt
59 @cindex @samp{--32} option, i386
60 @cindex @samp{--32} option, x86-64
61 @cindex @samp{--x32} option, i386
62 @cindex @samp{--x32} option, x86-64
63 @cindex @samp{--64} option, i386
64 @cindex @samp{--64} option, x86-64
65 @item --32 | --x32 | --64
66 Select the word size, either 32 bits or 64 bits. @samp{--32}
67 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
68 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 respectively.
70
71 These options are only available with the ELF object file format, and
72 require that the necessary BFD support has been included (on a 32-bit
73 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
74 usage and use x86-64 as target platform).
75
76 @item -n
77 By default, x86 GAS replaces multiple nop instructions used for
78 alignment within code sections with multi-byte nop instructions such
79 as leal 0(%esi,1),%esi. This switch disables the optimization.
80
81 @cindex @samp{--divide} option, i386
82 @item --divide
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
88
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
96 @code{i8086},
97 @code{i186},
98 @code{i286},
99 @code{i386},
100 @code{i486},
101 @code{i586},
102 @code{i686},
103 @code{pentium},
104 @code{pentiumpro},
105 @code{pentiumii},
106 @code{pentiumiii},
107 @code{pentium4},
108 @code{prescott},
109 @code{nocona},
110 @code{core},
111 @code{core2},
112 @code{corei7},
113 @code{l1om},
114 @code{k1om},
115 @code{k6},
116 @code{k6_2},
117 @code{athlon},
118 @code{opteron},
119 @code{k8},
120 @code{amdfam10},
121 @code{bdver1},
122 @code{bdver2},
123 @code{bdver3},
124 @code{btver1},
125 @code{btver2},
126 @code{generic32} and
127 @code{generic64}.
128
129 In addition to the basic instruction set, the assembler can be told to
130 accept various extension mnemonics. For example,
131 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
132 @var{vmx}. The following extensions are currently supported:
133 @code{8087},
134 @code{287},
135 @code{387},
136 @code{no87},
137 @code{mmx},
138 @code{nommx},
139 @code{sse},
140 @code{sse2},
141 @code{sse3},
142 @code{ssse3},
143 @code{sse4.1},
144 @code{sse4.2},
145 @code{sse4},
146 @code{nosse},
147 @code{avx},
148 @code{avx2},
149 @code{adx},
150 @code{rdseed},
151 @code{prfchw},
152 @code{smap},
153 @code{mpx},
154 @code{noavx},
155 @code{vmx},
156 @code{vmfunc},
157 @code{smx},
158 @code{xsave},
159 @code{xsaveopt},
160 @code{aes},
161 @code{pclmul},
162 @code{fsgsbase},
163 @code{rdrnd},
164 @code{f16c},
165 @code{bmi2},
166 @code{fma},
167 @code{movbe},
168 @code{ept},
169 @code{lzcnt},
170 @code{hle},
171 @code{rtm},
172 @code{invpcid},
173 @code{clflush},
174 @code{lwp},
175 @code{fma4},
176 @code{xop},
177 @code{cx16},
178 @code{syscall},
179 @code{rdtscp},
180 @code{3dnow},
181 @code{3dnowa},
182 @code{sse4a},
183 @code{sse5},
184 @code{svme},
185 @code{abm} and
186 @code{padlock}.
187 Note that rather than extending a basic instruction set, the extension
188 mnemonics starting with @code{no} revoke the respective functionality.
189
190 When the @code{.arch} directive is used with @option{-march}, the
191 @code{.arch} directive will take precedent.
192
193 @cindex @samp{-mtune=} option, i386
194 @cindex @samp{-mtune=} option, x86-64
195 @item -mtune=@var{CPU}
196 This option specifies a processor to optimize for. When used in
197 conjunction with the @option{-march} option, only instructions
198 of the processor specified by the @option{-march} option will be
199 generated.
200
201 Valid @var{CPU} values are identical to the processor list of
202 @option{-march=@var{CPU}}.
203
204 @cindex @samp{-msse2avx} option, i386
205 @cindex @samp{-msse2avx} option, x86-64
206 @item -msse2avx
207 This option specifies that the assembler should encode SSE instructions
208 with VEX prefix.
209
210 @cindex @samp{-msse-check=} option, i386
211 @cindex @samp{-msse-check=} option, x86-64
212 @item -msse-check=@var{none}
213 @itemx -msse-check=@var{warning}
214 @itemx -msse-check=@var{error}
215 These options control if the assembler should check SSE intructions.
216 @option{-msse-check=@var{none}} will make the assembler not to check SSE
217 instructions, which is the default. @option{-msse-check=@var{warning}}
218 will make the assembler issue a warning for any SSE intruction.
219 @option{-msse-check=@var{error}} will make the assembler issue an error
220 for any SSE intruction.
221
222 @cindex @samp{-mavxscalar=} option, i386
223 @cindex @samp{-mavxscalar=} option, x86-64
224 @item -mavxscalar=@var{128}
225 @itemx -mavxscalar=@var{256}
226 These options control how the assembler should encode scalar AVX
227 instructions. @option{-mavxscalar=@var{128}} will encode scalar
228 AVX instructions with 128bit vector length, which is the default.
229 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
230 with 256bit vector length.
231
232 @cindex @samp{-mmnemonic=} option, i386
233 @cindex @samp{-mmnemonic=} option, x86-64
234 @item -mmnemonic=@var{att}
235 @itemx -mmnemonic=@var{intel}
236 This option specifies instruction mnemonic for matching instructions.
237 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
238 take precedent.
239
240 @cindex @samp{-msyntax=} option, i386
241 @cindex @samp{-msyntax=} option, x86-64
242 @item -msyntax=@var{att}
243 @itemx -msyntax=@var{intel}
244 This option specifies instruction syntax when processing instructions.
245 The @code{.att_syntax} and @code{.intel_syntax} directives will
246 take precedent.
247
248 @cindex @samp{-mnaked-reg} option, i386
249 @cindex @samp{-mnaked-reg} option, x86-64
250 @item -mnaked-reg
251 This opetion specifies that registers don't require a @samp{%} prefix.
252 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
253
254 @cindex @samp{-madd-bnd-prefix} option, i386
255 @cindex @samp{-madd-bnd-prefix} option, x86-64
256 @item -madd-bnd-prefix
257 This option forces the assembler to add BND prefix to all branches, even
258 if such prefix was not explicitly specified in the source code.
259
260 @end table
261 @c man end
262
263 @node i386-Directives
264 @section x86 specific Directives
265
266 @cindex machine directives, x86
267 @cindex x86 machine directives
268 @table @code
269
270 @cindex @code{lcomm} directive, COFF
271 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
272 Reserve @var{length} (an absolute expression) bytes for a local common
273 denoted by @var{symbol}. The section and value of @var{symbol} are
274 those of the new local common. The addresses are allocated in the bss
275 section, so that at run-time the bytes start off zeroed. Since
276 @var{symbol} is not declared global, it is normally not visible to
277 @code{@value{LD}}. The optional third parameter, @var{alignment},
278 specifies the desired alignment of the symbol in the bss section.
279
280 This directive is only available for COFF based x86 targets.
281
282 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
283 @c .largecomm
284
285 @end table
286
287 @node i386-Syntax
288 @section i386 Syntactical Considerations
289 @menu
290 * i386-Variations:: AT&T Syntax versus Intel Syntax
291 * i386-Chars:: Special Characters
292 @end menu
293
294 @node i386-Variations
295 @subsection AT&T Syntax versus Intel Syntax
296
297 @cindex i386 intel_syntax pseudo op
298 @cindex intel_syntax pseudo op, i386
299 @cindex i386 att_syntax pseudo op
300 @cindex att_syntax pseudo op, i386
301 @cindex i386 syntax compatibility
302 @cindex syntax compatibility, i386
303 @cindex x86-64 intel_syntax pseudo op
304 @cindex intel_syntax pseudo op, x86-64
305 @cindex x86-64 att_syntax pseudo op
306 @cindex att_syntax pseudo op, x86-64
307 @cindex x86-64 syntax compatibility
308 @cindex syntax compatibility, x86-64
309
310 @code{@value{AS}} now supports assembly using Intel assembler syntax.
311 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
312 back to the usual AT&T mode for compatibility with the output of
313 @code{@value{GCC}}. Either of these directives may have an optional
314 argument, @code{prefix}, or @code{noprefix} specifying whether registers
315 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
316 different from Intel syntax. We mention these differences because
317 almost all 80386 documents use Intel syntax. Notable differences
318 between the two syntaxes are:
319
320 @cindex immediate operands, i386
321 @cindex i386 immediate operands
322 @cindex register operands, i386
323 @cindex i386 register operands
324 @cindex jump/call operands, i386
325 @cindex i386 jump/call operands
326 @cindex operand delimiters, i386
327
328 @cindex immediate operands, x86-64
329 @cindex x86-64 immediate operands
330 @cindex register operands, x86-64
331 @cindex x86-64 register operands
332 @cindex jump/call operands, x86-64
333 @cindex x86-64 jump/call operands
334 @cindex operand delimiters, x86-64
335 @itemize @bullet
336 @item
337 AT&T immediate operands are preceded by @samp{$}; Intel immediate
338 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
339 AT&T register operands are preceded by @samp{%}; Intel register operands
340 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
341 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
342
343 @cindex i386 source, destination operands
344 @cindex source, destination operands; i386
345 @cindex x86-64 source, destination operands
346 @cindex source, destination operands; x86-64
347 @item
348 AT&T and Intel syntax use the opposite order for source and destination
349 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
350 @samp{source, dest} convention is maintained for compatibility with
351 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
352 instructions with 2 immediate operands, such as the @samp{enter}
353 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
354
355 @cindex mnemonic suffixes, i386
356 @cindex sizes operands, i386
357 @cindex i386 size suffixes
358 @cindex mnemonic suffixes, x86-64
359 @cindex sizes operands, x86-64
360 @cindex x86-64 size suffixes
361 @item
362 In AT&T syntax the size of memory operands is determined from the last
363 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
364 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
365 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
366 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
367 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
368 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
369 syntax.
370
371 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
372 instruction with the 64-bit displacement or immediate operand.
373
374 @cindex return instructions, i386
375 @cindex i386 jump, call, return
376 @cindex return instructions, x86-64
377 @cindex x86-64 jump, call, return
378 @item
379 Immediate form long jumps and calls are
380 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
381 Intel syntax is
382 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
383 instruction
384 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
385 @samp{ret far @var{stack-adjust}}.
386
387 @cindex sections, i386
388 @cindex i386 sections
389 @cindex sections, x86-64
390 @cindex x86-64 sections
391 @item
392 The AT&T assembler does not provide support for multiple section
393 programs. Unix style systems expect all programs to be single sections.
394 @end itemize
395
396 @node i386-Chars
397 @subsection Special Characters
398
399 @cindex line comment character, i386
400 @cindex i386 line comment character
401 The presence of a @samp{#} appearing anywhere on a line indicates the
402 start of a comment that extends to the end of that line.
403
404 If a @samp{#} appears as the first character of a line then the whole
405 line is treated as a comment, but in this case the line can also be a
406 logical line number directive (@pxref{Comments}) or a preprocessor
407 control command (@pxref{Preprocessing}).
408
409 If the @option{--divide} command line option has not been specified
410 then the @samp{/} character appearing anywhere on a line also
411 introduces a line comment.
412
413 @cindex line separator, i386
414 @cindex statement separator, i386
415 @cindex i386 line separator
416 The @samp{;} character can be used to separate statements on the same
417 line.
418
419 @node i386-Mnemonics
420 @section Instruction Naming
421
422 @cindex i386 instruction naming
423 @cindex instruction naming, i386
424 @cindex x86-64 instruction naming
425 @cindex instruction naming, x86-64
426
427 Instruction mnemonics are suffixed with one character modifiers which
428 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
429 and @samp{q} specify byte, word, long and quadruple word operands. If
430 no suffix is specified by an instruction then @code{@value{AS}} tries to
431 fill in the missing suffix based on the destination register operand
432 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
433 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
434 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
435 assembler which assumes that a missing mnemonic suffix implies long
436 operand size. (This incompatibility does not affect compiler output
437 since compilers always explicitly specify the mnemonic suffix.)
438
439 Almost all instructions have the same names in AT&T and Intel format.
440 There are a few exceptions. The sign extend and zero extend
441 instructions need two sizes to specify them. They need a size to
442 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
443 is accomplished by using two instruction mnemonic suffixes in AT&T
444 syntax. Base names for sign extend and zero extend are
445 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
446 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
447 are tacked on to this base name, the @emph{from} suffix before the
448 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
449 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
450 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
451 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
452 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
453 quadruple word).
454
455 @cindex encoding options, i386
456 @cindex encoding options, x86-64
457
458 Different encoding options can be specified via optional mnemonic
459 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
460 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
461 prefers 8bit or 32bit displacement in encoding.
462
463 @cindex conversion instructions, i386
464 @cindex i386 conversion instructions
465 @cindex conversion instructions, x86-64
466 @cindex x86-64 conversion instructions
467 The Intel-syntax conversion instructions
468
469 @itemize @bullet
470 @item
471 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
472
473 @item
474 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
475
476 @item
477 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
478
479 @item
480 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
481
482 @item
483 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
484 (x86-64 only),
485
486 @item
487 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
488 @samp{%rdx:%rax} (x86-64 only),
489 @end itemize
490
491 @noindent
492 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
493 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
494 instructions.
495
496 @cindex jump instructions, i386
497 @cindex call instructions, i386
498 @cindex jump instructions, x86-64
499 @cindex call instructions, x86-64
500 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
501 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
502 convention.
503
504 @section AT&T Mnemonic versus Intel Mnemonic
505
506 @cindex i386 mnemonic compatibility
507 @cindex mnemonic compatibility, i386
508
509 @code{@value{AS}} supports assembly using Intel mnemonic.
510 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
511 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
512 syntax for compatibility with the output of @code{@value{GCC}}.
513 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
514 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
515 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
516 assembler with different mnemonics from those in Intel IA32 specification.
517 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
518
519 @node i386-Regs
520 @section Register Naming
521
522 @cindex i386 registers
523 @cindex registers, i386
524 @cindex x86-64 registers
525 @cindex registers, x86-64
526 Register operands are always prefixed with @samp{%}. The 80386 registers
527 consist of
528
529 @itemize @bullet
530 @item
531 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
532 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
533 frame pointer), and @samp{%esp} (the stack pointer).
534
535 @item
536 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
537 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
538
539 @item
540 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
541 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
542 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
543 @samp{%cx}, and @samp{%dx})
544
545 @item
546 the 6 section registers @samp{%cs} (code section), @samp{%ds}
547 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
548 and @samp{%gs}.
549
550 @item
551 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
552 @samp{%cr3}.
553
554 @item
555 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
556 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
557
558 @item
559 the 2 test registers @samp{%tr6} and @samp{%tr7}.
560
561 @item
562 the 8 floating point register stack @samp{%st} or equivalently
563 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
564 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
565 These registers are overloaded by 8 MMX registers @samp{%mm0},
566 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
567 @samp{%mm6} and @samp{%mm7}.
568
569 @item
570 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
571 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
572 @end itemize
573
574 The AMD x86-64 architecture extends the register set by:
575
576 @itemize @bullet
577 @item
578 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
579 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
580 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
581 pointer)
582
583 @item
584 the 8 extended registers @samp{%r8}--@samp{%r15}.
585
586 @item
587 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
588
589 @item
590 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
591
592 @item
593 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
594
595 @item
596 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
597
598 @item
599 the 8 debug registers: @samp{%db8}--@samp{%db15}.
600
601 @item
602 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
603 @end itemize
604
605 @node i386-Prefixes
606 @section Instruction Prefixes
607
608 @cindex i386 instruction prefixes
609 @cindex instruction prefixes, i386
610 @cindex prefixes, i386
611 Instruction prefixes are used to modify the following instruction. They
612 are used to repeat string instructions, to provide section overrides, to
613 perform bus lock operations, and to change operand and address sizes.
614 (Most instructions that normally operate on 32-bit operands will use
615 16-bit operands if the instruction has an ``operand size'' prefix.)
616 Instruction prefixes are best written on the same line as the instruction
617 they act upon. For example, the @samp{scas} (scan string) instruction is
618 repeated with:
619
620 @smallexample
621 repne scas %es:(%edi),%al
622 @end smallexample
623
624 You may also place prefixes on the lines immediately preceding the
625 instruction, but this circumvents checks that @code{@value{AS}} does
626 with prefixes, and will not work with all prefixes.
627
628 Here is a list of instruction prefixes:
629
630 @cindex section override prefixes, i386
631 @itemize @bullet
632 @item
633 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
634 @samp{fs}, @samp{gs}. These are automatically added by specifying
635 using the @var{section}:@var{memory-operand} form for memory references.
636
637 @cindex size prefixes, i386
638 @item
639 Operand/Address size prefixes @samp{data16} and @samp{addr16}
640 change 32-bit operands/addresses into 16-bit operands/addresses,
641 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
642 @code{.code16} section) into 32-bit operands/addresses. These prefixes
643 @emph{must} appear on the same line of code as the instruction they
644 modify. For example, in a 16-bit @code{.code16} section, you might
645 write:
646
647 @smallexample
648 addr32 jmpl *(%ebx)
649 @end smallexample
650
651 @cindex bus lock prefixes, i386
652 @cindex inhibiting interrupts, i386
653 @item
654 The bus lock prefix @samp{lock} inhibits interrupts during execution of
655 the instruction it precedes. (This is only valid with certain
656 instructions; see a 80386 manual for details).
657
658 @cindex coprocessor wait, i386
659 @item
660 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
661 complete the current instruction. This should never be needed for the
662 80386/80387 combination.
663
664 @cindex repeat prefixes, i386
665 @item
666 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
667 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
668 times if the current address size is 16-bits).
669 @cindex REX prefixes, i386
670 @item
671 The @samp{rex} family of prefixes is used by x86-64 to encode
672 extensions to i386 instruction set. The @samp{rex} prefix has four
673 bits --- an operand size overwrite (@code{64}) used to change operand size
674 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
675 register set.
676
677 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
678 instruction emits @samp{rex} prefix with all the bits set. By omitting
679 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
680 prefixes as well. Normally, there is no need to write the prefixes
681 explicitly, since gas will automatically generate them based on the
682 instruction operands.
683 @end itemize
684
685 @node i386-Memory
686 @section Memory References
687
688 @cindex i386 memory references
689 @cindex memory references, i386
690 @cindex x86-64 memory references
691 @cindex memory references, x86-64
692 An Intel syntax indirect memory reference of the form
693
694 @smallexample
695 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
696 @end smallexample
697
698 @noindent
699 is translated into the AT&T syntax
700
701 @smallexample
702 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
703 @end smallexample
704
705 @noindent
706 where @var{base} and @var{index} are the optional 32-bit base and
707 index registers, @var{disp} is the optional displacement, and
708 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
709 to calculate the address of the operand. If no @var{scale} is
710 specified, @var{scale} is taken to be 1. @var{section} specifies the
711 optional section register for the memory operand, and may override the
712 default section register (see a 80386 manual for section register
713 defaults). Note that section overrides in AT&T syntax @emph{must}
714 be preceded by a @samp{%}. If you specify a section override which
715 coincides with the default section register, @code{@value{AS}} does @emph{not}
716 output any section register override prefixes to assemble the given
717 instruction. Thus, section overrides can be specified to emphasize which
718 section register is used for a given memory operand.
719
720 Here are some examples of Intel and AT&T style memory references:
721
722 @table @asis
723 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
724 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
725 missing, and the default section is used (@samp{%ss} for addressing with
726 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
727
728 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
729 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
730 @samp{foo}. All other fields are missing. The section register here
731 defaults to @samp{%ds}.
732
733 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
734 This uses the value pointed to by @samp{foo} as a memory operand.
735 Note that @var{base} and @var{index} are both missing, but there is only
736 @emph{one} @samp{,}. This is a syntactic exception.
737
738 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
739 This selects the contents of the variable @samp{foo} with section
740 register @var{section} being @samp{%gs}.
741 @end table
742
743 Absolute (as opposed to PC relative) call and jump operands must be
744 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
745 always chooses PC relative addressing for jump/call labels.
746
747 Any instruction that has a memory operand, but no register operand,
748 @emph{must} specify its size (byte, word, long, or quadruple) with an
749 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
750 respectively).
751
752 The x86-64 architecture adds an RIP (instruction pointer relative)
753 addressing. This addressing mode is specified by using @samp{rip} as a
754 base register. Only constant offsets are valid. For example:
755
756 @table @asis
757 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
758 Points to the address 1234 bytes past the end of the current
759 instruction.
760
761 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
762 Points to the @code{symbol} in RIP relative way, this is shorter than
763 the default absolute addressing.
764 @end table
765
766 Other addressing modes remain unchanged in x86-64 architecture, except
767 registers used are 64-bit instead of 32-bit.
768
769 @node i386-Jumps
770 @section Handling of Jump Instructions
771
772 @cindex jump optimization, i386
773 @cindex i386 jump optimization
774 @cindex jump optimization, x86-64
775 @cindex x86-64 jump optimization
776 Jump instructions are always optimized to use the smallest possible
777 displacements. This is accomplished by using byte (8-bit) displacement
778 jumps whenever the target is sufficiently close. If a byte displacement
779 is insufficient a long displacement is used. We do not support
780 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
781 instruction with the @samp{data16} instruction prefix), since the 80386
782 insists upon masking @samp{%eip} to 16 bits after the word displacement
783 is added. (See also @pxref{i386-Arch})
784
785 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
786 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
787 displacements, so that if you use these instructions (@code{@value{GCC}} does
788 not use them) you may get an error message (and incorrect code). The AT&T
789 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
790 to
791
792 @smallexample
793 jcxz cx_zero
794 jmp cx_nonzero
795 cx_zero: jmp foo
796 cx_nonzero:
797 @end smallexample
798
799 @node i386-Float
800 @section Floating Point
801
802 @cindex i386 floating point
803 @cindex floating point, i386
804 @cindex x86-64 floating point
805 @cindex floating point, x86-64
806 All 80387 floating point types except packed BCD are supported.
807 (BCD support may be added without much difficulty). These data
808 types are 16-, 32-, and 64- bit integers, and single (32-bit),
809 double (64-bit), and extended (80-bit) precision floating point.
810 Each supported type has an instruction mnemonic suffix and a constructor
811 associated with it. Instruction mnemonic suffixes specify the operand's
812 data type. Constructors build these data types into memory.
813
814 @cindex @code{float} directive, i386
815 @cindex @code{single} directive, i386
816 @cindex @code{double} directive, i386
817 @cindex @code{tfloat} directive, i386
818 @cindex @code{float} directive, x86-64
819 @cindex @code{single} directive, x86-64
820 @cindex @code{double} directive, x86-64
821 @cindex @code{tfloat} directive, x86-64
822 @itemize @bullet
823 @item
824 Floating point constructors are @samp{.float} or @samp{.single},
825 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
826 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
827 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
828 only supports this format via the @samp{fldt} (load 80-bit real to stack
829 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
830
831 @cindex @code{word} directive, i386
832 @cindex @code{long} directive, i386
833 @cindex @code{int} directive, i386
834 @cindex @code{quad} directive, i386
835 @cindex @code{word} directive, x86-64
836 @cindex @code{long} directive, x86-64
837 @cindex @code{int} directive, x86-64
838 @cindex @code{quad} directive, x86-64
839 @item
840 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
841 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
842 corresponding instruction mnemonic suffixes are @samp{s} (single),
843 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
844 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
845 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
846 stack) instructions.
847 @end itemize
848
849 Register to register operations should not use instruction mnemonic suffixes.
850 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
851 wrote @samp{fst %st, %st(1)}, since all register to register operations
852 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
853 which converts @samp{%st} from 80-bit to 64-bit floating point format,
854 then stores the result in the 4 byte location @samp{mem})
855
856 @node i386-SIMD
857 @section Intel's MMX and AMD's 3DNow! SIMD Operations
858
859 @cindex MMX, i386
860 @cindex 3DNow!, i386
861 @cindex SIMD, i386
862 @cindex MMX, x86-64
863 @cindex 3DNow!, x86-64
864 @cindex SIMD, x86-64
865
866 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
867 instructions for integer data), available on Intel's Pentium MMX
868 processors and Pentium II processors, AMD's K6 and K6-2 processors,
869 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
870 instruction set (SIMD instructions for 32-bit floating point data)
871 available on AMD's K6-2 processor and possibly others in the future.
872
873 Currently, @code{@value{AS}} does not support Intel's floating point
874 SIMD, Katmai (KNI).
875
876 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
877 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
878 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
879 floating point values. The MMX registers cannot be used at the same time
880 as the floating point stack.
881
882 See Intel and AMD documentation, keeping in mind that the operand order in
883 instructions is reversed from the Intel syntax.
884
885 @node i386-LWP
886 @section AMD's Lightweight Profiling Instructions
887
888 @cindex LWP, i386
889 @cindex LWP, x86-64
890
891 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
892 instruction set, available on AMD's Family 15h (Orochi) processors.
893
894 LWP enables applications to collect and manage performance data, and
895 react to performance events. The collection of performance data
896 requires no context switches. LWP runs in the context of a thread and
897 so several counters can be used independently across multiple threads.
898 LWP can be used in both 64-bit and legacy 32-bit modes.
899
900 For detailed information on the LWP instruction set, see the
901 @cite{AMD Lightweight Profiling Specification} available at
902 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
903
904 @node i386-BMI
905 @section Bit Manipulation Instructions
906
907 @cindex BMI, i386
908 @cindex BMI, x86-64
909
910 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
911
912 BMI instructions provide several instructions implementing individual
913 bit manipulation operations such as isolation, masking, setting, or
914 resetting.
915
916 @c Need to add a specification citation here when available.
917
918 @node i386-TBM
919 @section AMD's Trailing Bit Manipulation Instructions
920
921 @cindex TBM, i386
922 @cindex TBM, x86-64
923
924 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
925 instruction set, available on AMD's BDVER2 processors (Trinity and
926 Viperfish).
927
928 TBM instructions provide instructions implementing individual bit
929 manipulation operations such as isolating, masking, setting, resetting,
930 complementing, and operations on trailing zeros and ones.
931
932 @c Need to add a specification citation here when available.
933
934 @node i386-16bit
935 @section Writing 16-bit Code
936
937 @cindex i386 16-bit code
938 @cindex 16-bit code, i386
939 @cindex real-mode code, i386
940 @cindex @code{code16gcc} directive, i386
941 @cindex @code{code16} directive, i386
942 @cindex @code{code32} directive, i386
943 @cindex @code{code64} directive, i386
944 @cindex @code{code64} directive, x86-64
945 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
946 or 64-bit x86-64 code depending on the default configuration,
947 it also supports writing code to run in real mode or in 16-bit protected
948 mode code segments. To do this, put a @samp{.code16} or
949 @samp{.code16gcc} directive before the assembly language instructions to
950 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
951 32-bit code with the @samp{.code32} directive or 64-bit code with the
952 @samp{.code64} directive.
953
954 @samp{.code16gcc} provides experimental support for generating 16-bit
955 code from gcc, and differs from @samp{.code16} in that @samp{call},
956 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
957 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
958 default to 32-bit size. This is so that the stack pointer is
959 manipulated in the same way over function calls, allowing access to
960 function parameters at the same stack offsets as in 32-bit mode.
961 @samp{.code16gcc} also automatically adds address size prefixes where
962 necessary to use the 32-bit addressing modes that gcc generates.
963
964 The code which @code{@value{AS}} generates in 16-bit mode will not
965 necessarily run on a 16-bit pre-80386 processor. To write code that
966 runs on such a processor, you must refrain from using @emph{any} 32-bit
967 constructs which require @code{@value{AS}} to output address or operand
968 size prefixes.
969
970 Note that writing 16-bit code instructions by explicitly specifying a
971 prefix or an instruction mnemonic suffix within a 32-bit code section
972 generates different machine instructions than those generated for a
973 16-bit code segment. In a 32-bit code section, the following code
974 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
975 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
976
977 @smallexample
978 pushw $4
979 @end smallexample
980
981 The same code in a 16-bit code section would generate the machine
982 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
983 is correct since the processor default operand size is assumed to be 16
984 bits in a 16-bit code section.
985
986 @node i386-Bugs
987 @section AT&T Syntax bugs
988
989 The UnixWare assembler, and probably other AT&T derived ix86 Unix
990 assemblers, generate floating point instructions with reversed source
991 and destination registers in certain cases. Unfortunately, gcc and
992 possibly many other programs use this reversed syntax, so we're stuck
993 with it.
994
995 For example
996
997 @smallexample
998 fsub %st,%st(3)
999 @end smallexample
1000 @noindent
1001 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1002 than the expected @samp{%st(3) - %st}. This happens with all the
1003 non-commutative arithmetic floating point operations with two register
1004 operands where the source register is @samp{%st} and the destination
1005 register is @samp{%st(i)}.
1006
1007 @node i386-Arch
1008 @section Specifying CPU Architecture
1009
1010 @cindex arch directive, i386
1011 @cindex i386 arch directive
1012 @cindex arch directive, x86-64
1013 @cindex x86-64 arch directive
1014
1015 @code{@value{AS}} may be told to assemble for a particular CPU
1016 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1017 directive enables a warning when gas detects an instruction that is not
1018 supported on the CPU specified. The choices for @var{cpu_type} are:
1019
1020 @multitable @columnfractions .20 .20 .20 .20
1021 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1022 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1023 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1024 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1025 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1026 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1027 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1028 @item @samp{btver1} @tab @samp{btver2}
1029 @item @samp{generic32} @tab @samp{generic64}
1030 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1031 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1032 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1033 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1034 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1035 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1036 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1037 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1038 @item @samp{.smap} @tab @samp{.mpx}
1039 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1040 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1041 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1042 @item @samp{.padlock}
1043 @end multitable
1044
1045 Apart from the warning, there are only two other effects on
1046 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1047 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1048 will automatically use a two byte opcode sequence. The larger three
1049 byte opcode sequence is used on the 486 (and when no architecture is
1050 specified) because it executes faster on the 486. Note that you can
1051 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1052 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1053 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1054 conditional jumps will be promoted when necessary to a two instruction
1055 sequence consisting of a conditional jump of the opposite sense around
1056 an unconditional jump to the target.
1057
1058 Following the CPU architecture (but not a sub-architecture, which are those
1059 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1060 control automatic promotion of conditional jumps. @samp{jumps} is the
1061 default, and enables jump promotion; All external jumps will be of the long
1062 variety, and file-local jumps will be promoted as necessary.
1063 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1064 byte offset jumps, and warns about file-local conditional jumps that
1065 @code{@value{AS}} promotes.
1066 Unconditional jumps are treated as for @samp{jumps}.
1067
1068 For example
1069
1070 @smallexample
1071 .arch i8086,nojumps
1072 @end smallexample
1073
1074 @node i386-Notes
1075 @section Notes
1076
1077 @cindex i386 @code{mul}, @code{imul} instructions
1078 @cindex @code{mul} instruction, i386
1079 @cindex @code{imul} instruction, i386
1080 @cindex @code{mul} instruction, x86-64
1081 @cindex @code{imul} instruction, x86-64
1082 There is some trickery concerning the @samp{mul} and @samp{imul}
1083 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1084 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1085 for @samp{imul}) can be output only in the one operand form. Thus,
1086 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1087 the expanding multiply would clobber the @samp{%edx} register, and this
1088 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1089 64-bit product in @samp{%edx:%eax}.
1090
1091 We have added a two operand form of @samp{imul} when the first operand
1092 is an immediate mode expression and the second operand is a register.
1093 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1094 example, can be done with @samp{imul $69, %eax} rather than @samp{imul
1095 $69, %eax, %eax}.
1096
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