1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
2 @c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
11 @chapter 80386 Dependent Features
14 @node Machine Dependencies
15 @chapter 80386 Dependent Features
19 @cindex i80386 support
20 @cindex x86-64 support
22 The i386 version @code{@value{AS}} supports both the original Intel 386
23 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
24 extending the Intel architecture to 64-bits.
27 * i386-Options:: Options
28 * i386-Directives:: X86 specific directives
29 * i386-Syntax:: Syntactical considerations
30 * i386-Mnemonics:: Instruction Naming
31 * i386-Regs:: Register Naming
32 * i386-Prefixes:: Instruction Prefixes
33 * i386-Memory:: Memory References
34 * i386-Jumps:: Handling of Jump Instructions
35 * i386-Float:: Floating Point
36 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
37 * i386-LWP:: AMD's Lightweight Profiling Instructions
38 * i386-BMI:: Bit Manipulation Instruction
39 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
40 * i386-16bit:: Writing 16-bit Code
41 * i386-Arch:: Specifying an x86 CPU architecture
42 * i386-Bugs:: AT&T Syntax bugs
49 @cindex options for i386
50 @cindex options for x86-64
52 @cindex x86-64 options
54 The i386 version of @code{@value{AS}} has a few machine
59 @cindex @samp{--32} option, i386
60 @cindex @samp{--32} option, x86-64
61 @cindex @samp{--x32} option, i386
62 @cindex @samp{--x32} option, x86-64
63 @cindex @samp{--64} option, i386
64 @cindex @samp{--64} option, x86-64
65 @item --32 | --x32 | --64
66 Select the word size, either 32 bits or 64 bits. @samp{--32}
67 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
68 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
71 These options are only available with the ELF object file format, and
72 require that the necessary BFD support has been included (on a 32-bit
73 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
74 usage and use x86-64 as target platform).
77 By default, x86 GAS replaces multiple nop instructions used for
78 alignment within code sections with multi-byte nop instructions such
79 as leal 0(%esi,1),%esi. This switch disables the optimization.
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
129 In addition to the basic instruction set, the assembler can be told to
130 accept various extension mnemonics. For example,
131 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
132 @var{vmx}. The following extensions are currently supported:
186 Note that rather than extending a basic instruction set, the extension
187 mnemonics starting with @code{no} revoke the respective functionality.
189 When the @code{.arch} directive is used with @option{-march}, the
190 @code{.arch} directive will take precedent.
192 @cindex @samp{-mtune=} option, i386
193 @cindex @samp{-mtune=} option, x86-64
194 @item -mtune=@var{CPU}
195 This option specifies a processor to optimize for. When used in
196 conjunction with the @option{-march} option, only instructions
197 of the processor specified by the @option{-march} option will be
200 Valid @var{CPU} values are identical to the processor list of
201 @option{-march=@var{CPU}}.
203 @cindex @samp{-msse2avx} option, i386
204 @cindex @samp{-msse2avx} option, x86-64
206 This option specifies that the assembler should encode SSE instructions
209 @cindex @samp{-msse-check=} option, i386
210 @cindex @samp{-msse-check=} option, x86-64
211 @item -msse-check=@var{none}
212 @itemx -msse-check=@var{warning}
213 @itemx -msse-check=@var{error}
214 These options control if the assembler should check SSE intructions.
215 @option{-msse-check=@var{none}} will make the assembler not to check SSE
216 instructions, which is the default. @option{-msse-check=@var{warning}}
217 will make the assembler issue a warning for any SSE intruction.
218 @option{-msse-check=@var{error}} will make the assembler issue an error
219 for any SSE intruction.
221 @cindex @samp{-mavxscalar=} option, i386
222 @cindex @samp{-mavxscalar=} option, x86-64
223 @item -mavxscalar=@var{128}
224 @itemx -mavxscalar=@var{256}
225 These options control how the assembler should encode scalar AVX
226 instructions. @option{-mavxscalar=@var{128}} will encode scalar
227 AVX instructions with 128bit vector length, which is the default.
228 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
229 with 256bit vector length.
231 @cindex @samp{-mmnemonic=} option, i386
232 @cindex @samp{-mmnemonic=} option, x86-64
233 @item -mmnemonic=@var{att}
234 @itemx -mmnemonic=@var{intel}
235 This option specifies instruction mnemonic for matching instructions.
236 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
239 @cindex @samp{-msyntax=} option, i386
240 @cindex @samp{-msyntax=} option, x86-64
241 @item -msyntax=@var{att}
242 @itemx -msyntax=@var{intel}
243 This option specifies instruction syntax when processing instructions.
244 The @code{.att_syntax} and @code{.intel_syntax} directives will
247 @cindex @samp{-mnaked-reg} option, i386
248 @cindex @samp{-mnaked-reg} option, x86-64
250 This opetion specifies that registers don't require a @samp{%} prefix.
251 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
256 @node i386-Directives
257 @section x86 specific Directives
259 @cindex machine directives, x86
260 @cindex x86 machine directives
263 @cindex @code{lcomm} directive, COFF
264 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
265 Reserve @var{length} (an absolute expression) bytes for a local common
266 denoted by @var{symbol}. The section and value of @var{symbol} are
267 those of the new local common. The addresses are allocated in the bss
268 section, so that at run-time the bytes start off zeroed. Since
269 @var{symbol} is not declared global, it is normally not visible to
270 @code{@value{LD}}. The optional third parameter, @var{alignment},
271 specifies the desired alignment of the symbol in the bss section.
273 This directive is only available for COFF based x86 targets.
275 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
281 @section i386 Syntactical Considerations
283 * i386-Variations:: AT&T Syntax versus Intel Syntax
284 * i386-Chars:: Special Characters
287 @node i386-Variations
288 @subsection AT&T Syntax versus Intel Syntax
290 @cindex i386 intel_syntax pseudo op
291 @cindex intel_syntax pseudo op, i386
292 @cindex i386 att_syntax pseudo op
293 @cindex att_syntax pseudo op, i386
294 @cindex i386 syntax compatibility
295 @cindex syntax compatibility, i386
296 @cindex x86-64 intel_syntax pseudo op
297 @cindex intel_syntax pseudo op, x86-64
298 @cindex x86-64 att_syntax pseudo op
299 @cindex att_syntax pseudo op, x86-64
300 @cindex x86-64 syntax compatibility
301 @cindex syntax compatibility, x86-64
303 @code{@value{AS}} now supports assembly using Intel assembler syntax.
304 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
305 back to the usual AT&T mode for compatibility with the output of
306 @code{@value{GCC}}. Either of these directives may have an optional
307 argument, @code{prefix}, or @code{noprefix} specifying whether registers
308 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
309 different from Intel syntax. We mention these differences because
310 almost all 80386 documents use Intel syntax. Notable differences
311 between the two syntaxes are:
313 @cindex immediate operands, i386
314 @cindex i386 immediate operands
315 @cindex register operands, i386
316 @cindex i386 register operands
317 @cindex jump/call operands, i386
318 @cindex i386 jump/call operands
319 @cindex operand delimiters, i386
321 @cindex immediate operands, x86-64
322 @cindex x86-64 immediate operands
323 @cindex register operands, x86-64
324 @cindex x86-64 register operands
325 @cindex jump/call operands, x86-64
326 @cindex x86-64 jump/call operands
327 @cindex operand delimiters, x86-64
330 AT&T immediate operands are preceded by @samp{$}; Intel immediate
331 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
332 AT&T register operands are preceded by @samp{%}; Intel register operands
333 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
334 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
336 @cindex i386 source, destination operands
337 @cindex source, destination operands; i386
338 @cindex x86-64 source, destination operands
339 @cindex source, destination operands; x86-64
341 AT&T and Intel syntax use the opposite order for source and destination
342 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
343 @samp{source, dest} convention is maintained for compatibility with
344 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
345 instructions with 2 immediate operands, such as the @samp{enter}
346 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
348 @cindex mnemonic suffixes, i386
349 @cindex sizes operands, i386
350 @cindex i386 size suffixes
351 @cindex mnemonic suffixes, x86-64
352 @cindex sizes operands, x86-64
353 @cindex x86-64 size suffixes
355 In AT&T syntax the size of memory operands is determined from the last
356 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
357 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
358 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
359 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
360 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
361 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
364 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
365 instruction with the 64-bit displacement or immediate operand.
367 @cindex return instructions, i386
368 @cindex i386 jump, call, return
369 @cindex return instructions, x86-64
370 @cindex x86-64 jump, call, return
372 Immediate form long jumps and calls are
373 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
375 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
377 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
378 @samp{ret far @var{stack-adjust}}.
380 @cindex sections, i386
381 @cindex i386 sections
382 @cindex sections, x86-64
383 @cindex x86-64 sections
385 The AT&T assembler does not provide support for multiple section
386 programs. Unix style systems expect all programs to be single sections.
390 @subsection Special Characters
392 @cindex line comment character, i386
393 @cindex i386 line comment character
394 The presence of a @samp{#} appearing anywhere on a line indicates the
395 start of a comment that extends to the end of that line.
397 If a @samp{#} appears as the first character of a line then the whole
398 line is treated as a comment, but in this case the line can also be a
399 logical line number directive (@pxref{Comments}) or a preprocessor
400 control command (@pxref{Preprocessing}).
402 If the @option{--divide} command line option has not been specified
403 then the @samp{/} character appearing anywhere on a line also
404 introduces a line comment.
406 @cindex line separator, i386
407 @cindex statement separator, i386
408 @cindex i386 line separator
409 The @samp{;} character can be used to separate statements on the same
413 @section Instruction Naming
415 @cindex i386 instruction naming
416 @cindex instruction naming, i386
417 @cindex x86-64 instruction naming
418 @cindex instruction naming, x86-64
420 Instruction mnemonics are suffixed with one character modifiers which
421 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
422 and @samp{q} specify byte, word, long and quadruple word operands. If
423 no suffix is specified by an instruction then @code{@value{AS}} tries to
424 fill in the missing suffix based on the destination register operand
425 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
426 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
427 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
428 assembler which assumes that a missing mnemonic suffix implies long
429 operand size. (This incompatibility does not affect compiler output
430 since compilers always explicitly specify the mnemonic suffix.)
432 Almost all instructions have the same names in AT&T and Intel format.
433 There are a few exceptions. The sign extend and zero extend
434 instructions need two sizes to specify them. They need a size to
435 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
436 is accomplished by using two instruction mnemonic suffixes in AT&T
437 syntax. Base names for sign extend and zero extend are
438 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
439 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
440 are tacked on to this base name, the @emph{from} suffix before the
441 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
442 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
443 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
444 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
445 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
448 @cindex encoding options, i386
449 @cindex encoding options, x86-64
451 Different encoding options can be specified via optional mnemonic
452 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
453 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
454 prefers 8bit or 32bit displacement in encoding.
456 @cindex conversion instructions, i386
457 @cindex i386 conversion instructions
458 @cindex conversion instructions, x86-64
459 @cindex x86-64 conversion instructions
460 The Intel-syntax conversion instructions
464 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
467 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
470 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
473 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
476 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
480 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
481 @samp{%rdx:%rax} (x86-64 only),
485 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
486 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
489 @cindex jump instructions, i386
490 @cindex call instructions, i386
491 @cindex jump instructions, x86-64
492 @cindex call instructions, x86-64
493 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
494 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
497 @section AT&T Mnemonic versus Intel Mnemonic
499 @cindex i386 mnemonic compatibility
500 @cindex mnemonic compatibility, i386
502 @code{@value{AS}} supports assembly using Intel mnemonic.
503 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
504 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
505 syntax for compatibility with the output of @code{@value{GCC}}.
506 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
507 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
508 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
509 assembler with different mnemonics from those in Intel IA32 specification.
510 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
513 @section Register Naming
515 @cindex i386 registers
516 @cindex registers, i386
517 @cindex x86-64 registers
518 @cindex registers, x86-64
519 Register operands are always prefixed with @samp{%}. The 80386 registers
524 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
525 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
526 frame pointer), and @samp{%esp} (the stack pointer).
529 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
530 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
533 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
534 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
535 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
536 @samp{%cx}, and @samp{%dx})
539 the 6 section registers @samp{%cs} (code section), @samp{%ds}
540 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
544 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
548 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
549 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
552 the 2 test registers @samp{%tr6} and @samp{%tr7}.
555 the 8 floating point register stack @samp{%st} or equivalently
556 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
557 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
558 These registers are overloaded by 8 MMX registers @samp{%mm0},
559 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
560 @samp{%mm6} and @samp{%mm7}.
563 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
564 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
567 The AMD x86-64 architecture extends the register set by:
571 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
572 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
573 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
577 the 8 extended registers @samp{%r8}--@samp{%r15}.
580 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
583 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
586 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
589 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
592 the 8 debug registers: @samp{%db8}--@samp{%db15}.
595 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
599 @section Instruction Prefixes
601 @cindex i386 instruction prefixes
602 @cindex instruction prefixes, i386
603 @cindex prefixes, i386
604 Instruction prefixes are used to modify the following instruction. They
605 are used to repeat string instructions, to provide section overrides, to
606 perform bus lock operations, and to change operand and address sizes.
607 (Most instructions that normally operate on 32-bit operands will use
608 16-bit operands if the instruction has an ``operand size'' prefix.)
609 Instruction prefixes are best written on the same line as the instruction
610 they act upon. For example, the @samp{scas} (scan string) instruction is
614 repne scas %es:(%edi),%al
617 You may also place prefixes on the lines immediately preceding the
618 instruction, but this circumvents checks that @code{@value{AS}} does
619 with prefixes, and will not work with all prefixes.
621 Here is a list of instruction prefixes:
623 @cindex section override prefixes, i386
626 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
627 @samp{fs}, @samp{gs}. These are automatically added by specifying
628 using the @var{section}:@var{memory-operand} form for memory references.
630 @cindex size prefixes, i386
632 Operand/Address size prefixes @samp{data16} and @samp{addr16}
633 change 32-bit operands/addresses into 16-bit operands/addresses,
634 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
635 @code{.code16} section) into 32-bit operands/addresses. These prefixes
636 @emph{must} appear on the same line of code as the instruction they
637 modify. For example, in a 16-bit @code{.code16} section, you might
644 @cindex bus lock prefixes, i386
645 @cindex inhibiting interrupts, i386
647 The bus lock prefix @samp{lock} inhibits interrupts during execution of
648 the instruction it precedes. (This is only valid with certain
649 instructions; see a 80386 manual for details).
651 @cindex coprocessor wait, i386
653 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
654 complete the current instruction. This should never be needed for the
655 80386/80387 combination.
657 @cindex repeat prefixes, i386
659 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
660 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
661 times if the current address size is 16-bits).
662 @cindex REX prefixes, i386
664 The @samp{rex} family of prefixes is used by x86-64 to encode
665 extensions to i386 instruction set. The @samp{rex} prefix has four
666 bits --- an operand size overwrite (@code{64}) used to change operand size
667 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
670 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
671 instruction emits @samp{rex} prefix with all the bits set. By omitting
672 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
673 prefixes as well. Normally, there is no need to write the prefixes
674 explicitly, since gas will automatically generate them based on the
675 instruction operands.
679 @section Memory References
681 @cindex i386 memory references
682 @cindex memory references, i386
683 @cindex x86-64 memory references
684 @cindex memory references, x86-64
685 An Intel syntax indirect memory reference of the form
688 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
692 is translated into the AT&T syntax
695 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
699 where @var{base} and @var{index} are the optional 32-bit base and
700 index registers, @var{disp} is the optional displacement, and
701 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
702 to calculate the address of the operand. If no @var{scale} is
703 specified, @var{scale} is taken to be 1. @var{section} specifies the
704 optional section register for the memory operand, and may override the
705 default section register (see a 80386 manual for section register
706 defaults). Note that section overrides in AT&T syntax @emph{must}
707 be preceded by a @samp{%}. If you specify a section override which
708 coincides with the default section register, @code{@value{AS}} does @emph{not}
709 output any section register override prefixes to assemble the given
710 instruction. Thus, section overrides can be specified to emphasize which
711 section register is used for a given memory operand.
713 Here are some examples of Intel and AT&T style memory references:
716 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
717 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
718 missing, and the default section is used (@samp{%ss} for addressing with
719 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
721 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
722 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
723 @samp{foo}. All other fields are missing. The section register here
724 defaults to @samp{%ds}.
726 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
727 This uses the value pointed to by @samp{foo} as a memory operand.
728 Note that @var{base} and @var{index} are both missing, but there is only
729 @emph{one} @samp{,}. This is a syntactic exception.
731 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
732 This selects the contents of the variable @samp{foo} with section
733 register @var{section} being @samp{%gs}.
736 Absolute (as opposed to PC relative) call and jump operands must be
737 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
738 always chooses PC relative addressing for jump/call labels.
740 Any instruction that has a memory operand, but no register operand,
741 @emph{must} specify its size (byte, word, long, or quadruple) with an
742 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
745 The x86-64 architecture adds an RIP (instruction pointer relative)
746 addressing. This addressing mode is specified by using @samp{rip} as a
747 base register. Only constant offsets are valid. For example:
750 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
751 Points to the address 1234 bytes past the end of the current
754 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
755 Points to the @code{symbol} in RIP relative way, this is shorter than
756 the default absolute addressing.
759 Other addressing modes remain unchanged in x86-64 architecture, except
760 registers used are 64-bit instead of 32-bit.
763 @section Handling of Jump Instructions
765 @cindex jump optimization, i386
766 @cindex i386 jump optimization
767 @cindex jump optimization, x86-64
768 @cindex x86-64 jump optimization
769 Jump instructions are always optimized to use the smallest possible
770 displacements. This is accomplished by using byte (8-bit) displacement
771 jumps whenever the target is sufficiently close. If a byte displacement
772 is insufficient a long displacement is used. We do not support
773 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
774 instruction with the @samp{data16} instruction prefix), since the 80386
775 insists upon masking @samp{%eip} to 16 bits after the word displacement
776 is added. (See also @pxref{i386-Arch})
778 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
779 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
780 displacements, so that if you use these instructions (@code{@value{GCC}} does
781 not use them) you may get an error message (and incorrect code). The AT&T
782 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
793 @section Floating Point
795 @cindex i386 floating point
796 @cindex floating point, i386
797 @cindex x86-64 floating point
798 @cindex floating point, x86-64
799 All 80387 floating point types except packed BCD are supported.
800 (BCD support may be added without much difficulty). These data
801 types are 16-, 32-, and 64- bit integers, and single (32-bit),
802 double (64-bit), and extended (80-bit) precision floating point.
803 Each supported type has an instruction mnemonic suffix and a constructor
804 associated with it. Instruction mnemonic suffixes specify the operand's
805 data type. Constructors build these data types into memory.
807 @cindex @code{float} directive, i386
808 @cindex @code{single} directive, i386
809 @cindex @code{double} directive, i386
810 @cindex @code{tfloat} directive, i386
811 @cindex @code{float} directive, x86-64
812 @cindex @code{single} directive, x86-64
813 @cindex @code{double} directive, x86-64
814 @cindex @code{tfloat} directive, x86-64
817 Floating point constructors are @samp{.float} or @samp{.single},
818 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
819 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
820 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
821 only supports this format via the @samp{fldt} (load 80-bit real to stack
822 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
824 @cindex @code{word} directive, i386
825 @cindex @code{long} directive, i386
826 @cindex @code{int} directive, i386
827 @cindex @code{quad} directive, i386
828 @cindex @code{word} directive, x86-64
829 @cindex @code{long} directive, x86-64
830 @cindex @code{int} directive, x86-64
831 @cindex @code{quad} directive, x86-64
833 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
834 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
835 corresponding instruction mnemonic suffixes are @samp{s} (single),
836 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
837 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
838 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
842 Register to register operations should not use instruction mnemonic suffixes.
843 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
844 wrote @samp{fst %st, %st(1)}, since all register to register operations
845 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
846 which converts @samp{%st} from 80-bit to 64-bit floating point format,
847 then stores the result in the 4 byte location @samp{mem})
850 @section Intel's MMX and AMD's 3DNow! SIMD Operations
856 @cindex 3DNow!, x86-64
859 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
860 instructions for integer data), available on Intel's Pentium MMX
861 processors and Pentium II processors, AMD's K6 and K6-2 processors,
862 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
863 instruction set (SIMD instructions for 32-bit floating point data)
864 available on AMD's K6-2 processor and possibly others in the future.
866 Currently, @code{@value{AS}} does not support Intel's floating point
869 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
870 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
871 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
872 floating point values. The MMX registers cannot be used at the same time
873 as the floating point stack.
875 See Intel and AMD documentation, keeping in mind that the operand order in
876 instructions is reversed from the Intel syntax.
879 @section AMD's Lightweight Profiling Instructions
884 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
885 instruction set, available on AMD's Family 15h (Orochi) processors.
887 LWP enables applications to collect and manage performance data, and
888 react to performance events. The collection of performance data
889 requires no context switches. LWP runs in the context of a thread and
890 so several counters can be used independently across multiple threads.
891 LWP can be used in both 64-bit and legacy 32-bit modes.
893 For detailed information on the LWP instruction set, see the
894 @cite{AMD Lightweight Profiling Specification} available at
895 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
898 @section Bit Manipulation Instructions
903 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
905 BMI instructions provide several instructions implementing individual
906 bit manipulation operations such as isolation, masking, setting, or
909 @c Need to add a specification citation here when available.
912 @section AMD's Trailing Bit Manipulation Instructions
917 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
918 instruction set, available on AMD's BDVER2 processors (Trinity and
921 TBM instructions provide instructions implementing individual bit
922 manipulation operations such as isolating, masking, setting, resetting,
923 complementing, and operations on trailing zeros and ones.
925 @c Need to add a specification citation here when available.
928 @section Writing 16-bit Code
930 @cindex i386 16-bit code
931 @cindex 16-bit code, i386
932 @cindex real-mode code, i386
933 @cindex @code{code16gcc} directive, i386
934 @cindex @code{code16} directive, i386
935 @cindex @code{code32} directive, i386
936 @cindex @code{code64} directive, i386
937 @cindex @code{code64} directive, x86-64
938 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
939 or 64-bit x86-64 code depending on the default configuration,
940 it also supports writing code to run in real mode or in 16-bit protected
941 mode code segments. To do this, put a @samp{.code16} or
942 @samp{.code16gcc} directive before the assembly language instructions to
943 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
944 32-bit code with the @samp{.code32} directive or 64-bit code with the
945 @samp{.code64} directive.
947 @samp{.code16gcc} provides experimental support for generating 16-bit
948 code from gcc, and differs from @samp{.code16} in that @samp{call},
949 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
950 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
951 default to 32-bit size. This is so that the stack pointer is
952 manipulated in the same way over function calls, allowing access to
953 function parameters at the same stack offsets as in 32-bit mode.
954 @samp{.code16gcc} also automatically adds address size prefixes where
955 necessary to use the 32-bit addressing modes that gcc generates.
957 The code which @code{@value{AS}} generates in 16-bit mode will not
958 necessarily run on a 16-bit pre-80386 processor. To write code that
959 runs on such a processor, you must refrain from using @emph{any} 32-bit
960 constructs which require @code{@value{AS}} to output address or operand
963 Note that writing 16-bit code instructions by explicitly specifying a
964 prefix or an instruction mnemonic suffix within a 32-bit code section
965 generates different machine instructions than those generated for a
966 16-bit code segment. In a 32-bit code section, the following code
967 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
968 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
974 The same code in a 16-bit code section would generate the machine
975 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
976 is correct since the processor default operand size is assumed to be 16
977 bits in a 16-bit code section.
980 @section AT&T Syntax bugs
982 The UnixWare assembler, and probably other AT&T derived ix86 Unix
983 assemblers, generate floating point instructions with reversed source
984 and destination registers in certain cases. Unfortunately, gcc and
985 possibly many other programs use this reversed syntax, so we're stuck
994 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
995 than the expected @samp{%st(3) - %st}. This happens with all the
996 non-commutative arithmetic floating point operations with two register
997 operands where the source register is @samp{%st} and the destination
998 register is @samp{%st(i)}.
1001 @section Specifying CPU Architecture
1003 @cindex arch directive, i386
1004 @cindex i386 arch directive
1005 @cindex arch directive, x86-64
1006 @cindex x86-64 arch directive
1008 @code{@value{AS}} may be told to assemble for a particular CPU
1009 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1010 directive enables a warning when gas detects an instruction that is not
1011 supported on the CPU specified. The choices for @var{cpu_type} are:
1013 @multitable @columnfractions .20 .20 .20 .20
1014 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1015 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1016 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1017 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1018 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1019 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1020 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1021 @item @samp{btver1} @tab @samp{btver2}
1022 @item @samp{generic32} @tab @samp{generic64}
1023 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1024 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1025 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1026 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1027 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1028 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1029 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1030 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1032 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1033 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1034 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1035 @item @samp{.padlock}
1038 Apart from the warning, there are only two other effects on
1039 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1040 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1041 will automatically use a two byte opcode sequence. The larger three
1042 byte opcode sequence is used on the 486 (and when no architecture is
1043 specified) because it executes faster on the 486. Note that you can
1044 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1045 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1046 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1047 conditional jumps will be promoted when necessary to a two instruction
1048 sequence consisting of a conditional jump of the opposite sense around
1049 an unconditional jump to the target.
1051 Following the CPU architecture (but not a sub-architecture, which are those
1052 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1053 control automatic promotion of conditional jumps. @samp{jumps} is the
1054 default, and enables jump promotion; All external jumps will be of the long
1055 variety, and file-local jumps will be promoted as necessary.
1056 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1057 byte offset jumps, and warns about file-local conditional jumps that
1058 @code{@value{AS}} promotes.
1059 Unconditional jumps are treated as for @samp{jumps}.
1070 @cindex i386 @code{mul}, @code{imul} instructions
1071 @cindex @code{mul} instruction, i386
1072 @cindex @code{imul} instruction, i386
1073 @cindex @code{mul} instruction, x86-64
1074 @cindex @code{imul} instruction, x86-64
1075 There is some trickery concerning the @samp{mul} and @samp{imul}
1076 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1077 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1078 for @samp{imul}) can be output only in the one operand form. Thus,
1079 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1080 the expanding multiply would clobber the @samp{%edx} register, and this
1081 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1082 64-bit product in @samp{%edx:%eax}.
1084 We have added a two operand form of @samp{imul} when the first operand
1085 is an immediate mode expression and the second operand is a register.
1086 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1087 example, can be done with @samp{imul $69, %eax} rather than @samp{imul