1 @c Copyright (C) 1991-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
130 In addition to the basic instruction set, the assembler can be told to
131 accept various extension mnemonics. For example,
132 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
133 @var{vmx}. The following extensions are currently supported:
207 Note that rather than extending a basic instruction set, the extension
208 mnemonics starting with @code{no} revoke the respective functionality.
210 When the @code{.arch} directive is used with @option{-march}, the
211 @code{.arch} directive will take precedent.
213 @cindex @samp{-mtune=} option, i386
214 @cindex @samp{-mtune=} option, x86-64
215 @item -mtune=@var{CPU}
216 This option specifies a processor to optimize for. When used in
217 conjunction with the @option{-march} option, only instructions
218 of the processor specified by the @option{-march} option will be
221 Valid @var{CPU} values are identical to the processor list of
222 @option{-march=@var{CPU}}.
224 @cindex @samp{-msse2avx} option, i386
225 @cindex @samp{-msse2avx} option, x86-64
227 This option specifies that the assembler should encode SSE instructions
230 @cindex @samp{-msse-check=} option, i386
231 @cindex @samp{-msse-check=} option, x86-64
232 @item -msse-check=@var{none}
233 @itemx -msse-check=@var{warning}
234 @itemx -msse-check=@var{error}
235 These options control if the assembler should check SSE instructions.
236 @option{-msse-check=@var{none}} will make the assembler not to check SSE
237 instructions, which is the default. @option{-msse-check=@var{warning}}
238 will make the assembler issue a warning for any SSE instruction.
239 @option{-msse-check=@var{error}} will make the assembler issue an error
240 for any SSE instruction.
242 @cindex @samp{-mavxscalar=} option, i386
243 @cindex @samp{-mavxscalar=} option, x86-64
244 @item -mavxscalar=@var{128}
245 @itemx -mavxscalar=@var{256}
246 These options control how the assembler should encode scalar AVX
247 instructions. @option{-mavxscalar=@var{128}} will encode scalar
248 AVX instructions with 128bit vector length, which is the default.
249 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
250 with 256bit vector length.
252 @cindex @samp{-mevexlig=} option, i386
253 @cindex @samp{-mevexlig=} option, x86-64
254 @item -mevexlig=@var{128}
255 @itemx -mevexlig=@var{256}
256 @itemx -mevexlig=@var{512}
257 These options control how the assembler should encode length-ignored
258 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
259 EVEX instructions with 128bit vector length, which is the default.
260 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
261 encode LIG EVEX instructions with 256bit and 512bit vector length,
264 @cindex @samp{-mevexwig=} option, i386
265 @cindex @samp{-mevexwig=} option, x86-64
266 @item -mevexwig=@var{0}
267 @itemx -mevexwig=@var{1}
268 These options control how the assembler should encode w-ignored (WIG)
269 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
270 EVEX instructions with evex.w = 0, which is the default.
271 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
274 @cindex @samp{-mmnemonic=} option, i386
275 @cindex @samp{-mmnemonic=} option, x86-64
276 @item -mmnemonic=@var{att}
277 @itemx -mmnemonic=@var{intel}
278 This option specifies instruction mnemonic for matching instructions.
279 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
282 @cindex @samp{-msyntax=} option, i386
283 @cindex @samp{-msyntax=} option, x86-64
284 @item -msyntax=@var{att}
285 @itemx -msyntax=@var{intel}
286 This option specifies instruction syntax when processing instructions.
287 The @code{.att_syntax} and @code{.intel_syntax} directives will
290 @cindex @samp{-mnaked-reg} option, i386
291 @cindex @samp{-mnaked-reg} option, x86-64
293 This opetion specifies that registers don't require a @samp{%} prefix.
294 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
296 @cindex @samp{-madd-bnd-prefix} option, i386
297 @cindex @samp{-madd-bnd-prefix} option, x86-64
298 @item -madd-bnd-prefix
299 This option forces the assembler to add BND prefix to all branches, even
300 if such prefix was not explicitly specified in the source code.
302 @cindex @samp{-mshared} option, i386
303 @cindex @samp{-mshared} option, x86-64
305 On ELF target, the assembler normally optimizes out non-PLT relocations
306 against defined non-weak global branch targets with default visibility.
307 The @samp{-mshared} option tells the assembler to generate code which
308 may go into a shared library where all non-weak global branch targets
309 with default visibility can be preempted. The resulting code is
310 slightly bigger. This option only affects the handling of branch
313 @cindex @samp{-mbig-obj} option, x86-64
315 On x86-64 PE/COFF target this option forces the use of big object file
316 format, which allows more than 32768 sections.
318 @cindex @samp{-momit-lock-prefix=} option, i386
319 @cindex @samp{-momit-lock-prefix=} option, x86-64
320 @item -momit-lock-prefix=@var{no}
321 @itemx -momit-lock-prefix=@var{yes}
322 These options control how the assembler should encode lock prefix.
323 This option is intended as a workaround for processors, that fail on
324 lock prefix. This option can only be safely used with single-core,
325 single-thread computers
326 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
327 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
328 which is the default.
330 @cindex @samp{-mevexrcig=} option, i386
331 @cindex @samp{-mevexrcig=} option, x86-64
332 @item -mevexrcig=@var{rne}
333 @itemx -mevexrcig=@var{rd}
334 @itemx -mevexrcig=@var{ru}
335 @itemx -mevexrcig=@var{rz}
336 These options control how the assembler should encode SAE-only
337 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
338 of EVEX instruction with 00, which is the default.
339 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
340 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
341 with 01, 10 and 11 RC bits, respectively.
343 @cindex @samp{-mamd64} option, x86-64
344 @cindex @samp{-mintel64} option, x86-64
347 This option specifies that the assembler should accept only AMD64 or
348 Intel64 ISA in 64-bit mode. The default is to accept both.
353 @node i386-Directives
354 @section x86 specific Directives
356 @cindex machine directives, x86
357 @cindex x86 machine directives
360 @cindex @code{lcomm} directive, COFF
361 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
362 Reserve @var{length} (an absolute expression) bytes for a local common
363 denoted by @var{symbol}. The section and value of @var{symbol} are
364 those of the new local common. The addresses are allocated in the bss
365 section, so that at run-time the bytes start off zeroed. Since
366 @var{symbol} is not declared global, it is normally not visible to
367 @code{@value{LD}}. The optional third parameter, @var{alignment},
368 specifies the desired alignment of the symbol in the bss section.
370 This directive is only available for COFF based x86 targets.
372 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
378 @section i386 Syntactical Considerations
380 * i386-Variations:: AT&T Syntax versus Intel Syntax
381 * i386-Chars:: Special Characters
384 @node i386-Variations
385 @subsection AT&T Syntax versus Intel Syntax
387 @cindex i386 intel_syntax pseudo op
388 @cindex intel_syntax pseudo op, i386
389 @cindex i386 att_syntax pseudo op
390 @cindex att_syntax pseudo op, i386
391 @cindex i386 syntax compatibility
392 @cindex syntax compatibility, i386
393 @cindex x86-64 intel_syntax pseudo op
394 @cindex intel_syntax pseudo op, x86-64
395 @cindex x86-64 att_syntax pseudo op
396 @cindex att_syntax pseudo op, x86-64
397 @cindex x86-64 syntax compatibility
398 @cindex syntax compatibility, x86-64
400 @code{@value{AS}} now supports assembly using Intel assembler syntax.
401 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
402 back to the usual AT&T mode for compatibility with the output of
403 @code{@value{GCC}}. Either of these directives may have an optional
404 argument, @code{prefix}, or @code{noprefix} specifying whether registers
405 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
406 different from Intel syntax. We mention these differences because
407 almost all 80386 documents use Intel syntax. Notable differences
408 between the two syntaxes are:
410 @cindex immediate operands, i386
411 @cindex i386 immediate operands
412 @cindex register operands, i386
413 @cindex i386 register operands
414 @cindex jump/call operands, i386
415 @cindex i386 jump/call operands
416 @cindex operand delimiters, i386
418 @cindex immediate operands, x86-64
419 @cindex x86-64 immediate operands
420 @cindex register operands, x86-64
421 @cindex x86-64 register operands
422 @cindex jump/call operands, x86-64
423 @cindex x86-64 jump/call operands
424 @cindex operand delimiters, x86-64
427 AT&T immediate operands are preceded by @samp{$}; Intel immediate
428 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
429 AT&T register operands are preceded by @samp{%}; Intel register operands
430 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
431 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
433 @cindex i386 source, destination operands
434 @cindex source, destination operands; i386
435 @cindex x86-64 source, destination operands
436 @cindex source, destination operands; x86-64
438 AT&T and Intel syntax use the opposite order for source and destination
439 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
440 @samp{source, dest} convention is maintained for compatibility with
441 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
442 instructions with 2 immediate operands, such as the @samp{enter}
443 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
445 @cindex mnemonic suffixes, i386
446 @cindex sizes operands, i386
447 @cindex i386 size suffixes
448 @cindex mnemonic suffixes, x86-64
449 @cindex sizes operands, x86-64
450 @cindex x86-64 size suffixes
452 In AT&T syntax the size of memory operands is determined from the last
453 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
454 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
455 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
456 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
457 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
458 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
461 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
462 instruction with the 64-bit displacement or immediate operand.
464 @cindex return instructions, i386
465 @cindex i386 jump, call, return
466 @cindex return instructions, x86-64
467 @cindex x86-64 jump, call, return
469 Immediate form long jumps and calls are
470 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
472 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
474 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
475 @samp{ret far @var{stack-adjust}}.
477 @cindex sections, i386
478 @cindex i386 sections
479 @cindex sections, x86-64
480 @cindex x86-64 sections
482 The AT&T assembler does not provide support for multiple section
483 programs. Unix style systems expect all programs to be single sections.
487 @subsection Special Characters
489 @cindex line comment character, i386
490 @cindex i386 line comment character
491 The presence of a @samp{#} appearing anywhere on a line indicates the
492 start of a comment that extends to the end of that line.
494 If a @samp{#} appears as the first character of a line then the whole
495 line is treated as a comment, but in this case the line can also be a
496 logical line number directive (@pxref{Comments}) or a preprocessor
497 control command (@pxref{Preprocessing}).
499 If the @option{--divide} command line option has not been specified
500 then the @samp{/} character appearing anywhere on a line also
501 introduces a line comment.
503 @cindex line separator, i386
504 @cindex statement separator, i386
505 @cindex i386 line separator
506 The @samp{;} character can be used to separate statements on the same
510 @section i386-Mnemonics
511 @subsection Instruction Naming
513 @cindex i386 instruction naming
514 @cindex instruction naming, i386
515 @cindex x86-64 instruction naming
516 @cindex instruction naming, x86-64
518 Instruction mnemonics are suffixed with one character modifiers which
519 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
520 and @samp{q} specify byte, word, long and quadruple word operands. If
521 no suffix is specified by an instruction then @code{@value{AS}} tries to
522 fill in the missing suffix based on the destination register operand
523 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
524 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
525 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
526 assembler which assumes that a missing mnemonic suffix implies long
527 operand size. (This incompatibility does not affect compiler output
528 since compilers always explicitly specify the mnemonic suffix.)
530 Almost all instructions have the same names in AT&T and Intel format.
531 There are a few exceptions. The sign extend and zero extend
532 instructions need two sizes to specify them. They need a size to
533 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
534 is accomplished by using two instruction mnemonic suffixes in AT&T
535 syntax. Base names for sign extend and zero extend are
536 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
537 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
538 are tacked on to this base name, the @emph{from} suffix before the
539 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
540 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
541 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
542 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
543 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
546 @cindex encoding options, i386
547 @cindex encoding options, x86-64
549 Different encoding options can be specified via optional mnemonic
550 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
551 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
552 prefers 8bit or 32bit displacement in encoding.
554 @cindex conversion instructions, i386
555 @cindex i386 conversion instructions
556 @cindex conversion instructions, x86-64
557 @cindex x86-64 conversion instructions
558 The Intel-syntax conversion instructions
562 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
565 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
568 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
571 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
574 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
578 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
579 @samp{%rdx:%rax} (x86-64 only),
583 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
584 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
587 @cindex jump instructions, i386
588 @cindex call instructions, i386
589 @cindex jump instructions, x86-64
590 @cindex call instructions, x86-64
591 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
592 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
595 @subsection AT&T Mnemonic versus Intel Mnemonic
597 @cindex i386 mnemonic compatibility
598 @cindex mnemonic compatibility, i386
600 @code{@value{AS}} supports assembly using Intel mnemonic.
601 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
602 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
603 syntax for compatibility with the output of @code{@value{GCC}}.
604 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
605 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
606 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
607 assembler with different mnemonics from those in Intel IA32 specification.
608 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
611 @section Register Naming
613 @cindex i386 registers
614 @cindex registers, i386
615 @cindex x86-64 registers
616 @cindex registers, x86-64
617 Register operands are always prefixed with @samp{%}. The 80386 registers
622 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
623 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
624 frame pointer), and @samp{%esp} (the stack pointer).
627 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
628 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
631 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
632 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
633 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
634 @samp{%cx}, and @samp{%dx})
637 the 6 section registers @samp{%cs} (code section), @samp{%ds}
638 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
642 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
646 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
647 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
650 the 2 test registers @samp{%tr6} and @samp{%tr7}.
653 the 8 floating point register stack @samp{%st} or equivalently
654 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
655 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
656 These registers are overloaded by 8 MMX registers @samp{%mm0},
657 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
658 @samp{%mm6} and @samp{%mm7}.
661 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
662 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
665 The AMD x86-64 architecture extends the register set by:
669 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
670 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
671 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
675 the 8 extended registers @samp{%r8}--@samp{%r15}.
678 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
681 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
684 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
687 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
690 the 8 debug registers: @samp{%db8}--@samp{%db15}.
693 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
697 @section Instruction Prefixes
699 @cindex i386 instruction prefixes
700 @cindex instruction prefixes, i386
701 @cindex prefixes, i386
702 Instruction prefixes are used to modify the following instruction. They
703 are used to repeat string instructions, to provide section overrides, to
704 perform bus lock operations, and to change operand and address sizes.
705 (Most instructions that normally operate on 32-bit operands will use
706 16-bit operands if the instruction has an ``operand size'' prefix.)
707 Instruction prefixes are best written on the same line as the instruction
708 they act upon. For example, the @samp{scas} (scan string) instruction is
712 repne scas %es:(%edi),%al
715 You may also place prefixes on the lines immediately preceding the
716 instruction, but this circumvents checks that @code{@value{AS}} does
717 with prefixes, and will not work with all prefixes.
719 Here is a list of instruction prefixes:
721 @cindex section override prefixes, i386
724 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
725 @samp{fs}, @samp{gs}. These are automatically added by specifying
726 using the @var{section}:@var{memory-operand} form for memory references.
728 @cindex size prefixes, i386
730 Operand/Address size prefixes @samp{data16} and @samp{addr16}
731 change 32-bit operands/addresses into 16-bit operands/addresses,
732 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
733 @code{.code16} section) into 32-bit operands/addresses. These prefixes
734 @emph{must} appear on the same line of code as the instruction they
735 modify. For example, in a 16-bit @code{.code16} section, you might
742 @cindex bus lock prefixes, i386
743 @cindex inhibiting interrupts, i386
745 The bus lock prefix @samp{lock} inhibits interrupts during execution of
746 the instruction it precedes. (This is only valid with certain
747 instructions; see a 80386 manual for details).
749 @cindex coprocessor wait, i386
751 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
752 complete the current instruction. This should never be needed for the
753 80386/80387 combination.
755 @cindex repeat prefixes, i386
757 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
758 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
759 times if the current address size is 16-bits).
760 @cindex REX prefixes, i386
762 The @samp{rex} family of prefixes is used by x86-64 to encode
763 extensions to i386 instruction set. The @samp{rex} prefix has four
764 bits --- an operand size overwrite (@code{64}) used to change operand size
765 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
768 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
769 instruction emits @samp{rex} prefix with all the bits set. By omitting
770 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
771 prefixes as well. Normally, there is no need to write the prefixes
772 explicitly, since gas will automatically generate them based on the
773 instruction operands.
777 @section Memory References
779 @cindex i386 memory references
780 @cindex memory references, i386
781 @cindex x86-64 memory references
782 @cindex memory references, x86-64
783 An Intel syntax indirect memory reference of the form
786 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
790 is translated into the AT&T syntax
793 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
797 where @var{base} and @var{index} are the optional 32-bit base and
798 index registers, @var{disp} is the optional displacement, and
799 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
800 to calculate the address of the operand. If no @var{scale} is
801 specified, @var{scale} is taken to be 1. @var{section} specifies the
802 optional section register for the memory operand, and may override the
803 default section register (see a 80386 manual for section register
804 defaults). Note that section overrides in AT&T syntax @emph{must}
805 be preceded by a @samp{%}. If you specify a section override which
806 coincides with the default section register, @code{@value{AS}} does @emph{not}
807 output any section register override prefixes to assemble the given
808 instruction. Thus, section overrides can be specified to emphasize which
809 section register is used for a given memory operand.
811 Here are some examples of Intel and AT&T style memory references:
814 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
815 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
816 missing, and the default section is used (@samp{%ss} for addressing with
817 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
819 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
820 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
821 @samp{foo}. All other fields are missing. The section register here
822 defaults to @samp{%ds}.
824 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
825 This uses the value pointed to by @samp{foo} as a memory operand.
826 Note that @var{base} and @var{index} are both missing, but there is only
827 @emph{one} @samp{,}. This is a syntactic exception.
829 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
830 This selects the contents of the variable @samp{foo} with section
831 register @var{section} being @samp{%gs}.
834 Absolute (as opposed to PC relative) call and jump operands must be
835 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
836 always chooses PC relative addressing for jump/call labels.
838 Any instruction that has a memory operand, but no register operand,
839 @emph{must} specify its size (byte, word, long, or quadruple) with an
840 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
843 The x86-64 architecture adds an RIP (instruction pointer relative)
844 addressing. This addressing mode is specified by using @samp{rip} as a
845 base register. Only constant offsets are valid. For example:
848 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
849 Points to the address 1234 bytes past the end of the current
852 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
853 Points to the @code{symbol} in RIP relative way, this is shorter than
854 the default absolute addressing.
857 Other addressing modes remain unchanged in x86-64 architecture, except
858 registers used are 64-bit instead of 32-bit.
861 @section Handling of Jump Instructions
863 @cindex jump optimization, i386
864 @cindex i386 jump optimization
865 @cindex jump optimization, x86-64
866 @cindex x86-64 jump optimization
867 Jump instructions are always optimized to use the smallest possible
868 displacements. This is accomplished by using byte (8-bit) displacement
869 jumps whenever the target is sufficiently close. If a byte displacement
870 is insufficient a long displacement is used. We do not support
871 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
872 instruction with the @samp{data16} instruction prefix), since the 80386
873 insists upon masking @samp{%eip} to 16 bits after the word displacement
874 is added. (See also @pxref{i386-Arch})
876 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
877 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
878 displacements, so that if you use these instructions (@code{@value{GCC}} does
879 not use them) you may get an error message (and incorrect code). The AT&T
880 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
891 @section Floating Point
893 @cindex i386 floating point
894 @cindex floating point, i386
895 @cindex x86-64 floating point
896 @cindex floating point, x86-64
897 All 80387 floating point types except packed BCD are supported.
898 (BCD support may be added without much difficulty). These data
899 types are 16-, 32-, and 64- bit integers, and single (32-bit),
900 double (64-bit), and extended (80-bit) precision floating point.
901 Each supported type has an instruction mnemonic suffix and a constructor
902 associated with it. Instruction mnemonic suffixes specify the operand's
903 data type. Constructors build these data types into memory.
905 @cindex @code{float} directive, i386
906 @cindex @code{single} directive, i386
907 @cindex @code{double} directive, i386
908 @cindex @code{tfloat} directive, i386
909 @cindex @code{float} directive, x86-64
910 @cindex @code{single} directive, x86-64
911 @cindex @code{double} directive, x86-64
912 @cindex @code{tfloat} directive, x86-64
915 Floating point constructors are @samp{.float} or @samp{.single},
916 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
917 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
918 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
919 only supports this format via the @samp{fldt} (load 80-bit real to stack
920 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
922 @cindex @code{word} directive, i386
923 @cindex @code{long} directive, i386
924 @cindex @code{int} directive, i386
925 @cindex @code{quad} directive, i386
926 @cindex @code{word} directive, x86-64
927 @cindex @code{long} directive, x86-64
928 @cindex @code{int} directive, x86-64
929 @cindex @code{quad} directive, x86-64
931 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
932 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
933 corresponding instruction mnemonic suffixes are @samp{s} (single),
934 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
935 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
936 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
940 Register to register operations should not use instruction mnemonic suffixes.
941 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
942 wrote @samp{fst %st, %st(1)}, since all register to register operations
943 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
944 which converts @samp{%st} from 80-bit to 64-bit floating point format,
945 then stores the result in the 4 byte location @samp{mem})
948 @section Intel's MMX and AMD's 3DNow! SIMD Operations
954 @cindex 3DNow!, x86-64
957 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
958 instructions for integer data), available on Intel's Pentium MMX
959 processors and Pentium II processors, AMD's K6 and K6-2 processors,
960 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
961 instruction set (SIMD instructions for 32-bit floating point data)
962 available on AMD's K6-2 processor and possibly others in the future.
964 Currently, @code{@value{AS}} does not support Intel's floating point
967 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
968 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
969 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
970 floating point values. The MMX registers cannot be used at the same time
971 as the floating point stack.
973 See Intel and AMD documentation, keeping in mind that the operand order in
974 instructions is reversed from the Intel syntax.
977 @section AMD's Lightweight Profiling Instructions
982 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
983 instruction set, available on AMD's Family 15h (Orochi) processors.
985 LWP enables applications to collect and manage performance data, and
986 react to performance events. The collection of performance data
987 requires no context switches. LWP runs in the context of a thread and
988 so several counters can be used independently across multiple threads.
989 LWP can be used in both 64-bit and legacy 32-bit modes.
991 For detailed information on the LWP instruction set, see the
992 @cite{AMD Lightweight Profiling Specification} available at
993 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
996 @section Bit Manipulation Instructions
1001 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1003 BMI instructions provide several instructions implementing individual
1004 bit manipulation operations such as isolation, masking, setting, or
1007 @c Need to add a specification citation here when available.
1010 @section AMD's Trailing Bit Manipulation Instructions
1015 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1016 instruction set, available on AMD's BDVER2 processors (Trinity and
1019 TBM instructions provide instructions implementing individual bit
1020 manipulation operations such as isolating, masking, setting, resetting,
1021 complementing, and operations on trailing zeros and ones.
1023 @c Need to add a specification citation here when available.
1026 @section Writing 16-bit Code
1028 @cindex i386 16-bit code
1029 @cindex 16-bit code, i386
1030 @cindex real-mode code, i386
1031 @cindex @code{code16gcc} directive, i386
1032 @cindex @code{code16} directive, i386
1033 @cindex @code{code32} directive, i386
1034 @cindex @code{code64} directive, i386
1035 @cindex @code{code64} directive, x86-64
1036 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1037 or 64-bit x86-64 code depending on the default configuration,
1038 it also supports writing code to run in real mode or in 16-bit protected
1039 mode code segments. To do this, put a @samp{.code16} or
1040 @samp{.code16gcc} directive before the assembly language instructions to
1041 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1042 32-bit code with the @samp{.code32} directive or 64-bit code with the
1043 @samp{.code64} directive.
1045 @samp{.code16gcc} provides experimental support for generating 16-bit
1046 code from gcc, and differs from @samp{.code16} in that @samp{call},
1047 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1048 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1049 default to 32-bit size. This is so that the stack pointer is
1050 manipulated in the same way over function calls, allowing access to
1051 function parameters at the same stack offsets as in 32-bit mode.
1052 @samp{.code16gcc} also automatically adds address size prefixes where
1053 necessary to use the 32-bit addressing modes that gcc generates.
1055 The code which @code{@value{AS}} generates in 16-bit mode will not
1056 necessarily run on a 16-bit pre-80386 processor. To write code that
1057 runs on such a processor, you must refrain from using @emph{any} 32-bit
1058 constructs which require @code{@value{AS}} to output address or operand
1061 Note that writing 16-bit code instructions by explicitly specifying a
1062 prefix or an instruction mnemonic suffix within a 32-bit code section
1063 generates different machine instructions than those generated for a
1064 16-bit code segment. In a 32-bit code section, the following code
1065 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1066 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1072 The same code in a 16-bit code section would generate the machine
1073 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1074 is correct since the processor default operand size is assumed to be 16
1075 bits in a 16-bit code section.
1078 @section Specifying CPU Architecture
1080 @cindex arch directive, i386
1081 @cindex i386 arch directive
1082 @cindex arch directive, x86-64
1083 @cindex x86-64 arch directive
1085 @code{@value{AS}} may be told to assemble for a particular CPU
1086 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1087 directive enables a warning when gas detects an instruction that is not
1088 supported on the CPU specified. The choices for @var{cpu_type} are:
1090 @multitable @columnfractions .20 .20 .20 .20
1091 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1092 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1093 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1094 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1095 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1096 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1097 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1098 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1099 @item @samp{generic32} @tab @samp{generic64}
1100 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1101 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1102 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1103 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1104 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1105 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1106 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1107 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1108 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1109 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1110 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1111 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1112 @item @samp{.avx512vbmi} @tab @samp{.clwb} @tab @samp{.pcommit}
1113 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1114 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1115 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1116 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1119 Apart from the warning, there are only two other effects on
1120 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1121 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1122 will automatically use a two byte opcode sequence. The larger three
1123 byte opcode sequence is used on the 486 (and when no architecture is
1124 specified) because it executes faster on the 486. Note that you can
1125 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1126 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1127 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1128 conditional jumps will be promoted when necessary to a two instruction
1129 sequence consisting of a conditional jump of the opposite sense around
1130 an unconditional jump to the target.
1132 Following the CPU architecture (but not a sub-architecture, which are those
1133 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1134 control automatic promotion of conditional jumps. @samp{jumps} is the
1135 default, and enables jump promotion; All external jumps will be of the long
1136 variety, and file-local jumps will be promoted as necessary.
1137 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1138 byte offset jumps, and warns about file-local conditional jumps that
1139 @code{@value{AS}} promotes.
1140 Unconditional jumps are treated as for @samp{jumps}.
1149 @section AT&T Syntax bugs
1151 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1152 assemblers, generate floating point instructions with reversed source
1153 and destination registers in certain cases. Unfortunately, gcc and
1154 possibly many other programs use this reversed syntax, so we're stuck
1163 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1164 than the expected @samp{%st(3) - %st}. This happens with all the
1165 non-commutative arithmetic floating point operations with two register
1166 operands where the source register is @samp{%st} and the destination
1167 register is @samp{%st(i)}.
1172 @cindex i386 @code{mul}, @code{imul} instructions
1173 @cindex @code{mul} instruction, i386
1174 @cindex @code{imul} instruction, i386
1175 @cindex @code{mul} instruction, x86-64
1176 @cindex @code{imul} instruction, x86-64
1177 There is some trickery concerning the @samp{mul} and @samp{imul}
1178 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1179 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1180 for @samp{imul}) can be output only in the one operand form. Thus,
1181 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1182 the expanding multiply would clobber the @samp{%edx} register, and this
1183 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1184 64-bit product in @samp{%edx:%eax}.
1186 We have added a two operand form of @samp{imul} when the first operand
1187 is an immediate mode expression and the second operand is a register.
1188 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1189 example, can be done with @samp{imul $69, %eax} rather than @samp{imul