1 @c Copyright (C) 1991-2018 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
78 byte nop (0x90) is explicitly specified as the fill byte for alignment.
80 @cindex @samp{--divide} option, i386
82 On SVR4-derived platforms, the character @samp{/} is treated as a comment
83 character, which means that it cannot be used in expressions. The
84 @samp{--divide} option turns @samp{/} into a normal character. This does
85 not disable @samp{/} at the beginning of a line starting a comment, or
86 affect using @samp{#} for starting a comment.
88 @cindex @samp{-march=} option, i386
89 @cindex @samp{-march=} option, x86-64
90 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
91 This option specifies the target processor. The assembler will
92 issue an error message if an attempt is made to assemble an instruction
93 which will not execute on the target processor. The following
94 processor names are recognized:
131 In addition to the basic instruction set, the assembler can be told to
132 accept various extension mnemonics. For example,
133 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
134 @var{vmx}. The following extensions are currently supported:
188 @code{avx512_4fmaps},
189 @code{avx512_4vnniw},
190 @code{avx512_vpopcntdq},
193 @code{avx512_bitalg},
203 @code{noavx512_4fmaps},
204 @code{noavx512_4vnniw},
205 @code{noavx512_vpopcntdq},
206 @code{noavx512_vbmi2},
207 @code{noavx512_vnni},
208 @code{noavx512_bitalg},
247 Note that rather than extending a basic instruction set, the extension
248 mnemonics starting with @code{no} revoke the respective functionality.
250 When the @code{.arch} directive is used with @option{-march}, the
251 @code{.arch} directive will take precedent.
253 @cindex @samp{-mtune=} option, i386
254 @cindex @samp{-mtune=} option, x86-64
255 @item -mtune=@var{CPU}
256 This option specifies a processor to optimize for. When used in
257 conjunction with the @option{-march} option, only instructions
258 of the processor specified by the @option{-march} option will be
261 Valid @var{CPU} values are identical to the processor list of
262 @option{-march=@var{CPU}}.
264 @cindex @samp{-msse2avx} option, i386
265 @cindex @samp{-msse2avx} option, x86-64
267 This option specifies that the assembler should encode SSE instructions
270 @cindex @samp{-msse-check=} option, i386
271 @cindex @samp{-msse-check=} option, x86-64
272 @item -msse-check=@var{none}
273 @itemx -msse-check=@var{warning}
274 @itemx -msse-check=@var{error}
275 These options control if the assembler should check SSE instructions.
276 @option{-msse-check=@var{none}} will make the assembler not to check SSE
277 instructions, which is the default. @option{-msse-check=@var{warning}}
278 will make the assembler issue a warning for any SSE instruction.
279 @option{-msse-check=@var{error}} will make the assembler issue an error
280 for any SSE instruction.
282 @cindex @samp{-mavxscalar=} option, i386
283 @cindex @samp{-mavxscalar=} option, x86-64
284 @item -mavxscalar=@var{128}
285 @itemx -mavxscalar=@var{256}
286 These options control how the assembler should encode scalar AVX
287 instructions. @option{-mavxscalar=@var{128}} will encode scalar
288 AVX instructions with 128bit vector length, which is the default.
289 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
290 with 256bit vector length.
292 @cindex @samp{-mevexlig=} option, i386
293 @cindex @samp{-mevexlig=} option, x86-64
294 @item -mevexlig=@var{128}
295 @itemx -mevexlig=@var{256}
296 @itemx -mevexlig=@var{512}
297 These options control how the assembler should encode length-ignored
298 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
299 EVEX instructions with 128bit vector length, which is the default.
300 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
301 encode LIG EVEX instructions with 256bit and 512bit vector length,
304 @cindex @samp{-mevexwig=} option, i386
305 @cindex @samp{-mevexwig=} option, x86-64
306 @item -mevexwig=@var{0}
307 @itemx -mevexwig=@var{1}
308 These options control how the assembler should encode w-ignored (WIG)
309 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
310 EVEX instructions with evex.w = 0, which is the default.
311 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
314 @cindex @samp{-mmnemonic=} option, i386
315 @cindex @samp{-mmnemonic=} option, x86-64
316 @item -mmnemonic=@var{att}
317 @itemx -mmnemonic=@var{intel}
318 This option specifies instruction mnemonic for matching instructions.
319 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
322 @cindex @samp{-msyntax=} option, i386
323 @cindex @samp{-msyntax=} option, x86-64
324 @item -msyntax=@var{att}
325 @itemx -msyntax=@var{intel}
326 This option specifies instruction syntax when processing instructions.
327 The @code{.att_syntax} and @code{.intel_syntax} directives will
330 @cindex @samp{-mnaked-reg} option, i386
331 @cindex @samp{-mnaked-reg} option, x86-64
333 This option specifies that registers don't require a @samp{%} prefix.
334 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
336 @cindex @samp{-madd-bnd-prefix} option, i386
337 @cindex @samp{-madd-bnd-prefix} option, x86-64
338 @item -madd-bnd-prefix
339 This option forces the assembler to add BND prefix to all branches, even
340 if such prefix was not explicitly specified in the source code.
342 @cindex @samp{-mshared} option, i386
343 @cindex @samp{-mshared} option, x86-64
345 On ELF target, the assembler normally optimizes out non-PLT relocations
346 against defined non-weak global branch targets with default visibility.
347 The @samp{-mshared} option tells the assembler to generate code which
348 may go into a shared library where all non-weak global branch targets
349 with default visibility can be preempted. The resulting code is
350 slightly bigger. This option only affects the handling of branch
353 @cindex @samp{-mbig-obj} option, x86-64
355 On x86-64 PE/COFF target this option forces the use of big object file
356 format, which allows more than 32768 sections.
358 @cindex @samp{-momit-lock-prefix=} option, i386
359 @cindex @samp{-momit-lock-prefix=} option, x86-64
360 @item -momit-lock-prefix=@var{no}
361 @itemx -momit-lock-prefix=@var{yes}
362 These options control how the assembler should encode lock prefix.
363 This option is intended as a workaround for processors, that fail on
364 lock prefix. This option can only be safely used with single-core,
365 single-thread computers
366 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
367 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
368 which is the default.
370 @cindex @samp{-mfence-as-lock-add=} option, i386
371 @cindex @samp{-mfence-as-lock-add=} option, x86-64
372 @item -mfence-as-lock-add=@var{no}
373 @itemx -mfence-as-lock-add=@var{yes}
374 These options control how the assembler should encode lfence, mfence and
376 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
377 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
378 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
379 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
380 sfence as usual, which is the default.
382 @cindex @samp{-mrelax-relocations=} option, i386
383 @cindex @samp{-mrelax-relocations=} option, x86-64
384 @item -mrelax-relocations=@var{no}
385 @itemx -mrelax-relocations=@var{yes}
386 These options control whether the assembler should generate relax
387 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
388 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
389 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
390 @option{-mrelax-relocations=@var{no}} will not generate relax
391 relocations. The default can be controlled by a configure option
392 @option{--enable-x86-relax-relocations}.
394 @cindex @samp{-mevexrcig=} option, i386
395 @cindex @samp{-mevexrcig=} option, x86-64
396 @item -mevexrcig=@var{rne}
397 @itemx -mevexrcig=@var{rd}
398 @itemx -mevexrcig=@var{ru}
399 @itemx -mevexrcig=@var{rz}
400 These options control how the assembler should encode SAE-only
401 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
402 of EVEX instruction with 00, which is the default.
403 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
404 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
405 with 01, 10 and 11 RC bits, respectively.
407 @cindex @samp{-mamd64} option, x86-64
408 @cindex @samp{-mintel64} option, x86-64
411 This option specifies that the assembler should accept only AMD64 or
412 Intel64 ISA in 64-bit mode. The default is to accept both.
414 @cindex @samp{-O0} option, i386
415 @cindex @samp{-O0} option, x86-64
416 @cindex @samp{-O} option, i386
417 @cindex @samp{-O} option, x86-64
418 @cindex @samp{-O1} option, i386
419 @cindex @samp{-O1} option, x86-64
420 @cindex @samp{-O2} option, i386
421 @cindex @samp{-O2} option, x86-64
422 @cindex @samp{-Os} option, i386
423 @cindex @samp{-Os} option, x86-64
424 @item -O0 | -O | -O1 | -O2 | -Os
425 Optimize instruction encoding with smaller instruction size. @samp{-O}
426 and @samp{-O1} encode 64-bit register load instructions with 64-bit
427 immediate as 32-bit register load instructions with 31-bit or 32-bits
428 immediates and encode 64-bit register clearing instructions with 32-bit
429 register clearing instructions. @samp{-O2} includes @samp{-O1}
430 optimization plus encodes 256-bit and 512-bit vector register clearing
431 instructions with 128-bit vector register clearing instructions.
432 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
433 and 64-bit register tests with immediate as 8-bit register test with
434 immediate. @samp{-O0} turns off this optimization.
439 @node i386-Directives
440 @section x86 specific Directives
442 @cindex machine directives, x86
443 @cindex x86 machine directives
446 @cindex @code{lcomm} directive, COFF
447 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
448 Reserve @var{length} (an absolute expression) bytes for a local common
449 denoted by @var{symbol}. The section and value of @var{symbol} are
450 those of the new local common. The addresses are allocated in the bss
451 section, so that at run-time the bytes start off zeroed. Since
452 @var{symbol} is not declared global, it is normally not visible to
453 @code{@value{LD}}. The optional third parameter, @var{alignment},
454 specifies the desired alignment of the symbol in the bss section.
456 This directive is only available for COFF based x86 targets.
458 @cindex @code{largecomm} directive, ELF
459 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
460 This directive behaves in the same way as the @code{comm} directive
461 except that the data is placed into the @var{.lbss} section instead of
462 the @var{.bss} section @ref{Comm}.
464 The directive is intended to be used for data which requires a large
465 amount of space, and it is only available for ELF based x86_64
468 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
473 @section i386 Syntactical Considerations
475 * i386-Variations:: AT&T Syntax versus Intel Syntax
476 * i386-Chars:: Special Characters
479 @node i386-Variations
480 @subsection AT&T Syntax versus Intel Syntax
482 @cindex i386 intel_syntax pseudo op
483 @cindex intel_syntax pseudo op, i386
484 @cindex i386 att_syntax pseudo op
485 @cindex att_syntax pseudo op, i386
486 @cindex i386 syntax compatibility
487 @cindex syntax compatibility, i386
488 @cindex x86-64 intel_syntax pseudo op
489 @cindex intel_syntax pseudo op, x86-64
490 @cindex x86-64 att_syntax pseudo op
491 @cindex att_syntax pseudo op, x86-64
492 @cindex x86-64 syntax compatibility
493 @cindex syntax compatibility, x86-64
495 @code{@value{AS}} now supports assembly using Intel assembler syntax.
496 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
497 back to the usual AT&T mode for compatibility with the output of
498 @code{@value{GCC}}. Either of these directives may have an optional
499 argument, @code{prefix}, or @code{noprefix} specifying whether registers
500 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
501 different from Intel syntax. We mention these differences because
502 almost all 80386 documents use Intel syntax. Notable differences
503 between the two syntaxes are:
505 @cindex immediate operands, i386
506 @cindex i386 immediate operands
507 @cindex register operands, i386
508 @cindex i386 register operands
509 @cindex jump/call operands, i386
510 @cindex i386 jump/call operands
511 @cindex operand delimiters, i386
513 @cindex immediate operands, x86-64
514 @cindex x86-64 immediate operands
515 @cindex register operands, x86-64
516 @cindex x86-64 register operands
517 @cindex jump/call operands, x86-64
518 @cindex x86-64 jump/call operands
519 @cindex operand delimiters, x86-64
522 AT&T immediate operands are preceded by @samp{$}; Intel immediate
523 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
524 AT&T register operands are preceded by @samp{%}; Intel register operands
525 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
526 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
528 @cindex i386 source, destination operands
529 @cindex source, destination operands; i386
530 @cindex x86-64 source, destination operands
531 @cindex source, destination operands; x86-64
533 AT&T and Intel syntax use the opposite order for source and destination
534 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
535 @samp{source, dest} convention is maintained for compatibility with
536 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
537 instructions with 2 immediate operands, such as the @samp{enter}
538 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
540 @cindex mnemonic suffixes, i386
541 @cindex sizes operands, i386
542 @cindex i386 size suffixes
543 @cindex mnemonic suffixes, x86-64
544 @cindex sizes operands, x86-64
545 @cindex x86-64 size suffixes
547 In AT&T syntax the size of memory operands is determined from the last
548 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
549 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
550 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
551 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
552 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
553 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
556 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
557 instruction with the 64-bit displacement or immediate operand.
559 @cindex return instructions, i386
560 @cindex i386 jump, call, return
561 @cindex return instructions, x86-64
562 @cindex x86-64 jump, call, return
564 Immediate form long jumps and calls are
565 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
567 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
569 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
570 @samp{ret far @var{stack-adjust}}.
572 @cindex sections, i386
573 @cindex i386 sections
574 @cindex sections, x86-64
575 @cindex x86-64 sections
577 The AT&T assembler does not provide support for multiple section
578 programs. Unix style systems expect all programs to be single sections.
582 @subsection Special Characters
584 @cindex line comment character, i386
585 @cindex i386 line comment character
586 The presence of a @samp{#} appearing anywhere on a line indicates the
587 start of a comment that extends to the end of that line.
589 If a @samp{#} appears as the first character of a line then the whole
590 line is treated as a comment, but in this case the line can also be a
591 logical line number directive (@pxref{Comments}) or a preprocessor
592 control command (@pxref{Preprocessing}).
594 If the @option{--divide} command line option has not been specified
595 then the @samp{/} character appearing anywhere on a line also
596 introduces a line comment.
598 @cindex line separator, i386
599 @cindex statement separator, i386
600 @cindex i386 line separator
601 The @samp{;} character can be used to separate statements on the same
605 @section i386-Mnemonics
606 @subsection Instruction Naming
608 @cindex i386 instruction naming
609 @cindex instruction naming, i386
610 @cindex x86-64 instruction naming
611 @cindex instruction naming, x86-64
613 Instruction mnemonics are suffixed with one character modifiers which
614 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
615 and @samp{q} specify byte, word, long and quadruple word operands. If
616 no suffix is specified by an instruction then @code{@value{AS}} tries to
617 fill in the missing suffix based on the destination register operand
618 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
619 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
620 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
621 assembler which assumes that a missing mnemonic suffix implies long
622 operand size. (This incompatibility does not affect compiler output
623 since compilers always explicitly specify the mnemonic suffix.)
625 Almost all instructions have the same names in AT&T and Intel format.
626 There are a few exceptions. The sign extend and zero extend
627 instructions need two sizes to specify them. They need a size to
628 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
629 is accomplished by using two instruction mnemonic suffixes in AT&T
630 syntax. Base names for sign extend and zero extend are
631 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
632 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
633 are tacked on to this base name, the @emph{from} suffix before the
634 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
635 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
636 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
637 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
638 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
641 @cindex encoding options, i386
642 @cindex encoding options, x86-64
644 Different encoding options can be specified via pseudo prefixes:
648 @samp{@{disp8@}} -- prefer 8-bit displacement.
651 @samp{@{disp32@}} -- prefer 32-bit displacement.
654 @samp{@{load@}} -- prefer load-form instruction.
657 @samp{@{store@}} -- prefer store-form instruction.
660 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
663 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
666 @samp{@{evex@}} -- encode with EVEX prefix.
669 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
670 instructions (x86-64 only). Note that this differs from the @samp{rex}
671 prefix which generates REX prefix unconditionally.
674 @samp{@{nooptimize@}} -- disable instruction size optimization.
677 @cindex conversion instructions, i386
678 @cindex i386 conversion instructions
679 @cindex conversion instructions, x86-64
680 @cindex x86-64 conversion instructions
681 The Intel-syntax conversion instructions
685 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
688 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
691 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
694 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
697 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
701 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
702 @samp{%rdx:%rax} (x86-64 only),
706 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
707 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
710 @cindex jump instructions, i386
711 @cindex call instructions, i386
712 @cindex jump instructions, x86-64
713 @cindex call instructions, x86-64
714 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
715 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
718 @subsection AT&T Mnemonic versus Intel Mnemonic
720 @cindex i386 mnemonic compatibility
721 @cindex mnemonic compatibility, i386
723 @code{@value{AS}} supports assembly using Intel mnemonic.
724 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
725 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
726 syntax for compatibility with the output of @code{@value{GCC}}.
727 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
728 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
729 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
730 assembler with different mnemonics from those in Intel IA32 specification.
731 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
734 @section Register Naming
736 @cindex i386 registers
737 @cindex registers, i386
738 @cindex x86-64 registers
739 @cindex registers, x86-64
740 Register operands are always prefixed with @samp{%}. The 80386 registers
745 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
746 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
747 frame pointer), and @samp{%esp} (the stack pointer).
750 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
751 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
754 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
755 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
756 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
757 @samp{%cx}, and @samp{%dx})
760 the 6 section registers @samp{%cs} (code section), @samp{%ds}
761 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
765 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
766 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
769 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
770 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
773 the 2 test registers @samp{%tr6} and @samp{%tr7}.
776 the 8 floating point register stack @samp{%st} or equivalently
777 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
778 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
779 These registers are overloaded by 8 MMX registers @samp{%mm0},
780 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
781 @samp{%mm6} and @samp{%mm7}.
784 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
785 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
788 The AMD x86-64 architecture extends the register set by:
792 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
793 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
794 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
798 the 8 extended registers @samp{%r8}--@samp{%r15}.
801 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
804 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
807 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
810 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
813 the 8 debug registers: @samp{%db8}--@samp{%db15}.
816 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
819 With the AVX extensions more registers were made available:
824 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
825 available in 32-bit mode). The bottom 128 bits are overlaid with the
826 @samp{xmm0}--@samp{xmm15} registers.
830 The AVX2 extensions made in 64-bit mode more registers available:
835 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
836 registers @samp{%ymm16}--@samp{%ymm31}.
840 The AVX512 extensions added the following registers:
845 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
846 available in 32-bit mode). The bottom 128 bits are overlaid with the
847 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
848 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
851 the 8 mask registers @samp{%k0}--@samp{%k7}.
856 @section Instruction Prefixes
858 @cindex i386 instruction prefixes
859 @cindex instruction prefixes, i386
860 @cindex prefixes, i386
861 Instruction prefixes are used to modify the following instruction. They
862 are used to repeat string instructions, to provide section overrides, to
863 perform bus lock operations, and to change operand and address sizes.
864 (Most instructions that normally operate on 32-bit operands will use
865 16-bit operands if the instruction has an ``operand size'' prefix.)
866 Instruction prefixes are best written on the same line as the instruction
867 they act upon. For example, the @samp{scas} (scan string) instruction is
871 repne scas %es:(%edi),%al
874 You may also place prefixes on the lines immediately preceding the
875 instruction, but this circumvents checks that @code{@value{AS}} does
876 with prefixes, and will not work with all prefixes.
878 Here is a list of instruction prefixes:
880 @cindex section override prefixes, i386
883 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
884 @samp{fs}, @samp{gs}. These are automatically added by specifying
885 using the @var{section}:@var{memory-operand} form for memory references.
887 @cindex size prefixes, i386
889 Operand/Address size prefixes @samp{data16} and @samp{addr16}
890 change 32-bit operands/addresses into 16-bit operands/addresses,
891 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
892 @code{.code16} section) into 32-bit operands/addresses. These prefixes
893 @emph{must} appear on the same line of code as the instruction they
894 modify. For example, in a 16-bit @code{.code16} section, you might
901 @cindex bus lock prefixes, i386
902 @cindex inhibiting interrupts, i386
904 The bus lock prefix @samp{lock} inhibits interrupts during execution of
905 the instruction it precedes. (This is only valid with certain
906 instructions; see a 80386 manual for details).
908 @cindex coprocessor wait, i386
910 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
911 complete the current instruction. This should never be needed for the
912 80386/80387 combination.
914 @cindex repeat prefixes, i386
916 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
917 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
918 times if the current address size is 16-bits).
919 @cindex REX prefixes, i386
921 The @samp{rex} family of prefixes is used by x86-64 to encode
922 extensions to i386 instruction set. The @samp{rex} prefix has four
923 bits --- an operand size overwrite (@code{64}) used to change operand size
924 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
927 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
928 instruction emits @samp{rex} prefix with all the bits set. By omitting
929 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
930 prefixes as well. Normally, there is no need to write the prefixes
931 explicitly, since gas will automatically generate them based on the
932 instruction operands.
936 @section Memory References
938 @cindex i386 memory references
939 @cindex memory references, i386
940 @cindex x86-64 memory references
941 @cindex memory references, x86-64
942 An Intel syntax indirect memory reference of the form
945 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
949 is translated into the AT&T syntax
952 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
956 where @var{base} and @var{index} are the optional 32-bit base and
957 index registers, @var{disp} is the optional displacement, and
958 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
959 to calculate the address of the operand. If no @var{scale} is
960 specified, @var{scale} is taken to be 1. @var{section} specifies the
961 optional section register for the memory operand, and may override the
962 default section register (see a 80386 manual for section register
963 defaults). Note that section overrides in AT&T syntax @emph{must}
964 be preceded by a @samp{%}. If you specify a section override which
965 coincides with the default section register, @code{@value{AS}} does @emph{not}
966 output any section register override prefixes to assemble the given
967 instruction. Thus, section overrides can be specified to emphasize which
968 section register is used for a given memory operand.
970 Here are some examples of Intel and AT&T style memory references:
973 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
974 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
975 missing, and the default section is used (@samp{%ss} for addressing with
976 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
978 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
979 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
980 @samp{foo}. All other fields are missing. The section register here
981 defaults to @samp{%ds}.
983 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
984 This uses the value pointed to by @samp{foo} as a memory operand.
985 Note that @var{base} and @var{index} are both missing, but there is only
986 @emph{one} @samp{,}. This is a syntactic exception.
988 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
989 This selects the contents of the variable @samp{foo} with section
990 register @var{section} being @samp{%gs}.
993 Absolute (as opposed to PC relative) call and jump operands must be
994 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
995 always chooses PC relative addressing for jump/call labels.
997 Any instruction that has a memory operand, but no register operand,
998 @emph{must} specify its size (byte, word, long, or quadruple) with an
999 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1002 The x86-64 architecture adds an RIP (instruction pointer relative)
1003 addressing. This addressing mode is specified by using @samp{rip} as a
1004 base register. Only constant offsets are valid. For example:
1007 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1008 Points to the address 1234 bytes past the end of the current
1011 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1012 Points to the @code{symbol} in RIP relative way, this is shorter than
1013 the default absolute addressing.
1016 Other addressing modes remain unchanged in x86-64 architecture, except
1017 registers used are 64-bit instead of 32-bit.
1020 @section Handling of Jump Instructions
1022 @cindex jump optimization, i386
1023 @cindex i386 jump optimization
1024 @cindex jump optimization, x86-64
1025 @cindex x86-64 jump optimization
1026 Jump instructions are always optimized to use the smallest possible
1027 displacements. This is accomplished by using byte (8-bit) displacement
1028 jumps whenever the target is sufficiently close. If a byte displacement
1029 is insufficient a long displacement is used. We do not support
1030 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1031 instruction with the @samp{data16} instruction prefix), since the 80386
1032 insists upon masking @samp{%eip} to 16 bits after the word displacement
1033 is added. (See also @pxref{i386-Arch})
1035 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1036 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1037 displacements, so that if you use these instructions (@code{@value{GCC}} does
1038 not use them) you may get an error message (and incorrect code). The AT&T
1039 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1050 @section Floating Point
1052 @cindex i386 floating point
1053 @cindex floating point, i386
1054 @cindex x86-64 floating point
1055 @cindex floating point, x86-64
1056 All 80387 floating point types except packed BCD are supported.
1057 (BCD support may be added without much difficulty). These data
1058 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1059 double (64-bit), and extended (80-bit) precision floating point.
1060 Each supported type has an instruction mnemonic suffix and a constructor
1061 associated with it. Instruction mnemonic suffixes specify the operand's
1062 data type. Constructors build these data types into memory.
1064 @cindex @code{float} directive, i386
1065 @cindex @code{single} directive, i386
1066 @cindex @code{double} directive, i386
1067 @cindex @code{tfloat} directive, i386
1068 @cindex @code{float} directive, x86-64
1069 @cindex @code{single} directive, x86-64
1070 @cindex @code{double} directive, x86-64
1071 @cindex @code{tfloat} directive, x86-64
1074 Floating point constructors are @samp{.float} or @samp{.single},
1075 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1076 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1077 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1078 only supports this format via the @samp{fldt} (load 80-bit real to stack
1079 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1081 @cindex @code{word} directive, i386
1082 @cindex @code{long} directive, i386
1083 @cindex @code{int} directive, i386
1084 @cindex @code{quad} directive, i386
1085 @cindex @code{word} directive, x86-64
1086 @cindex @code{long} directive, x86-64
1087 @cindex @code{int} directive, x86-64
1088 @cindex @code{quad} directive, x86-64
1090 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1091 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1092 corresponding instruction mnemonic suffixes are @samp{s} (single),
1093 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1094 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1095 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1096 stack) instructions.
1099 Register to register operations should not use instruction mnemonic suffixes.
1100 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1101 wrote @samp{fst %st, %st(1)}, since all register to register operations
1102 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1103 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1104 then stores the result in the 4 byte location @samp{mem})
1107 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1110 @cindex 3DNow!, i386
1113 @cindex 3DNow!, x86-64
1114 @cindex SIMD, x86-64
1116 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1117 instructions for integer data), available on Intel's Pentium MMX
1118 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1119 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1120 instruction set (SIMD instructions for 32-bit floating point data)
1121 available on AMD's K6-2 processor and possibly others in the future.
1123 Currently, @code{@value{AS}} does not support Intel's floating point
1126 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1127 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1128 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1129 floating point values. The MMX registers cannot be used at the same time
1130 as the floating point stack.
1132 See Intel and AMD documentation, keeping in mind that the operand order in
1133 instructions is reversed from the Intel syntax.
1136 @section AMD's Lightweight Profiling Instructions
1141 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1142 instruction set, available on AMD's Family 15h (Orochi) processors.
1144 LWP enables applications to collect and manage performance data, and
1145 react to performance events. The collection of performance data
1146 requires no context switches. LWP runs in the context of a thread and
1147 so several counters can be used independently across multiple threads.
1148 LWP can be used in both 64-bit and legacy 32-bit modes.
1150 For detailed information on the LWP instruction set, see the
1151 @cite{AMD Lightweight Profiling Specification} available at
1152 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1155 @section Bit Manipulation Instructions
1160 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1162 BMI instructions provide several instructions implementing individual
1163 bit manipulation operations such as isolation, masking, setting, or
1166 @c Need to add a specification citation here when available.
1169 @section AMD's Trailing Bit Manipulation Instructions
1174 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1175 instruction set, available on AMD's BDVER2 processors (Trinity and
1178 TBM instructions provide instructions implementing individual bit
1179 manipulation operations such as isolating, masking, setting, resetting,
1180 complementing, and operations on trailing zeros and ones.
1182 @c Need to add a specification citation here when available.
1185 @section Writing 16-bit Code
1187 @cindex i386 16-bit code
1188 @cindex 16-bit code, i386
1189 @cindex real-mode code, i386
1190 @cindex @code{code16gcc} directive, i386
1191 @cindex @code{code16} directive, i386
1192 @cindex @code{code32} directive, i386
1193 @cindex @code{code64} directive, i386
1194 @cindex @code{code64} directive, x86-64
1195 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1196 or 64-bit x86-64 code depending on the default configuration,
1197 it also supports writing code to run in real mode or in 16-bit protected
1198 mode code segments. To do this, put a @samp{.code16} or
1199 @samp{.code16gcc} directive before the assembly language instructions to
1200 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1201 32-bit code with the @samp{.code32} directive or 64-bit code with the
1202 @samp{.code64} directive.
1204 @samp{.code16gcc} provides experimental support for generating 16-bit
1205 code from gcc, and differs from @samp{.code16} in that @samp{call},
1206 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1207 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1208 default to 32-bit size. This is so that the stack pointer is
1209 manipulated in the same way over function calls, allowing access to
1210 function parameters at the same stack offsets as in 32-bit mode.
1211 @samp{.code16gcc} also automatically adds address size prefixes where
1212 necessary to use the 32-bit addressing modes that gcc generates.
1214 The code which @code{@value{AS}} generates in 16-bit mode will not
1215 necessarily run on a 16-bit pre-80386 processor. To write code that
1216 runs on such a processor, you must refrain from using @emph{any} 32-bit
1217 constructs which require @code{@value{AS}} to output address or operand
1220 Note that writing 16-bit code instructions by explicitly specifying a
1221 prefix or an instruction mnemonic suffix within a 32-bit code section
1222 generates different machine instructions than those generated for a
1223 16-bit code segment. In a 32-bit code section, the following code
1224 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1225 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1231 The same code in a 16-bit code section would generate the machine
1232 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1233 is correct since the processor default operand size is assumed to be 16
1234 bits in a 16-bit code section.
1237 @section Specifying CPU Architecture
1239 @cindex arch directive, i386
1240 @cindex i386 arch directive
1241 @cindex arch directive, x86-64
1242 @cindex x86-64 arch directive
1244 @code{@value{AS}} may be told to assemble for a particular CPU
1245 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1246 directive enables a warning when gas detects an instruction that is not
1247 supported on the CPU specified. The choices for @var{cpu_type} are:
1249 @multitable @columnfractions .20 .20 .20 .20
1250 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1251 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1252 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1253 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1254 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1255 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1256 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1257 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1258 @item @samp{generic32} @tab @samp{generic64}
1259 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1260 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1261 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1262 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1263 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1264 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1265 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1266 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1267 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1268 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1269 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1270 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1271 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1272 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1273 @item @samp{.avx512_bitalg}
1274 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1275 @item @samp{.wbnoinvd} @tab @samp{.pconfig}
1276 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1277 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1278 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1279 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1280 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1283 Apart from the warning, there are only two other effects on
1284 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1285 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1286 will automatically use a two byte opcode sequence. The larger three
1287 byte opcode sequence is used on the 486 (and when no architecture is
1288 specified) because it executes faster on the 486. Note that you can
1289 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1290 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1291 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1292 conditional jumps will be promoted when necessary to a two instruction
1293 sequence consisting of a conditional jump of the opposite sense around
1294 an unconditional jump to the target.
1296 Following the CPU architecture (but not a sub-architecture, which are those
1297 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1298 control automatic promotion of conditional jumps. @samp{jumps} is the
1299 default, and enables jump promotion; All external jumps will be of the long
1300 variety, and file-local jumps will be promoted as necessary.
1301 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1302 byte offset jumps, and warns about file-local conditional jumps that
1303 @code{@value{AS}} promotes.
1304 Unconditional jumps are treated as for @samp{jumps}.
1313 @section AT&T Syntax bugs
1315 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1316 assemblers, generate floating point instructions with reversed source
1317 and destination registers in certain cases. Unfortunately, gcc and
1318 possibly many other programs use this reversed syntax, so we're stuck
1327 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1328 than the expected @samp{%st(3) - %st}. This happens with all the
1329 non-commutative arithmetic floating point operations with two register
1330 operands where the source register is @samp{%st} and the destination
1331 register is @samp{%st(i)}.
1336 @cindex i386 @code{mul}, @code{imul} instructions
1337 @cindex @code{mul} instruction, i386
1338 @cindex @code{imul} instruction, i386
1339 @cindex @code{mul} instruction, x86-64
1340 @cindex @code{imul} instruction, x86-64
1341 There is some trickery concerning the @samp{mul} and @samp{imul}
1342 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1343 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1344 for @samp{imul}) can be output only in the one operand form. Thus,
1345 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1346 the expanding multiply would clobber the @samp{%edx} register, and this
1347 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1348 64-bit product in @samp{%edx:%eax}.
1350 We have added a two operand form of @samp{imul} when the first operand
1351 is an immediate mode expression and the second operand is a register.
1352 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1353 example, can be done with @samp{imul $69, %eax} rather than @samp{imul