1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
2 @c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: AT&T Syntax versus Intel Syntax
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-16bit:: Writing 16-bit Code
37 * i386-Arch:: Specifying an x86 CPU architecture
38 * i386-Bugs:: AT&T Syntax bugs
45 @cindex options for i386
46 @cindex options for x86-64
48 @cindex x86-64 options
50 The i386 version of @code{@value{AS}} has a few machine
54 @cindex @samp{--32} option, i386
55 @cindex @samp{--32} option, x86-64
56 @cindex @samp{--64} option, i386
57 @cindex @samp{--64} option, x86-64
59 Select the word size, either 32 bits or 64 bits. Selecting 32-bit
60 implies Intel i386 architecture, while 64-bit implies AMD x86-64
63 These options are only available with the ELF object file format, and
64 require that the necessary BFD support has been included (on a 32-bit
65 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
66 usage and use x86-64 as target platform).
69 By default, x86 GAS replaces multiple nop instructions used for
70 alignment within code sections with multi-byte nop instructions such
71 as leal 0(%esi,1),%esi. This switch disables the optimization.
73 @cindex @samp{--divide} option, i386
75 On SVR4-derived platforms, the character @samp{/} is treated as a comment
76 character, which means that it cannot be used in expressions. The
77 @samp{--divide} option turns @samp{/} into a normal character. This does
78 not disable @samp{/} at the beginning of a line starting a comment, or
79 affect using @samp{#} for starting a comment.
81 @cindex @samp{-march=} option, i386
82 @cindex @samp{-march=} option, x86-64
83 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
84 This option specifies the target processor. The assembler will
85 issue an error message if an attempt is made to assemble an instruction
86 which will not execute on the target processor. The following
87 processor names are recognized:
115 In addition to the basic instruction set, the assembler can be told to
116 accept various extension mnemonics. For example,
117 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
118 @var{vmx}. The following extensions are currently supported:
154 Note that rather than extending a basic instruction set, the extension
155 mnemonics starting with @code{no} revoke the respective functionality.
157 When the @code{.arch} directive is used with @option{-march}, the
158 @code{.arch} directive will take precedent.
160 @cindex @samp{-mtune=} option, i386
161 @cindex @samp{-mtune=} option, x86-64
162 @item -mtune=@var{CPU}
163 This option specifies a processor to optimize for. When used in
164 conjunction with the @option{-march} option, only instructions
165 of the processor specified by the @option{-march} option will be
168 Valid @var{CPU} values are identical to the processor list of
169 @option{-march=@var{CPU}}.
171 @cindex @samp{-msse2avx} option, i386
172 @cindex @samp{-msse2avx} option, x86-64
174 This option specifies that the assembler should encode SSE instructions
177 @cindex @samp{-msse-check=} option, i386
178 @cindex @samp{-msse-check=} option, x86-64
179 @item -msse-check=@var{none}
180 @item -msse-check=@var{warning}
181 @item -msse-check=@var{error}
182 These options control if the assembler should check SSE intructions.
183 @option{-msse-check=@var{none}} will make the assembler not to check SSE
184 instructions, which is the default. @option{-msse-check=@var{warning}}
185 will make the assembler issue a warning for any SSE intruction.
186 @option{-msse-check=@var{error}} will make the assembler issue an error
187 for any SSE intruction.
189 @cindex @samp{-mmnemonic=} option, i386
190 @cindex @samp{-mmnemonic=} option, x86-64
191 @item -mmnemonic=@var{att}
192 @item -mmnemonic=@var{intel}
193 This option specifies instruction mnemonic for matching instructions.
194 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
197 @cindex @samp{-msyntax=} option, i386
198 @cindex @samp{-msyntax=} option, x86-64
199 @item -msyntax=@var{att}
200 @item -msyntax=@var{intel}
201 This option specifies instruction syntax when processing instructions.
202 The @code{.att_syntax} and @code{.intel_syntax} directives will
205 @cindex @samp{-mnaked-reg} option, i386
206 @cindex @samp{-mnaked-reg} option, x86-64
208 This opetion specifies that registers don't require a @samp{%} prefix.
209 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
213 @node i386-Directives
214 @section x86 specific Directives
216 @cindex machine directives, x86
217 @cindex x86 machine directives
220 @cindex @code{lcomm} directive, COFF
221 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
222 Reserve @var{length} (an absolute expression) bytes for a local common
223 denoted by @var{symbol}. The section and value of @var{symbol} are
224 those of the new local common. The addresses are allocated in the bss
225 section, so that at run-time the bytes start off zeroed. Since
226 @var{symbol} is not declared global, it is normally not visible to
227 @code{@value{LD}}. The optional third parameter, @var{alignment},
228 specifies the desired alignment of the symbol in the bss section.
230 This directive is only available for COFF based x86 targets.
232 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
238 @section AT&T Syntax versus Intel Syntax
240 @cindex i386 intel_syntax pseudo op
241 @cindex intel_syntax pseudo op, i386
242 @cindex i386 att_syntax pseudo op
243 @cindex att_syntax pseudo op, i386
244 @cindex i386 syntax compatibility
245 @cindex syntax compatibility, i386
246 @cindex x86-64 intel_syntax pseudo op
247 @cindex intel_syntax pseudo op, x86-64
248 @cindex x86-64 att_syntax pseudo op
249 @cindex att_syntax pseudo op, x86-64
250 @cindex x86-64 syntax compatibility
251 @cindex syntax compatibility, x86-64
253 @code{@value{AS}} now supports assembly using Intel assembler syntax.
254 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
255 back to the usual AT&T mode for compatibility with the output of
256 @code{@value{GCC}}. Either of these directives may have an optional
257 argument, @code{prefix}, or @code{noprefix} specifying whether registers
258 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
259 different from Intel syntax. We mention these differences because
260 almost all 80386 documents use Intel syntax. Notable differences
261 between the two syntaxes are:
263 @cindex immediate operands, i386
264 @cindex i386 immediate operands
265 @cindex register operands, i386
266 @cindex i386 register operands
267 @cindex jump/call operands, i386
268 @cindex i386 jump/call operands
269 @cindex operand delimiters, i386
271 @cindex immediate operands, x86-64
272 @cindex x86-64 immediate operands
273 @cindex register operands, x86-64
274 @cindex x86-64 register operands
275 @cindex jump/call operands, x86-64
276 @cindex x86-64 jump/call operands
277 @cindex operand delimiters, x86-64
280 AT&T immediate operands are preceded by @samp{$}; Intel immediate
281 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
282 AT&T register operands are preceded by @samp{%}; Intel register operands
283 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
284 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
286 @cindex i386 source, destination operands
287 @cindex source, destination operands; i386
288 @cindex x86-64 source, destination operands
289 @cindex source, destination operands; x86-64
291 AT&T and Intel syntax use the opposite order for source and destination
292 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
293 @samp{source, dest} convention is maintained for compatibility with
294 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
295 instructions with 2 immediate operands, such as the @samp{enter}
296 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
298 @cindex mnemonic suffixes, i386
299 @cindex sizes operands, i386
300 @cindex i386 size suffixes
301 @cindex mnemonic suffixes, x86-64
302 @cindex sizes operands, x86-64
303 @cindex x86-64 size suffixes
305 In AT&T syntax the size of memory operands is determined from the last
306 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
307 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
308 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
309 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
310 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
311 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
314 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
315 instruction with the 64-bit displacement or immediate operand.
317 @cindex return instructions, i386
318 @cindex i386 jump, call, return
319 @cindex return instructions, x86-64
320 @cindex x86-64 jump, call, return
322 Immediate form long jumps and calls are
323 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
325 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
327 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
328 @samp{ret far @var{stack-adjust}}.
330 @cindex sections, i386
331 @cindex i386 sections
332 @cindex sections, x86-64
333 @cindex x86-64 sections
335 The AT&T assembler does not provide support for multiple section
336 programs. Unix style systems expect all programs to be single sections.
340 @section Instruction Naming
342 @cindex i386 instruction naming
343 @cindex instruction naming, i386
344 @cindex x86-64 instruction naming
345 @cindex instruction naming, x86-64
347 Instruction mnemonics are suffixed with one character modifiers which
348 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
349 and @samp{q} specify byte, word, long and quadruple word operands. If
350 no suffix is specified by an instruction then @code{@value{AS}} tries to
351 fill in the missing suffix based on the destination register operand
352 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
353 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
354 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
355 assembler which assumes that a missing mnemonic suffix implies long
356 operand size. (This incompatibility does not affect compiler output
357 since compilers always explicitly specify the mnemonic suffix.)
359 Almost all instructions have the same names in AT&T and Intel format.
360 There are a few exceptions. The sign extend and zero extend
361 instructions need two sizes to specify them. They need a size to
362 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
363 is accomplished by using two instruction mnemonic suffixes in AT&T
364 syntax. Base names for sign extend and zero extend are
365 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
366 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
367 are tacked on to this base name, the @emph{from} suffix before the
368 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
369 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
370 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
371 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
372 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
375 @cindex encoding options, i386
376 @cindex encoding options, x86-64
378 Different encoding options can be specified via optional mnemonic
379 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
380 moving from one register to another.
382 @cindex conversion instructions, i386
383 @cindex i386 conversion instructions
384 @cindex conversion instructions, x86-64
385 @cindex x86-64 conversion instructions
386 The Intel-syntax conversion instructions
390 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
393 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
396 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
399 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
402 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
406 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
407 @samp{%rdx:%rax} (x86-64 only),
411 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
412 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
415 @cindex jump instructions, i386
416 @cindex call instructions, i386
417 @cindex jump instructions, x86-64
418 @cindex call instructions, x86-64
419 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
420 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
423 @section AT&T Mnemonic versus Intel Mnemonic
425 @cindex i386 mnemonic compatibility
426 @cindex mnemonic compatibility, i386
428 @code{@value{AS}} supports assembly using Intel mnemonic.
429 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
430 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
431 syntax for compatibility with the output of @code{@value{GCC}}.
432 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
433 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
434 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
435 assembler with different mnemonics from those in Intel IA32 specification.
436 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
439 @section Register Naming
441 @cindex i386 registers
442 @cindex registers, i386
443 @cindex x86-64 registers
444 @cindex registers, x86-64
445 Register operands are always prefixed with @samp{%}. The 80386 registers
450 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
451 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
452 frame pointer), and @samp{%esp} (the stack pointer).
455 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
456 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
459 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
460 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
461 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
462 @samp{%cx}, and @samp{%dx})
465 the 6 section registers @samp{%cs} (code section), @samp{%ds}
466 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
470 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
474 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
475 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
478 the 2 test registers @samp{%tr6} and @samp{%tr7}.
481 the 8 floating point register stack @samp{%st} or equivalently
482 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
483 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
484 These registers are overloaded by 8 MMX registers @samp{%mm0},
485 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
486 @samp{%mm6} and @samp{%mm7}.
489 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
490 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
493 The AMD x86-64 architecture extends the register set by:
497 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
498 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
499 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
503 the 8 extended registers @samp{%r8}--@samp{%r15}.
506 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
509 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
512 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
515 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
518 the 8 debug registers: @samp{%db8}--@samp{%db15}.
521 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
525 @section Instruction Prefixes
527 @cindex i386 instruction prefixes
528 @cindex instruction prefixes, i386
529 @cindex prefixes, i386
530 Instruction prefixes are used to modify the following instruction. They
531 are used to repeat string instructions, to provide section overrides, to
532 perform bus lock operations, and to change operand and address sizes.
533 (Most instructions that normally operate on 32-bit operands will use
534 16-bit operands if the instruction has an ``operand size'' prefix.)
535 Instruction prefixes are best written on the same line as the instruction
536 they act upon. For example, the @samp{scas} (scan string) instruction is
540 repne scas %es:(%edi),%al
543 You may also place prefixes on the lines immediately preceding the
544 instruction, but this circumvents checks that @code{@value{AS}} does
545 with prefixes, and will not work with all prefixes.
547 Here is a list of instruction prefixes:
549 @cindex section override prefixes, i386
552 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
553 @samp{fs}, @samp{gs}. These are automatically added by specifying
554 using the @var{section}:@var{memory-operand} form for memory references.
556 @cindex size prefixes, i386
558 Operand/Address size prefixes @samp{data16} and @samp{addr16}
559 change 32-bit operands/addresses into 16-bit operands/addresses,
560 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
561 @code{.code16} section) into 32-bit operands/addresses. These prefixes
562 @emph{must} appear on the same line of code as the instruction they
563 modify. For example, in a 16-bit @code{.code16} section, you might
570 @cindex bus lock prefixes, i386
571 @cindex inhibiting interrupts, i386
573 The bus lock prefix @samp{lock} inhibits interrupts during execution of
574 the instruction it precedes. (This is only valid with certain
575 instructions; see a 80386 manual for details).
577 @cindex coprocessor wait, i386
579 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
580 complete the current instruction. This should never be needed for the
581 80386/80387 combination.
583 @cindex repeat prefixes, i386
585 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
586 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
587 times if the current address size is 16-bits).
588 @cindex REX prefixes, i386
590 The @samp{rex} family of prefixes is used by x86-64 to encode
591 extensions to i386 instruction set. The @samp{rex} prefix has four
592 bits --- an operand size overwrite (@code{64}) used to change operand size
593 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
596 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
597 instruction emits @samp{rex} prefix with all the bits set. By omitting
598 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
599 prefixes as well. Normally, there is no need to write the prefixes
600 explicitly, since gas will automatically generate them based on the
601 instruction operands.
605 @section Memory References
607 @cindex i386 memory references
608 @cindex memory references, i386
609 @cindex x86-64 memory references
610 @cindex memory references, x86-64
611 An Intel syntax indirect memory reference of the form
614 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
618 is translated into the AT&T syntax
621 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
625 where @var{base} and @var{index} are the optional 32-bit base and
626 index registers, @var{disp} is the optional displacement, and
627 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
628 to calculate the address of the operand. If no @var{scale} is
629 specified, @var{scale} is taken to be 1. @var{section} specifies the
630 optional section register for the memory operand, and may override the
631 default section register (see a 80386 manual for section register
632 defaults). Note that section overrides in AT&T syntax @emph{must}
633 be preceded by a @samp{%}. If you specify a section override which
634 coincides with the default section register, @code{@value{AS}} does @emph{not}
635 output any section register override prefixes to assemble the given
636 instruction. Thus, section overrides can be specified to emphasize which
637 section register is used for a given memory operand.
639 Here are some examples of Intel and AT&T style memory references:
642 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
643 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
644 missing, and the default section is used (@samp{%ss} for addressing with
645 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
647 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
648 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
649 @samp{foo}. All other fields are missing. The section register here
650 defaults to @samp{%ds}.
652 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
653 This uses the value pointed to by @samp{foo} as a memory operand.
654 Note that @var{base} and @var{index} are both missing, but there is only
655 @emph{one} @samp{,}. This is a syntactic exception.
657 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
658 This selects the contents of the variable @samp{foo} with section
659 register @var{section} being @samp{%gs}.
662 Absolute (as opposed to PC relative) call and jump operands must be
663 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
664 always chooses PC relative addressing for jump/call labels.
666 Any instruction that has a memory operand, but no register operand,
667 @emph{must} specify its size (byte, word, long, or quadruple) with an
668 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
671 The x86-64 architecture adds an RIP (instruction pointer relative)
672 addressing. This addressing mode is specified by using @samp{rip} as a
673 base register. Only constant offsets are valid. For example:
676 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
677 Points to the address 1234 bytes past the end of the current
680 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
681 Points to the @code{symbol} in RIP relative way, this is shorter than
682 the default absolute addressing.
685 Other addressing modes remain unchanged in x86-64 architecture, except
686 registers used are 64-bit instead of 32-bit.
689 @section Handling of Jump Instructions
691 @cindex jump optimization, i386
692 @cindex i386 jump optimization
693 @cindex jump optimization, x86-64
694 @cindex x86-64 jump optimization
695 Jump instructions are always optimized to use the smallest possible
696 displacements. This is accomplished by using byte (8-bit) displacement
697 jumps whenever the target is sufficiently close. If a byte displacement
698 is insufficient a long displacement is used. We do not support
699 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
700 instruction with the @samp{data16} instruction prefix), since the 80386
701 insists upon masking @samp{%eip} to 16 bits after the word displacement
702 is added. (See also @pxref{i386-Arch})
704 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
705 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
706 displacements, so that if you use these instructions (@code{@value{GCC}} does
707 not use them) you may get an error message (and incorrect code). The AT&T
708 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
719 @section Floating Point
721 @cindex i386 floating point
722 @cindex floating point, i386
723 @cindex x86-64 floating point
724 @cindex floating point, x86-64
725 All 80387 floating point types except packed BCD are supported.
726 (BCD support may be added without much difficulty). These data
727 types are 16-, 32-, and 64- bit integers, and single (32-bit),
728 double (64-bit), and extended (80-bit) precision floating point.
729 Each supported type has an instruction mnemonic suffix and a constructor
730 associated with it. Instruction mnemonic suffixes specify the operand's
731 data type. Constructors build these data types into memory.
733 @cindex @code{float} directive, i386
734 @cindex @code{single} directive, i386
735 @cindex @code{double} directive, i386
736 @cindex @code{tfloat} directive, i386
737 @cindex @code{float} directive, x86-64
738 @cindex @code{single} directive, x86-64
739 @cindex @code{double} directive, x86-64
740 @cindex @code{tfloat} directive, x86-64
743 Floating point constructors are @samp{.float} or @samp{.single},
744 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
745 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
746 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
747 only supports this format via the @samp{fldt} (load 80-bit real to stack
748 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
750 @cindex @code{word} directive, i386
751 @cindex @code{long} directive, i386
752 @cindex @code{int} directive, i386
753 @cindex @code{quad} directive, i386
754 @cindex @code{word} directive, x86-64
755 @cindex @code{long} directive, x86-64
756 @cindex @code{int} directive, x86-64
757 @cindex @code{quad} directive, x86-64
759 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
760 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
761 corresponding instruction mnemonic suffixes are @samp{s} (single),
762 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
763 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
764 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
768 Register to register operations should not use instruction mnemonic suffixes.
769 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
770 wrote @samp{fst %st, %st(1)}, since all register to register operations
771 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
772 which converts @samp{%st} from 80-bit to 64-bit floating point format,
773 then stores the result in the 4 byte location @samp{mem})
776 @section Intel's MMX and AMD's 3DNow! SIMD Operations
782 @cindex 3DNow!, x86-64
785 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
786 instructions for integer data), available on Intel's Pentium MMX
787 processors and Pentium II processors, AMD's K6 and K6-2 processors,
788 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
789 instruction set (SIMD instructions for 32-bit floating point data)
790 available on AMD's K6-2 processor and possibly others in the future.
792 Currently, @code{@value{AS}} does not support Intel's floating point
795 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
796 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
797 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
798 floating point values. The MMX registers cannot be used at the same time
799 as the floating point stack.
801 See Intel and AMD documentation, keeping in mind that the operand order in
802 instructions is reversed from the Intel syntax.
805 @section AMD's Lightweight Profiling Instructions
810 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
811 instruction set, available on AMD's Family 15h (Orochi) processors.
813 LWP enables applications to collect and manage performance data, and
814 react to performance events. The collection of performance data
815 requires no context switches. LWP runs in the context of a thread and
816 so several counters can be used independently across multiple threads.
817 LWP can be used in both 64-bit and legacy 32-bit modes.
819 For detailed information on the LWP instruction set, see the
820 @cite{AMD Lightweight Profiling Specification} available at
821 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
824 @section Writing 16-bit Code
826 @cindex i386 16-bit code
827 @cindex 16-bit code, i386
828 @cindex real-mode code, i386
829 @cindex @code{code16gcc} directive, i386
830 @cindex @code{code16} directive, i386
831 @cindex @code{code32} directive, i386
832 @cindex @code{code64} directive, i386
833 @cindex @code{code64} directive, x86-64
834 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
835 or 64-bit x86-64 code depending on the default configuration,
836 it also supports writing code to run in real mode or in 16-bit protected
837 mode code segments. To do this, put a @samp{.code16} or
838 @samp{.code16gcc} directive before the assembly language instructions to
839 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
840 32-bit code with the @samp{.code32} directive or 64-bit code with the
841 @samp{.code64} directive.
843 @samp{.code16gcc} provides experimental support for generating 16-bit
844 code from gcc, and differs from @samp{.code16} in that @samp{call},
845 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
846 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
847 default to 32-bit size. This is so that the stack pointer is
848 manipulated in the same way over function calls, allowing access to
849 function parameters at the same stack offsets as in 32-bit mode.
850 @samp{.code16gcc} also automatically adds address size prefixes where
851 necessary to use the 32-bit addressing modes that gcc generates.
853 The code which @code{@value{AS}} generates in 16-bit mode will not
854 necessarily run on a 16-bit pre-80386 processor. To write code that
855 runs on such a processor, you must refrain from using @emph{any} 32-bit
856 constructs which require @code{@value{AS}} to output address or operand
859 Note that writing 16-bit code instructions by explicitly specifying a
860 prefix or an instruction mnemonic suffix within a 32-bit code section
861 generates different machine instructions than those generated for a
862 16-bit code segment. In a 32-bit code section, the following code
863 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
864 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
870 The same code in a 16-bit code section would generate the machine
871 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
872 is correct since the processor default operand size is assumed to be 16
873 bits in a 16-bit code section.
876 @section AT&T Syntax bugs
878 The UnixWare assembler, and probably other AT&T derived ix86 Unix
879 assemblers, generate floating point instructions with reversed source
880 and destination registers in certain cases. Unfortunately, gcc and
881 possibly many other programs use this reversed syntax, so we're stuck
890 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
891 than the expected @samp{%st(3) - %st}. This happens with all the
892 non-commutative arithmetic floating point operations with two register
893 operands where the source register is @samp{%st} and the destination
894 register is @samp{%st(i)}.
897 @section Specifying CPU Architecture
899 @cindex arch directive, i386
900 @cindex i386 arch directive
901 @cindex arch directive, x86-64
902 @cindex x86-64 arch directive
904 @code{@value{AS}} may be told to assemble for a particular CPU
905 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
906 directive enables a warning when gas detects an instruction that is not
907 supported on the CPU specified. The choices for @var{cpu_type} are:
909 @multitable @columnfractions .20 .20 .20 .20
910 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
911 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
912 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
913 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
914 @item @samp{corei7} @tab @samp{l1om}
915 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
916 @item @samp{amdfam10}
917 @item @samp{generic32} @tab @samp{generic64}
918 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
919 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
920 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
921 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe}
922 @item @samp{.ept} @tab @samp{.clflush}
923 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
924 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
926 @item @samp{.padlock}
929 Apart from the warning, there are only two other effects on
930 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
931 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
932 will automatically use a two byte opcode sequence. The larger three
933 byte opcode sequence is used on the 486 (and when no architecture is
934 specified) because it executes faster on the 486. Note that you can
935 explicitly request the two byte opcode by writing @samp{sarl %eax}.
936 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
937 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
938 conditional jumps will be promoted when necessary to a two instruction
939 sequence consisting of a conditional jump of the opposite sense around
940 an unconditional jump to the target.
942 Following the CPU architecture (but not a sub-architecture, which are those
943 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
944 control automatic promotion of conditional jumps. @samp{jumps} is the
945 default, and enables jump promotion; All external jumps will be of the long
946 variety, and file-local jumps will be promoted as necessary.
947 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
948 byte offset jumps, and warns about file-local conditional jumps that
949 @code{@value{AS}} promotes.
950 Unconditional jumps are treated as for @samp{jumps}.
961 @cindex i386 @code{mul}, @code{imul} instructions
962 @cindex @code{mul} instruction, i386
963 @cindex @code{imul} instruction, i386
964 @cindex @code{mul} instruction, x86-64
965 @cindex @code{imul} instruction, x86-64
966 There is some trickery concerning the @samp{mul} and @samp{imul}
967 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
968 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
969 for @samp{imul}) can be output only in the one operand form. Thus,
970 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
971 the expanding multiply would clobber the @samp{%edx} register, and this
972 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
973 64-bit product in @samp{%edx:%eax}.
975 We have added a two operand form of @samp{imul} when the first operand
976 is an immediate mode expression and the second operand is a register.
977 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
978 example, can be done with @samp{imul $69, %eax} rather than @samp{imul