gas/doc/c-i860.texi

   1 @c Copyright (C) 2000 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4 @ifset GENERIC
   5 @page
   6 @node i860-Dependent
   7 @chapter Intel i860 Dependent Features
   8 @end ifset
   9 @ifclear GENERIC
  10 @node Machine Dependencies
  11 @chapter Intel i860 Dependent Features
  12 @end ifclear
  13
  14 @ignore
  15 @c FIXME: This is basically a stub for i860. There is tons more information
  16 that I will add later (jle@cygnus.com). The assembler is still being
  17 written. The i860 assembler that existed previously was never finished
  18 and doesn't even build. Further, its not BFD_ASSEMBLER and it doesn't
  19 do ELF (it doesn't do anything, but you get the point).
  20 @end ignore
  21
  22 @cindex i860 support
  23 @menu
  24 * Options-i860::                i860 Command-line Options
  25 * Directives-i860::             i860 Machine Directives
  26 * Opcodes for i860::            i860 Opcodes
  27 @end menu
  28
  29 @node Options-i860
  30
  31 @section i860 Command-line Options
  32 @subsection SVR4 compatibility options
  33 @table @code
  34 @item -V
  35 Print assembler version.
  36 @item -Qy
  37 Ignored.
  38 @item -Qn
  39 Ignored.
  40 @end table
  41 @subsection Other options
  42 @table @code
  43 @item -EL
  44 Select little endian output (this is the default).
  45 @item -EB
  46 Select big endian output. Note that the i860 always reads instructions
  47 as little endian data, so this option only effects data and not
  48 instructions.
  49 @end table
  50
  51 @node Directives-i860
  52 @section i860 Machine Directives
  53
  54 @cindex machine directives, i860
  55 @cindex i860 machine directives
  56
  57 @table @code
  58 @cindex @code{dual} directive, i860
  59 @item .dual
  60 Enter dual instruction mode. While this directive is supported, the
  61 preferred way to use dual instruction mode is to explicitly code
  62 the dual bit with the @code{d.} prefix.
  63 @end table
  64
  65 @table @code
  66 @cindex @code{enddual} directive, i860
  67 @item .enddual
  68 Exit dual instruction mode. While this directive is supported, the
  69 preferred way to use dual instruction mode is to explicitly code
  70 the dual bit with the @code{d.} prefix.
  71 @end table
  72
  73 @table @code
  74 @cindex @code{atmp} directive, i860
  75 @item .atmp
  76 Change the temporary register used when expanding pseudo operations. The
  77 default register is @code{r31}.
  78 @end table
  79
  80 @node Opcodes for i860
  81 @section i860 Opcodes
  82
  83 @cindex opcodes, i860
  84 @cindex i860 opcodes
  85 All of the Intel i860 machine instructions are supported.
  86
  87 Some opcodes are processed beyond simply emitting a single corresponding
  88 instruction. For example, @samp{mov} and other instructions with larg
  89 displacements may be expanded into 2 or 3 instructions (FIXME: add details).
  90