gas/doc/c-mips.texi

   1 @c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4 @ifset GENERIC
   5 @page
   6 @node MIPS-Dependent
   7 @chapter MIPS Dependent Features
   8 @end ifset
   9 @ifclear GENERIC
  10 @node Machine Dependencies
  11 @chapter MIPS Dependent Features
  12 @end ifclear
  13
  14 @cindex MIPS processor
  15 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
  16 different @sc{mips} processors, and MIPS ISA levels I through IV.  For
  17 information about the @sc{mips} instruction set, see @cite{MIPS RISC
  18 Architecture}, by Kane and Heindrich (Prentice-Hall).  For an overview
  19 of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
  20 Programming'' in the same work.
  21
  22 @menu
  23 * MIPS Opts::   Assembler options
  24 * MIPS Object:: ECOFF object code
  25 * MIPS Stabs::  Directives for debugging information
  26 * MIPS ISA::    Directives to override the ISA level
  27 @end menu
  28
  29 @node MIPS Opts
  30 @section Assembler options
  31
  32 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
  33 special options:
  34
  35 @table @code
  36 @cindex @code{-G} option (MIPS)
  37 @item -G @var{num}
  38 This option sets the largest size of an object that can be referenced
  39 implicitly with the @code{gp} register.  It is only accepted for targets
  40 that use @sc{ecoff} format.  The default value is 8.
  41
  42 @cindex @code{-EB} option (MIPS)
  43 @cindex @code{-EL} option (MIPS)
  44 @cindex MIPS big-endian output
  45 @cindex MIPS little-endian output
  46 @cindex big-endian output, MIPS
  47 @cindex little-endian output, MIPS
  48 @item -EB
  49 @itemx -EL
  50 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
  51 little-endian output at run time (unlike the other @sc{gnu} development
  52 tools, which must be configured for one or the other).  Use @samp{-EB}
  53 to select big-endian output, and @samp{-EL} for little-endian.
  54
  55 @cindex MIPS architecture options
  56 @item -mips1
  57 @itemx -mips2
  58 @itemx -mips3
  59 @itemx -mips4
  60 Generate code for a particular MIPS Instruction Set Architecture level.
  61 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
  62 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
  63 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
  64 @sc{r10000} processors.  You can also switch instruction sets during the
  65 assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
  66
  67 @item -mips16
  68 @itemx -no-mips16
  69 Generate code for the MIPS 16 processor.  This is equivalent to putting
  70 @samp{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
  71 turns off this option.
  72
  73 @item -m4650
  74 @itemx -no-m4650
  75 Generate code for the MIPS @sc{r4650} chip.  This tells the assembler to accept
  76 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
  77 instructions around accesses to the @samp{HI} and @samp{LO} registers.
  78 @samp{-no-m4650} turns off this option.
  79
  80 @item -m4010
  81 @itemx -no-m4010
  82 Generate code for the LSI @sc{r4010} chip.  This tells the assembler to
  83 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
  84 etc.), and to not schedule @samp{nop} instructions around accesses to
  85 the @samp{HI} and @samp{LO} registers.  @samp{-no-m4010} turns off this
  86 option.
  87
  88 @item -mcpu=@var{CPU}
  89 Generate code for a particular MIPS cpu.  This has little effect on the
  90 assembler, but it is passed by @code{@value{GCC}}.
  91
  92 @cindex @code{-nocpp} ignored (MIPS)
  93 @item -nocpp
  94 This option is ignored.  It is accepted for command-line compatibility with
  95 other assemblers, which use it to turn off C style preprocessing.  With
  96 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
  97 @sc{gnu} assembler itself never runs the C preprocessor.
  98
  99 @item --trap
 100 @itemx --no-break
 101 @c FIXME!  (1) reflect these options (next item too) in option summaries;
 102 @c         (2) stop teasing, say _which_ instructions expanded _how_.
 103 @code{@value{AS}} automatically macro expands certain division and
 104 multiplication instructions to check for overflow and division by zero.  This
 105 option causes @code{@value{AS}} to generate code to take a trap exception
 106 rather than a break exception when an error is detected.  The trap instructions
 107 are only supported at Instruction Set Architecture level 2 and higher.
 108
 109 @item --break
 110 @itemx --no-trap
 111 Generate code to take a break exception rather than a trap exception when an
 112 error is detected.  This is the default.
 113 @end table
 114
 115 @node MIPS Object
 116 @section MIPS ECOFF object code
 117
 118 @cindex ECOFF sections
 119 @cindex MIPS ECOFF sections
 120 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
 121 besides the usual @code{.text}, @code{.data} and @code{.bss}.  The
 122 additional sections are @code{.rdata}, used for read-only data,
 123 @code{.sdata}, used for small data, and @code{.sbss}, used for small
 124 common objects.
 125
 126 @cindex small objects, MIPS ECOFF
 127 @cindex @code{gp} register, MIPS
 128 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
 129 register to form the address of a ``small object''.  Any object in the
 130 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
 131 For external objects, or for objects in the @code{.bss} section, you can use
 132 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
 133 @code{$gp}; the default value is 8, meaning that a reference to any object
 134 eight bytes or smaller uses @code{$gp}.  Passing @samp{-G 0} to
 135 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
 136 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
 137 or @code{sbss} in any case).  The size of an object in the @code{.bss} section
 138 is set by the @code{.comm} or @code{.lcomm} directive that defines it.  The
 139 size of an external object may be set with the @code{.extern} directive.  For
 140 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
 141 in length, whie leaving @code{sym} otherwise undefined.
 142
 143 Using small @sc{ecoff} objects requires linker support, and assumes that the
 144 @code{$gp} register is correctly initialized (normally done automatically by
 145 the startup code).  @sc{mips} @sc{ecoff} assembly code must not modify the
 146 @code{$gp} register.
 147
 148 @node MIPS Stabs
 149 @section Directives for debugging information
 150
 151 @cindex MIPS debugging directives
 152 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
 153 generating debugging information which are not support by traditional @sc{mips}
 154 assemblers.  These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
 155 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
 156 @code{.stabd}, @code{.stabn}, and @code{.stabs}.  The debugging information
 157 generated by the three @code{.stab} directives can only be read by @sc{gdb},
 158 not by traditional @sc{mips} debuggers (this enhancement is required to fully
 159 support C++ debugging).  These directives are primarily used by compilers, not
 160 assembly language programmers!
 161
 162 @node MIPS ISA
 163 @section Directives to override the ISA level
 164
 165 @cindex MIPS ISA override
 166 @kindex @code{.set mips@var{n}}
 167 @sc{gnu} @code{@value{AS}} supports an additional directive to change
 168 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
 169 mips@var{n}}.  @var{n} should be a number from 0 to 4.  A value from 1
 170 to 4 makes the assembler accept instructions for the corresponding
 171 @sc{isa} level, from that point on in the assembly.  @code{.set
 172 mips@var{n}} affects not only which instructions are permitted, but also
 173 how certain macros are expanded.  @code{.set mips0} restores the
 174 @sc{isa} level to its original level: either the level you selected with
 175 command line options, or the default for your configuration.  You can
 176 use this feature to permit specific @sc{r4000} instructions while
 177 assembling in 32 bit mode.  Use this directive with care!
 178
 179 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
 180 in which it will assemble instructions for the MIPS 16 processor.  Use
 181 @samp{.set nomips16} to return to normal 32 bit mode.
 182
 183 Traditional @sc{mips} assemblers do not support this directive.