1 @c Copyright (C) 1991-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
16 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
17 and MIPS64. For information about the MIPS instruction set, see
18 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
19 For an overview of MIPS assembly conventions, see ``Appendix D:
20 Assembly Language Programming'' in the same work.
23 * MIPS Options:: Assembler options
24 * MIPS Macros:: High-level assembly macros
25 * MIPS Symbol Sizes:: Directives to override the size of symbols
26 * MIPS Small Data:: Controlling the use of small data accesses
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS assembly options:: Directives to control code generation
29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
30 * MIPS insn:: Directive to mark data as an instruction
31 * MIPS FP ABIs:: Marking which FP ABI is in use
32 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
33 * MIPS Option Stack:: Directives to save and restore options
34 * MIPS ASE Instruction Generation Overrides:: Directives to control
35 generation of MIPS ASE instructions
36 * MIPS Floating-Point:: Directives to override floating-point options
37 * MIPS Syntax:: MIPS specific syntactical considerations
41 @section Assembler options
43 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
47 @cindex @code{-G} option (MIPS)
49 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
50 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any MIPS configuration of @code{@value{AS}} can select big-endian or
61 little-endian output at run time (unlike the other @sc{gnu} development
62 tools, which must be configured for one or the other). Use @samp{-EB}
63 to select big-endian output, and @samp{-EL} for little-endian.
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
68 Generate SVR4-style PIC. This option tells the assembler to generate
69 SVR4-style position-independent macro expansions. It also tells the
70 assembler to mark the output file as PIC.
73 @cindex @option{-mvxworks-pic} option, MIPS
74 Generate VxWorks PIC. This option tells the assembler to generate
75 VxWorks-style position-independent macro expansions.
77 @cindex MIPS architecture options
93 Generate code for a particular MIPS Instruction Set Architecture level.
94 @samp{-mips1} corresponds to the R2000 and R3000 processors,
95 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
96 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
97 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3},
98 @samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2},
99 @samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to
100 generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32
101 Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64
102 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors,
103 respectively. You can also switch instruction sets during the assembly;
104 see @ref{MIPS ISA, Directives to override the ISA level}.
108 Some macros have different expansions for 32-bit and 64-bit registers.
109 The register sizes are normally inferred from the ISA and ABI, but these
110 flags force a certain group of registers to be treated as 32 bits wide at
111 all times. @samp{-mgp32} controls the size of general-purpose registers
112 and @samp{-mfp32} controls the size of floating-point registers.
114 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
115 of registers to be changed for parts of an object. The default value is
116 restored by @code{.set gp=default} and @code{.set fp=default}.
118 On some MIPS variants there is a 32-bit mode flag; when this flag is
119 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
120 save the 32-bit registers on a context switch, so it is essential never
121 to use the 64-bit registers.
125 Assume that 64-bit registers are available. This is provided in the
126 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
128 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
129 of registers to be changed for parts of an object. The default value is
130 restored by @code{.set gp=default} and @code{.set fp=default}.
133 Make no assumptions about whether 32-bit or 64-bit floating-point
134 registers are available. This is provided to support having modules
135 compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can
136 only be used with MIPS II and above.
138 The @code{.set fp=xx} directive allows a part of an object to be marked
139 as not making assumptions about 32-bit or 64-bit FP registers. The
140 default value is restored by @code{.set fp=default}.
143 @itemx -mno-odd-spreg
144 Enable use of floating-point operations on odd-numbered single-precision
145 registers when supported by the ISA. @samp{-mfpxx} implies
146 @samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg}
150 Generate code for the MIPS 16 processor. This is equivalent to putting
151 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
152 turns off this option.
155 @itemx -mno-micromips
156 Generate code for the microMIPS processor. This is equivalent to putting
157 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
158 turns off this option. This is equivalent to putting @code{.set nomicromips}
159 at the start of the assembly file.
162 @itemx -mno-smartmips
163 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
164 provides a number of new instructions which target smartcard and
165 cryptographic applications. This is equivalent to putting
166 @code{.set smartmips} at the start of the assembly file.
167 @samp{-mno-smartmips} turns off this option.
171 Generate code for the MIPS-3D Application Specific Extension.
172 This tells the assembler to accept MIPS-3D instructions.
173 @samp{-no-mips3d} turns off this option.
177 Generate code for the MDMX Application Specific Extension.
178 This tells the assembler to accept MDMX instructions.
179 @samp{-no-mdmx} turns off this option.
183 Generate code for the DSP Release 1 Application Specific Extension.
184 This tells the assembler to accept DSP Release 1 instructions.
185 @samp{-mno-dsp} turns off this option.
189 Generate code for the DSP Release 2 Application Specific Extension.
190 This option implies @samp{-mdsp}.
191 This tells the assembler to accept DSP Release 2 instructions.
192 @samp{-mno-dspr2} turns off this option.
196 Generate code for the DSP Release 3 Application Specific Extension.
197 This option implies @samp{-mdsp} and @samp{-mdspr2}.
198 This tells the assembler to accept DSP Release 3 instructions.
199 @samp{-mno-dspr3} turns off this option.
203 Generate code for the MT Application Specific Extension.
204 This tells the assembler to accept MT instructions.
205 @samp{-mno-mt} turns off this option.
209 Generate code for the MCU Application Specific Extension.
210 This tells the assembler to accept MCU instructions.
211 @samp{-mno-mcu} turns off this option.
215 Generate code for the MIPS SIMD Architecture Extension.
216 This tells the assembler to accept MSA instructions.
217 @samp{-mno-msa} turns off this option.
221 Generate code for the MIPS eXtended Physical Address (XPA) Extension.
222 This tells the assembler to accept XPA instructions.
223 @samp{-mno-xpa} turns off this option.
227 Generate code for the Virtualization Application Specific Extension.
228 This tells the assembler to accept Virtualization instructions.
229 @samp{-mno-virt} turns off this option.
233 Only use 32-bit instruction encodings when generating code for the
234 microMIPS processor. This option inhibits the use of any 16-bit
235 instructions. This is equivalent to putting @code{.set insn32} at
236 the start of the assembly file. @samp{-mno-insn32} turns off this
237 option. This is equivalent to putting @code{.set noinsn32} at the
238 start of the assembly file. By default @samp{-mno-insn32} is
239 selected, allowing all instructions to be used.
243 Cause nops to be inserted if the read of the destination register
244 of an mfhi or mflo instruction occurs in the following two instructions.
247 @itemx -mno-fix-rm7000
248 Cause nops to be inserted if a dmult or dmultu instruction is
249 followed by a load instruction.
251 @item -mfix-loongson2f-jump
252 @itemx -mno-fix-loongson2f-jump
253 Eliminate instruction fetch from outside 256M region to work around the
254 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
255 the kernel may crash. The issue has been solved in latest processor
256 batches, but this fix has no side effect to them.
258 @item -mfix-loongson2f-nop
259 @itemx -mno-fix-loongson2f-nop
260 Replace nops by @code{or at,at,zero} to work around the Loongson2F
261 @samp{nop} errata. Without it, under extreme cases, the CPU might
262 deadlock. The issue has been solved in later Loongson2F batches, but
263 this fix has no side effect to them.
266 @itemx -mno-fix-vr4120
267 Insert nops to work around certain VR4120 errata. This option is
268 intended to be used on GCC-generated code: it is not designed to catch
269 all problems in hand-written assembler code.
272 @itemx -mno-fix-vr4130
273 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
277 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
280 @itemx -mno-fix-cn63xxp1
281 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
282 certain CN63XXP1 errata.
286 Generate code for the LSI R4010 chip. This tells the assembler to
287 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
288 etc.), and to not schedule @samp{nop} instructions around accesses to
289 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
294 Generate code for the MIPS R4650 chip. This tells the assembler to accept
295 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
296 instructions around accesses to the @samp{HI} and @samp{LO} registers.
297 @samp{-no-m4650} turns off this option.
303 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
304 R@var{nnnn} chip. This tells the assembler to accept instructions
305 specific to that chip, and to schedule for that chip's hazards.
307 @item -march=@var{cpu}
308 Generate code for a particular MIPS CPU. It is exactly equivalent to
309 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
310 understood. Valid @var{cpu} value are:
402 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
403 accepted as synonyms for @samp{@var{n}f1_1}. These values are
406 @item -mtune=@var{cpu}
407 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
408 identical to @samp{-march=@var{cpu}}.
410 @item -mabi=@var{abi}
411 Record which ABI the source code uses. The recognized arguments
412 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
418 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
419 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
421 @cindex @code{-nocpp} ignored (MIPS)
423 This option is ignored. It is accepted for command-line compatibility with
424 other assemblers, which use it to turn off C style preprocessing. With
425 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
426 @sc{gnu} assembler itself never runs the C preprocessor.
430 Disable or enable floating-point instructions. Note that by default
431 floating-point instructions are always allowed even with CPU targets
432 that don't have support for these instructions.
435 @itemx -mdouble-float
436 Disable or enable double-precision floating-point operations. Note
437 that by default double-precision floating-point operations are always
438 allowed even with CPU targets that don't have support for these
441 @item --construct-floats
442 @itemx --no-construct-floats
443 The @code{--no-construct-floats} option disables the construction of
444 double width floating point constants by loading the two halves of the
445 value into the two single width floating point registers that make up
446 the double width register. This feature is useful if the processor
447 support the FR bit in its status register, and this bit is known (by
448 the programmer) to be set. This bit prevents the aliasing of the double
449 width register by the single width registers.
451 By default @code{--construct-floats} is selected, allowing construction
452 of these floating point constants.
455 @itemx --no-relax-branch
456 The @samp{--relax-branch} option enables the relaxation of out-of-range
457 branches. Any branches whose target cannot be reached directly are
458 converted to a small instruction sequence including an inverse-condition
459 branch to the physically next instruction, and a jump to the original
460 target is inserted between the two instructions. In PIC code the jump
461 will involve further instructions for address calculation.
463 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
464 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
465 relaxation, because they have no complementing counterparts. They could
466 be relaxed with the use of a longer sequence involving another branch,
467 however this has not been implemented and if their target turns out of
468 reach, they produce an error even if branch relaxation is enabled.
470 Also no MIPS16 branches are ever relaxed.
472 By default @samp{--no-relax-branch} is selected, causing any out-of-range
473 branches to produce an error.
475 @cindex @option{-mnan=} command line option, MIPS
476 @item -mnan=@var{encoding}
477 This option indicates whether the source code uses the IEEE 2008
478 NaN encoding (@option{-mnan=2008}) or the original MIPS encoding
479 (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan}
480 directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
482 @option{-mnan=legacy} is the default if no @option{-mnan} option or
483 @code{.nan} directive is used.
487 @c FIXME! (1) reflect these options (next item too) in option summaries;
488 @c (2) stop teasing, say _which_ instructions expanded _how_.
489 @code{@value{AS}} automatically macro expands certain division and
490 multiplication instructions to check for overflow and division by zero. This
491 option causes @code{@value{AS}} to generate code to take a trap exception
492 rather than a break exception when an error is detected. The trap instructions
493 are only supported at Instruction Set Architecture level 2 and higher.
497 Generate code to take a break exception rather than a trap exception when an
498 error is detected. This is the default.
502 Control generation of @code{.pdr} sections. Off by default on IRIX, on
507 When generating code using the Unix calling conventions (selected by
508 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
509 which can go into a shared library. The @samp{-mno-shared} option
510 tells gas to generate code which uses the calling convention, but can
511 not go into a shared library. The resulting code is slightly more
512 efficient. This option only affects the handling of the
513 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
517 @section High-level assembly macros
519 MIPS assemblers have traditionally provided a wider range of
520 instructions than the MIPS architecture itself. These extra
521 instructions are usually referred to as ``macro'' instructions
522 @footnote{The term ``macro'' is somewhat overloaded here, since
523 these macros have no relation to those defined by @code{.macro},
524 @pxref{Macro,, @code{.macro}}.}.
526 Some MIPS macro instructions extend an underlying architectural instruction
527 while others are entirely new. An example of the former type is @code{and},
528 which allows the third operand to be either a register or an arbitrary
529 immediate value. Examples of the latter type include @code{bgt}, which
530 branches to the third operand when the first operand is greater than
531 the second operand, and @code{ulh}, which implements an unaligned
534 One of the most common extensions provided by macros is to expand
535 memory offsets to the full address range (32 or 64 bits) and to allow
536 symbolic offsets such as @samp{my_data + 4} to be used in place of
537 integer constants. For example, the architectural instruction
538 @code{lbu} allows only a signed 16-bit offset, whereas the macro
539 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
540 The implementation of these symbolic offsets depends on several factors,
541 such as whether the assembler is generating SVR4-style PIC (selected by
542 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
543 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
544 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
545 of small data accesses}).
547 @kindex @code{.set macro}
548 @kindex @code{.set nomacro}
549 Sometimes it is undesirable to have one assembly instruction expand
550 to several machine instructions. The directive @code{.set nomacro}
551 tells the assembler to warn when this happens. @code{.set macro}
552 restores the default behavior.
554 @cindex @code{at} register, MIPS
555 @kindex @code{.set at=@var{reg}}
556 Some macro instructions need a temporary register to store intermediate
557 results. This register is usually @code{$1}, also known as @code{$at},
558 but it can be changed to any core register @var{reg} using
559 @code{.set at=@var{reg}}. Note that @code{$at} always refers
560 to @code{$1} regardless of which register is being used as the
563 @kindex @code{.set at}
564 @kindex @code{.set noat}
565 Implicit uses of the temporary register in macros could interfere with
566 explicit uses in the assembly code. The assembler therefore warns
567 whenever it sees an explicit use of the temporary register. The directive
568 @code{.set noat} silences this warning while @code{.set at} restores
569 the default behavior. It is safe to use @code{.set noat} while
570 @code{.set nomacro} is in effect since single-instruction macros
571 never need a temporary register.
573 Note that while the @sc{gnu} assembler provides these macros for compatibility,
574 it does not make any attempt to optimize them with the surrounding code.
576 @node MIPS Symbol Sizes
577 @section Directives to override the size of symbols
579 @kindex @code{.set sym32}
580 @kindex @code{.set nosym32}
581 The n64 ABI allows symbols to have any 64-bit value. Although this
582 provides a great deal of flexibility, it means that some macros have
583 much longer expansions than their 32-bit counterparts. For example,
584 the non-PIC expansion of @samp{dla $4,sym} is usually:
589 daddiu $4,$4,%higher(sym)
590 daddiu $1,$1,%lo(sym)
595 whereas the 32-bit expansion is simply:
599 daddiu $4,$4,%lo(sym)
602 n64 code is sometimes constructed in such a way that all symbolic
603 constants are known to have 32-bit values, and in such cases, it's
604 preferable to use the 32-bit expansion instead of the 64-bit
607 You can use the @code{.set sym32} directive to tell the assembler
608 that, from this point on, all expressions of the form
609 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
610 have 32-bit values. For example:
619 will cause the assembler to treat @samp{sym}, @code{sym+16} and
620 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
621 addresses is not affected.
623 The directive @code{.set nosym32} ends a @code{.set sym32} block and
624 reverts to the normal behavior. It is also possible to change the
625 symbol size using the command-line options @option{-msym32} and
628 These options and directives are always accepted, but at present,
629 they have no effect for anything other than n64.
631 @node MIPS Small Data
632 @section Controlling the use of small data accesses
634 @c This section deliberately glosses over the possibility of using -G
635 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
636 @cindex small data, MIPS
637 @cindex @code{gp} register, MIPS
638 It often takes several instructions to load the address of a symbol.
639 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
640 of @samp{dla $4,addr} is usually:
644 daddiu $4,$4,%lo(addr)
647 The sequence is much longer when @samp{addr} is a 64-bit symbol.
648 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
650 In order to cut down on this overhead, most embedded MIPS systems
651 set aside a 64-kilobyte ``small data'' area and guarantee that all
652 data of size @var{n} and smaller will be placed in that area.
653 The limit @var{n} is passed to both the assembler and the linker
654 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
655 Assembler options}. Note that the same value of @var{n} must be used
656 when linking and when assembling all input files to the link; any
657 inconsistency could cause a relocation overflow error.
659 The size of an object in the @code{.bss} section is set by the
660 @code{.comm} or @code{.lcomm} directive that defines it. The size of
661 an external object may be set with the @code{.extern} directive. For
662 example, @samp{.extern sym,4} declares that the object at @code{sym}
663 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
665 When no @option{-G} option is given, the default limit is 8 bytes.
666 The option @option{-G 0} prevents any data from being automatically
669 It is also possible to mark specific objects as small by putting them
670 in the special sections @code{.sdata} and @code{.sbss}, which are
671 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
672 The toolchain will treat such data as small regardless of the
675 On startup, systems that support a small data area are expected to
676 initialize register @code{$28}, also known as @code{$gp}, in such a
677 way that small data can be accessed using a 16-bit offset from that
678 register. For example, when @samp{addr} is small data,
679 the @samp{dla $4,addr} instruction above is equivalent to:
682 daddiu $4,$28,%gp_rel(addr)
685 Small data is not supported for SVR4-style PIC.
688 @section Directives to override the ISA level
690 @cindex MIPS ISA override
691 @kindex @code{.set mips@var{n}}
692 @sc{gnu} @code{@value{AS}} supports an additional directive to change
693 the MIPS Instruction Set Architecture level on the fly: @code{.set
694 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3,
695 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6.
696 The values other than 0 make the assembler accept instructions
697 for the corresponding ISA level, from that point on in the
698 assembly. @code{.set mips@var{n}} affects not only which instructions
699 are permitted, but also how certain macros are expanded. @code{.set
700 mips0} restores the ISA level to its original level: either the
701 level you selected with command line options, or the default for your
702 configuration. You can use this feature to permit specific MIPS III
703 instructions while assembling in 32 bit mode. Use this directive with
706 @cindex MIPS CPU override
707 @kindex @code{.set arch=@var{cpu}}
708 The @code{.set arch=@var{cpu}} directive provides even finer control.
709 It changes the effective CPU target and allows the assembler to use
710 instructions specific to a particular CPU. All CPUs supported by the
711 @samp{-march} command line option are also selectable by this directive.
712 The original value is restored by @code{.set arch=default}.
714 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
715 in which it will assemble instructions for the MIPS 16 processor. Use
716 @code{.set nomips16} to return to normal 32 bit mode.
718 Traditional MIPS assemblers do not support this directive.
720 The directive @code{.set micromips} puts the assembler into microMIPS mode,
721 in which it will assemble instructions for the microMIPS processor. Use
722 @code{.set nomicromips} to return to normal 32 bit mode.
724 Traditional MIPS assemblers do not support this directive.
726 @node MIPS assembly options
727 @section Directives to control code generation
729 @cindex MIPS directives to override command line options
730 @kindex @code{.module}
731 The @code{.module} directive allows command line options to be set directly
732 from assembly. The format of the directive matches the @code{.set}
733 directive but only those options which are relevant to a whole module are
734 supported. The effect of a @code{.module} directive is the same as the
735 corresponding command line option. Where @code{.set} directives support
736 returning to a default then the @code{.module} directives do not as they
739 These module-level directives must appear first in assembly.
741 Traditional MIPS assemblers do not support this directive.
743 @cindex MIPS 32-bit microMIPS instruction generation override
744 @kindex @code{.set insn32}
745 @kindex @code{.set noinsn32}
746 The directive @code{.set insn32} makes the assembler only use 32-bit
747 instruction encodings when generating code for the microMIPS processor.
748 This directive inhibits the use of any 16-bit instructions from that
749 point on in the assembly. The @code{.set noinsn32} directive allows
750 16-bit instructions to be accepted.
752 Traditional MIPS assemblers do not support this directive.
754 @node MIPS autoextend
755 @section Directives for extending MIPS 16 bit instructions
757 @kindex @code{.set autoextend}
758 @kindex @code{.set noautoextend}
759 By default, MIPS 16 instructions are automatically extended to 32 bits
760 when necessary. The directive @code{.set noautoextend} will turn this
761 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
762 must be explicitly extended with the @code{.e} modifier (e.g.,
763 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
764 to once again automatically extend instructions when necessary.
766 This directive is only meaningful when in MIPS 16 mode. Traditional
767 MIPS assemblers do not support this directive.
770 @section Directive to mark data as an instruction
773 The @code{.insn} directive tells @code{@value{AS}} that the following
774 data is actually instructions. This makes a difference in MIPS 16 and
775 microMIPS modes: when loading the address of a label which precedes
776 instructions, @code{@value{AS}} automatically adds 1 to the value, so
777 that jumping to the loaded address will do the right thing.
779 @kindex @code{.global}
780 The @code{.global} and @code{.globl} directives supported by
781 @code{@value{AS}} will by default mark the symbol as pointing to a
782 region of data not code. This means that, for example, any
783 instructions following such a symbol will not be disassembled by
784 @code{objdump} as it will regard them as data. To change this
785 behavior an optional section name can be placed after the symbol name
786 in the @code{.global} directive. If this section exists and is known
787 to be a code section, then the symbol will be marked as pointing at
788 code not data. Ie the syntax for the directive is:
790 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
792 Here is a short example:
795 .global foo .text, bar, baz .data
806 @section Directives to control the FP ABI
808 * MIPS FP ABI History:: History of FP ABIs
809 * MIPS FP ABI Variants:: Supported FP ABIs
810 * MIPS FP ABI Selection:: Automatic selection of FP ABI
811 * MIPS FP ABI Compatibility:: Linking different FP ABI variants
814 @node MIPS FP ABI History
815 @subsection History of FP ABIs
816 @cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS
817 @cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS
818 The MIPS ABIs support a variety of different floating-point extensions
819 where calling-convention and register sizes vary for floating-point data.
820 The extensions exist to support a wide variety of optional architecture
821 features. The resulting ABI variants are generally incompatible with each
822 other and must be tracked carefully.
824 Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}}
825 directive is used to indicate which ABI is in use by a specific module.
826 It was then left to the user to ensure that command line options and the
827 selected ABI were compatible with some potential for inconsistencies.
829 @node MIPS FP ABI Variants
830 @subsection Supported FP ABIs
831 The supported floating-point ABI variants are:
834 @item 0 - No floating-point
835 This variant is used to indicate that floating-point is not used within
836 the module at all and therefore has no impact on the ABI. This is the
839 @item 1 - Double-precision
840 This variant indicates that double-precision support is used. For 64-bit
841 ABIs this means that 64-bit wide floating-point registers are required.
842 For 32-bit ABIs this means that 32-bit wide floating-point registers are
843 required and double-precision operations use pairs of registers.
845 @item 2 - Single-precision
846 This variant indicates that single-precision support is used. Double
847 precision operations will be supported via soft-float routines.
850 This variant indicates that although floating-point support is used all
851 operations are emulated in software. This means the ABI is modified to
852 pass all floating-point data in general-purpose registers.
855 This variant existed as an initial attempt at supporting 64-bit wide
856 floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been
857 superseded by 5, 6 and 7.
859 @item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
860 This variant is used by 32-bit ABIs to indicate that the floating-point
861 code in the module has been designed to operate correctly with either
862 32-bit wide or 64-bit wide floating-point registers. Double-precision
863 support is used. Only O32 currently supports this variant and requires
864 a minimum architecture of MIPS II.
866 @item 6 - Double-precision 32-bit FPU, 64-bit FPU
867 This variant is used by 32-bit ABIs to indicate that the floating-point
868 code in the module requires 64-bit wide floating-point registers.
869 Double-precision support is used. Only O32 currently supports this
870 variant and requires a minimum architecture of MIPS32r2.
872 @item 7 - Double-precision compat 32-bit FPU, 64-bit FPU
873 This variant is used by 32-bit ABIs to indicate that the floating-point
874 code in the module requires 64-bit wide floating-point registers.
875 Double-precision support is used. This differs from the previous ABI
876 as it restricts use of odd-numbered single-precision registers. Only
877 O32 currently supports this variant and requires a minimum architecture
881 @node MIPS FP ABI Selection
882 @subsection Automatic selection of FP ABI
883 @cindex @code{.module fp=@var{nn}} directive, MIPS
884 In order to simplify and add safety to the process of selecting the
885 correct floating-point ABI, the assembler will automatically infer the
886 correct @code{.gnu_attribute 4, @var{n}} directive based on command line
887 options and @code{.module} overrides. Where an explicit
888 @code{.gnu_attribute 4, @var{n}} directive has been seen then a warning
889 will be raised if it does not match an inferred setting.
891 The floating-point ABI is inferred as follows. If @samp{-msoft-float}
892 has been used the module will be marked as soft-float. If
893 @samp{-msingle-float} has been used then the module will be marked as
894 single-precision. The remaining ABIs are then selected based
895 on the FP register width. Double-precision is selected if the width
896 of GP and FP registers match and the special double-precision variants
897 for 32-bit ABIs are then selected depending on @samp{-mfpxx},
898 @samp{-mfp64} and @samp{-mno-odd-spreg}.
900 @node MIPS FP ABI Compatibility
901 @subsection Linking different FP ABI variants
902 Modules using the default FP ABI (no floating-point) can be linked with
903 any other (singular) FP ABI variant.
905 Special compatibility support exists for O32 with the four
906 double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically
907 designed to be compatible with the standard double-precision ABI and the
908 @samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be
909 built as @samp{-mfpxx} to ensure the maximum compatibility with other
910 modules produced for more specific needs. The only FP ABIs which cannot
911 be linked together are the standard double-precision ABI and the full
912 @samp{-mfp64} ABI with @samp{-modd-spreg}.
914 @node MIPS NaN Encodings
915 @section Directives to record which NaN encoding is being used
917 @cindex MIPS IEEE 754 NaN data encoding selection
918 @cindex @code{.nan} directive, MIPS
919 The IEEE 754 floating-point standard defines two types of not-a-number
920 (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version
921 of the standard did not specify how these two types should be
922 distinguished. Most implementations followed the i387 model, in which
923 the first bit of the significand is set for quiet NaNs and clear for
924 signalling NaNs. However, the original MIPS implementation assigned the
925 opposite meaning to the bit, so that it was set for signalling NaNs and
926 clear for quiet NaNs.
928 The 2008 revision of the standard formally suggested the i387 choice
929 and as from Sep 2012 the current release of the MIPS architecture
930 therefore optionally supports that form. Code that uses one NaN encoding
931 would usually be incompatible with code that uses the other NaN encoding,
932 so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which
933 encoding is being used.
935 Assembly files can use the @code{.nan} directive to select between the
936 two encodings. @samp{.nan 2008} says that the assembly file uses the
937 IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses
938 the original MIPS encoding. If several @code{.nan} directives are given,
939 the final setting is the one that is used.
941 The command-line options @option{-mnan=legacy} and @option{-mnan=2008}
942 can be used instead of @samp{.nan legacy} and @samp{.nan 2008}
943 respectively. However, any @code{.nan} directive overrides the
944 command-line setting.
946 @samp{.nan legacy} is the default if no @code{.nan} directive or
947 @option{-mnan} option is given.
949 Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and
950 therefore these directives do not affect code generation. They simply
951 control the setting of the @code{EF_MIPS_NAN2008} flag.
953 Traditional MIPS assemblers do not support these directives.
955 @node MIPS Option Stack
956 @section Directives to save and restore options
958 @cindex MIPS option stack
959 @kindex @code{.set push}
960 @kindex @code{.set pop}
961 The directives @code{.set push} and @code{.set pop} may be used to save
962 and restore the current settings for all the options which are
963 controlled by @code{.set}. The @code{.set push} directive saves the
964 current settings on a stack. The @code{.set pop} directive pops the
965 stack and restores the settings.
967 These directives can be useful inside an macro which must change an
968 option such as the ISA level or instruction reordering but does not want
969 to change the state of the code which invoked the macro.
971 Traditional MIPS assemblers do not support these directives.
973 @node MIPS ASE Instruction Generation Overrides
974 @section Directives to control generation of MIPS ASE instructions
976 @cindex MIPS MIPS-3D instruction generation override
977 @kindex @code{.set mips3d}
978 @kindex @code{.set nomips3d}
979 The directive @code{.set mips3d} makes the assembler accept instructions
980 from the MIPS-3D Application Specific Extension from that point on
981 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
982 instructions from being accepted.
984 @cindex SmartMIPS instruction generation override
985 @kindex @code{.set smartmips}
986 @kindex @code{.set nosmartmips}
987 The directive @code{.set smartmips} makes the assembler accept
988 instructions from the SmartMIPS Application Specific Extension to the
989 MIPS32 ISA from that point on in the assembly. The
990 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
993 @cindex MIPS MDMX instruction generation override
994 @kindex @code{.set mdmx}
995 @kindex @code{.set nomdmx}
996 The directive @code{.set mdmx} makes the assembler accept instructions
997 from the MDMX Application Specific Extension from that point on
998 in the assembly. The @code{.set nomdmx} directive prevents MDMX
999 instructions from being accepted.
1001 @cindex MIPS DSP Release 1 instruction generation override
1002 @kindex @code{.set dsp}
1003 @kindex @code{.set nodsp}
1004 The directive @code{.set dsp} makes the assembler accept instructions
1005 from the DSP Release 1 Application Specific Extension from that point
1006 on in the assembly. The @code{.set nodsp} directive prevents DSP
1007 Release 1 instructions from being accepted.
1009 @cindex MIPS DSP Release 2 instruction generation override
1010 @kindex @code{.set dspr2}
1011 @kindex @code{.set nodspr2}
1012 The directive @code{.set dspr2} makes the assembler accept instructions
1013 from the DSP Release 2 Application Specific Extension from that point
1014 on in the assembly. This directive implies @code{.set dsp}. The
1015 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
1018 @cindex MIPS DSP Release 3 instruction generation override
1019 @kindex @code{.set dspr3}
1020 @kindex @code{.set nodspr3}
1021 The directive @code{.set dspr3} makes the assembler accept instructions
1022 from the DSP Release 3 Application Specific Extension from that point
1023 on in the assembly. This directive implies @code{.set dsp} and
1024 @code{.set dspr2}. The @code{.set nodspr3} directive prevents DSP
1025 Release 3 instructions from being accepted.
1027 @cindex MIPS MT instruction generation override
1028 @kindex @code{.set mt}
1029 @kindex @code{.set nomt}
1030 The directive @code{.set mt} makes the assembler accept instructions
1031 from the MT Application Specific Extension from that point on
1032 in the assembly. The @code{.set nomt} directive prevents MT
1033 instructions from being accepted.
1035 @cindex MIPS MCU instruction generation override
1036 @kindex @code{.set mcu}
1037 @kindex @code{.set nomcu}
1038 The directive @code{.set mcu} makes the assembler accept instructions
1039 from the MCU Application Specific Extension from that point on
1040 in the assembly. The @code{.set nomcu} directive prevents MCU
1041 instructions from being accepted.
1043 @cindex MIPS SIMD Architecture instruction generation override
1044 @kindex @code{.set msa}
1045 @kindex @code{.set nomsa}
1046 The directive @code{.set msa} makes the assembler accept instructions
1047 from the MIPS SIMD Architecture Extension from that point on
1048 in the assembly. The @code{.set nomsa} directive prevents MSA
1049 instructions from being accepted.
1051 @cindex Virtualization instruction generation override
1052 @kindex @code{.set virt}
1053 @kindex @code{.set novirt}
1054 The directive @code{.set virt} makes the assembler accept instructions
1055 from the Virtualization Application Specific Extension from that point
1056 on in the assembly. The @code{.set novirt} directive prevents Virtualization
1057 instructions from being accepted.
1059 @cindex MIPS eXtended Physical Address (XPA) instruction generation override
1060 @kindex @code{.set xpa}
1061 @kindex @code{.set noxpa}
1062 The directive @code{.set xpa} makes the assembler accept instructions
1063 from the XPA Extension from that point on in the assembly. The
1064 @code{.set noxpa} directive prevents XPA instructions from being accepted.
1066 Traditional MIPS assemblers do not support these directives.
1068 @node MIPS Floating-Point
1069 @section Directives to override floating-point options
1071 @cindex Disable floating-point instructions
1072 @kindex @code{.set softfloat}
1073 @kindex @code{.set hardfloat}
1074 The directives @code{.set softfloat} and @code{.set hardfloat} provide
1075 finer control of disabling and enabling float-point instructions.
1076 These directives always override the default (that hard-float
1077 instructions are accepted) or the command-line options
1078 (@samp{-msoft-float} and @samp{-mhard-float}).
1080 @cindex Disable single-precision floating-point operations
1081 @kindex @code{.set singlefloat}
1082 @kindex @code{.set doublefloat}
1083 The directives @code{.set singlefloat} and @code{.set doublefloat}
1084 provide finer control of disabling and enabling double-precision
1085 float-point operations. These directives always override the default
1086 (that double-precision operations are accepted) or the command-line
1087 options (@samp{-msingle-float} and @samp{-mdouble-float}).
1089 Traditional MIPS assemblers do not support these directives.
1092 @section Syntactical considerations for the MIPS assembler
1094 * MIPS-Chars:: Special Characters
1098 @subsection Special Characters
1100 @cindex line comment character, MIPS
1101 @cindex MIPS line comment character
1102 The presence of a @samp{#} on a line indicates the start of a comment
1103 that extends to the end of the current line.
1105 If a @samp{#} appears as the first character of a line, the whole line
1106 is treated as a comment, but in this case the line can also be a
1107 logical line number directive (@pxref{Comments}) or a
1108 preprocessor control command (@pxref{Preprocessing}).
1110 @cindex line separator, MIPS
1111 @cindex statement separator, MIPS
1112 @cindex MIPS line separator
1113 The @samp{;} character can be used to separate statements on the same
projects / deliverable / binutils-gdb.git / blob